fimc-is-param.c 24 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923
  1. /*
  2. * Samsung EXYNOS4x12 FIMC-IS (Imaging Subsystem) driver
  3. *
  4. * Copyright (C) 2013 Samsung Electronics Co., Ltd.
  5. *
  6. * Authors: Younghwan Joo <yhwan.joo@samsung.com>
  7. * Sylwester Nawrocki <s.nawrocki@samsung.com>
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License version 2 as
  11. * published by the Free Software Foundation.
  12. */
  13. #define pr_fmt(fmt) "%s:%d " fmt, __func__, __LINE__
  14. #include <linux/bitops.h>
  15. #include <linux/bug.h>
  16. #include <linux/device.h>
  17. #include <linux/errno.h>
  18. #include <linux/kernel.h>
  19. #include <linux/module.h>
  20. #include <linux/platform_device.h>
  21. #include <linux/slab.h>
  22. #include <linux/types.h>
  23. #include <linux/videodev2.h>
  24. #include <media/v4l2-device.h>
  25. #include <media/v4l2-ioctl.h>
  26. #include "fimc-is.h"
  27. #include "fimc-is-command.h"
  28. #include "fimc-is-errno.h"
  29. #include "fimc-is-param.h"
  30. #include "fimc-is-regs.h"
  31. #include "fimc-is-sensor.h"
  32. static void __hw_param_copy(void *dst, void *src)
  33. {
  34. memcpy(dst, src, FIMC_IS_PARAM_MAX_SIZE);
  35. }
  36. void __fimc_is_hw_update_param_global_shotmode(struct fimc_is *is)
  37. {
  38. struct param_global_shotmode *dst, *src;
  39. dst = &is->is_p_region->parameter.global.shotmode;
  40. src = &is->cfg_param[is->scenario_id].global.shotmode;
  41. __hw_param_copy(dst, src);
  42. }
  43. void __fimc_is_hw_update_param_sensor_framerate(struct fimc_is *is)
  44. {
  45. struct param_sensor_framerate *dst, *src;
  46. dst = &is->is_p_region->parameter.sensor.frame_rate;
  47. src = &is->cfg_param[is->scenario_id].sensor.frame_rate;
  48. __hw_param_copy(dst, src);
  49. }
  50. int __fimc_is_hw_update_param(struct fimc_is *is, u32 offset)
  51. {
  52. struct is_param_region *par = &is->is_p_region->parameter;
  53. struct is_config_param *cfg = &is->cfg_param[is->scenario_id];
  54. switch (offset) {
  55. case PARAM_ISP_CONTROL:
  56. __hw_param_copy(&par->isp.control, &cfg->isp.control);
  57. break;
  58. case PARAM_ISP_OTF_INPUT:
  59. __hw_param_copy(&par->isp.otf_input, &cfg->isp.otf_input);
  60. break;
  61. case PARAM_ISP_DMA1_INPUT:
  62. __hw_param_copy(&par->isp.dma1_input, &cfg->isp.dma1_input);
  63. break;
  64. case PARAM_ISP_DMA2_INPUT:
  65. __hw_param_copy(&par->isp.dma2_input, &cfg->isp.dma2_input);
  66. break;
  67. case PARAM_ISP_AA:
  68. __hw_param_copy(&par->isp.aa, &cfg->isp.aa);
  69. break;
  70. case PARAM_ISP_FLASH:
  71. __hw_param_copy(&par->isp.flash, &cfg->isp.flash);
  72. break;
  73. case PARAM_ISP_AWB:
  74. __hw_param_copy(&par->isp.awb, &cfg->isp.awb);
  75. break;
  76. case PARAM_ISP_IMAGE_EFFECT:
  77. __hw_param_copy(&par->isp.effect, &cfg->isp.effect);
  78. break;
  79. case PARAM_ISP_ISO:
  80. __hw_param_copy(&par->isp.iso, &cfg->isp.iso);
  81. break;
  82. case PARAM_ISP_ADJUST:
  83. __hw_param_copy(&par->isp.adjust, &cfg->isp.adjust);
  84. break;
  85. case PARAM_ISP_METERING:
  86. __hw_param_copy(&par->isp.metering, &cfg->isp.metering);
  87. break;
  88. case PARAM_ISP_AFC:
  89. __hw_param_copy(&par->isp.afc, &cfg->isp.afc);
  90. break;
  91. case PARAM_ISP_OTF_OUTPUT:
  92. __hw_param_copy(&par->isp.otf_output, &cfg->isp.otf_output);
  93. break;
  94. case PARAM_ISP_DMA1_OUTPUT:
  95. __hw_param_copy(&par->isp.dma1_output, &cfg->isp.dma1_output);
  96. break;
  97. case PARAM_ISP_DMA2_OUTPUT:
  98. __hw_param_copy(&par->isp.dma2_output, &cfg->isp.dma2_output);
  99. break;
  100. case PARAM_DRC_CONTROL:
  101. __hw_param_copy(&par->drc.control, &cfg->drc.control);
  102. break;
  103. case PARAM_DRC_OTF_INPUT:
  104. __hw_param_copy(&par->drc.otf_input, &cfg->drc.otf_input);
  105. break;
  106. case PARAM_DRC_DMA_INPUT:
  107. __hw_param_copy(&par->drc.dma_input, &cfg->drc.dma_input);
  108. break;
  109. case PARAM_DRC_OTF_OUTPUT:
  110. __hw_param_copy(&par->drc.otf_output, &cfg->drc.otf_output);
  111. break;
  112. case PARAM_FD_CONTROL:
  113. __hw_param_copy(&par->fd.control, &cfg->fd.control);
  114. break;
  115. case PARAM_FD_OTF_INPUT:
  116. __hw_param_copy(&par->fd.otf_input, &cfg->fd.otf_input);
  117. break;
  118. case PARAM_FD_DMA_INPUT:
  119. __hw_param_copy(&par->fd.dma_input, &cfg->fd.dma_input);
  120. break;
  121. case PARAM_FD_CONFIG:
  122. __hw_param_copy(&par->fd.config, &cfg->fd.config);
  123. break;
  124. default:
  125. return -EINVAL;
  126. }
  127. return 0;
  128. }
  129. unsigned int __get_pending_param_count(struct fimc_is *is)
  130. {
  131. struct is_config_param *config = &is->cfg_param[is->scenario_id];
  132. unsigned long flags;
  133. unsigned int count;
  134. spin_lock_irqsave(&is->slock, flags);
  135. count = hweight32(config->p_region_index1);
  136. count += hweight32(config->p_region_index2);
  137. spin_unlock_irqrestore(&is->slock, flags);
  138. return count;
  139. }
  140. int __is_hw_update_params(struct fimc_is *is)
  141. {
  142. unsigned long *p_index1, *p_index2;
  143. int i, id, ret = 0;
  144. id = is->scenario_id;
  145. p_index1 = &is->cfg_param[id].p_region_index1;
  146. p_index2 = &is->cfg_param[id].p_region_index2;
  147. if (test_bit(PARAM_GLOBAL_SHOTMODE, p_index1))
  148. __fimc_is_hw_update_param_global_shotmode(is);
  149. if (test_bit(PARAM_SENSOR_FRAME_RATE, p_index1))
  150. __fimc_is_hw_update_param_sensor_framerate(is);
  151. for (i = PARAM_ISP_CONTROL; i < PARAM_DRC_CONTROL; i++) {
  152. if (test_bit(i, p_index1))
  153. ret = __fimc_is_hw_update_param(is, i);
  154. }
  155. for (i = PARAM_DRC_CONTROL; i < PARAM_SCALERC_CONTROL; i++) {
  156. if (test_bit(i, p_index1))
  157. ret = __fimc_is_hw_update_param(is, i);
  158. }
  159. for (i = PARAM_FD_CONTROL; i <= PARAM_FD_CONFIG; i++) {
  160. if (test_bit((i - 32), p_index2))
  161. ret = __fimc_is_hw_update_param(is, i);
  162. }
  163. return ret;
  164. }
  165. void __is_get_frame_size(struct fimc_is *is, struct v4l2_mbus_framefmt *mf)
  166. {
  167. struct isp_param *isp;
  168. isp = &is->cfg_param[is->scenario_id].isp;
  169. mf->width = isp->otf_input.width;
  170. mf->height = isp->otf_input.height;
  171. }
  172. void __is_set_frame_size(struct fimc_is *is, struct v4l2_mbus_framefmt *mf)
  173. {
  174. struct isp_param *isp;
  175. struct drc_param *drc;
  176. struct fd_param *fd;
  177. unsigned int mode;
  178. mode = is->scenario_id;
  179. isp = &is->cfg_param[mode].isp;
  180. drc = &is->cfg_param[mode].drc;
  181. fd = &is->cfg_param[mode].fd;
  182. /* Update isp size info (OTF only) */
  183. isp->otf_input.width = mf->width;
  184. isp->otf_input.height = mf->height;
  185. isp->otf_output.width = mf->width;
  186. isp->otf_output.height = mf->height;
  187. /* Update drc size info (OTF only) */
  188. drc->otf_input.width = mf->width;
  189. drc->otf_input.height = mf->height;
  190. drc->otf_output.width = mf->width;
  191. drc->otf_output.height = mf->height;
  192. /* Update fd size info (OTF only) */
  193. fd->otf_input.width = mf->width;
  194. fd->otf_input.height = mf->height;
  195. if (test_bit(PARAM_ISP_OTF_INPUT,
  196. &is->cfg_param[mode].p_region_index1))
  197. return;
  198. /* Update field */
  199. fimc_is_set_param_bit(is, PARAM_ISP_OTF_INPUT);
  200. fimc_is_set_param_bit(is, PARAM_ISP_OTF_OUTPUT);
  201. fimc_is_set_param_bit(is, PARAM_DRC_OTF_INPUT);
  202. fimc_is_set_param_bit(is, PARAM_DRC_OTF_OUTPUT);
  203. fimc_is_set_param_bit(is, PARAM_FD_OTF_INPUT);
  204. }
  205. int fimc_is_hw_get_sensor_max_framerate(struct fimc_is *is)
  206. {
  207. switch (is->sensor->drvdata->id) {
  208. case FIMC_IS_SENSOR_ID_S5K6A3:
  209. return 30;
  210. default:
  211. return 15;
  212. }
  213. }
  214. void __is_set_sensor(struct fimc_is *is, int fps)
  215. {
  216. struct sensor_param *sensor;
  217. struct isp_param *isp;
  218. unsigned long *p_index, mode;
  219. mode = is->scenario_id;
  220. p_index = &is->cfg_param[mode].p_region_index1;
  221. sensor = &is->cfg_param[mode].sensor;
  222. isp = &is->cfg_param[mode].isp;
  223. if (fps == 0) {
  224. sensor->frame_rate.frame_rate =
  225. fimc_is_hw_get_sensor_max_framerate(is);
  226. isp->otf_input.frametime_min = 0;
  227. isp->otf_input.frametime_max = 66666;
  228. } else {
  229. sensor->frame_rate.frame_rate = fps;
  230. isp->otf_input.frametime_min = 0;
  231. isp->otf_input.frametime_max = (u32)1000000 / fps;
  232. }
  233. if (!test_bit(PARAM_SENSOR_FRAME_RATE, p_index))
  234. fimc_is_set_param_bit(is, PARAM_SENSOR_FRAME_RATE);
  235. if (!test_bit(PARAM_ISP_OTF_INPUT, p_index))
  236. fimc_is_set_param_bit(is, PARAM_ISP_OTF_INPUT);
  237. }
  238. void __is_set_init_isp_aa(struct fimc_is *is)
  239. {
  240. struct isp_param *isp;
  241. isp = &is->cfg_param[is->scenario_id].isp;
  242. isp->aa.cmd = ISP_AA_COMMAND_START;
  243. isp->aa.target = ISP_AA_TARGET_AF | ISP_AA_TARGET_AE |
  244. ISP_AA_TARGET_AWB;
  245. isp->aa.mode = 0;
  246. isp->aa.scene = 0;
  247. isp->aa.sleep = 0;
  248. isp->aa.face = 0;
  249. isp->aa.touch_x = 0;
  250. isp->aa.touch_y = 0;
  251. isp->aa.manual_af_setting = 0;
  252. isp->aa.err = ISP_AF_ERROR_NONE;
  253. fimc_is_set_param_bit(is, PARAM_ISP_AA);
  254. }
  255. void __is_set_isp_flash(struct fimc_is *is, u32 cmd, u32 redeye)
  256. {
  257. unsigned int mode = is->scenario_id;
  258. struct is_config_param *cfg = &is->cfg_param[mode];
  259. struct isp_param *isp = &cfg->isp;
  260. isp->flash.cmd = cmd;
  261. isp->flash.redeye = redeye;
  262. isp->flash.err = ISP_FLASH_ERROR_NONE;
  263. if (!test_bit(PARAM_ISP_FLASH, &cfg->p_region_index1))
  264. fimc_is_set_param_bit(is, PARAM_ISP_FLASH);
  265. }
  266. void __is_set_isp_awb(struct fimc_is *is, u32 cmd, u32 val)
  267. {
  268. unsigned int mode = is->scenario_id;
  269. struct isp_param *isp;
  270. unsigned long *p_index;
  271. p_index = &is->cfg_param[mode].p_region_index1;
  272. isp = &is->cfg_param[mode].isp;
  273. isp->awb.cmd = cmd;
  274. isp->awb.illumination = val;
  275. isp->awb.err = ISP_AWB_ERROR_NONE;
  276. if (!test_bit(PARAM_ISP_AWB, p_index))
  277. fimc_is_set_param_bit(is, PARAM_ISP_AWB);
  278. }
  279. void __is_set_isp_effect(struct fimc_is *is, u32 cmd)
  280. {
  281. unsigned int mode = is->scenario_id;
  282. struct isp_param *isp;
  283. unsigned long *p_index;
  284. p_index = &is->cfg_param[mode].p_region_index1;
  285. isp = &is->cfg_param[mode].isp;
  286. isp->effect.cmd = cmd;
  287. isp->effect.err = ISP_IMAGE_EFFECT_ERROR_NONE;
  288. if (!test_bit(PARAM_ISP_IMAGE_EFFECT, p_index))
  289. fimc_is_set_param_bit(is, PARAM_ISP_IMAGE_EFFECT);
  290. }
  291. void __is_set_isp_iso(struct fimc_is *is, u32 cmd, u32 val)
  292. {
  293. unsigned int mode = is->scenario_id;
  294. struct isp_param *isp;
  295. unsigned long *p_index;
  296. p_index = &is->cfg_param[mode].p_region_index1;
  297. isp = &is->cfg_param[mode].isp;
  298. isp->iso.cmd = cmd;
  299. isp->iso.value = val;
  300. isp->iso.err = ISP_ISO_ERROR_NONE;
  301. if (!test_bit(PARAM_ISP_ISO, p_index))
  302. fimc_is_set_param_bit(is, PARAM_ISP_ISO);
  303. }
  304. void __is_set_isp_adjust(struct fimc_is *is, u32 cmd, u32 val)
  305. {
  306. unsigned int mode = is->scenario_id;
  307. unsigned long *p_index;
  308. struct isp_param *isp;
  309. p_index = &is->cfg_param[mode].p_region_index1;
  310. isp = &is->cfg_param[mode].isp;
  311. switch (cmd) {
  312. case ISP_ADJUST_COMMAND_MANUAL_CONTRAST:
  313. isp->adjust.contrast = val;
  314. break;
  315. case ISP_ADJUST_COMMAND_MANUAL_SATURATION:
  316. isp->adjust.saturation = val;
  317. break;
  318. case ISP_ADJUST_COMMAND_MANUAL_SHARPNESS:
  319. isp->adjust.sharpness = val;
  320. break;
  321. case ISP_ADJUST_COMMAND_MANUAL_EXPOSURE:
  322. isp->adjust.exposure = val;
  323. break;
  324. case ISP_ADJUST_COMMAND_MANUAL_BRIGHTNESS:
  325. isp->adjust.brightness = val;
  326. break;
  327. case ISP_ADJUST_COMMAND_MANUAL_HUE:
  328. isp->adjust.hue = val;
  329. break;
  330. case ISP_ADJUST_COMMAND_AUTO:
  331. isp->adjust.contrast = 0;
  332. isp->adjust.saturation = 0;
  333. isp->adjust.sharpness = 0;
  334. isp->adjust.exposure = 0;
  335. isp->adjust.brightness = 0;
  336. isp->adjust.hue = 0;
  337. break;
  338. }
  339. if (!test_bit(PARAM_ISP_ADJUST, p_index)) {
  340. isp->adjust.cmd = cmd;
  341. isp->adjust.err = ISP_ADJUST_ERROR_NONE;
  342. fimc_is_set_param_bit(is, PARAM_ISP_ADJUST);
  343. } else {
  344. isp->adjust.cmd |= cmd;
  345. }
  346. }
  347. void __is_set_isp_metering(struct fimc_is *is, u32 id, u32 val)
  348. {
  349. struct isp_param *isp;
  350. unsigned long *p_index, mode;
  351. mode = is->scenario_id;
  352. p_index = &is->cfg_param[mode].p_region_index1;
  353. isp = &is->cfg_param[mode].isp;
  354. switch (id) {
  355. case IS_METERING_CONFIG_CMD:
  356. isp->metering.cmd = val;
  357. break;
  358. case IS_METERING_CONFIG_WIN_POS_X:
  359. isp->metering.win_pos_x = val;
  360. break;
  361. case IS_METERING_CONFIG_WIN_POS_Y:
  362. isp->metering.win_pos_y = val;
  363. break;
  364. case IS_METERING_CONFIG_WIN_WIDTH:
  365. isp->metering.win_width = val;
  366. break;
  367. case IS_METERING_CONFIG_WIN_HEIGHT:
  368. isp->metering.win_height = val;
  369. break;
  370. default:
  371. return;
  372. }
  373. if (!test_bit(PARAM_ISP_METERING, p_index)) {
  374. isp->metering.err = ISP_METERING_ERROR_NONE;
  375. fimc_is_set_param_bit(is, PARAM_ISP_METERING);
  376. }
  377. }
  378. void __is_set_isp_afc(struct fimc_is *is, u32 cmd, u32 val)
  379. {
  380. struct isp_param *isp;
  381. unsigned long *p_index, mode;
  382. mode = is->scenario_id;
  383. p_index = &is->cfg_param[mode].p_region_index1;
  384. isp = &is->cfg_param[mode].isp;
  385. isp->afc.cmd = cmd;
  386. isp->afc.manual = val;
  387. isp->afc.err = ISP_AFC_ERROR_NONE;
  388. if (!test_bit(PARAM_ISP_AFC, p_index))
  389. fimc_is_set_param_bit(is, PARAM_ISP_AFC);
  390. }
  391. void __is_set_drc_control(struct fimc_is *is, u32 val)
  392. {
  393. struct drc_param *drc;
  394. unsigned long *p_index, mode;
  395. mode = is->scenario_id;
  396. p_index = &is->cfg_param[mode].p_region_index1;
  397. drc = &is->cfg_param[mode].drc;
  398. drc->control.bypass = val;
  399. if (!test_bit(PARAM_DRC_CONTROL, p_index))
  400. fimc_is_set_param_bit(is, PARAM_DRC_CONTROL);
  401. }
  402. void __is_set_fd_control(struct fimc_is *is, u32 val)
  403. {
  404. struct fd_param *fd;
  405. unsigned long *p_index, mode;
  406. mode = is->scenario_id;
  407. p_index = &is->cfg_param[mode].p_region_index2;
  408. fd = &is->cfg_param[mode].fd;
  409. fd->control.cmd = val;
  410. if (!test_bit((PARAM_FD_CONFIG - 32), p_index))
  411. fimc_is_set_param_bit(is, PARAM_FD_CONTROL);
  412. }
  413. void __is_set_fd_config_maxface(struct fimc_is *is, u32 val)
  414. {
  415. struct fd_param *fd;
  416. unsigned long *p_index, mode;
  417. mode = is->scenario_id;
  418. p_index = &is->cfg_param[mode].p_region_index2;
  419. fd = &is->cfg_param[mode].fd;
  420. fd->config.max_number = val;
  421. if (!test_bit((PARAM_FD_CONFIG - 32), p_index)) {
  422. fd->config.cmd = FD_CONFIG_COMMAND_MAXIMUM_NUMBER;
  423. fd->config.err = ERROR_FD_NONE;
  424. fimc_is_set_param_bit(is, PARAM_FD_CONFIG);
  425. } else {
  426. fd->config.cmd |= FD_CONFIG_COMMAND_MAXIMUM_NUMBER;
  427. }
  428. }
  429. void __is_set_fd_config_rollangle(struct fimc_is *is, u32 val)
  430. {
  431. struct fd_param *fd;
  432. unsigned long *p_index, mode;
  433. mode = is->scenario_id;
  434. p_index = &is->cfg_param[mode].p_region_index2;
  435. fd = &is->cfg_param[mode].fd;
  436. fd->config.roll_angle = val;
  437. if (!test_bit((PARAM_FD_CONFIG - 32), p_index)) {
  438. fd->config.cmd = FD_CONFIG_COMMAND_ROLL_ANGLE;
  439. fd->config.err = ERROR_FD_NONE;
  440. fimc_is_set_param_bit(is, PARAM_FD_CONFIG);
  441. } else {
  442. fd->config.cmd |= FD_CONFIG_COMMAND_ROLL_ANGLE;
  443. }
  444. }
  445. void __is_set_fd_config_yawangle(struct fimc_is *is, u32 val)
  446. {
  447. struct fd_param *fd;
  448. unsigned long *p_index, mode;
  449. mode = is->scenario_id;
  450. p_index = &is->cfg_param[mode].p_region_index2;
  451. fd = &is->cfg_param[mode].fd;
  452. fd->config.yaw_angle = val;
  453. if (!test_bit((PARAM_FD_CONFIG - 32), p_index)) {
  454. fd->config.cmd = FD_CONFIG_COMMAND_YAW_ANGLE;
  455. fd->config.err = ERROR_FD_NONE;
  456. fimc_is_set_param_bit(is, PARAM_FD_CONFIG);
  457. } else {
  458. fd->config.cmd |= FD_CONFIG_COMMAND_YAW_ANGLE;
  459. }
  460. }
  461. void __is_set_fd_config_smilemode(struct fimc_is *is, u32 val)
  462. {
  463. struct fd_param *fd;
  464. unsigned long *p_index, mode;
  465. mode = is->scenario_id;
  466. p_index = &is->cfg_param[mode].p_region_index2;
  467. fd = &is->cfg_param[mode].fd;
  468. fd->config.smile_mode = val;
  469. if (!test_bit((PARAM_FD_CONFIG - 32), p_index)) {
  470. fd->config.cmd = FD_CONFIG_COMMAND_SMILE_MODE;
  471. fd->config.err = ERROR_FD_NONE;
  472. fimc_is_set_param_bit(is, PARAM_FD_CONFIG);
  473. } else {
  474. fd->config.cmd |= FD_CONFIG_COMMAND_SMILE_MODE;
  475. }
  476. }
  477. void __is_set_fd_config_blinkmode(struct fimc_is *is, u32 val)
  478. {
  479. struct fd_param *fd;
  480. unsigned long *p_index, mode;
  481. mode = is->scenario_id;
  482. p_index = &is->cfg_param[mode].p_region_index2;
  483. fd = &is->cfg_param[mode].fd;
  484. fd->config.blink_mode = val;
  485. if (!test_bit((PARAM_FD_CONFIG - 32), p_index)) {
  486. fd->config.cmd = FD_CONFIG_COMMAND_BLINK_MODE;
  487. fd->config.err = ERROR_FD_NONE;
  488. fimc_is_set_param_bit(is, PARAM_FD_CONFIG);
  489. } else {
  490. fd->config.cmd |= FD_CONFIG_COMMAND_BLINK_MODE;
  491. }
  492. }
  493. void __is_set_fd_config_eyedetect(struct fimc_is *is, u32 val)
  494. {
  495. struct fd_param *fd;
  496. unsigned long *p_index, mode;
  497. mode = is->scenario_id;
  498. p_index = &is->cfg_param[mode].p_region_index2;
  499. fd = &is->cfg_param[mode].fd;
  500. fd->config.eye_detect = val;
  501. if (!test_bit((PARAM_FD_CONFIG - 32), p_index)) {
  502. fd->config.cmd = FD_CONFIG_COMMAND_EYES_DETECT;
  503. fd->config.err = ERROR_FD_NONE;
  504. fimc_is_set_param_bit(is, PARAM_FD_CONFIG);
  505. } else {
  506. fd->config.cmd |= FD_CONFIG_COMMAND_EYES_DETECT;
  507. }
  508. }
  509. void __is_set_fd_config_mouthdetect(struct fimc_is *is, u32 val)
  510. {
  511. struct fd_param *fd;
  512. unsigned long *p_index, mode;
  513. mode = is->scenario_id;
  514. p_index = &is->cfg_param[mode].p_region_index2;
  515. fd = &is->cfg_param[mode].fd;
  516. fd->config.mouth_detect = val;
  517. if (!test_bit((PARAM_FD_CONFIG - 32), p_index)) {
  518. fd->config.cmd = FD_CONFIG_COMMAND_MOUTH_DETECT;
  519. fd->config.err = ERROR_FD_NONE;
  520. fimc_is_set_param_bit(is, PARAM_FD_CONFIG);
  521. } else {
  522. fd->config.cmd |= FD_CONFIG_COMMAND_MOUTH_DETECT;
  523. }
  524. }
  525. void __is_set_fd_config_orientation(struct fimc_is *is, u32 val)
  526. {
  527. struct fd_param *fd;
  528. unsigned long *p_index, mode;
  529. mode = is->scenario_id;
  530. p_index = &is->cfg_param[mode].p_region_index2;
  531. fd = &is->cfg_param[mode].fd;
  532. fd->config.orientation = val;
  533. if (!test_bit((PARAM_FD_CONFIG - 32), p_index)) {
  534. fd->config.cmd = FD_CONFIG_COMMAND_ORIENTATION;
  535. fd->config.err = ERROR_FD_NONE;
  536. fimc_is_set_param_bit(is, PARAM_FD_CONFIG);
  537. } else {
  538. fd->config.cmd |= FD_CONFIG_COMMAND_ORIENTATION;
  539. }
  540. }
  541. void __is_set_fd_config_orientation_val(struct fimc_is *is, u32 val)
  542. {
  543. struct fd_param *fd;
  544. unsigned long *p_index, mode;
  545. mode = is->scenario_id;
  546. p_index = &is->cfg_param[mode].p_region_index2;
  547. fd = &is->cfg_param[mode].fd;
  548. fd->config.orientation_value = val;
  549. if (!test_bit((PARAM_FD_CONFIG - 32), p_index)) {
  550. fd->config.cmd = FD_CONFIG_COMMAND_ORIENTATION_VALUE;
  551. fd->config.err = ERROR_FD_NONE;
  552. fimc_is_set_param_bit(is, PARAM_FD_CONFIG);
  553. } else {
  554. fd->config.cmd |= FD_CONFIG_COMMAND_ORIENTATION_VALUE;
  555. }
  556. }
  557. void fimc_is_set_initial_params(struct fimc_is *is)
  558. {
  559. struct global_param *global;
  560. struct sensor_param *sensor;
  561. struct isp_param *isp;
  562. struct drc_param *drc;
  563. struct fd_param *fd;
  564. unsigned long *p_index1, *p_index2;
  565. unsigned int mode;
  566. mode = is->scenario_id;
  567. global = &is->cfg_param[mode].global;
  568. sensor = &is->cfg_param[mode].sensor;
  569. isp = &is->cfg_param[mode].isp;
  570. drc = &is->cfg_param[mode].drc;
  571. fd = &is->cfg_param[mode].fd;
  572. p_index1 = &is->cfg_param[mode].p_region_index1;
  573. p_index2 = &is->cfg_param[mode].p_region_index2;
  574. /* Global */
  575. global->shotmode.cmd = 1;
  576. fimc_is_set_param_bit(is, PARAM_GLOBAL_SHOTMODE);
  577. /* ISP */
  578. isp->control.cmd = CONTROL_COMMAND_START;
  579. isp->control.bypass = CONTROL_BYPASS_DISABLE;
  580. isp->control.err = CONTROL_ERROR_NONE;
  581. fimc_is_set_param_bit(is, PARAM_ISP_CONTROL);
  582. isp->otf_input.cmd = OTF_INPUT_COMMAND_ENABLE;
  583. if (!test_bit(PARAM_ISP_OTF_INPUT, p_index1)) {
  584. isp->otf_input.width = DEFAULT_PREVIEW_STILL_WIDTH;
  585. isp->otf_input.height = DEFAULT_PREVIEW_STILL_HEIGHT;
  586. fimc_is_set_param_bit(is, PARAM_ISP_OTF_INPUT);
  587. }
  588. if (is->sensor->test_pattern)
  589. isp->otf_input.format = OTF_INPUT_FORMAT_STRGEN_COLORBAR_BAYER;
  590. else
  591. isp->otf_input.format = OTF_INPUT_FORMAT_BAYER;
  592. isp->otf_input.bitwidth = 10;
  593. isp->otf_input.order = OTF_INPUT_ORDER_BAYER_GR_BG;
  594. isp->otf_input.crop_offset_x = 0;
  595. isp->otf_input.crop_offset_y = 0;
  596. isp->otf_input.err = OTF_INPUT_ERROR_NONE;
  597. isp->dma1_input.cmd = DMA_INPUT_COMMAND_DISABLE;
  598. isp->dma1_input.width = 0;
  599. isp->dma1_input.height = 0;
  600. isp->dma1_input.format = 0;
  601. isp->dma1_input.bitwidth = 0;
  602. isp->dma1_input.plane = 0;
  603. isp->dma1_input.order = 0;
  604. isp->dma1_input.buffer_number = 0;
  605. isp->dma1_input.width = 0;
  606. isp->dma1_input.err = DMA_INPUT_ERROR_NONE;
  607. fimc_is_set_param_bit(is, PARAM_ISP_DMA1_INPUT);
  608. isp->dma2_input.cmd = DMA_INPUT_COMMAND_DISABLE;
  609. isp->dma2_input.width = 0;
  610. isp->dma2_input.height = 0;
  611. isp->dma2_input.format = 0;
  612. isp->dma2_input.bitwidth = 0;
  613. isp->dma2_input.plane = 0;
  614. isp->dma2_input.order = 0;
  615. isp->dma2_input.buffer_number = 0;
  616. isp->dma2_input.width = 0;
  617. isp->dma2_input.err = DMA_INPUT_ERROR_NONE;
  618. fimc_is_set_param_bit(is, PARAM_ISP_DMA2_INPUT);
  619. isp->aa.cmd = ISP_AA_COMMAND_START;
  620. isp->aa.target = ISP_AA_TARGET_AE | ISP_AA_TARGET_AWB;
  621. fimc_is_set_param_bit(is, PARAM_ISP_AA);
  622. if (!test_bit(PARAM_ISP_FLASH, p_index1))
  623. __is_set_isp_flash(is, ISP_FLASH_COMMAND_DISABLE,
  624. ISP_FLASH_REDEYE_DISABLE);
  625. if (!test_bit(PARAM_ISP_AWB, p_index1))
  626. __is_set_isp_awb(is, ISP_AWB_COMMAND_AUTO, 0);
  627. if (!test_bit(PARAM_ISP_IMAGE_EFFECT, p_index1))
  628. __is_set_isp_effect(is, ISP_IMAGE_EFFECT_DISABLE);
  629. if (!test_bit(PARAM_ISP_ISO, p_index1))
  630. __is_set_isp_iso(is, ISP_ISO_COMMAND_AUTO, 0);
  631. if (!test_bit(PARAM_ISP_ADJUST, p_index1)) {
  632. __is_set_isp_adjust(is, ISP_ADJUST_COMMAND_MANUAL_CONTRAST, 0);
  633. __is_set_isp_adjust(is,
  634. ISP_ADJUST_COMMAND_MANUAL_SATURATION, 0);
  635. __is_set_isp_adjust(is, ISP_ADJUST_COMMAND_MANUAL_SHARPNESS, 0);
  636. __is_set_isp_adjust(is, ISP_ADJUST_COMMAND_MANUAL_EXPOSURE, 0);
  637. __is_set_isp_adjust(is,
  638. ISP_ADJUST_COMMAND_MANUAL_BRIGHTNESS, 0);
  639. __is_set_isp_adjust(is, ISP_ADJUST_COMMAND_MANUAL_HUE, 0);
  640. }
  641. if (!test_bit(PARAM_ISP_METERING, p_index1)) {
  642. __is_set_isp_metering(is, 0, ISP_METERING_COMMAND_CENTER);
  643. __is_set_isp_metering(is, 1, 0);
  644. __is_set_isp_metering(is, 2, 0);
  645. __is_set_isp_metering(is, 3, 0);
  646. __is_set_isp_metering(is, 4, 0);
  647. }
  648. if (!test_bit(PARAM_ISP_AFC, p_index1))
  649. __is_set_isp_afc(is, ISP_AFC_COMMAND_AUTO, 0);
  650. isp->otf_output.cmd = OTF_OUTPUT_COMMAND_ENABLE;
  651. if (!test_bit(PARAM_ISP_OTF_OUTPUT, p_index1)) {
  652. isp->otf_output.width = DEFAULT_PREVIEW_STILL_WIDTH;
  653. isp->otf_output.height = DEFAULT_PREVIEW_STILL_HEIGHT;
  654. fimc_is_set_param_bit(is, PARAM_ISP_OTF_OUTPUT);
  655. }
  656. isp->otf_output.format = OTF_OUTPUT_FORMAT_YUV444;
  657. isp->otf_output.bitwidth = 12;
  658. isp->otf_output.order = 0;
  659. isp->otf_output.err = OTF_OUTPUT_ERROR_NONE;
  660. if (!test_bit(PARAM_ISP_DMA1_OUTPUT, p_index1)) {
  661. isp->dma1_output.cmd = DMA_OUTPUT_COMMAND_DISABLE;
  662. isp->dma1_output.width = 0;
  663. isp->dma1_output.height = 0;
  664. isp->dma1_output.format = 0;
  665. isp->dma1_output.bitwidth = 0;
  666. isp->dma1_output.plane = 0;
  667. isp->dma1_output.order = 0;
  668. isp->dma1_output.buffer_number = 0;
  669. isp->dma1_output.buffer_address = 0;
  670. isp->dma1_output.notify_dma_done = 0;
  671. isp->dma1_output.dma_out_mask = 0;
  672. isp->dma1_output.err = DMA_OUTPUT_ERROR_NONE;
  673. fimc_is_set_param_bit(is, PARAM_ISP_DMA1_OUTPUT);
  674. }
  675. if (!test_bit(PARAM_ISP_DMA2_OUTPUT, p_index1)) {
  676. isp->dma2_output.cmd = DMA_OUTPUT_COMMAND_DISABLE;
  677. isp->dma2_output.width = 0;
  678. isp->dma2_output.height = 0;
  679. isp->dma2_output.format = 0;
  680. isp->dma2_output.bitwidth = 0;
  681. isp->dma2_output.plane = 0;
  682. isp->dma2_output.order = 0;
  683. isp->dma2_output.buffer_number = 0;
  684. isp->dma2_output.buffer_address = 0;
  685. isp->dma2_output.notify_dma_done = 0;
  686. isp->dma2_output.dma_out_mask = 0;
  687. isp->dma2_output.err = DMA_OUTPUT_ERROR_NONE;
  688. fimc_is_set_param_bit(is, PARAM_ISP_DMA2_OUTPUT);
  689. }
  690. /* Sensor */
  691. if (!test_bit(PARAM_SENSOR_FRAME_RATE, p_index1)) {
  692. if (!mode)
  693. __is_set_sensor(is, 0);
  694. }
  695. /* DRC */
  696. drc->control.cmd = CONTROL_COMMAND_START;
  697. __is_set_drc_control(is, CONTROL_BYPASS_ENABLE);
  698. drc->otf_input.cmd = OTF_INPUT_COMMAND_ENABLE;
  699. if (!test_bit(PARAM_DRC_OTF_INPUT, p_index1)) {
  700. drc->otf_input.width = DEFAULT_PREVIEW_STILL_WIDTH;
  701. drc->otf_input.height = DEFAULT_PREVIEW_STILL_HEIGHT;
  702. fimc_is_set_param_bit(is, PARAM_DRC_OTF_INPUT);
  703. }
  704. drc->otf_input.format = OTF_INPUT_FORMAT_YUV444;
  705. drc->otf_input.bitwidth = 12;
  706. drc->otf_input.order = 0;
  707. drc->otf_input.err = OTF_INPUT_ERROR_NONE;
  708. drc->dma_input.cmd = DMA_INPUT_COMMAND_DISABLE;
  709. drc->dma_input.width = 0;
  710. drc->dma_input.height = 0;
  711. drc->dma_input.format = 0;
  712. drc->dma_input.bitwidth = 0;
  713. drc->dma_input.plane = 0;
  714. drc->dma_input.order = 0;
  715. drc->dma_input.buffer_number = 0;
  716. drc->dma_input.width = 0;
  717. drc->dma_input.err = DMA_INPUT_ERROR_NONE;
  718. fimc_is_set_param_bit(is, PARAM_DRC_DMA_INPUT);
  719. drc->otf_output.cmd = OTF_OUTPUT_COMMAND_ENABLE;
  720. if (!test_bit(PARAM_DRC_OTF_OUTPUT, p_index1)) {
  721. drc->otf_output.width = DEFAULT_PREVIEW_STILL_WIDTH;
  722. drc->otf_output.height = DEFAULT_PREVIEW_STILL_HEIGHT;
  723. fimc_is_set_param_bit(is, PARAM_DRC_OTF_OUTPUT);
  724. }
  725. drc->otf_output.format = OTF_OUTPUT_FORMAT_YUV444;
  726. drc->otf_output.bitwidth = 8;
  727. drc->otf_output.order = 0;
  728. drc->otf_output.err = OTF_OUTPUT_ERROR_NONE;
  729. /* FD */
  730. __is_set_fd_control(is, CONTROL_COMMAND_STOP);
  731. fd->control.bypass = CONTROL_BYPASS_DISABLE;
  732. fd->otf_input.cmd = OTF_INPUT_COMMAND_ENABLE;
  733. if (!test_bit((PARAM_FD_OTF_INPUT - 32), p_index2)) {
  734. fd->otf_input.width = DEFAULT_PREVIEW_STILL_WIDTH;
  735. fd->otf_input.height = DEFAULT_PREVIEW_STILL_HEIGHT;
  736. fimc_is_set_param_bit(is, PARAM_FD_OTF_INPUT);
  737. }
  738. fd->otf_input.format = OTF_INPUT_FORMAT_YUV444;
  739. fd->otf_input.bitwidth = 8;
  740. fd->otf_input.order = 0;
  741. fd->otf_input.err = OTF_INPUT_ERROR_NONE;
  742. fd->dma_input.cmd = DMA_INPUT_COMMAND_DISABLE;
  743. fd->dma_input.width = 0;
  744. fd->dma_input.height = 0;
  745. fd->dma_input.format = 0;
  746. fd->dma_input.bitwidth = 0;
  747. fd->dma_input.plane = 0;
  748. fd->dma_input.order = 0;
  749. fd->dma_input.buffer_number = 0;
  750. fd->dma_input.width = 0;
  751. fd->dma_input.err = DMA_INPUT_ERROR_NONE;
  752. fimc_is_set_param_bit(is, PARAM_FD_DMA_INPUT);
  753. __is_set_fd_config_maxface(is, 5);
  754. __is_set_fd_config_rollangle(is, FD_CONFIG_ROLL_ANGLE_FULL);
  755. __is_set_fd_config_yawangle(is, FD_CONFIG_YAW_ANGLE_45_90);
  756. __is_set_fd_config_smilemode(is, FD_CONFIG_SMILE_MODE_DISABLE);
  757. __is_set_fd_config_blinkmode(is, FD_CONFIG_BLINK_MODE_DISABLE);
  758. __is_set_fd_config_eyedetect(is, FD_CONFIG_EYES_DETECT_ENABLE);
  759. __is_set_fd_config_mouthdetect(is, FD_CONFIG_MOUTH_DETECT_DISABLE);
  760. __is_set_fd_config_orientation(is, FD_CONFIG_ORIENTATION_DISABLE);
  761. __is_set_fd_config_orientation_val(is, 0);
  762. }