phy3250.dts 3.0 KB

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  1. /*
  2. * PHYTEC phyCORE-LPC3250 board
  3. *
  4. * Copyright 2012 Roland Stigge <stigge@antcom.de>
  5. *
  6. * The code contained herein is licensed under the GNU General Public
  7. * License. You may obtain a copy of the GNU General Public License
  8. * Version 2 or later at the following locations:
  9. *
  10. * http://www.opensource.org/licenses/gpl-license.html
  11. * http://www.gnu.org/copyleft/gpl.html
  12. */
  13. /dts-v1/;
  14. /include/ "lpc32xx.dtsi"
  15. / {
  16. model = "PHYTEC phyCORE-LPC3250 board based on NXP LPC3250";
  17. compatible = "phytec,phy3250", "nxp,lpc3250";
  18. #address-cells = <1>;
  19. #size-cells = <1>;
  20. memory {
  21. device_type = "memory";
  22. reg = <0 0x4000000>;
  23. };
  24. ahb {
  25. mac: ethernet@31060000 {
  26. phy-mode = "rmii";
  27. use-iram;
  28. };
  29. /* Here, choose exactly one from: ohci, usbd */
  30. ohci@31020000 {
  31. transceiver = <&isp1301>;
  32. status = "okay";
  33. };
  34. /*
  35. usbd@31020000 {
  36. transceiver = <&isp1301>;
  37. status = "okay";
  38. };
  39. */
  40. clcd@31040000 {
  41. status = "okay";
  42. };
  43. /* 64MB Flash via SLC NAND controller */
  44. slc: flash@20020000 {
  45. status = "okay";
  46. #address-cells = <1>;
  47. #size-cells = <1>;
  48. nxp,wdr-clks = <14>;
  49. nxp,wwidth = <40000000>;
  50. nxp,whold = <100000000>;
  51. nxp,wsetup = <100000000>;
  52. nxp,rdr-clks = <14>;
  53. nxp,rwidth = <40000000>;
  54. nxp,rhold = <66666666>;
  55. nxp,rsetup = <100000000>;
  56. nand-on-flash-bbt;
  57. gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */
  58. mtd0@00000000 {
  59. label = "phy3250-boot";
  60. reg = <0x00000000 0x00064000>;
  61. read-only;
  62. };
  63. mtd1@00064000 {
  64. label = "phy3250-uboot";
  65. reg = <0x00064000 0x00190000>;
  66. read-only;
  67. };
  68. mtd2@001f4000 {
  69. label = "phy3250-ubt-prms";
  70. reg = <0x001f4000 0x00010000>;
  71. };
  72. mtd3@00204000 {
  73. label = "phy3250-kernel";
  74. reg = <0x00204000 0x00400000>;
  75. };
  76. mtd4@00604000 {
  77. label = "phy3250-rootfs";
  78. reg = <0x00604000 0x039fc000>;
  79. };
  80. };
  81. apb {
  82. i2c1: i2c@400A0000 {
  83. clock-frequency = <100000>;
  84. pcf8563: rtc@51 {
  85. compatible = "nxp,pcf8563";
  86. reg = <0x51>;
  87. };
  88. uda1380: uda1380@18 {
  89. compatible = "nxp,uda1380";
  90. reg = <0x18>;
  91. power-gpio = <&gpio 0x59 0>;
  92. reset-gpio = <&gpio 0x51 0>;
  93. dac-clk = "wspll";
  94. };
  95. };
  96. i2c2: i2c@400A8000 {
  97. clock-frequency = <100000>;
  98. };
  99. i2cusb: i2c@31020300 {
  100. clock-frequency = <100000>;
  101. isp1301: usb-transceiver@2c {
  102. compatible = "nxp,isp1301";
  103. reg = <0x2c>;
  104. };
  105. };
  106. ssp0: ssp@20084000 {
  107. eeprom: at25@0 {
  108. compatible = "atmel,at25";
  109. };
  110. };
  111. };
  112. fab {
  113. tsc@40048000 {
  114. status = "okay";
  115. };
  116. key@40050000 {
  117. status = "okay";
  118. keypad,num-rows = <1>;
  119. keypad,num-columns = <1>;
  120. nxp,debounce-delay-ms = <3>;
  121. nxp,scan-delay-ms = <34>;
  122. linux,keymap = <0x00000002>;
  123. };
  124. };
  125. };
  126. leds {
  127. compatible = "gpio-leds";
  128. led0 {
  129. gpios = <&gpio 5 1 1>; /* GPO_P3 1, GPIO 80, active low */
  130. linux,default-trigger = "heartbeat";
  131. default-state = "off";
  132. };
  133. led1 {
  134. gpios = <&gpio 5 14 1>; /* GPO_P3 14, GPIO 93, active low */
  135. linux,default-trigger = "timer";
  136. default-state = "off";
  137. };
  138. };
  139. };