i915_debugfs.c 28 KB

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  1. /*
  2. * Copyright © 2008 Intel Corporation
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the next
  12. * paragraph) shall be included in all copies or substantial portions of the
  13. * Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21. * IN THE SOFTWARE.
  22. *
  23. * Authors:
  24. * Eric Anholt <eric@anholt.net>
  25. * Keith Packard <keithp@keithp.com>
  26. *
  27. */
  28. #include <linux/seq_file.h>
  29. #include <linux/debugfs.h>
  30. #include <linux/slab.h>
  31. #include "drmP.h"
  32. #include "drm.h"
  33. #include "intel_drv.h"
  34. #include "i915_drm.h"
  35. #include "i915_drv.h"
  36. #define DRM_I915_RING_DEBUG 1
  37. #if defined(CONFIG_DEBUG_FS)
  38. #define ACTIVE_LIST 1
  39. #define FLUSHING_LIST 2
  40. #define INACTIVE_LIST 3
  41. static const char *yesno(int v)
  42. {
  43. return v ? "yes" : "no";
  44. }
  45. static int i915_capabilities(struct seq_file *m, void *data)
  46. {
  47. struct drm_info_node *node = (struct drm_info_node *) m->private;
  48. struct drm_device *dev = node->minor->dev;
  49. const struct intel_device_info *info = INTEL_INFO(dev);
  50. seq_printf(m, "gen: %d\n", info->gen);
  51. #define B(x) seq_printf(m, #x ": %s\n", yesno(info->x))
  52. B(is_mobile);
  53. B(is_i85x);
  54. B(is_i915g);
  55. B(is_i945gm);
  56. B(is_g33);
  57. B(need_gfx_hws);
  58. B(is_g4x);
  59. B(is_pineview);
  60. B(is_broadwater);
  61. B(is_crestline);
  62. B(is_ironlake);
  63. B(has_fbc);
  64. B(has_rc6);
  65. B(has_pipe_cxsr);
  66. B(has_hotplug);
  67. B(cursor_needs_physical);
  68. B(has_overlay);
  69. B(overlay_needs_physical);
  70. B(supports_tv);
  71. #undef B
  72. return 0;
  73. }
  74. static const char *get_pin_flag(struct drm_i915_gem_object *obj_priv)
  75. {
  76. if (obj_priv->user_pin_count > 0)
  77. return "P";
  78. else if (obj_priv->pin_count > 0)
  79. return "p";
  80. else
  81. return " ";
  82. }
  83. static const char *get_tiling_flag(struct drm_i915_gem_object *obj_priv)
  84. {
  85. switch (obj_priv->tiling_mode) {
  86. default:
  87. case I915_TILING_NONE: return " ";
  88. case I915_TILING_X: return "X";
  89. case I915_TILING_Y: return "Y";
  90. }
  91. }
  92. static void
  93. describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
  94. {
  95. seq_printf(m, "%p: %s%s %8zd %08x %08x %d%s%s",
  96. &obj->base,
  97. get_pin_flag(obj),
  98. get_tiling_flag(obj),
  99. obj->base.size,
  100. obj->base.read_domains,
  101. obj->base.write_domain,
  102. obj->last_rendering_seqno,
  103. obj->dirty ? " dirty" : "",
  104. obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
  105. if (obj->base.name)
  106. seq_printf(m, " (name: %d)", obj->base.name);
  107. if (obj->fence_reg != I915_FENCE_REG_NONE)
  108. seq_printf(m, " (fence: %d)", obj->fence_reg);
  109. if (obj->gtt_space != NULL)
  110. seq_printf(m, " (gtt_offset: %08x)", obj->gtt_offset);
  111. }
  112. static int i915_gem_object_list_info(struct seq_file *m, void *data)
  113. {
  114. struct drm_info_node *node = (struct drm_info_node *) m->private;
  115. uintptr_t list = (uintptr_t) node->info_ent->data;
  116. struct list_head *head;
  117. struct drm_device *dev = node->minor->dev;
  118. drm_i915_private_t *dev_priv = dev->dev_private;
  119. struct drm_i915_gem_object *obj_priv;
  120. int ret;
  121. ret = mutex_lock_interruptible(&dev->struct_mutex);
  122. if (ret)
  123. return ret;
  124. switch (list) {
  125. case ACTIVE_LIST:
  126. seq_printf(m, "Active:\n");
  127. head = &dev_priv->render_ring.active_list;
  128. break;
  129. case INACTIVE_LIST:
  130. seq_printf(m, "Inactive:\n");
  131. head = &dev_priv->mm.inactive_list;
  132. break;
  133. case FLUSHING_LIST:
  134. seq_printf(m, "Flushing:\n");
  135. head = &dev_priv->mm.flushing_list;
  136. break;
  137. default:
  138. mutex_unlock(&dev->struct_mutex);
  139. return -EINVAL;
  140. }
  141. list_for_each_entry(obj_priv, head, list) {
  142. seq_printf(m, " ");
  143. describe_obj(m, obj_priv);
  144. seq_printf(m, "\n");
  145. }
  146. mutex_unlock(&dev->struct_mutex);
  147. return 0;
  148. }
  149. static int i915_gem_pageflip_info(struct seq_file *m, void *data)
  150. {
  151. struct drm_info_node *node = (struct drm_info_node *) m->private;
  152. struct drm_device *dev = node->minor->dev;
  153. unsigned long flags;
  154. struct intel_crtc *crtc;
  155. list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
  156. const char *pipe = crtc->pipe ? "B" : "A";
  157. const char *plane = crtc->plane ? "B" : "A";
  158. struct intel_unpin_work *work;
  159. spin_lock_irqsave(&dev->event_lock, flags);
  160. work = crtc->unpin_work;
  161. if (work == NULL) {
  162. seq_printf(m, "No flip due on pipe %s (plane %s)\n",
  163. pipe, plane);
  164. } else {
  165. if (!work->pending) {
  166. seq_printf(m, "Flip queued on pipe %s (plane %s)\n",
  167. pipe, plane);
  168. } else {
  169. seq_printf(m, "Flip pending (waiting for vsync) on pipe %s (plane %s)\n",
  170. pipe, plane);
  171. }
  172. if (work->enable_stall_check)
  173. seq_printf(m, "Stall check enabled, ");
  174. else
  175. seq_printf(m, "Stall check waiting for page flip ioctl, ");
  176. seq_printf(m, "%d prepares\n", work->pending);
  177. if (work->old_fb_obj) {
  178. struct drm_i915_gem_object *obj_priv = to_intel_bo(work->old_fb_obj);
  179. if(obj_priv)
  180. seq_printf(m, "Old framebuffer gtt_offset 0x%08x\n", obj_priv->gtt_offset );
  181. }
  182. if (work->pending_flip_obj) {
  183. struct drm_i915_gem_object *obj_priv = to_intel_bo(work->pending_flip_obj);
  184. if(obj_priv)
  185. seq_printf(m, "New framebuffer gtt_offset 0x%08x\n", obj_priv->gtt_offset );
  186. }
  187. }
  188. spin_unlock_irqrestore(&dev->event_lock, flags);
  189. }
  190. return 0;
  191. }
  192. static int i915_gem_request_info(struct seq_file *m, void *data)
  193. {
  194. struct drm_info_node *node = (struct drm_info_node *) m->private;
  195. struct drm_device *dev = node->minor->dev;
  196. drm_i915_private_t *dev_priv = dev->dev_private;
  197. struct drm_i915_gem_request *gem_request;
  198. int ret;
  199. ret = mutex_lock_interruptible(&dev->struct_mutex);
  200. if (ret)
  201. return ret;
  202. seq_printf(m, "Request:\n");
  203. list_for_each_entry(gem_request, &dev_priv->render_ring.request_list,
  204. list) {
  205. seq_printf(m, " %d @ %d\n",
  206. gem_request->seqno,
  207. (int) (jiffies - gem_request->emitted_jiffies));
  208. }
  209. mutex_unlock(&dev->struct_mutex);
  210. return 0;
  211. }
  212. static int i915_gem_seqno_info(struct seq_file *m, void *data)
  213. {
  214. struct drm_info_node *node = (struct drm_info_node *) m->private;
  215. struct drm_device *dev = node->minor->dev;
  216. drm_i915_private_t *dev_priv = dev->dev_private;
  217. int ret;
  218. ret = mutex_lock_interruptible(&dev->struct_mutex);
  219. if (ret)
  220. return ret;
  221. if (dev_priv->render_ring.status_page.page_addr != NULL) {
  222. seq_printf(m, "Current sequence: %d\n",
  223. i915_get_gem_seqno(dev, &dev_priv->render_ring));
  224. } else {
  225. seq_printf(m, "Current sequence: hws uninitialized\n");
  226. }
  227. seq_printf(m, "Waiter sequence: %d\n",
  228. dev_priv->mm.waiting_gem_seqno);
  229. seq_printf(m, "IRQ sequence: %d\n", dev_priv->mm.irq_gem_seqno);
  230. mutex_unlock(&dev->struct_mutex);
  231. return 0;
  232. }
  233. static int i915_interrupt_info(struct seq_file *m, void *data)
  234. {
  235. struct drm_info_node *node = (struct drm_info_node *) m->private;
  236. struct drm_device *dev = node->minor->dev;
  237. drm_i915_private_t *dev_priv = dev->dev_private;
  238. int ret;
  239. ret = mutex_lock_interruptible(&dev->struct_mutex);
  240. if (ret)
  241. return ret;
  242. if (!HAS_PCH_SPLIT(dev)) {
  243. seq_printf(m, "Interrupt enable: %08x\n",
  244. I915_READ(IER));
  245. seq_printf(m, "Interrupt identity: %08x\n",
  246. I915_READ(IIR));
  247. seq_printf(m, "Interrupt mask: %08x\n",
  248. I915_READ(IMR));
  249. seq_printf(m, "Pipe A stat: %08x\n",
  250. I915_READ(PIPEASTAT));
  251. seq_printf(m, "Pipe B stat: %08x\n",
  252. I915_READ(PIPEBSTAT));
  253. } else {
  254. seq_printf(m, "North Display Interrupt enable: %08x\n",
  255. I915_READ(DEIER));
  256. seq_printf(m, "North Display Interrupt identity: %08x\n",
  257. I915_READ(DEIIR));
  258. seq_printf(m, "North Display Interrupt mask: %08x\n",
  259. I915_READ(DEIMR));
  260. seq_printf(m, "South Display Interrupt enable: %08x\n",
  261. I915_READ(SDEIER));
  262. seq_printf(m, "South Display Interrupt identity: %08x\n",
  263. I915_READ(SDEIIR));
  264. seq_printf(m, "South Display Interrupt mask: %08x\n",
  265. I915_READ(SDEIMR));
  266. seq_printf(m, "Graphics Interrupt enable: %08x\n",
  267. I915_READ(GTIER));
  268. seq_printf(m, "Graphics Interrupt identity: %08x\n",
  269. I915_READ(GTIIR));
  270. seq_printf(m, "Graphics Interrupt mask: %08x\n",
  271. I915_READ(GTIMR));
  272. }
  273. seq_printf(m, "Interrupts received: %d\n",
  274. atomic_read(&dev_priv->irq_received));
  275. if (dev_priv->render_ring.status_page.page_addr != NULL) {
  276. seq_printf(m, "Current sequence: %d\n",
  277. i915_get_gem_seqno(dev, &dev_priv->render_ring));
  278. } else {
  279. seq_printf(m, "Current sequence: hws uninitialized\n");
  280. }
  281. seq_printf(m, "Waiter sequence: %d\n",
  282. dev_priv->mm.waiting_gem_seqno);
  283. seq_printf(m, "IRQ sequence: %d\n",
  284. dev_priv->mm.irq_gem_seqno);
  285. mutex_unlock(&dev->struct_mutex);
  286. return 0;
  287. }
  288. static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
  289. {
  290. struct drm_info_node *node = (struct drm_info_node *) m->private;
  291. struct drm_device *dev = node->minor->dev;
  292. drm_i915_private_t *dev_priv = dev->dev_private;
  293. int i, ret;
  294. ret = mutex_lock_interruptible(&dev->struct_mutex);
  295. if (ret)
  296. return ret;
  297. seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
  298. seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
  299. for (i = 0; i < dev_priv->num_fence_regs; i++) {
  300. struct drm_gem_object *obj = dev_priv->fence_regs[i].obj;
  301. if (obj == NULL) {
  302. seq_printf(m, "Fenced object[%2d] = unused\n", i);
  303. } else {
  304. struct drm_i915_gem_object *obj_priv;
  305. obj_priv = to_intel_bo(obj);
  306. seq_printf(m, "Fenced object[%2d] = %p: %s "
  307. "%08x %08zx %08x %s %08x %08x %d",
  308. i, obj, get_pin_flag(obj_priv),
  309. obj_priv->gtt_offset,
  310. obj->size, obj_priv->stride,
  311. get_tiling_flag(obj_priv),
  312. obj->read_domains, obj->write_domain,
  313. obj_priv->last_rendering_seqno);
  314. if (obj->name)
  315. seq_printf(m, " (name: %d)", obj->name);
  316. seq_printf(m, "\n");
  317. }
  318. }
  319. mutex_unlock(&dev->struct_mutex);
  320. return 0;
  321. }
  322. static int i915_hws_info(struct seq_file *m, void *data)
  323. {
  324. struct drm_info_node *node = (struct drm_info_node *) m->private;
  325. struct drm_device *dev = node->minor->dev;
  326. drm_i915_private_t *dev_priv = dev->dev_private;
  327. int i;
  328. volatile u32 *hws;
  329. hws = (volatile u32 *)dev_priv->render_ring.status_page.page_addr;
  330. if (hws == NULL)
  331. return 0;
  332. for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
  333. seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
  334. i * 4,
  335. hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
  336. }
  337. return 0;
  338. }
  339. static void i915_dump_pages(struct seq_file *m, struct page **pages, int page_count)
  340. {
  341. int page, i;
  342. uint32_t *mem;
  343. for (page = 0; page < page_count; page++) {
  344. mem = kmap(pages[page]);
  345. for (i = 0; i < PAGE_SIZE; i += 4)
  346. seq_printf(m, "%08x : %08x\n", i, mem[i / 4]);
  347. kunmap(pages[page]);
  348. }
  349. }
  350. static int i915_batchbuffer_info(struct seq_file *m, void *data)
  351. {
  352. struct drm_info_node *node = (struct drm_info_node *) m->private;
  353. struct drm_device *dev = node->minor->dev;
  354. drm_i915_private_t *dev_priv = dev->dev_private;
  355. struct drm_gem_object *obj;
  356. struct drm_i915_gem_object *obj_priv;
  357. int ret;
  358. ret = mutex_lock_interruptible(&dev->struct_mutex);
  359. if (ret)
  360. return ret;
  361. list_for_each_entry(obj_priv, &dev_priv->render_ring.active_list,
  362. list) {
  363. obj = &obj_priv->base;
  364. if (obj->read_domains & I915_GEM_DOMAIN_COMMAND) {
  365. ret = i915_gem_object_get_pages(obj, 0);
  366. if (ret) {
  367. mutex_unlock(&dev->struct_mutex);
  368. return ret;
  369. }
  370. seq_printf(m, "--- gtt_offset = 0x%08x\n", obj_priv->gtt_offset);
  371. i915_dump_pages(m, obj_priv->pages, obj->size / PAGE_SIZE);
  372. i915_gem_object_put_pages(obj);
  373. }
  374. }
  375. mutex_unlock(&dev->struct_mutex);
  376. return 0;
  377. }
  378. static int i915_ringbuffer_data(struct seq_file *m, void *data)
  379. {
  380. struct drm_info_node *node = (struct drm_info_node *) m->private;
  381. struct drm_device *dev = node->minor->dev;
  382. drm_i915_private_t *dev_priv = dev->dev_private;
  383. int ret;
  384. ret = mutex_lock_interruptible(&dev->struct_mutex);
  385. if (ret)
  386. return ret;
  387. if (!dev_priv->render_ring.gem_object) {
  388. seq_printf(m, "No ringbuffer setup\n");
  389. } else {
  390. u8 *virt = dev_priv->render_ring.virtual_start;
  391. uint32_t off;
  392. for (off = 0; off < dev_priv->render_ring.size; off += 4) {
  393. uint32_t *ptr = (uint32_t *)(virt + off);
  394. seq_printf(m, "%08x : %08x\n", off, *ptr);
  395. }
  396. }
  397. mutex_unlock(&dev->struct_mutex);
  398. return 0;
  399. }
  400. static int i915_ringbuffer_info(struct seq_file *m, void *data)
  401. {
  402. struct drm_info_node *node = (struct drm_info_node *) m->private;
  403. struct drm_device *dev = node->minor->dev;
  404. drm_i915_private_t *dev_priv = dev->dev_private;
  405. unsigned int head, tail;
  406. head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
  407. tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
  408. seq_printf(m, "RingHead : %08x\n", head);
  409. seq_printf(m, "RingTail : %08x\n", tail);
  410. seq_printf(m, "RingSize : %08lx\n", dev_priv->render_ring.size);
  411. seq_printf(m, "Acthd : %08x\n", I915_READ(INTEL_INFO(dev)->gen >= 4 ? ACTHD_I965 : ACTHD));
  412. return 0;
  413. }
  414. static const char *pin_flag(int pinned)
  415. {
  416. if (pinned > 0)
  417. return " P";
  418. else if (pinned < 0)
  419. return " p";
  420. else
  421. return "";
  422. }
  423. static const char *tiling_flag(int tiling)
  424. {
  425. switch (tiling) {
  426. default:
  427. case I915_TILING_NONE: return "";
  428. case I915_TILING_X: return " X";
  429. case I915_TILING_Y: return " Y";
  430. }
  431. }
  432. static const char *dirty_flag(int dirty)
  433. {
  434. return dirty ? " dirty" : "";
  435. }
  436. static const char *purgeable_flag(int purgeable)
  437. {
  438. return purgeable ? " purgeable" : "";
  439. }
  440. static int i915_error_state(struct seq_file *m, void *unused)
  441. {
  442. struct drm_info_node *node = (struct drm_info_node *) m->private;
  443. struct drm_device *dev = node->minor->dev;
  444. drm_i915_private_t *dev_priv = dev->dev_private;
  445. struct drm_i915_error_state *error;
  446. unsigned long flags;
  447. int i, page, offset, elt;
  448. spin_lock_irqsave(&dev_priv->error_lock, flags);
  449. if (!dev_priv->first_error) {
  450. seq_printf(m, "no error state collected\n");
  451. goto out;
  452. }
  453. error = dev_priv->first_error;
  454. seq_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec,
  455. error->time.tv_usec);
  456. seq_printf(m, "PCI ID: 0x%04x\n", dev->pci_device);
  457. seq_printf(m, "EIR: 0x%08x\n", error->eir);
  458. seq_printf(m, " PGTBL_ER: 0x%08x\n", error->pgtbl_er);
  459. seq_printf(m, " INSTPM: 0x%08x\n", error->instpm);
  460. seq_printf(m, " IPEIR: 0x%08x\n", error->ipeir);
  461. seq_printf(m, " IPEHR: 0x%08x\n", error->ipehr);
  462. seq_printf(m, " INSTDONE: 0x%08x\n", error->instdone);
  463. seq_printf(m, " ACTHD: 0x%08x\n", error->acthd);
  464. if (INTEL_INFO(dev)->gen >= 4) {
  465. seq_printf(m, " INSTPS: 0x%08x\n", error->instps);
  466. seq_printf(m, " INSTDONE1: 0x%08x\n", error->instdone1);
  467. }
  468. seq_printf(m, "seqno: 0x%08x\n", error->seqno);
  469. if (error->active_bo_count) {
  470. seq_printf(m, "Buffers [%d]:\n", error->active_bo_count);
  471. for (i = 0; i < error->active_bo_count; i++) {
  472. seq_printf(m, " %08x %8zd %08x %08x %08x%s%s%s%s",
  473. error->active_bo[i].gtt_offset,
  474. error->active_bo[i].size,
  475. error->active_bo[i].read_domains,
  476. error->active_bo[i].write_domain,
  477. error->active_bo[i].seqno,
  478. pin_flag(error->active_bo[i].pinned),
  479. tiling_flag(error->active_bo[i].tiling),
  480. dirty_flag(error->active_bo[i].dirty),
  481. purgeable_flag(error->active_bo[i].purgeable));
  482. if (error->active_bo[i].name)
  483. seq_printf(m, " (name: %d)", error->active_bo[i].name);
  484. if (error->active_bo[i].fence_reg != I915_FENCE_REG_NONE)
  485. seq_printf(m, " (fence: %d)", error->active_bo[i].fence_reg);
  486. seq_printf(m, "\n");
  487. }
  488. }
  489. for (i = 0; i < ARRAY_SIZE(error->batchbuffer); i++) {
  490. if (error->batchbuffer[i]) {
  491. struct drm_i915_error_object *obj = error->batchbuffer[i];
  492. seq_printf(m, "--- gtt_offset = 0x%08x\n", obj->gtt_offset);
  493. offset = 0;
  494. for (page = 0; page < obj->page_count; page++) {
  495. for (elt = 0; elt < PAGE_SIZE/4; elt++) {
  496. seq_printf(m, "%08x : %08x\n", offset, obj->pages[page][elt]);
  497. offset += 4;
  498. }
  499. }
  500. }
  501. }
  502. if (error->ringbuffer) {
  503. struct drm_i915_error_object *obj = error->ringbuffer;
  504. seq_printf(m, "--- ringbuffer = 0x%08x\n", obj->gtt_offset);
  505. offset = 0;
  506. for (page = 0; page < obj->page_count; page++) {
  507. for (elt = 0; elt < PAGE_SIZE/4; elt++) {
  508. seq_printf(m, "%08x : %08x\n", offset, obj->pages[page][elt]);
  509. offset += 4;
  510. }
  511. }
  512. }
  513. if (error->overlay)
  514. intel_overlay_print_error_state(m, error->overlay);
  515. out:
  516. spin_unlock_irqrestore(&dev_priv->error_lock, flags);
  517. return 0;
  518. }
  519. static int i915_rstdby_delays(struct seq_file *m, void *unused)
  520. {
  521. struct drm_info_node *node = (struct drm_info_node *) m->private;
  522. struct drm_device *dev = node->minor->dev;
  523. drm_i915_private_t *dev_priv = dev->dev_private;
  524. u16 crstanddelay = I915_READ16(CRSTANDVID);
  525. seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f));
  526. return 0;
  527. }
  528. static int i915_cur_delayinfo(struct seq_file *m, void *unused)
  529. {
  530. struct drm_info_node *node = (struct drm_info_node *) m->private;
  531. struct drm_device *dev = node->minor->dev;
  532. drm_i915_private_t *dev_priv = dev->dev_private;
  533. u16 rgvswctl = I915_READ16(MEMSWCTL);
  534. u16 rgvstat = I915_READ16(MEMSTAT_ILK);
  535. seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
  536. seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
  537. seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
  538. MEMSTAT_VID_SHIFT);
  539. seq_printf(m, "Current P-state: %d\n",
  540. (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
  541. return 0;
  542. }
  543. static int i915_delayfreq_table(struct seq_file *m, void *unused)
  544. {
  545. struct drm_info_node *node = (struct drm_info_node *) m->private;
  546. struct drm_device *dev = node->minor->dev;
  547. drm_i915_private_t *dev_priv = dev->dev_private;
  548. u32 delayfreq;
  549. int i;
  550. for (i = 0; i < 16; i++) {
  551. delayfreq = I915_READ(PXVFREQ_BASE + i * 4);
  552. seq_printf(m, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i, delayfreq,
  553. (delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT);
  554. }
  555. return 0;
  556. }
  557. static inline int MAP_TO_MV(int map)
  558. {
  559. return 1250 - (map * 25);
  560. }
  561. static int i915_inttoext_table(struct seq_file *m, void *unused)
  562. {
  563. struct drm_info_node *node = (struct drm_info_node *) m->private;
  564. struct drm_device *dev = node->minor->dev;
  565. drm_i915_private_t *dev_priv = dev->dev_private;
  566. u32 inttoext;
  567. int i;
  568. for (i = 1; i <= 32; i++) {
  569. inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4);
  570. seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext);
  571. }
  572. return 0;
  573. }
  574. static int i915_drpc_info(struct seq_file *m, void *unused)
  575. {
  576. struct drm_info_node *node = (struct drm_info_node *) m->private;
  577. struct drm_device *dev = node->minor->dev;
  578. drm_i915_private_t *dev_priv = dev->dev_private;
  579. u32 rgvmodectl = I915_READ(MEMMODECTL);
  580. u32 rstdbyctl = I915_READ(MCHBAR_RENDER_STANDBY);
  581. u16 crstandvid = I915_READ16(CRSTANDVID);
  582. seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
  583. "yes" : "no");
  584. seq_printf(m, "Boost freq: %d\n",
  585. (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
  586. MEMMODE_BOOST_FREQ_SHIFT);
  587. seq_printf(m, "HW control enabled: %s\n",
  588. rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
  589. seq_printf(m, "SW control enabled: %s\n",
  590. rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
  591. seq_printf(m, "Gated voltage change: %s\n",
  592. rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
  593. seq_printf(m, "Starting frequency: P%d\n",
  594. (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
  595. seq_printf(m, "Max P-state: P%d\n",
  596. (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
  597. seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
  598. seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
  599. seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
  600. seq_printf(m, "Render standby enabled: %s\n",
  601. (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
  602. return 0;
  603. }
  604. static int i915_fbc_status(struct seq_file *m, void *unused)
  605. {
  606. struct drm_info_node *node = (struct drm_info_node *) m->private;
  607. struct drm_device *dev = node->minor->dev;
  608. drm_i915_private_t *dev_priv = dev->dev_private;
  609. if (!I915_HAS_FBC(dev)) {
  610. seq_printf(m, "FBC unsupported on this chipset\n");
  611. return 0;
  612. }
  613. if (intel_fbc_enabled(dev)) {
  614. seq_printf(m, "FBC enabled\n");
  615. } else {
  616. seq_printf(m, "FBC disabled: ");
  617. switch (dev_priv->no_fbc_reason) {
  618. case FBC_NO_OUTPUT:
  619. seq_printf(m, "no outputs");
  620. break;
  621. case FBC_STOLEN_TOO_SMALL:
  622. seq_printf(m, "not enough stolen memory");
  623. break;
  624. case FBC_UNSUPPORTED_MODE:
  625. seq_printf(m, "mode not supported");
  626. break;
  627. case FBC_MODE_TOO_LARGE:
  628. seq_printf(m, "mode too large");
  629. break;
  630. case FBC_BAD_PLANE:
  631. seq_printf(m, "FBC unsupported on plane");
  632. break;
  633. case FBC_NOT_TILED:
  634. seq_printf(m, "scanout buffer not tiled");
  635. break;
  636. case FBC_MULTIPLE_PIPES:
  637. seq_printf(m, "multiple pipes are enabled");
  638. break;
  639. default:
  640. seq_printf(m, "unknown reason");
  641. }
  642. seq_printf(m, "\n");
  643. }
  644. return 0;
  645. }
  646. static int i915_sr_status(struct seq_file *m, void *unused)
  647. {
  648. struct drm_info_node *node = (struct drm_info_node *) m->private;
  649. struct drm_device *dev = node->minor->dev;
  650. drm_i915_private_t *dev_priv = dev->dev_private;
  651. bool sr_enabled = false;
  652. if (IS_IRONLAKE(dev))
  653. sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
  654. else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
  655. sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
  656. else if (IS_I915GM(dev))
  657. sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
  658. else if (IS_PINEVIEW(dev))
  659. sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
  660. seq_printf(m, "self-refresh: %s\n",
  661. sr_enabled ? "enabled" : "disabled");
  662. return 0;
  663. }
  664. static int i915_emon_status(struct seq_file *m, void *unused)
  665. {
  666. struct drm_info_node *node = (struct drm_info_node *) m->private;
  667. struct drm_device *dev = node->minor->dev;
  668. drm_i915_private_t *dev_priv = dev->dev_private;
  669. unsigned long temp, chipset, gfx;
  670. int ret;
  671. ret = mutex_lock_interruptible(&dev->struct_mutex);
  672. if (ret)
  673. return ret;
  674. temp = i915_mch_val(dev_priv);
  675. chipset = i915_chipset_val(dev_priv);
  676. gfx = i915_gfx_val(dev_priv);
  677. mutex_unlock(&dev->struct_mutex);
  678. seq_printf(m, "GMCH temp: %ld\n", temp);
  679. seq_printf(m, "Chipset power: %ld\n", chipset);
  680. seq_printf(m, "GFX power: %ld\n", gfx);
  681. seq_printf(m, "Total power: %ld\n", chipset + gfx);
  682. return 0;
  683. }
  684. static int i915_gfxec(struct seq_file *m, void *unused)
  685. {
  686. struct drm_info_node *node = (struct drm_info_node *) m->private;
  687. struct drm_device *dev = node->minor->dev;
  688. drm_i915_private_t *dev_priv = dev->dev_private;
  689. seq_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4));
  690. return 0;
  691. }
  692. static int i915_opregion(struct seq_file *m, void *unused)
  693. {
  694. struct drm_info_node *node = (struct drm_info_node *) m->private;
  695. struct drm_device *dev = node->minor->dev;
  696. drm_i915_private_t *dev_priv = dev->dev_private;
  697. struct intel_opregion *opregion = &dev_priv->opregion;
  698. int ret;
  699. ret = mutex_lock_interruptible(&dev->struct_mutex);
  700. if (ret)
  701. return ret;
  702. if (opregion->header)
  703. seq_write(m, opregion->header, OPREGION_SIZE);
  704. mutex_unlock(&dev->struct_mutex);
  705. return 0;
  706. }
  707. static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
  708. {
  709. struct drm_info_node *node = (struct drm_info_node *) m->private;
  710. struct drm_device *dev = node->minor->dev;
  711. drm_i915_private_t *dev_priv = dev->dev_private;
  712. struct intel_fbdev *ifbdev;
  713. struct intel_framebuffer *fb;
  714. int ret;
  715. ret = mutex_lock_interruptible(&dev->mode_config.mutex);
  716. if (ret)
  717. return ret;
  718. ifbdev = dev_priv->fbdev;
  719. fb = to_intel_framebuffer(ifbdev->helper.fb);
  720. seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, obj ",
  721. fb->base.width,
  722. fb->base.height,
  723. fb->base.depth,
  724. fb->base.bits_per_pixel);
  725. describe_obj(m, to_intel_bo(fb->obj));
  726. seq_printf(m, "\n");
  727. list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
  728. if (&fb->base == ifbdev->helper.fb)
  729. continue;
  730. seq_printf(m, "user size: %d x %d, depth %d, %d bpp, obj ",
  731. fb->base.width,
  732. fb->base.height,
  733. fb->base.depth,
  734. fb->base.bits_per_pixel);
  735. describe_obj(m, to_intel_bo(fb->obj));
  736. seq_printf(m, "\n");
  737. }
  738. mutex_unlock(&dev->mode_config.mutex);
  739. return 0;
  740. }
  741. static int
  742. i915_wedged_open(struct inode *inode,
  743. struct file *filp)
  744. {
  745. filp->private_data = inode->i_private;
  746. return 0;
  747. }
  748. static ssize_t
  749. i915_wedged_read(struct file *filp,
  750. char __user *ubuf,
  751. size_t max,
  752. loff_t *ppos)
  753. {
  754. struct drm_device *dev = filp->private_data;
  755. drm_i915_private_t *dev_priv = dev->dev_private;
  756. char buf[80];
  757. int len;
  758. len = snprintf(buf, sizeof (buf),
  759. "wedged : %d\n",
  760. atomic_read(&dev_priv->mm.wedged));
  761. if (len > sizeof (buf))
  762. len = sizeof (buf);
  763. return simple_read_from_buffer(ubuf, max, ppos, buf, len);
  764. }
  765. static ssize_t
  766. i915_wedged_write(struct file *filp,
  767. const char __user *ubuf,
  768. size_t cnt,
  769. loff_t *ppos)
  770. {
  771. struct drm_device *dev = filp->private_data;
  772. drm_i915_private_t *dev_priv = dev->dev_private;
  773. char buf[20];
  774. int val = 1;
  775. if (cnt > 0) {
  776. if (cnt > sizeof (buf) - 1)
  777. return -EINVAL;
  778. if (copy_from_user(buf, ubuf, cnt))
  779. return -EFAULT;
  780. buf[cnt] = 0;
  781. val = simple_strtoul(buf, NULL, 0);
  782. }
  783. DRM_INFO("Manually setting wedged to %d\n", val);
  784. atomic_set(&dev_priv->mm.wedged, val);
  785. if (val) {
  786. DRM_WAKEUP(&dev_priv->irq_queue);
  787. queue_work(dev_priv->wq, &dev_priv->error_work);
  788. }
  789. return cnt;
  790. }
  791. static const struct file_operations i915_wedged_fops = {
  792. .owner = THIS_MODULE,
  793. .open = i915_wedged_open,
  794. .read = i915_wedged_read,
  795. .write = i915_wedged_write,
  796. };
  797. /* As the drm_debugfs_init() routines are called before dev->dev_private is
  798. * allocated we need to hook into the minor for release. */
  799. static int
  800. drm_add_fake_info_node(struct drm_minor *minor,
  801. struct dentry *ent,
  802. const void *key)
  803. {
  804. struct drm_info_node *node;
  805. node = kmalloc(sizeof(struct drm_info_node), GFP_KERNEL);
  806. if (node == NULL) {
  807. debugfs_remove(ent);
  808. return -ENOMEM;
  809. }
  810. node->minor = minor;
  811. node->dent = ent;
  812. node->info_ent = (void *) key;
  813. list_add(&node->list, &minor->debugfs_nodes.list);
  814. return 0;
  815. }
  816. static int i915_wedged_create(struct dentry *root, struct drm_minor *minor)
  817. {
  818. struct drm_device *dev = minor->dev;
  819. struct dentry *ent;
  820. ent = debugfs_create_file("i915_wedged",
  821. S_IRUGO | S_IWUSR,
  822. root, dev,
  823. &i915_wedged_fops);
  824. if (IS_ERR(ent))
  825. return PTR_ERR(ent);
  826. return drm_add_fake_info_node(minor, ent, &i915_wedged_fops);
  827. }
  828. static struct drm_info_list i915_debugfs_list[] = {
  829. {"i915_capabilities", i915_capabilities, 0, 0},
  830. {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
  831. {"i915_gem_flushing", i915_gem_object_list_info, 0, (void *) FLUSHING_LIST},
  832. {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
  833. {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
  834. {"i915_gem_request", i915_gem_request_info, 0},
  835. {"i915_gem_seqno", i915_gem_seqno_info, 0},
  836. {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
  837. {"i915_gem_interrupt", i915_interrupt_info, 0},
  838. {"i915_gem_hws", i915_hws_info, 0},
  839. {"i915_ringbuffer_data", i915_ringbuffer_data, 0},
  840. {"i915_ringbuffer_info", i915_ringbuffer_info, 0},
  841. {"i915_batchbuffers", i915_batchbuffer_info, 0},
  842. {"i915_error_state", i915_error_state, 0},
  843. {"i915_rstdby_delays", i915_rstdby_delays, 0},
  844. {"i915_cur_delayinfo", i915_cur_delayinfo, 0},
  845. {"i915_delayfreq_table", i915_delayfreq_table, 0},
  846. {"i915_inttoext_table", i915_inttoext_table, 0},
  847. {"i915_drpc_info", i915_drpc_info, 0},
  848. {"i915_emon_status", i915_emon_status, 0},
  849. {"i915_gfxec", i915_gfxec, 0},
  850. {"i915_fbc_status", i915_fbc_status, 0},
  851. {"i915_sr_status", i915_sr_status, 0},
  852. {"i915_opregion", i915_opregion, 0},
  853. {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
  854. };
  855. #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
  856. int i915_debugfs_init(struct drm_minor *minor)
  857. {
  858. int ret;
  859. ret = i915_wedged_create(minor->debugfs_root, minor);
  860. if (ret)
  861. return ret;
  862. return drm_debugfs_create_files(i915_debugfs_list,
  863. I915_DEBUGFS_ENTRIES,
  864. minor->debugfs_root, minor);
  865. }
  866. void i915_debugfs_cleanup(struct drm_minor *minor)
  867. {
  868. drm_debugfs_remove_files(i915_debugfs_list,
  869. I915_DEBUGFS_ENTRIES, minor);
  870. drm_debugfs_remove_files((struct drm_info_list *) &i915_wedged_fops,
  871. 1, minor);
  872. }
  873. #endif /* CONFIG_DEBUG_FS */