synclink_cs.c 109 KB

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  1. /*
  2. * linux/drivers/char/pcmcia/synclink_cs.c
  3. *
  4. * $Id: synclink_cs.c,v 4.34 2005/09/08 13:20:54 paulkf Exp $
  5. *
  6. * Device driver for Microgate SyncLink PC Card
  7. * multiprotocol serial adapter.
  8. *
  9. * written by Paul Fulghum for Microgate Corporation
  10. * paulkf@microgate.com
  11. *
  12. * Microgate and SyncLink are trademarks of Microgate Corporation
  13. *
  14. * This code is released under the GNU General Public License (GPL)
  15. *
  16. * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  17. * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  18. * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  19. * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
  20. * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  21. * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  22. * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  23. * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  24. * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  25. * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
  26. * OF THE POSSIBILITY OF SUCH DAMAGE.
  27. */
  28. #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq))
  29. #if defined(__i386__)
  30. # define BREAKPOINT() asm(" int $3");
  31. #else
  32. # define BREAKPOINT() { }
  33. #endif
  34. #define MAX_DEVICE_COUNT 4
  35. #include <linux/module.h>
  36. #include <linux/errno.h>
  37. #include <linux/signal.h>
  38. #include <linux/sched.h>
  39. #include <linux/timer.h>
  40. #include <linux/time.h>
  41. #include <linux/interrupt.h>
  42. #include <linux/tty.h>
  43. #include <linux/tty_flip.h>
  44. #include <linux/serial.h>
  45. #include <linux/major.h>
  46. #include <linux/string.h>
  47. #include <linux/fcntl.h>
  48. #include <linux/ptrace.h>
  49. #include <linux/ioport.h>
  50. #include <linux/mm.h>
  51. #include <linux/seq_file.h>
  52. #include <linux/slab.h>
  53. #include <linux/netdevice.h>
  54. #include <linux/vmalloc.h>
  55. #include <linux/init.h>
  56. #include <linux/delay.h>
  57. #include <linux/ioctl.h>
  58. #include <linux/synclink.h>
  59. #include <asm/io.h>
  60. #include <asm/irq.h>
  61. #include <asm/dma.h>
  62. #include <linux/bitops.h>
  63. #include <asm/types.h>
  64. #include <linux/termios.h>
  65. #include <linux/workqueue.h>
  66. #include <linux/hdlc.h>
  67. #include <pcmcia/cistpl.h>
  68. #include <pcmcia/cisreg.h>
  69. #include <pcmcia/ds.h>
  70. #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_CS_MODULE))
  71. #define SYNCLINK_GENERIC_HDLC 1
  72. #else
  73. #define SYNCLINK_GENERIC_HDLC 0
  74. #endif
  75. #define GET_USER(error,value,addr) error = get_user(value,addr)
  76. #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
  77. #define PUT_USER(error,value,addr) error = put_user(value,addr)
  78. #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
  79. #include <asm/uaccess.h>
  80. static MGSL_PARAMS default_params = {
  81. MGSL_MODE_HDLC, /* unsigned long mode */
  82. 0, /* unsigned char loopback; */
  83. HDLC_FLAG_UNDERRUN_ABORT15, /* unsigned short flags; */
  84. HDLC_ENCODING_NRZI_SPACE, /* unsigned char encoding; */
  85. 0, /* unsigned long clock_speed; */
  86. 0xff, /* unsigned char addr_filter; */
  87. HDLC_CRC_16_CCITT, /* unsigned short crc_type; */
  88. HDLC_PREAMBLE_LENGTH_8BITS, /* unsigned char preamble_length; */
  89. HDLC_PREAMBLE_PATTERN_NONE, /* unsigned char preamble; */
  90. 9600, /* unsigned long data_rate; */
  91. 8, /* unsigned char data_bits; */
  92. 1, /* unsigned char stop_bits; */
  93. ASYNC_PARITY_NONE /* unsigned char parity; */
  94. };
  95. typedef struct
  96. {
  97. int count;
  98. unsigned char status;
  99. char data[1];
  100. } RXBUF;
  101. /* The queue of BH actions to be performed */
  102. #define BH_RECEIVE 1
  103. #define BH_TRANSMIT 2
  104. #define BH_STATUS 4
  105. #define IO_PIN_SHUTDOWN_LIMIT 100
  106. #define RELEVANT_IFLAG(iflag) (iflag & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK))
  107. struct _input_signal_events {
  108. int ri_up;
  109. int ri_down;
  110. int dsr_up;
  111. int dsr_down;
  112. int dcd_up;
  113. int dcd_down;
  114. int cts_up;
  115. int cts_down;
  116. };
  117. /*
  118. * Device instance data structure
  119. */
  120. typedef struct _mgslpc_info {
  121. struct tty_port port;
  122. void *if_ptr; /* General purpose pointer (used by SPPP) */
  123. int magic;
  124. int line;
  125. struct mgsl_icount icount;
  126. int timeout;
  127. int x_char; /* xon/xoff character */
  128. unsigned char read_status_mask;
  129. unsigned char ignore_status_mask;
  130. unsigned char *tx_buf;
  131. int tx_put;
  132. int tx_get;
  133. int tx_count;
  134. /* circular list of fixed length rx buffers */
  135. unsigned char *rx_buf; /* memory allocated for all rx buffers */
  136. int rx_buf_total_size; /* size of memory allocated for rx buffers */
  137. int rx_put; /* index of next empty rx buffer */
  138. int rx_get; /* index of next full rx buffer */
  139. int rx_buf_size; /* size in bytes of single rx buffer */
  140. int rx_buf_count; /* total number of rx buffers */
  141. int rx_frame_count; /* number of full rx buffers */
  142. wait_queue_head_t status_event_wait_q;
  143. wait_queue_head_t event_wait_q;
  144. struct timer_list tx_timer; /* HDLC transmit timeout timer */
  145. struct _mgslpc_info *next_device; /* device list link */
  146. unsigned short imra_value;
  147. unsigned short imrb_value;
  148. unsigned char pim_value;
  149. spinlock_t lock;
  150. struct work_struct task; /* task structure for scheduling bh */
  151. u32 max_frame_size;
  152. u32 pending_bh;
  153. bool bh_running;
  154. bool bh_requested;
  155. int dcd_chkcount; /* check counts to prevent */
  156. int cts_chkcount; /* too many IRQs if a signal */
  157. int dsr_chkcount; /* is floating */
  158. int ri_chkcount;
  159. bool rx_enabled;
  160. bool rx_overflow;
  161. bool tx_enabled;
  162. bool tx_active;
  163. bool tx_aborting;
  164. u32 idle_mode;
  165. int if_mode; /* serial interface selection (RS-232, v.35 etc) */
  166. char device_name[25]; /* device instance name */
  167. unsigned int io_base; /* base I/O address of adapter */
  168. unsigned int irq_level;
  169. MGSL_PARAMS params; /* communications parameters */
  170. unsigned char serial_signals; /* current serial signal states */
  171. bool irq_occurred; /* for diagnostics use */
  172. char testing_irq;
  173. unsigned int init_error; /* startup error (DIAGS) */
  174. char *flag_buf;
  175. bool drop_rts_on_tx_done;
  176. struct _input_signal_events input_signal_events;
  177. /* PCMCIA support */
  178. struct pcmcia_device *p_dev;
  179. int stop;
  180. /* SPPP/Cisco HDLC device parts */
  181. int netcount;
  182. spinlock_t netlock;
  183. #if SYNCLINK_GENERIC_HDLC
  184. struct net_device *netdev;
  185. #endif
  186. } MGSLPC_INFO;
  187. #define MGSLPC_MAGIC 0x5402
  188. /*
  189. * The size of the serial xmit buffer is 1 page, or 4096 bytes
  190. */
  191. #define TXBUFSIZE 4096
  192. #define CHA 0x00 /* channel A offset */
  193. #define CHB 0x40 /* channel B offset */
  194. /*
  195. * FIXME: PPC has PVR defined in asm/reg.h. For now we just undef it.
  196. */
  197. #undef PVR
  198. #define RXFIFO 0
  199. #define TXFIFO 0
  200. #define STAR 0x20
  201. #define CMDR 0x20
  202. #define RSTA 0x21
  203. #define PRE 0x21
  204. #define MODE 0x22
  205. #define TIMR 0x23
  206. #define XAD1 0x24
  207. #define XAD2 0x25
  208. #define RAH1 0x26
  209. #define RAH2 0x27
  210. #define DAFO 0x27
  211. #define RAL1 0x28
  212. #define RFC 0x28
  213. #define RHCR 0x29
  214. #define RAL2 0x29
  215. #define RBCL 0x2a
  216. #define XBCL 0x2a
  217. #define RBCH 0x2b
  218. #define XBCH 0x2b
  219. #define CCR0 0x2c
  220. #define CCR1 0x2d
  221. #define CCR2 0x2e
  222. #define CCR3 0x2f
  223. #define VSTR 0x34
  224. #define BGR 0x34
  225. #define RLCR 0x35
  226. #define AML 0x36
  227. #define AMH 0x37
  228. #define GIS 0x38
  229. #define IVA 0x38
  230. #define IPC 0x39
  231. #define ISR 0x3a
  232. #define IMR 0x3a
  233. #define PVR 0x3c
  234. #define PIS 0x3d
  235. #define PIM 0x3d
  236. #define PCR 0x3e
  237. #define CCR4 0x3f
  238. // IMR/ISR
  239. #define IRQ_BREAK_ON BIT15 // rx break detected
  240. #define IRQ_DATAOVERRUN BIT14 // receive data overflow
  241. #define IRQ_ALLSENT BIT13 // all sent
  242. #define IRQ_UNDERRUN BIT12 // transmit data underrun
  243. #define IRQ_TIMER BIT11 // timer interrupt
  244. #define IRQ_CTS BIT10 // CTS status change
  245. #define IRQ_TXREPEAT BIT9 // tx message repeat
  246. #define IRQ_TXFIFO BIT8 // transmit pool ready
  247. #define IRQ_RXEOM BIT7 // receive message end
  248. #define IRQ_EXITHUNT BIT6 // receive frame start
  249. #define IRQ_RXTIME BIT6 // rx char timeout
  250. #define IRQ_DCD BIT2 // carrier detect status change
  251. #define IRQ_OVERRUN BIT1 // receive frame overflow
  252. #define IRQ_RXFIFO BIT0 // receive pool full
  253. // STAR
  254. #define XFW BIT6 // transmit FIFO write enable
  255. #define CEC BIT2 // command executing
  256. #define CTS BIT1 // CTS state
  257. #define PVR_DTR BIT0
  258. #define PVR_DSR BIT1
  259. #define PVR_RI BIT2
  260. #define PVR_AUTOCTS BIT3
  261. #define PVR_RS232 0x20 /* 0010b */
  262. #define PVR_V35 0xe0 /* 1110b */
  263. #define PVR_RS422 0x40 /* 0100b */
  264. /* Register access functions */
  265. #define write_reg(info, reg, val) outb((val),(info)->io_base + (reg))
  266. #define read_reg(info, reg) inb((info)->io_base + (reg))
  267. #define read_reg16(info, reg) inw((info)->io_base + (reg))
  268. #define write_reg16(info, reg, val) outw((val), (info)->io_base + (reg))
  269. #define set_reg_bits(info, reg, mask) \
  270. write_reg(info, (reg), \
  271. (unsigned char) (read_reg(info, (reg)) | (mask)))
  272. #define clear_reg_bits(info, reg, mask) \
  273. write_reg(info, (reg), \
  274. (unsigned char) (read_reg(info, (reg)) & ~(mask)))
  275. /*
  276. * interrupt enable/disable routines
  277. */
  278. static void irq_disable(MGSLPC_INFO *info, unsigned char channel, unsigned short mask)
  279. {
  280. if (channel == CHA) {
  281. info->imra_value |= mask;
  282. write_reg16(info, CHA + IMR, info->imra_value);
  283. } else {
  284. info->imrb_value |= mask;
  285. write_reg16(info, CHB + IMR, info->imrb_value);
  286. }
  287. }
  288. static void irq_enable(MGSLPC_INFO *info, unsigned char channel, unsigned short mask)
  289. {
  290. if (channel == CHA) {
  291. info->imra_value &= ~mask;
  292. write_reg16(info, CHA + IMR, info->imra_value);
  293. } else {
  294. info->imrb_value &= ~mask;
  295. write_reg16(info, CHB + IMR, info->imrb_value);
  296. }
  297. }
  298. #define port_irq_disable(info, mask) \
  299. { info->pim_value |= (mask); write_reg(info, PIM, info->pim_value); }
  300. #define port_irq_enable(info, mask) \
  301. { info->pim_value &= ~(mask); write_reg(info, PIM, info->pim_value); }
  302. static void rx_start(MGSLPC_INFO *info);
  303. static void rx_stop(MGSLPC_INFO *info);
  304. static void tx_start(MGSLPC_INFO *info, struct tty_struct *tty);
  305. static void tx_stop(MGSLPC_INFO *info);
  306. static void tx_set_idle(MGSLPC_INFO *info);
  307. static void get_signals(MGSLPC_INFO *info);
  308. static void set_signals(MGSLPC_INFO *info);
  309. static void reset_device(MGSLPC_INFO *info);
  310. static void hdlc_mode(MGSLPC_INFO *info);
  311. static void async_mode(MGSLPC_INFO *info);
  312. static void tx_timeout(unsigned long context);
  313. static int carrier_raised(struct tty_port *port);
  314. static void dtr_rts(struct tty_port *port, int onoff);
  315. #if SYNCLINK_GENERIC_HDLC
  316. #define dev_to_port(D) (dev_to_hdlc(D)->priv)
  317. static void hdlcdev_tx_done(MGSLPC_INFO *info);
  318. static void hdlcdev_rx(MGSLPC_INFO *info, char *buf, int size);
  319. static int hdlcdev_init(MGSLPC_INFO *info);
  320. static void hdlcdev_exit(MGSLPC_INFO *info);
  321. #endif
  322. static void trace_block(MGSLPC_INFO *info,const char* data, int count, int xmit);
  323. static bool register_test(MGSLPC_INFO *info);
  324. static bool irq_test(MGSLPC_INFO *info);
  325. static int adapter_test(MGSLPC_INFO *info);
  326. static int claim_resources(MGSLPC_INFO *info);
  327. static void release_resources(MGSLPC_INFO *info);
  328. static void mgslpc_add_device(MGSLPC_INFO *info);
  329. static void mgslpc_remove_device(MGSLPC_INFO *info);
  330. static bool rx_get_frame(MGSLPC_INFO *info, struct tty_struct *tty);
  331. static void rx_reset_buffers(MGSLPC_INFO *info);
  332. static int rx_alloc_buffers(MGSLPC_INFO *info);
  333. static void rx_free_buffers(MGSLPC_INFO *info);
  334. static irqreturn_t mgslpc_isr(int irq, void *dev_id);
  335. /*
  336. * Bottom half interrupt handlers
  337. */
  338. static void bh_handler(struct work_struct *work);
  339. static void bh_transmit(MGSLPC_INFO *info, struct tty_struct *tty);
  340. static void bh_status(MGSLPC_INFO *info);
  341. /*
  342. * ioctl handlers
  343. */
  344. static int tiocmget(struct tty_struct *tty);
  345. static int tiocmset(struct tty_struct *tty,
  346. unsigned int set, unsigned int clear);
  347. static int get_stats(MGSLPC_INFO *info, struct mgsl_icount __user *user_icount);
  348. static int get_params(MGSLPC_INFO *info, MGSL_PARAMS __user *user_params);
  349. static int set_params(MGSLPC_INFO *info, MGSL_PARAMS __user *new_params, struct tty_struct *tty);
  350. static int get_txidle(MGSLPC_INFO *info, int __user *idle_mode);
  351. static int set_txidle(MGSLPC_INFO *info, int idle_mode);
  352. static int set_txenable(MGSLPC_INFO *info, int enable, struct tty_struct *tty);
  353. static int tx_abort(MGSLPC_INFO *info);
  354. static int set_rxenable(MGSLPC_INFO *info, int enable);
  355. static int wait_events(MGSLPC_INFO *info, int __user *mask);
  356. static MGSLPC_INFO *mgslpc_device_list = NULL;
  357. static int mgslpc_device_count = 0;
  358. /*
  359. * Set this param to non-zero to load eax with the
  360. * .text section address and breakpoint on module load.
  361. * This is useful for use with gdb and add-symbol-file command.
  362. */
  363. static bool break_on_load=0;
  364. /*
  365. * Driver major number, defaults to zero to get auto
  366. * assigned major number. May be forced as module parameter.
  367. */
  368. static int ttymajor=0;
  369. static int debug_level = 0;
  370. static int maxframe[MAX_DEVICE_COUNT] = {0,};
  371. module_param(break_on_load, bool, 0);
  372. module_param(ttymajor, int, 0);
  373. module_param(debug_level, int, 0);
  374. module_param_array(maxframe, int, NULL, 0);
  375. MODULE_LICENSE("GPL");
  376. static char *driver_name = "SyncLink PC Card driver";
  377. static char *driver_version = "$Revision: 4.34 $";
  378. static struct tty_driver *serial_driver;
  379. /* number of characters left in xmit buffer before we ask for more */
  380. #define WAKEUP_CHARS 256
  381. static void mgslpc_change_params(MGSLPC_INFO *info, struct tty_struct *tty);
  382. static void mgslpc_wait_until_sent(struct tty_struct *tty, int timeout);
  383. /* PCMCIA prototypes */
  384. static int mgslpc_config(struct pcmcia_device *link);
  385. static void mgslpc_release(u_long arg);
  386. static void mgslpc_detach(struct pcmcia_device *p_dev);
  387. /*
  388. * 1st function defined in .text section. Calling this function in
  389. * init_module() followed by a breakpoint allows a remote debugger
  390. * (gdb) to get the .text address for the add-symbol-file command.
  391. * This allows remote debugging of dynamically loadable modules.
  392. */
  393. static void* mgslpc_get_text_ptr(void)
  394. {
  395. return mgslpc_get_text_ptr;
  396. }
  397. /**
  398. * line discipline callback wrappers
  399. *
  400. * The wrappers maintain line discipline references
  401. * while calling into the line discipline.
  402. *
  403. * ldisc_receive_buf - pass receive data to line discipline
  404. */
  405. static void ldisc_receive_buf(struct tty_struct *tty,
  406. const __u8 *data, char *flags, int count)
  407. {
  408. struct tty_ldisc *ld;
  409. if (!tty)
  410. return;
  411. ld = tty_ldisc_ref(tty);
  412. if (ld) {
  413. if (ld->ops->receive_buf)
  414. ld->ops->receive_buf(tty, data, flags, count);
  415. tty_ldisc_deref(ld);
  416. }
  417. }
  418. static const struct tty_port_operations mgslpc_port_ops = {
  419. .carrier_raised = carrier_raised,
  420. .dtr_rts = dtr_rts
  421. };
  422. static int mgslpc_probe(struct pcmcia_device *link)
  423. {
  424. MGSLPC_INFO *info;
  425. int ret;
  426. if (debug_level >= DEBUG_LEVEL_INFO)
  427. printk("mgslpc_attach\n");
  428. info = kzalloc(sizeof(MGSLPC_INFO), GFP_KERNEL);
  429. if (!info) {
  430. printk("Error can't allocate device instance data\n");
  431. return -ENOMEM;
  432. }
  433. info->magic = MGSLPC_MAGIC;
  434. tty_port_init(&info->port);
  435. info->port.ops = &mgslpc_port_ops;
  436. INIT_WORK(&info->task, bh_handler);
  437. info->max_frame_size = 4096;
  438. info->port.close_delay = 5*HZ/10;
  439. info->port.closing_wait = 30*HZ;
  440. init_waitqueue_head(&info->status_event_wait_q);
  441. init_waitqueue_head(&info->event_wait_q);
  442. spin_lock_init(&info->lock);
  443. spin_lock_init(&info->netlock);
  444. memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
  445. info->idle_mode = HDLC_TXIDLE_FLAGS;
  446. info->imra_value = 0xffff;
  447. info->imrb_value = 0xffff;
  448. info->pim_value = 0xff;
  449. info->p_dev = link;
  450. link->priv = info;
  451. /* Initialize the struct pcmcia_device structure */
  452. ret = mgslpc_config(link);
  453. if (ret) {
  454. tty_port_destroy(&info->port);
  455. return ret;
  456. }
  457. mgslpc_add_device(info);
  458. return 0;
  459. }
  460. /* Card has been inserted.
  461. */
  462. static int mgslpc_ioprobe(struct pcmcia_device *p_dev, void *priv_data)
  463. {
  464. return pcmcia_request_io(p_dev);
  465. }
  466. static int mgslpc_config(struct pcmcia_device *link)
  467. {
  468. MGSLPC_INFO *info = link->priv;
  469. int ret;
  470. if (debug_level >= DEBUG_LEVEL_INFO)
  471. printk("mgslpc_config(0x%p)\n", link);
  472. link->config_flags |= CONF_ENABLE_IRQ | CONF_AUTO_SET_IO;
  473. ret = pcmcia_loop_config(link, mgslpc_ioprobe, NULL);
  474. if (ret != 0)
  475. goto failed;
  476. link->config_index = 8;
  477. link->config_regs = PRESENT_OPTION;
  478. ret = pcmcia_request_irq(link, mgslpc_isr);
  479. if (ret)
  480. goto failed;
  481. ret = pcmcia_enable_device(link);
  482. if (ret)
  483. goto failed;
  484. info->io_base = link->resource[0]->start;
  485. info->irq_level = link->irq;
  486. return 0;
  487. failed:
  488. mgslpc_release((u_long)link);
  489. return -ENODEV;
  490. }
  491. /* Card has been removed.
  492. * Unregister device and release PCMCIA configuration.
  493. * If device is open, postpone until it is closed.
  494. */
  495. static void mgslpc_release(u_long arg)
  496. {
  497. struct pcmcia_device *link = (struct pcmcia_device *)arg;
  498. if (debug_level >= DEBUG_LEVEL_INFO)
  499. printk("mgslpc_release(0x%p)\n", link);
  500. pcmcia_disable_device(link);
  501. }
  502. static void mgslpc_detach(struct pcmcia_device *link)
  503. {
  504. if (debug_level >= DEBUG_LEVEL_INFO)
  505. printk("mgslpc_detach(0x%p)\n", link);
  506. ((MGSLPC_INFO *)link->priv)->stop = 1;
  507. mgslpc_release((u_long)link);
  508. mgslpc_remove_device((MGSLPC_INFO *)link->priv);
  509. }
  510. static int mgslpc_suspend(struct pcmcia_device *link)
  511. {
  512. MGSLPC_INFO *info = link->priv;
  513. info->stop = 1;
  514. return 0;
  515. }
  516. static int mgslpc_resume(struct pcmcia_device *link)
  517. {
  518. MGSLPC_INFO *info = link->priv;
  519. info->stop = 0;
  520. return 0;
  521. }
  522. static inline bool mgslpc_paranoia_check(MGSLPC_INFO *info,
  523. char *name, const char *routine)
  524. {
  525. #ifdef MGSLPC_PARANOIA_CHECK
  526. static const char *badmagic =
  527. "Warning: bad magic number for mgsl struct (%s) in %s\n";
  528. static const char *badinfo =
  529. "Warning: null mgslpc_info for (%s) in %s\n";
  530. if (!info) {
  531. printk(badinfo, name, routine);
  532. return true;
  533. }
  534. if (info->magic != MGSLPC_MAGIC) {
  535. printk(badmagic, name, routine);
  536. return true;
  537. }
  538. #else
  539. if (!info)
  540. return true;
  541. #endif
  542. return false;
  543. }
  544. #define CMD_RXFIFO BIT7 // release current rx FIFO
  545. #define CMD_RXRESET BIT6 // receiver reset
  546. #define CMD_RXFIFO_READ BIT5
  547. #define CMD_START_TIMER BIT4
  548. #define CMD_TXFIFO BIT3 // release current tx FIFO
  549. #define CMD_TXEOM BIT1 // transmit end message
  550. #define CMD_TXRESET BIT0 // transmit reset
  551. static bool wait_command_complete(MGSLPC_INFO *info, unsigned char channel)
  552. {
  553. int i = 0;
  554. /* wait for command completion */
  555. while (read_reg(info, (unsigned char)(channel+STAR)) & BIT2) {
  556. udelay(1);
  557. if (i++ == 1000)
  558. return false;
  559. }
  560. return true;
  561. }
  562. static void issue_command(MGSLPC_INFO *info, unsigned char channel, unsigned char cmd)
  563. {
  564. wait_command_complete(info, channel);
  565. write_reg(info, (unsigned char) (channel + CMDR), cmd);
  566. }
  567. static void tx_pause(struct tty_struct *tty)
  568. {
  569. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  570. unsigned long flags;
  571. if (mgslpc_paranoia_check(info, tty->name, "tx_pause"))
  572. return;
  573. if (debug_level >= DEBUG_LEVEL_INFO)
  574. printk("tx_pause(%s)\n",info->device_name);
  575. spin_lock_irqsave(&info->lock,flags);
  576. if (info->tx_enabled)
  577. tx_stop(info);
  578. spin_unlock_irqrestore(&info->lock,flags);
  579. }
  580. static void tx_release(struct tty_struct *tty)
  581. {
  582. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  583. unsigned long flags;
  584. if (mgslpc_paranoia_check(info, tty->name, "tx_release"))
  585. return;
  586. if (debug_level >= DEBUG_LEVEL_INFO)
  587. printk("tx_release(%s)\n",info->device_name);
  588. spin_lock_irqsave(&info->lock,flags);
  589. if (!info->tx_enabled)
  590. tx_start(info, tty);
  591. spin_unlock_irqrestore(&info->lock,flags);
  592. }
  593. /* Return next bottom half action to perform.
  594. * or 0 if nothing to do.
  595. */
  596. static int bh_action(MGSLPC_INFO *info)
  597. {
  598. unsigned long flags;
  599. int rc = 0;
  600. spin_lock_irqsave(&info->lock,flags);
  601. if (info->pending_bh & BH_RECEIVE) {
  602. info->pending_bh &= ~BH_RECEIVE;
  603. rc = BH_RECEIVE;
  604. } else if (info->pending_bh & BH_TRANSMIT) {
  605. info->pending_bh &= ~BH_TRANSMIT;
  606. rc = BH_TRANSMIT;
  607. } else if (info->pending_bh & BH_STATUS) {
  608. info->pending_bh &= ~BH_STATUS;
  609. rc = BH_STATUS;
  610. }
  611. if (!rc) {
  612. /* Mark BH routine as complete */
  613. info->bh_running = false;
  614. info->bh_requested = false;
  615. }
  616. spin_unlock_irqrestore(&info->lock,flags);
  617. return rc;
  618. }
  619. static void bh_handler(struct work_struct *work)
  620. {
  621. MGSLPC_INFO *info = container_of(work, MGSLPC_INFO, task);
  622. struct tty_struct *tty;
  623. int action;
  624. if (!info)
  625. return;
  626. if (debug_level >= DEBUG_LEVEL_BH)
  627. printk( "%s(%d):bh_handler(%s) entry\n",
  628. __FILE__,__LINE__,info->device_name);
  629. info->bh_running = true;
  630. tty = tty_port_tty_get(&info->port);
  631. while((action = bh_action(info)) != 0) {
  632. /* Process work item */
  633. if ( debug_level >= DEBUG_LEVEL_BH )
  634. printk( "%s(%d):bh_handler() work item action=%d\n",
  635. __FILE__,__LINE__,action);
  636. switch (action) {
  637. case BH_RECEIVE:
  638. while(rx_get_frame(info, tty));
  639. break;
  640. case BH_TRANSMIT:
  641. bh_transmit(info, tty);
  642. break;
  643. case BH_STATUS:
  644. bh_status(info);
  645. break;
  646. default:
  647. /* unknown work item ID */
  648. printk("Unknown work item ID=%08X!\n", action);
  649. break;
  650. }
  651. }
  652. tty_kref_put(tty);
  653. if (debug_level >= DEBUG_LEVEL_BH)
  654. printk( "%s(%d):bh_handler(%s) exit\n",
  655. __FILE__,__LINE__,info->device_name);
  656. }
  657. static void bh_transmit(MGSLPC_INFO *info, struct tty_struct *tty)
  658. {
  659. if (debug_level >= DEBUG_LEVEL_BH)
  660. printk("bh_transmit() entry on %s\n", info->device_name);
  661. if (tty)
  662. tty_wakeup(tty);
  663. }
  664. static void bh_status(MGSLPC_INFO *info)
  665. {
  666. info->ri_chkcount = 0;
  667. info->dsr_chkcount = 0;
  668. info->dcd_chkcount = 0;
  669. info->cts_chkcount = 0;
  670. }
  671. /* eom: non-zero = end of frame */
  672. static void rx_ready_hdlc(MGSLPC_INFO *info, int eom)
  673. {
  674. unsigned char data[2];
  675. unsigned char fifo_count, read_count, i;
  676. RXBUF *buf = (RXBUF*)(info->rx_buf + (info->rx_put * info->rx_buf_size));
  677. if (debug_level >= DEBUG_LEVEL_ISR)
  678. printk("%s(%d):rx_ready_hdlc(eom=%d)\n",__FILE__,__LINE__,eom);
  679. if (!info->rx_enabled)
  680. return;
  681. if (info->rx_frame_count >= info->rx_buf_count) {
  682. /* no more free buffers */
  683. issue_command(info, CHA, CMD_RXRESET);
  684. info->pending_bh |= BH_RECEIVE;
  685. info->rx_overflow = true;
  686. info->icount.buf_overrun++;
  687. return;
  688. }
  689. if (eom) {
  690. /* end of frame, get FIFO count from RBCL register */
  691. if (!(fifo_count = (unsigned char)(read_reg(info, CHA+RBCL) & 0x1f)))
  692. fifo_count = 32;
  693. } else
  694. fifo_count = 32;
  695. do {
  696. if (fifo_count == 1) {
  697. read_count = 1;
  698. data[0] = read_reg(info, CHA + RXFIFO);
  699. } else {
  700. read_count = 2;
  701. *((unsigned short *) data) = read_reg16(info, CHA + RXFIFO);
  702. }
  703. fifo_count -= read_count;
  704. if (!fifo_count && eom)
  705. buf->status = data[--read_count];
  706. for (i = 0; i < read_count; i++) {
  707. if (buf->count >= info->max_frame_size) {
  708. /* frame too large, reset receiver and reset current buffer */
  709. issue_command(info, CHA, CMD_RXRESET);
  710. buf->count = 0;
  711. return;
  712. }
  713. *(buf->data + buf->count) = data[i];
  714. buf->count++;
  715. }
  716. } while (fifo_count);
  717. if (eom) {
  718. info->pending_bh |= BH_RECEIVE;
  719. info->rx_frame_count++;
  720. info->rx_put++;
  721. if (info->rx_put >= info->rx_buf_count)
  722. info->rx_put = 0;
  723. }
  724. issue_command(info, CHA, CMD_RXFIFO);
  725. }
  726. static void rx_ready_async(MGSLPC_INFO *info, int tcd, struct tty_struct *tty)
  727. {
  728. unsigned char data, status, flag;
  729. int fifo_count;
  730. int work = 0;
  731. struct mgsl_icount *icount = &info->icount;
  732. if (!tty) {
  733. /* tty is not available anymore */
  734. issue_command(info, CHA, CMD_RXRESET);
  735. if (debug_level >= DEBUG_LEVEL_ISR)
  736. printk("%s(%d):rx_ready_async(tty=NULL)\n",__FILE__,__LINE__);
  737. return;
  738. }
  739. if (tcd) {
  740. /* early termination, get FIFO count from RBCL register */
  741. fifo_count = (unsigned char)(read_reg(info, CHA+RBCL) & 0x1f);
  742. /* Zero fifo count could mean 0 or 32 bytes available.
  743. * If BIT5 of STAR is set then at least 1 byte is available.
  744. */
  745. if (!fifo_count && (read_reg(info,CHA+STAR) & BIT5))
  746. fifo_count = 32;
  747. } else
  748. fifo_count = 32;
  749. tty_buffer_request_room(tty, fifo_count);
  750. /* Flush received async data to receive data buffer. */
  751. while (fifo_count) {
  752. data = read_reg(info, CHA + RXFIFO);
  753. status = read_reg(info, CHA + RXFIFO);
  754. fifo_count -= 2;
  755. icount->rx++;
  756. flag = TTY_NORMAL;
  757. // if no frameing/crc error then save data
  758. // BIT7:parity error
  759. // BIT6:framing error
  760. if (status & (BIT7 + BIT6)) {
  761. if (status & BIT7)
  762. icount->parity++;
  763. else
  764. icount->frame++;
  765. /* discard char if tty control flags say so */
  766. if (status & info->ignore_status_mask)
  767. continue;
  768. status &= info->read_status_mask;
  769. if (status & BIT7)
  770. flag = TTY_PARITY;
  771. else if (status & BIT6)
  772. flag = TTY_FRAME;
  773. }
  774. work += tty_insert_flip_char(tty, data, flag);
  775. }
  776. issue_command(info, CHA, CMD_RXFIFO);
  777. if (debug_level >= DEBUG_LEVEL_ISR) {
  778. printk("%s(%d):rx_ready_async",
  779. __FILE__,__LINE__);
  780. printk("%s(%d):rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
  781. __FILE__,__LINE__,icount->rx,icount->brk,
  782. icount->parity,icount->frame,icount->overrun);
  783. }
  784. if (work)
  785. tty_flip_buffer_push(tty);
  786. }
  787. static void tx_done(MGSLPC_INFO *info, struct tty_struct *tty)
  788. {
  789. if (!info->tx_active)
  790. return;
  791. info->tx_active = false;
  792. info->tx_aborting = false;
  793. if (info->params.mode == MGSL_MODE_ASYNC)
  794. return;
  795. info->tx_count = info->tx_put = info->tx_get = 0;
  796. del_timer(&info->tx_timer);
  797. if (info->drop_rts_on_tx_done) {
  798. get_signals(info);
  799. if (info->serial_signals & SerialSignal_RTS) {
  800. info->serial_signals &= ~SerialSignal_RTS;
  801. set_signals(info);
  802. }
  803. info->drop_rts_on_tx_done = false;
  804. }
  805. #if SYNCLINK_GENERIC_HDLC
  806. if (info->netcount)
  807. hdlcdev_tx_done(info);
  808. else
  809. #endif
  810. {
  811. if (tty && (tty->stopped || tty->hw_stopped)) {
  812. tx_stop(info);
  813. return;
  814. }
  815. info->pending_bh |= BH_TRANSMIT;
  816. }
  817. }
  818. static void tx_ready(MGSLPC_INFO *info, struct tty_struct *tty)
  819. {
  820. unsigned char fifo_count = 32;
  821. int c;
  822. if (debug_level >= DEBUG_LEVEL_ISR)
  823. printk("%s(%d):tx_ready(%s)\n", __FILE__,__LINE__,info->device_name);
  824. if (info->params.mode == MGSL_MODE_HDLC) {
  825. if (!info->tx_active)
  826. return;
  827. } else {
  828. if (tty && (tty->stopped || tty->hw_stopped)) {
  829. tx_stop(info);
  830. return;
  831. }
  832. if (!info->tx_count)
  833. info->tx_active = false;
  834. }
  835. if (!info->tx_count)
  836. return;
  837. while (info->tx_count && fifo_count) {
  838. c = min(2, min_t(int, fifo_count, min(info->tx_count, TXBUFSIZE - info->tx_get)));
  839. if (c == 1) {
  840. write_reg(info, CHA + TXFIFO, *(info->tx_buf + info->tx_get));
  841. } else {
  842. write_reg16(info, CHA + TXFIFO,
  843. *((unsigned short*)(info->tx_buf + info->tx_get)));
  844. }
  845. info->tx_count -= c;
  846. info->tx_get = (info->tx_get + c) & (TXBUFSIZE - 1);
  847. fifo_count -= c;
  848. }
  849. if (info->params.mode == MGSL_MODE_ASYNC) {
  850. if (info->tx_count < WAKEUP_CHARS)
  851. info->pending_bh |= BH_TRANSMIT;
  852. issue_command(info, CHA, CMD_TXFIFO);
  853. } else {
  854. if (info->tx_count)
  855. issue_command(info, CHA, CMD_TXFIFO);
  856. else
  857. issue_command(info, CHA, CMD_TXFIFO + CMD_TXEOM);
  858. }
  859. }
  860. static void cts_change(MGSLPC_INFO *info, struct tty_struct *tty)
  861. {
  862. get_signals(info);
  863. if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
  864. irq_disable(info, CHB, IRQ_CTS);
  865. info->icount.cts++;
  866. if (info->serial_signals & SerialSignal_CTS)
  867. info->input_signal_events.cts_up++;
  868. else
  869. info->input_signal_events.cts_down++;
  870. wake_up_interruptible(&info->status_event_wait_q);
  871. wake_up_interruptible(&info->event_wait_q);
  872. if (tty && tty_port_cts_enabled(&info->port)) {
  873. if (tty->hw_stopped) {
  874. if (info->serial_signals & SerialSignal_CTS) {
  875. if (debug_level >= DEBUG_LEVEL_ISR)
  876. printk("CTS tx start...");
  877. tty->hw_stopped = 0;
  878. tx_start(info, tty);
  879. info->pending_bh |= BH_TRANSMIT;
  880. return;
  881. }
  882. } else {
  883. if (!(info->serial_signals & SerialSignal_CTS)) {
  884. if (debug_level >= DEBUG_LEVEL_ISR)
  885. printk("CTS tx stop...");
  886. tty->hw_stopped = 1;
  887. tx_stop(info);
  888. }
  889. }
  890. }
  891. info->pending_bh |= BH_STATUS;
  892. }
  893. static void dcd_change(MGSLPC_INFO *info, struct tty_struct *tty)
  894. {
  895. get_signals(info);
  896. if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
  897. irq_disable(info, CHB, IRQ_DCD);
  898. info->icount.dcd++;
  899. if (info->serial_signals & SerialSignal_DCD) {
  900. info->input_signal_events.dcd_up++;
  901. }
  902. else
  903. info->input_signal_events.dcd_down++;
  904. #if SYNCLINK_GENERIC_HDLC
  905. if (info->netcount) {
  906. if (info->serial_signals & SerialSignal_DCD)
  907. netif_carrier_on(info->netdev);
  908. else
  909. netif_carrier_off(info->netdev);
  910. }
  911. #endif
  912. wake_up_interruptible(&info->status_event_wait_q);
  913. wake_up_interruptible(&info->event_wait_q);
  914. if (info->port.flags & ASYNC_CHECK_CD) {
  915. if (debug_level >= DEBUG_LEVEL_ISR)
  916. printk("%s CD now %s...", info->device_name,
  917. (info->serial_signals & SerialSignal_DCD) ? "on" : "off");
  918. if (info->serial_signals & SerialSignal_DCD)
  919. wake_up_interruptible(&info->port.open_wait);
  920. else {
  921. if (debug_level >= DEBUG_LEVEL_ISR)
  922. printk("doing serial hangup...");
  923. if (tty)
  924. tty_hangup(tty);
  925. }
  926. }
  927. info->pending_bh |= BH_STATUS;
  928. }
  929. static void dsr_change(MGSLPC_INFO *info)
  930. {
  931. get_signals(info);
  932. if ((info->dsr_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
  933. port_irq_disable(info, PVR_DSR);
  934. info->icount.dsr++;
  935. if (info->serial_signals & SerialSignal_DSR)
  936. info->input_signal_events.dsr_up++;
  937. else
  938. info->input_signal_events.dsr_down++;
  939. wake_up_interruptible(&info->status_event_wait_q);
  940. wake_up_interruptible(&info->event_wait_q);
  941. info->pending_bh |= BH_STATUS;
  942. }
  943. static void ri_change(MGSLPC_INFO *info)
  944. {
  945. get_signals(info);
  946. if ((info->ri_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
  947. port_irq_disable(info, PVR_RI);
  948. info->icount.rng++;
  949. if (info->serial_signals & SerialSignal_RI)
  950. info->input_signal_events.ri_up++;
  951. else
  952. info->input_signal_events.ri_down++;
  953. wake_up_interruptible(&info->status_event_wait_q);
  954. wake_up_interruptible(&info->event_wait_q);
  955. info->pending_bh |= BH_STATUS;
  956. }
  957. /* Interrupt service routine entry point.
  958. *
  959. * Arguments:
  960. *
  961. * irq interrupt number that caused interrupt
  962. * dev_id device ID supplied during interrupt registration
  963. */
  964. static irqreturn_t mgslpc_isr(int dummy, void *dev_id)
  965. {
  966. MGSLPC_INFO *info = dev_id;
  967. struct tty_struct *tty;
  968. unsigned short isr;
  969. unsigned char gis, pis;
  970. int count=0;
  971. if (debug_level >= DEBUG_LEVEL_ISR)
  972. printk("mgslpc_isr(%d) entry.\n", info->irq_level);
  973. if (!(info->p_dev->_locked))
  974. return IRQ_HANDLED;
  975. tty = tty_port_tty_get(&info->port);
  976. spin_lock(&info->lock);
  977. while ((gis = read_reg(info, CHA + GIS))) {
  978. if (debug_level >= DEBUG_LEVEL_ISR)
  979. printk("mgslpc_isr %s gis=%04X\n", info->device_name,gis);
  980. if ((gis & 0x70) || count > 1000) {
  981. printk("synclink_cs:hardware failed or ejected\n");
  982. break;
  983. }
  984. count++;
  985. if (gis & (BIT1 + BIT0)) {
  986. isr = read_reg16(info, CHB + ISR);
  987. if (isr & IRQ_DCD)
  988. dcd_change(info, tty);
  989. if (isr & IRQ_CTS)
  990. cts_change(info, tty);
  991. }
  992. if (gis & (BIT3 + BIT2))
  993. {
  994. isr = read_reg16(info, CHA + ISR);
  995. if (isr & IRQ_TIMER) {
  996. info->irq_occurred = true;
  997. irq_disable(info, CHA, IRQ_TIMER);
  998. }
  999. /* receive IRQs */
  1000. if (isr & IRQ_EXITHUNT) {
  1001. info->icount.exithunt++;
  1002. wake_up_interruptible(&info->event_wait_q);
  1003. }
  1004. if (isr & IRQ_BREAK_ON) {
  1005. info->icount.brk++;
  1006. if (info->port.flags & ASYNC_SAK)
  1007. do_SAK(tty);
  1008. }
  1009. if (isr & IRQ_RXTIME) {
  1010. issue_command(info, CHA, CMD_RXFIFO_READ);
  1011. }
  1012. if (isr & (IRQ_RXEOM + IRQ_RXFIFO)) {
  1013. if (info->params.mode == MGSL_MODE_HDLC)
  1014. rx_ready_hdlc(info, isr & IRQ_RXEOM);
  1015. else
  1016. rx_ready_async(info, isr & IRQ_RXEOM, tty);
  1017. }
  1018. /* transmit IRQs */
  1019. if (isr & IRQ_UNDERRUN) {
  1020. if (info->tx_aborting)
  1021. info->icount.txabort++;
  1022. else
  1023. info->icount.txunder++;
  1024. tx_done(info, tty);
  1025. }
  1026. else if (isr & IRQ_ALLSENT) {
  1027. info->icount.txok++;
  1028. tx_done(info, tty);
  1029. }
  1030. else if (isr & IRQ_TXFIFO)
  1031. tx_ready(info, tty);
  1032. }
  1033. if (gis & BIT7) {
  1034. pis = read_reg(info, CHA + PIS);
  1035. if (pis & BIT1)
  1036. dsr_change(info);
  1037. if (pis & BIT2)
  1038. ri_change(info);
  1039. }
  1040. }
  1041. /* Request bottom half processing if there's something
  1042. * for it to do and the bh is not already running
  1043. */
  1044. if (info->pending_bh && !info->bh_running && !info->bh_requested) {
  1045. if ( debug_level >= DEBUG_LEVEL_ISR )
  1046. printk("%s(%d):%s queueing bh task.\n",
  1047. __FILE__,__LINE__,info->device_name);
  1048. schedule_work(&info->task);
  1049. info->bh_requested = true;
  1050. }
  1051. spin_unlock(&info->lock);
  1052. tty_kref_put(tty);
  1053. if (debug_level >= DEBUG_LEVEL_ISR)
  1054. printk("%s(%d):mgslpc_isr(%d)exit.\n",
  1055. __FILE__, __LINE__, info->irq_level);
  1056. return IRQ_HANDLED;
  1057. }
  1058. /* Initialize and start device.
  1059. */
  1060. static int startup(MGSLPC_INFO * info, struct tty_struct *tty)
  1061. {
  1062. int retval = 0;
  1063. if (debug_level >= DEBUG_LEVEL_INFO)
  1064. printk("%s(%d):startup(%s)\n",__FILE__,__LINE__,info->device_name);
  1065. if (info->port.flags & ASYNC_INITIALIZED)
  1066. return 0;
  1067. if (!info->tx_buf) {
  1068. /* allocate a page of memory for a transmit buffer */
  1069. info->tx_buf = (unsigned char *)get_zeroed_page(GFP_KERNEL);
  1070. if (!info->tx_buf) {
  1071. printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n",
  1072. __FILE__,__LINE__,info->device_name);
  1073. return -ENOMEM;
  1074. }
  1075. }
  1076. info->pending_bh = 0;
  1077. memset(&info->icount, 0, sizeof(info->icount));
  1078. setup_timer(&info->tx_timer, tx_timeout, (unsigned long)info);
  1079. /* Allocate and claim adapter resources */
  1080. retval = claim_resources(info);
  1081. /* perform existence check and diagnostics */
  1082. if ( !retval )
  1083. retval = adapter_test(info);
  1084. if ( retval ) {
  1085. if (capable(CAP_SYS_ADMIN) && tty)
  1086. set_bit(TTY_IO_ERROR, &tty->flags);
  1087. release_resources(info);
  1088. return retval;
  1089. }
  1090. /* program hardware for current parameters */
  1091. mgslpc_change_params(info, tty);
  1092. if (tty)
  1093. clear_bit(TTY_IO_ERROR, &tty->flags);
  1094. info->port.flags |= ASYNC_INITIALIZED;
  1095. return 0;
  1096. }
  1097. /* Called by mgslpc_close() and mgslpc_hangup() to shutdown hardware
  1098. */
  1099. static void shutdown(MGSLPC_INFO * info, struct tty_struct *tty)
  1100. {
  1101. unsigned long flags;
  1102. if (!(info->port.flags & ASYNC_INITIALIZED))
  1103. return;
  1104. if (debug_level >= DEBUG_LEVEL_INFO)
  1105. printk("%s(%d):mgslpc_shutdown(%s)\n",
  1106. __FILE__,__LINE__, info->device_name );
  1107. /* clear status wait queue because status changes */
  1108. /* can't happen after shutting down the hardware */
  1109. wake_up_interruptible(&info->status_event_wait_q);
  1110. wake_up_interruptible(&info->event_wait_q);
  1111. del_timer_sync(&info->tx_timer);
  1112. if (info->tx_buf) {
  1113. free_page((unsigned long) info->tx_buf);
  1114. info->tx_buf = NULL;
  1115. }
  1116. spin_lock_irqsave(&info->lock,flags);
  1117. rx_stop(info);
  1118. tx_stop(info);
  1119. /* TODO:disable interrupts instead of reset to preserve signal states */
  1120. reset_device(info);
  1121. if (!tty || tty->termios.c_cflag & HUPCL) {
  1122. info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
  1123. set_signals(info);
  1124. }
  1125. spin_unlock_irqrestore(&info->lock,flags);
  1126. release_resources(info);
  1127. if (tty)
  1128. set_bit(TTY_IO_ERROR, &tty->flags);
  1129. info->port.flags &= ~ASYNC_INITIALIZED;
  1130. }
  1131. static void mgslpc_program_hw(MGSLPC_INFO *info, struct tty_struct *tty)
  1132. {
  1133. unsigned long flags;
  1134. spin_lock_irqsave(&info->lock,flags);
  1135. rx_stop(info);
  1136. tx_stop(info);
  1137. info->tx_count = info->tx_put = info->tx_get = 0;
  1138. if (info->params.mode == MGSL_MODE_HDLC || info->netcount)
  1139. hdlc_mode(info);
  1140. else
  1141. async_mode(info);
  1142. set_signals(info);
  1143. info->dcd_chkcount = 0;
  1144. info->cts_chkcount = 0;
  1145. info->ri_chkcount = 0;
  1146. info->dsr_chkcount = 0;
  1147. irq_enable(info, CHB, IRQ_DCD | IRQ_CTS);
  1148. port_irq_enable(info, (unsigned char) PVR_DSR | PVR_RI);
  1149. get_signals(info);
  1150. if (info->netcount || (tty && (tty->termios.c_cflag & CREAD)))
  1151. rx_start(info);
  1152. spin_unlock_irqrestore(&info->lock,flags);
  1153. }
  1154. /* Reconfigure adapter based on new parameters
  1155. */
  1156. static void mgslpc_change_params(MGSLPC_INFO *info, struct tty_struct *tty)
  1157. {
  1158. unsigned cflag;
  1159. int bits_per_char;
  1160. if (!tty)
  1161. return;
  1162. if (debug_level >= DEBUG_LEVEL_INFO)
  1163. printk("%s(%d):mgslpc_change_params(%s)\n",
  1164. __FILE__,__LINE__, info->device_name );
  1165. cflag = tty->termios.c_cflag;
  1166. /* if B0 rate (hangup) specified then negate DTR and RTS */
  1167. /* otherwise assert DTR and RTS */
  1168. if (cflag & CBAUD)
  1169. info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
  1170. else
  1171. info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
  1172. /* byte size and parity */
  1173. switch (cflag & CSIZE) {
  1174. case CS5: info->params.data_bits = 5; break;
  1175. case CS6: info->params.data_bits = 6; break;
  1176. case CS7: info->params.data_bits = 7; break;
  1177. case CS8: info->params.data_bits = 8; break;
  1178. default: info->params.data_bits = 7; break;
  1179. }
  1180. if (cflag & CSTOPB)
  1181. info->params.stop_bits = 2;
  1182. else
  1183. info->params.stop_bits = 1;
  1184. info->params.parity = ASYNC_PARITY_NONE;
  1185. if (cflag & PARENB) {
  1186. if (cflag & PARODD)
  1187. info->params.parity = ASYNC_PARITY_ODD;
  1188. else
  1189. info->params.parity = ASYNC_PARITY_EVEN;
  1190. #ifdef CMSPAR
  1191. if (cflag & CMSPAR)
  1192. info->params.parity = ASYNC_PARITY_SPACE;
  1193. #endif
  1194. }
  1195. /* calculate number of jiffies to transmit a full
  1196. * FIFO (32 bytes) at specified data rate
  1197. */
  1198. bits_per_char = info->params.data_bits +
  1199. info->params.stop_bits + 1;
  1200. /* if port data rate is set to 460800 or less then
  1201. * allow tty settings to override, otherwise keep the
  1202. * current data rate.
  1203. */
  1204. if (info->params.data_rate <= 460800) {
  1205. info->params.data_rate = tty_get_baud_rate(tty);
  1206. }
  1207. if ( info->params.data_rate ) {
  1208. info->timeout = (32*HZ*bits_per_char) /
  1209. info->params.data_rate;
  1210. }
  1211. info->timeout += HZ/50; /* Add .02 seconds of slop */
  1212. if (cflag & CRTSCTS)
  1213. info->port.flags |= ASYNC_CTS_FLOW;
  1214. else
  1215. info->port.flags &= ~ASYNC_CTS_FLOW;
  1216. if (cflag & CLOCAL)
  1217. info->port.flags &= ~ASYNC_CHECK_CD;
  1218. else
  1219. info->port.flags |= ASYNC_CHECK_CD;
  1220. /* process tty input control flags */
  1221. info->read_status_mask = 0;
  1222. if (I_INPCK(tty))
  1223. info->read_status_mask |= BIT7 | BIT6;
  1224. if (I_IGNPAR(tty))
  1225. info->ignore_status_mask |= BIT7 | BIT6;
  1226. mgslpc_program_hw(info, tty);
  1227. }
  1228. /* Add a character to the transmit buffer
  1229. */
  1230. static int mgslpc_put_char(struct tty_struct *tty, unsigned char ch)
  1231. {
  1232. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1233. unsigned long flags;
  1234. if (debug_level >= DEBUG_LEVEL_INFO) {
  1235. printk( "%s(%d):mgslpc_put_char(%d) on %s\n",
  1236. __FILE__,__LINE__,ch,info->device_name);
  1237. }
  1238. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_put_char"))
  1239. return 0;
  1240. if (!info->tx_buf)
  1241. return 0;
  1242. spin_lock_irqsave(&info->lock,flags);
  1243. if (info->params.mode == MGSL_MODE_ASYNC || !info->tx_active) {
  1244. if (info->tx_count < TXBUFSIZE - 1) {
  1245. info->tx_buf[info->tx_put++] = ch;
  1246. info->tx_put &= TXBUFSIZE-1;
  1247. info->tx_count++;
  1248. }
  1249. }
  1250. spin_unlock_irqrestore(&info->lock,flags);
  1251. return 1;
  1252. }
  1253. /* Enable transmitter so remaining characters in the
  1254. * transmit buffer are sent.
  1255. */
  1256. static void mgslpc_flush_chars(struct tty_struct *tty)
  1257. {
  1258. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1259. unsigned long flags;
  1260. if (debug_level >= DEBUG_LEVEL_INFO)
  1261. printk( "%s(%d):mgslpc_flush_chars() entry on %s tx_count=%d\n",
  1262. __FILE__,__LINE__,info->device_name,info->tx_count);
  1263. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_flush_chars"))
  1264. return;
  1265. if (info->tx_count <= 0 || tty->stopped ||
  1266. tty->hw_stopped || !info->tx_buf)
  1267. return;
  1268. if (debug_level >= DEBUG_LEVEL_INFO)
  1269. printk( "%s(%d):mgslpc_flush_chars() entry on %s starting transmitter\n",
  1270. __FILE__,__LINE__,info->device_name);
  1271. spin_lock_irqsave(&info->lock,flags);
  1272. if (!info->tx_active)
  1273. tx_start(info, tty);
  1274. spin_unlock_irqrestore(&info->lock,flags);
  1275. }
  1276. /* Send a block of data
  1277. *
  1278. * Arguments:
  1279. *
  1280. * tty pointer to tty information structure
  1281. * buf pointer to buffer containing send data
  1282. * count size of send data in bytes
  1283. *
  1284. * Returns: number of characters written
  1285. */
  1286. static int mgslpc_write(struct tty_struct * tty,
  1287. const unsigned char *buf, int count)
  1288. {
  1289. int c, ret = 0;
  1290. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1291. unsigned long flags;
  1292. if (debug_level >= DEBUG_LEVEL_INFO)
  1293. printk( "%s(%d):mgslpc_write(%s) count=%d\n",
  1294. __FILE__,__LINE__,info->device_name,count);
  1295. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_write") ||
  1296. !info->tx_buf)
  1297. goto cleanup;
  1298. if (info->params.mode == MGSL_MODE_HDLC) {
  1299. if (count > TXBUFSIZE) {
  1300. ret = -EIO;
  1301. goto cleanup;
  1302. }
  1303. if (info->tx_active)
  1304. goto cleanup;
  1305. else if (info->tx_count)
  1306. goto start;
  1307. }
  1308. for (;;) {
  1309. c = min(count,
  1310. min(TXBUFSIZE - info->tx_count - 1,
  1311. TXBUFSIZE - info->tx_put));
  1312. if (c <= 0)
  1313. break;
  1314. memcpy(info->tx_buf + info->tx_put, buf, c);
  1315. spin_lock_irqsave(&info->lock,flags);
  1316. info->tx_put = (info->tx_put + c) & (TXBUFSIZE-1);
  1317. info->tx_count += c;
  1318. spin_unlock_irqrestore(&info->lock,flags);
  1319. buf += c;
  1320. count -= c;
  1321. ret += c;
  1322. }
  1323. start:
  1324. if (info->tx_count && !tty->stopped && !tty->hw_stopped) {
  1325. spin_lock_irqsave(&info->lock,flags);
  1326. if (!info->tx_active)
  1327. tx_start(info, tty);
  1328. spin_unlock_irqrestore(&info->lock,flags);
  1329. }
  1330. cleanup:
  1331. if (debug_level >= DEBUG_LEVEL_INFO)
  1332. printk( "%s(%d):mgslpc_write(%s) returning=%d\n",
  1333. __FILE__,__LINE__,info->device_name,ret);
  1334. return ret;
  1335. }
  1336. /* Return the count of free bytes in transmit buffer
  1337. */
  1338. static int mgslpc_write_room(struct tty_struct *tty)
  1339. {
  1340. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1341. int ret;
  1342. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_write_room"))
  1343. return 0;
  1344. if (info->params.mode == MGSL_MODE_HDLC) {
  1345. /* HDLC (frame oriented) mode */
  1346. if (info->tx_active)
  1347. return 0;
  1348. else
  1349. return HDLC_MAX_FRAME_SIZE;
  1350. } else {
  1351. ret = TXBUFSIZE - info->tx_count - 1;
  1352. if (ret < 0)
  1353. ret = 0;
  1354. }
  1355. if (debug_level >= DEBUG_LEVEL_INFO)
  1356. printk("%s(%d):mgslpc_write_room(%s)=%d\n",
  1357. __FILE__,__LINE__, info->device_name, ret);
  1358. return ret;
  1359. }
  1360. /* Return the count of bytes in transmit buffer
  1361. */
  1362. static int mgslpc_chars_in_buffer(struct tty_struct *tty)
  1363. {
  1364. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1365. int rc;
  1366. if (debug_level >= DEBUG_LEVEL_INFO)
  1367. printk("%s(%d):mgslpc_chars_in_buffer(%s)\n",
  1368. __FILE__,__LINE__, info->device_name );
  1369. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_chars_in_buffer"))
  1370. return 0;
  1371. if (info->params.mode == MGSL_MODE_HDLC)
  1372. rc = info->tx_active ? info->max_frame_size : 0;
  1373. else
  1374. rc = info->tx_count;
  1375. if (debug_level >= DEBUG_LEVEL_INFO)
  1376. printk("%s(%d):mgslpc_chars_in_buffer(%s)=%d\n",
  1377. __FILE__,__LINE__, info->device_name, rc);
  1378. return rc;
  1379. }
  1380. /* Discard all data in the send buffer
  1381. */
  1382. static void mgslpc_flush_buffer(struct tty_struct *tty)
  1383. {
  1384. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1385. unsigned long flags;
  1386. if (debug_level >= DEBUG_LEVEL_INFO)
  1387. printk("%s(%d):mgslpc_flush_buffer(%s) entry\n",
  1388. __FILE__,__LINE__, info->device_name );
  1389. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_flush_buffer"))
  1390. return;
  1391. spin_lock_irqsave(&info->lock,flags);
  1392. info->tx_count = info->tx_put = info->tx_get = 0;
  1393. del_timer(&info->tx_timer);
  1394. spin_unlock_irqrestore(&info->lock,flags);
  1395. wake_up_interruptible(&tty->write_wait);
  1396. tty_wakeup(tty);
  1397. }
  1398. /* Send a high-priority XON/XOFF character
  1399. */
  1400. static void mgslpc_send_xchar(struct tty_struct *tty, char ch)
  1401. {
  1402. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1403. unsigned long flags;
  1404. if (debug_level >= DEBUG_LEVEL_INFO)
  1405. printk("%s(%d):mgslpc_send_xchar(%s,%d)\n",
  1406. __FILE__,__LINE__, info->device_name, ch );
  1407. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_send_xchar"))
  1408. return;
  1409. info->x_char = ch;
  1410. if (ch) {
  1411. spin_lock_irqsave(&info->lock,flags);
  1412. if (!info->tx_enabled)
  1413. tx_start(info, tty);
  1414. spin_unlock_irqrestore(&info->lock,flags);
  1415. }
  1416. }
  1417. /* Signal remote device to throttle send data (our receive data)
  1418. */
  1419. static void mgslpc_throttle(struct tty_struct * tty)
  1420. {
  1421. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1422. unsigned long flags;
  1423. if (debug_level >= DEBUG_LEVEL_INFO)
  1424. printk("%s(%d):mgslpc_throttle(%s) entry\n",
  1425. __FILE__,__LINE__, info->device_name );
  1426. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_throttle"))
  1427. return;
  1428. if (I_IXOFF(tty))
  1429. mgslpc_send_xchar(tty, STOP_CHAR(tty));
  1430. if (tty->termios.c_cflag & CRTSCTS) {
  1431. spin_lock_irqsave(&info->lock,flags);
  1432. info->serial_signals &= ~SerialSignal_RTS;
  1433. set_signals(info);
  1434. spin_unlock_irqrestore(&info->lock,flags);
  1435. }
  1436. }
  1437. /* Signal remote device to stop throttling send data (our receive data)
  1438. */
  1439. static void mgslpc_unthrottle(struct tty_struct * tty)
  1440. {
  1441. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1442. unsigned long flags;
  1443. if (debug_level >= DEBUG_LEVEL_INFO)
  1444. printk("%s(%d):mgslpc_unthrottle(%s) entry\n",
  1445. __FILE__,__LINE__, info->device_name );
  1446. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_unthrottle"))
  1447. return;
  1448. if (I_IXOFF(tty)) {
  1449. if (info->x_char)
  1450. info->x_char = 0;
  1451. else
  1452. mgslpc_send_xchar(tty, START_CHAR(tty));
  1453. }
  1454. if (tty->termios.c_cflag & CRTSCTS) {
  1455. spin_lock_irqsave(&info->lock,flags);
  1456. info->serial_signals |= SerialSignal_RTS;
  1457. set_signals(info);
  1458. spin_unlock_irqrestore(&info->lock,flags);
  1459. }
  1460. }
  1461. /* get the current serial statistics
  1462. */
  1463. static int get_stats(MGSLPC_INFO * info, struct mgsl_icount __user *user_icount)
  1464. {
  1465. int err;
  1466. if (debug_level >= DEBUG_LEVEL_INFO)
  1467. printk("get_params(%s)\n", info->device_name);
  1468. if (!user_icount) {
  1469. memset(&info->icount, 0, sizeof(info->icount));
  1470. } else {
  1471. COPY_TO_USER(err, user_icount, &info->icount, sizeof(struct mgsl_icount));
  1472. if (err)
  1473. return -EFAULT;
  1474. }
  1475. return 0;
  1476. }
  1477. /* get the current serial parameters
  1478. */
  1479. static int get_params(MGSLPC_INFO * info, MGSL_PARAMS __user *user_params)
  1480. {
  1481. int err;
  1482. if (debug_level >= DEBUG_LEVEL_INFO)
  1483. printk("get_params(%s)\n", info->device_name);
  1484. COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS));
  1485. if (err)
  1486. return -EFAULT;
  1487. return 0;
  1488. }
  1489. /* set the serial parameters
  1490. *
  1491. * Arguments:
  1492. *
  1493. * info pointer to device instance data
  1494. * new_params user buffer containing new serial params
  1495. *
  1496. * Returns: 0 if success, otherwise error code
  1497. */
  1498. static int set_params(MGSLPC_INFO * info, MGSL_PARAMS __user *new_params, struct tty_struct *tty)
  1499. {
  1500. unsigned long flags;
  1501. MGSL_PARAMS tmp_params;
  1502. int err;
  1503. if (debug_level >= DEBUG_LEVEL_INFO)
  1504. printk("%s(%d):set_params %s\n", __FILE__,__LINE__,
  1505. info->device_name );
  1506. COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS));
  1507. if (err) {
  1508. if ( debug_level >= DEBUG_LEVEL_INFO )
  1509. printk( "%s(%d):set_params(%s) user buffer copy failed\n",
  1510. __FILE__,__LINE__,info->device_name);
  1511. return -EFAULT;
  1512. }
  1513. spin_lock_irqsave(&info->lock,flags);
  1514. memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
  1515. spin_unlock_irqrestore(&info->lock,flags);
  1516. mgslpc_change_params(info, tty);
  1517. return 0;
  1518. }
  1519. static int get_txidle(MGSLPC_INFO * info, int __user *idle_mode)
  1520. {
  1521. int err;
  1522. if (debug_level >= DEBUG_LEVEL_INFO)
  1523. printk("get_txidle(%s)=%d\n", info->device_name, info->idle_mode);
  1524. COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int));
  1525. if (err)
  1526. return -EFAULT;
  1527. return 0;
  1528. }
  1529. static int set_txidle(MGSLPC_INFO * info, int idle_mode)
  1530. {
  1531. unsigned long flags;
  1532. if (debug_level >= DEBUG_LEVEL_INFO)
  1533. printk("set_txidle(%s,%d)\n", info->device_name, idle_mode);
  1534. spin_lock_irqsave(&info->lock,flags);
  1535. info->idle_mode = idle_mode;
  1536. tx_set_idle(info);
  1537. spin_unlock_irqrestore(&info->lock,flags);
  1538. return 0;
  1539. }
  1540. static int get_interface(MGSLPC_INFO * info, int __user *if_mode)
  1541. {
  1542. int err;
  1543. if (debug_level >= DEBUG_LEVEL_INFO)
  1544. printk("get_interface(%s)=%d\n", info->device_name, info->if_mode);
  1545. COPY_TO_USER(err,if_mode, &info->if_mode, sizeof(int));
  1546. if (err)
  1547. return -EFAULT;
  1548. return 0;
  1549. }
  1550. static int set_interface(MGSLPC_INFO * info, int if_mode)
  1551. {
  1552. unsigned long flags;
  1553. unsigned char val;
  1554. if (debug_level >= DEBUG_LEVEL_INFO)
  1555. printk("set_interface(%s,%d)\n", info->device_name, if_mode);
  1556. spin_lock_irqsave(&info->lock,flags);
  1557. info->if_mode = if_mode;
  1558. val = read_reg(info, PVR) & 0x0f;
  1559. switch (info->if_mode)
  1560. {
  1561. case MGSL_INTERFACE_RS232: val |= PVR_RS232; break;
  1562. case MGSL_INTERFACE_V35: val |= PVR_V35; break;
  1563. case MGSL_INTERFACE_RS422: val |= PVR_RS422; break;
  1564. }
  1565. write_reg(info, PVR, val);
  1566. spin_unlock_irqrestore(&info->lock,flags);
  1567. return 0;
  1568. }
  1569. static int set_txenable(MGSLPC_INFO * info, int enable, struct tty_struct *tty)
  1570. {
  1571. unsigned long flags;
  1572. if (debug_level >= DEBUG_LEVEL_INFO)
  1573. printk("set_txenable(%s,%d)\n", info->device_name, enable);
  1574. spin_lock_irqsave(&info->lock,flags);
  1575. if (enable) {
  1576. if (!info->tx_enabled)
  1577. tx_start(info, tty);
  1578. } else {
  1579. if (info->tx_enabled)
  1580. tx_stop(info);
  1581. }
  1582. spin_unlock_irqrestore(&info->lock,flags);
  1583. return 0;
  1584. }
  1585. static int tx_abort(MGSLPC_INFO * info)
  1586. {
  1587. unsigned long flags;
  1588. if (debug_level >= DEBUG_LEVEL_INFO)
  1589. printk("tx_abort(%s)\n", info->device_name);
  1590. spin_lock_irqsave(&info->lock,flags);
  1591. if (info->tx_active && info->tx_count &&
  1592. info->params.mode == MGSL_MODE_HDLC) {
  1593. /* clear data count so FIFO is not filled on next IRQ.
  1594. * This results in underrun and abort transmission.
  1595. */
  1596. info->tx_count = info->tx_put = info->tx_get = 0;
  1597. info->tx_aborting = true;
  1598. }
  1599. spin_unlock_irqrestore(&info->lock,flags);
  1600. return 0;
  1601. }
  1602. static int set_rxenable(MGSLPC_INFO * info, int enable)
  1603. {
  1604. unsigned long flags;
  1605. if (debug_level >= DEBUG_LEVEL_INFO)
  1606. printk("set_rxenable(%s,%d)\n", info->device_name, enable);
  1607. spin_lock_irqsave(&info->lock,flags);
  1608. if (enable) {
  1609. if (!info->rx_enabled)
  1610. rx_start(info);
  1611. } else {
  1612. if (info->rx_enabled)
  1613. rx_stop(info);
  1614. }
  1615. spin_unlock_irqrestore(&info->lock,flags);
  1616. return 0;
  1617. }
  1618. /* wait for specified event to occur
  1619. *
  1620. * Arguments: info pointer to device instance data
  1621. * mask pointer to bitmask of events to wait for
  1622. * Return Value: 0 if successful and bit mask updated with
  1623. * of events triggerred,
  1624. * otherwise error code
  1625. */
  1626. static int wait_events(MGSLPC_INFO * info, int __user *mask_ptr)
  1627. {
  1628. unsigned long flags;
  1629. int s;
  1630. int rc=0;
  1631. struct mgsl_icount cprev, cnow;
  1632. int events;
  1633. int mask;
  1634. struct _input_signal_events oldsigs, newsigs;
  1635. DECLARE_WAITQUEUE(wait, current);
  1636. COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int));
  1637. if (rc)
  1638. return -EFAULT;
  1639. if (debug_level >= DEBUG_LEVEL_INFO)
  1640. printk("wait_events(%s,%d)\n", info->device_name, mask);
  1641. spin_lock_irqsave(&info->lock,flags);
  1642. /* return immediately if state matches requested events */
  1643. get_signals(info);
  1644. s = info->serial_signals;
  1645. events = mask &
  1646. ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
  1647. ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
  1648. ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
  1649. ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
  1650. if (events) {
  1651. spin_unlock_irqrestore(&info->lock,flags);
  1652. goto exit;
  1653. }
  1654. /* save current irq counts */
  1655. cprev = info->icount;
  1656. oldsigs = info->input_signal_events;
  1657. if ((info->params.mode == MGSL_MODE_HDLC) &&
  1658. (mask & MgslEvent_ExitHuntMode))
  1659. irq_enable(info, CHA, IRQ_EXITHUNT);
  1660. set_current_state(TASK_INTERRUPTIBLE);
  1661. add_wait_queue(&info->event_wait_q, &wait);
  1662. spin_unlock_irqrestore(&info->lock,flags);
  1663. for(;;) {
  1664. schedule();
  1665. if (signal_pending(current)) {
  1666. rc = -ERESTARTSYS;
  1667. break;
  1668. }
  1669. /* get current irq counts */
  1670. spin_lock_irqsave(&info->lock,flags);
  1671. cnow = info->icount;
  1672. newsigs = info->input_signal_events;
  1673. set_current_state(TASK_INTERRUPTIBLE);
  1674. spin_unlock_irqrestore(&info->lock,flags);
  1675. /* if no change, wait aborted for some reason */
  1676. if (newsigs.dsr_up == oldsigs.dsr_up &&
  1677. newsigs.dsr_down == oldsigs.dsr_down &&
  1678. newsigs.dcd_up == oldsigs.dcd_up &&
  1679. newsigs.dcd_down == oldsigs.dcd_down &&
  1680. newsigs.cts_up == oldsigs.cts_up &&
  1681. newsigs.cts_down == oldsigs.cts_down &&
  1682. newsigs.ri_up == oldsigs.ri_up &&
  1683. newsigs.ri_down == oldsigs.ri_down &&
  1684. cnow.exithunt == cprev.exithunt &&
  1685. cnow.rxidle == cprev.rxidle) {
  1686. rc = -EIO;
  1687. break;
  1688. }
  1689. events = mask &
  1690. ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
  1691. (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
  1692. (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
  1693. (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
  1694. (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
  1695. (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
  1696. (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
  1697. (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
  1698. (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
  1699. (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
  1700. if (events)
  1701. break;
  1702. cprev = cnow;
  1703. oldsigs = newsigs;
  1704. }
  1705. remove_wait_queue(&info->event_wait_q, &wait);
  1706. set_current_state(TASK_RUNNING);
  1707. if (mask & MgslEvent_ExitHuntMode) {
  1708. spin_lock_irqsave(&info->lock,flags);
  1709. if (!waitqueue_active(&info->event_wait_q))
  1710. irq_disable(info, CHA, IRQ_EXITHUNT);
  1711. spin_unlock_irqrestore(&info->lock,flags);
  1712. }
  1713. exit:
  1714. if (rc == 0)
  1715. PUT_USER(rc, events, mask_ptr);
  1716. return rc;
  1717. }
  1718. static int modem_input_wait(MGSLPC_INFO *info,int arg)
  1719. {
  1720. unsigned long flags;
  1721. int rc;
  1722. struct mgsl_icount cprev, cnow;
  1723. DECLARE_WAITQUEUE(wait, current);
  1724. /* save current irq counts */
  1725. spin_lock_irqsave(&info->lock,flags);
  1726. cprev = info->icount;
  1727. add_wait_queue(&info->status_event_wait_q, &wait);
  1728. set_current_state(TASK_INTERRUPTIBLE);
  1729. spin_unlock_irqrestore(&info->lock,flags);
  1730. for(;;) {
  1731. schedule();
  1732. if (signal_pending(current)) {
  1733. rc = -ERESTARTSYS;
  1734. break;
  1735. }
  1736. /* get new irq counts */
  1737. spin_lock_irqsave(&info->lock,flags);
  1738. cnow = info->icount;
  1739. set_current_state(TASK_INTERRUPTIBLE);
  1740. spin_unlock_irqrestore(&info->lock,flags);
  1741. /* if no change, wait aborted for some reason */
  1742. if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
  1743. cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
  1744. rc = -EIO;
  1745. break;
  1746. }
  1747. /* check for change in caller specified modem input */
  1748. if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
  1749. (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
  1750. (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
  1751. (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
  1752. rc = 0;
  1753. break;
  1754. }
  1755. cprev = cnow;
  1756. }
  1757. remove_wait_queue(&info->status_event_wait_q, &wait);
  1758. set_current_state(TASK_RUNNING);
  1759. return rc;
  1760. }
  1761. /* return the state of the serial control and status signals
  1762. */
  1763. static int tiocmget(struct tty_struct *tty)
  1764. {
  1765. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1766. unsigned int result;
  1767. unsigned long flags;
  1768. spin_lock_irqsave(&info->lock,flags);
  1769. get_signals(info);
  1770. spin_unlock_irqrestore(&info->lock,flags);
  1771. result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
  1772. ((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
  1773. ((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
  1774. ((info->serial_signals & SerialSignal_RI) ? TIOCM_RNG:0) +
  1775. ((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
  1776. ((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS:0);
  1777. if (debug_level >= DEBUG_LEVEL_INFO)
  1778. printk("%s(%d):%s tiocmget() value=%08X\n",
  1779. __FILE__,__LINE__, info->device_name, result );
  1780. return result;
  1781. }
  1782. /* set modem control signals (DTR/RTS)
  1783. */
  1784. static int tiocmset(struct tty_struct *tty,
  1785. unsigned int set, unsigned int clear)
  1786. {
  1787. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1788. unsigned long flags;
  1789. if (debug_level >= DEBUG_LEVEL_INFO)
  1790. printk("%s(%d):%s tiocmset(%x,%x)\n",
  1791. __FILE__,__LINE__,info->device_name, set, clear);
  1792. if (set & TIOCM_RTS)
  1793. info->serial_signals |= SerialSignal_RTS;
  1794. if (set & TIOCM_DTR)
  1795. info->serial_signals |= SerialSignal_DTR;
  1796. if (clear & TIOCM_RTS)
  1797. info->serial_signals &= ~SerialSignal_RTS;
  1798. if (clear & TIOCM_DTR)
  1799. info->serial_signals &= ~SerialSignal_DTR;
  1800. spin_lock_irqsave(&info->lock,flags);
  1801. set_signals(info);
  1802. spin_unlock_irqrestore(&info->lock,flags);
  1803. return 0;
  1804. }
  1805. /* Set or clear transmit break condition
  1806. *
  1807. * Arguments: tty pointer to tty instance data
  1808. * break_state -1=set break condition, 0=clear
  1809. */
  1810. static int mgslpc_break(struct tty_struct *tty, int break_state)
  1811. {
  1812. MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data;
  1813. unsigned long flags;
  1814. if (debug_level >= DEBUG_LEVEL_INFO)
  1815. printk("%s(%d):mgslpc_break(%s,%d)\n",
  1816. __FILE__,__LINE__, info->device_name, break_state);
  1817. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_break"))
  1818. return -EINVAL;
  1819. spin_lock_irqsave(&info->lock,flags);
  1820. if (break_state == -1)
  1821. set_reg_bits(info, CHA+DAFO, BIT6);
  1822. else
  1823. clear_reg_bits(info, CHA+DAFO, BIT6);
  1824. spin_unlock_irqrestore(&info->lock,flags);
  1825. return 0;
  1826. }
  1827. static int mgslpc_get_icount(struct tty_struct *tty,
  1828. struct serial_icounter_struct *icount)
  1829. {
  1830. MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data;
  1831. struct mgsl_icount cnow; /* kernel counter temps */
  1832. unsigned long flags;
  1833. spin_lock_irqsave(&info->lock,flags);
  1834. cnow = info->icount;
  1835. spin_unlock_irqrestore(&info->lock,flags);
  1836. icount->cts = cnow.cts;
  1837. icount->dsr = cnow.dsr;
  1838. icount->rng = cnow.rng;
  1839. icount->dcd = cnow.dcd;
  1840. icount->rx = cnow.rx;
  1841. icount->tx = cnow.tx;
  1842. icount->frame = cnow.frame;
  1843. icount->overrun = cnow.overrun;
  1844. icount->parity = cnow.parity;
  1845. icount->brk = cnow.brk;
  1846. icount->buf_overrun = cnow.buf_overrun;
  1847. return 0;
  1848. }
  1849. /* Service an IOCTL request
  1850. *
  1851. * Arguments:
  1852. *
  1853. * tty pointer to tty instance data
  1854. * cmd IOCTL command code
  1855. * arg command argument/context
  1856. *
  1857. * Return Value: 0 if success, otherwise error code
  1858. */
  1859. static int mgslpc_ioctl(struct tty_struct *tty,
  1860. unsigned int cmd, unsigned long arg)
  1861. {
  1862. MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data;
  1863. void __user *argp = (void __user *)arg;
  1864. if (debug_level >= DEBUG_LEVEL_INFO)
  1865. printk("%s(%d):mgslpc_ioctl %s cmd=%08X\n", __FILE__,__LINE__,
  1866. info->device_name, cmd );
  1867. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_ioctl"))
  1868. return -ENODEV;
  1869. if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
  1870. (cmd != TIOCMIWAIT)) {
  1871. if (tty->flags & (1 << TTY_IO_ERROR))
  1872. return -EIO;
  1873. }
  1874. switch (cmd) {
  1875. case MGSL_IOCGPARAMS:
  1876. return get_params(info, argp);
  1877. case MGSL_IOCSPARAMS:
  1878. return set_params(info, argp, tty);
  1879. case MGSL_IOCGTXIDLE:
  1880. return get_txidle(info, argp);
  1881. case MGSL_IOCSTXIDLE:
  1882. return set_txidle(info, (int)arg);
  1883. case MGSL_IOCGIF:
  1884. return get_interface(info, argp);
  1885. case MGSL_IOCSIF:
  1886. return set_interface(info,(int)arg);
  1887. case MGSL_IOCTXENABLE:
  1888. return set_txenable(info,(int)arg, tty);
  1889. case MGSL_IOCRXENABLE:
  1890. return set_rxenable(info,(int)arg);
  1891. case MGSL_IOCTXABORT:
  1892. return tx_abort(info);
  1893. case MGSL_IOCGSTATS:
  1894. return get_stats(info, argp);
  1895. case MGSL_IOCWAITEVENT:
  1896. return wait_events(info, argp);
  1897. case TIOCMIWAIT:
  1898. return modem_input_wait(info,(int)arg);
  1899. default:
  1900. return -ENOIOCTLCMD;
  1901. }
  1902. return 0;
  1903. }
  1904. /* Set new termios settings
  1905. *
  1906. * Arguments:
  1907. *
  1908. * tty pointer to tty structure
  1909. * termios pointer to buffer to hold returned old termios
  1910. */
  1911. static void mgslpc_set_termios(struct tty_struct *tty, struct ktermios *old_termios)
  1912. {
  1913. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1914. unsigned long flags;
  1915. if (debug_level >= DEBUG_LEVEL_INFO)
  1916. printk("%s(%d):mgslpc_set_termios %s\n", __FILE__,__LINE__,
  1917. tty->driver->name );
  1918. /* just return if nothing has changed */
  1919. if ((tty->termios.c_cflag == old_termios->c_cflag)
  1920. && (RELEVANT_IFLAG(tty->termios.c_iflag)
  1921. == RELEVANT_IFLAG(old_termios->c_iflag)))
  1922. return;
  1923. mgslpc_change_params(info, tty);
  1924. /* Handle transition to B0 status */
  1925. if (old_termios->c_cflag & CBAUD &&
  1926. !(tty->termios.c_cflag & CBAUD)) {
  1927. info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
  1928. spin_lock_irqsave(&info->lock,flags);
  1929. set_signals(info);
  1930. spin_unlock_irqrestore(&info->lock,flags);
  1931. }
  1932. /* Handle transition away from B0 status */
  1933. if (!(old_termios->c_cflag & CBAUD) &&
  1934. tty->termios.c_cflag & CBAUD) {
  1935. info->serial_signals |= SerialSignal_DTR;
  1936. if (!(tty->termios.c_cflag & CRTSCTS) ||
  1937. !test_bit(TTY_THROTTLED, &tty->flags)) {
  1938. info->serial_signals |= SerialSignal_RTS;
  1939. }
  1940. spin_lock_irqsave(&info->lock,flags);
  1941. set_signals(info);
  1942. spin_unlock_irqrestore(&info->lock,flags);
  1943. }
  1944. /* Handle turning off CRTSCTS */
  1945. if (old_termios->c_cflag & CRTSCTS &&
  1946. !(tty->termios.c_cflag & CRTSCTS)) {
  1947. tty->hw_stopped = 0;
  1948. tx_release(tty);
  1949. }
  1950. }
  1951. static void mgslpc_close(struct tty_struct *tty, struct file * filp)
  1952. {
  1953. MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data;
  1954. struct tty_port *port = &info->port;
  1955. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_close"))
  1956. return;
  1957. if (debug_level >= DEBUG_LEVEL_INFO)
  1958. printk("%s(%d):mgslpc_close(%s) entry, count=%d\n",
  1959. __FILE__,__LINE__, info->device_name, port->count);
  1960. WARN_ON(!port->count);
  1961. if (tty_port_close_start(port, tty, filp) == 0)
  1962. goto cleanup;
  1963. if (port->flags & ASYNC_INITIALIZED)
  1964. mgslpc_wait_until_sent(tty, info->timeout);
  1965. mgslpc_flush_buffer(tty);
  1966. tty_ldisc_flush(tty);
  1967. shutdown(info, tty);
  1968. tty_port_close_end(port, tty);
  1969. tty_port_tty_set(port, NULL);
  1970. cleanup:
  1971. if (debug_level >= DEBUG_LEVEL_INFO)
  1972. printk("%s(%d):mgslpc_close(%s) exit, count=%d\n", __FILE__,__LINE__,
  1973. tty->driver->name, port->count);
  1974. }
  1975. /* Wait until the transmitter is empty.
  1976. */
  1977. static void mgslpc_wait_until_sent(struct tty_struct *tty, int timeout)
  1978. {
  1979. MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data;
  1980. unsigned long orig_jiffies, char_time;
  1981. if (!info )
  1982. return;
  1983. if (debug_level >= DEBUG_LEVEL_INFO)
  1984. printk("%s(%d):mgslpc_wait_until_sent(%s) entry\n",
  1985. __FILE__,__LINE__, info->device_name );
  1986. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_wait_until_sent"))
  1987. return;
  1988. if (!(info->port.flags & ASYNC_INITIALIZED))
  1989. goto exit;
  1990. orig_jiffies = jiffies;
  1991. /* Set check interval to 1/5 of estimated time to
  1992. * send a character, and make it at least 1. The check
  1993. * interval should also be less than the timeout.
  1994. * Note: use tight timings here to satisfy the NIST-PCTS.
  1995. */
  1996. if ( info->params.data_rate ) {
  1997. char_time = info->timeout/(32 * 5);
  1998. if (!char_time)
  1999. char_time++;
  2000. } else
  2001. char_time = 1;
  2002. if (timeout)
  2003. char_time = min_t(unsigned long, char_time, timeout);
  2004. if (info->params.mode == MGSL_MODE_HDLC) {
  2005. while (info->tx_active) {
  2006. msleep_interruptible(jiffies_to_msecs(char_time));
  2007. if (signal_pending(current))
  2008. break;
  2009. if (timeout && time_after(jiffies, orig_jiffies + timeout))
  2010. break;
  2011. }
  2012. } else {
  2013. while ((info->tx_count || info->tx_active) &&
  2014. info->tx_enabled) {
  2015. msleep_interruptible(jiffies_to_msecs(char_time));
  2016. if (signal_pending(current))
  2017. break;
  2018. if (timeout && time_after(jiffies, orig_jiffies + timeout))
  2019. break;
  2020. }
  2021. }
  2022. exit:
  2023. if (debug_level >= DEBUG_LEVEL_INFO)
  2024. printk("%s(%d):mgslpc_wait_until_sent(%s) exit\n",
  2025. __FILE__,__LINE__, info->device_name );
  2026. }
  2027. /* Called by tty_hangup() when a hangup is signaled.
  2028. * This is the same as closing all open files for the port.
  2029. */
  2030. static void mgslpc_hangup(struct tty_struct *tty)
  2031. {
  2032. MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data;
  2033. if (debug_level >= DEBUG_LEVEL_INFO)
  2034. printk("%s(%d):mgslpc_hangup(%s)\n",
  2035. __FILE__,__LINE__, info->device_name );
  2036. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_hangup"))
  2037. return;
  2038. mgslpc_flush_buffer(tty);
  2039. shutdown(info, tty);
  2040. tty_port_hangup(&info->port);
  2041. }
  2042. static int carrier_raised(struct tty_port *port)
  2043. {
  2044. MGSLPC_INFO *info = container_of(port, MGSLPC_INFO, port);
  2045. unsigned long flags;
  2046. spin_lock_irqsave(&info->lock,flags);
  2047. get_signals(info);
  2048. spin_unlock_irqrestore(&info->lock,flags);
  2049. if (info->serial_signals & SerialSignal_DCD)
  2050. return 1;
  2051. return 0;
  2052. }
  2053. static void dtr_rts(struct tty_port *port, int onoff)
  2054. {
  2055. MGSLPC_INFO *info = container_of(port, MGSLPC_INFO, port);
  2056. unsigned long flags;
  2057. spin_lock_irqsave(&info->lock,flags);
  2058. if (onoff)
  2059. info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
  2060. else
  2061. info->serial_signals &= ~SerialSignal_RTS + SerialSignal_DTR;
  2062. set_signals(info);
  2063. spin_unlock_irqrestore(&info->lock,flags);
  2064. }
  2065. static int mgslpc_open(struct tty_struct *tty, struct file * filp)
  2066. {
  2067. MGSLPC_INFO *info;
  2068. struct tty_port *port;
  2069. int retval, line;
  2070. unsigned long flags;
  2071. /* verify range of specified line number */
  2072. line = tty->index;
  2073. if (line >= mgslpc_device_count) {
  2074. printk("%s(%d):mgslpc_open with invalid line #%d.\n",
  2075. __FILE__,__LINE__,line);
  2076. return -ENODEV;
  2077. }
  2078. /* find the info structure for the specified line */
  2079. info = mgslpc_device_list;
  2080. while(info && info->line != line)
  2081. info = info->next_device;
  2082. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_open"))
  2083. return -ENODEV;
  2084. port = &info->port;
  2085. tty->driver_data = info;
  2086. tty_port_tty_set(port, tty);
  2087. if (debug_level >= DEBUG_LEVEL_INFO)
  2088. printk("%s(%d):mgslpc_open(%s), old ref count = %d\n",
  2089. __FILE__,__LINE__,tty->driver->name, port->count);
  2090. /* If port is closing, signal caller to try again */
  2091. if (tty_hung_up_p(filp) || port->flags & ASYNC_CLOSING){
  2092. if (port->flags & ASYNC_CLOSING)
  2093. interruptible_sleep_on(&port->close_wait);
  2094. retval = ((port->flags & ASYNC_HUP_NOTIFY) ?
  2095. -EAGAIN : -ERESTARTSYS);
  2096. goto cleanup;
  2097. }
  2098. tty->low_latency = (port->flags & ASYNC_LOW_LATENCY) ? 1 : 0;
  2099. spin_lock_irqsave(&info->netlock, flags);
  2100. if (info->netcount) {
  2101. retval = -EBUSY;
  2102. spin_unlock_irqrestore(&info->netlock, flags);
  2103. goto cleanup;
  2104. }
  2105. spin_lock(&port->lock);
  2106. port->count++;
  2107. spin_unlock(&port->lock);
  2108. spin_unlock_irqrestore(&info->netlock, flags);
  2109. if (port->count == 1) {
  2110. /* 1st open on this device, init hardware */
  2111. retval = startup(info, tty);
  2112. if (retval < 0)
  2113. goto cleanup;
  2114. }
  2115. retval = tty_port_block_til_ready(&info->port, tty, filp);
  2116. if (retval) {
  2117. if (debug_level >= DEBUG_LEVEL_INFO)
  2118. printk("%s(%d):block_til_ready(%s) returned %d\n",
  2119. __FILE__,__LINE__, info->device_name, retval);
  2120. goto cleanup;
  2121. }
  2122. if (debug_level >= DEBUG_LEVEL_INFO)
  2123. printk("%s(%d):mgslpc_open(%s) success\n",
  2124. __FILE__,__LINE__, info->device_name);
  2125. retval = 0;
  2126. cleanup:
  2127. return retval;
  2128. }
  2129. /*
  2130. * /proc fs routines....
  2131. */
  2132. static inline void line_info(struct seq_file *m, MGSLPC_INFO *info)
  2133. {
  2134. char stat_buf[30];
  2135. unsigned long flags;
  2136. seq_printf(m, "%s:io:%04X irq:%d",
  2137. info->device_name, info->io_base, info->irq_level);
  2138. /* output current serial signal states */
  2139. spin_lock_irqsave(&info->lock,flags);
  2140. get_signals(info);
  2141. spin_unlock_irqrestore(&info->lock,flags);
  2142. stat_buf[0] = 0;
  2143. stat_buf[1] = 0;
  2144. if (info->serial_signals & SerialSignal_RTS)
  2145. strcat(stat_buf, "|RTS");
  2146. if (info->serial_signals & SerialSignal_CTS)
  2147. strcat(stat_buf, "|CTS");
  2148. if (info->serial_signals & SerialSignal_DTR)
  2149. strcat(stat_buf, "|DTR");
  2150. if (info->serial_signals & SerialSignal_DSR)
  2151. strcat(stat_buf, "|DSR");
  2152. if (info->serial_signals & SerialSignal_DCD)
  2153. strcat(stat_buf, "|CD");
  2154. if (info->serial_signals & SerialSignal_RI)
  2155. strcat(stat_buf, "|RI");
  2156. if (info->params.mode == MGSL_MODE_HDLC) {
  2157. seq_printf(m, " HDLC txok:%d rxok:%d",
  2158. info->icount.txok, info->icount.rxok);
  2159. if (info->icount.txunder)
  2160. seq_printf(m, " txunder:%d", info->icount.txunder);
  2161. if (info->icount.txabort)
  2162. seq_printf(m, " txabort:%d", info->icount.txabort);
  2163. if (info->icount.rxshort)
  2164. seq_printf(m, " rxshort:%d", info->icount.rxshort);
  2165. if (info->icount.rxlong)
  2166. seq_printf(m, " rxlong:%d", info->icount.rxlong);
  2167. if (info->icount.rxover)
  2168. seq_printf(m, " rxover:%d", info->icount.rxover);
  2169. if (info->icount.rxcrc)
  2170. seq_printf(m, " rxcrc:%d", info->icount.rxcrc);
  2171. } else {
  2172. seq_printf(m, " ASYNC tx:%d rx:%d",
  2173. info->icount.tx, info->icount.rx);
  2174. if (info->icount.frame)
  2175. seq_printf(m, " fe:%d", info->icount.frame);
  2176. if (info->icount.parity)
  2177. seq_printf(m, " pe:%d", info->icount.parity);
  2178. if (info->icount.brk)
  2179. seq_printf(m, " brk:%d", info->icount.brk);
  2180. if (info->icount.overrun)
  2181. seq_printf(m, " oe:%d", info->icount.overrun);
  2182. }
  2183. /* Append serial signal status to end */
  2184. seq_printf(m, " %s\n", stat_buf+1);
  2185. seq_printf(m, "txactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
  2186. info->tx_active,info->bh_requested,info->bh_running,
  2187. info->pending_bh);
  2188. }
  2189. /* Called to print information about devices
  2190. */
  2191. static int mgslpc_proc_show(struct seq_file *m, void *v)
  2192. {
  2193. MGSLPC_INFO *info;
  2194. seq_printf(m, "synclink driver:%s\n", driver_version);
  2195. info = mgslpc_device_list;
  2196. while( info ) {
  2197. line_info(m, info);
  2198. info = info->next_device;
  2199. }
  2200. return 0;
  2201. }
  2202. static int mgslpc_proc_open(struct inode *inode, struct file *file)
  2203. {
  2204. return single_open(file, mgslpc_proc_show, NULL);
  2205. }
  2206. static const struct file_operations mgslpc_proc_fops = {
  2207. .owner = THIS_MODULE,
  2208. .open = mgslpc_proc_open,
  2209. .read = seq_read,
  2210. .llseek = seq_lseek,
  2211. .release = single_release,
  2212. };
  2213. static int rx_alloc_buffers(MGSLPC_INFO *info)
  2214. {
  2215. /* each buffer has header and data */
  2216. info->rx_buf_size = sizeof(RXBUF) + info->max_frame_size;
  2217. /* calculate total allocation size for 8 buffers */
  2218. info->rx_buf_total_size = info->rx_buf_size * 8;
  2219. /* limit total allocated memory */
  2220. if (info->rx_buf_total_size > 0x10000)
  2221. info->rx_buf_total_size = 0x10000;
  2222. /* calculate number of buffers */
  2223. info->rx_buf_count = info->rx_buf_total_size / info->rx_buf_size;
  2224. info->rx_buf = kmalloc(info->rx_buf_total_size, GFP_KERNEL);
  2225. if (info->rx_buf == NULL)
  2226. return -ENOMEM;
  2227. /* unused flag buffer to satisfy receive_buf calling interface */
  2228. info->flag_buf = kzalloc(info->max_frame_size, GFP_KERNEL);
  2229. if (!info->flag_buf) {
  2230. kfree(info->rx_buf);
  2231. info->rx_buf = NULL;
  2232. return -ENOMEM;
  2233. }
  2234. rx_reset_buffers(info);
  2235. return 0;
  2236. }
  2237. static void rx_free_buffers(MGSLPC_INFO *info)
  2238. {
  2239. kfree(info->rx_buf);
  2240. info->rx_buf = NULL;
  2241. kfree(info->flag_buf);
  2242. info->flag_buf = NULL;
  2243. }
  2244. static int claim_resources(MGSLPC_INFO *info)
  2245. {
  2246. if (rx_alloc_buffers(info) < 0 ) {
  2247. printk( "Can't allocate rx buffer %s\n", info->device_name);
  2248. release_resources(info);
  2249. return -ENODEV;
  2250. }
  2251. return 0;
  2252. }
  2253. static void release_resources(MGSLPC_INFO *info)
  2254. {
  2255. if (debug_level >= DEBUG_LEVEL_INFO)
  2256. printk("release_resources(%s)\n", info->device_name);
  2257. rx_free_buffers(info);
  2258. }
  2259. /* Add the specified device instance data structure to the
  2260. * global linked list of devices and increment the device count.
  2261. *
  2262. * Arguments: info pointer to device instance data
  2263. */
  2264. static void mgslpc_add_device(MGSLPC_INFO *info)
  2265. {
  2266. info->next_device = NULL;
  2267. info->line = mgslpc_device_count;
  2268. sprintf(info->device_name,"ttySLP%d",info->line);
  2269. if (info->line < MAX_DEVICE_COUNT) {
  2270. if (maxframe[info->line])
  2271. info->max_frame_size = maxframe[info->line];
  2272. }
  2273. mgslpc_device_count++;
  2274. if (!mgslpc_device_list)
  2275. mgslpc_device_list = info;
  2276. else {
  2277. MGSLPC_INFO *current_dev = mgslpc_device_list;
  2278. while( current_dev->next_device )
  2279. current_dev = current_dev->next_device;
  2280. current_dev->next_device = info;
  2281. }
  2282. if (info->max_frame_size < 4096)
  2283. info->max_frame_size = 4096;
  2284. else if (info->max_frame_size > 65535)
  2285. info->max_frame_size = 65535;
  2286. printk( "SyncLink PC Card %s:IO=%04X IRQ=%d\n",
  2287. info->device_name, info->io_base, info->irq_level);
  2288. #if SYNCLINK_GENERIC_HDLC
  2289. hdlcdev_init(info);
  2290. #endif
  2291. tty_port_register_device(&info->port, serial_driver, info->line,
  2292. &info->p_dev->dev);
  2293. }
  2294. static void mgslpc_remove_device(MGSLPC_INFO *remove_info)
  2295. {
  2296. MGSLPC_INFO *info = mgslpc_device_list;
  2297. MGSLPC_INFO *last = NULL;
  2298. while(info) {
  2299. if (info == remove_info) {
  2300. if (last)
  2301. last->next_device = info->next_device;
  2302. else
  2303. mgslpc_device_list = info->next_device;
  2304. tty_unregister_device(serial_driver, info->line);
  2305. #if SYNCLINK_GENERIC_HDLC
  2306. hdlcdev_exit(info);
  2307. #endif
  2308. release_resources(info);
  2309. tty_port_destroy(&info->port);
  2310. kfree(info);
  2311. mgslpc_device_count--;
  2312. return;
  2313. }
  2314. last = info;
  2315. info = info->next_device;
  2316. }
  2317. }
  2318. static const struct pcmcia_device_id mgslpc_ids[] = {
  2319. PCMCIA_DEVICE_MANF_CARD(0x02c5, 0x0050),
  2320. PCMCIA_DEVICE_NULL
  2321. };
  2322. MODULE_DEVICE_TABLE(pcmcia, mgslpc_ids);
  2323. static struct pcmcia_driver mgslpc_driver = {
  2324. .owner = THIS_MODULE,
  2325. .name = "synclink_cs",
  2326. .probe = mgslpc_probe,
  2327. .remove = mgslpc_detach,
  2328. .id_table = mgslpc_ids,
  2329. .suspend = mgslpc_suspend,
  2330. .resume = mgslpc_resume,
  2331. };
  2332. static const struct tty_operations mgslpc_ops = {
  2333. .open = mgslpc_open,
  2334. .close = mgslpc_close,
  2335. .write = mgslpc_write,
  2336. .put_char = mgslpc_put_char,
  2337. .flush_chars = mgslpc_flush_chars,
  2338. .write_room = mgslpc_write_room,
  2339. .chars_in_buffer = mgslpc_chars_in_buffer,
  2340. .flush_buffer = mgslpc_flush_buffer,
  2341. .ioctl = mgslpc_ioctl,
  2342. .throttle = mgslpc_throttle,
  2343. .unthrottle = mgslpc_unthrottle,
  2344. .send_xchar = mgslpc_send_xchar,
  2345. .break_ctl = mgslpc_break,
  2346. .wait_until_sent = mgslpc_wait_until_sent,
  2347. .set_termios = mgslpc_set_termios,
  2348. .stop = tx_pause,
  2349. .start = tx_release,
  2350. .hangup = mgslpc_hangup,
  2351. .tiocmget = tiocmget,
  2352. .tiocmset = tiocmset,
  2353. .get_icount = mgslpc_get_icount,
  2354. .proc_fops = &mgslpc_proc_fops,
  2355. };
  2356. static int __init synclink_cs_init(void)
  2357. {
  2358. int rc;
  2359. if (break_on_load) {
  2360. mgslpc_get_text_ptr();
  2361. BREAKPOINT();
  2362. }
  2363. serial_driver = tty_alloc_driver(MAX_DEVICE_COUNT,
  2364. TTY_DRIVER_REAL_RAW |
  2365. TTY_DRIVER_DYNAMIC_DEV);
  2366. if (IS_ERR(serial_driver)) {
  2367. rc = PTR_ERR(serial_driver);
  2368. goto err;
  2369. }
  2370. /* Initialize the tty_driver structure */
  2371. serial_driver->driver_name = "synclink_cs";
  2372. serial_driver->name = "ttySLP";
  2373. serial_driver->major = ttymajor;
  2374. serial_driver->minor_start = 64;
  2375. serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
  2376. serial_driver->subtype = SERIAL_TYPE_NORMAL;
  2377. serial_driver->init_termios = tty_std_termios;
  2378. serial_driver->init_termios.c_cflag =
  2379. B9600 | CS8 | CREAD | HUPCL | CLOCAL;
  2380. tty_set_operations(serial_driver, &mgslpc_ops);
  2381. rc = tty_register_driver(serial_driver);
  2382. if (rc < 0) {
  2383. printk(KERN_ERR "%s(%d):Couldn't register serial driver\n",
  2384. __FILE__, __LINE__);
  2385. goto err_put_tty;
  2386. }
  2387. rc = pcmcia_register_driver(&mgslpc_driver);
  2388. if (rc < 0)
  2389. goto err_unreg_tty;
  2390. printk(KERN_INFO "%s %s, tty major#%d\n", driver_name, driver_version,
  2391. serial_driver->major);
  2392. return 0;
  2393. err_unreg_tty:
  2394. tty_unregister_driver(serial_driver);
  2395. err_put_tty:
  2396. put_tty_driver(serial_driver);
  2397. err:
  2398. return rc;
  2399. }
  2400. static void __exit synclink_cs_exit(void)
  2401. {
  2402. pcmcia_unregister_driver(&mgslpc_driver);
  2403. tty_unregister_driver(serial_driver);
  2404. put_tty_driver(serial_driver);
  2405. }
  2406. module_init(synclink_cs_init);
  2407. module_exit(synclink_cs_exit);
  2408. static void mgslpc_set_rate(MGSLPC_INFO *info, unsigned char channel, unsigned int rate)
  2409. {
  2410. unsigned int M, N;
  2411. unsigned char val;
  2412. /* note:standard BRG mode is broken in V3.2 chip
  2413. * so enhanced mode is always used
  2414. */
  2415. if (rate) {
  2416. N = 3686400 / rate;
  2417. if (!N)
  2418. N = 1;
  2419. N >>= 1;
  2420. for (M = 1; N > 64 && M < 16; M++)
  2421. N >>= 1;
  2422. N--;
  2423. /* BGR[5..0] = N
  2424. * BGR[9..6] = M
  2425. * BGR[7..0] contained in BGR register
  2426. * BGR[9..8] contained in CCR2[7..6]
  2427. * divisor = (N+1)*2^M
  2428. *
  2429. * Note: M *must* not be zero (causes asymetric duty cycle)
  2430. */
  2431. write_reg(info, (unsigned char) (channel + BGR),
  2432. (unsigned char) ((M << 6) + N));
  2433. val = read_reg(info, (unsigned char) (channel + CCR2)) & 0x3f;
  2434. val |= ((M << 4) & 0xc0);
  2435. write_reg(info, (unsigned char) (channel + CCR2), val);
  2436. }
  2437. }
  2438. /* Enabled the AUX clock output at the specified frequency.
  2439. */
  2440. static void enable_auxclk(MGSLPC_INFO *info)
  2441. {
  2442. unsigned char val;
  2443. /* MODE
  2444. *
  2445. * 07..06 MDS[1..0] 10 = transparent HDLC mode
  2446. * 05 ADM Address Mode, 0 = no addr recognition
  2447. * 04 TMD Timer Mode, 0 = external
  2448. * 03 RAC Receiver Active, 0 = inactive
  2449. * 02 RTS 0=RTS active during xmit, 1=RTS always active
  2450. * 01 TRS Timer Resolution, 1=512
  2451. * 00 TLP Test Loop, 0 = no loop
  2452. *
  2453. * 1000 0010
  2454. */
  2455. val = 0x82;
  2456. /* channel B RTS is used to enable AUXCLK driver on SP505 */
  2457. if (info->params.mode == MGSL_MODE_HDLC && info->params.clock_speed)
  2458. val |= BIT2;
  2459. write_reg(info, CHB + MODE, val);
  2460. /* CCR0
  2461. *
  2462. * 07 PU Power Up, 1=active, 0=power down
  2463. * 06 MCE Master Clock Enable, 1=enabled
  2464. * 05 Reserved, 0
  2465. * 04..02 SC[2..0] Encoding
  2466. * 01..00 SM[1..0] Serial Mode, 00=HDLC
  2467. *
  2468. * 11000000
  2469. */
  2470. write_reg(info, CHB + CCR0, 0xc0);
  2471. /* CCR1
  2472. *
  2473. * 07 SFLG Shared Flag, 0 = disable shared flags
  2474. * 06 GALP Go Active On Loop, 0 = not used
  2475. * 05 GLP Go On Loop, 0 = not used
  2476. * 04 ODS Output Driver Select, 1=TxD is push-pull output
  2477. * 03 ITF Interframe Time Fill, 0=mark, 1=flag
  2478. * 02..00 CM[2..0] Clock Mode
  2479. *
  2480. * 0001 0111
  2481. */
  2482. write_reg(info, CHB + CCR1, 0x17);
  2483. /* CCR2 (Channel B)
  2484. *
  2485. * 07..06 BGR[9..8] Baud rate bits 9..8
  2486. * 05 BDF Baud rate divisor factor, 0=1, 1=BGR value
  2487. * 04 SSEL Clock source select, 1=submode b
  2488. * 03 TOE 0=TxCLK is input, 1=TxCLK is output
  2489. * 02 RWX Read/Write Exchange 0=disabled
  2490. * 01 C32, CRC select, 0=CRC-16, 1=CRC-32
  2491. * 00 DIV, data inversion 0=disabled, 1=enabled
  2492. *
  2493. * 0011 1000
  2494. */
  2495. if (info->params.mode == MGSL_MODE_HDLC && info->params.clock_speed)
  2496. write_reg(info, CHB + CCR2, 0x38);
  2497. else
  2498. write_reg(info, CHB + CCR2, 0x30);
  2499. /* CCR4
  2500. *
  2501. * 07 MCK4 Master Clock Divide by 4, 1=enabled
  2502. * 06 EBRG Enhanced Baud Rate Generator Mode, 1=enabled
  2503. * 05 TST1 Test Pin, 0=normal operation
  2504. * 04 ICD Ivert Carrier Detect, 1=enabled (active low)
  2505. * 03..02 Reserved, must be 0
  2506. * 01..00 RFT[1..0] RxFIFO Threshold 00=32 bytes
  2507. *
  2508. * 0101 0000
  2509. */
  2510. write_reg(info, CHB + CCR4, 0x50);
  2511. /* if auxclk not enabled, set internal BRG so
  2512. * CTS transitions can be detected (requires TxC)
  2513. */
  2514. if (info->params.mode == MGSL_MODE_HDLC && info->params.clock_speed)
  2515. mgslpc_set_rate(info, CHB, info->params.clock_speed);
  2516. else
  2517. mgslpc_set_rate(info, CHB, 921600);
  2518. }
  2519. static void loopback_enable(MGSLPC_INFO *info)
  2520. {
  2521. unsigned char val;
  2522. /* CCR1:02..00 CM[2..0] Clock Mode = 111 (clock mode 7) */
  2523. val = read_reg(info, CHA + CCR1) | (BIT2 + BIT1 + BIT0);
  2524. write_reg(info, CHA + CCR1, val);
  2525. /* CCR2:04 SSEL Clock source select, 1=submode b */
  2526. val = read_reg(info, CHA + CCR2) | (BIT4 + BIT5);
  2527. write_reg(info, CHA + CCR2, val);
  2528. /* set LinkSpeed if available, otherwise default to 2Mbps */
  2529. if (info->params.clock_speed)
  2530. mgslpc_set_rate(info, CHA, info->params.clock_speed);
  2531. else
  2532. mgslpc_set_rate(info, CHA, 1843200);
  2533. /* MODE:00 TLP Test Loop, 1=loopback enabled */
  2534. val = read_reg(info, CHA + MODE) | BIT0;
  2535. write_reg(info, CHA + MODE, val);
  2536. }
  2537. static void hdlc_mode(MGSLPC_INFO *info)
  2538. {
  2539. unsigned char val;
  2540. unsigned char clkmode, clksubmode;
  2541. /* disable all interrupts */
  2542. irq_disable(info, CHA, 0xffff);
  2543. irq_disable(info, CHB, 0xffff);
  2544. port_irq_disable(info, 0xff);
  2545. /* assume clock mode 0a, rcv=RxC xmt=TxC */
  2546. clkmode = clksubmode = 0;
  2547. if (info->params.flags & HDLC_FLAG_RXC_DPLL
  2548. && info->params.flags & HDLC_FLAG_TXC_DPLL) {
  2549. /* clock mode 7a, rcv = DPLL, xmt = DPLL */
  2550. clkmode = 7;
  2551. } else if (info->params.flags & HDLC_FLAG_RXC_BRG
  2552. && info->params.flags & HDLC_FLAG_TXC_BRG) {
  2553. /* clock mode 7b, rcv = BRG, xmt = BRG */
  2554. clkmode = 7;
  2555. clksubmode = 1;
  2556. } else if (info->params.flags & HDLC_FLAG_RXC_DPLL) {
  2557. if (info->params.flags & HDLC_FLAG_TXC_BRG) {
  2558. /* clock mode 6b, rcv = DPLL, xmt = BRG/16 */
  2559. clkmode = 6;
  2560. clksubmode = 1;
  2561. } else {
  2562. /* clock mode 6a, rcv = DPLL, xmt = TxC */
  2563. clkmode = 6;
  2564. }
  2565. } else if (info->params.flags & HDLC_FLAG_TXC_BRG) {
  2566. /* clock mode 0b, rcv = RxC, xmt = BRG */
  2567. clksubmode = 1;
  2568. }
  2569. /* MODE
  2570. *
  2571. * 07..06 MDS[1..0] 10 = transparent HDLC mode
  2572. * 05 ADM Address Mode, 0 = no addr recognition
  2573. * 04 TMD Timer Mode, 0 = external
  2574. * 03 RAC Receiver Active, 0 = inactive
  2575. * 02 RTS 0=RTS active during xmit, 1=RTS always active
  2576. * 01 TRS Timer Resolution, 1=512
  2577. * 00 TLP Test Loop, 0 = no loop
  2578. *
  2579. * 1000 0010
  2580. */
  2581. val = 0x82;
  2582. if (info->params.loopback)
  2583. val |= BIT0;
  2584. /* preserve RTS state */
  2585. if (info->serial_signals & SerialSignal_RTS)
  2586. val |= BIT2;
  2587. write_reg(info, CHA + MODE, val);
  2588. /* CCR0
  2589. *
  2590. * 07 PU Power Up, 1=active, 0=power down
  2591. * 06 MCE Master Clock Enable, 1=enabled
  2592. * 05 Reserved, 0
  2593. * 04..02 SC[2..0] Encoding
  2594. * 01..00 SM[1..0] Serial Mode, 00=HDLC
  2595. *
  2596. * 11000000
  2597. */
  2598. val = 0xc0;
  2599. switch (info->params.encoding)
  2600. {
  2601. case HDLC_ENCODING_NRZI:
  2602. val |= BIT3;
  2603. break;
  2604. case HDLC_ENCODING_BIPHASE_SPACE:
  2605. val |= BIT4;
  2606. break; // FM0
  2607. case HDLC_ENCODING_BIPHASE_MARK:
  2608. val |= BIT4 + BIT2;
  2609. break; // FM1
  2610. case HDLC_ENCODING_BIPHASE_LEVEL:
  2611. val |= BIT4 + BIT3;
  2612. break; // Manchester
  2613. }
  2614. write_reg(info, CHA + CCR0, val);
  2615. /* CCR1
  2616. *
  2617. * 07 SFLG Shared Flag, 0 = disable shared flags
  2618. * 06 GALP Go Active On Loop, 0 = not used
  2619. * 05 GLP Go On Loop, 0 = not used
  2620. * 04 ODS Output Driver Select, 1=TxD is push-pull output
  2621. * 03 ITF Interframe Time Fill, 0=mark, 1=flag
  2622. * 02..00 CM[2..0] Clock Mode
  2623. *
  2624. * 0001 0000
  2625. */
  2626. val = 0x10 + clkmode;
  2627. write_reg(info, CHA + CCR1, val);
  2628. /* CCR2
  2629. *
  2630. * 07..06 BGR[9..8] Baud rate bits 9..8
  2631. * 05 BDF Baud rate divisor factor, 0=1, 1=BGR value
  2632. * 04 SSEL Clock source select, 1=submode b
  2633. * 03 TOE 0=TxCLK is input, 0=TxCLK is input
  2634. * 02 RWX Read/Write Exchange 0=disabled
  2635. * 01 C32, CRC select, 0=CRC-16, 1=CRC-32
  2636. * 00 DIV, data inversion 0=disabled, 1=enabled
  2637. *
  2638. * 0000 0000
  2639. */
  2640. val = 0x00;
  2641. if (clkmode == 2 || clkmode == 3 || clkmode == 6
  2642. || clkmode == 7 || (clkmode == 0 && clksubmode == 1))
  2643. val |= BIT5;
  2644. if (clksubmode)
  2645. val |= BIT4;
  2646. if (info->params.crc_type == HDLC_CRC_32_CCITT)
  2647. val |= BIT1;
  2648. if (info->params.encoding == HDLC_ENCODING_NRZB)
  2649. val |= BIT0;
  2650. write_reg(info, CHA + CCR2, val);
  2651. /* CCR3
  2652. *
  2653. * 07..06 PRE[1..0] Preamble count 00=1, 01=2, 10=4, 11=8
  2654. * 05 EPT Enable preamble transmission, 1=enabled
  2655. * 04 RADD Receive address pushed to FIFO, 0=disabled
  2656. * 03 CRL CRC Reset Level, 0=FFFF
  2657. * 02 RCRC Rx CRC 0=On 1=Off
  2658. * 01 TCRC Tx CRC 0=On 1=Off
  2659. * 00 PSD DPLL Phase Shift Disable
  2660. *
  2661. * 0000 0000
  2662. */
  2663. val = 0x00;
  2664. if (info->params.crc_type == HDLC_CRC_NONE)
  2665. val |= BIT2 + BIT1;
  2666. if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE)
  2667. val |= BIT5;
  2668. switch (info->params.preamble_length)
  2669. {
  2670. case HDLC_PREAMBLE_LENGTH_16BITS:
  2671. val |= BIT6;
  2672. break;
  2673. case HDLC_PREAMBLE_LENGTH_32BITS:
  2674. val |= BIT6;
  2675. break;
  2676. case HDLC_PREAMBLE_LENGTH_64BITS:
  2677. val |= BIT7 + BIT6;
  2678. break;
  2679. }
  2680. write_reg(info, CHA + CCR3, val);
  2681. /* PRE - Preamble pattern */
  2682. val = 0;
  2683. switch (info->params.preamble)
  2684. {
  2685. case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break;
  2686. case HDLC_PREAMBLE_PATTERN_10: val = 0xaa; break;
  2687. case HDLC_PREAMBLE_PATTERN_01: val = 0x55; break;
  2688. case HDLC_PREAMBLE_PATTERN_ONES: val = 0xff; break;
  2689. }
  2690. write_reg(info, CHA + PRE, val);
  2691. /* CCR4
  2692. *
  2693. * 07 MCK4 Master Clock Divide by 4, 1=enabled
  2694. * 06 EBRG Enhanced Baud Rate Generator Mode, 1=enabled
  2695. * 05 TST1 Test Pin, 0=normal operation
  2696. * 04 ICD Ivert Carrier Detect, 1=enabled (active low)
  2697. * 03..02 Reserved, must be 0
  2698. * 01..00 RFT[1..0] RxFIFO Threshold 00=32 bytes
  2699. *
  2700. * 0101 0000
  2701. */
  2702. val = 0x50;
  2703. write_reg(info, CHA + CCR4, val);
  2704. if (info->params.flags & HDLC_FLAG_RXC_DPLL)
  2705. mgslpc_set_rate(info, CHA, info->params.clock_speed * 16);
  2706. else
  2707. mgslpc_set_rate(info, CHA, info->params.clock_speed);
  2708. /* RLCR Receive length check register
  2709. *
  2710. * 7 1=enable receive length check
  2711. * 6..0 Max frame length = (RL + 1) * 32
  2712. */
  2713. write_reg(info, CHA + RLCR, 0);
  2714. /* XBCH Transmit Byte Count High
  2715. *
  2716. * 07 DMA mode, 0 = interrupt driven
  2717. * 06 NRM, 0=ABM (ignored)
  2718. * 05 CAS Carrier Auto Start
  2719. * 04 XC Transmit Continuously (ignored)
  2720. * 03..00 XBC[10..8] Transmit byte count bits 10..8
  2721. *
  2722. * 0000 0000
  2723. */
  2724. val = 0x00;
  2725. if (info->params.flags & HDLC_FLAG_AUTO_DCD)
  2726. val |= BIT5;
  2727. write_reg(info, CHA + XBCH, val);
  2728. enable_auxclk(info);
  2729. if (info->params.loopback || info->testing_irq)
  2730. loopback_enable(info);
  2731. if (info->params.flags & HDLC_FLAG_AUTO_CTS)
  2732. {
  2733. irq_enable(info, CHB, IRQ_CTS);
  2734. /* PVR[3] 1=AUTO CTS active */
  2735. set_reg_bits(info, CHA + PVR, BIT3);
  2736. } else
  2737. clear_reg_bits(info, CHA + PVR, BIT3);
  2738. irq_enable(info, CHA,
  2739. IRQ_RXEOM + IRQ_RXFIFO + IRQ_ALLSENT +
  2740. IRQ_UNDERRUN + IRQ_TXFIFO);
  2741. issue_command(info, CHA, CMD_TXRESET + CMD_RXRESET);
  2742. wait_command_complete(info, CHA);
  2743. read_reg16(info, CHA + ISR); /* clear pending IRQs */
  2744. /* Master clock mode enabled above to allow reset commands
  2745. * to complete even if no data clocks are present.
  2746. *
  2747. * Disable master clock mode for normal communications because
  2748. * V3.2 of the ESCC2 has a bug that prevents the transmit all sent
  2749. * IRQ when in master clock mode.
  2750. *
  2751. * Leave master clock mode enabled for IRQ test because the
  2752. * timer IRQ used by the test can only happen in master clock mode.
  2753. */
  2754. if (!info->testing_irq)
  2755. clear_reg_bits(info, CHA + CCR0, BIT6);
  2756. tx_set_idle(info);
  2757. tx_stop(info);
  2758. rx_stop(info);
  2759. }
  2760. static void rx_stop(MGSLPC_INFO *info)
  2761. {
  2762. if (debug_level >= DEBUG_LEVEL_ISR)
  2763. printk("%s(%d):rx_stop(%s)\n",
  2764. __FILE__,__LINE__, info->device_name );
  2765. /* MODE:03 RAC Receiver Active, 0=inactive */
  2766. clear_reg_bits(info, CHA + MODE, BIT3);
  2767. info->rx_enabled = false;
  2768. info->rx_overflow = false;
  2769. }
  2770. static void rx_start(MGSLPC_INFO *info)
  2771. {
  2772. if (debug_level >= DEBUG_LEVEL_ISR)
  2773. printk("%s(%d):rx_start(%s)\n",
  2774. __FILE__,__LINE__, info->device_name );
  2775. rx_reset_buffers(info);
  2776. info->rx_enabled = false;
  2777. info->rx_overflow = false;
  2778. /* MODE:03 RAC Receiver Active, 1=active */
  2779. set_reg_bits(info, CHA + MODE, BIT3);
  2780. info->rx_enabled = true;
  2781. }
  2782. static void tx_start(MGSLPC_INFO *info, struct tty_struct *tty)
  2783. {
  2784. if (debug_level >= DEBUG_LEVEL_ISR)
  2785. printk("%s(%d):tx_start(%s)\n",
  2786. __FILE__,__LINE__, info->device_name );
  2787. if (info->tx_count) {
  2788. /* If auto RTS enabled and RTS is inactive, then assert */
  2789. /* RTS and set a flag indicating that the driver should */
  2790. /* negate RTS when the transmission completes. */
  2791. info->drop_rts_on_tx_done = false;
  2792. if (info->params.flags & HDLC_FLAG_AUTO_RTS) {
  2793. get_signals(info);
  2794. if (!(info->serial_signals & SerialSignal_RTS)) {
  2795. info->serial_signals |= SerialSignal_RTS;
  2796. set_signals(info);
  2797. info->drop_rts_on_tx_done = true;
  2798. }
  2799. }
  2800. if (info->params.mode == MGSL_MODE_ASYNC) {
  2801. if (!info->tx_active) {
  2802. info->tx_active = true;
  2803. tx_ready(info, tty);
  2804. }
  2805. } else {
  2806. info->tx_active = true;
  2807. tx_ready(info, tty);
  2808. mod_timer(&info->tx_timer, jiffies +
  2809. msecs_to_jiffies(5000));
  2810. }
  2811. }
  2812. if (!info->tx_enabled)
  2813. info->tx_enabled = true;
  2814. }
  2815. static void tx_stop(MGSLPC_INFO *info)
  2816. {
  2817. if (debug_level >= DEBUG_LEVEL_ISR)
  2818. printk("%s(%d):tx_stop(%s)\n",
  2819. __FILE__,__LINE__, info->device_name );
  2820. del_timer(&info->tx_timer);
  2821. info->tx_enabled = false;
  2822. info->tx_active = false;
  2823. }
  2824. /* Reset the adapter to a known state and prepare it for further use.
  2825. */
  2826. static void reset_device(MGSLPC_INFO *info)
  2827. {
  2828. /* power up both channels (set BIT7) */
  2829. write_reg(info, CHA + CCR0, 0x80);
  2830. write_reg(info, CHB + CCR0, 0x80);
  2831. write_reg(info, CHA + MODE, 0);
  2832. write_reg(info, CHB + MODE, 0);
  2833. /* disable all interrupts */
  2834. irq_disable(info, CHA, 0xffff);
  2835. irq_disable(info, CHB, 0xffff);
  2836. port_irq_disable(info, 0xff);
  2837. /* PCR Port Configuration Register
  2838. *
  2839. * 07..04 DEC[3..0] Serial I/F select outputs
  2840. * 03 output, 1=AUTO CTS control enabled
  2841. * 02 RI Ring Indicator input 0=active
  2842. * 01 DSR input 0=active
  2843. * 00 DTR output 0=active
  2844. *
  2845. * 0000 0110
  2846. */
  2847. write_reg(info, PCR, 0x06);
  2848. /* PVR Port Value Register
  2849. *
  2850. * 07..04 DEC[3..0] Serial I/F select (0000=disabled)
  2851. * 03 AUTO CTS output 1=enabled
  2852. * 02 RI Ring Indicator input
  2853. * 01 DSR input
  2854. * 00 DTR output (1=inactive)
  2855. *
  2856. * 0000 0001
  2857. */
  2858. // write_reg(info, PVR, PVR_DTR);
  2859. /* IPC Interrupt Port Configuration
  2860. *
  2861. * 07 VIS 1=Masked interrupts visible
  2862. * 06..05 Reserved, 0
  2863. * 04..03 SLA Slave address, 00 ignored
  2864. * 02 CASM Cascading Mode, 1=daisy chain
  2865. * 01..00 IC[1..0] Interrupt Config, 01=push-pull output, active low
  2866. *
  2867. * 0000 0101
  2868. */
  2869. write_reg(info, IPC, 0x05);
  2870. }
  2871. static void async_mode(MGSLPC_INFO *info)
  2872. {
  2873. unsigned char val;
  2874. /* disable all interrupts */
  2875. irq_disable(info, CHA, 0xffff);
  2876. irq_disable(info, CHB, 0xffff);
  2877. port_irq_disable(info, 0xff);
  2878. /* MODE
  2879. *
  2880. * 07 Reserved, 0
  2881. * 06 FRTS RTS State, 0=active
  2882. * 05 FCTS Flow Control on CTS
  2883. * 04 FLON Flow Control Enable
  2884. * 03 RAC Receiver Active, 0 = inactive
  2885. * 02 RTS 0=Auto RTS, 1=manual RTS
  2886. * 01 TRS Timer Resolution, 1=512
  2887. * 00 TLP Test Loop, 0 = no loop
  2888. *
  2889. * 0000 0110
  2890. */
  2891. val = 0x06;
  2892. if (info->params.loopback)
  2893. val |= BIT0;
  2894. /* preserve RTS state */
  2895. if (!(info->serial_signals & SerialSignal_RTS))
  2896. val |= BIT6;
  2897. write_reg(info, CHA + MODE, val);
  2898. /* CCR0
  2899. *
  2900. * 07 PU Power Up, 1=active, 0=power down
  2901. * 06 MCE Master Clock Enable, 1=enabled
  2902. * 05 Reserved, 0
  2903. * 04..02 SC[2..0] Encoding, 000=NRZ
  2904. * 01..00 SM[1..0] Serial Mode, 11=Async
  2905. *
  2906. * 1000 0011
  2907. */
  2908. write_reg(info, CHA + CCR0, 0x83);
  2909. /* CCR1
  2910. *
  2911. * 07..05 Reserved, 0
  2912. * 04 ODS Output Driver Select, 1=TxD is push-pull output
  2913. * 03 BCR Bit Clock Rate, 1=16x
  2914. * 02..00 CM[2..0] Clock Mode, 111=BRG
  2915. *
  2916. * 0001 1111
  2917. */
  2918. write_reg(info, CHA + CCR1, 0x1f);
  2919. /* CCR2 (channel A)
  2920. *
  2921. * 07..06 BGR[9..8] Baud rate bits 9..8
  2922. * 05 BDF Baud rate divisor factor, 0=1, 1=BGR value
  2923. * 04 SSEL Clock source select, 1=submode b
  2924. * 03 TOE 0=TxCLK is input, 0=TxCLK is input
  2925. * 02 RWX Read/Write Exchange 0=disabled
  2926. * 01 Reserved, 0
  2927. * 00 DIV, data inversion 0=disabled, 1=enabled
  2928. *
  2929. * 0001 0000
  2930. */
  2931. write_reg(info, CHA + CCR2, 0x10);
  2932. /* CCR3
  2933. *
  2934. * 07..01 Reserved, 0
  2935. * 00 PSD DPLL Phase Shift Disable
  2936. *
  2937. * 0000 0000
  2938. */
  2939. write_reg(info, CHA + CCR3, 0);
  2940. /* CCR4
  2941. *
  2942. * 07 MCK4 Master Clock Divide by 4, 1=enabled
  2943. * 06 EBRG Enhanced Baud Rate Generator Mode, 1=enabled
  2944. * 05 TST1 Test Pin, 0=normal operation
  2945. * 04 ICD Ivert Carrier Detect, 1=enabled (active low)
  2946. * 03..00 Reserved, must be 0
  2947. *
  2948. * 0101 0000
  2949. */
  2950. write_reg(info, CHA + CCR4, 0x50);
  2951. mgslpc_set_rate(info, CHA, info->params.data_rate * 16);
  2952. /* DAFO Data Format
  2953. *
  2954. * 07 Reserved, 0
  2955. * 06 XBRK transmit break, 0=normal operation
  2956. * 05 Stop bits (0=1, 1=2)
  2957. * 04..03 PAR[1..0] Parity (01=odd, 10=even)
  2958. * 02 PAREN Parity Enable
  2959. * 01..00 CHL[1..0] Character Length (00=8, 01=7)
  2960. *
  2961. */
  2962. val = 0x00;
  2963. if (info->params.data_bits != 8)
  2964. val |= BIT0; /* 7 bits */
  2965. if (info->params.stop_bits != 1)
  2966. val |= BIT5;
  2967. if (info->params.parity != ASYNC_PARITY_NONE)
  2968. {
  2969. val |= BIT2; /* Parity enable */
  2970. if (info->params.parity == ASYNC_PARITY_ODD)
  2971. val |= BIT3;
  2972. else
  2973. val |= BIT4;
  2974. }
  2975. write_reg(info, CHA + DAFO, val);
  2976. /* RFC Rx FIFO Control
  2977. *
  2978. * 07 Reserved, 0
  2979. * 06 DPS, 1=parity bit not stored in data byte
  2980. * 05 DXS, 0=all data stored in FIFO (including XON/XOFF)
  2981. * 04 RFDF Rx FIFO Data Format, 1=status byte stored in FIFO
  2982. * 03..02 RFTH[1..0], rx threshold, 11=16 status + 16 data byte
  2983. * 01 Reserved, 0
  2984. * 00 TCDE Terminate Char Detect Enable, 0=disabled
  2985. *
  2986. * 0101 1100
  2987. */
  2988. write_reg(info, CHA + RFC, 0x5c);
  2989. /* RLCR Receive length check register
  2990. *
  2991. * Max frame length = (RL + 1) * 32
  2992. */
  2993. write_reg(info, CHA + RLCR, 0);
  2994. /* XBCH Transmit Byte Count High
  2995. *
  2996. * 07 DMA mode, 0 = interrupt driven
  2997. * 06 NRM, 0=ABM (ignored)
  2998. * 05 CAS Carrier Auto Start
  2999. * 04 XC Transmit Continuously (ignored)
  3000. * 03..00 XBC[10..8] Transmit byte count bits 10..8
  3001. *
  3002. * 0000 0000
  3003. */
  3004. val = 0x00;
  3005. if (info->params.flags & HDLC_FLAG_AUTO_DCD)
  3006. val |= BIT5;
  3007. write_reg(info, CHA + XBCH, val);
  3008. if (info->params.flags & HDLC_FLAG_AUTO_CTS)
  3009. irq_enable(info, CHA, IRQ_CTS);
  3010. /* MODE:03 RAC Receiver Active, 1=active */
  3011. set_reg_bits(info, CHA + MODE, BIT3);
  3012. enable_auxclk(info);
  3013. if (info->params.flags & HDLC_FLAG_AUTO_CTS) {
  3014. irq_enable(info, CHB, IRQ_CTS);
  3015. /* PVR[3] 1=AUTO CTS active */
  3016. set_reg_bits(info, CHA + PVR, BIT3);
  3017. } else
  3018. clear_reg_bits(info, CHA + PVR, BIT3);
  3019. irq_enable(info, CHA,
  3020. IRQ_RXEOM + IRQ_RXFIFO + IRQ_BREAK_ON + IRQ_RXTIME +
  3021. IRQ_ALLSENT + IRQ_TXFIFO);
  3022. issue_command(info, CHA, CMD_TXRESET + CMD_RXRESET);
  3023. wait_command_complete(info, CHA);
  3024. read_reg16(info, CHA + ISR); /* clear pending IRQs */
  3025. }
  3026. /* Set the HDLC idle mode for the transmitter.
  3027. */
  3028. static void tx_set_idle(MGSLPC_INFO *info)
  3029. {
  3030. /* Note: ESCC2 only supports flags and one idle modes */
  3031. if (info->idle_mode == HDLC_TXIDLE_FLAGS)
  3032. set_reg_bits(info, CHA + CCR1, BIT3);
  3033. else
  3034. clear_reg_bits(info, CHA + CCR1, BIT3);
  3035. }
  3036. /* get state of the V24 status (input) signals.
  3037. */
  3038. static void get_signals(MGSLPC_INFO *info)
  3039. {
  3040. unsigned char status = 0;
  3041. /* preserve DTR and RTS */
  3042. info->serial_signals &= SerialSignal_DTR + SerialSignal_RTS;
  3043. if (read_reg(info, CHB + VSTR) & BIT7)
  3044. info->serial_signals |= SerialSignal_DCD;
  3045. if (read_reg(info, CHB + STAR) & BIT1)
  3046. info->serial_signals |= SerialSignal_CTS;
  3047. status = read_reg(info, CHA + PVR);
  3048. if (!(status & PVR_RI))
  3049. info->serial_signals |= SerialSignal_RI;
  3050. if (!(status & PVR_DSR))
  3051. info->serial_signals |= SerialSignal_DSR;
  3052. }
  3053. /* Set the state of DTR and RTS based on contents of
  3054. * serial_signals member of device extension.
  3055. */
  3056. static void set_signals(MGSLPC_INFO *info)
  3057. {
  3058. unsigned char val;
  3059. val = read_reg(info, CHA + MODE);
  3060. if (info->params.mode == MGSL_MODE_ASYNC) {
  3061. if (info->serial_signals & SerialSignal_RTS)
  3062. val &= ~BIT6;
  3063. else
  3064. val |= BIT6;
  3065. } else {
  3066. if (info->serial_signals & SerialSignal_RTS)
  3067. val |= BIT2;
  3068. else
  3069. val &= ~BIT2;
  3070. }
  3071. write_reg(info, CHA + MODE, val);
  3072. if (info->serial_signals & SerialSignal_DTR)
  3073. clear_reg_bits(info, CHA + PVR, PVR_DTR);
  3074. else
  3075. set_reg_bits(info, CHA + PVR, PVR_DTR);
  3076. }
  3077. static void rx_reset_buffers(MGSLPC_INFO *info)
  3078. {
  3079. RXBUF *buf;
  3080. int i;
  3081. info->rx_put = 0;
  3082. info->rx_get = 0;
  3083. info->rx_frame_count = 0;
  3084. for (i=0 ; i < info->rx_buf_count ; i++) {
  3085. buf = (RXBUF*)(info->rx_buf + (i * info->rx_buf_size));
  3086. buf->status = buf->count = 0;
  3087. }
  3088. }
  3089. /* Attempt to return a received HDLC frame
  3090. * Only frames received without errors are returned.
  3091. *
  3092. * Returns true if frame returned, otherwise false
  3093. */
  3094. static bool rx_get_frame(MGSLPC_INFO *info, struct tty_struct *tty)
  3095. {
  3096. unsigned short status;
  3097. RXBUF *buf;
  3098. unsigned int framesize = 0;
  3099. unsigned long flags;
  3100. bool return_frame = false;
  3101. if (info->rx_frame_count == 0)
  3102. return false;
  3103. buf = (RXBUF*)(info->rx_buf + (info->rx_get * info->rx_buf_size));
  3104. status = buf->status;
  3105. /* 07 VFR 1=valid frame
  3106. * 06 RDO 1=data overrun
  3107. * 05 CRC 1=OK, 0=error
  3108. * 04 RAB 1=frame aborted
  3109. */
  3110. if ((status & 0xf0) != 0xA0) {
  3111. if (!(status & BIT7) || (status & BIT4))
  3112. info->icount.rxabort++;
  3113. else if (status & BIT6)
  3114. info->icount.rxover++;
  3115. else if (!(status & BIT5)) {
  3116. info->icount.rxcrc++;
  3117. if (info->params.crc_type & HDLC_CRC_RETURN_EX)
  3118. return_frame = true;
  3119. }
  3120. framesize = 0;
  3121. #if SYNCLINK_GENERIC_HDLC
  3122. {
  3123. info->netdev->stats.rx_errors++;
  3124. info->netdev->stats.rx_frame_errors++;
  3125. }
  3126. #endif
  3127. } else
  3128. return_frame = true;
  3129. if (return_frame)
  3130. framesize = buf->count;
  3131. if (debug_level >= DEBUG_LEVEL_BH)
  3132. printk("%s(%d):rx_get_frame(%s) status=%04X size=%d\n",
  3133. __FILE__,__LINE__,info->device_name,status,framesize);
  3134. if (debug_level >= DEBUG_LEVEL_DATA)
  3135. trace_block(info, buf->data, framesize, 0);
  3136. if (framesize) {
  3137. if ((info->params.crc_type & HDLC_CRC_RETURN_EX &&
  3138. framesize+1 > info->max_frame_size) ||
  3139. framesize > info->max_frame_size)
  3140. info->icount.rxlong++;
  3141. else {
  3142. if (status & BIT5)
  3143. info->icount.rxok++;
  3144. if (info->params.crc_type & HDLC_CRC_RETURN_EX) {
  3145. *(buf->data + framesize) = status & BIT5 ? RX_OK:RX_CRC_ERROR;
  3146. ++framesize;
  3147. }
  3148. #if SYNCLINK_GENERIC_HDLC
  3149. if (info->netcount)
  3150. hdlcdev_rx(info, buf->data, framesize);
  3151. else
  3152. #endif
  3153. ldisc_receive_buf(tty, buf->data, info->flag_buf, framesize);
  3154. }
  3155. }
  3156. spin_lock_irqsave(&info->lock,flags);
  3157. buf->status = buf->count = 0;
  3158. info->rx_frame_count--;
  3159. info->rx_get++;
  3160. if (info->rx_get >= info->rx_buf_count)
  3161. info->rx_get = 0;
  3162. spin_unlock_irqrestore(&info->lock,flags);
  3163. return true;
  3164. }
  3165. static bool register_test(MGSLPC_INFO *info)
  3166. {
  3167. static unsigned char patterns[] =
  3168. { 0x00, 0xff, 0xaa, 0x55, 0x69, 0x96, 0x0f };
  3169. static unsigned int count = ARRAY_SIZE(patterns);
  3170. unsigned int i;
  3171. bool rc = true;
  3172. unsigned long flags;
  3173. spin_lock_irqsave(&info->lock,flags);
  3174. reset_device(info);
  3175. for (i = 0; i < count; i++) {
  3176. write_reg(info, XAD1, patterns[i]);
  3177. write_reg(info, XAD2, patterns[(i + 1) % count]);
  3178. if ((read_reg(info, XAD1) != patterns[i]) ||
  3179. (read_reg(info, XAD2) != patterns[(i + 1) % count])) {
  3180. rc = false;
  3181. break;
  3182. }
  3183. }
  3184. spin_unlock_irqrestore(&info->lock,flags);
  3185. return rc;
  3186. }
  3187. static bool irq_test(MGSLPC_INFO *info)
  3188. {
  3189. unsigned long end_time;
  3190. unsigned long flags;
  3191. spin_lock_irqsave(&info->lock,flags);
  3192. reset_device(info);
  3193. info->testing_irq = true;
  3194. hdlc_mode(info);
  3195. info->irq_occurred = false;
  3196. /* init hdlc mode */
  3197. irq_enable(info, CHA, IRQ_TIMER);
  3198. write_reg(info, CHA + TIMR, 0); /* 512 cycles */
  3199. issue_command(info, CHA, CMD_START_TIMER);
  3200. spin_unlock_irqrestore(&info->lock,flags);
  3201. end_time=100;
  3202. while(end_time-- && !info->irq_occurred) {
  3203. msleep_interruptible(10);
  3204. }
  3205. info->testing_irq = false;
  3206. spin_lock_irqsave(&info->lock,flags);
  3207. reset_device(info);
  3208. spin_unlock_irqrestore(&info->lock,flags);
  3209. return info->irq_occurred;
  3210. }
  3211. static int adapter_test(MGSLPC_INFO *info)
  3212. {
  3213. if (!register_test(info)) {
  3214. info->init_error = DiagStatus_AddressFailure;
  3215. printk( "%s(%d):Register test failure for device %s Addr=%04X\n",
  3216. __FILE__,__LINE__,info->device_name, (unsigned short)(info->io_base) );
  3217. return -ENODEV;
  3218. }
  3219. if (!irq_test(info)) {
  3220. info->init_error = DiagStatus_IrqFailure;
  3221. printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
  3222. __FILE__,__LINE__,info->device_name, (unsigned short)(info->irq_level) );
  3223. return -ENODEV;
  3224. }
  3225. if (debug_level >= DEBUG_LEVEL_INFO)
  3226. printk("%s(%d):device %s passed diagnostics\n",
  3227. __FILE__,__LINE__,info->device_name);
  3228. return 0;
  3229. }
  3230. static void trace_block(MGSLPC_INFO *info,const char* data, int count, int xmit)
  3231. {
  3232. int i;
  3233. int linecount;
  3234. if (xmit)
  3235. printk("%s tx data:\n",info->device_name);
  3236. else
  3237. printk("%s rx data:\n",info->device_name);
  3238. while(count) {
  3239. if (count > 16)
  3240. linecount = 16;
  3241. else
  3242. linecount = count;
  3243. for(i=0;i<linecount;i++)
  3244. printk("%02X ",(unsigned char)data[i]);
  3245. for(;i<17;i++)
  3246. printk(" ");
  3247. for(i=0;i<linecount;i++) {
  3248. if (data[i]>=040 && data[i]<=0176)
  3249. printk("%c",data[i]);
  3250. else
  3251. printk(".");
  3252. }
  3253. printk("\n");
  3254. data += linecount;
  3255. count -= linecount;
  3256. }
  3257. }
  3258. /* HDLC frame time out
  3259. * update stats and do tx completion processing
  3260. */
  3261. static void tx_timeout(unsigned long context)
  3262. {
  3263. MGSLPC_INFO *info = (MGSLPC_INFO*)context;
  3264. unsigned long flags;
  3265. if ( debug_level >= DEBUG_LEVEL_INFO )
  3266. printk( "%s(%d):tx_timeout(%s)\n",
  3267. __FILE__,__LINE__,info->device_name);
  3268. if(info->tx_active &&
  3269. info->params.mode == MGSL_MODE_HDLC) {
  3270. info->icount.txtimeout++;
  3271. }
  3272. spin_lock_irqsave(&info->lock,flags);
  3273. info->tx_active = false;
  3274. info->tx_count = info->tx_put = info->tx_get = 0;
  3275. spin_unlock_irqrestore(&info->lock,flags);
  3276. #if SYNCLINK_GENERIC_HDLC
  3277. if (info->netcount)
  3278. hdlcdev_tx_done(info);
  3279. else
  3280. #endif
  3281. {
  3282. struct tty_struct *tty = tty_port_tty_get(&info->port);
  3283. bh_transmit(info, tty);
  3284. tty_kref_put(tty);
  3285. }
  3286. }
  3287. #if SYNCLINK_GENERIC_HDLC
  3288. /**
  3289. * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
  3290. * set encoding and frame check sequence (FCS) options
  3291. *
  3292. * dev pointer to network device structure
  3293. * encoding serial encoding setting
  3294. * parity FCS setting
  3295. *
  3296. * returns 0 if success, otherwise error code
  3297. */
  3298. static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
  3299. unsigned short parity)
  3300. {
  3301. MGSLPC_INFO *info = dev_to_port(dev);
  3302. struct tty_struct *tty;
  3303. unsigned char new_encoding;
  3304. unsigned short new_crctype;
  3305. /* return error if TTY interface open */
  3306. if (info->port.count)
  3307. return -EBUSY;
  3308. switch (encoding)
  3309. {
  3310. case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
  3311. case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
  3312. case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
  3313. case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
  3314. case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
  3315. default: return -EINVAL;
  3316. }
  3317. switch (parity)
  3318. {
  3319. case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
  3320. case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
  3321. case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
  3322. default: return -EINVAL;
  3323. }
  3324. info->params.encoding = new_encoding;
  3325. info->params.crc_type = new_crctype;
  3326. /* if network interface up, reprogram hardware */
  3327. if (info->netcount) {
  3328. tty = tty_port_tty_get(&info->port);
  3329. mgslpc_program_hw(info, tty);
  3330. tty_kref_put(tty);
  3331. }
  3332. return 0;
  3333. }
  3334. /**
  3335. * called by generic HDLC layer to send frame
  3336. *
  3337. * skb socket buffer containing HDLC frame
  3338. * dev pointer to network device structure
  3339. */
  3340. static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb,
  3341. struct net_device *dev)
  3342. {
  3343. MGSLPC_INFO *info = dev_to_port(dev);
  3344. unsigned long flags;
  3345. if (debug_level >= DEBUG_LEVEL_INFO)
  3346. printk(KERN_INFO "%s:hdlc_xmit(%s)\n",__FILE__,dev->name);
  3347. /* stop sending until this frame completes */
  3348. netif_stop_queue(dev);
  3349. /* copy data to device buffers */
  3350. skb_copy_from_linear_data(skb, info->tx_buf, skb->len);
  3351. info->tx_get = 0;
  3352. info->tx_put = info->tx_count = skb->len;
  3353. /* update network statistics */
  3354. dev->stats.tx_packets++;
  3355. dev->stats.tx_bytes += skb->len;
  3356. /* done with socket buffer, so free it */
  3357. dev_kfree_skb(skb);
  3358. /* save start time for transmit timeout detection */
  3359. dev->trans_start = jiffies;
  3360. /* start hardware transmitter if necessary */
  3361. spin_lock_irqsave(&info->lock,flags);
  3362. if (!info->tx_active) {
  3363. struct tty_struct *tty = tty_port_tty_get(&info->port);
  3364. tx_start(info, tty);
  3365. tty_kref_put(tty);
  3366. }
  3367. spin_unlock_irqrestore(&info->lock,flags);
  3368. return NETDEV_TX_OK;
  3369. }
  3370. /**
  3371. * called by network layer when interface enabled
  3372. * claim resources and initialize hardware
  3373. *
  3374. * dev pointer to network device structure
  3375. *
  3376. * returns 0 if success, otherwise error code
  3377. */
  3378. static int hdlcdev_open(struct net_device *dev)
  3379. {
  3380. MGSLPC_INFO *info = dev_to_port(dev);
  3381. struct tty_struct *tty;
  3382. int rc;
  3383. unsigned long flags;
  3384. if (debug_level >= DEBUG_LEVEL_INFO)
  3385. printk("%s:hdlcdev_open(%s)\n",__FILE__,dev->name);
  3386. /* generic HDLC layer open processing */
  3387. if ((rc = hdlc_open(dev)))
  3388. return rc;
  3389. /* arbitrate between network and tty opens */
  3390. spin_lock_irqsave(&info->netlock, flags);
  3391. if (info->port.count != 0 || info->netcount != 0) {
  3392. printk(KERN_WARNING "%s: hdlc_open returning busy\n", dev->name);
  3393. spin_unlock_irqrestore(&info->netlock, flags);
  3394. return -EBUSY;
  3395. }
  3396. info->netcount=1;
  3397. spin_unlock_irqrestore(&info->netlock, flags);
  3398. tty = tty_port_tty_get(&info->port);
  3399. /* claim resources and init adapter */
  3400. if ((rc = startup(info, tty)) != 0) {
  3401. tty_kref_put(tty);
  3402. spin_lock_irqsave(&info->netlock, flags);
  3403. info->netcount=0;
  3404. spin_unlock_irqrestore(&info->netlock, flags);
  3405. return rc;
  3406. }
  3407. /* assert DTR and RTS, apply hardware settings */
  3408. info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
  3409. mgslpc_program_hw(info, tty);
  3410. tty_kref_put(tty);
  3411. /* enable network layer transmit */
  3412. dev->trans_start = jiffies;
  3413. netif_start_queue(dev);
  3414. /* inform generic HDLC layer of current DCD status */
  3415. spin_lock_irqsave(&info->lock, flags);
  3416. get_signals(info);
  3417. spin_unlock_irqrestore(&info->lock, flags);
  3418. if (info->serial_signals & SerialSignal_DCD)
  3419. netif_carrier_on(dev);
  3420. else
  3421. netif_carrier_off(dev);
  3422. return 0;
  3423. }
  3424. /**
  3425. * called by network layer when interface is disabled
  3426. * shutdown hardware and release resources
  3427. *
  3428. * dev pointer to network device structure
  3429. *
  3430. * returns 0 if success, otherwise error code
  3431. */
  3432. static int hdlcdev_close(struct net_device *dev)
  3433. {
  3434. MGSLPC_INFO *info = dev_to_port(dev);
  3435. struct tty_struct *tty = tty_port_tty_get(&info->port);
  3436. unsigned long flags;
  3437. if (debug_level >= DEBUG_LEVEL_INFO)
  3438. printk("%s:hdlcdev_close(%s)\n",__FILE__,dev->name);
  3439. netif_stop_queue(dev);
  3440. /* shutdown adapter and release resources */
  3441. shutdown(info, tty);
  3442. tty_kref_put(tty);
  3443. hdlc_close(dev);
  3444. spin_lock_irqsave(&info->netlock, flags);
  3445. info->netcount=0;
  3446. spin_unlock_irqrestore(&info->netlock, flags);
  3447. return 0;
  3448. }
  3449. /**
  3450. * called by network layer to process IOCTL call to network device
  3451. *
  3452. * dev pointer to network device structure
  3453. * ifr pointer to network interface request structure
  3454. * cmd IOCTL command code
  3455. *
  3456. * returns 0 if success, otherwise error code
  3457. */
  3458. static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
  3459. {
  3460. const size_t size = sizeof(sync_serial_settings);
  3461. sync_serial_settings new_line;
  3462. sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
  3463. MGSLPC_INFO *info = dev_to_port(dev);
  3464. unsigned int flags;
  3465. if (debug_level >= DEBUG_LEVEL_INFO)
  3466. printk("%s:hdlcdev_ioctl(%s)\n",__FILE__,dev->name);
  3467. /* return error if TTY interface open */
  3468. if (info->port.count)
  3469. return -EBUSY;
  3470. if (cmd != SIOCWANDEV)
  3471. return hdlc_ioctl(dev, ifr, cmd);
  3472. memset(&new_line, 0, size);
  3473. switch(ifr->ifr_settings.type) {
  3474. case IF_GET_IFACE: /* return current sync_serial_settings */
  3475. ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
  3476. if (ifr->ifr_settings.size < size) {
  3477. ifr->ifr_settings.size = size; /* data size wanted */
  3478. return -ENOBUFS;
  3479. }
  3480. flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
  3481. HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
  3482. HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
  3483. HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
  3484. switch (flags){
  3485. case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
  3486. case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
  3487. case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
  3488. case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
  3489. default: new_line.clock_type = CLOCK_DEFAULT;
  3490. }
  3491. new_line.clock_rate = info->params.clock_speed;
  3492. new_line.loopback = info->params.loopback ? 1:0;
  3493. if (copy_to_user(line, &new_line, size))
  3494. return -EFAULT;
  3495. return 0;
  3496. case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
  3497. if(!capable(CAP_NET_ADMIN))
  3498. return -EPERM;
  3499. if (copy_from_user(&new_line, line, size))
  3500. return -EFAULT;
  3501. switch (new_line.clock_type)
  3502. {
  3503. case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
  3504. case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
  3505. case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
  3506. case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
  3507. case CLOCK_DEFAULT: flags = info->params.flags &
  3508. (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
  3509. HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
  3510. HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
  3511. HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
  3512. default: return -EINVAL;
  3513. }
  3514. if (new_line.loopback != 0 && new_line.loopback != 1)
  3515. return -EINVAL;
  3516. info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
  3517. HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
  3518. HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
  3519. HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
  3520. info->params.flags |= flags;
  3521. info->params.loopback = new_line.loopback;
  3522. if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
  3523. info->params.clock_speed = new_line.clock_rate;
  3524. else
  3525. info->params.clock_speed = 0;
  3526. /* if network interface up, reprogram hardware */
  3527. if (info->netcount) {
  3528. struct tty_struct *tty = tty_port_tty_get(&info->port);
  3529. mgslpc_program_hw(info, tty);
  3530. tty_kref_put(tty);
  3531. }
  3532. return 0;
  3533. default:
  3534. return hdlc_ioctl(dev, ifr, cmd);
  3535. }
  3536. }
  3537. /**
  3538. * called by network layer when transmit timeout is detected
  3539. *
  3540. * dev pointer to network device structure
  3541. */
  3542. static void hdlcdev_tx_timeout(struct net_device *dev)
  3543. {
  3544. MGSLPC_INFO *info = dev_to_port(dev);
  3545. unsigned long flags;
  3546. if (debug_level >= DEBUG_LEVEL_INFO)
  3547. printk("hdlcdev_tx_timeout(%s)\n",dev->name);
  3548. dev->stats.tx_errors++;
  3549. dev->stats.tx_aborted_errors++;
  3550. spin_lock_irqsave(&info->lock,flags);
  3551. tx_stop(info);
  3552. spin_unlock_irqrestore(&info->lock,flags);
  3553. netif_wake_queue(dev);
  3554. }
  3555. /**
  3556. * called by device driver when transmit completes
  3557. * reenable network layer transmit if stopped
  3558. *
  3559. * info pointer to device instance information
  3560. */
  3561. static void hdlcdev_tx_done(MGSLPC_INFO *info)
  3562. {
  3563. if (netif_queue_stopped(info->netdev))
  3564. netif_wake_queue(info->netdev);
  3565. }
  3566. /**
  3567. * called by device driver when frame received
  3568. * pass frame to network layer
  3569. *
  3570. * info pointer to device instance information
  3571. * buf pointer to buffer contianing frame data
  3572. * size count of data bytes in buf
  3573. */
  3574. static void hdlcdev_rx(MGSLPC_INFO *info, char *buf, int size)
  3575. {
  3576. struct sk_buff *skb = dev_alloc_skb(size);
  3577. struct net_device *dev = info->netdev;
  3578. if (debug_level >= DEBUG_LEVEL_INFO)
  3579. printk("hdlcdev_rx(%s)\n",dev->name);
  3580. if (skb == NULL) {
  3581. printk(KERN_NOTICE "%s: can't alloc skb, dropping packet\n", dev->name);
  3582. dev->stats.rx_dropped++;
  3583. return;
  3584. }
  3585. memcpy(skb_put(skb, size), buf, size);
  3586. skb->protocol = hdlc_type_trans(skb, dev);
  3587. dev->stats.rx_packets++;
  3588. dev->stats.rx_bytes += size;
  3589. netif_rx(skb);
  3590. }
  3591. static const struct net_device_ops hdlcdev_ops = {
  3592. .ndo_open = hdlcdev_open,
  3593. .ndo_stop = hdlcdev_close,
  3594. .ndo_change_mtu = hdlc_change_mtu,
  3595. .ndo_start_xmit = hdlc_start_xmit,
  3596. .ndo_do_ioctl = hdlcdev_ioctl,
  3597. .ndo_tx_timeout = hdlcdev_tx_timeout,
  3598. };
  3599. /**
  3600. * called by device driver when adding device instance
  3601. * do generic HDLC initialization
  3602. *
  3603. * info pointer to device instance information
  3604. *
  3605. * returns 0 if success, otherwise error code
  3606. */
  3607. static int hdlcdev_init(MGSLPC_INFO *info)
  3608. {
  3609. int rc;
  3610. struct net_device *dev;
  3611. hdlc_device *hdlc;
  3612. /* allocate and initialize network and HDLC layer objects */
  3613. if (!(dev = alloc_hdlcdev(info))) {
  3614. printk(KERN_ERR "%s:hdlc device allocation failure\n",__FILE__);
  3615. return -ENOMEM;
  3616. }
  3617. /* for network layer reporting purposes only */
  3618. dev->base_addr = info->io_base;
  3619. dev->irq = info->irq_level;
  3620. /* network layer callbacks and settings */
  3621. dev->netdev_ops = &hdlcdev_ops;
  3622. dev->watchdog_timeo = 10 * HZ;
  3623. dev->tx_queue_len = 50;
  3624. /* generic HDLC layer callbacks and settings */
  3625. hdlc = dev_to_hdlc(dev);
  3626. hdlc->attach = hdlcdev_attach;
  3627. hdlc->xmit = hdlcdev_xmit;
  3628. /* register objects with HDLC layer */
  3629. if ((rc = register_hdlc_device(dev))) {
  3630. printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
  3631. free_netdev(dev);
  3632. return rc;
  3633. }
  3634. info->netdev = dev;
  3635. return 0;
  3636. }
  3637. /**
  3638. * called by device driver when removing device instance
  3639. * do generic HDLC cleanup
  3640. *
  3641. * info pointer to device instance information
  3642. */
  3643. static void hdlcdev_exit(MGSLPC_INFO *info)
  3644. {
  3645. unregister_hdlc_device(info->netdev);
  3646. free_netdev(info->netdev);
  3647. info->netdev = NULL;
  3648. }
  3649. #endif /* CONFIG_HDLC */