mpi2_cnfg.h 143 KB

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  1. /*
  2. * Copyright (c) 2000-2011 LSI Corporation.
  3. *
  4. *
  5. * Name: mpi2_cnfg.h
  6. * Title: MPI Configuration messages and pages
  7. * Creation Date: November 10, 2006
  8. *
  9. * mpi2_cnfg.h Version: 02.00.21
  10. *
  11. * Version History
  12. * ---------------
  13. *
  14. * Date Version Description
  15. * -------- -------- ------------------------------------------------------
  16. * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A.
  17. * 06-04-07 02.00.01 Added defines for SAS IO Unit Page 2 PhyFlags.
  18. * Added Manufacturing Page 11.
  19. * Added MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE
  20. * define.
  21. * 06-26-07 02.00.02 Adding generic structure for product-specific
  22. * Manufacturing pages: MPI2_CONFIG_PAGE_MANUFACTURING_PS.
  23. * Rework of BIOS Page 2 configuration page.
  24. * Fixed MPI2_BIOSPAGE2_BOOT_DEVICE to be a union of the
  25. * forms.
  26. * Added configuration pages IOC Page 8 and Driver
  27. * Persistent Mapping Page 0.
  28. * 08-31-07 02.00.03 Modified configuration pages dealing with Integrated
  29. * RAID (Manufacturing Page 4, RAID Volume Pages 0 and 1,
  30. * RAID Physical Disk Pages 0 and 1, RAID Configuration
  31. * Page 0).
  32. * Added new value for AccessStatus field of SAS Device
  33. * Page 0 (_SATA_NEEDS_INITIALIZATION).
  34. * 10-31-07 02.00.04 Added missing SEPDevHandle field to
  35. * MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0.
  36. * 12-18-07 02.00.05 Modified IO Unit Page 0 to use 32-bit version fields for
  37. * NVDATA.
  38. * Modified IOC Page 7 to use masks and added field for
  39. * SASBroadcastPrimitiveMasks.
  40. * Added MPI2_CONFIG_PAGE_BIOS_4.
  41. * Added MPI2_CONFIG_PAGE_LOG_0.
  42. * 02-29-08 02.00.06 Modified various names to make them 32-character unique.
  43. * Added SAS Device IDs.
  44. * Updated Integrated RAID configuration pages including
  45. * Manufacturing Page 4, IOC Page 6, and RAID Configuration
  46. * Page 0.
  47. * 05-21-08 02.00.07 Added define MPI2_MANPAGE4_MIX_SSD_SAS_SATA.
  48. * Added define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION.
  49. * Fixed define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING.
  50. * Added missing MaxNumRoutedSasAddresses field to
  51. * MPI2_CONFIG_PAGE_EXPANDER_0.
  52. * Added SAS Port Page 0.
  53. * Modified structure layout for
  54. * MPI2_CONFIG_PAGE_DRIVER_MAPPING_0.
  55. * 06-27-08 02.00.08 Changed MPI2_CONFIG_PAGE_RD_PDISK_1 to use
  56. * MPI2_RAID_PHYS_DISK1_PATH_MAX to size the array.
  57. * 10-02-08 02.00.09 Changed MPI2_RAID_PGAD_CONFIGNUM_MASK from 0x0000FFFF
  58. * to 0x000000FF.
  59. * Added two new values for the Physical Disk Coercion Size
  60. * bits in the Flags field of Manufacturing Page 4.
  61. * Added product-specific Manufacturing pages 16 to 31.
  62. * Modified Flags bits for controlling write cache on SATA
  63. * drives in IO Unit Page 1.
  64. * Added new bit to AdditionalControlFlags of SAS IO Unit
  65. * Page 1 to control Invalid Topology Correction.
  66. * Added additional defines for RAID Volume Page 0
  67. * VolumeStatusFlags field.
  68. * Modified meaning of RAID Volume Page 0 VolumeSettings
  69. * define for auto-configure of hot-swap drives.
  70. * Added SupportedPhysDisks field to RAID Volume Page 1 and
  71. * added related defines.
  72. * Added PhysDiskAttributes field (and related defines) to
  73. * RAID Physical Disk Page 0.
  74. * Added MPI2_SAS_PHYINFO_PHY_VACANT define.
  75. * Added three new DiscoveryStatus bits for SAS IO Unit
  76. * Page 0 and SAS Expander Page 0.
  77. * Removed multiplexing information from SAS IO Unit pages.
  78. * Added BootDeviceWaitTime field to SAS IO Unit Page 4.
  79. * Removed Zone Address Resolved bit from PhyInfo and from
  80. * Expander Page 0 Flags field.
  81. * Added two new AccessStatus values to SAS Device Page 0
  82. * for indicating routing problems. Added 3 reserved words
  83. * to this page.
  84. * 01-19-09 02.00.10 Fixed defines for GPIOVal field of IO Unit Page 3.
  85. * Inserted missing reserved field into structure for IOC
  86. * Page 6.
  87. * Added more pending task bits to RAID Volume Page 0
  88. * VolumeStatusFlags defines.
  89. * Added MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED define.
  90. * Added a new DiscoveryStatus bit for SAS IO Unit Page 0
  91. * and SAS Expander Page 0 to flag a downstream initiator
  92. * when in simplified routing mode.
  93. * Removed SATA Init Failure defines for DiscoveryStatus
  94. * fields of SAS IO Unit Page 0 and SAS Expander Page 0.
  95. * Added MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED define.
  96. * Added PortGroups, DmaGroup, and ControlGroup fields to
  97. * SAS Device Page 0.
  98. * 05-06-09 02.00.11 Added structures and defines for IO Unit Page 5 and IO
  99. * Unit Page 6.
  100. * Added expander reduced functionality data to SAS
  101. * Expander Page 0.
  102. * Added SAS PHY Page 2 and SAS PHY Page 3.
  103. * 07-30-09 02.00.12 Added IO Unit Page 7.
  104. * Added new device ids.
  105. * Added SAS IO Unit Page 5.
  106. * Added partial and slumber power management capable flags
  107. * to SAS Device Page 0 Flags field.
  108. * Added PhyInfo defines for power condition.
  109. * Added Ethernet configuration pages.
  110. * 10-28-09 02.00.13 Added MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY.
  111. * Added SAS PHY Page 4 structure and defines.
  112. * 02-10-10 02.00.14 Modified the comments for the configuration page
  113. * structures that contain an array of data. The host
  114. * should use the "count" field in the page data (e.g. the
  115. * NumPhys field) to determine the number of valid elements
  116. * in the array.
  117. * Added/modified some MPI2_MFGPAGE_DEVID_SAS defines.
  118. * Added PowerManagementCapabilities to IO Unit Page 7.
  119. * Added PortWidthModGroup field to
  120. * MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS.
  121. * Added MPI2_CONFIG_PAGE_SASIOUNIT_6 and related defines.
  122. * Added MPI2_CONFIG_PAGE_SASIOUNIT_7 and related defines.
  123. * Added MPI2_CONFIG_PAGE_SASIOUNIT_8 and related defines.
  124. * 05-12-10 02.00.15 Added MPI2_RAIDVOL0_STATUS_FLAG_VOL_NOT_CONSISTENT
  125. * define.
  126. * Added MPI2_PHYSDISK0_INCOMPATIBLE_MEDIA_TYPE define.
  127. * Added MPI2_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY define.
  128. * 08-11-10 02.00.16 Removed IO Unit Page 1 device path (multi-pathing)
  129. * defines.
  130. * 11-10-10 02.00.17 Added ReceptacleID field (replacing Reserved1) to
  131. * MPI2_MANPAGE7_CONNECTOR_INFO and reworked defines for
  132. * the Pinout field.
  133. * Added BoardTemperature and BoardTemperatureUnits fields
  134. * to MPI2_CONFIG_PAGE_IO_UNIT_7.
  135. * Added MPI2_CONFIG_EXTPAGETYPE_EXT_MANUFACTURING define
  136. * and MPI2_CONFIG_PAGE_EXT_MAN_PS structure.
  137. * 02-23-11 02.00.18 Added ProxyVF_ID field to MPI2_CONFIG_REQUEST.
  138. * Added IO Unit Page 8, IO Unit Page 9,
  139. * and IO Unit Page 10.
  140. * Added SASNotifyPrimitiveMasks field to
  141. * MPI2_CONFIG_PAGE_IOC_7.
  142. * 03-09-11 02.00.19 Fixed IO Unit Page 10 (to match the spec).
  143. * 05-25-11 02.00.20 Cleaned up a few comments.
  144. * 08-24-11 02.00.21 Marked the IO Unit Page 7 PowerManagementCapabilities
  145. * for PCIe link as obsolete.
  146. * Added SpinupFlags field containing a Disable Spin-up
  147. * bit to the MPI2_SAS_IOUNIT4_SPINUP_GROUP fields of
  148. * SAS IO Unit Page 4.
  149. * --------------------------------------------------------------------------
  150. */
  151. #ifndef MPI2_CNFG_H
  152. #define MPI2_CNFG_H
  153. /*****************************************************************************
  154. * Configuration Page Header and defines
  155. *****************************************************************************/
  156. /* Config Page Header */
  157. typedef struct _MPI2_CONFIG_PAGE_HEADER
  158. {
  159. U8 PageVersion; /* 0x00 */
  160. U8 PageLength; /* 0x01 */
  161. U8 PageNumber; /* 0x02 */
  162. U8 PageType; /* 0x03 */
  163. } MPI2_CONFIG_PAGE_HEADER, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_HEADER,
  164. Mpi2ConfigPageHeader_t, MPI2_POINTER pMpi2ConfigPageHeader_t;
  165. typedef union _MPI2_CONFIG_PAGE_HEADER_UNION
  166. {
  167. MPI2_CONFIG_PAGE_HEADER Struct;
  168. U8 Bytes[4];
  169. U16 Word16[2];
  170. U32 Word32;
  171. } MPI2_CONFIG_PAGE_HEADER_UNION, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_HEADER_UNION,
  172. Mpi2ConfigPageHeaderUnion, MPI2_POINTER pMpi2ConfigPageHeaderUnion;
  173. /* Extended Config Page Header */
  174. typedef struct _MPI2_CONFIG_EXTENDED_PAGE_HEADER
  175. {
  176. U8 PageVersion; /* 0x00 */
  177. U8 Reserved1; /* 0x01 */
  178. U8 PageNumber; /* 0x02 */
  179. U8 PageType; /* 0x03 */
  180. U16 ExtPageLength; /* 0x04 */
  181. U8 ExtPageType; /* 0x06 */
  182. U8 Reserved2; /* 0x07 */
  183. } MPI2_CONFIG_EXTENDED_PAGE_HEADER,
  184. MPI2_POINTER PTR_MPI2_CONFIG_EXTENDED_PAGE_HEADER,
  185. Mpi2ConfigExtendedPageHeader_t, MPI2_POINTER pMpi2ConfigExtendedPageHeader_t;
  186. typedef union _MPI2_CONFIG_EXT_PAGE_HEADER_UNION
  187. {
  188. MPI2_CONFIG_PAGE_HEADER Struct;
  189. MPI2_CONFIG_EXTENDED_PAGE_HEADER Ext;
  190. U8 Bytes[8];
  191. U16 Word16[4];
  192. U32 Word32[2];
  193. } MPI2_CONFIG_EXT_PAGE_HEADER_UNION, MPI2_POINTER PTR_MPI2_CONFIG_EXT_PAGE_HEADER_UNION,
  194. Mpi2ConfigPageExtendedHeaderUnion, MPI2_POINTER pMpi2ConfigPageExtendedHeaderUnion;
  195. /* PageType field values */
  196. #define MPI2_CONFIG_PAGEATTR_READ_ONLY (0x00)
  197. #define MPI2_CONFIG_PAGEATTR_CHANGEABLE (0x10)
  198. #define MPI2_CONFIG_PAGEATTR_PERSISTENT (0x20)
  199. #define MPI2_CONFIG_PAGEATTR_MASK (0xF0)
  200. #define MPI2_CONFIG_PAGETYPE_IO_UNIT (0x00)
  201. #define MPI2_CONFIG_PAGETYPE_IOC (0x01)
  202. #define MPI2_CONFIG_PAGETYPE_BIOS (0x02)
  203. #define MPI2_CONFIG_PAGETYPE_RAID_VOLUME (0x08)
  204. #define MPI2_CONFIG_PAGETYPE_MANUFACTURING (0x09)
  205. #define MPI2_CONFIG_PAGETYPE_RAID_PHYSDISK (0x0A)
  206. #define MPI2_CONFIG_PAGETYPE_EXTENDED (0x0F)
  207. #define MPI2_CONFIG_PAGETYPE_MASK (0x0F)
  208. #define MPI2_CONFIG_TYPENUM_MASK (0x0FFF)
  209. /* ExtPageType field values */
  210. #define MPI2_CONFIG_EXTPAGETYPE_SAS_IO_UNIT (0x10)
  211. #define MPI2_CONFIG_EXTPAGETYPE_SAS_EXPANDER (0x11)
  212. #define MPI2_CONFIG_EXTPAGETYPE_SAS_DEVICE (0x12)
  213. #define MPI2_CONFIG_EXTPAGETYPE_SAS_PHY (0x13)
  214. #define MPI2_CONFIG_EXTPAGETYPE_LOG (0x14)
  215. #define MPI2_CONFIG_EXTPAGETYPE_ENCLOSURE (0x15)
  216. #define MPI2_CONFIG_EXTPAGETYPE_RAID_CONFIG (0x16)
  217. #define MPI2_CONFIG_EXTPAGETYPE_DRIVER_MAPPING (0x17)
  218. #define MPI2_CONFIG_EXTPAGETYPE_SAS_PORT (0x18)
  219. #define MPI2_CONFIG_EXTPAGETYPE_ETHERNET (0x19)
  220. #define MPI2_CONFIG_EXTPAGETYPE_EXT_MANUFACTURING (0x1A)
  221. /*****************************************************************************
  222. * PageAddress defines
  223. *****************************************************************************/
  224. /* RAID Volume PageAddress format */
  225. #define MPI2_RAID_VOLUME_PGAD_FORM_MASK (0xF0000000)
  226. #define MPI2_RAID_VOLUME_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
  227. #define MPI2_RAID_VOLUME_PGAD_FORM_HANDLE (0x10000000)
  228. #define MPI2_RAID_VOLUME_PGAD_HANDLE_MASK (0x0000FFFF)
  229. /* RAID Physical Disk PageAddress format */
  230. #define MPI2_PHYSDISK_PGAD_FORM_MASK (0xF0000000)
  231. #define MPI2_PHYSDISK_PGAD_FORM_GET_NEXT_PHYSDISKNUM (0x00000000)
  232. #define MPI2_PHYSDISK_PGAD_FORM_PHYSDISKNUM (0x10000000)
  233. #define MPI2_PHYSDISK_PGAD_FORM_DEVHANDLE (0x20000000)
  234. #define MPI2_PHYSDISK_PGAD_PHYSDISKNUM_MASK (0x000000FF)
  235. #define MPI2_PHYSDISK_PGAD_DEVHANDLE_MASK (0x0000FFFF)
  236. /* SAS Expander PageAddress format */
  237. #define MPI2_SAS_EXPAND_PGAD_FORM_MASK (0xF0000000)
  238. #define MPI2_SAS_EXPAND_PGAD_FORM_GET_NEXT_HNDL (0x00000000)
  239. #define MPI2_SAS_EXPAND_PGAD_FORM_HNDL_PHY_NUM (0x10000000)
  240. #define MPI2_SAS_EXPAND_PGAD_FORM_HNDL (0x20000000)
  241. #define MPI2_SAS_EXPAND_PGAD_HANDLE_MASK (0x0000FFFF)
  242. #define MPI2_SAS_EXPAND_PGAD_PHYNUM_MASK (0x00FF0000)
  243. #define MPI2_SAS_EXPAND_PGAD_PHYNUM_SHIFT (16)
  244. /* SAS Device PageAddress format */
  245. #define MPI2_SAS_DEVICE_PGAD_FORM_MASK (0xF0000000)
  246. #define MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
  247. #define MPI2_SAS_DEVICE_PGAD_FORM_HANDLE (0x20000000)
  248. #define MPI2_SAS_DEVICE_PGAD_HANDLE_MASK (0x0000FFFF)
  249. /* SAS PHY PageAddress format */
  250. #define MPI2_SAS_PHY_PGAD_FORM_MASK (0xF0000000)
  251. #define MPI2_SAS_PHY_PGAD_FORM_PHY_NUMBER (0x00000000)
  252. #define MPI2_SAS_PHY_PGAD_FORM_PHY_TBL_INDEX (0x10000000)
  253. #define MPI2_SAS_PHY_PGAD_PHY_NUMBER_MASK (0x000000FF)
  254. #define MPI2_SAS_PHY_PGAD_PHY_TBL_INDEX_MASK (0x0000FFFF)
  255. /* SAS Port PageAddress format */
  256. #define MPI2_SASPORT_PGAD_FORM_MASK (0xF0000000)
  257. #define MPI2_SASPORT_PGAD_FORM_GET_NEXT_PORT (0x00000000)
  258. #define MPI2_SASPORT_PGAD_FORM_PORT_NUM (0x10000000)
  259. #define MPI2_SASPORT_PGAD_PORTNUMBER_MASK (0x00000FFF)
  260. /* SAS Enclosure PageAddress format */
  261. #define MPI2_SAS_ENCLOS_PGAD_FORM_MASK (0xF0000000)
  262. #define MPI2_SAS_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
  263. #define MPI2_SAS_ENCLOS_PGAD_FORM_HANDLE (0x10000000)
  264. #define MPI2_SAS_ENCLOS_PGAD_HANDLE_MASK (0x0000FFFF)
  265. /* RAID Configuration PageAddress format */
  266. #define MPI2_RAID_PGAD_FORM_MASK (0xF0000000)
  267. #define MPI2_RAID_PGAD_FORM_GET_NEXT_CONFIGNUM (0x00000000)
  268. #define MPI2_RAID_PGAD_FORM_CONFIGNUM (0x10000000)
  269. #define MPI2_RAID_PGAD_FORM_ACTIVE_CONFIG (0x20000000)
  270. #define MPI2_RAID_PGAD_CONFIGNUM_MASK (0x000000FF)
  271. /* Driver Persistent Mapping PageAddress format */
  272. #define MPI2_DPM_PGAD_FORM_MASK (0xF0000000)
  273. #define MPI2_DPM_PGAD_FORM_ENTRY_RANGE (0x00000000)
  274. #define MPI2_DPM_PGAD_ENTRY_COUNT_MASK (0x0FFF0000)
  275. #define MPI2_DPM_PGAD_ENTRY_COUNT_SHIFT (16)
  276. #define MPI2_DPM_PGAD_START_ENTRY_MASK (0x0000FFFF)
  277. /* Ethernet PageAddress format */
  278. #define MPI2_ETHERNET_PGAD_FORM_MASK (0xF0000000)
  279. #define MPI2_ETHERNET_PGAD_FORM_IF_NUM (0x00000000)
  280. #define MPI2_ETHERNET_PGAD_IF_NUMBER_MASK (0x000000FF)
  281. /****************************************************************************
  282. * Configuration messages
  283. ****************************************************************************/
  284. /* Configuration Request Message */
  285. typedef struct _MPI2_CONFIG_REQUEST
  286. {
  287. U8 Action; /* 0x00 */
  288. U8 SGLFlags; /* 0x01 */
  289. U8 ChainOffset; /* 0x02 */
  290. U8 Function; /* 0x03 */
  291. U16 ExtPageLength; /* 0x04 */
  292. U8 ExtPageType; /* 0x06 */
  293. U8 MsgFlags; /* 0x07 */
  294. U8 VP_ID; /* 0x08 */
  295. U8 VF_ID; /* 0x09 */
  296. U16 Reserved1; /* 0x0A */
  297. U8 Reserved2; /* 0x0C */
  298. U8 ProxyVF_ID; /* 0x0D */
  299. U16 Reserved4; /* 0x0E */
  300. U32 Reserved3; /* 0x10 */
  301. MPI2_CONFIG_PAGE_HEADER Header; /* 0x14 */
  302. U32 PageAddress; /* 0x18 */
  303. MPI2_SGE_IO_UNION PageBufferSGE; /* 0x1C */
  304. } MPI2_CONFIG_REQUEST, MPI2_POINTER PTR_MPI2_CONFIG_REQUEST,
  305. Mpi2ConfigRequest_t, MPI2_POINTER pMpi2ConfigRequest_t;
  306. /* values for the Action field */
  307. #define MPI2_CONFIG_ACTION_PAGE_HEADER (0x00)
  308. #define MPI2_CONFIG_ACTION_PAGE_READ_CURRENT (0x01)
  309. #define MPI2_CONFIG_ACTION_PAGE_WRITE_CURRENT (0x02)
  310. #define MPI2_CONFIG_ACTION_PAGE_DEFAULT (0x03)
  311. #define MPI2_CONFIG_ACTION_PAGE_WRITE_NVRAM (0x04)
  312. #define MPI2_CONFIG_ACTION_PAGE_READ_DEFAULT (0x05)
  313. #define MPI2_CONFIG_ACTION_PAGE_READ_NVRAM (0x06)
  314. #define MPI2_CONFIG_ACTION_PAGE_GET_CHANGEABLE (0x07)
  315. /* use MPI2_SGLFLAGS_ defines from mpi2.h for the SGLFlags field */
  316. /* Config Reply Message */
  317. typedef struct _MPI2_CONFIG_REPLY
  318. {
  319. U8 Action; /* 0x00 */
  320. U8 SGLFlags; /* 0x01 */
  321. U8 MsgLength; /* 0x02 */
  322. U8 Function; /* 0x03 */
  323. U16 ExtPageLength; /* 0x04 */
  324. U8 ExtPageType; /* 0x06 */
  325. U8 MsgFlags; /* 0x07 */
  326. U8 VP_ID; /* 0x08 */
  327. U8 VF_ID; /* 0x09 */
  328. U16 Reserved1; /* 0x0A */
  329. U16 Reserved2; /* 0x0C */
  330. U16 IOCStatus; /* 0x0E */
  331. U32 IOCLogInfo; /* 0x10 */
  332. MPI2_CONFIG_PAGE_HEADER Header; /* 0x14 */
  333. } MPI2_CONFIG_REPLY, MPI2_POINTER PTR_MPI2_CONFIG_REPLY,
  334. Mpi2ConfigReply_t, MPI2_POINTER pMpi2ConfigReply_t;
  335. /*****************************************************************************
  336. *
  337. * C o n f i g u r a t i o n P a g e s
  338. *
  339. *****************************************************************************/
  340. /****************************************************************************
  341. * Manufacturing Config pages
  342. ****************************************************************************/
  343. #define MPI2_MFGPAGE_VENDORID_LSI (0x1000)
  344. /* SAS */
  345. #define MPI2_MFGPAGE_DEVID_SAS2004 (0x0070)
  346. #define MPI2_MFGPAGE_DEVID_SAS2008 (0x0072)
  347. #define MPI2_MFGPAGE_DEVID_SAS2108_1 (0x0074)
  348. #define MPI2_MFGPAGE_DEVID_SAS2108_2 (0x0076)
  349. #define MPI2_MFGPAGE_DEVID_SAS2108_3 (0x0077)
  350. #define MPI2_MFGPAGE_DEVID_SAS2116_1 (0x0064)
  351. #define MPI2_MFGPAGE_DEVID_SAS2116_2 (0x0065)
  352. #define MPI2_MFGPAGE_DEVID_SSS6200 (0x007E)
  353. #define MPI2_MFGPAGE_DEVID_SAS2208_1 (0x0080)
  354. #define MPI2_MFGPAGE_DEVID_SAS2208_2 (0x0081)
  355. #define MPI2_MFGPAGE_DEVID_SAS2208_3 (0x0082)
  356. #define MPI2_MFGPAGE_DEVID_SAS2208_4 (0x0083)
  357. #define MPI2_MFGPAGE_DEVID_SAS2208_5 (0x0084)
  358. #define MPI2_MFGPAGE_DEVID_SAS2208_6 (0x0085)
  359. #define MPI2_MFGPAGE_DEVID_SAS2308_1 (0x0086)
  360. #define MPI2_MFGPAGE_DEVID_SAS2308_2 (0x0087)
  361. #define MPI2_MFGPAGE_DEVID_SAS2308_3 (0x006E)
  362. /* Manufacturing Page 0 */
  363. typedef struct _MPI2_CONFIG_PAGE_MAN_0
  364. {
  365. MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
  366. U8 ChipName[16]; /* 0x04 */
  367. U8 ChipRevision[8]; /* 0x14 */
  368. U8 BoardName[16]; /* 0x1C */
  369. U8 BoardAssembly[16]; /* 0x2C */
  370. U8 BoardTracerNumber[16]; /* 0x3C */
  371. } MPI2_CONFIG_PAGE_MAN_0,
  372. MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_0,
  373. Mpi2ManufacturingPage0_t, MPI2_POINTER pMpi2ManufacturingPage0_t;
  374. #define MPI2_MANUFACTURING0_PAGEVERSION (0x00)
  375. /* Manufacturing Page 1 */
  376. typedef struct _MPI2_CONFIG_PAGE_MAN_1
  377. {
  378. MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
  379. U8 VPD[256]; /* 0x04 */
  380. } MPI2_CONFIG_PAGE_MAN_1,
  381. MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_1,
  382. Mpi2ManufacturingPage1_t, MPI2_POINTER pMpi2ManufacturingPage1_t;
  383. #define MPI2_MANUFACTURING1_PAGEVERSION (0x00)
  384. typedef struct _MPI2_CHIP_REVISION_ID
  385. {
  386. U16 DeviceID; /* 0x00 */
  387. U8 PCIRevisionID; /* 0x02 */
  388. U8 Reserved; /* 0x03 */
  389. } MPI2_CHIP_REVISION_ID, MPI2_POINTER PTR_MPI2_CHIP_REVISION_ID,
  390. Mpi2ChipRevisionId_t, MPI2_POINTER pMpi2ChipRevisionId_t;
  391. /* Manufacturing Page 2 */
  392. /*
  393. * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
  394. * one and check Header.PageLength at runtime.
  395. */
  396. #ifndef MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS
  397. #define MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS (1)
  398. #endif
  399. typedef struct _MPI2_CONFIG_PAGE_MAN_2
  400. {
  401. MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
  402. MPI2_CHIP_REVISION_ID ChipId; /* 0x04 */
  403. U32 HwSettings[MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS];/* 0x08 */
  404. } MPI2_CONFIG_PAGE_MAN_2,
  405. MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_2,
  406. Mpi2ManufacturingPage2_t, MPI2_POINTER pMpi2ManufacturingPage2_t;
  407. #define MPI2_MANUFACTURING2_PAGEVERSION (0x00)
  408. /* Manufacturing Page 3 */
  409. /*
  410. * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
  411. * one and check Header.PageLength at runtime.
  412. */
  413. #ifndef MPI2_MAN_PAGE_3_INFO_WORDS
  414. #define MPI2_MAN_PAGE_3_INFO_WORDS (1)
  415. #endif
  416. typedef struct _MPI2_CONFIG_PAGE_MAN_3
  417. {
  418. MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
  419. MPI2_CHIP_REVISION_ID ChipId; /* 0x04 */
  420. U32 Info[MPI2_MAN_PAGE_3_INFO_WORDS];/* 0x08 */
  421. } MPI2_CONFIG_PAGE_MAN_3,
  422. MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_3,
  423. Mpi2ManufacturingPage3_t, MPI2_POINTER pMpi2ManufacturingPage3_t;
  424. #define MPI2_MANUFACTURING3_PAGEVERSION (0x00)
  425. /* Manufacturing Page 4 */
  426. typedef struct _MPI2_MANPAGE4_PWR_SAVE_SETTINGS
  427. {
  428. U8 PowerSaveFlags; /* 0x00 */
  429. U8 InternalOperationsSleepTime; /* 0x01 */
  430. U8 InternalOperationsRunTime; /* 0x02 */
  431. U8 HostIdleTime; /* 0x03 */
  432. } MPI2_MANPAGE4_PWR_SAVE_SETTINGS,
  433. MPI2_POINTER PTR_MPI2_MANPAGE4_PWR_SAVE_SETTINGS,
  434. Mpi2ManPage4PwrSaveSettings_t, MPI2_POINTER pMpi2ManPage4PwrSaveSettings_t;
  435. /* defines for the PowerSaveFlags field */
  436. #define MPI2_MANPAGE4_MASK_POWERSAVE_MODE (0x03)
  437. #define MPI2_MANPAGE4_POWERSAVE_MODE_DISABLED (0x00)
  438. #define MPI2_MANPAGE4_CUSTOM_POWERSAVE_MODE (0x01)
  439. #define MPI2_MANPAGE4_FULL_POWERSAVE_MODE (0x02)
  440. typedef struct _MPI2_CONFIG_PAGE_MAN_4
  441. {
  442. MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
  443. U32 Reserved1; /* 0x04 */
  444. U32 Flags; /* 0x08 */
  445. U8 InquirySize; /* 0x0C */
  446. U8 Reserved2; /* 0x0D */
  447. U16 Reserved3; /* 0x0E */
  448. U8 InquiryData[56]; /* 0x10 */
  449. U32 RAID0VolumeSettings; /* 0x48 */
  450. U32 RAID1EVolumeSettings; /* 0x4C */
  451. U32 RAID1VolumeSettings; /* 0x50 */
  452. U32 RAID10VolumeSettings; /* 0x54 */
  453. U32 Reserved4; /* 0x58 */
  454. U32 Reserved5; /* 0x5C */
  455. MPI2_MANPAGE4_PWR_SAVE_SETTINGS PowerSaveSettings; /* 0x60 */
  456. U8 MaxOCEDisks; /* 0x64 */
  457. U8 ResyncRate; /* 0x65 */
  458. U16 DataScrubDuration; /* 0x66 */
  459. U8 MaxHotSpares; /* 0x68 */
  460. U8 MaxPhysDisksPerVol; /* 0x69 */
  461. U8 MaxPhysDisks; /* 0x6A */
  462. U8 MaxVolumes; /* 0x6B */
  463. } MPI2_CONFIG_PAGE_MAN_4,
  464. MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_4,
  465. Mpi2ManufacturingPage4_t, MPI2_POINTER pMpi2ManufacturingPage4_t;
  466. #define MPI2_MANUFACTURING4_PAGEVERSION (0x0A)
  467. /* Manufacturing Page 4 Flags field */
  468. #define MPI2_MANPAGE4_METADATA_SIZE_MASK (0x00030000)
  469. #define MPI2_MANPAGE4_METADATA_512MB (0x00000000)
  470. #define MPI2_MANPAGE4_MIX_SSD_SAS_SATA (0x00008000)
  471. #define MPI2_MANPAGE4_MIX_SSD_AND_NON_SSD (0x00004000)
  472. #define MPI2_MANPAGE4_HIDE_PHYSDISK_NON_IR (0x00002000)
  473. #define MPI2_MANPAGE4_MASK_PHYSDISK_COERCION (0x00001C00)
  474. #define MPI2_MANPAGE4_PHYSDISK_COERCION_1GB (0x00000000)
  475. #define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION (0x00000400)
  476. #define MPI2_MANPAGE4_PHYSDISK_ADAPTIVE_COERCION (0x00000800)
  477. #define MPI2_MANPAGE4_PHYSDISK_ZERO_COERCION (0x00000C00)
  478. #define MPI2_MANPAGE4_MASK_BAD_BLOCK_MARKING (0x00000300)
  479. #define MPI2_MANPAGE4_DEFAULT_BAD_BLOCK_MARKING (0x00000000)
  480. #define MPI2_MANPAGE4_TABLE_BAD_BLOCK_MARKING (0x00000100)
  481. #define MPI2_MANPAGE4_WRITE_LONG_BAD_BLOCK_MARKING (0x00000200)
  482. #define MPI2_MANPAGE4_FORCE_OFFLINE_FAILOVER (0x00000080)
  483. #define MPI2_MANPAGE4_RAID10_DISABLE (0x00000040)
  484. #define MPI2_MANPAGE4_RAID1E_DISABLE (0x00000020)
  485. #define MPI2_MANPAGE4_RAID1_DISABLE (0x00000010)
  486. #define MPI2_MANPAGE4_RAID0_DISABLE (0x00000008)
  487. #define MPI2_MANPAGE4_IR_MODEPAGE8_DISABLE (0x00000004)
  488. #define MPI2_MANPAGE4_IM_RESYNC_CACHE_ENABLE (0x00000002)
  489. #define MPI2_MANPAGE4_IR_NO_MIX_SAS_SATA (0x00000001)
  490. /* Manufacturing Page 5 */
  491. /*
  492. * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
  493. * one and check the value returned for NumPhys at runtime.
  494. */
  495. #ifndef MPI2_MAN_PAGE_5_PHY_ENTRIES
  496. #define MPI2_MAN_PAGE_5_PHY_ENTRIES (1)
  497. #endif
  498. typedef struct _MPI2_MANUFACTURING5_ENTRY
  499. {
  500. U64 WWID; /* 0x00 */
  501. U64 DeviceName; /* 0x08 */
  502. } MPI2_MANUFACTURING5_ENTRY, MPI2_POINTER PTR_MPI2_MANUFACTURING5_ENTRY,
  503. Mpi2Manufacturing5Entry_t, MPI2_POINTER pMpi2Manufacturing5Entry_t;
  504. typedef struct _MPI2_CONFIG_PAGE_MAN_5
  505. {
  506. MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
  507. U8 NumPhys; /* 0x04 */
  508. U8 Reserved1; /* 0x05 */
  509. U16 Reserved2; /* 0x06 */
  510. U32 Reserved3; /* 0x08 */
  511. U32 Reserved4; /* 0x0C */
  512. MPI2_MANUFACTURING5_ENTRY Phy[MPI2_MAN_PAGE_5_PHY_ENTRIES];/* 0x08 */
  513. } MPI2_CONFIG_PAGE_MAN_5,
  514. MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_5,
  515. Mpi2ManufacturingPage5_t, MPI2_POINTER pMpi2ManufacturingPage5_t;
  516. #define MPI2_MANUFACTURING5_PAGEVERSION (0x03)
  517. /* Manufacturing Page 6 */
  518. typedef struct _MPI2_CONFIG_PAGE_MAN_6
  519. {
  520. MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
  521. U32 ProductSpecificInfo;/* 0x04 */
  522. } MPI2_CONFIG_PAGE_MAN_6,
  523. MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_6,
  524. Mpi2ManufacturingPage6_t, MPI2_POINTER pMpi2ManufacturingPage6_t;
  525. #define MPI2_MANUFACTURING6_PAGEVERSION (0x00)
  526. /* Manufacturing Page 7 */
  527. typedef struct _MPI2_MANPAGE7_CONNECTOR_INFO
  528. {
  529. U32 Pinout; /* 0x00 */
  530. U8 Connector[16]; /* 0x04 */
  531. U8 Location; /* 0x14 */
  532. U8 ReceptacleID; /* 0x15 */
  533. U16 Slot; /* 0x16 */
  534. U32 Reserved2; /* 0x18 */
  535. } MPI2_MANPAGE7_CONNECTOR_INFO, MPI2_POINTER PTR_MPI2_MANPAGE7_CONNECTOR_INFO,
  536. Mpi2ManPage7ConnectorInfo_t, MPI2_POINTER pMpi2ManPage7ConnectorInfo_t;
  537. /* defines for the Pinout field */
  538. #define MPI2_MANPAGE7_PINOUT_LANE_MASK (0x0000FF00)
  539. #define MPI2_MANPAGE7_PINOUT_LANE_SHIFT (8)
  540. #define MPI2_MANPAGE7_PINOUT_TYPE_MASK (0x000000FF)
  541. #define MPI2_MANPAGE7_PINOUT_TYPE_UNKNOWN (0x00)
  542. #define MPI2_MANPAGE7_PINOUT_SATA_SINGLE (0x01)
  543. #define MPI2_MANPAGE7_PINOUT_SFF_8482 (0x02)
  544. #define MPI2_MANPAGE7_PINOUT_SFF_8486 (0x03)
  545. #define MPI2_MANPAGE7_PINOUT_SFF_8484 (0x04)
  546. #define MPI2_MANPAGE7_PINOUT_SFF_8087 (0x05)
  547. #define MPI2_MANPAGE7_PINOUT_SFF_8643_4I (0x06)
  548. #define MPI2_MANPAGE7_PINOUT_SFF_8643_8I (0x07)
  549. #define MPI2_MANPAGE7_PINOUT_SFF_8470 (0x08)
  550. #define MPI2_MANPAGE7_PINOUT_SFF_8088 (0x09)
  551. #define MPI2_MANPAGE7_PINOUT_SFF_8644_4X (0x0A)
  552. #define MPI2_MANPAGE7_PINOUT_SFF_8644_8X (0x0B)
  553. #define MPI2_MANPAGE7_PINOUT_SFF_8644_16X (0x0C)
  554. #define MPI2_MANPAGE7_PINOUT_SFF_8436 (0x0D)
  555. /* defines for the Location field */
  556. #define MPI2_MANPAGE7_LOCATION_UNKNOWN (0x01)
  557. #define MPI2_MANPAGE7_LOCATION_INTERNAL (0x02)
  558. #define MPI2_MANPAGE7_LOCATION_EXTERNAL (0x04)
  559. #define MPI2_MANPAGE7_LOCATION_SWITCHABLE (0x08)
  560. #define MPI2_MANPAGE7_LOCATION_AUTO (0x10)
  561. #define MPI2_MANPAGE7_LOCATION_NOT_PRESENT (0x20)
  562. #define MPI2_MANPAGE7_LOCATION_NOT_CONNECTED (0x80)
  563. /*
  564. * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
  565. * one and check the value returned for NumPhys at runtime.
  566. */
  567. #ifndef MPI2_MANPAGE7_CONNECTOR_INFO_MAX
  568. #define MPI2_MANPAGE7_CONNECTOR_INFO_MAX (1)
  569. #endif
  570. typedef struct _MPI2_CONFIG_PAGE_MAN_7
  571. {
  572. MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
  573. U32 Reserved1; /* 0x04 */
  574. U32 Reserved2; /* 0x08 */
  575. U32 Flags; /* 0x0C */
  576. U8 EnclosureName[16]; /* 0x10 */
  577. U8 NumPhys; /* 0x20 */
  578. U8 Reserved3; /* 0x21 */
  579. U16 Reserved4; /* 0x22 */
  580. MPI2_MANPAGE7_CONNECTOR_INFO ConnectorInfo[MPI2_MANPAGE7_CONNECTOR_INFO_MAX]; /* 0x24 */
  581. } MPI2_CONFIG_PAGE_MAN_7,
  582. MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_7,
  583. Mpi2ManufacturingPage7_t, MPI2_POINTER pMpi2ManufacturingPage7_t;
  584. #define MPI2_MANUFACTURING7_PAGEVERSION (0x01)
  585. /* defines for the Flags field */
  586. #define MPI2_MANPAGE7_FLAG_USE_SLOT_INFO (0x00000001)
  587. /*
  588. * Generic structure to use for product-specific manufacturing pages
  589. * (currently Manufacturing Page 8 through Manufacturing Page 31).
  590. */
  591. typedef struct _MPI2_CONFIG_PAGE_MAN_PS
  592. {
  593. MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
  594. U32 ProductSpecificInfo;/* 0x04 */
  595. } MPI2_CONFIG_PAGE_MAN_PS,
  596. MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_PS,
  597. Mpi2ManufacturingPagePS_t, MPI2_POINTER pMpi2ManufacturingPagePS_t;
  598. #define MPI2_MANUFACTURING8_PAGEVERSION (0x00)
  599. #define MPI2_MANUFACTURING9_PAGEVERSION (0x00)
  600. #define MPI2_MANUFACTURING10_PAGEVERSION (0x00)
  601. #define MPI2_MANUFACTURING11_PAGEVERSION (0x00)
  602. #define MPI2_MANUFACTURING12_PAGEVERSION (0x00)
  603. #define MPI2_MANUFACTURING13_PAGEVERSION (0x00)
  604. #define MPI2_MANUFACTURING14_PAGEVERSION (0x00)
  605. #define MPI2_MANUFACTURING15_PAGEVERSION (0x00)
  606. #define MPI2_MANUFACTURING16_PAGEVERSION (0x00)
  607. #define MPI2_MANUFACTURING17_PAGEVERSION (0x00)
  608. #define MPI2_MANUFACTURING18_PAGEVERSION (0x00)
  609. #define MPI2_MANUFACTURING19_PAGEVERSION (0x00)
  610. #define MPI2_MANUFACTURING20_PAGEVERSION (0x00)
  611. #define MPI2_MANUFACTURING21_PAGEVERSION (0x00)
  612. #define MPI2_MANUFACTURING22_PAGEVERSION (0x00)
  613. #define MPI2_MANUFACTURING23_PAGEVERSION (0x00)
  614. #define MPI2_MANUFACTURING24_PAGEVERSION (0x00)
  615. #define MPI2_MANUFACTURING25_PAGEVERSION (0x00)
  616. #define MPI2_MANUFACTURING26_PAGEVERSION (0x00)
  617. #define MPI2_MANUFACTURING27_PAGEVERSION (0x00)
  618. #define MPI2_MANUFACTURING28_PAGEVERSION (0x00)
  619. #define MPI2_MANUFACTURING29_PAGEVERSION (0x00)
  620. #define MPI2_MANUFACTURING30_PAGEVERSION (0x00)
  621. #define MPI2_MANUFACTURING31_PAGEVERSION (0x00)
  622. /****************************************************************************
  623. * IO Unit Config Pages
  624. ****************************************************************************/
  625. /* IO Unit Page 0 */
  626. typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_0
  627. {
  628. MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
  629. U64 UniqueValue; /* 0x04 */
  630. MPI2_VERSION_UNION NvdataVersionDefault; /* 0x08 */
  631. MPI2_VERSION_UNION NvdataVersionPersistent; /* 0x0A */
  632. } MPI2_CONFIG_PAGE_IO_UNIT_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_0,
  633. Mpi2IOUnitPage0_t, MPI2_POINTER pMpi2IOUnitPage0_t;
  634. #define MPI2_IOUNITPAGE0_PAGEVERSION (0x02)
  635. /* IO Unit Page 1 */
  636. typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_1
  637. {
  638. MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
  639. U32 Flags; /* 0x04 */
  640. } MPI2_CONFIG_PAGE_IO_UNIT_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_1,
  641. Mpi2IOUnitPage1_t, MPI2_POINTER pMpi2IOUnitPage1_t;
  642. #define MPI2_IOUNITPAGE1_PAGEVERSION (0x04)
  643. /* IO Unit Page 1 Flags defines */
  644. #define MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY (0x00000800)
  645. #define MPI2_IOUNITPAGE1_MASK_SATA_WRITE_CACHE (0x00000600)
  646. #define MPI2_IOUNITPAGE1_SATA_WRITE_CACHE_SHIFT (9)
  647. #define MPI2_IOUNITPAGE1_ENABLE_SATA_WRITE_CACHE (0x00000000)
  648. #define MPI2_IOUNITPAGE1_DISABLE_SATA_WRITE_CACHE (0x00000200)
  649. #define MPI2_IOUNITPAGE1_UNCHANGED_SATA_WRITE_CACHE (0x00000400)
  650. #define MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE (0x00000100)
  651. #define MPI2_IOUNITPAGE1_DISABLE_IR (0x00000040)
  652. #define MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING (0x00000020)
  653. #define MPI2_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID (0x00000004)
  654. /* IO Unit Page 3 */
  655. /*
  656. * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
  657. * one and check the value returned for GPIOCount at runtime.
  658. */
  659. #ifndef MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX
  660. #define MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX (1)
  661. #endif
  662. typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_3
  663. {
  664. MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
  665. U8 GPIOCount; /* 0x04 */
  666. U8 Reserved1; /* 0x05 */
  667. U16 Reserved2; /* 0x06 */
  668. U16 GPIOVal[MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX];/* 0x08 */
  669. } MPI2_CONFIG_PAGE_IO_UNIT_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_3,
  670. Mpi2IOUnitPage3_t, MPI2_POINTER pMpi2IOUnitPage3_t;
  671. #define MPI2_IOUNITPAGE3_PAGEVERSION (0x01)
  672. /* defines for IO Unit Page 3 GPIOVal field */
  673. #define MPI2_IOUNITPAGE3_GPIO_FUNCTION_MASK (0xFFFC)
  674. #define MPI2_IOUNITPAGE3_GPIO_FUNCTION_SHIFT (2)
  675. #define MPI2_IOUNITPAGE3_GPIO_SETTING_OFF (0x0000)
  676. #define MPI2_IOUNITPAGE3_GPIO_SETTING_ON (0x0001)
  677. /* IO Unit Page 5 */
  678. /*
  679. * Upper layer code (drivers, utilities, etc.) should leave this define set to
  680. * one and check the value returned for NumDmaEngines at runtime.
  681. */
  682. #ifndef MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES
  683. #define MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES (1)
  684. #endif
  685. typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_5 {
  686. MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
  687. U64 RaidAcceleratorBufferBaseAddress; /* 0x04 */
  688. U64 RaidAcceleratorBufferSize; /* 0x0C */
  689. U64 RaidAcceleratorControlBaseAddress; /* 0x14 */
  690. U8 RAControlSize; /* 0x1C */
  691. U8 NumDmaEngines; /* 0x1D */
  692. U8 RAMinControlSize; /* 0x1E */
  693. U8 RAMaxControlSize; /* 0x1F */
  694. U32 Reserved1; /* 0x20 */
  695. U32 Reserved2; /* 0x24 */
  696. U32 Reserved3; /* 0x28 */
  697. U32 DmaEngineCapabilities
  698. [MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES]; /* 0x2C */
  699. } MPI2_CONFIG_PAGE_IO_UNIT_5, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_5,
  700. Mpi2IOUnitPage5_t, MPI2_POINTER pMpi2IOUnitPage5_t;
  701. #define MPI2_IOUNITPAGE5_PAGEVERSION (0x00)
  702. /* defines for IO Unit Page 5 DmaEngineCapabilities field */
  703. #define MPI2_IOUNITPAGE5_DMA_CAP_MASK_MAX_REQUESTS (0xFF00)
  704. #define MPI2_IOUNITPAGE5_DMA_CAP_SHIFT_MAX_REQUESTS (16)
  705. #define MPI2_IOUNITPAGE5_DMA_CAP_EEDP (0x0008)
  706. #define MPI2_IOUNITPAGE5_DMA_CAP_PARITY_GENERATION (0x0004)
  707. #define MPI2_IOUNITPAGE5_DMA_CAP_HASHING (0x0002)
  708. #define MPI2_IOUNITPAGE5_DMA_CAP_ENCRYPTION (0x0001)
  709. /* IO Unit Page 6 */
  710. typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_6 {
  711. MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
  712. U16 Flags; /* 0x04 */
  713. U8 RAHostControlSize; /* 0x06 */
  714. U8 Reserved0; /* 0x07 */
  715. U64 RaidAcceleratorHostControlBaseAddress; /* 0x08 */
  716. U32 Reserved1; /* 0x10 */
  717. U32 Reserved2; /* 0x14 */
  718. U32 Reserved3; /* 0x18 */
  719. } MPI2_CONFIG_PAGE_IO_UNIT_6, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_6,
  720. Mpi2IOUnitPage6_t, MPI2_POINTER pMpi2IOUnitPage6_t;
  721. #define MPI2_IOUNITPAGE6_PAGEVERSION (0x00)
  722. /* defines for IO Unit Page 6 Flags field */
  723. #define MPI2_IOUNITPAGE6_FLAGS_ENABLE_RAID_ACCELERATOR (0x0001)
  724. /* IO Unit Page 7 */
  725. typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_7 {
  726. MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
  727. U16 Reserved1; /* 0x04 */
  728. U8 PCIeWidth; /* 0x06 */
  729. U8 PCIeSpeed; /* 0x07 */
  730. U32 ProcessorState; /* 0x08 */
  731. U32 PowerManagementCapabilities; /* 0x0C */
  732. U16 IOCTemperature; /* 0x10 */
  733. U8 IOCTemperatureUnits; /* 0x12 */
  734. U8 IOCSpeed; /* 0x13 */
  735. U16 BoardTemperature; /* 0x14 */
  736. U8 BoardTemperatureUnits; /* 0x16 */
  737. U8 Reserved3; /* 0x17 */
  738. } MPI2_CONFIG_PAGE_IO_UNIT_7, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_7,
  739. Mpi2IOUnitPage7_t, MPI2_POINTER pMpi2IOUnitPage7_t;
  740. #define MPI2_IOUNITPAGE7_PAGEVERSION (0x02)
  741. /* defines for IO Unit Page 7 PCIeWidth field */
  742. #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X1 (0x01)
  743. #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X2 (0x02)
  744. #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X4 (0x04)
  745. #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X8 (0x08)
  746. /* defines for IO Unit Page 7 PCIeSpeed field */
  747. #define MPI2_IOUNITPAGE7_PCIE_SPEED_2_5_GBPS (0x00)
  748. #define MPI2_IOUNITPAGE7_PCIE_SPEED_5_0_GBPS (0x01)
  749. #define MPI2_IOUNITPAGE7_PCIE_SPEED_8_0_GBPS (0x02)
  750. /* defines for IO Unit Page 7 ProcessorState field */
  751. #define MPI2_IOUNITPAGE7_PSTATE_MASK_SECOND (0x0000000F)
  752. #define MPI2_IOUNITPAGE7_PSTATE_SHIFT_SECOND (0)
  753. #define MPI2_IOUNITPAGE7_PSTATE_NOT_PRESENT (0x00)
  754. #define MPI2_IOUNITPAGE7_PSTATE_DISABLED (0x01)
  755. #define MPI2_IOUNITPAGE7_PSTATE_ENABLED (0x02)
  756. /* defines for IO Unit Page 7 PowerManagementCapabilities field */
  757. #define MPI2_IOUNITPAGE7_PMCAP_12_5_PCT_IOCSPEED (0x00000400)
  758. #define MPI2_IOUNITPAGE7_PMCAP_25_0_PCT_IOCSPEED (0x00000200)
  759. #define MPI2_IOUNITPAGE7_PMCAP_50_0_PCT_IOCSPEED (0x00000100)
  760. #define MPI2_IOUNITPAGE7_PMCAP_PCIE_WIDTH_CHANGE (0x00000008) /* obsolete */
  761. #define MPI2_IOUNITPAGE7_PMCAP_PCIE_SPEED_CHANGE (0x00000004) /* obsolete */
  762. /* defines for IO Unit Page 7 IOCTemperatureUnits field */
  763. #define MPI2_IOUNITPAGE7_IOC_TEMP_NOT_PRESENT (0x00)
  764. #define MPI2_IOUNITPAGE7_IOC_TEMP_FAHRENHEIT (0x01)
  765. #define MPI2_IOUNITPAGE7_IOC_TEMP_CELSIUS (0x02)
  766. /* defines for IO Unit Page 7 IOCSpeed field */
  767. #define MPI2_IOUNITPAGE7_IOC_SPEED_FULL (0x01)
  768. #define MPI2_IOUNITPAGE7_IOC_SPEED_HALF (0x02)
  769. #define MPI2_IOUNITPAGE7_IOC_SPEED_QUARTER (0x04)
  770. #define MPI2_IOUNITPAGE7_IOC_SPEED_EIGHTH (0x08)
  771. /* defines for IO Unit Page 7 BoardTemperatureUnits field */
  772. #define MPI2_IOUNITPAGE7_BOARD_TEMP_NOT_PRESENT (0x00)
  773. #define MPI2_IOUNITPAGE7_BOARD_TEMP_FAHRENHEIT (0x01)
  774. #define MPI2_IOUNITPAGE7_BOARD_TEMP_CELSIUS (0x02)
  775. /* IO Unit Page 8 */
  776. #define MPI2_IOUNIT8_NUM_THRESHOLDS (4)
  777. typedef struct _MPI2_IOUNIT8_SENSOR {
  778. U16 Flags; /* 0x00 */
  779. U16 Reserved1; /* 0x02 */
  780. U16
  781. Threshold[MPI2_IOUNIT8_NUM_THRESHOLDS]; /* 0x04 */
  782. U32 Reserved2; /* 0x0C */
  783. U32 Reserved3; /* 0x10 */
  784. U32 Reserved4; /* 0x14 */
  785. } MPI2_IOUNIT8_SENSOR, MPI2_POINTER PTR_MPI2_IOUNIT8_SENSOR,
  786. Mpi2IOUnit8Sensor_t, MPI2_POINTER pMpi2IOUnit8Sensor_t;
  787. /* defines for IO Unit Page 8 Sensor Flags field */
  788. #define MPI2_IOUNIT8_SENSOR_FLAGS_T3_ENABLE (0x0008)
  789. #define MPI2_IOUNIT8_SENSOR_FLAGS_T2_ENABLE (0x0004)
  790. #define MPI2_IOUNIT8_SENSOR_FLAGS_T1_ENABLE (0x0002)
  791. #define MPI2_IOUNIT8_SENSOR_FLAGS_T0_ENABLE (0x0001)
  792. /*
  793. * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
  794. * one and check the value returned for NumSensors at runtime.
  795. */
  796. #ifndef MPI2_IOUNITPAGE8_SENSOR_ENTRIES
  797. #define MPI2_IOUNITPAGE8_SENSOR_ENTRIES (1)
  798. #endif
  799. typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_8 {
  800. MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
  801. U32 Reserved1; /* 0x04 */
  802. U32 Reserved2; /* 0x08 */
  803. U8 NumSensors; /* 0x0C */
  804. U8 PollingInterval; /* 0x0D */
  805. U16 Reserved3; /* 0x0E */
  806. MPI2_IOUNIT8_SENSOR
  807. Sensor[MPI2_IOUNITPAGE8_SENSOR_ENTRIES];/* 0x10 */
  808. } MPI2_CONFIG_PAGE_IO_UNIT_8, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_8,
  809. Mpi2IOUnitPage8_t, MPI2_POINTER pMpi2IOUnitPage8_t;
  810. #define MPI2_IOUNITPAGE8_PAGEVERSION (0x00)
  811. /* IO Unit Page 9 */
  812. typedef struct _MPI2_IOUNIT9_SENSOR {
  813. U16 CurrentTemperature; /* 0x00 */
  814. U16 Reserved1; /* 0x02 */
  815. U8 Flags; /* 0x04 */
  816. U8 Reserved2; /* 0x05 */
  817. U16 Reserved3; /* 0x06 */
  818. U32 Reserved4; /* 0x08 */
  819. U32 Reserved5; /* 0x0C */
  820. } MPI2_IOUNIT9_SENSOR, MPI2_POINTER PTR_MPI2_IOUNIT9_SENSOR,
  821. Mpi2IOUnit9Sensor_t, MPI2_POINTER pMpi2IOUnit9Sensor_t;
  822. /* defines for IO Unit Page 9 Sensor Flags field */
  823. #define MPI2_IOUNIT9_SENSOR_FLAGS_TEMP_VALID (0x01)
  824. /*
  825. * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
  826. * one and check the value returned for NumSensors at runtime.
  827. */
  828. #ifndef MPI2_IOUNITPAGE9_SENSOR_ENTRIES
  829. #define MPI2_IOUNITPAGE9_SENSOR_ENTRIES (1)
  830. #endif
  831. typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_9 {
  832. MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
  833. U32 Reserved1; /* 0x04 */
  834. U32 Reserved2; /* 0x08 */
  835. U8 NumSensors; /* 0x0C */
  836. U8 Reserved4; /* 0x0D */
  837. U16 Reserved3; /* 0x0E */
  838. MPI2_IOUNIT9_SENSOR
  839. Sensor[MPI2_IOUNITPAGE9_SENSOR_ENTRIES];/* 0x10 */
  840. } MPI2_CONFIG_PAGE_IO_UNIT_9, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_9,
  841. Mpi2IOUnitPage9_t, MPI2_POINTER pMpi2IOUnitPage9_t;
  842. #define MPI2_IOUNITPAGE9_PAGEVERSION (0x00)
  843. /* IO Unit Page 10 */
  844. typedef struct _MPI2_IOUNIT10_FUNCTION {
  845. U8 CreditPercent; /* 0x00 */
  846. U8 Reserved1; /* 0x01 */
  847. U16 Reserved2; /* 0x02 */
  848. } MPI2_IOUNIT10_FUNCTION, MPI2_POINTER PTR_MPI2_IOUNIT10_FUNCTION,
  849. Mpi2IOUnit10Function_t, MPI2_POINTER pMpi2IOUnit10Function_t;
  850. /*
  851. * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
  852. * one and check the value returned for NumFunctions at runtime.
  853. */
  854. #ifndef MPI2_IOUNITPAGE10_FUNCTION_ENTRIES
  855. #define MPI2_IOUNITPAGE10_FUNCTION_ENTRIES (1)
  856. #endif
  857. typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_10 {
  858. MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
  859. U8 NumFunctions; /* 0x04 */
  860. U8 Reserved1; /* 0x05 */
  861. U16 Reserved2; /* 0x06 */
  862. U32 Reserved3; /* 0x08 */
  863. U32 Reserved4; /* 0x0C */
  864. MPI2_IOUNIT10_FUNCTION
  865. Function[MPI2_IOUNITPAGE10_FUNCTION_ENTRIES];/* 0x10 */
  866. } MPI2_CONFIG_PAGE_IO_UNIT_10, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_10,
  867. Mpi2IOUnitPage10_t, MPI2_POINTER pMpi2IOUnitPage10_t;
  868. #define MPI2_IOUNITPAGE10_PAGEVERSION (0x01)
  869. /****************************************************************************
  870. * IOC Config Pages
  871. ****************************************************************************/
  872. /* IOC Page 0 */
  873. typedef struct _MPI2_CONFIG_PAGE_IOC_0
  874. {
  875. MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
  876. U32 Reserved1; /* 0x04 */
  877. U32 Reserved2; /* 0x08 */
  878. U16 VendorID; /* 0x0C */
  879. U16 DeviceID; /* 0x0E */
  880. U8 RevisionID; /* 0x10 */
  881. U8 Reserved3; /* 0x11 */
  882. U16 Reserved4; /* 0x12 */
  883. U32 ClassCode; /* 0x14 */
  884. U16 SubsystemVendorID; /* 0x18 */
  885. U16 SubsystemID; /* 0x1A */
  886. } MPI2_CONFIG_PAGE_IOC_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_0,
  887. Mpi2IOCPage0_t, MPI2_POINTER pMpi2IOCPage0_t;
  888. #define MPI2_IOCPAGE0_PAGEVERSION (0x02)
  889. /* IOC Page 1 */
  890. typedef struct _MPI2_CONFIG_PAGE_IOC_1
  891. {
  892. MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
  893. U32 Flags; /* 0x04 */
  894. U32 CoalescingTimeout; /* 0x08 */
  895. U8 CoalescingDepth; /* 0x0C */
  896. U8 PCISlotNum; /* 0x0D */
  897. U8 PCIBusNum; /* 0x0E */
  898. U8 PCIDomainSegment; /* 0x0F */
  899. U32 Reserved1; /* 0x10 */
  900. U32 Reserved2; /* 0x14 */
  901. } MPI2_CONFIG_PAGE_IOC_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_1,
  902. Mpi2IOCPage1_t, MPI2_POINTER pMpi2IOCPage1_t;
  903. #define MPI2_IOCPAGE1_PAGEVERSION (0x05)
  904. /* defines for IOC Page 1 Flags field */
  905. #define MPI2_IOCPAGE1_REPLY_COALESCING (0x00000001)
  906. #define MPI2_IOCPAGE1_PCISLOTNUM_UNKNOWN (0xFF)
  907. #define MPI2_IOCPAGE1_PCIBUSNUM_UNKNOWN (0xFF)
  908. #define MPI2_IOCPAGE1_PCIDOMAIN_UNKNOWN (0xFF)
  909. /* IOC Page 6 */
  910. typedef struct _MPI2_CONFIG_PAGE_IOC_6
  911. {
  912. MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
  913. U32 CapabilitiesFlags; /* 0x04 */
  914. U8 MaxDrivesRAID0; /* 0x08 */
  915. U8 MaxDrivesRAID1; /* 0x09 */
  916. U8 MaxDrivesRAID1E; /* 0x0A */
  917. U8 MaxDrivesRAID10; /* 0x0B */
  918. U8 MinDrivesRAID0; /* 0x0C */
  919. U8 MinDrivesRAID1; /* 0x0D */
  920. U8 MinDrivesRAID1E; /* 0x0E */
  921. U8 MinDrivesRAID10; /* 0x0F */
  922. U32 Reserved1; /* 0x10 */
  923. U8 MaxGlobalHotSpares; /* 0x14 */
  924. U8 MaxPhysDisks; /* 0x15 */
  925. U8 MaxVolumes; /* 0x16 */
  926. U8 MaxConfigs; /* 0x17 */
  927. U8 MaxOCEDisks; /* 0x18 */
  928. U8 Reserved2; /* 0x19 */
  929. U16 Reserved3; /* 0x1A */
  930. U32 SupportedStripeSizeMapRAID0; /* 0x1C */
  931. U32 SupportedStripeSizeMapRAID1E; /* 0x20 */
  932. U32 SupportedStripeSizeMapRAID10; /* 0x24 */
  933. U32 Reserved4; /* 0x28 */
  934. U32 Reserved5; /* 0x2C */
  935. U16 DefaultMetadataSize; /* 0x30 */
  936. U16 Reserved6; /* 0x32 */
  937. U16 MaxBadBlockTableEntries; /* 0x34 */
  938. U16 Reserved7; /* 0x36 */
  939. U32 IRNvsramVersion; /* 0x38 */
  940. } MPI2_CONFIG_PAGE_IOC_6, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_6,
  941. Mpi2IOCPage6_t, MPI2_POINTER pMpi2IOCPage6_t;
  942. #define MPI2_IOCPAGE6_PAGEVERSION (0x04)
  943. /* defines for IOC Page 6 CapabilitiesFlags */
  944. #define MPI2_IOCPAGE6_CAP_FLAGS_RAID10_SUPPORT (0x00000010)
  945. #define MPI2_IOCPAGE6_CAP_FLAGS_RAID1_SUPPORT (0x00000008)
  946. #define MPI2_IOCPAGE6_CAP_FLAGS_RAID1E_SUPPORT (0x00000004)
  947. #define MPI2_IOCPAGE6_CAP_FLAGS_RAID0_SUPPORT (0x00000002)
  948. #define MPI2_IOCPAGE6_CAP_FLAGS_GLOBAL_HOT_SPARE (0x00000001)
  949. /* IOC Page 7 */
  950. #define MPI2_IOCPAGE7_EVENTMASK_WORDS (4)
  951. typedef struct _MPI2_CONFIG_PAGE_IOC_7
  952. {
  953. MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
  954. U32 Reserved1; /* 0x04 */
  955. U32 EventMasks[MPI2_IOCPAGE7_EVENTMASK_WORDS];/* 0x08 */
  956. U16 SASBroadcastPrimitiveMasks; /* 0x18 */
  957. U16 SASNotifyPrimitiveMasks; /* 0x1A */
  958. U32 Reserved3; /* 0x1C */
  959. } MPI2_CONFIG_PAGE_IOC_7, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_7,
  960. Mpi2IOCPage7_t, MPI2_POINTER pMpi2IOCPage7_t;
  961. #define MPI2_IOCPAGE7_PAGEVERSION (0x02)
  962. /* IOC Page 8 */
  963. typedef struct _MPI2_CONFIG_PAGE_IOC_8
  964. {
  965. MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
  966. U8 NumDevsPerEnclosure; /* 0x04 */
  967. U8 Reserved1; /* 0x05 */
  968. U16 Reserved2; /* 0x06 */
  969. U16 MaxPersistentEntries; /* 0x08 */
  970. U16 MaxNumPhysicalMappedIDs; /* 0x0A */
  971. U16 Flags; /* 0x0C */
  972. U16 Reserved3; /* 0x0E */
  973. U16 IRVolumeMappingFlags; /* 0x10 */
  974. U16 Reserved4; /* 0x12 */
  975. U32 Reserved5; /* 0x14 */
  976. } MPI2_CONFIG_PAGE_IOC_8, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_8,
  977. Mpi2IOCPage8_t, MPI2_POINTER pMpi2IOCPage8_t;
  978. #define MPI2_IOCPAGE8_PAGEVERSION (0x00)
  979. /* defines for IOC Page 8 Flags field */
  980. #define MPI2_IOCPAGE8_FLAGS_DA_START_SLOT_1 (0x00000020)
  981. #define MPI2_IOCPAGE8_FLAGS_RESERVED_TARGETID_0 (0x00000010)
  982. #define MPI2_IOCPAGE8_FLAGS_MASK_MAPPING_MODE (0x0000000E)
  983. #define MPI2_IOCPAGE8_FLAGS_DEVICE_PERSISTENCE_MAPPING (0x00000000)
  984. #define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING (0x00000002)
  985. #define MPI2_IOCPAGE8_FLAGS_DISABLE_PERSISTENT_MAPPING (0x00000001)
  986. #define MPI2_IOCPAGE8_FLAGS_ENABLE_PERSISTENT_MAPPING (0x00000000)
  987. /* defines for IOC Page 8 IRVolumeMappingFlags */
  988. #define MPI2_IOCPAGE8_IRFLAGS_MASK_VOLUME_MAPPING_MODE (0x00000003)
  989. #define MPI2_IOCPAGE8_IRFLAGS_LOW_VOLUME_MAPPING (0x00000000)
  990. #define MPI2_IOCPAGE8_IRFLAGS_HIGH_VOLUME_MAPPING (0x00000001)
  991. /****************************************************************************
  992. * BIOS Config Pages
  993. ****************************************************************************/
  994. /* BIOS Page 1 */
  995. typedef struct _MPI2_CONFIG_PAGE_BIOS_1
  996. {
  997. MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
  998. U32 BiosOptions; /* 0x04 */
  999. U32 IOCSettings; /* 0x08 */
  1000. U32 Reserved1; /* 0x0C */
  1001. U32 DeviceSettings; /* 0x10 */
  1002. U16 NumberOfDevices; /* 0x14 */
  1003. U16 Reserved2; /* 0x16 */
  1004. U16 IOTimeoutBlockDevicesNonRM; /* 0x18 */
  1005. U16 IOTimeoutSequential; /* 0x1A */
  1006. U16 IOTimeoutOther; /* 0x1C */
  1007. U16 IOTimeoutBlockDevicesRM; /* 0x1E */
  1008. } MPI2_CONFIG_PAGE_BIOS_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_1,
  1009. Mpi2BiosPage1_t, MPI2_POINTER pMpi2BiosPage1_t;
  1010. #define MPI2_BIOSPAGE1_PAGEVERSION (0x04)
  1011. /* values for BIOS Page 1 BiosOptions field */
  1012. #define MPI2_BIOSPAGE1_OPTIONS_DISABLE_BIOS (0x00000001)
  1013. /* values for BIOS Page 1 IOCSettings field */
  1014. #define MPI2_BIOSPAGE1_IOCSET_MASK_BOOT_PREFERENCE (0x00030000)
  1015. #define MPI2_BIOSPAGE1_IOCSET_ENCLOSURE_SLOT_BOOT (0x00000000)
  1016. #define MPI2_BIOSPAGE1_IOCSET_SAS_ADDRESS_BOOT (0x00010000)
  1017. #define MPI2_BIOSPAGE1_IOCSET_MASK_RM_SETTING (0x000000C0)
  1018. #define MPI2_BIOSPAGE1_IOCSET_NONE_RM_SETTING (0x00000000)
  1019. #define MPI2_BIOSPAGE1_IOCSET_BOOT_RM_SETTING (0x00000040)
  1020. #define MPI2_BIOSPAGE1_IOCSET_MEDIA_RM_SETTING (0x00000080)
  1021. #define MPI2_BIOSPAGE1_IOCSET_MASK_ADAPTER_SUPPORT (0x00000030)
  1022. #define MPI2_BIOSPAGE1_IOCSET_NO_SUPPORT (0x00000000)
  1023. #define MPI2_BIOSPAGE1_IOCSET_BIOS_SUPPORT (0x00000010)
  1024. #define MPI2_BIOSPAGE1_IOCSET_OS_SUPPORT (0x00000020)
  1025. #define MPI2_BIOSPAGE1_IOCSET_ALL_SUPPORT (0x00000030)
  1026. #define MPI2_BIOSPAGE1_IOCSET_ALTERNATE_CHS (0x00000008)
  1027. /* values for BIOS Page 1 DeviceSettings field */
  1028. #define MPI2_BIOSPAGE1_DEVSET_DISABLE_SMART_POLLING (0x00000010)
  1029. #define MPI2_BIOSPAGE1_DEVSET_DISABLE_SEQ_LUN (0x00000008)
  1030. #define MPI2_BIOSPAGE1_DEVSET_DISABLE_RM_LUN (0x00000004)
  1031. #define MPI2_BIOSPAGE1_DEVSET_DISABLE_NON_RM_LUN (0x00000002)
  1032. #define MPI2_BIOSPAGE1_DEVSET_DISABLE_OTHER_LUN (0x00000001)
  1033. /* BIOS Page 2 */
  1034. typedef struct _MPI2_BOOT_DEVICE_ADAPTER_ORDER
  1035. {
  1036. U32 Reserved1; /* 0x00 */
  1037. U32 Reserved2; /* 0x04 */
  1038. U32 Reserved3; /* 0x08 */
  1039. U32 Reserved4; /* 0x0C */
  1040. U32 Reserved5; /* 0x10 */
  1041. U32 Reserved6; /* 0x14 */
  1042. } MPI2_BOOT_DEVICE_ADAPTER_ORDER,
  1043. MPI2_POINTER PTR_MPI2_BOOT_DEVICE_ADAPTER_ORDER,
  1044. Mpi2BootDeviceAdapterOrder_t, MPI2_POINTER pMpi2BootDeviceAdapterOrder_t;
  1045. typedef struct _MPI2_BOOT_DEVICE_SAS_WWID
  1046. {
  1047. U64 SASAddress; /* 0x00 */
  1048. U8 LUN[8]; /* 0x08 */
  1049. U32 Reserved1; /* 0x10 */
  1050. U32 Reserved2; /* 0x14 */
  1051. } MPI2_BOOT_DEVICE_SAS_WWID, MPI2_POINTER PTR_MPI2_BOOT_DEVICE_SAS_WWID,
  1052. Mpi2BootDeviceSasWwid_t, MPI2_POINTER pMpi2BootDeviceSasWwid_t;
  1053. typedef struct _MPI2_BOOT_DEVICE_ENCLOSURE_SLOT
  1054. {
  1055. U64 EnclosureLogicalID; /* 0x00 */
  1056. U32 Reserved1; /* 0x08 */
  1057. U32 Reserved2; /* 0x0C */
  1058. U16 SlotNumber; /* 0x10 */
  1059. U16 Reserved3; /* 0x12 */
  1060. U32 Reserved4; /* 0x14 */
  1061. } MPI2_BOOT_DEVICE_ENCLOSURE_SLOT,
  1062. MPI2_POINTER PTR_MPI2_BOOT_DEVICE_ENCLOSURE_SLOT,
  1063. Mpi2BootDeviceEnclosureSlot_t, MPI2_POINTER pMpi2BootDeviceEnclosureSlot_t;
  1064. typedef struct _MPI2_BOOT_DEVICE_DEVICE_NAME
  1065. {
  1066. U64 DeviceName; /* 0x00 */
  1067. U8 LUN[8]; /* 0x08 */
  1068. U32 Reserved1; /* 0x10 */
  1069. U32 Reserved2; /* 0x14 */
  1070. } MPI2_BOOT_DEVICE_DEVICE_NAME, MPI2_POINTER PTR_MPI2_BOOT_DEVICE_DEVICE_NAME,
  1071. Mpi2BootDeviceDeviceName_t, MPI2_POINTER pMpi2BootDeviceDeviceName_t;
  1072. typedef union _MPI2_MPI2_BIOSPAGE2_BOOT_DEVICE
  1073. {
  1074. MPI2_BOOT_DEVICE_ADAPTER_ORDER AdapterOrder;
  1075. MPI2_BOOT_DEVICE_SAS_WWID SasWwid;
  1076. MPI2_BOOT_DEVICE_ENCLOSURE_SLOT EnclosureSlot;
  1077. MPI2_BOOT_DEVICE_DEVICE_NAME DeviceName;
  1078. } MPI2_BIOSPAGE2_BOOT_DEVICE, MPI2_POINTER PTR_MPI2_BIOSPAGE2_BOOT_DEVICE,
  1079. Mpi2BiosPage2BootDevice_t, MPI2_POINTER pMpi2BiosPage2BootDevice_t;
  1080. typedef struct _MPI2_CONFIG_PAGE_BIOS_2
  1081. {
  1082. MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
  1083. U32 Reserved1; /* 0x04 */
  1084. U32 Reserved2; /* 0x08 */
  1085. U32 Reserved3; /* 0x0C */
  1086. U32 Reserved4; /* 0x10 */
  1087. U32 Reserved5; /* 0x14 */
  1088. U32 Reserved6; /* 0x18 */
  1089. U8 ReqBootDeviceForm; /* 0x1C */
  1090. U8 Reserved7; /* 0x1D */
  1091. U16 Reserved8; /* 0x1E */
  1092. MPI2_BIOSPAGE2_BOOT_DEVICE RequestedBootDevice; /* 0x20 */
  1093. U8 ReqAltBootDeviceForm; /* 0x38 */
  1094. U8 Reserved9; /* 0x39 */
  1095. U16 Reserved10; /* 0x3A */
  1096. MPI2_BIOSPAGE2_BOOT_DEVICE RequestedAltBootDevice; /* 0x3C */
  1097. U8 CurrentBootDeviceForm; /* 0x58 */
  1098. U8 Reserved11; /* 0x59 */
  1099. U16 Reserved12; /* 0x5A */
  1100. MPI2_BIOSPAGE2_BOOT_DEVICE CurrentBootDevice; /* 0x58 */
  1101. } MPI2_CONFIG_PAGE_BIOS_2, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_2,
  1102. Mpi2BiosPage2_t, MPI2_POINTER pMpi2BiosPage2_t;
  1103. #define MPI2_BIOSPAGE2_PAGEVERSION (0x04)
  1104. /* values for BIOS Page 2 BootDeviceForm fields */
  1105. #define MPI2_BIOSPAGE2_FORM_MASK (0x0F)
  1106. #define MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED (0x00)
  1107. #define MPI2_BIOSPAGE2_FORM_SAS_WWID (0x05)
  1108. #define MPI2_BIOSPAGE2_FORM_ENCLOSURE_SLOT (0x06)
  1109. #define MPI2_BIOSPAGE2_FORM_DEVICE_NAME (0x07)
  1110. /* BIOS Page 3 */
  1111. typedef struct _MPI2_ADAPTER_INFO
  1112. {
  1113. U8 PciBusNumber; /* 0x00 */
  1114. U8 PciDeviceAndFunctionNumber; /* 0x01 */
  1115. U16 AdapterFlags; /* 0x02 */
  1116. } MPI2_ADAPTER_INFO, MPI2_POINTER PTR_MPI2_ADAPTER_INFO,
  1117. Mpi2AdapterInfo_t, MPI2_POINTER pMpi2AdapterInfo_t;
  1118. #define MPI2_ADAPTER_INFO_FLAGS_EMBEDDED (0x0001)
  1119. #define MPI2_ADAPTER_INFO_FLAGS_INIT_STATUS (0x0002)
  1120. typedef struct _MPI2_CONFIG_PAGE_BIOS_3
  1121. {
  1122. MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
  1123. U32 GlobalFlags; /* 0x04 */
  1124. U32 BiosVersion; /* 0x08 */
  1125. MPI2_ADAPTER_INFO AdapterOrder[4]; /* 0x0C */
  1126. U32 Reserved1; /* 0x1C */
  1127. } MPI2_CONFIG_PAGE_BIOS_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_3,
  1128. Mpi2BiosPage3_t, MPI2_POINTER pMpi2BiosPage3_t;
  1129. #define MPI2_BIOSPAGE3_PAGEVERSION (0x00)
  1130. /* values for BIOS Page 3 GlobalFlags */
  1131. #define MPI2_BIOSPAGE3_FLAGS_PAUSE_ON_ERROR (0x00000002)
  1132. #define MPI2_BIOSPAGE3_FLAGS_VERBOSE_ENABLE (0x00000004)
  1133. #define MPI2_BIOSPAGE3_FLAGS_HOOK_INT_40_DISABLE (0x00000010)
  1134. #define MPI2_BIOSPAGE3_FLAGS_DEV_LIST_DISPLAY_MASK (0x000000E0)
  1135. #define MPI2_BIOSPAGE3_FLAGS_INSTALLED_DEV_DISPLAY (0x00000000)
  1136. #define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DISPLAY (0x00000020)
  1137. #define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DEV_DISPLAY (0x00000040)
  1138. /* BIOS Page 4 */
  1139. /*
  1140. * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
  1141. * one and check the value returned for NumPhys at runtime.
  1142. */
  1143. #ifndef MPI2_BIOS_PAGE_4_PHY_ENTRIES
  1144. #define MPI2_BIOS_PAGE_4_PHY_ENTRIES (1)
  1145. #endif
  1146. typedef struct _MPI2_BIOS4_ENTRY
  1147. {
  1148. U64 ReassignmentWWID; /* 0x00 */
  1149. U64 ReassignmentDeviceName; /* 0x08 */
  1150. } MPI2_BIOS4_ENTRY, MPI2_POINTER PTR_MPI2_BIOS4_ENTRY,
  1151. Mpi2MBios4Entry_t, MPI2_POINTER pMpi2Bios4Entry_t;
  1152. typedef struct _MPI2_CONFIG_PAGE_BIOS_4
  1153. {
  1154. MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
  1155. U8 NumPhys; /* 0x04 */
  1156. U8 Reserved1; /* 0x05 */
  1157. U16 Reserved2; /* 0x06 */
  1158. MPI2_BIOS4_ENTRY Phy[MPI2_BIOS_PAGE_4_PHY_ENTRIES]; /* 0x08 */
  1159. } MPI2_CONFIG_PAGE_BIOS_4, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_4,
  1160. Mpi2BiosPage4_t, MPI2_POINTER pMpi2BiosPage4_t;
  1161. #define MPI2_BIOSPAGE4_PAGEVERSION (0x01)
  1162. /****************************************************************************
  1163. * RAID Volume Config Pages
  1164. ****************************************************************************/
  1165. /* RAID Volume Page 0 */
  1166. typedef struct _MPI2_RAIDVOL0_PHYS_DISK
  1167. {
  1168. U8 RAIDSetNum; /* 0x00 */
  1169. U8 PhysDiskMap; /* 0x01 */
  1170. U8 PhysDiskNum; /* 0x02 */
  1171. U8 Reserved; /* 0x03 */
  1172. } MPI2_RAIDVOL0_PHYS_DISK, MPI2_POINTER PTR_MPI2_RAIDVOL0_PHYS_DISK,
  1173. Mpi2RaidVol0PhysDisk_t, MPI2_POINTER pMpi2RaidVol0PhysDisk_t;
  1174. /* defines for the PhysDiskMap field */
  1175. #define MPI2_RAIDVOL0_PHYSDISK_PRIMARY (0x01)
  1176. #define MPI2_RAIDVOL0_PHYSDISK_SECONDARY (0x02)
  1177. typedef struct _MPI2_RAIDVOL0_SETTINGS
  1178. {
  1179. U16 Settings; /* 0x00 */
  1180. U8 HotSparePool; /* 0x01 */
  1181. U8 Reserved; /* 0x02 */
  1182. } MPI2_RAIDVOL0_SETTINGS, MPI2_POINTER PTR_MPI2_RAIDVOL0_SETTINGS,
  1183. Mpi2RaidVol0Settings_t, MPI2_POINTER pMpi2RaidVol0Settings_t;
  1184. /* RAID Volume Page 0 HotSparePool defines, also used in RAID Physical Disk */
  1185. #define MPI2_RAID_HOT_SPARE_POOL_0 (0x01)
  1186. #define MPI2_RAID_HOT_SPARE_POOL_1 (0x02)
  1187. #define MPI2_RAID_HOT_SPARE_POOL_2 (0x04)
  1188. #define MPI2_RAID_HOT_SPARE_POOL_3 (0x08)
  1189. #define MPI2_RAID_HOT_SPARE_POOL_4 (0x10)
  1190. #define MPI2_RAID_HOT_SPARE_POOL_5 (0x20)
  1191. #define MPI2_RAID_HOT_SPARE_POOL_6 (0x40)
  1192. #define MPI2_RAID_HOT_SPARE_POOL_7 (0x80)
  1193. /* RAID Volume Page 0 VolumeSettings defines */
  1194. #define MPI2_RAIDVOL0_SETTING_USE_PRODUCT_ID_SUFFIX (0x0008)
  1195. #define MPI2_RAIDVOL0_SETTING_AUTO_CONFIG_HSWAP_DISABLE (0x0004)
  1196. #define MPI2_RAIDVOL0_SETTING_MASK_WRITE_CACHING (0x0003)
  1197. #define MPI2_RAIDVOL0_SETTING_UNCHANGED (0x0000)
  1198. #define MPI2_RAIDVOL0_SETTING_DISABLE_WRITE_CACHING (0x0001)
  1199. #define MPI2_RAIDVOL0_SETTING_ENABLE_WRITE_CACHING (0x0002)
  1200. /*
  1201. * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
  1202. * one and check the value returned for NumPhysDisks at runtime.
  1203. */
  1204. #ifndef MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX
  1205. #define MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX (1)
  1206. #endif
  1207. typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_0
  1208. {
  1209. MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
  1210. U16 DevHandle; /* 0x04 */
  1211. U8 VolumeState; /* 0x06 */
  1212. U8 VolumeType; /* 0x07 */
  1213. U32 VolumeStatusFlags; /* 0x08 */
  1214. MPI2_RAIDVOL0_SETTINGS VolumeSettings; /* 0x0C */
  1215. U64 MaxLBA; /* 0x10 */
  1216. U32 StripeSize; /* 0x18 */
  1217. U16 BlockSize; /* 0x1C */
  1218. U16 Reserved1; /* 0x1E */
  1219. U8 SupportedPhysDisks; /* 0x20 */
  1220. U8 ResyncRate; /* 0x21 */
  1221. U16 DataScrubDuration; /* 0x22 */
  1222. U8 NumPhysDisks; /* 0x24 */
  1223. U8 Reserved2; /* 0x25 */
  1224. U8 Reserved3; /* 0x26 */
  1225. U8 InactiveStatus; /* 0x27 */
  1226. MPI2_RAIDVOL0_PHYS_DISK PhysDisk[MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX]; /* 0x28 */
  1227. } MPI2_CONFIG_PAGE_RAID_VOL_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_VOL_0,
  1228. Mpi2RaidVolPage0_t, MPI2_POINTER pMpi2RaidVolPage0_t;
  1229. #define MPI2_RAIDVOLPAGE0_PAGEVERSION (0x0A)
  1230. /* values for RAID VolumeState */
  1231. #define MPI2_RAID_VOL_STATE_MISSING (0x00)
  1232. #define MPI2_RAID_VOL_STATE_FAILED (0x01)
  1233. #define MPI2_RAID_VOL_STATE_INITIALIZING (0x02)
  1234. #define MPI2_RAID_VOL_STATE_ONLINE (0x03)
  1235. #define MPI2_RAID_VOL_STATE_DEGRADED (0x04)
  1236. #define MPI2_RAID_VOL_STATE_OPTIMAL (0x05)
  1237. /* values for RAID VolumeType */
  1238. #define MPI2_RAID_VOL_TYPE_RAID0 (0x00)
  1239. #define MPI2_RAID_VOL_TYPE_RAID1E (0x01)
  1240. #define MPI2_RAID_VOL_TYPE_RAID1 (0x02)
  1241. #define MPI2_RAID_VOL_TYPE_RAID10 (0x05)
  1242. #define MPI2_RAID_VOL_TYPE_UNKNOWN (0xFF)
  1243. /* values for RAID Volume Page 0 VolumeStatusFlags field */
  1244. #define MPI2_RAIDVOL0_STATUS_FLAG_PENDING_RESYNC (0x02000000)
  1245. #define MPI2_RAIDVOL0_STATUS_FLAG_BACKG_INIT_PENDING (0x01000000)
  1246. #define MPI2_RAIDVOL0_STATUS_FLAG_MDC_PENDING (0x00800000)
  1247. #define MPI2_RAIDVOL0_STATUS_FLAG_USER_CONSIST_PENDING (0x00400000)
  1248. #define MPI2_RAIDVOL0_STATUS_FLAG_MAKE_DATA_CONSISTENT (0x00200000)
  1249. #define MPI2_RAIDVOL0_STATUS_FLAG_DATA_SCRUB (0x00100000)
  1250. #define MPI2_RAIDVOL0_STATUS_FLAG_CONSISTENCY_CHECK (0x00080000)
  1251. #define MPI2_RAIDVOL0_STATUS_FLAG_CAPACITY_EXPANSION (0x00040000)
  1252. #define MPI2_RAIDVOL0_STATUS_FLAG_BACKGROUND_INIT (0x00020000)
  1253. #define MPI2_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS (0x00010000)
  1254. #define MPI2_RAIDVOL0_STATUS_FLAG_VOL_NOT_CONSISTENT (0x00000080)
  1255. #define MPI2_RAIDVOL0_STATUS_FLAG_OCE_ALLOWED (0x00000040)
  1256. #define MPI2_RAIDVOL0_STATUS_FLAG_BGI_COMPLETE (0x00000020)
  1257. #define MPI2_RAIDVOL0_STATUS_FLAG_1E_OFFSET_MIRROR (0x00000000)
  1258. #define MPI2_RAIDVOL0_STATUS_FLAG_1E_ADJACENT_MIRROR (0x00000010)
  1259. #define MPI2_RAIDVOL0_STATUS_FLAG_BAD_BLOCK_TABLE_FULL (0x00000008)
  1260. #define MPI2_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE (0x00000004)
  1261. #define MPI2_RAIDVOL0_STATUS_FLAG_QUIESCED (0x00000002)
  1262. #define MPI2_RAIDVOL0_STATUS_FLAG_ENABLED (0x00000001)
  1263. /* values for RAID Volume Page 0 SupportedPhysDisks field */
  1264. #define MPI2_RAIDVOL0_SUPPORT_SOLID_STATE_DISKS (0x08)
  1265. #define MPI2_RAIDVOL0_SUPPORT_HARD_DISKS (0x04)
  1266. #define MPI2_RAIDVOL0_SUPPORT_SAS_PROTOCOL (0x02)
  1267. #define MPI2_RAIDVOL0_SUPPORT_SATA_PROTOCOL (0x01)
  1268. /* values for RAID Volume Page 0 InactiveStatus field */
  1269. #define MPI2_RAIDVOLPAGE0_UNKNOWN_INACTIVE (0x00)
  1270. #define MPI2_RAIDVOLPAGE0_STALE_METADATA_INACTIVE (0x01)
  1271. #define MPI2_RAIDVOLPAGE0_FOREIGN_VOLUME_INACTIVE (0x02)
  1272. #define MPI2_RAIDVOLPAGE0_INSUFFICIENT_RESOURCE_INACTIVE (0x03)
  1273. #define MPI2_RAIDVOLPAGE0_CLONE_VOLUME_INACTIVE (0x04)
  1274. #define MPI2_RAIDVOLPAGE0_INSUFFICIENT_METADATA_INACTIVE (0x05)
  1275. #define MPI2_RAIDVOLPAGE0_PREVIOUSLY_DELETED (0x06)
  1276. /* RAID Volume Page 1 */
  1277. typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_1
  1278. {
  1279. MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
  1280. U16 DevHandle; /* 0x04 */
  1281. U16 Reserved0; /* 0x06 */
  1282. U8 GUID[24]; /* 0x08 */
  1283. U8 Name[16]; /* 0x20 */
  1284. U64 WWID; /* 0x30 */
  1285. U32 Reserved1; /* 0x38 */
  1286. U32 Reserved2; /* 0x3C */
  1287. } MPI2_CONFIG_PAGE_RAID_VOL_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_VOL_1,
  1288. Mpi2RaidVolPage1_t, MPI2_POINTER pMpi2RaidVolPage1_t;
  1289. #define MPI2_RAIDVOLPAGE1_PAGEVERSION (0x03)
  1290. /****************************************************************************
  1291. * RAID Physical Disk Config Pages
  1292. ****************************************************************************/
  1293. /* RAID Physical Disk Page 0 */
  1294. typedef struct _MPI2_RAIDPHYSDISK0_SETTINGS
  1295. {
  1296. U16 Reserved1; /* 0x00 */
  1297. U8 HotSparePool; /* 0x02 */
  1298. U8 Reserved2; /* 0x03 */
  1299. } MPI2_RAIDPHYSDISK0_SETTINGS, MPI2_POINTER PTR_MPI2_RAIDPHYSDISK0_SETTINGS,
  1300. Mpi2RaidPhysDisk0Settings_t, MPI2_POINTER pMpi2RaidPhysDisk0Settings_t;
  1301. /* use MPI2_RAID_HOT_SPARE_POOL_ defines for the HotSparePool field */
  1302. typedef struct _MPI2_RAIDPHYSDISK0_INQUIRY_DATA
  1303. {
  1304. U8 VendorID[8]; /* 0x00 */
  1305. U8 ProductID[16]; /* 0x08 */
  1306. U8 ProductRevLevel[4]; /* 0x18 */
  1307. U8 SerialNum[32]; /* 0x1C */
  1308. } MPI2_RAIDPHYSDISK0_INQUIRY_DATA,
  1309. MPI2_POINTER PTR_MPI2_RAIDPHYSDISK0_INQUIRY_DATA,
  1310. Mpi2RaidPhysDisk0InquiryData_t, MPI2_POINTER pMpi2RaidPhysDisk0InquiryData_t;
  1311. typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_0
  1312. {
  1313. MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
  1314. U16 DevHandle; /* 0x04 */
  1315. U8 Reserved1; /* 0x06 */
  1316. U8 PhysDiskNum; /* 0x07 */
  1317. MPI2_RAIDPHYSDISK0_SETTINGS PhysDiskSettings; /* 0x08 */
  1318. U32 Reserved2; /* 0x0C */
  1319. MPI2_RAIDPHYSDISK0_INQUIRY_DATA InquiryData; /* 0x10 */
  1320. U32 Reserved3; /* 0x4C */
  1321. U8 PhysDiskState; /* 0x50 */
  1322. U8 OfflineReason; /* 0x51 */
  1323. U8 IncompatibleReason; /* 0x52 */
  1324. U8 PhysDiskAttributes; /* 0x53 */
  1325. U32 PhysDiskStatusFlags; /* 0x54 */
  1326. U64 DeviceMaxLBA; /* 0x58 */
  1327. U64 HostMaxLBA; /* 0x60 */
  1328. U64 CoercedMaxLBA; /* 0x68 */
  1329. U16 BlockSize; /* 0x70 */
  1330. U16 Reserved5; /* 0x72 */
  1331. U32 Reserved6; /* 0x74 */
  1332. } MPI2_CONFIG_PAGE_RD_PDISK_0,
  1333. MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RD_PDISK_0,
  1334. Mpi2RaidPhysDiskPage0_t, MPI2_POINTER pMpi2RaidPhysDiskPage0_t;
  1335. #define MPI2_RAIDPHYSDISKPAGE0_PAGEVERSION (0x05)
  1336. /* PhysDiskState defines */
  1337. #define MPI2_RAID_PD_STATE_NOT_CONFIGURED (0x00)
  1338. #define MPI2_RAID_PD_STATE_NOT_COMPATIBLE (0x01)
  1339. #define MPI2_RAID_PD_STATE_OFFLINE (0x02)
  1340. #define MPI2_RAID_PD_STATE_ONLINE (0x03)
  1341. #define MPI2_RAID_PD_STATE_HOT_SPARE (0x04)
  1342. #define MPI2_RAID_PD_STATE_DEGRADED (0x05)
  1343. #define MPI2_RAID_PD_STATE_REBUILDING (0x06)
  1344. #define MPI2_RAID_PD_STATE_OPTIMAL (0x07)
  1345. /* OfflineReason defines */
  1346. #define MPI2_PHYSDISK0_ONLINE (0x00)
  1347. #define MPI2_PHYSDISK0_OFFLINE_MISSING (0x01)
  1348. #define MPI2_PHYSDISK0_OFFLINE_FAILED (0x03)
  1349. #define MPI2_PHYSDISK0_OFFLINE_INITIALIZING (0x04)
  1350. #define MPI2_PHYSDISK0_OFFLINE_REQUESTED (0x05)
  1351. #define MPI2_PHYSDISK0_OFFLINE_FAILED_REQUESTED (0x06)
  1352. #define MPI2_PHYSDISK0_OFFLINE_OTHER (0xFF)
  1353. /* IncompatibleReason defines */
  1354. #define MPI2_PHYSDISK0_COMPATIBLE (0x00)
  1355. #define MPI2_PHYSDISK0_INCOMPATIBLE_PROTOCOL (0x01)
  1356. #define MPI2_PHYSDISK0_INCOMPATIBLE_BLOCKSIZE (0x02)
  1357. #define MPI2_PHYSDISK0_INCOMPATIBLE_MAX_LBA (0x03)
  1358. #define MPI2_PHYSDISK0_INCOMPATIBLE_SATA_EXTENDED_CMD (0x04)
  1359. #define MPI2_PHYSDISK0_INCOMPATIBLE_REMOVEABLE_MEDIA (0x05)
  1360. #define MPI2_PHYSDISK0_INCOMPATIBLE_MEDIA_TYPE (0x06)
  1361. #define MPI2_PHYSDISK0_INCOMPATIBLE_UNKNOWN (0xFF)
  1362. /* PhysDiskAttributes defines */
  1363. #define MPI2_PHYSDISK0_ATTRIB_MEDIA_MASK (0x0C)
  1364. #define MPI2_PHYSDISK0_ATTRIB_SOLID_STATE_DRIVE (0x08)
  1365. #define MPI2_PHYSDISK0_ATTRIB_HARD_DISK_DRIVE (0x04)
  1366. #define MPI2_PHYSDISK0_ATTRIB_PROTOCOL_MASK (0x03)
  1367. #define MPI2_PHYSDISK0_ATTRIB_SAS_PROTOCOL (0x02)
  1368. #define MPI2_PHYSDISK0_ATTRIB_SATA_PROTOCOL (0x01)
  1369. /* PhysDiskStatusFlags defines */
  1370. #define MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED (0x00000040)
  1371. #define MPI2_PHYSDISK0_STATUS_FLAG_OCE_TARGET (0x00000020)
  1372. #define MPI2_PHYSDISK0_STATUS_FLAG_WRITE_CACHE_ENABLED (0x00000010)
  1373. #define MPI2_PHYSDISK0_STATUS_FLAG_OPTIMAL_PREVIOUS (0x00000000)
  1374. #define MPI2_PHYSDISK0_STATUS_FLAG_NOT_OPTIMAL_PREVIOUS (0x00000008)
  1375. #define MPI2_PHYSDISK0_STATUS_FLAG_INACTIVE_VOLUME (0x00000004)
  1376. #define MPI2_PHYSDISK0_STATUS_FLAG_QUIESCED (0x00000002)
  1377. #define MPI2_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC (0x00000001)
  1378. /* RAID Physical Disk Page 1 */
  1379. /*
  1380. * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
  1381. * one and check the value returned for NumPhysDiskPaths at runtime.
  1382. */
  1383. #ifndef MPI2_RAID_PHYS_DISK1_PATH_MAX
  1384. #define MPI2_RAID_PHYS_DISK1_PATH_MAX (1)
  1385. #endif
  1386. typedef struct _MPI2_RAIDPHYSDISK1_PATH
  1387. {
  1388. U16 DevHandle; /* 0x00 */
  1389. U16 Reserved1; /* 0x02 */
  1390. U64 WWID; /* 0x04 */
  1391. U64 OwnerWWID; /* 0x0C */
  1392. U8 OwnerIdentifier; /* 0x14 */
  1393. U8 Reserved2; /* 0x15 */
  1394. U16 Flags; /* 0x16 */
  1395. } MPI2_RAIDPHYSDISK1_PATH, MPI2_POINTER PTR_MPI2_RAIDPHYSDISK1_PATH,
  1396. Mpi2RaidPhysDisk1Path_t, MPI2_POINTER pMpi2RaidPhysDisk1Path_t;
  1397. /* RAID Physical Disk Page 1 Physical Disk Path Flags field defines */
  1398. #define MPI2_RAID_PHYSDISK1_FLAG_PRIMARY (0x0004)
  1399. #define MPI2_RAID_PHYSDISK1_FLAG_BROKEN (0x0002)
  1400. #define MPI2_RAID_PHYSDISK1_FLAG_INVALID (0x0001)
  1401. typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_1
  1402. {
  1403. MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
  1404. U8 NumPhysDiskPaths; /* 0x04 */
  1405. U8 PhysDiskNum; /* 0x05 */
  1406. U16 Reserved1; /* 0x06 */
  1407. U32 Reserved2; /* 0x08 */
  1408. MPI2_RAIDPHYSDISK1_PATH PhysicalDiskPath[MPI2_RAID_PHYS_DISK1_PATH_MAX];/* 0x0C */
  1409. } MPI2_CONFIG_PAGE_RD_PDISK_1,
  1410. MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RD_PDISK_1,
  1411. Mpi2RaidPhysDiskPage1_t, MPI2_POINTER pMpi2RaidPhysDiskPage1_t;
  1412. #define MPI2_RAIDPHYSDISKPAGE1_PAGEVERSION (0x02)
  1413. /****************************************************************************
  1414. * values for fields used by several types of SAS Config Pages
  1415. ****************************************************************************/
  1416. /* values for NegotiatedLinkRates fields */
  1417. #define MPI2_SAS_NEG_LINK_RATE_MASK_LOGICAL (0xF0)
  1418. #define MPI2_SAS_NEG_LINK_RATE_SHIFT_LOGICAL (4)
  1419. #define MPI2_SAS_NEG_LINK_RATE_MASK_PHYSICAL (0x0F)
  1420. /* link rates used for Negotiated Physical and Logical Link Rate */
  1421. #define MPI2_SAS_NEG_LINK_RATE_UNKNOWN_LINK_RATE (0x00)
  1422. #define MPI2_SAS_NEG_LINK_RATE_PHY_DISABLED (0x01)
  1423. #define MPI2_SAS_NEG_LINK_RATE_NEGOTIATION_FAILED (0x02)
  1424. #define MPI2_SAS_NEG_LINK_RATE_SATA_OOB_COMPLETE (0x03)
  1425. #define MPI2_SAS_NEG_LINK_RATE_PORT_SELECTOR (0x04)
  1426. #define MPI2_SAS_NEG_LINK_RATE_SMP_RESET_IN_PROGRESS (0x05)
  1427. #define MPI2_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY (0x06)
  1428. #define MPI2_SAS_NEG_LINK_RATE_1_5 (0x08)
  1429. #define MPI2_SAS_NEG_LINK_RATE_3_0 (0x09)
  1430. #define MPI2_SAS_NEG_LINK_RATE_6_0 (0x0A)
  1431. /* values for AttachedPhyInfo fields */
  1432. #define MPI2_SAS_APHYINFO_INSIDE_ZPSDS_PERSISTENT (0x00000040)
  1433. #define MPI2_SAS_APHYINFO_REQUESTED_INSIDE_ZPSDS (0x00000020)
  1434. #define MPI2_SAS_APHYINFO_BREAK_REPLY_CAPABLE (0x00000010)
  1435. #define MPI2_SAS_APHYINFO_REASON_MASK (0x0000000F)
  1436. #define MPI2_SAS_APHYINFO_REASON_UNKNOWN (0x00000000)
  1437. #define MPI2_SAS_APHYINFO_REASON_POWER_ON (0x00000001)
  1438. #define MPI2_SAS_APHYINFO_REASON_HARD_RESET (0x00000002)
  1439. #define MPI2_SAS_APHYINFO_REASON_SMP_PHY_CONTROL (0x00000003)
  1440. #define MPI2_SAS_APHYINFO_REASON_LOSS_OF_SYNC (0x00000004)
  1441. #define MPI2_SAS_APHYINFO_REASON_MULTIPLEXING_SEQ (0x00000005)
  1442. #define MPI2_SAS_APHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00000006)
  1443. #define MPI2_SAS_APHYINFO_REASON_BREAK_TIMEOUT (0x00000007)
  1444. #define MPI2_SAS_APHYINFO_REASON_PHY_TEST_STOPPED (0x00000008)
  1445. /* values for PhyInfo fields */
  1446. #define MPI2_SAS_PHYINFO_PHY_VACANT (0x80000000)
  1447. #define MPI2_SAS_PHYINFO_PHY_POWER_CONDITION_MASK (0x18000000)
  1448. #define MPI2_SAS_PHYINFO_SHIFT_PHY_POWER_CONDITION (27)
  1449. #define MPI2_SAS_PHYINFO_PHY_POWER_ACTIVE (0x00000000)
  1450. #define MPI2_SAS_PHYINFO_PHY_POWER_PARTIAL (0x08000000)
  1451. #define MPI2_SAS_PHYINFO_PHY_POWER_SLUMBER (0x10000000)
  1452. #define MPI2_SAS_PHYINFO_CHANGED_REQ_INSIDE_ZPSDS (0x04000000)
  1453. #define MPI2_SAS_PHYINFO_INSIDE_ZPSDS_PERSISTENT (0x02000000)
  1454. #define MPI2_SAS_PHYINFO_REQ_INSIDE_ZPSDS (0x01000000)
  1455. #define MPI2_SAS_PHYINFO_ZONE_GROUP_PERSISTENT (0x00400000)
  1456. #define MPI2_SAS_PHYINFO_INSIDE_ZPSDS (0x00200000)
  1457. #define MPI2_SAS_PHYINFO_ZONING_ENABLED (0x00100000)
  1458. #define MPI2_SAS_PHYINFO_REASON_MASK (0x000F0000)
  1459. #define MPI2_SAS_PHYINFO_REASON_UNKNOWN (0x00000000)
  1460. #define MPI2_SAS_PHYINFO_REASON_POWER_ON (0x00010000)
  1461. #define MPI2_SAS_PHYINFO_REASON_HARD_RESET (0x00020000)
  1462. #define MPI2_SAS_PHYINFO_REASON_SMP_PHY_CONTROL (0x00030000)
  1463. #define MPI2_SAS_PHYINFO_REASON_LOSS_OF_SYNC (0x00040000)
  1464. #define MPI2_SAS_PHYINFO_REASON_MULTIPLEXING_SEQ (0x00050000)
  1465. #define MPI2_SAS_PHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00060000)
  1466. #define MPI2_SAS_PHYINFO_REASON_BREAK_TIMEOUT (0x00070000)
  1467. #define MPI2_SAS_PHYINFO_REASON_PHY_TEST_STOPPED (0x00080000)
  1468. #define MPI2_SAS_PHYINFO_MULTIPLEXING_SUPPORTED (0x00008000)
  1469. #define MPI2_SAS_PHYINFO_SATA_PORT_ACTIVE (0x00004000)
  1470. #define MPI2_SAS_PHYINFO_SATA_PORT_SELECTOR_PRESENT (0x00002000)
  1471. #define MPI2_SAS_PHYINFO_VIRTUAL_PHY (0x00001000)
  1472. #define MPI2_SAS_PHYINFO_MASK_PARTIAL_PATHWAY_TIME (0x00000F00)
  1473. #define MPI2_SAS_PHYINFO_SHIFT_PARTIAL_PATHWAY_TIME (8)
  1474. #define MPI2_SAS_PHYINFO_MASK_ROUTING_ATTRIBUTE (0x000000F0)
  1475. #define MPI2_SAS_PHYINFO_DIRECT_ROUTING (0x00000000)
  1476. #define MPI2_SAS_PHYINFO_SUBTRACTIVE_ROUTING (0x00000010)
  1477. #define MPI2_SAS_PHYINFO_TABLE_ROUTING (0x00000020)
  1478. /* values for SAS ProgrammedLinkRate fields */
  1479. #define MPI2_SAS_PRATE_MAX_RATE_MASK (0xF0)
  1480. #define MPI2_SAS_PRATE_MAX_RATE_NOT_PROGRAMMABLE (0x00)
  1481. #define MPI2_SAS_PRATE_MAX_RATE_1_5 (0x80)
  1482. #define MPI2_SAS_PRATE_MAX_RATE_3_0 (0x90)
  1483. #define MPI2_SAS_PRATE_MAX_RATE_6_0 (0xA0)
  1484. #define MPI2_SAS_PRATE_MIN_RATE_MASK (0x0F)
  1485. #define MPI2_SAS_PRATE_MIN_RATE_NOT_PROGRAMMABLE (0x00)
  1486. #define MPI2_SAS_PRATE_MIN_RATE_1_5 (0x08)
  1487. #define MPI2_SAS_PRATE_MIN_RATE_3_0 (0x09)
  1488. #define MPI2_SAS_PRATE_MIN_RATE_6_0 (0x0A)
  1489. /* values for SAS HwLinkRate fields */
  1490. #define MPI2_SAS_HWRATE_MAX_RATE_MASK (0xF0)
  1491. #define MPI2_SAS_HWRATE_MAX_RATE_1_5 (0x80)
  1492. #define MPI2_SAS_HWRATE_MAX_RATE_3_0 (0x90)
  1493. #define MPI2_SAS_HWRATE_MAX_RATE_6_0 (0xA0)
  1494. #define MPI2_SAS_HWRATE_MIN_RATE_MASK (0x0F)
  1495. #define MPI2_SAS_HWRATE_MIN_RATE_1_5 (0x08)
  1496. #define MPI2_SAS_HWRATE_MIN_RATE_3_0 (0x09)
  1497. #define MPI2_SAS_HWRATE_MIN_RATE_6_0 (0x0A)
  1498. /****************************************************************************
  1499. * SAS IO Unit Config Pages
  1500. ****************************************************************************/
  1501. /* SAS IO Unit Page 0 */
  1502. typedef struct _MPI2_SAS_IO_UNIT0_PHY_DATA
  1503. {
  1504. U8 Port; /* 0x00 */
  1505. U8 PortFlags; /* 0x01 */
  1506. U8 PhyFlags; /* 0x02 */
  1507. U8 NegotiatedLinkRate; /* 0x03 */
  1508. U32 ControllerPhyDeviceInfo;/* 0x04 */
  1509. U16 AttachedDevHandle; /* 0x08 */
  1510. U16 ControllerDevHandle; /* 0x0A */
  1511. U32 DiscoveryStatus; /* 0x0C */
  1512. U32 Reserved; /* 0x10 */
  1513. } MPI2_SAS_IO_UNIT0_PHY_DATA, MPI2_POINTER PTR_MPI2_SAS_IO_UNIT0_PHY_DATA,
  1514. Mpi2SasIOUnit0PhyData_t, MPI2_POINTER pMpi2SasIOUnit0PhyData_t;
  1515. /*
  1516. * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
  1517. * one and check the value returned for NumPhys at runtime.
  1518. */
  1519. #ifndef MPI2_SAS_IOUNIT0_PHY_MAX
  1520. #define MPI2_SAS_IOUNIT0_PHY_MAX (1)
  1521. #endif
  1522. typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_0
  1523. {
  1524. MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
  1525. U32 Reserved1; /* 0x08 */
  1526. U8 NumPhys; /* 0x0C */
  1527. U8 Reserved2; /* 0x0D */
  1528. U16 Reserved3; /* 0x0E */
  1529. MPI2_SAS_IO_UNIT0_PHY_DATA PhyData[MPI2_SAS_IOUNIT0_PHY_MAX]; /* 0x10 */
  1530. } MPI2_CONFIG_PAGE_SASIOUNIT_0,
  1531. MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_0,
  1532. Mpi2SasIOUnitPage0_t, MPI2_POINTER pMpi2SasIOUnitPage0_t;
  1533. #define MPI2_SASIOUNITPAGE0_PAGEVERSION (0x05)
  1534. /* values for SAS IO Unit Page 0 PortFlags */
  1535. #define MPI2_SASIOUNIT0_PORTFLAGS_DISCOVERY_IN_PROGRESS (0x08)
  1536. #define MPI2_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG (0x01)
  1537. /* values for SAS IO Unit Page 0 PhyFlags */
  1538. #define MPI2_SASIOUNIT0_PHYFLAGS_ZONING_ENABLED (0x10)
  1539. #define MPI2_SASIOUNIT0_PHYFLAGS_PHY_DISABLED (0x08)
  1540. /* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
  1541. /* see mpi2_sas.h for values for SAS IO Unit Page 0 ControllerPhyDeviceInfo values */
  1542. /* values for SAS IO Unit Page 0 DiscoveryStatus */
  1543. #define MPI2_SASIOUNIT0_DS_MAX_ENCLOSURES_EXCEED (0x80000000)
  1544. #define MPI2_SASIOUNIT0_DS_MAX_EXPANDERS_EXCEED (0x40000000)
  1545. #define MPI2_SASIOUNIT0_DS_MAX_DEVICES_EXCEED (0x20000000)
  1546. #define MPI2_SASIOUNIT0_DS_MAX_TOPO_PHYS_EXCEED (0x10000000)
  1547. #define MPI2_SASIOUNIT0_DS_DOWNSTREAM_INITIATOR (0x08000000)
  1548. #define MPI2_SASIOUNIT0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000)
  1549. #define MPI2_SASIOUNIT0_DS_EXP_MULTI_SUBTRACTIVE (0x00004000)
  1550. #define MPI2_SASIOUNIT0_DS_MULTI_PORT_DOMAIN (0x00002000)
  1551. #define MPI2_SASIOUNIT0_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000)
  1552. #define MPI2_SASIOUNIT0_DS_UNSUPPORTED_DEVICE (0x00000800)
  1553. #define MPI2_SASIOUNIT0_DS_TABLE_LINK (0x00000400)
  1554. #define MPI2_SASIOUNIT0_DS_SUBTRACTIVE_LINK (0x00000200)
  1555. #define MPI2_SASIOUNIT0_DS_SMP_CRC_ERROR (0x00000100)
  1556. #define MPI2_SASIOUNIT0_DS_SMP_FUNCTION_FAILED (0x00000080)
  1557. #define MPI2_SASIOUNIT0_DS_INDEX_NOT_EXIST (0x00000040)
  1558. #define MPI2_SASIOUNIT0_DS_OUT_ROUTE_ENTRIES (0x00000020)
  1559. #define MPI2_SASIOUNIT0_DS_SMP_TIMEOUT (0x00000010)
  1560. #define MPI2_SASIOUNIT0_DS_MULTIPLE_PORTS (0x00000004)
  1561. #define MPI2_SASIOUNIT0_DS_UNADDRESSABLE_DEVICE (0x00000002)
  1562. #define MPI2_SASIOUNIT0_DS_LOOP_DETECTED (0x00000001)
  1563. /* SAS IO Unit Page 1 */
  1564. typedef struct _MPI2_SAS_IO_UNIT1_PHY_DATA
  1565. {
  1566. U8 Port; /* 0x00 */
  1567. U8 PortFlags; /* 0x01 */
  1568. U8 PhyFlags; /* 0x02 */
  1569. U8 MaxMinLinkRate; /* 0x03 */
  1570. U32 ControllerPhyDeviceInfo; /* 0x04 */
  1571. U16 MaxTargetPortConnectTime; /* 0x08 */
  1572. U16 Reserved1; /* 0x0A */
  1573. } MPI2_SAS_IO_UNIT1_PHY_DATA, MPI2_POINTER PTR_MPI2_SAS_IO_UNIT1_PHY_DATA,
  1574. Mpi2SasIOUnit1PhyData_t, MPI2_POINTER pMpi2SasIOUnit1PhyData_t;
  1575. /*
  1576. * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
  1577. * one and check the value returned for NumPhys at runtime.
  1578. */
  1579. #ifndef MPI2_SAS_IOUNIT1_PHY_MAX
  1580. #define MPI2_SAS_IOUNIT1_PHY_MAX (1)
  1581. #endif
  1582. typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_1
  1583. {
  1584. MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
  1585. U16 ControlFlags; /* 0x08 */
  1586. U16 SASNarrowMaxQueueDepth; /* 0x0A */
  1587. U16 AdditionalControlFlags; /* 0x0C */
  1588. U16 SASWideMaxQueueDepth; /* 0x0E */
  1589. U8 NumPhys; /* 0x10 */
  1590. U8 SATAMaxQDepth; /* 0x11 */
  1591. U8 ReportDeviceMissingDelay; /* 0x12 */
  1592. U8 IODeviceMissingDelay; /* 0x13 */
  1593. MPI2_SAS_IO_UNIT1_PHY_DATA PhyData[MPI2_SAS_IOUNIT1_PHY_MAX]; /* 0x14 */
  1594. } MPI2_CONFIG_PAGE_SASIOUNIT_1,
  1595. MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_1,
  1596. Mpi2SasIOUnitPage1_t, MPI2_POINTER pMpi2SasIOUnitPage1_t;
  1597. #define MPI2_SASIOUNITPAGE1_PAGEVERSION (0x09)
  1598. /* values for SAS IO Unit Page 1 ControlFlags */
  1599. #define MPI2_SASIOUNIT1_CONTROL_DEVICE_SELF_TEST (0x8000)
  1600. #define MPI2_SASIOUNIT1_CONTROL_SATA_3_0_MAX (0x4000)
  1601. #define MPI2_SASIOUNIT1_CONTROL_SATA_1_5_MAX (0x2000)
  1602. #define MPI2_SASIOUNIT1_CONTROL_SATA_SW_PRESERVE (0x1000)
  1603. #define MPI2_SASIOUNIT1_CONTROL_MASK_DEV_SUPPORT (0x0600)
  1604. #define MPI2_SASIOUNIT1_CONTROL_SHIFT_DEV_SUPPORT (9)
  1605. #define MPI2_SASIOUNIT1_CONTROL_DEV_SUPPORT_BOTH (0x0)
  1606. #define MPI2_SASIOUNIT1_CONTROL_DEV_SAS_SUPPORT (0x1)
  1607. #define MPI2_SASIOUNIT1_CONTROL_DEV_SATA_SUPPORT (0x2)
  1608. #define MPI2_SASIOUNIT1_CONTROL_SATA_48BIT_LBA_REQUIRED (0x0080)
  1609. #define MPI2_SASIOUNIT1_CONTROL_SATA_SMART_REQUIRED (0x0040)
  1610. #define MPI2_SASIOUNIT1_CONTROL_SATA_NCQ_REQUIRED (0x0020)
  1611. #define MPI2_SASIOUNIT1_CONTROL_SATA_FUA_REQUIRED (0x0010)
  1612. #define MPI2_SASIOUNIT1_CONTROL_TABLE_SUBTRACTIVE_ILLEGAL (0x0008)
  1613. #define MPI2_SASIOUNIT1_CONTROL_SUBTRACTIVE_ILLEGAL (0x0004)
  1614. #define MPI2_SASIOUNIT1_CONTROL_FIRST_LVL_DISC_ONLY (0x0002)
  1615. #define MPI2_SASIOUNIT1_CONTROL_CLEAR_AFFILIATION (0x0001)
  1616. /* values for SAS IO Unit Page 1 AdditionalControlFlags */
  1617. #define MPI2_SASIOUNIT1_ACONTROL_MULTI_PORT_DOMAIN_ILLEGAL (0x0080)
  1618. #define MPI2_SASIOUNIT1_ACONTROL_SATA_ASYNCHROUNOUS_NOTIFICATION (0x0040)
  1619. #define MPI2_SASIOUNIT1_ACONTROL_INVALID_TOPOLOGY_CORRECTION (0x0020)
  1620. #define MPI2_SASIOUNIT1_ACONTROL_PORT_ENABLE_ONLY_SATA_LINK_RESET (0x0010)
  1621. #define MPI2_SASIOUNIT1_ACONTROL_OTHER_AFFILIATION_SATA_LINK_RESET (0x0008)
  1622. #define MPI2_SASIOUNIT1_ACONTROL_SELF_AFFILIATION_SATA_LINK_RESET (0x0004)
  1623. #define MPI2_SASIOUNIT1_ACONTROL_NO_AFFILIATION_SATA_LINK_RESET (0x0002)
  1624. #define MPI2_SASIOUNIT1_ACONTROL_ALLOW_TABLE_TO_TABLE (0x0001)
  1625. /* defines for SAS IO Unit Page 1 ReportDeviceMissingDelay */
  1626. #define MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK (0x7F)
  1627. #define MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16 (0x80)
  1628. /* values for SAS IO Unit Page 1 PortFlags */
  1629. #define MPI2_SASIOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG (0x01)
  1630. /* values for SAS IO Unit Page 1 PhyFlags */
  1631. #define MPI2_SASIOUNIT1_PHYFLAGS_ZONING_ENABLE (0x10)
  1632. #define MPI2_SASIOUNIT1_PHYFLAGS_PHY_DISABLE (0x08)
  1633. /* values for SAS IO Unit Page 1 MaxMinLinkRate */
  1634. #define MPI2_SASIOUNIT1_MAX_RATE_MASK (0xF0)
  1635. #define MPI2_SASIOUNIT1_MAX_RATE_1_5 (0x80)
  1636. #define MPI2_SASIOUNIT1_MAX_RATE_3_0 (0x90)
  1637. #define MPI2_SASIOUNIT1_MAX_RATE_6_0 (0xA0)
  1638. #define MPI2_SASIOUNIT1_MIN_RATE_MASK (0x0F)
  1639. #define MPI2_SASIOUNIT1_MIN_RATE_1_5 (0x08)
  1640. #define MPI2_SASIOUNIT1_MIN_RATE_3_0 (0x09)
  1641. #define MPI2_SASIOUNIT1_MIN_RATE_6_0 (0x0A)
  1642. /* see mpi2_sas.h for values for SAS IO Unit Page 1 ControllerPhyDeviceInfo values */
  1643. /* SAS IO Unit Page 4 */
  1644. typedef struct _MPI2_SAS_IOUNIT4_SPINUP_GROUP
  1645. {
  1646. U8 MaxTargetSpinup; /* 0x00 */
  1647. U8 SpinupDelay; /* 0x01 */
  1648. U8 SpinupFlags; /* 0x02 */
  1649. U8 Reserved1; /* 0x03 */
  1650. } MPI2_SAS_IOUNIT4_SPINUP_GROUP, MPI2_POINTER PTR_MPI2_SAS_IOUNIT4_SPINUP_GROUP,
  1651. Mpi2SasIOUnit4SpinupGroup_t, MPI2_POINTER pMpi2SasIOUnit4SpinupGroup_t;
  1652. /* defines for SAS IO Unit Page 4 SpinupFlags */
  1653. #define MPI2_SASIOUNIT4_SPINUP_DISABLE_FLAG (0x01)
  1654. /*
  1655. * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
  1656. * one and check the value returned for NumPhys at runtime.
  1657. */
  1658. #ifndef MPI2_SAS_IOUNIT4_PHY_MAX
  1659. #define MPI2_SAS_IOUNIT4_PHY_MAX (4)
  1660. #endif
  1661. typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_4
  1662. {
  1663. MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
  1664. MPI2_SAS_IOUNIT4_SPINUP_GROUP SpinupGroupParameters[4]; /* 0x08 */
  1665. U32 Reserved1; /* 0x18 */
  1666. U32 Reserved2; /* 0x1C */
  1667. U32 Reserved3; /* 0x20 */
  1668. U8 BootDeviceWaitTime; /* 0x24 */
  1669. U8 Reserved4; /* 0x25 */
  1670. U16 Reserved5; /* 0x26 */
  1671. U8 NumPhys; /* 0x28 */
  1672. U8 PEInitialSpinupDelay; /* 0x29 */
  1673. U8 PEReplyDelay; /* 0x2A */
  1674. U8 Flags; /* 0x2B */
  1675. U8 PHY[MPI2_SAS_IOUNIT4_PHY_MAX]; /* 0x2C */
  1676. } MPI2_CONFIG_PAGE_SASIOUNIT_4,
  1677. MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_4,
  1678. Mpi2SasIOUnitPage4_t, MPI2_POINTER pMpi2SasIOUnitPage4_t;
  1679. #define MPI2_SASIOUNITPAGE4_PAGEVERSION (0x02)
  1680. /* defines for Flags field */
  1681. #define MPI2_SASIOUNIT4_FLAGS_AUTO_PORTENABLE (0x01)
  1682. /* defines for PHY field */
  1683. #define MPI2_SASIOUNIT4_PHY_SPINUP_GROUP_MASK (0x03)
  1684. /* SAS IO Unit Page 5 */
  1685. typedef struct _MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS {
  1686. U8 ControlFlags; /* 0x00 */
  1687. U8 PortWidthModGroup; /* 0x01 */
  1688. U16 InactivityTimerExponent; /* 0x02 */
  1689. U8 SATAPartialTimeout; /* 0x04 */
  1690. U8 Reserved2; /* 0x05 */
  1691. U8 SATASlumberTimeout; /* 0x06 */
  1692. U8 Reserved3; /* 0x07 */
  1693. U8 SASPartialTimeout; /* 0x08 */
  1694. U8 Reserved4; /* 0x09 */
  1695. U8 SASSlumberTimeout; /* 0x0A */
  1696. U8 Reserved5; /* 0x0B */
  1697. } MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS,
  1698. MPI2_POINTER PTR_MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS,
  1699. Mpi2SasIOUnit5PhyPmSettings_t, MPI2_POINTER pMpi2SasIOUnit5PhyPmSettings_t;
  1700. /* defines for ControlFlags field */
  1701. #define MPI2_SASIOUNIT5_CONTROL_SAS_SLUMBER_ENABLE (0x08)
  1702. #define MPI2_SASIOUNIT5_CONTROL_SAS_PARTIAL_ENABLE (0x04)
  1703. #define MPI2_SASIOUNIT5_CONTROL_SATA_SLUMBER_ENABLE (0x02)
  1704. #define MPI2_SASIOUNIT5_CONTROL_SATA_PARTIAL_ENABLE (0x01)
  1705. /* defines for PortWidthModeGroup field */
  1706. #define MPI2_SASIOUNIT5_PWMG_DISABLE (0xFF)
  1707. /* defines for InactivityTimerExponent field */
  1708. #define MPI2_SASIOUNIT5_ITE_MASK_SAS_SLUMBER (0x7000)
  1709. #define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_SLUMBER (12)
  1710. #define MPI2_SASIOUNIT5_ITE_MASK_SAS_PARTIAL (0x0700)
  1711. #define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_PARTIAL (8)
  1712. #define MPI2_SASIOUNIT5_ITE_MASK_SATA_SLUMBER (0x0070)
  1713. #define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_SLUMBER (4)
  1714. #define MPI2_SASIOUNIT5_ITE_MASK_SATA_PARTIAL (0x0007)
  1715. #define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_PARTIAL (0)
  1716. #define MPI2_SASIOUNIT5_ITE_TEN_SECONDS (7)
  1717. #define MPI2_SASIOUNIT5_ITE_ONE_SECOND (6)
  1718. #define MPI2_SASIOUNIT5_ITE_HUNDRED_MILLISECONDS (5)
  1719. #define MPI2_SASIOUNIT5_ITE_TEN_MILLISECONDS (4)
  1720. #define MPI2_SASIOUNIT5_ITE_ONE_MILLISECOND (3)
  1721. #define MPI2_SASIOUNIT5_ITE_HUNDRED_MICROSECONDS (2)
  1722. #define MPI2_SASIOUNIT5_ITE_TEN_MICROSECONDS (1)
  1723. #define MPI2_SASIOUNIT5_ITE_ONE_MICROSECOND (0)
  1724. /*
  1725. * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
  1726. * one and check the value returned for NumPhys at runtime.
  1727. */
  1728. #ifndef MPI2_SAS_IOUNIT5_PHY_MAX
  1729. #define MPI2_SAS_IOUNIT5_PHY_MAX (1)
  1730. #endif
  1731. typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_5 {
  1732. MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
  1733. U8 NumPhys; /* 0x08 */
  1734. U8 Reserved1; /* 0x09 */
  1735. U16 Reserved2; /* 0x0A */
  1736. U32 Reserved3; /* 0x0C */
  1737. MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS SASPhyPowerManagementSettings
  1738. [MPI2_SAS_IOUNIT5_PHY_MAX]; /* 0x10 */
  1739. } MPI2_CONFIG_PAGE_SASIOUNIT_5,
  1740. MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_5,
  1741. Mpi2SasIOUnitPage5_t, MPI2_POINTER pMpi2SasIOUnitPage5_t;
  1742. #define MPI2_SASIOUNITPAGE5_PAGEVERSION (0x01)
  1743. /* SAS IO Unit Page 6 */
  1744. typedef struct _MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS {
  1745. U8 CurrentStatus; /* 0x00 */
  1746. U8 CurrentModulation; /* 0x01 */
  1747. U8 CurrentUtilization; /* 0x02 */
  1748. U8 Reserved1; /* 0x03 */
  1749. U32 Reserved2; /* 0x04 */
  1750. } MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS,
  1751. MPI2_POINTER PTR_MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS,
  1752. Mpi2SasIOUnit6PortWidthModGroupStatus_t,
  1753. MPI2_POINTER pMpi2SasIOUnit6PortWidthModGroupStatus_t;
  1754. /* defines for CurrentStatus field */
  1755. #define MPI2_SASIOUNIT6_STATUS_UNAVAILABLE (0x00)
  1756. #define MPI2_SASIOUNIT6_STATUS_UNCONFIGURED (0x01)
  1757. #define MPI2_SASIOUNIT6_STATUS_INVALID_CONFIG (0x02)
  1758. #define MPI2_SASIOUNIT6_STATUS_LINK_DOWN (0x03)
  1759. #define MPI2_SASIOUNIT6_STATUS_OBSERVATION_ONLY (0x04)
  1760. #define MPI2_SASIOUNIT6_STATUS_INACTIVE (0x05)
  1761. #define MPI2_SASIOUNIT6_STATUS_ACTIVE_IOUNIT (0x06)
  1762. #define MPI2_SASIOUNIT6_STATUS_ACTIVE_HOST (0x07)
  1763. /* defines for CurrentModulation field */
  1764. #define MPI2_SASIOUNIT6_MODULATION_25_PERCENT (0x00)
  1765. #define MPI2_SASIOUNIT6_MODULATION_50_PERCENT (0x01)
  1766. #define MPI2_SASIOUNIT6_MODULATION_75_PERCENT (0x02)
  1767. #define MPI2_SASIOUNIT6_MODULATION_100_PERCENT (0x03)
  1768. /*
  1769. * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
  1770. * one and check the value returned for NumGroups at runtime.
  1771. */
  1772. #ifndef MPI2_SAS_IOUNIT6_GROUP_MAX
  1773. #define MPI2_SAS_IOUNIT6_GROUP_MAX (1)
  1774. #endif
  1775. typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_6 {
  1776. MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
  1777. U32 Reserved1; /* 0x08 */
  1778. U32 Reserved2; /* 0x0C */
  1779. U8 NumGroups; /* 0x10 */
  1780. U8 Reserved3; /* 0x11 */
  1781. U16 Reserved4; /* 0x12 */
  1782. MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS
  1783. PortWidthModulationGroupStatus[MPI2_SAS_IOUNIT6_GROUP_MAX]; /* 0x14 */
  1784. } MPI2_CONFIG_PAGE_SASIOUNIT_6,
  1785. MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_6,
  1786. Mpi2SasIOUnitPage6_t, MPI2_POINTER pMpi2SasIOUnitPage6_t;
  1787. #define MPI2_SASIOUNITPAGE6_PAGEVERSION (0x00)
  1788. /* SAS IO Unit Page 7 */
  1789. typedef struct _MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS {
  1790. U8 Flags; /* 0x00 */
  1791. U8 Reserved1; /* 0x01 */
  1792. U16 Reserved2; /* 0x02 */
  1793. U8 Threshold75Pct; /* 0x04 */
  1794. U8 Threshold50Pct; /* 0x05 */
  1795. U8 Threshold25Pct; /* 0x06 */
  1796. U8 Reserved3; /* 0x07 */
  1797. } MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS,
  1798. MPI2_POINTER PTR_MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS,
  1799. Mpi2SasIOUnit7PortWidthModGroupSettings_t,
  1800. MPI2_POINTER pMpi2SasIOUnit7PortWidthModGroupSettings_t;
  1801. /* defines for Flags field */
  1802. #define MPI2_SASIOUNIT7_FLAGS_ENABLE_PORT_WIDTH_MODULATION (0x01)
  1803. /*
  1804. * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
  1805. * one and check the value returned for NumGroups at runtime.
  1806. */
  1807. #ifndef MPI2_SAS_IOUNIT7_GROUP_MAX
  1808. #define MPI2_SAS_IOUNIT7_GROUP_MAX (1)
  1809. #endif
  1810. typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_7 {
  1811. MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
  1812. U8 SamplingInterval; /* 0x08 */
  1813. U8 WindowLength; /* 0x09 */
  1814. U16 Reserved1; /* 0x0A */
  1815. U32 Reserved2; /* 0x0C */
  1816. U32 Reserved3; /* 0x10 */
  1817. U8 NumGroups; /* 0x14 */
  1818. U8 Reserved4; /* 0x15 */
  1819. U16 Reserved5; /* 0x16 */
  1820. MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS
  1821. PortWidthModulationGroupSettings[MPI2_SAS_IOUNIT7_GROUP_MAX]; /* 0x18 */
  1822. } MPI2_CONFIG_PAGE_SASIOUNIT_7,
  1823. MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_7,
  1824. Mpi2SasIOUnitPage7_t, MPI2_POINTER pMpi2SasIOUnitPage7_t;
  1825. #define MPI2_SASIOUNITPAGE7_PAGEVERSION (0x00)
  1826. /* SAS IO Unit Page 8 */
  1827. typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_8 {
  1828. MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
  1829. U32 Reserved1; /* 0x08 */
  1830. U32 PowerManagementCapabilities;/* 0x0C */
  1831. U32 Reserved2; /* 0x10 */
  1832. } MPI2_CONFIG_PAGE_SASIOUNIT_8,
  1833. MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_8,
  1834. Mpi2SasIOUnitPage8_t, MPI2_POINTER pMpi2SasIOUnitPage8_t;
  1835. #define MPI2_SASIOUNITPAGE8_PAGEVERSION (0x00)
  1836. /* defines for PowerManagementCapabilities field */
  1837. #define MPI2_SASIOUNIT8_PM_HOST_PORT_WIDTH_MOD (0x00001000)
  1838. #define MPI2_SASIOUNIT8_PM_HOST_SAS_SLUMBER_MODE (0x00000800)
  1839. #define MPI2_SASIOUNIT8_PM_HOST_SAS_PARTIAL_MODE (0x00000400)
  1840. #define MPI2_SASIOUNIT8_PM_HOST_SATA_SLUMBER_MODE (0x00000200)
  1841. #define MPI2_SASIOUNIT8_PM_HOST_SATA_PARTIAL_MODE (0x00000100)
  1842. #define MPI2_SASIOUNIT8_PM_IOUNIT_PORT_WIDTH_MOD (0x00000010)
  1843. #define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_SLUMBER_MODE (0x00000008)
  1844. #define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_PARTIAL_MODE (0x00000004)
  1845. #define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_SLUMBER_MODE (0x00000002)
  1846. #define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_PARTIAL_MODE (0x00000001)
  1847. /****************************************************************************
  1848. * SAS Expander Config Pages
  1849. ****************************************************************************/
  1850. /* SAS Expander Page 0 */
  1851. typedef struct _MPI2_CONFIG_PAGE_EXPANDER_0
  1852. {
  1853. MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
  1854. U8 PhysicalPort; /* 0x08 */
  1855. U8 ReportGenLength; /* 0x09 */
  1856. U16 EnclosureHandle; /* 0x0A */
  1857. U64 SASAddress; /* 0x0C */
  1858. U32 DiscoveryStatus; /* 0x14 */
  1859. U16 DevHandle; /* 0x18 */
  1860. U16 ParentDevHandle; /* 0x1A */
  1861. U16 ExpanderChangeCount; /* 0x1C */
  1862. U16 ExpanderRouteIndexes; /* 0x1E */
  1863. U8 NumPhys; /* 0x20 */
  1864. U8 SASLevel; /* 0x21 */
  1865. U16 Flags; /* 0x22 */
  1866. U16 STPBusInactivityTimeLimit; /* 0x24 */
  1867. U16 STPMaxConnectTimeLimit; /* 0x26 */
  1868. U16 STP_SMP_NexusLossTime; /* 0x28 */
  1869. U16 MaxNumRoutedSasAddresses; /* 0x2A */
  1870. U64 ActiveZoneManagerSASAddress;/* 0x2C */
  1871. U16 ZoneLockInactivityLimit; /* 0x34 */
  1872. U16 Reserved1; /* 0x36 */
  1873. U8 TimeToReducedFunc; /* 0x38 */
  1874. U8 InitialTimeToReducedFunc; /* 0x39 */
  1875. U8 MaxReducedFuncTime; /* 0x3A */
  1876. U8 Reserved2; /* 0x3B */
  1877. } MPI2_CONFIG_PAGE_EXPANDER_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXPANDER_0,
  1878. Mpi2ExpanderPage0_t, MPI2_POINTER pMpi2ExpanderPage0_t;
  1879. #define MPI2_SASEXPANDER0_PAGEVERSION (0x06)
  1880. /* values for SAS Expander Page 0 DiscoveryStatus field */
  1881. #define MPI2_SAS_EXPANDER0_DS_MAX_ENCLOSURES_EXCEED (0x80000000)
  1882. #define MPI2_SAS_EXPANDER0_DS_MAX_EXPANDERS_EXCEED (0x40000000)
  1883. #define MPI2_SAS_EXPANDER0_DS_MAX_DEVICES_EXCEED (0x20000000)
  1884. #define MPI2_SAS_EXPANDER0_DS_MAX_TOPO_PHYS_EXCEED (0x10000000)
  1885. #define MPI2_SAS_EXPANDER0_DS_DOWNSTREAM_INITIATOR (0x08000000)
  1886. #define MPI2_SAS_EXPANDER0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000)
  1887. #define MPI2_SAS_EXPANDER0_DS_EXP_MULTI_SUBTRACTIVE (0x00004000)
  1888. #define MPI2_SAS_EXPANDER0_DS_MULTI_PORT_DOMAIN (0x00002000)
  1889. #define MPI2_SAS_EXPANDER0_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000)
  1890. #define MPI2_SAS_EXPANDER0_DS_UNSUPPORTED_DEVICE (0x00000800)
  1891. #define MPI2_SAS_EXPANDER0_DS_TABLE_LINK (0x00000400)
  1892. #define MPI2_SAS_EXPANDER0_DS_SUBTRACTIVE_LINK (0x00000200)
  1893. #define MPI2_SAS_EXPANDER0_DS_SMP_CRC_ERROR (0x00000100)
  1894. #define MPI2_SAS_EXPANDER0_DS_SMP_FUNCTION_FAILED (0x00000080)
  1895. #define MPI2_SAS_EXPANDER0_DS_INDEX_NOT_EXIST (0x00000040)
  1896. #define MPI2_SAS_EXPANDER0_DS_OUT_ROUTE_ENTRIES (0x00000020)
  1897. #define MPI2_SAS_EXPANDER0_DS_SMP_TIMEOUT (0x00000010)
  1898. #define MPI2_SAS_EXPANDER0_DS_MULTIPLE_PORTS (0x00000004)
  1899. #define MPI2_SAS_EXPANDER0_DS_UNADDRESSABLE_DEVICE (0x00000002)
  1900. #define MPI2_SAS_EXPANDER0_DS_LOOP_DETECTED (0x00000001)
  1901. /* values for SAS Expander Page 0 Flags field */
  1902. #define MPI2_SAS_EXPANDER0_FLAGS_REDUCED_FUNCTIONALITY (0x2000)
  1903. #define MPI2_SAS_EXPANDER0_FLAGS_ZONE_LOCKED (0x1000)
  1904. #define MPI2_SAS_EXPANDER0_FLAGS_SUPPORTED_PHYSICAL_PRES (0x0800)
  1905. #define MPI2_SAS_EXPANDER0_FLAGS_ASSERTED_PHYSICAL_PRES (0x0400)
  1906. #define MPI2_SAS_EXPANDER0_FLAGS_ZONING_SUPPORT (0x0200)
  1907. #define MPI2_SAS_EXPANDER0_FLAGS_ENABLED_ZONING (0x0100)
  1908. #define MPI2_SAS_EXPANDER0_FLAGS_TABLE_TO_TABLE_SUPPORT (0x0080)
  1909. #define MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE (0x0010)
  1910. #define MPI2_SAS_EXPANDER0_FLAGS_OTHERS_CONFIG (0x0004)
  1911. #define MPI2_SAS_EXPANDER0_FLAGS_CONFIG_IN_PROGRESS (0x0002)
  1912. #define MPI2_SAS_EXPANDER0_FLAGS_ROUTE_TABLE_CONFIG (0x0001)
  1913. /* SAS Expander Page 1 */
  1914. typedef struct _MPI2_CONFIG_PAGE_EXPANDER_1
  1915. {
  1916. MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
  1917. U8 PhysicalPort; /* 0x08 */
  1918. U8 Reserved1; /* 0x09 */
  1919. U16 Reserved2; /* 0x0A */
  1920. U8 NumPhys; /* 0x0C */
  1921. U8 Phy; /* 0x0D */
  1922. U16 NumTableEntriesProgrammed; /* 0x0E */
  1923. U8 ProgrammedLinkRate; /* 0x10 */
  1924. U8 HwLinkRate; /* 0x11 */
  1925. U16 AttachedDevHandle; /* 0x12 */
  1926. U32 PhyInfo; /* 0x14 */
  1927. U32 AttachedDeviceInfo; /* 0x18 */
  1928. U16 ExpanderDevHandle; /* 0x1C */
  1929. U8 ChangeCount; /* 0x1E */
  1930. U8 NegotiatedLinkRate; /* 0x1F */
  1931. U8 PhyIdentifier; /* 0x20 */
  1932. U8 AttachedPhyIdentifier; /* 0x21 */
  1933. U8 Reserved3; /* 0x22 */
  1934. U8 DiscoveryInfo; /* 0x23 */
  1935. U32 AttachedPhyInfo; /* 0x24 */
  1936. U8 ZoneGroup; /* 0x28 */
  1937. U8 SelfConfigStatus; /* 0x29 */
  1938. U16 Reserved4; /* 0x2A */
  1939. } MPI2_CONFIG_PAGE_EXPANDER_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXPANDER_1,
  1940. Mpi2ExpanderPage1_t, MPI2_POINTER pMpi2ExpanderPage1_t;
  1941. #define MPI2_SASEXPANDER1_PAGEVERSION (0x02)
  1942. /* use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */
  1943. /* use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */
  1944. /* use MPI2_SAS_PHYINFO_ for the PhyInfo field */
  1945. /* see mpi2_sas.h for the MPI2_SAS_DEVICE_INFO_ defines used for the AttachedDeviceInfo field */
  1946. /* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
  1947. /* values for SAS Expander Page 1 DiscoveryInfo field */
  1948. #define MPI2_SAS_EXPANDER1_DISCINFO_BAD_PHY_DISABLED (0x04)
  1949. #define MPI2_SAS_EXPANDER1_DISCINFO_LINK_STATUS_CHANGE (0x02)
  1950. #define MPI2_SAS_EXPANDER1_DISCINFO_NO_ROUTING_ENTRIES (0x01)
  1951. /* use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */
  1952. /****************************************************************************
  1953. * SAS Device Config Pages
  1954. ****************************************************************************/
  1955. /* SAS Device Page 0 */
  1956. typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_0
  1957. {
  1958. MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
  1959. U16 Slot; /* 0x08 */
  1960. U16 EnclosureHandle; /* 0x0A */
  1961. U64 SASAddress; /* 0x0C */
  1962. U16 ParentDevHandle; /* 0x14 */
  1963. U8 PhyNum; /* 0x16 */
  1964. U8 AccessStatus; /* 0x17 */
  1965. U16 DevHandle; /* 0x18 */
  1966. U8 AttachedPhyIdentifier; /* 0x1A */
  1967. U8 ZoneGroup; /* 0x1B */
  1968. U32 DeviceInfo; /* 0x1C */
  1969. U16 Flags; /* 0x20 */
  1970. U8 PhysicalPort; /* 0x22 */
  1971. U8 MaxPortConnections; /* 0x23 */
  1972. U64 DeviceName; /* 0x24 */
  1973. U8 PortGroups; /* 0x2C */
  1974. U8 DmaGroup; /* 0x2D */
  1975. U8 ControlGroup; /* 0x2E */
  1976. U8 Reserved1; /* 0x2F */
  1977. U32 Reserved2; /* 0x30 */
  1978. U32 Reserved3; /* 0x34 */
  1979. } MPI2_CONFIG_PAGE_SAS_DEV_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_DEV_0,
  1980. Mpi2SasDevicePage0_t, MPI2_POINTER pMpi2SasDevicePage0_t;
  1981. #define MPI2_SASDEVICE0_PAGEVERSION (0x08)
  1982. /* values for SAS Device Page 0 AccessStatus field */
  1983. #define MPI2_SAS_DEVICE0_ASTATUS_NO_ERRORS (0x00)
  1984. #define MPI2_SAS_DEVICE0_ASTATUS_SATA_INIT_FAILED (0x01)
  1985. #define MPI2_SAS_DEVICE0_ASTATUS_SATA_CAPABILITY_FAILED (0x02)
  1986. #define MPI2_SAS_DEVICE0_ASTATUS_SATA_AFFILIATION_CONFLICT (0x03)
  1987. #define MPI2_SAS_DEVICE0_ASTATUS_SATA_NEEDS_INITIALIZATION (0x04)
  1988. #define MPI2_SAS_DEVICE0_ASTATUS_ROUTE_NOT_ADDRESSABLE (0x05)
  1989. #define MPI2_SAS_DEVICE0_ASTATUS_SMP_ERROR_NOT_ADDRESSABLE (0x06)
  1990. #define MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED (0x07)
  1991. /* specific values for SATA Init failures */
  1992. #define MPI2_SAS_DEVICE0_ASTATUS_SIF_UNKNOWN (0x10)
  1993. #define MPI2_SAS_DEVICE0_ASTATUS_SIF_AFFILIATION_CONFLICT (0x11)
  1994. #define MPI2_SAS_DEVICE0_ASTATUS_SIF_DIAG (0x12)
  1995. #define MPI2_SAS_DEVICE0_ASTATUS_SIF_IDENTIFICATION (0x13)
  1996. #define MPI2_SAS_DEVICE0_ASTATUS_SIF_CHECK_POWER (0x14)
  1997. #define MPI2_SAS_DEVICE0_ASTATUS_SIF_PIO_SN (0x15)
  1998. #define MPI2_SAS_DEVICE0_ASTATUS_SIF_MDMA_SN (0x16)
  1999. #define MPI2_SAS_DEVICE0_ASTATUS_SIF_UDMA_SN (0x17)
  2000. #define MPI2_SAS_DEVICE0_ASTATUS_SIF_ZONING_VIOLATION (0x18)
  2001. #define MPI2_SAS_DEVICE0_ASTATUS_SIF_NOT_ADDRESSABLE (0x19)
  2002. #define MPI2_SAS_DEVICE0_ASTATUS_SIF_MAX (0x1F)
  2003. /* see mpi2_sas.h for values for SAS Device Page 0 DeviceInfo values */
  2004. /* values for SAS Device Page 0 Flags field */
  2005. #define MPI2_SAS_DEVICE0_FLAGS_UNAUTHORIZED_DEVICE (0x8000)
  2006. #define MPI2_SAS_DEVICE0_FLAGS_SLUMBER_PM_CAPABLE (0x1000)
  2007. #define MPI2_SAS_DEVICE0_FLAGS_PARTIAL_PM_CAPABLE (0x0800)
  2008. #define MPI2_SAS_DEVICE0_FLAGS_SATA_ASYNCHRONOUS_NOTIFY (0x0400)
  2009. #define MPI2_SAS_DEVICE0_FLAGS_SATA_SW_PRESERVE (0x0200)
  2010. #define MPI2_SAS_DEVICE0_FLAGS_UNSUPPORTED_DEVICE (0x0100)
  2011. #define MPI2_SAS_DEVICE0_FLAGS_SATA_48BIT_LBA_SUPPORTED (0x0080)
  2012. #define MPI2_SAS_DEVICE0_FLAGS_SATA_SMART_SUPPORTED (0x0040)
  2013. #define MPI2_SAS_DEVICE0_FLAGS_SATA_NCQ_SUPPORTED (0x0020)
  2014. #define MPI2_SAS_DEVICE0_FLAGS_SATA_FUA_SUPPORTED (0x0010)
  2015. #define MPI2_SAS_DEVICE0_FLAGS_PORT_SELECTOR_ATTACH (0x0008)
  2016. #define MPI2_SAS_DEVICE0_FLAGS_DEVICE_PRESENT (0x0001)
  2017. /* SAS Device Page 1 */
  2018. typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_1
  2019. {
  2020. MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
  2021. U32 Reserved1; /* 0x08 */
  2022. U64 SASAddress; /* 0x0C */
  2023. U32 Reserved2; /* 0x14 */
  2024. U16 DevHandle; /* 0x18 */
  2025. U16 Reserved3; /* 0x1A */
  2026. U8 InitialRegDeviceFIS[20];/* 0x1C */
  2027. } MPI2_CONFIG_PAGE_SAS_DEV_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_DEV_1,
  2028. Mpi2SasDevicePage1_t, MPI2_POINTER pMpi2SasDevicePage1_t;
  2029. #define MPI2_SASDEVICE1_PAGEVERSION (0x01)
  2030. /****************************************************************************
  2031. * SAS PHY Config Pages
  2032. ****************************************************************************/
  2033. /* SAS PHY Page 0 */
  2034. typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_0
  2035. {
  2036. MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
  2037. U16 OwnerDevHandle; /* 0x08 */
  2038. U16 Reserved1; /* 0x0A */
  2039. U16 AttachedDevHandle; /* 0x0C */
  2040. U8 AttachedPhyIdentifier; /* 0x0E */
  2041. U8 Reserved2; /* 0x0F */
  2042. U32 AttachedPhyInfo; /* 0x10 */
  2043. U8 ProgrammedLinkRate; /* 0x14 */
  2044. U8 HwLinkRate; /* 0x15 */
  2045. U8 ChangeCount; /* 0x16 */
  2046. U8 Flags; /* 0x17 */
  2047. U32 PhyInfo; /* 0x18 */
  2048. U8 NegotiatedLinkRate; /* 0x1C */
  2049. U8 Reserved3; /* 0x1D */
  2050. U16 Reserved4; /* 0x1E */
  2051. } MPI2_CONFIG_PAGE_SAS_PHY_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_0,
  2052. Mpi2SasPhyPage0_t, MPI2_POINTER pMpi2SasPhyPage0_t;
  2053. #define MPI2_SASPHY0_PAGEVERSION (0x03)
  2054. /* use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */
  2055. /* use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */
  2056. /* use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */
  2057. /* values for SAS PHY Page 0 Flags field */
  2058. #define MPI2_SAS_PHY0_FLAGS_SGPIO_DIRECT_ATTACH_ENC (0x01)
  2059. /* use MPI2_SAS_PHYINFO_ for the PhyInfo field */
  2060. /* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
  2061. /* SAS PHY Page 1 */
  2062. typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_1
  2063. {
  2064. MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
  2065. U32 Reserved1; /* 0x08 */
  2066. U32 InvalidDwordCount; /* 0x0C */
  2067. U32 RunningDisparityErrorCount; /* 0x10 */
  2068. U32 LossDwordSynchCount; /* 0x14 */
  2069. U32 PhyResetProblemCount; /* 0x18 */
  2070. } MPI2_CONFIG_PAGE_SAS_PHY_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_1,
  2071. Mpi2SasPhyPage1_t, MPI2_POINTER pMpi2SasPhyPage1_t;
  2072. #define MPI2_SASPHY1_PAGEVERSION (0x01)
  2073. /* SAS PHY Page 2 */
  2074. typedef struct _MPI2_SASPHY2_PHY_EVENT {
  2075. U8 PhyEventCode; /* 0x00 */
  2076. U8 Reserved1; /* 0x01 */
  2077. U16 Reserved2; /* 0x02 */
  2078. U32 PhyEventInfo; /* 0x04 */
  2079. } MPI2_SASPHY2_PHY_EVENT, MPI2_POINTER PTR_MPI2_SASPHY2_PHY_EVENT,
  2080. Mpi2SasPhy2PhyEvent_t, MPI2_POINTER pMpi2SasPhy2PhyEvent_t;
  2081. /* use MPI2_SASPHY3_EVENT_CODE_ for the PhyEventCode field */
  2082. /*
  2083. * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
  2084. * one and check the value returned for NumPhyEvents at runtime.
  2085. */
  2086. #ifndef MPI2_SASPHY2_PHY_EVENT_MAX
  2087. #define MPI2_SASPHY2_PHY_EVENT_MAX (1)
  2088. #endif
  2089. typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_2 {
  2090. MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
  2091. U32 Reserved1; /* 0x08 */
  2092. U8 NumPhyEvents; /* 0x0C */
  2093. U8 Reserved2; /* 0x0D */
  2094. U16 Reserved3; /* 0x0E */
  2095. MPI2_SASPHY2_PHY_EVENT PhyEvent[MPI2_SASPHY2_PHY_EVENT_MAX];
  2096. /* 0x10 */
  2097. } MPI2_CONFIG_PAGE_SAS_PHY_2, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_2,
  2098. Mpi2SasPhyPage2_t, MPI2_POINTER pMpi2SasPhyPage2_t;
  2099. #define MPI2_SASPHY2_PAGEVERSION (0x00)
  2100. /* SAS PHY Page 3 */
  2101. typedef struct _MPI2_SASPHY3_PHY_EVENT_CONFIG {
  2102. U8 PhyEventCode; /* 0x00 */
  2103. U8 Reserved1; /* 0x01 */
  2104. U16 Reserved2; /* 0x02 */
  2105. U8 CounterType; /* 0x04 */
  2106. U8 ThresholdWindow; /* 0x05 */
  2107. U8 TimeUnits; /* 0x06 */
  2108. U8 Reserved3; /* 0x07 */
  2109. U32 EventThreshold; /* 0x08 */
  2110. U16 ThresholdFlags; /* 0x0C */
  2111. U16 Reserved4; /* 0x0E */
  2112. } MPI2_SASPHY3_PHY_EVENT_CONFIG, MPI2_POINTER PTR_MPI2_SASPHY3_PHY_EVENT_CONFIG,
  2113. Mpi2SasPhy3PhyEventConfig_t, MPI2_POINTER pMpi2SasPhy3PhyEventConfig_t;
  2114. /* values for PhyEventCode field */
  2115. #define MPI2_SASPHY3_EVENT_CODE_NO_EVENT (0x00)
  2116. #define MPI2_SASPHY3_EVENT_CODE_INVALID_DWORD (0x01)
  2117. #define MPI2_SASPHY3_EVENT_CODE_RUNNING_DISPARITY_ERROR (0x02)
  2118. #define MPI2_SASPHY3_EVENT_CODE_LOSS_DWORD_SYNC (0x03)
  2119. #define MPI2_SASPHY3_EVENT_CODE_PHY_RESET_PROBLEM (0x04)
  2120. #define MPI2_SASPHY3_EVENT_CODE_ELASTICITY_BUF_OVERFLOW (0x05)
  2121. #define MPI2_SASPHY3_EVENT_CODE_RX_ERROR (0x06)
  2122. #define MPI2_SASPHY3_EVENT_CODE_RX_ADDR_FRAME_ERROR (0x20)
  2123. #define MPI2_SASPHY3_EVENT_CODE_TX_AC_OPEN_REJECT (0x21)
  2124. #define MPI2_SASPHY3_EVENT_CODE_RX_AC_OPEN_REJECT (0x22)
  2125. #define MPI2_SASPHY3_EVENT_CODE_TX_RC_OPEN_REJECT (0x23)
  2126. #define MPI2_SASPHY3_EVENT_CODE_RX_RC_OPEN_REJECT (0x24)
  2127. #define MPI2_SASPHY3_EVENT_CODE_RX_AIP_PARTIAL_WAITING_ON (0x25)
  2128. #define MPI2_SASPHY3_EVENT_CODE_RX_AIP_CONNECT_WAITING_ON (0x26)
  2129. #define MPI2_SASPHY3_EVENT_CODE_TX_BREAK (0x27)
  2130. #define MPI2_SASPHY3_EVENT_CODE_RX_BREAK (0x28)
  2131. #define MPI2_SASPHY3_EVENT_CODE_BREAK_TIMEOUT (0x29)
  2132. #define MPI2_SASPHY3_EVENT_CODE_CONNECTION (0x2A)
  2133. #define MPI2_SASPHY3_EVENT_CODE_PEAKTX_PATHWAY_BLOCKED (0x2B)
  2134. #define MPI2_SASPHY3_EVENT_CODE_PEAKTX_ARB_WAIT_TIME (0x2C)
  2135. #define MPI2_SASPHY3_EVENT_CODE_PEAK_ARB_WAIT_TIME (0x2D)
  2136. #define MPI2_SASPHY3_EVENT_CODE_PEAK_CONNECT_TIME (0x2E)
  2137. #define MPI2_SASPHY3_EVENT_CODE_TX_SSP_FRAMES (0x40)
  2138. #define MPI2_SASPHY3_EVENT_CODE_RX_SSP_FRAMES (0x41)
  2139. #define MPI2_SASPHY3_EVENT_CODE_TX_SSP_ERROR_FRAMES (0x42)
  2140. #define MPI2_SASPHY3_EVENT_CODE_RX_SSP_ERROR_FRAMES (0x43)
  2141. #define MPI2_SASPHY3_EVENT_CODE_TX_CREDIT_BLOCKED (0x44)
  2142. #define MPI2_SASPHY3_EVENT_CODE_RX_CREDIT_BLOCKED (0x45)
  2143. #define MPI2_SASPHY3_EVENT_CODE_TX_SATA_FRAMES (0x50)
  2144. #define MPI2_SASPHY3_EVENT_CODE_RX_SATA_FRAMES (0x51)
  2145. #define MPI2_SASPHY3_EVENT_CODE_SATA_OVERFLOW (0x52)
  2146. #define MPI2_SASPHY3_EVENT_CODE_TX_SMP_FRAMES (0x60)
  2147. #define MPI2_SASPHY3_EVENT_CODE_RX_SMP_FRAMES (0x61)
  2148. #define MPI2_SASPHY3_EVENT_CODE_RX_SMP_ERROR_FRAMES (0x63)
  2149. #define MPI2_SASPHY3_EVENT_CODE_HOTPLUG_TIMEOUT (0xD0)
  2150. #define MPI2_SASPHY3_EVENT_CODE_MISALIGNED_MUX_PRIMITIVE (0xD1)
  2151. #define MPI2_SASPHY3_EVENT_CODE_RX_AIP (0xD2)
  2152. /* values for the CounterType field */
  2153. #define MPI2_SASPHY3_COUNTER_TYPE_WRAPPING (0x00)
  2154. #define MPI2_SASPHY3_COUNTER_TYPE_SATURATING (0x01)
  2155. #define MPI2_SASPHY3_COUNTER_TYPE_PEAK_VALUE (0x02)
  2156. /* values for the TimeUnits field */
  2157. #define MPI2_SASPHY3_TIME_UNITS_10_MICROSECONDS (0x00)
  2158. #define MPI2_SASPHY3_TIME_UNITS_100_MICROSECONDS (0x01)
  2159. #define MPI2_SASPHY3_TIME_UNITS_1_MILLISECOND (0x02)
  2160. #define MPI2_SASPHY3_TIME_UNITS_10_MILLISECONDS (0x03)
  2161. /* values for the ThresholdFlags field */
  2162. #define MPI2_SASPHY3_TFLAGS_PHY_RESET (0x0002)
  2163. #define MPI2_SASPHY3_TFLAGS_EVENT_NOTIFY (0x0001)
  2164. /*
  2165. * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
  2166. * one and check the value returned for NumPhyEvents at runtime.
  2167. */
  2168. #ifndef MPI2_SASPHY3_PHY_EVENT_MAX
  2169. #define MPI2_SASPHY3_PHY_EVENT_MAX (1)
  2170. #endif
  2171. typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_3 {
  2172. MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
  2173. U32 Reserved1; /* 0x08 */
  2174. U8 NumPhyEvents; /* 0x0C */
  2175. U8 Reserved2; /* 0x0D */
  2176. U16 Reserved3; /* 0x0E */
  2177. MPI2_SASPHY3_PHY_EVENT_CONFIG PhyEventConfig
  2178. [MPI2_SASPHY3_PHY_EVENT_MAX]; /* 0x10 */
  2179. } MPI2_CONFIG_PAGE_SAS_PHY_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_3,
  2180. Mpi2SasPhyPage3_t, MPI2_POINTER pMpi2SasPhyPage3_t;
  2181. #define MPI2_SASPHY3_PAGEVERSION (0x00)
  2182. /* SAS PHY Page 4 */
  2183. typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_4 {
  2184. MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
  2185. U16 Reserved1; /* 0x08 */
  2186. U8 Reserved2; /* 0x0A */
  2187. U8 Flags; /* 0x0B */
  2188. U8 InitialFrame[28]; /* 0x0C */
  2189. } MPI2_CONFIG_PAGE_SAS_PHY_4, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_4,
  2190. Mpi2SasPhyPage4_t, MPI2_POINTER pMpi2SasPhyPage4_t;
  2191. #define MPI2_SASPHY4_PAGEVERSION (0x00)
  2192. /* values for the Flags field */
  2193. #define MPI2_SASPHY4_FLAGS_FRAME_VALID (0x02)
  2194. #define MPI2_SASPHY4_FLAGS_SATA_FRAME (0x01)
  2195. /****************************************************************************
  2196. * SAS Port Config Pages
  2197. ****************************************************************************/
  2198. /* SAS Port Page 0 */
  2199. typedef struct _MPI2_CONFIG_PAGE_SAS_PORT_0
  2200. {
  2201. MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
  2202. U8 PortNumber; /* 0x08 */
  2203. U8 PhysicalPort; /* 0x09 */
  2204. U8 PortWidth; /* 0x0A */
  2205. U8 PhysicalPortWidth; /* 0x0B */
  2206. U8 ZoneGroup; /* 0x0C */
  2207. U8 Reserved1; /* 0x0D */
  2208. U16 Reserved2; /* 0x0E */
  2209. U64 SASAddress; /* 0x10 */
  2210. U32 DeviceInfo; /* 0x18 */
  2211. U32 Reserved3; /* 0x1C */
  2212. U32 Reserved4; /* 0x20 */
  2213. } MPI2_CONFIG_PAGE_SAS_PORT_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PORT_0,
  2214. Mpi2SasPortPage0_t, MPI2_POINTER pMpi2SasPortPage0_t;
  2215. #define MPI2_SASPORT0_PAGEVERSION (0x00)
  2216. /* see mpi2_sas.h for values for SAS Port Page 0 DeviceInfo values */
  2217. /****************************************************************************
  2218. * SAS Enclosure Config Pages
  2219. ****************************************************************************/
  2220. /* SAS Enclosure Page 0 */
  2221. typedef struct _MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0
  2222. {
  2223. MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
  2224. U32 Reserved1; /* 0x08 */
  2225. U64 EnclosureLogicalID; /* 0x0C */
  2226. U16 Flags; /* 0x14 */
  2227. U16 EnclosureHandle; /* 0x16 */
  2228. U16 NumSlots; /* 0x18 */
  2229. U16 StartSlot; /* 0x1A */
  2230. U16 Reserved2; /* 0x1C */
  2231. U16 SEPDevHandle; /* 0x1E */
  2232. U32 Reserved3; /* 0x20 */
  2233. U32 Reserved4; /* 0x24 */
  2234. } MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0,
  2235. MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0,
  2236. Mpi2SasEnclosurePage0_t, MPI2_POINTER pMpi2SasEnclosurePage0_t;
  2237. #define MPI2_SASENCLOSURE0_PAGEVERSION (0x03)
  2238. /* values for SAS Enclosure Page 0 Flags field */
  2239. #define MPI2_SAS_ENCLS0_FLAGS_MNG_MASK (0x000F)
  2240. #define MPI2_SAS_ENCLS0_FLAGS_MNG_UNKNOWN (0x0000)
  2241. #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SES (0x0001)
  2242. #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SGPIO (0x0002)
  2243. #define MPI2_SAS_ENCLS0_FLAGS_MNG_EXP_SGPIO (0x0003)
  2244. #define MPI2_SAS_ENCLS0_FLAGS_MNG_SES_ENCLOSURE (0x0004)
  2245. #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_GPIO (0x0005)
  2246. /****************************************************************************
  2247. * Log Config Page
  2248. ****************************************************************************/
  2249. /* Log Page 0 */
  2250. /*
  2251. * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
  2252. * one and check the value returned for NumLogEntries at runtime.
  2253. */
  2254. #ifndef MPI2_LOG_0_NUM_LOG_ENTRIES
  2255. #define MPI2_LOG_0_NUM_LOG_ENTRIES (1)
  2256. #endif
  2257. #define MPI2_LOG_0_LOG_DATA_LENGTH (0x1C)
  2258. typedef struct _MPI2_LOG_0_ENTRY
  2259. {
  2260. U64 TimeStamp; /* 0x00 */
  2261. U32 Reserved1; /* 0x08 */
  2262. U16 LogSequence; /* 0x0C */
  2263. U16 LogEntryQualifier; /* 0x0E */
  2264. U8 VP_ID; /* 0x10 */
  2265. U8 VF_ID; /* 0x11 */
  2266. U16 Reserved2; /* 0x12 */
  2267. U8 LogData[MPI2_LOG_0_LOG_DATA_LENGTH];/* 0x14 */
  2268. } MPI2_LOG_0_ENTRY, MPI2_POINTER PTR_MPI2_LOG_0_ENTRY,
  2269. Mpi2Log0Entry_t, MPI2_POINTER pMpi2Log0Entry_t;
  2270. /* values for Log Page 0 LogEntry LogEntryQualifier field */
  2271. #define MPI2_LOG_0_ENTRY_QUAL_ENTRY_UNUSED (0x0000)
  2272. #define MPI2_LOG_0_ENTRY_QUAL_POWER_ON_RESET (0x0001)
  2273. #define MPI2_LOG_0_ENTRY_QUAL_TIMESTAMP_UPDATE (0x0002)
  2274. #define MPI2_LOG_0_ENTRY_QUAL_MIN_IMPLEMENT_SPEC (0x8000)
  2275. #define MPI2_LOG_0_ENTRY_QUAL_MAX_IMPLEMENT_SPEC (0xFFFF)
  2276. typedef struct _MPI2_CONFIG_PAGE_LOG_0
  2277. {
  2278. MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
  2279. U32 Reserved1; /* 0x08 */
  2280. U32 Reserved2; /* 0x0C */
  2281. U16 NumLogEntries; /* 0x10 */
  2282. U16 Reserved3; /* 0x12 */
  2283. MPI2_LOG_0_ENTRY LogEntry[MPI2_LOG_0_NUM_LOG_ENTRIES]; /* 0x14 */
  2284. } MPI2_CONFIG_PAGE_LOG_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_LOG_0,
  2285. Mpi2LogPage0_t, MPI2_POINTER pMpi2LogPage0_t;
  2286. #define MPI2_LOG_0_PAGEVERSION (0x02)
  2287. /****************************************************************************
  2288. * RAID Config Page
  2289. ****************************************************************************/
  2290. /* RAID Page 0 */
  2291. /*
  2292. * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
  2293. * one and check the value returned for NumElements at runtime.
  2294. */
  2295. #ifndef MPI2_RAIDCONFIG0_MAX_ELEMENTS
  2296. #define MPI2_RAIDCONFIG0_MAX_ELEMENTS (1)
  2297. #endif
  2298. typedef struct _MPI2_RAIDCONFIG0_CONFIG_ELEMENT
  2299. {
  2300. U16 ElementFlags; /* 0x00 */
  2301. U16 VolDevHandle; /* 0x02 */
  2302. U8 HotSparePool; /* 0x04 */
  2303. U8 PhysDiskNum; /* 0x05 */
  2304. U16 PhysDiskDevHandle; /* 0x06 */
  2305. } MPI2_RAIDCONFIG0_CONFIG_ELEMENT,
  2306. MPI2_POINTER PTR_MPI2_RAIDCONFIG0_CONFIG_ELEMENT,
  2307. Mpi2RaidConfig0ConfigElement_t, MPI2_POINTER pMpi2RaidConfig0ConfigElement_t;
  2308. /* values for the ElementFlags field */
  2309. #define MPI2_RAIDCONFIG0_EFLAGS_MASK_ELEMENT_TYPE (0x000F)
  2310. #define MPI2_RAIDCONFIG0_EFLAGS_VOLUME_ELEMENT (0x0000)
  2311. #define MPI2_RAIDCONFIG0_EFLAGS_VOL_PHYS_DISK_ELEMENT (0x0001)
  2312. #define MPI2_RAIDCONFIG0_EFLAGS_HOT_SPARE_ELEMENT (0x0002)
  2313. #define MPI2_RAIDCONFIG0_EFLAGS_OCE_ELEMENT (0x0003)
  2314. typedef struct _MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0
  2315. {
  2316. MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
  2317. U8 NumHotSpares; /* 0x08 */
  2318. U8 NumPhysDisks; /* 0x09 */
  2319. U8 NumVolumes; /* 0x0A */
  2320. U8 ConfigNum; /* 0x0B */
  2321. U32 Flags; /* 0x0C */
  2322. U8 ConfigGUID[24]; /* 0x10 */
  2323. U32 Reserved1; /* 0x28 */
  2324. U8 NumElements; /* 0x2C */
  2325. U8 Reserved2; /* 0x2D */
  2326. U16 Reserved3; /* 0x2E */
  2327. MPI2_RAIDCONFIG0_CONFIG_ELEMENT ConfigElement[MPI2_RAIDCONFIG0_MAX_ELEMENTS]; /* 0x30 */
  2328. } MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0,
  2329. MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0,
  2330. Mpi2RaidConfigurationPage0_t, MPI2_POINTER pMpi2RaidConfigurationPage0_t;
  2331. #define MPI2_RAIDCONFIG0_PAGEVERSION (0x00)
  2332. /* values for RAID Configuration Page 0 Flags field */
  2333. #define MPI2_RAIDCONFIG0_FLAG_FOREIGN_CONFIG (0x00000001)
  2334. /****************************************************************************
  2335. * Driver Persistent Mapping Config Pages
  2336. ****************************************************************************/
  2337. /* Driver Persistent Mapping Page 0 */
  2338. typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY
  2339. {
  2340. U64 PhysicalIdentifier; /* 0x00 */
  2341. U16 MappingInformation; /* 0x08 */
  2342. U16 DeviceIndex; /* 0x0A */
  2343. U32 PhysicalBitsMapping; /* 0x0C */
  2344. U32 Reserved1; /* 0x10 */
  2345. } MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY,
  2346. MPI2_POINTER PTR_MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY,
  2347. Mpi2DriverMap0Entry_t, MPI2_POINTER pMpi2DriverMap0Entry_t;
  2348. typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAPPING_0
  2349. {
  2350. MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
  2351. MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY Entry; /* 0x08 */
  2352. } MPI2_CONFIG_PAGE_DRIVER_MAPPING_0,
  2353. MPI2_POINTER PTR_MPI2_CONFIG_PAGE_DRIVER_MAPPING_0,
  2354. Mpi2DriverMappingPage0_t, MPI2_POINTER pMpi2DriverMappingPage0_t;
  2355. #define MPI2_DRIVERMAPPING0_PAGEVERSION (0x00)
  2356. /* values for Driver Persistent Mapping Page 0 MappingInformation field */
  2357. #define MPI2_DRVMAP0_MAPINFO_SLOT_MASK (0x07F0)
  2358. #define MPI2_DRVMAP0_MAPINFO_SLOT_SHIFT (4)
  2359. #define MPI2_DRVMAP0_MAPINFO_MISSING_MASK (0x000F)
  2360. /****************************************************************************
  2361. * Ethernet Config Pages
  2362. ****************************************************************************/
  2363. /* Ethernet Page 0 */
  2364. /* IP address (union of IPv4 and IPv6) */
  2365. typedef union _MPI2_ETHERNET_IP_ADDR {
  2366. U32 IPv4Addr;
  2367. U32 IPv6Addr[4];
  2368. } MPI2_ETHERNET_IP_ADDR, MPI2_POINTER PTR_MPI2_ETHERNET_IP_ADDR,
  2369. Mpi2EthernetIpAddr_t, MPI2_POINTER pMpi2EthernetIpAddr_t;
  2370. #define MPI2_ETHERNET_HOST_NAME_LENGTH (32)
  2371. typedef struct _MPI2_CONFIG_PAGE_ETHERNET_0 {
  2372. MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
  2373. U8 NumInterfaces; /* 0x08 */
  2374. U8 Reserved0; /* 0x09 */
  2375. U16 Reserved1; /* 0x0A */
  2376. U32 Status; /* 0x0C */
  2377. U8 MediaState; /* 0x10 */
  2378. U8 Reserved2; /* 0x11 */
  2379. U16 Reserved3; /* 0x12 */
  2380. U8 MacAddress[6]; /* 0x14 */
  2381. U8 Reserved4; /* 0x1A */
  2382. U8 Reserved5; /* 0x1B */
  2383. MPI2_ETHERNET_IP_ADDR IpAddress; /* 0x1C */
  2384. MPI2_ETHERNET_IP_ADDR SubnetMask; /* 0x2C */
  2385. MPI2_ETHERNET_IP_ADDR GatewayIpAddress; /* 0x3C */
  2386. MPI2_ETHERNET_IP_ADDR DNS1IpAddress; /* 0x4C */
  2387. MPI2_ETHERNET_IP_ADDR DNS2IpAddress; /* 0x5C */
  2388. MPI2_ETHERNET_IP_ADDR DhcpIpAddress; /* 0x6C */
  2389. U8 HostName
  2390. [MPI2_ETHERNET_HOST_NAME_LENGTH];/* 0x7C */
  2391. } MPI2_CONFIG_PAGE_ETHERNET_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_ETHERNET_0,
  2392. Mpi2EthernetPage0_t, MPI2_POINTER pMpi2EthernetPage0_t;
  2393. #define MPI2_ETHERNETPAGE0_PAGEVERSION (0x00)
  2394. /* values for Ethernet Page 0 Status field */
  2395. #define MPI2_ETHPG0_STATUS_IPV6_CAPABLE (0x80000000)
  2396. #define MPI2_ETHPG0_STATUS_IPV4_CAPABLE (0x40000000)
  2397. #define MPI2_ETHPG0_STATUS_CONSOLE_CONNECTED (0x20000000)
  2398. #define MPI2_ETHPG0_STATUS_DEFAULT_IF (0x00000100)
  2399. #define MPI2_ETHPG0_STATUS_FW_DWNLD_ENABLED (0x00000080)
  2400. #define MPI2_ETHPG0_STATUS_TELNET_ENABLED (0x00000040)
  2401. #define MPI2_ETHPG0_STATUS_SSH2_ENABLED (0x00000020)
  2402. #define MPI2_ETHPG0_STATUS_DHCP_CLIENT_ENABLED (0x00000010)
  2403. #define MPI2_ETHPG0_STATUS_IPV6_ENABLED (0x00000008)
  2404. #define MPI2_ETHPG0_STATUS_IPV4_ENABLED (0x00000004)
  2405. #define MPI2_ETHPG0_STATUS_IPV6_ADDRESSES (0x00000002)
  2406. #define MPI2_ETHPG0_STATUS_ETH_IF_ENABLED (0x00000001)
  2407. /* values for Ethernet Page 0 MediaState field */
  2408. #define MPI2_ETHPG0_MS_DUPLEX_MASK (0x80)
  2409. #define MPI2_ETHPG0_MS_HALF_DUPLEX (0x00)
  2410. #define MPI2_ETHPG0_MS_FULL_DUPLEX (0x80)
  2411. #define MPI2_ETHPG0_MS_CONNECT_SPEED_MASK (0x07)
  2412. #define MPI2_ETHPG0_MS_NOT_CONNECTED (0x00)
  2413. #define MPI2_ETHPG0_MS_10MBIT (0x01)
  2414. #define MPI2_ETHPG0_MS_100MBIT (0x02)
  2415. #define MPI2_ETHPG0_MS_1GBIT (0x03)
  2416. /* Ethernet Page 1 */
  2417. typedef struct _MPI2_CONFIG_PAGE_ETHERNET_1 {
  2418. MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
  2419. U32 Reserved0; /* 0x08 */
  2420. U32 Flags; /* 0x0C */
  2421. U8 MediaState; /* 0x10 */
  2422. U8 Reserved1; /* 0x11 */
  2423. U16 Reserved2; /* 0x12 */
  2424. U8 MacAddress[6]; /* 0x14 */
  2425. U8 Reserved3; /* 0x1A */
  2426. U8 Reserved4; /* 0x1B */
  2427. MPI2_ETHERNET_IP_ADDR StaticIpAddress; /* 0x1C */
  2428. MPI2_ETHERNET_IP_ADDR StaticSubnetMask; /* 0x2C */
  2429. MPI2_ETHERNET_IP_ADDR StaticGatewayIpAddress; /* 0x3C */
  2430. MPI2_ETHERNET_IP_ADDR StaticDNS1IpAddress; /* 0x4C */
  2431. MPI2_ETHERNET_IP_ADDR StaticDNS2IpAddress; /* 0x5C */
  2432. U32 Reserved5; /* 0x6C */
  2433. U32 Reserved6; /* 0x70 */
  2434. U32 Reserved7; /* 0x74 */
  2435. U32 Reserved8; /* 0x78 */
  2436. U8 HostName
  2437. [MPI2_ETHERNET_HOST_NAME_LENGTH];/* 0x7C */
  2438. } MPI2_CONFIG_PAGE_ETHERNET_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_ETHERNET_1,
  2439. Mpi2EthernetPage1_t, MPI2_POINTER pMpi2EthernetPage1_t;
  2440. #define MPI2_ETHERNETPAGE1_PAGEVERSION (0x00)
  2441. /* values for Ethernet Page 1 Flags field */
  2442. #define MPI2_ETHPG1_FLAG_SET_DEFAULT_IF (0x00000100)
  2443. #define MPI2_ETHPG1_FLAG_ENABLE_FW_DOWNLOAD (0x00000080)
  2444. #define MPI2_ETHPG1_FLAG_ENABLE_TELNET (0x00000040)
  2445. #define MPI2_ETHPG1_FLAG_ENABLE_SSH2 (0x00000020)
  2446. #define MPI2_ETHPG1_FLAG_ENABLE_DHCP_CLIENT (0x00000010)
  2447. #define MPI2_ETHPG1_FLAG_ENABLE_IPV6 (0x00000008)
  2448. #define MPI2_ETHPG1_FLAG_ENABLE_IPV4 (0x00000004)
  2449. #define MPI2_ETHPG1_FLAG_USE_IPV6_ADDRESSES (0x00000002)
  2450. #define MPI2_ETHPG1_FLAG_ENABLE_ETH_IF (0x00000001)
  2451. /* values for Ethernet Page 1 MediaState field */
  2452. #define MPI2_ETHPG1_MS_DUPLEX_MASK (0x80)
  2453. #define MPI2_ETHPG1_MS_HALF_DUPLEX (0x00)
  2454. #define MPI2_ETHPG1_MS_FULL_DUPLEX (0x80)
  2455. #define MPI2_ETHPG1_MS_DATA_RATE_MASK (0x07)
  2456. #define MPI2_ETHPG1_MS_DATA_RATE_AUTO (0x00)
  2457. #define MPI2_ETHPG1_MS_DATA_RATE_10MBIT (0x01)
  2458. #define MPI2_ETHPG1_MS_DATA_RATE_100MBIT (0x02)
  2459. #define MPI2_ETHPG1_MS_DATA_RATE_1GBIT (0x03)
  2460. /****************************************************************************
  2461. * Extended Manufacturing Config Pages
  2462. ****************************************************************************/
  2463. /*
  2464. * Generic structure to use for product-specific extended manufacturing pages
  2465. * (currently Extended Manufacturing Page 40 through Extended Manufacturing
  2466. * Page 60).
  2467. */
  2468. typedef struct _MPI2_CONFIG_PAGE_EXT_MAN_PS {
  2469. MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
  2470. U32 ProductSpecificInfo; /* 0x08 */
  2471. } MPI2_CONFIG_PAGE_EXT_MAN_PS,
  2472. MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXT_MAN_PS,
  2473. Mpi2ExtManufacturingPagePS_t,
  2474. MPI2_POINTER pMpi2ExtManufacturingPagePS_t;
  2475. /* PageVersion should be provided by product-specific code */
  2476. #endif