aerdrv.h 3.4 KB

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  1. /*
  2. * Copyright (C) 2006 Intel Corp.
  3. * Tom Long Nguyen (tom.l.nguyen@intel.com)
  4. * Zhang Yanmin (yanmin.zhang@intel.com)
  5. *
  6. */
  7. #ifndef _AERDRV_H_
  8. #define _AERDRV_H_
  9. #include <linux/workqueue.h>
  10. #include <linux/pcieport_if.h>
  11. #include <linux/aer.h>
  12. #include <linux/interrupt.h>
  13. #define AER_NONFATAL 0
  14. #define AER_FATAL 1
  15. #define AER_CORRECTABLE 2
  16. #define AER_UNCORRECTABLE 4
  17. #define AER_ERROR_MASK 0x001fffff
  18. #define AER_ERROR(d) (d & AER_ERROR_MASK)
  19. /* Root Error Status Register Bits */
  20. #define ROOT_ERR_STATUS_MASKS 0x0f
  21. #define SYSTEM_ERROR_INTR_ON_MESG_MASK (PCI_EXP_RTCTL_SECEE| \
  22. PCI_EXP_RTCTL_SENFEE| \
  23. PCI_EXP_RTCTL_SEFEE)
  24. #define ROOT_PORT_INTR_ON_MESG_MASK (PCI_ERR_ROOT_CMD_COR_EN| \
  25. PCI_ERR_ROOT_CMD_NONFATAL_EN| \
  26. PCI_ERR_ROOT_CMD_FATAL_EN)
  27. #define ERR_COR_ID(d) (d & 0xffff)
  28. #define ERR_UNCOR_ID(d) (d >> 16)
  29. #define AER_SUCCESS 0
  30. #define AER_UNSUCCESS 1
  31. #define AER_ERROR_SOURCES_MAX 100
  32. #define AER_LOG_TLP_MASKS (PCI_ERR_UNC_POISON_TLP| \
  33. PCI_ERR_UNC_ECRC| \
  34. PCI_ERR_UNC_UNSUP| \
  35. PCI_ERR_UNC_COMP_ABORT| \
  36. PCI_ERR_UNC_UNX_COMP| \
  37. PCI_ERR_UNC_MALF_TLP)
  38. /* AER Error Info Flags */
  39. #define AER_TLP_HEADER_VALID_FLAG 0x00000001
  40. #define AER_MULTI_ERROR_VALID_FLAG 0x00000002
  41. #define ERR_CORRECTABLE_ERROR_MASK 0x000031c1
  42. #define ERR_UNCORRECTABLE_ERROR_MASK 0x001ff010
  43. struct header_log_regs {
  44. unsigned int dw0;
  45. unsigned int dw1;
  46. unsigned int dw2;
  47. unsigned int dw3;
  48. };
  49. #define AER_MAX_MULTI_ERR_DEVICES 5 /* Not likely to have more */
  50. struct aer_err_info {
  51. struct pci_dev *dev[AER_MAX_MULTI_ERR_DEVICES];
  52. int error_dev_num;
  53. u16 id;
  54. int severity; /* 0:NONFATAL | 1:FATAL | 2:COR */
  55. int flags;
  56. unsigned int status; /* COR/UNCOR Error Status */
  57. struct header_log_regs tlp; /* TLP Header */
  58. };
  59. struct aer_err_source {
  60. unsigned int status;
  61. unsigned int id;
  62. };
  63. struct aer_rpc {
  64. struct pcie_device *rpd; /* Root Port device */
  65. struct work_struct dpc_handler;
  66. struct aer_err_source e_sources[AER_ERROR_SOURCES_MAX];
  67. unsigned short prod_idx; /* Error Producer Index */
  68. unsigned short cons_idx; /* Error Consumer Index */
  69. int isr;
  70. spinlock_t e_lock; /*
  71. * Lock access to Error Status/ID Regs
  72. * and error producer/consumer index
  73. */
  74. struct mutex rpc_mutex; /*
  75. * only one thread could do
  76. * recovery on the same
  77. * root port hierarchy
  78. */
  79. wait_queue_head_t wait_release;
  80. };
  81. struct aer_broadcast_data {
  82. enum pci_channel_state state;
  83. enum pci_ers_result result;
  84. };
  85. static inline pci_ers_result_t merge_result(enum pci_ers_result orig,
  86. enum pci_ers_result new)
  87. {
  88. if (new == PCI_ERS_RESULT_NONE)
  89. return orig;
  90. switch (orig) {
  91. case PCI_ERS_RESULT_CAN_RECOVER:
  92. case PCI_ERS_RESULT_RECOVERED:
  93. orig = new;
  94. break;
  95. case PCI_ERS_RESULT_DISCONNECT:
  96. if (new == PCI_ERS_RESULT_NEED_RESET)
  97. orig = new;
  98. break;
  99. default:
  100. break;
  101. }
  102. return orig;
  103. }
  104. extern struct bus_type pcie_port_bus_type;
  105. extern void aer_enable_rootport(struct aer_rpc *rpc);
  106. extern void aer_delete_rootport(struct aer_rpc *rpc);
  107. extern int aer_init(struct pcie_device *dev);
  108. extern void aer_isr(struct work_struct *work);
  109. extern void aer_print_error(struct pci_dev *dev, struct aer_err_info *info);
  110. extern irqreturn_t aer_irq(int irq, void *context);
  111. #ifdef CONFIG_ACPI
  112. extern int aer_osc_setup(struct pcie_device *pciedev);
  113. #else
  114. static inline int aer_osc_setup(struct pcie_device *pciedev)
  115. {
  116. return 0;
  117. }
  118. #endif
  119. #endif //_AERDRV_H_