3945.c 76 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of version 2 of the GNU General Public License as
  7. * published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program; if not, write to the Free Software Foundation, Inc.,
  16. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17. *
  18. * The full GNU General Public License is included in this distribution in the
  19. * file called LICENSE.
  20. *
  21. * Contact Information:
  22. * Intel Linux Wireless <ilw@linux.intel.com>
  23. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  24. *
  25. *****************************************************************************/
  26. #include <linux/kernel.h>
  27. #include <linux/module.h>
  28. #include <linux/init.h>
  29. #include <linux/slab.h>
  30. #include <linux/pci.h>
  31. #include <linux/dma-mapping.h>
  32. #include <linux/delay.h>
  33. #include <linux/sched.h>
  34. #include <linux/skbuff.h>
  35. #include <linux/netdevice.h>
  36. #include <linux/firmware.h>
  37. #include <linux/etherdevice.h>
  38. #include <asm/unaligned.h>
  39. #include <net/mac80211.h>
  40. #include "iwl-fh.h"
  41. #include "iwl-commands.h"
  42. #include "iwl-sta.h"
  43. #include "iwl-eeprom.h"
  44. #include "iwl-core.h"
  45. #include "iwl-helpers.h"
  46. #include "iwl-led.h"
  47. #include "3945.h"
  48. /* Send led command */
  49. static int il3945_send_led_cmd(struct il_priv *il,
  50. struct il_led_cmd *led_cmd)
  51. {
  52. struct il_host_cmd cmd = {
  53. .id = REPLY_LEDS_CMD,
  54. .len = sizeof(struct il_led_cmd),
  55. .data = led_cmd,
  56. .flags = CMD_ASYNC,
  57. .callback = NULL,
  58. };
  59. return il_send_cmd(il, &cmd);
  60. }
  61. const struct il_led_ops il3945_led_ops = {
  62. .cmd = il3945_send_led_cmd,
  63. };
  64. #define IL_DECLARE_RATE_INFO(r, ip, in, rp, rn, pp, np) \
  65. [RATE_##r##M_IDX] = { RATE_##r##M_PLCP, \
  66. RATE_##r##M_IEEE, \
  67. RATE_##ip##M_IDX, \
  68. RATE_##in##M_IDX, \
  69. RATE_##rp##M_IDX, \
  70. RATE_##rn##M_IDX, \
  71. RATE_##pp##M_IDX, \
  72. RATE_##np##M_IDX, \
  73. RATE_##r##M_IDX_TBL, \
  74. RATE_##ip##M_IDX_TBL }
  75. /*
  76. * Parameter order:
  77. * rate, prev rate, next rate, prev tgg rate, next tgg rate
  78. *
  79. * If there isn't a valid next or previous rate then INV is used which
  80. * maps to RATE_INVALID
  81. *
  82. */
  83. const struct il3945_rate_info il3945_rates[RATE_COUNT_3945] = {
  84. IL_DECLARE_RATE_INFO(1, INV, 2, INV, 2, INV, 2), /* 1mbps */
  85. IL_DECLARE_RATE_INFO(2, 1, 5, 1, 5, 1, 5), /* 2mbps */
  86. IL_DECLARE_RATE_INFO(5, 2, 6, 2, 11, 2, 11), /*5.5mbps */
  87. IL_DECLARE_RATE_INFO(11, 9, 12, 5, 12, 5, 18), /* 11mbps */
  88. IL_DECLARE_RATE_INFO(6, 5, 9, 5, 11, 5, 11), /* 6mbps */
  89. IL_DECLARE_RATE_INFO(9, 6, 11, 5, 11, 5, 11), /* 9mbps */
  90. IL_DECLARE_RATE_INFO(12, 11, 18, 11, 18, 11, 18), /* 12mbps */
  91. IL_DECLARE_RATE_INFO(18, 12, 24, 12, 24, 11, 24), /* 18mbps */
  92. IL_DECLARE_RATE_INFO(24, 18, 36, 18, 36, 18, 36), /* 24mbps */
  93. IL_DECLARE_RATE_INFO(36, 24, 48, 24, 48, 24, 48), /* 36mbps */
  94. IL_DECLARE_RATE_INFO(48, 36, 54, 36, 54, 36, 54), /* 48mbps */
  95. IL_DECLARE_RATE_INFO(54, 48, INV, 48, INV, 48, INV),/* 54mbps */
  96. };
  97. static inline u8 il3945_get_prev_ieee_rate(u8 rate_idx)
  98. {
  99. u8 rate = il3945_rates[rate_idx].prev_ieee;
  100. if (rate == RATE_INVALID)
  101. rate = rate_idx;
  102. return rate;
  103. }
  104. /* 1 = enable the il3945_disable_events() function */
  105. #define IL_EVT_DISABLE (0)
  106. #define IL_EVT_DISABLE_SIZE (1532/32)
  107. /**
  108. * il3945_disable_events - Disable selected events in uCode event log
  109. *
  110. * Disable an event by writing "1"s into "disable"
  111. * bitmap in SRAM. Bit position corresponds to Event # (id/type).
  112. * Default values of 0 enable uCode events to be logged.
  113. * Use for only special debugging. This function is just a placeholder as-is,
  114. * you'll need to provide the special bits! ...
  115. * ... and set IL_EVT_DISABLE to 1. */
  116. void il3945_disable_events(struct il_priv *il)
  117. {
  118. int i;
  119. u32 base; /* SRAM address of event log header */
  120. u32 disable_ptr; /* SRAM address of event-disable bitmap array */
  121. u32 array_size; /* # of u32 entries in array */
  122. static const u32 evt_disable[IL_EVT_DISABLE_SIZE] = {
  123. 0x00000000, /* 31 - 0 Event id numbers */
  124. 0x00000000, /* 63 - 32 */
  125. 0x00000000, /* 95 - 64 */
  126. 0x00000000, /* 127 - 96 */
  127. 0x00000000, /* 159 - 128 */
  128. 0x00000000, /* 191 - 160 */
  129. 0x00000000, /* 223 - 192 */
  130. 0x00000000, /* 255 - 224 */
  131. 0x00000000, /* 287 - 256 */
  132. 0x00000000, /* 319 - 288 */
  133. 0x00000000, /* 351 - 320 */
  134. 0x00000000, /* 383 - 352 */
  135. 0x00000000, /* 415 - 384 */
  136. 0x00000000, /* 447 - 416 */
  137. 0x00000000, /* 479 - 448 */
  138. 0x00000000, /* 511 - 480 */
  139. 0x00000000, /* 543 - 512 */
  140. 0x00000000, /* 575 - 544 */
  141. 0x00000000, /* 607 - 576 */
  142. 0x00000000, /* 639 - 608 */
  143. 0x00000000, /* 671 - 640 */
  144. 0x00000000, /* 703 - 672 */
  145. 0x00000000, /* 735 - 704 */
  146. 0x00000000, /* 767 - 736 */
  147. 0x00000000, /* 799 - 768 */
  148. 0x00000000, /* 831 - 800 */
  149. 0x00000000, /* 863 - 832 */
  150. 0x00000000, /* 895 - 864 */
  151. 0x00000000, /* 927 - 896 */
  152. 0x00000000, /* 959 - 928 */
  153. 0x00000000, /* 991 - 960 */
  154. 0x00000000, /* 1023 - 992 */
  155. 0x00000000, /* 1055 - 1024 */
  156. 0x00000000, /* 1087 - 1056 */
  157. 0x00000000, /* 1119 - 1088 */
  158. 0x00000000, /* 1151 - 1120 */
  159. 0x00000000, /* 1183 - 1152 */
  160. 0x00000000, /* 1215 - 1184 */
  161. 0x00000000, /* 1247 - 1216 */
  162. 0x00000000, /* 1279 - 1248 */
  163. 0x00000000, /* 1311 - 1280 */
  164. 0x00000000, /* 1343 - 1312 */
  165. 0x00000000, /* 1375 - 1344 */
  166. 0x00000000, /* 1407 - 1376 */
  167. 0x00000000, /* 1439 - 1408 */
  168. 0x00000000, /* 1471 - 1440 */
  169. 0x00000000, /* 1503 - 1472 */
  170. };
  171. base = le32_to_cpu(il->card_alive.log_event_table_ptr);
  172. if (!il3945_hw_valid_rtc_data_addr(base)) {
  173. IL_ERR("Invalid event log pointer 0x%08X\n", base);
  174. return;
  175. }
  176. disable_ptr = il_read_targ_mem(il, base + (4 * sizeof(u32)));
  177. array_size = il_read_targ_mem(il, base + (5 * sizeof(u32)));
  178. if (IL_EVT_DISABLE && array_size == IL_EVT_DISABLE_SIZE) {
  179. D_INFO("Disabling selected uCode log events at 0x%x\n",
  180. disable_ptr);
  181. for (i = 0; i < IL_EVT_DISABLE_SIZE; i++)
  182. il_write_targ_mem(il,
  183. disable_ptr + (i * sizeof(u32)),
  184. evt_disable[i]);
  185. } else {
  186. D_INFO("Selected uCode log events may be disabled\n");
  187. D_INFO(" by writing \"1\"s into disable bitmap\n");
  188. D_INFO(" in SRAM at 0x%x, size %d u32s\n",
  189. disable_ptr, array_size);
  190. }
  191. }
  192. static int il3945_hwrate_to_plcp_idx(u8 plcp)
  193. {
  194. int idx;
  195. for (idx = 0; idx < RATE_COUNT_3945; idx++)
  196. if (il3945_rates[idx].plcp == plcp)
  197. return idx;
  198. return -1;
  199. }
  200. #ifdef CONFIG_IWLEGACY_DEBUG
  201. #define TX_STATUS_ENTRY(x) case TX_3945_STATUS_FAIL_ ## x: return #x
  202. static const char *il3945_get_tx_fail_reason(u32 status)
  203. {
  204. switch (status & TX_STATUS_MSK) {
  205. case TX_3945_STATUS_SUCCESS:
  206. return "SUCCESS";
  207. TX_STATUS_ENTRY(SHORT_LIMIT);
  208. TX_STATUS_ENTRY(LONG_LIMIT);
  209. TX_STATUS_ENTRY(FIFO_UNDERRUN);
  210. TX_STATUS_ENTRY(MGMNT_ABORT);
  211. TX_STATUS_ENTRY(NEXT_FRAG);
  212. TX_STATUS_ENTRY(LIFE_EXPIRE);
  213. TX_STATUS_ENTRY(DEST_PS);
  214. TX_STATUS_ENTRY(ABORTED);
  215. TX_STATUS_ENTRY(BT_RETRY);
  216. TX_STATUS_ENTRY(STA_INVALID);
  217. TX_STATUS_ENTRY(FRAG_DROPPED);
  218. TX_STATUS_ENTRY(TID_DISABLE);
  219. TX_STATUS_ENTRY(FRAME_FLUSHED);
  220. TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL);
  221. TX_STATUS_ENTRY(TX_LOCKED);
  222. TX_STATUS_ENTRY(NO_BEACON_ON_RADAR);
  223. }
  224. return "UNKNOWN";
  225. }
  226. #else
  227. static inline const char *il3945_get_tx_fail_reason(u32 status)
  228. {
  229. return "";
  230. }
  231. #endif
  232. /*
  233. * get ieee prev rate from rate scale table.
  234. * for A and B mode we need to overright prev
  235. * value
  236. */
  237. int il3945_rs_next_rate(struct il_priv *il, int rate)
  238. {
  239. int next_rate = il3945_get_prev_ieee_rate(rate);
  240. switch (il->band) {
  241. case IEEE80211_BAND_5GHZ:
  242. if (rate == RATE_12M_IDX)
  243. next_rate = RATE_9M_IDX;
  244. else if (rate == RATE_6M_IDX)
  245. next_rate = RATE_6M_IDX;
  246. break;
  247. case IEEE80211_BAND_2GHZ:
  248. if (!(il->_3945.sta_supp_rates & IL_OFDM_RATES_MASK) &&
  249. il_is_associated(il)) {
  250. if (rate == RATE_11M_IDX)
  251. next_rate = RATE_5M_IDX;
  252. }
  253. break;
  254. default:
  255. break;
  256. }
  257. return next_rate;
  258. }
  259. /**
  260. * il3945_tx_queue_reclaim - Reclaim Tx queue entries already Tx'd
  261. *
  262. * When FW advances 'R' idx, all entries between old and new 'R' idx
  263. * need to be reclaimed. As result, some free space forms. If there is
  264. * enough free space (> low mark), wake the stack that feeds us.
  265. */
  266. static void il3945_tx_queue_reclaim(struct il_priv *il,
  267. int txq_id, int idx)
  268. {
  269. struct il_tx_queue *txq = &il->txq[txq_id];
  270. struct il_queue *q = &txq->q;
  271. struct il_tx_info *tx_info;
  272. BUG_ON(txq_id == IL39_CMD_QUEUE_NUM);
  273. for (idx = il_queue_inc_wrap(idx, q->n_bd);
  274. q->read_ptr != idx;
  275. q->read_ptr = il_queue_inc_wrap(q->read_ptr, q->n_bd)) {
  276. tx_info = &txq->txb[txq->q.read_ptr];
  277. ieee80211_tx_status_irqsafe(il->hw, tx_info->skb);
  278. tx_info->skb = NULL;
  279. il->cfg->ops->lib->txq_free_tfd(il, txq);
  280. }
  281. if (il_queue_space(q) > q->low_mark && txq_id >= 0 &&
  282. txq_id != IL39_CMD_QUEUE_NUM && il->mac80211_registered)
  283. il_wake_queue(il, txq);
  284. }
  285. /**
  286. * il3945_rx_reply_tx - Handle Tx response
  287. */
  288. static void il3945_rx_reply_tx(struct il_priv *il,
  289. struct il_rx_buf *rxb)
  290. {
  291. struct il_rx_pkt *pkt = rxb_addr(rxb);
  292. u16 sequence = le16_to_cpu(pkt->hdr.sequence);
  293. int txq_id = SEQ_TO_QUEUE(sequence);
  294. int idx = SEQ_TO_IDX(sequence);
  295. struct il_tx_queue *txq = &il->txq[txq_id];
  296. struct ieee80211_tx_info *info;
  297. struct il3945_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
  298. u32 status = le32_to_cpu(tx_resp->status);
  299. int rate_idx;
  300. int fail;
  301. if (idx >= txq->q.n_bd || il_queue_used(&txq->q, idx) == 0) {
  302. IL_ERR("Read idx for DMA queue txq_id (%d) idx %d "
  303. "is out of range [0-%d] %d %d\n", txq_id,
  304. idx, txq->q.n_bd, txq->q.write_ptr,
  305. txq->q.read_ptr);
  306. return;
  307. }
  308. txq->time_stamp = jiffies;
  309. info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb);
  310. ieee80211_tx_info_clear_status(info);
  311. /* Fill the MRR chain with some info about on-chip retransmissions */
  312. rate_idx = il3945_hwrate_to_plcp_idx(tx_resp->rate);
  313. if (info->band == IEEE80211_BAND_5GHZ)
  314. rate_idx -= IL_FIRST_OFDM_RATE;
  315. fail = tx_resp->failure_frame;
  316. info->status.rates[0].idx = rate_idx;
  317. info->status.rates[0].count = fail + 1; /* add final attempt */
  318. /* tx_status->rts_retry_count = tx_resp->failure_rts; */
  319. info->flags |= ((status & TX_STATUS_MSK) == TX_STATUS_SUCCESS) ?
  320. IEEE80211_TX_STAT_ACK : 0;
  321. D_TX("Tx queue %d Status %s (0x%08x) plcp rate %d retries %d\n",
  322. txq_id, il3945_get_tx_fail_reason(status), status,
  323. tx_resp->rate, tx_resp->failure_frame);
  324. D_TX_REPLY("Tx queue reclaim %d\n", idx);
  325. il3945_tx_queue_reclaim(il, txq_id, idx);
  326. if (status & TX_ABORT_REQUIRED_MSK)
  327. IL_ERR("TODO: Implement Tx ABORT REQUIRED!!!\n");
  328. }
  329. /*****************************************************************************
  330. *
  331. * Intel PRO/Wireless 3945ABG/BG Network Connection
  332. *
  333. * RX handler implementations
  334. *
  335. *****************************************************************************/
  336. #ifdef CONFIG_IWLEGACY_DEBUGFS
  337. static void il3945_accumulative_stats(struct il_priv *il,
  338. __le32 *stats)
  339. {
  340. int i;
  341. __le32 *prev_stats;
  342. u32 *accum_stats;
  343. u32 *delta, *max_delta;
  344. prev_stats = (__le32 *)&il->_3945.stats;
  345. accum_stats = (u32 *)&il->_3945.accum_stats;
  346. delta = (u32 *)&il->_3945.delta_stats;
  347. max_delta = (u32 *)&il->_3945.max_delta;
  348. for (i = sizeof(__le32); i < sizeof(struct il3945_notif_stats);
  349. i += sizeof(__le32), stats++, prev_stats++, delta++,
  350. max_delta++, accum_stats++) {
  351. if (le32_to_cpu(*stats) > le32_to_cpu(*prev_stats)) {
  352. *delta = (le32_to_cpu(*stats) -
  353. le32_to_cpu(*prev_stats));
  354. *accum_stats += *delta;
  355. if (*delta > *max_delta)
  356. *max_delta = *delta;
  357. }
  358. }
  359. /* reset accumulative stats for "no-counter" type stats */
  360. il->_3945.accum_stats.general.temperature =
  361. il->_3945.stats.general.temperature;
  362. il->_3945.accum_stats.general.ttl_timestamp =
  363. il->_3945.stats.general.ttl_timestamp;
  364. }
  365. #endif
  366. void il3945_hw_rx_stats(struct il_priv *il,
  367. struct il_rx_buf *rxb)
  368. {
  369. struct il_rx_pkt *pkt = rxb_addr(rxb);
  370. D_RX("Statistics notification received (%d vs %d).\n",
  371. (int)sizeof(struct il3945_notif_stats),
  372. le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK);
  373. #ifdef CONFIG_IWLEGACY_DEBUGFS
  374. il3945_accumulative_stats(il, (__le32 *)&pkt->u.raw);
  375. #endif
  376. memcpy(&il->_3945.stats, pkt->u.raw, sizeof(il->_3945.stats));
  377. }
  378. void il3945_reply_stats(struct il_priv *il,
  379. struct il_rx_buf *rxb)
  380. {
  381. struct il_rx_pkt *pkt = rxb_addr(rxb);
  382. __le32 *flag = (__le32 *)&pkt->u.raw;
  383. if (le32_to_cpu(*flag) & UCODE_STATISTICS_CLEAR_MSK) {
  384. #ifdef CONFIG_IWLEGACY_DEBUGFS
  385. memset(&il->_3945.accum_stats, 0,
  386. sizeof(struct il3945_notif_stats));
  387. memset(&il->_3945.delta_stats, 0,
  388. sizeof(struct il3945_notif_stats));
  389. memset(&il->_3945.max_delta, 0,
  390. sizeof(struct il3945_notif_stats));
  391. #endif
  392. D_RX("Statistics have been cleared\n");
  393. }
  394. il3945_hw_rx_stats(il, rxb);
  395. }
  396. /******************************************************************************
  397. *
  398. * Misc. internal state and helper functions
  399. *
  400. ******************************************************************************/
  401. /* This is necessary only for a number of stats, see the caller. */
  402. static int il3945_is_network_packet(struct il_priv *il,
  403. struct ieee80211_hdr *header)
  404. {
  405. /* Filter incoming packets to determine if they are targeted toward
  406. * this network, discarding packets coming from ourselves */
  407. switch (il->iw_mode) {
  408. case NL80211_IFTYPE_ADHOC: /* Header: Dest. | Source | BSSID */
  409. /* packets to our IBSS update information */
  410. return !compare_ether_addr(header->addr3, il->bssid);
  411. case NL80211_IFTYPE_STATION: /* Header: Dest. | AP{BSSID} | Source */
  412. /* packets to our IBSS update information */
  413. return !compare_ether_addr(header->addr2, il->bssid);
  414. default:
  415. return 1;
  416. }
  417. }
  418. static void il3945_pass_packet_to_mac80211(struct il_priv *il,
  419. struct il_rx_buf *rxb,
  420. struct ieee80211_rx_status *stats)
  421. {
  422. struct il_rx_pkt *pkt = rxb_addr(rxb);
  423. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)IL_RX_DATA(pkt);
  424. struct il3945_rx_frame_hdr *rx_hdr = IL_RX_HDR(pkt);
  425. struct il3945_rx_frame_end *rx_end = IL_RX_END(pkt);
  426. u16 len = le16_to_cpu(rx_hdr->len);
  427. struct sk_buff *skb;
  428. __le16 fc = hdr->frame_control;
  429. /* We received data from the HW, so stop the watchdog */
  430. if (unlikely(len + IL39_RX_FRAME_SIZE >
  431. PAGE_SIZE << il->hw_params.rx_page_order)) {
  432. D_DROP("Corruption detected!\n");
  433. return;
  434. }
  435. /* We only process data packets if the interface is open */
  436. if (unlikely(!il->is_open)) {
  437. D_DROP(
  438. "Dropping packet while interface is not open.\n");
  439. return;
  440. }
  441. skb = dev_alloc_skb(128);
  442. if (!skb) {
  443. IL_ERR("dev_alloc_skb failed\n");
  444. return;
  445. }
  446. if (!il3945_mod_params.sw_crypto)
  447. il_set_decrypted_flag(il,
  448. (struct ieee80211_hdr *)rxb_addr(rxb),
  449. le32_to_cpu(rx_end->status), stats);
  450. skb_add_rx_frag(skb, 0, rxb->page,
  451. (void *)rx_hdr->payload - (void *)pkt, len);
  452. il_update_stats(il, false, fc, len);
  453. memcpy(IEEE80211_SKB_RXCB(skb), stats, sizeof(*stats));
  454. ieee80211_rx(il->hw, skb);
  455. il->alloc_rxb_page--;
  456. rxb->page = NULL;
  457. }
  458. #define IL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
  459. static void il3945_rx_reply_rx(struct il_priv *il,
  460. struct il_rx_buf *rxb)
  461. {
  462. struct ieee80211_hdr *header;
  463. struct ieee80211_rx_status rx_status;
  464. struct il_rx_pkt *pkt = rxb_addr(rxb);
  465. struct il3945_rx_frame_stats *rx_stats = IL_RX_STATS(pkt);
  466. struct il3945_rx_frame_hdr *rx_hdr = IL_RX_HDR(pkt);
  467. struct il3945_rx_frame_end *rx_end = IL_RX_END(pkt);
  468. u16 rx_stats_sig_avg __maybe_unused = le16_to_cpu(rx_stats->sig_avg);
  469. u16 rx_stats_noise_diff __maybe_unused = le16_to_cpu(rx_stats->noise_diff);
  470. u8 network_packet;
  471. rx_status.flag = 0;
  472. rx_status.mactime = le64_to_cpu(rx_end->timestamp);
  473. rx_status.band = (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
  474. IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
  475. rx_status.freq =
  476. ieee80211_channel_to_frequency(le16_to_cpu(rx_hdr->channel),
  477. rx_status.band);
  478. rx_status.rate_idx = il3945_hwrate_to_plcp_idx(rx_hdr->rate);
  479. if (rx_status.band == IEEE80211_BAND_5GHZ)
  480. rx_status.rate_idx -= IL_FIRST_OFDM_RATE;
  481. rx_status.antenna = (le16_to_cpu(rx_hdr->phy_flags) &
  482. RX_RES_PHY_FLAGS_ANTENNA_MSK) >> 4;
  483. /* set the preamble flag if appropriate */
  484. if (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
  485. rx_status.flag |= RX_FLAG_SHORTPRE;
  486. if ((unlikely(rx_stats->phy_count > 20))) {
  487. D_DROP("dsp size out of range [0,20]: %d/n",
  488. rx_stats->phy_count);
  489. return;
  490. }
  491. if (!(rx_end->status & RX_RES_STATUS_NO_CRC32_ERROR) ||
  492. !(rx_end->status & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
  493. D_RX("Bad CRC or FIFO: 0x%08X.\n", rx_end->status);
  494. return;
  495. }
  496. /* Convert 3945's rssi indicator to dBm */
  497. rx_status.signal = rx_stats->rssi - IL39_RSSI_OFFSET;
  498. D_STATS("Rssi %d sig_avg %d noise_diff %d\n",
  499. rx_status.signal, rx_stats_sig_avg,
  500. rx_stats_noise_diff);
  501. header = (struct ieee80211_hdr *)IL_RX_DATA(pkt);
  502. network_packet = il3945_is_network_packet(il, header);
  503. D_STATS("[%c] %d RSSI:%d Signal:%u, Rate:%u\n",
  504. network_packet ? '*' : ' ',
  505. le16_to_cpu(rx_hdr->channel),
  506. rx_status.signal, rx_status.signal,
  507. rx_status.rate_idx);
  508. il_dbg_log_rx_data_frame(il, le16_to_cpu(rx_hdr->len),
  509. header);
  510. if (network_packet) {
  511. il->_3945.last_beacon_time =
  512. le32_to_cpu(rx_end->beacon_timestamp);
  513. il->_3945.last_tsf = le64_to_cpu(rx_end->timestamp);
  514. il->_3945.last_rx_rssi = rx_status.signal;
  515. }
  516. il3945_pass_packet_to_mac80211(il, rxb, &rx_status);
  517. }
  518. int il3945_hw_txq_attach_buf_to_tfd(struct il_priv *il,
  519. struct il_tx_queue *txq,
  520. dma_addr_t addr, u16 len, u8 reset, u8 pad)
  521. {
  522. int count;
  523. struct il_queue *q;
  524. struct il3945_tfd *tfd, *tfd_tmp;
  525. q = &txq->q;
  526. tfd_tmp = (struct il3945_tfd *)txq->tfds;
  527. tfd = &tfd_tmp[q->write_ptr];
  528. if (reset)
  529. memset(tfd, 0, sizeof(*tfd));
  530. count = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
  531. if (count >= NUM_TFD_CHUNKS || count < 0) {
  532. IL_ERR("Error can not send more than %d chunks\n",
  533. NUM_TFD_CHUNKS);
  534. return -EINVAL;
  535. }
  536. tfd->tbs[count].addr = cpu_to_le32(addr);
  537. tfd->tbs[count].len = cpu_to_le32(len);
  538. count++;
  539. tfd->control_flags = cpu_to_le32(TFD_CTL_COUNT_SET(count) |
  540. TFD_CTL_PAD_SET(pad));
  541. return 0;
  542. }
  543. /**
  544. * il3945_hw_txq_free_tfd - Free one TFD, those at idx [txq->q.read_ptr]
  545. *
  546. * Does NOT advance any idxes
  547. */
  548. void il3945_hw_txq_free_tfd(struct il_priv *il, struct il_tx_queue *txq)
  549. {
  550. struct il3945_tfd *tfd_tmp = (struct il3945_tfd *)txq->tfds;
  551. int idx = txq->q.read_ptr;
  552. struct il3945_tfd *tfd = &tfd_tmp[idx];
  553. struct pci_dev *dev = il->pci_dev;
  554. int i;
  555. int counter;
  556. /* sanity check */
  557. counter = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
  558. if (counter > NUM_TFD_CHUNKS) {
  559. IL_ERR("Too many chunks: %i\n", counter);
  560. /* @todo issue fatal error, it is quite serious situation */
  561. return;
  562. }
  563. /* Unmap tx_cmd */
  564. if (counter)
  565. pci_unmap_single(dev,
  566. dma_unmap_addr(&txq->meta[idx], mapping),
  567. dma_unmap_len(&txq->meta[idx], len),
  568. PCI_DMA_TODEVICE);
  569. /* unmap chunks if any */
  570. for (i = 1; i < counter; i++)
  571. pci_unmap_single(dev, le32_to_cpu(tfd->tbs[i].addr),
  572. le32_to_cpu(tfd->tbs[i].len), PCI_DMA_TODEVICE);
  573. /* free SKB */
  574. if (txq->txb) {
  575. struct sk_buff *skb;
  576. skb = txq->txb[txq->q.read_ptr].skb;
  577. /* can be called from irqs-disabled context */
  578. if (skb) {
  579. dev_kfree_skb_any(skb);
  580. txq->txb[txq->q.read_ptr].skb = NULL;
  581. }
  582. }
  583. }
  584. /**
  585. * il3945_hw_build_tx_cmd_rate - Add rate portion to TX_CMD:
  586. *
  587. */
  588. void il3945_hw_build_tx_cmd_rate(struct il_priv *il,
  589. struct il_device_cmd *cmd,
  590. struct ieee80211_tx_info *info,
  591. struct ieee80211_hdr *hdr,
  592. int sta_id, int tx_id)
  593. {
  594. u16 hw_value = ieee80211_get_tx_rate(il->hw, info)->hw_value;
  595. u16 rate_idx = min(hw_value & 0xffff, RATE_COUNT_3945);
  596. u16 rate_mask;
  597. int rate;
  598. u8 rts_retry_limit;
  599. u8 data_retry_limit;
  600. __le32 tx_flags;
  601. __le16 fc = hdr->frame_control;
  602. struct il3945_tx_cmd *tx_cmd = (struct il3945_tx_cmd *)cmd->cmd.payload;
  603. rate = il3945_rates[rate_idx].plcp;
  604. tx_flags = tx_cmd->tx_flags;
  605. /* We need to figure out how to get the sta->supp_rates while
  606. * in this running context */
  607. rate_mask = RATES_MASK_3945;
  608. /* Set retry limit on DATA packets and Probe Responses*/
  609. if (ieee80211_is_probe_resp(fc))
  610. data_retry_limit = 3;
  611. else
  612. data_retry_limit = IL_DEFAULT_TX_RETRY;
  613. tx_cmd->data_retry_limit = data_retry_limit;
  614. if (tx_id >= IL39_CMD_QUEUE_NUM)
  615. rts_retry_limit = 3;
  616. else
  617. rts_retry_limit = 7;
  618. if (data_retry_limit < rts_retry_limit)
  619. rts_retry_limit = data_retry_limit;
  620. tx_cmd->rts_retry_limit = rts_retry_limit;
  621. tx_cmd->rate = rate;
  622. tx_cmd->tx_flags = tx_flags;
  623. /* OFDM */
  624. tx_cmd->supp_rates[0] =
  625. ((rate_mask & IL_OFDM_RATES_MASK) >> IL_FIRST_OFDM_RATE) & 0xFF;
  626. /* CCK */
  627. tx_cmd->supp_rates[1] = (rate_mask & 0xF);
  628. D_RATE("Tx sta id: %d, rate: %d (plcp), flags: 0x%4X "
  629. "cck/ofdm mask: 0x%x/0x%x\n", sta_id,
  630. tx_cmd->rate, le32_to_cpu(tx_cmd->tx_flags),
  631. tx_cmd->supp_rates[1], tx_cmd->supp_rates[0]);
  632. }
  633. static u8 il3945_sync_sta(struct il_priv *il, int sta_id, u16 tx_rate)
  634. {
  635. unsigned long flags_spin;
  636. struct il_station_entry *station;
  637. if (sta_id == IL_INVALID_STATION)
  638. return IL_INVALID_STATION;
  639. spin_lock_irqsave(&il->sta_lock, flags_spin);
  640. station = &il->stations[sta_id];
  641. station->sta.sta.modify_mask = STA_MODIFY_TX_RATE_MSK;
  642. station->sta.rate_n_flags = cpu_to_le16(tx_rate);
  643. station->sta.mode = STA_CONTROL_MODIFY_MSK;
  644. il_send_add_sta(il, &station->sta, CMD_ASYNC);
  645. spin_unlock_irqrestore(&il->sta_lock, flags_spin);
  646. D_RATE("SCALE sync station %d to rate %d\n",
  647. sta_id, tx_rate);
  648. return sta_id;
  649. }
  650. static void il3945_set_pwr_vmain(struct il_priv *il)
  651. {
  652. /*
  653. * (for documentation purposes)
  654. * to set power to V_AUX, do
  655. if (pci_pme_capable(il->pci_dev, PCI_D3cold)) {
  656. il_set_bits_mask_prph(il, APMG_PS_CTRL_REG,
  657. APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
  658. ~APMG_PS_CTRL_MSK_PWR_SRC);
  659. _il_poll_bit(il, CSR_GPIO_IN,
  660. CSR_GPIO_IN_VAL_VAUX_PWR_SRC,
  661. CSR_GPIO_IN_BIT_AUX_POWER, 5000);
  662. }
  663. */
  664. il_set_bits_mask_prph(il, APMG_PS_CTRL_REG,
  665. APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
  666. ~APMG_PS_CTRL_MSK_PWR_SRC);
  667. _il_poll_bit(il, CSR_GPIO_IN, CSR_GPIO_IN_VAL_VMAIN_PWR_SRC,
  668. CSR_GPIO_IN_BIT_AUX_POWER, 5000); /* uS */
  669. }
  670. static int il3945_rx_init(struct il_priv *il, struct il_rx_queue *rxq)
  671. {
  672. il_wr(il, FH39_RCSR_RBD_BASE(0), rxq->bd_dma);
  673. il_wr(il, FH39_RCSR_RPTR_ADDR(0),
  674. rxq->rb_stts_dma);
  675. il_wr(il, FH39_RCSR_WPTR(0), 0);
  676. il_wr(il, FH39_RCSR_CONFIG(0),
  677. FH39_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE |
  678. FH39_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE |
  679. FH39_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN |
  680. FH39_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 |
  681. (RX_QUEUE_SIZE_LOG << FH39_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE) |
  682. FH39_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST |
  683. (1 << FH39_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH) |
  684. FH39_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH);
  685. /* fake read to flush all prev I/O */
  686. il_rd(il, FH39_RSSR_CTRL);
  687. return 0;
  688. }
  689. static int il3945_tx_reset(struct il_priv *il)
  690. {
  691. /* bypass mode */
  692. il_wr_prph(il, ALM_SCD_MODE_REG, 0x2);
  693. /* RA 0 is active */
  694. il_wr_prph(il, ALM_SCD_ARASTAT_REG, 0x01);
  695. /* all 6 fifo are active */
  696. il_wr_prph(il, ALM_SCD_TXFACT_REG, 0x3f);
  697. il_wr_prph(il, ALM_SCD_SBYP_MODE_1_REG, 0x010000);
  698. il_wr_prph(il, ALM_SCD_SBYP_MODE_2_REG, 0x030002);
  699. il_wr_prph(il, ALM_SCD_TXF4MF_REG, 0x000004);
  700. il_wr_prph(il, ALM_SCD_TXF5MF_REG, 0x000005);
  701. il_wr(il, FH39_TSSR_CBB_BASE,
  702. il->_3945.shared_phys);
  703. il_wr(il, FH39_TSSR_MSG_CONFIG,
  704. FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON |
  705. FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON |
  706. FH39_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B |
  707. FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON |
  708. FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON |
  709. FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH |
  710. FH39_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH);
  711. return 0;
  712. }
  713. /**
  714. * il3945_txq_ctx_reset - Reset TX queue context
  715. *
  716. * Destroys all DMA structures and initialize them again
  717. */
  718. static int il3945_txq_ctx_reset(struct il_priv *il)
  719. {
  720. int rc;
  721. int txq_id, slots_num;
  722. il3945_hw_txq_ctx_free(il);
  723. /* allocate tx queue structure */
  724. rc = il_alloc_txq_mem(il);
  725. if (rc)
  726. return rc;
  727. /* Tx CMD queue */
  728. rc = il3945_tx_reset(il);
  729. if (rc)
  730. goto error;
  731. /* Tx queue(s) */
  732. for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++) {
  733. slots_num = (txq_id == IL39_CMD_QUEUE_NUM) ?
  734. TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
  735. rc = il_tx_queue_init(il, &il->txq[txq_id],
  736. slots_num, txq_id);
  737. if (rc) {
  738. IL_ERR("Tx %d queue init failed\n", txq_id);
  739. goto error;
  740. }
  741. }
  742. return rc;
  743. error:
  744. il3945_hw_txq_ctx_free(il);
  745. return rc;
  746. }
  747. /*
  748. * Start up 3945's basic functionality after it has been reset
  749. * (e.g. after platform boot, or shutdown via il_apm_stop())
  750. * NOTE: This does not load uCode nor start the embedded processor
  751. */
  752. static int il3945_apm_init(struct il_priv *il)
  753. {
  754. int ret = il_apm_init(il);
  755. /* Clear APMG (NIC's internal power management) interrupts */
  756. il_wr_prph(il, APMG_RTC_INT_MSK_REG, 0x0);
  757. il_wr_prph(il, APMG_RTC_INT_STT_REG, 0xFFFFFFFF);
  758. /* Reset radio chip */
  759. il_set_bits_prph(il, APMG_PS_CTRL_REG,
  760. APMG_PS_CTRL_VAL_RESET_REQ);
  761. udelay(5);
  762. il_clear_bits_prph(il, APMG_PS_CTRL_REG,
  763. APMG_PS_CTRL_VAL_RESET_REQ);
  764. return ret;
  765. }
  766. static void il3945_nic_config(struct il_priv *il)
  767. {
  768. struct il3945_eeprom *eeprom = (struct il3945_eeprom *)il->eeprom;
  769. unsigned long flags;
  770. u8 rev_id = il->pci_dev->revision;
  771. spin_lock_irqsave(&il->lock, flags);
  772. /* Determine HW type */
  773. D_INFO("HW Revision ID = 0x%X\n", rev_id);
  774. if (rev_id & PCI_CFG_REV_ID_BIT_RTP)
  775. D_INFO("RTP type\n");
  776. else if (rev_id & PCI_CFG_REV_ID_BIT_BASIC_SKU) {
  777. D_INFO("3945 RADIO-MB type\n");
  778. il_set_bit(il, CSR_HW_IF_CONFIG_REG,
  779. CSR39_HW_IF_CONFIG_REG_BIT_3945_MB);
  780. } else {
  781. D_INFO("3945 RADIO-MM type\n");
  782. il_set_bit(il, CSR_HW_IF_CONFIG_REG,
  783. CSR39_HW_IF_CONFIG_REG_BIT_3945_MM);
  784. }
  785. if (EEPROM_SKU_CAP_OP_MODE_MRC == eeprom->sku_cap) {
  786. D_INFO("SKU OP mode is mrc\n");
  787. il_set_bit(il, CSR_HW_IF_CONFIG_REG,
  788. CSR39_HW_IF_CONFIG_REG_BIT_SKU_MRC);
  789. } else
  790. D_INFO("SKU OP mode is basic\n");
  791. if ((eeprom->board_revision & 0xF0) == 0xD0) {
  792. D_INFO("3945ABG revision is 0x%X\n",
  793. eeprom->board_revision);
  794. il_set_bit(il, CSR_HW_IF_CONFIG_REG,
  795. CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
  796. } else {
  797. D_INFO("3945ABG revision is 0x%X\n",
  798. eeprom->board_revision);
  799. il_clear_bit(il, CSR_HW_IF_CONFIG_REG,
  800. CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
  801. }
  802. if (eeprom->almgor_m_version <= 1) {
  803. il_set_bit(il, CSR_HW_IF_CONFIG_REG,
  804. CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A);
  805. D_INFO("Card M type A version is 0x%X\n",
  806. eeprom->almgor_m_version);
  807. } else {
  808. D_INFO("Card M type B version is 0x%X\n",
  809. eeprom->almgor_m_version);
  810. il_set_bit(il, CSR_HW_IF_CONFIG_REG,
  811. CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B);
  812. }
  813. spin_unlock_irqrestore(&il->lock, flags);
  814. if (eeprom->sku_cap & EEPROM_SKU_CAP_SW_RF_KILL_ENABLE)
  815. D_RF_KILL("SW RF KILL supported in EEPROM.\n");
  816. if (eeprom->sku_cap & EEPROM_SKU_CAP_HW_RF_KILL_ENABLE)
  817. D_RF_KILL("HW RF KILL supported in EEPROM.\n");
  818. }
  819. int il3945_hw_nic_init(struct il_priv *il)
  820. {
  821. int rc;
  822. unsigned long flags;
  823. struct il_rx_queue *rxq = &il->rxq;
  824. spin_lock_irqsave(&il->lock, flags);
  825. il->cfg->ops->lib->apm_ops.init(il);
  826. spin_unlock_irqrestore(&il->lock, flags);
  827. il3945_set_pwr_vmain(il);
  828. il->cfg->ops->lib->apm_ops.config(il);
  829. /* Allocate the RX queue, or reset if it is already allocated */
  830. if (!rxq->bd) {
  831. rc = il_rx_queue_alloc(il);
  832. if (rc) {
  833. IL_ERR("Unable to initialize Rx queue\n");
  834. return -ENOMEM;
  835. }
  836. } else
  837. il3945_rx_queue_reset(il, rxq);
  838. il3945_rx_replenish(il);
  839. il3945_rx_init(il, rxq);
  840. /* Look at using this instead:
  841. rxq->need_update = 1;
  842. il_rx_queue_update_write_ptr(il, rxq);
  843. */
  844. il_wr(il, FH39_RCSR_WPTR(0), rxq->write & ~7);
  845. rc = il3945_txq_ctx_reset(il);
  846. if (rc)
  847. return rc;
  848. set_bit(S_INIT, &il->status);
  849. return 0;
  850. }
  851. /**
  852. * il3945_hw_txq_ctx_free - Free TXQ Context
  853. *
  854. * Destroy all TX DMA queues and structures
  855. */
  856. void il3945_hw_txq_ctx_free(struct il_priv *il)
  857. {
  858. int txq_id;
  859. /* Tx queues */
  860. if (il->txq)
  861. for (txq_id = 0; txq_id < il->hw_params.max_txq_num;
  862. txq_id++)
  863. if (txq_id == IL39_CMD_QUEUE_NUM)
  864. il_cmd_queue_free(il);
  865. else
  866. il_tx_queue_free(il, txq_id);
  867. /* free tx queue structure */
  868. il_txq_mem(il);
  869. }
  870. void il3945_hw_txq_ctx_stop(struct il_priv *il)
  871. {
  872. int txq_id;
  873. /* stop SCD */
  874. il_wr_prph(il, ALM_SCD_MODE_REG, 0);
  875. il_wr_prph(il, ALM_SCD_TXFACT_REG, 0);
  876. /* reset TFD queues */
  877. for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++) {
  878. il_wr(il, FH39_TCSR_CONFIG(txq_id), 0x0);
  879. il_poll_bit(il, FH39_TSSR_TX_STATUS,
  880. FH39_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(txq_id),
  881. 1000);
  882. }
  883. il3945_hw_txq_ctx_free(il);
  884. }
  885. /**
  886. * il3945_hw_reg_adjust_power_by_temp
  887. * return idx delta into power gain settings table
  888. */
  889. static int il3945_hw_reg_adjust_power_by_temp(int new_reading, int old_reading)
  890. {
  891. return (new_reading - old_reading) * (-11) / 100;
  892. }
  893. /**
  894. * il3945_hw_reg_temp_out_of_range - Keep temperature in sane range
  895. */
  896. static inline int il3945_hw_reg_temp_out_of_range(int temperature)
  897. {
  898. return (temperature < -260 || temperature > 25) ? 1 : 0;
  899. }
  900. int il3945_hw_get_temperature(struct il_priv *il)
  901. {
  902. return _il_rd(il, CSR_UCODE_DRV_GP2);
  903. }
  904. /**
  905. * il3945_hw_reg_txpower_get_temperature
  906. * get the current temperature by reading from NIC
  907. */
  908. static int il3945_hw_reg_txpower_get_temperature(struct il_priv *il)
  909. {
  910. struct il3945_eeprom *eeprom = (struct il3945_eeprom *)il->eeprom;
  911. int temperature;
  912. temperature = il3945_hw_get_temperature(il);
  913. /* driver's okay range is -260 to +25.
  914. * human readable okay range is 0 to +285 */
  915. D_INFO("Temperature: %d\n", temperature + IL_TEMP_CONVERT);
  916. /* handle insane temp reading */
  917. if (il3945_hw_reg_temp_out_of_range(temperature)) {
  918. IL_ERR("Error bad temperature value %d\n", temperature);
  919. /* if really really hot(?),
  920. * substitute the 3rd band/group's temp measured at factory */
  921. if (il->last_temperature > 100)
  922. temperature = eeprom->groups[2].temperature;
  923. else /* else use most recent "sane" value from driver */
  924. temperature = il->last_temperature;
  925. }
  926. return temperature; /* raw, not "human readable" */
  927. }
  928. /* Adjust Txpower only if temperature variance is greater than threshold.
  929. *
  930. * Both are lower than older versions' 9 degrees */
  931. #define IL_TEMPERATURE_LIMIT_TIMER 6
  932. /**
  933. * il3945_is_temp_calib_needed - determines if new calibration is needed
  934. *
  935. * records new temperature in tx_mgr->temperature.
  936. * replaces tx_mgr->last_temperature *only* if calib needed
  937. * (assumes caller will actually do the calibration!). */
  938. static int il3945_is_temp_calib_needed(struct il_priv *il)
  939. {
  940. int temp_diff;
  941. il->temperature = il3945_hw_reg_txpower_get_temperature(il);
  942. temp_diff = il->temperature - il->last_temperature;
  943. /* get absolute value */
  944. if (temp_diff < 0) {
  945. D_POWER("Getting cooler, delta %d,\n", temp_diff);
  946. temp_diff = -temp_diff;
  947. } else if (temp_diff == 0)
  948. D_POWER("Same temp,\n");
  949. else
  950. D_POWER("Getting warmer, delta %d,\n", temp_diff);
  951. /* if we don't need calibration, *don't* update last_temperature */
  952. if (temp_diff < IL_TEMPERATURE_LIMIT_TIMER) {
  953. D_POWER("Timed thermal calib not needed\n");
  954. return 0;
  955. }
  956. D_POWER("Timed thermal calib needed\n");
  957. /* assume that caller will actually do calib ...
  958. * update the "last temperature" value */
  959. il->last_temperature = il->temperature;
  960. return 1;
  961. }
  962. #define IL_MAX_GAIN_ENTRIES 78
  963. #define IL_CCK_FROM_OFDM_POWER_DIFF -5
  964. #define IL_CCK_FROM_OFDM_IDX_DIFF (10)
  965. /* radio and DSP power table, each step is 1/2 dB.
  966. * 1st number is for RF analog gain, 2nd number is for DSP pre-DAC gain. */
  967. static struct il3945_tx_power power_gain_table[2][IL_MAX_GAIN_ENTRIES] = {
  968. {
  969. {251, 127}, /* 2.4 GHz, highest power */
  970. {251, 127},
  971. {251, 127},
  972. {251, 127},
  973. {251, 125},
  974. {251, 110},
  975. {251, 105},
  976. {251, 98},
  977. {187, 125},
  978. {187, 115},
  979. {187, 108},
  980. {187, 99},
  981. {243, 119},
  982. {243, 111},
  983. {243, 105},
  984. {243, 97},
  985. {243, 92},
  986. {211, 106},
  987. {211, 100},
  988. {179, 120},
  989. {179, 113},
  990. {179, 107},
  991. {147, 125},
  992. {147, 119},
  993. {147, 112},
  994. {147, 106},
  995. {147, 101},
  996. {147, 97},
  997. {147, 91},
  998. {115, 107},
  999. {235, 121},
  1000. {235, 115},
  1001. {235, 109},
  1002. {203, 127},
  1003. {203, 121},
  1004. {203, 115},
  1005. {203, 108},
  1006. {203, 102},
  1007. {203, 96},
  1008. {203, 92},
  1009. {171, 110},
  1010. {171, 104},
  1011. {171, 98},
  1012. {139, 116},
  1013. {227, 125},
  1014. {227, 119},
  1015. {227, 113},
  1016. {227, 107},
  1017. {227, 101},
  1018. {227, 96},
  1019. {195, 113},
  1020. {195, 106},
  1021. {195, 102},
  1022. {195, 95},
  1023. {163, 113},
  1024. {163, 106},
  1025. {163, 102},
  1026. {163, 95},
  1027. {131, 113},
  1028. {131, 106},
  1029. {131, 102},
  1030. {131, 95},
  1031. {99, 113},
  1032. {99, 106},
  1033. {99, 102},
  1034. {99, 95},
  1035. {67, 113},
  1036. {67, 106},
  1037. {67, 102},
  1038. {67, 95},
  1039. {35, 113},
  1040. {35, 106},
  1041. {35, 102},
  1042. {35, 95},
  1043. {3, 113},
  1044. {3, 106},
  1045. {3, 102},
  1046. {3, 95} }, /* 2.4 GHz, lowest power */
  1047. {
  1048. {251, 127}, /* 5.x GHz, highest power */
  1049. {251, 120},
  1050. {251, 114},
  1051. {219, 119},
  1052. {219, 101},
  1053. {187, 113},
  1054. {187, 102},
  1055. {155, 114},
  1056. {155, 103},
  1057. {123, 117},
  1058. {123, 107},
  1059. {123, 99},
  1060. {123, 92},
  1061. {91, 108},
  1062. {59, 125},
  1063. {59, 118},
  1064. {59, 109},
  1065. {59, 102},
  1066. {59, 96},
  1067. {59, 90},
  1068. {27, 104},
  1069. {27, 98},
  1070. {27, 92},
  1071. {115, 118},
  1072. {115, 111},
  1073. {115, 104},
  1074. {83, 126},
  1075. {83, 121},
  1076. {83, 113},
  1077. {83, 105},
  1078. {83, 99},
  1079. {51, 118},
  1080. {51, 111},
  1081. {51, 104},
  1082. {51, 98},
  1083. {19, 116},
  1084. {19, 109},
  1085. {19, 102},
  1086. {19, 98},
  1087. {19, 93},
  1088. {171, 113},
  1089. {171, 107},
  1090. {171, 99},
  1091. {139, 120},
  1092. {139, 113},
  1093. {139, 107},
  1094. {139, 99},
  1095. {107, 120},
  1096. {107, 113},
  1097. {107, 107},
  1098. {107, 99},
  1099. {75, 120},
  1100. {75, 113},
  1101. {75, 107},
  1102. {75, 99},
  1103. {43, 120},
  1104. {43, 113},
  1105. {43, 107},
  1106. {43, 99},
  1107. {11, 120},
  1108. {11, 113},
  1109. {11, 107},
  1110. {11, 99},
  1111. {131, 107},
  1112. {131, 99},
  1113. {99, 120},
  1114. {99, 113},
  1115. {99, 107},
  1116. {99, 99},
  1117. {67, 120},
  1118. {67, 113},
  1119. {67, 107},
  1120. {67, 99},
  1121. {35, 120},
  1122. {35, 113},
  1123. {35, 107},
  1124. {35, 99},
  1125. {3, 120} } /* 5.x GHz, lowest power */
  1126. };
  1127. static inline u8 il3945_hw_reg_fix_power_idx(int idx)
  1128. {
  1129. if (idx < 0)
  1130. return 0;
  1131. if (idx >= IL_MAX_GAIN_ENTRIES)
  1132. return IL_MAX_GAIN_ENTRIES - 1;
  1133. return (u8) idx;
  1134. }
  1135. /* Kick off thermal recalibration check every 60 seconds */
  1136. #define REG_RECALIB_PERIOD (60)
  1137. /**
  1138. * il3945_hw_reg_set_scan_power - Set Tx power for scan probe requests
  1139. *
  1140. * Set (in our channel info database) the direct scan Tx power for 1 Mbit (CCK)
  1141. * or 6 Mbit (OFDM) rates.
  1142. */
  1143. static void il3945_hw_reg_set_scan_power(struct il_priv *il, u32 scan_tbl_idx,
  1144. s32 rate_idx, const s8 *clip_pwrs,
  1145. struct il_channel_info *ch_info,
  1146. int band_idx)
  1147. {
  1148. struct il3945_scan_power_info *scan_power_info;
  1149. s8 power;
  1150. u8 power_idx;
  1151. scan_power_info = &ch_info->scan_pwr_info[scan_tbl_idx];
  1152. /* use this channel group's 6Mbit clipping/saturation pwr,
  1153. * but cap at regulatory scan power restriction (set during init
  1154. * based on eeprom channel data) for this channel. */
  1155. power = min(ch_info->scan_power, clip_pwrs[RATE_6M_IDX_TBL]);
  1156. power = min(power, il->tx_power_user_lmt);
  1157. scan_power_info->requested_power = power;
  1158. /* find difference between new scan *power* and current "normal"
  1159. * Tx *power* for 6Mb. Use this difference (x2) to adjust the
  1160. * current "normal" temperature-compensated Tx power *idx* for
  1161. * this rate (1Mb or 6Mb) to yield new temp-compensated scan power
  1162. * *idx*. */
  1163. power_idx = ch_info->power_info[rate_idx].power_table_idx
  1164. - (power - ch_info->power_info
  1165. [RATE_6M_IDX_TBL].requested_power) * 2;
  1166. /* store reference idx that we use when adjusting *all* scan
  1167. * powers. So we can accommodate user (all channel) or spectrum
  1168. * management (single channel) power changes "between" temperature
  1169. * feedback compensation procedures.
  1170. * don't force fit this reference idx into gain table; it may be a
  1171. * negative number. This will help avoid errors when we're at
  1172. * the lower bounds (highest gains, for warmest temperatures)
  1173. * of the table. */
  1174. /* don't exceed table bounds for "real" setting */
  1175. power_idx = il3945_hw_reg_fix_power_idx(power_idx);
  1176. scan_power_info->power_table_idx = power_idx;
  1177. scan_power_info->tpc.tx_gain =
  1178. power_gain_table[band_idx][power_idx].tx_gain;
  1179. scan_power_info->tpc.dsp_atten =
  1180. power_gain_table[band_idx][power_idx].dsp_atten;
  1181. }
  1182. /**
  1183. * il3945_send_tx_power - fill in Tx Power command with gain settings
  1184. *
  1185. * Configures power settings for all rates for the current channel,
  1186. * using values from channel info struct, and send to NIC
  1187. */
  1188. static int il3945_send_tx_power(struct il_priv *il)
  1189. {
  1190. int rate_idx, i;
  1191. const struct il_channel_info *ch_info = NULL;
  1192. struct il3945_txpowertable_cmd txpower = {
  1193. .channel = il->ctx.active.channel,
  1194. };
  1195. u16 chan;
  1196. if (WARN_ONCE(test_bit(S_SCAN_HW, &il->status),
  1197. "TX Power requested while scanning!\n"))
  1198. return -EAGAIN;
  1199. chan = le16_to_cpu(il->ctx.active.channel);
  1200. txpower.band = (il->band == IEEE80211_BAND_5GHZ) ? 0 : 1;
  1201. ch_info = il_get_channel_info(il, il->band, chan);
  1202. if (!ch_info) {
  1203. IL_ERR(
  1204. "Failed to get channel info for channel %d [%d]\n",
  1205. chan, il->band);
  1206. return -EINVAL;
  1207. }
  1208. if (!il_is_channel_valid(ch_info)) {
  1209. D_POWER("Not calling TX_PWR_TBL_CMD on "
  1210. "non-Tx channel.\n");
  1211. return 0;
  1212. }
  1213. /* fill cmd with power settings for all rates for current channel */
  1214. /* Fill OFDM rate */
  1215. for (rate_idx = IL_FIRST_OFDM_RATE, i = 0;
  1216. rate_idx <= IL39_LAST_OFDM_RATE; rate_idx++, i++) {
  1217. txpower.power[i].tpc = ch_info->power_info[i].tpc;
  1218. txpower.power[i].rate = il3945_rates[rate_idx].plcp;
  1219. D_POWER("ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
  1220. le16_to_cpu(txpower.channel),
  1221. txpower.band,
  1222. txpower.power[i].tpc.tx_gain,
  1223. txpower.power[i].tpc.dsp_atten,
  1224. txpower.power[i].rate);
  1225. }
  1226. /* Fill CCK rates */
  1227. for (rate_idx = IL_FIRST_CCK_RATE;
  1228. rate_idx <= IL_LAST_CCK_RATE; rate_idx++, i++) {
  1229. txpower.power[i].tpc = ch_info->power_info[i].tpc;
  1230. txpower.power[i].rate = il3945_rates[rate_idx].plcp;
  1231. D_POWER("ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
  1232. le16_to_cpu(txpower.channel),
  1233. txpower.band,
  1234. txpower.power[i].tpc.tx_gain,
  1235. txpower.power[i].tpc.dsp_atten,
  1236. txpower.power[i].rate);
  1237. }
  1238. return il_send_cmd_pdu(il, REPLY_TX_PWR_TBL_CMD,
  1239. sizeof(struct il3945_txpowertable_cmd),
  1240. &txpower);
  1241. }
  1242. /**
  1243. * il3945_hw_reg_set_new_power - Configures power tables at new levels
  1244. * @ch_info: Channel to update. Uses power_info.requested_power.
  1245. *
  1246. * Replace requested_power and base_power_idx ch_info fields for
  1247. * one channel.
  1248. *
  1249. * Called if user or spectrum management changes power preferences.
  1250. * Takes into account h/w and modulation limitations (clip power).
  1251. *
  1252. * This does *not* send anything to NIC, just sets up ch_info for one channel.
  1253. *
  1254. * NOTE: reg_compensate_for_temperature_dif() *must* be run after this to
  1255. * properly fill out the scan powers, and actual h/w gain settings,
  1256. * and send changes to NIC
  1257. */
  1258. static int il3945_hw_reg_set_new_power(struct il_priv *il,
  1259. struct il_channel_info *ch_info)
  1260. {
  1261. struct il3945_channel_power_info *power_info;
  1262. int power_changed = 0;
  1263. int i;
  1264. const s8 *clip_pwrs;
  1265. int power;
  1266. /* Get this chnlgrp's rate-to-max/clip-powers table */
  1267. clip_pwrs = il->_3945.clip_groups[ch_info->group_idx].clip_powers;
  1268. /* Get this channel's rate-to-current-power settings table */
  1269. power_info = ch_info->power_info;
  1270. /* update OFDM Txpower settings */
  1271. for (i = RATE_6M_IDX_TBL; i <= RATE_54M_IDX_TBL;
  1272. i++, ++power_info) {
  1273. int delta_idx;
  1274. /* limit new power to be no more than h/w capability */
  1275. power = min(ch_info->curr_txpow, clip_pwrs[i]);
  1276. if (power == power_info->requested_power)
  1277. continue;
  1278. /* find difference between old and new requested powers,
  1279. * update base (non-temp-compensated) power idx */
  1280. delta_idx = (power - power_info->requested_power) * 2;
  1281. power_info->base_power_idx -= delta_idx;
  1282. /* save new requested power value */
  1283. power_info->requested_power = power;
  1284. power_changed = 1;
  1285. }
  1286. /* update CCK Txpower settings, based on OFDM 12M setting ...
  1287. * ... all CCK power settings for a given channel are the *same*. */
  1288. if (power_changed) {
  1289. power =
  1290. ch_info->power_info[RATE_12M_IDX_TBL].
  1291. requested_power + IL_CCK_FROM_OFDM_POWER_DIFF;
  1292. /* do all CCK rates' il3945_channel_power_info structures */
  1293. for (i = RATE_1M_IDX_TBL; i <= RATE_11M_IDX_TBL; i++) {
  1294. power_info->requested_power = power;
  1295. power_info->base_power_idx =
  1296. ch_info->power_info[RATE_12M_IDX_TBL].
  1297. base_power_idx + IL_CCK_FROM_OFDM_IDX_DIFF;
  1298. ++power_info;
  1299. }
  1300. }
  1301. return 0;
  1302. }
  1303. /**
  1304. * il3945_hw_reg_get_ch_txpower_limit - returns new power limit for channel
  1305. *
  1306. * NOTE: Returned power limit may be less (but not more) than requested,
  1307. * based strictly on regulatory (eeprom and spectrum mgt) limitations
  1308. * (no consideration for h/w clipping limitations).
  1309. */
  1310. static int il3945_hw_reg_get_ch_txpower_limit(struct il_channel_info *ch_info)
  1311. {
  1312. s8 max_power;
  1313. #if 0
  1314. /* if we're using TGd limits, use lower of TGd or EEPROM */
  1315. if (ch_info->tgd_data.max_power != 0)
  1316. max_power = min(ch_info->tgd_data.max_power,
  1317. ch_info->eeprom.max_power_avg);
  1318. /* else just use EEPROM limits */
  1319. else
  1320. #endif
  1321. max_power = ch_info->eeprom.max_power_avg;
  1322. return min(max_power, ch_info->max_power_avg);
  1323. }
  1324. /**
  1325. * il3945_hw_reg_comp_txpower_temp - Compensate for temperature
  1326. *
  1327. * Compensate txpower settings of *all* channels for temperature.
  1328. * This only accounts for the difference between current temperature
  1329. * and the factory calibration temperatures, and bases the new settings
  1330. * on the channel's base_power_idx.
  1331. *
  1332. * If RxOn is "associated", this sends the new Txpower to NIC!
  1333. */
  1334. static int il3945_hw_reg_comp_txpower_temp(struct il_priv *il)
  1335. {
  1336. struct il_channel_info *ch_info = NULL;
  1337. struct il3945_eeprom *eeprom = (struct il3945_eeprom *)il->eeprom;
  1338. int delta_idx;
  1339. const s8 *clip_pwrs; /* array of h/w max power levels for each rate */
  1340. u8 a_band;
  1341. u8 rate_idx;
  1342. u8 scan_tbl_idx;
  1343. u8 i;
  1344. int ref_temp;
  1345. int temperature = il->temperature;
  1346. if (il->disable_tx_power_cal ||
  1347. test_bit(S_SCANNING, &il->status)) {
  1348. /* do not perform tx power calibration */
  1349. return 0;
  1350. }
  1351. /* set up new Tx power info for each and every channel, 2.4 and 5.x */
  1352. for (i = 0; i < il->channel_count; i++) {
  1353. ch_info = &il->channel_info[i];
  1354. a_band = il_is_channel_a_band(ch_info);
  1355. /* Get this chnlgrp's factory calibration temperature */
  1356. ref_temp = (s16)eeprom->groups[ch_info->group_idx].
  1357. temperature;
  1358. /* get power idx adjustment based on current and factory
  1359. * temps */
  1360. delta_idx = il3945_hw_reg_adjust_power_by_temp(temperature,
  1361. ref_temp);
  1362. /* set tx power value for all rates, OFDM and CCK */
  1363. for (rate_idx = 0; rate_idx < RATE_COUNT_3945;
  1364. rate_idx++) {
  1365. int power_idx =
  1366. ch_info->power_info[rate_idx].base_power_idx;
  1367. /* temperature compensate */
  1368. power_idx += delta_idx;
  1369. /* stay within table range */
  1370. power_idx = il3945_hw_reg_fix_power_idx(power_idx);
  1371. ch_info->power_info[rate_idx].
  1372. power_table_idx = (u8) power_idx;
  1373. ch_info->power_info[rate_idx].tpc =
  1374. power_gain_table[a_band][power_idx];
  1375. }
  1376. /* Get this chnlgrp's rate-to-max/clip-powers table */
  1377. clip_pwrs = il->_3945.clip_groups[ch_info->group_idx].clip_powers;
  1378. /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
  1379. for (scan_tbl_idx = 0;
  1380. scan_tbl_idx < IL_NUM_SCAN_RATES; scan_tbl_idx++) {
  1381. s32 actual_idx = (scan_tbl_idx == 0) ?
  1382. RATE_1M_IDX_TBL : RATE_6M_IDX_TBL;
  1383. il3945_hw_reg_set_scan_power(il, scan_tbl_idx,
  1384. actual_idx, clip_pwrs,
  1385. ch_info, a_band);
  1386. }
  1387. }
  1388. /* send Txpower command for current channel to ucode */
  1389. return il->cfg->ops->lib->send_tx_power(il);
  1390. }
  1391. int il3945_hw_reg_set_txpower(struct il_priv *il, s8 power)
  1392. {
  1393. struct il_channel_info *ch_info;
  1394. s8 max_power;
  1395. u8 a_band;
  1396. u8 i;
  1397. if (il->tx_power_user_lmt == power) {
  1398. D_POWER("Requested Tx power same as current "
  1399. "limit: %ddBm.\n", power);
  1400. return 0;
  1401. }
  1402. D_POWER("Setting upper limit clamp to %ddBm.\n", power);
  1403. il->tx_power_user_lmt = power;
  1404. /* set up new Tx powers for each and every channel, 2.4 and 5.x */
  1405. for (i = 0; i < il->channel_count; i++) {
  1406. ch_info = &il->channel_info[i];
  1407. a_band = il_is_channel_a_band(ch_info);
  1408. /* find minimum power of all user and regulatory constraints
  1409. * (does not consider h/w clipping limitations) */
  1410. max_power = il3945_hw_reg_get_ch_txpower_limit(ch_info);
  1411. max_power = min(power, max_power);
  1412. if (max_power != ch_info->curr_txpow) {
  1413. ch_info->curr_txpow = max_power;
  1414. /* this considers the h/w clipping limitations */
  1415. il3945_hw_reg_set_new_power(il, ch_info);
  1416. }
  1417. }
  1418. /* update txpower settings for all channels,
  1419. * send to NIC if associated. */
  1420. il3945_is_temp_calib_needed(il);
  1421. il3945_hw_reg_comp_txpower_temp(il);
  1422. return 0;
  1423. }
  1424. static int il3945_send_rxon_assoc(struct il_priv *il,
  1425. struct il_rxon_context *ctx)
  1426. {
  1427. int rc = 0;
  1428. struct il_rx_pkt *pkt;
  1429. struct il3945_rxon_assoc_cmd rxon_assoc;
  1430. struct il_host_cmd cmd = {
  1431. .id = REPLY_RXON_ASSOC,
  1432. .len = sizeof(rxon_assoc),
  1433. .flags = CMD_WANT_SKB,
  1434. .data = &rxon_assoc,
  1435. };
  1436. const struct il_rxon_cmd *rxon1 = &ctx->staging;
  1437. const struct il_rxon_cmd *rxon2 = &ctx->active;
  1438. if (rxon1->flags == rxon2->flags &&
  1439. rxon1->filter_flags == rxon2->filter_flags &&
  1440. rxon1->cck_basic_rates == rxon2->cck_basic_rates &&
  1441. rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates) {
  1442. D_INFO("Using current RXON_ASSOC. Not resending.\n");
  1443. return 0;
  1444. }
  1445. rxon_assoc.flags = ctx->staging.flags;
  1446. rxon_assoc.filter_flags = ctx->staging.filter_flags;
  1447. rxon_assoc.ofdm_basic_rates = ctx->staging.ofdm_basic_rates;
  1448. rxon_assoc.cck_basic_rates = ctx->staging.cck_basic_rates;
  1449. rxon_assoc.reserved = 0;
  1450. rc = il_send_cmd_sync(il, &cmd);
  1451. if (rc)
  1452. return rc;
  1453. pkt = (struct il_rx_pkt *)cmd.reply_page;
  1454. if (pkt->hdr.flags & IL_CMD_FAILED_MSK) {
  1455. IL_ERR("Bad return from REPLY_RXON_ASSOC command\n");
  1456. rc = -EIO;
  1457. }
  1458. il_free_pages(il, cmd.reply_page);
  1459. return rc;
  1460. }
  1461. /**
  1462. * il3945_commit_rxon - commit staging_rxon to hardware
  1463. *
  1464. * The RXON command in staging_rxon is committed to the hardware and
  1465. * the active_rxon structure is updated with the new data. This
  1466. * function correctly transitions out of the RXON_ASSOC_MSK state if
  1467. * a HW tune is required based on the RXON structure changes.
  1468. */
  1469. int il3945_commit_rxon(struct il_priv *il, struct il_rxon_context *ctx)
  1470. {
  1471. /* cast away the const for active_rxon in this function */
  1472. struct il3945_rxon_cmd *active_rxon = (void *)&ctx->active;
  1473. struct il3945_rxon_cmd *staging_rxon = (void *)&ctx->staging;
  1474. int rc = 0;
  1475. bool new_assoc = !!(staging_rxon->filter_flags & RXON_FILTER_ASSOC_MSK);
  1476. if (test_bit(S_EXIT_PENDING, &il->status))
  1477. return -EINVAL;
  1478. if (!il_is_alive(il))
  1479. return -1;
  1480. /* always get timestamp with Rx frame */
  1481. staging_rxon->flags |= RXON_FLG_TSF2HOST_MSK;
  1482. /* select antenna */
  1483. staging_rxon->flags &=
  1484. ~(RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_SEL_MSK);
  1485. staging_rxon->flags |= il3945_get_antenna_flags(il);
  1486. rc = il_check_rxon_cmd(il, ctx);
  1487. if (rc) {
  1488. IL_ERR("Invalid RXON configuration. Not committing.\n");
  1489. return -EINVAL;
  1490. }
  1491. /* If we don't need to send a full RXON, we can use
  1492. * il3945_rxon_assoc_cmd which is used to reconfigure filter
  1493. * and other flags for the current radio configuration. */
  1494. if (!il_full_rxon_required(il,
  1495. &il->ctx)) {
  1496. rc = il_send_rxon_assoc(il,
  1497. &il->ctx);
  1498. if (rc) {
  1499. IL_ERR("Error setting RXON_ASSOC "
  1500. "configuration (%d).\n", rc);
  1501. return rc;
  1502. }
  1503. memcpy(active_rxon, staging_rxon, sizeof(*active_rxon));
  1504. /*
  1505. * We do not commit tx power settings while channel changing,
  1506. * do it now if tx power changed.
  1507. */
  1508. il_set_tx_power(il, il->tx_power_next, false);
  1509. return 0;
  1510. }
  1511. /* If we are currently associated and the new config requires
  1512. * an RXON_ASSOC and the new config wants the associated mask enabled,
  1513. * we must clear the associated from the active configuration
  1514. * before we apply the new config */
  1515. if (il_is_associated(il) && new_assoc) {
  1516. D_INFO("Toggling associated bit on current RXON\n");
  1517. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  1518. /*
  1519. * reserved4 and 5 could have been filled by the iwlcore code.
  1520. * Let's clear them before pushing to the 3945.
  1521. */
  1522. active_rxon->reserved4 = 0;
  1523. active_rxon->reserved5 = 0;
  1524. rc = il_send_cmd_pdu(il, REPLY_RXON,
  1525. sizeof(struct il3945_rxon_cmd),
  1526. &il->ctx.active);
  1527. /* If the mask clearing failed then we set
  1528. * active_rxon back to what it was previously */
  1529. if (rc) {
  1530. active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
  1531. IL_ERR("Error clearing ASSOC_MSK on current "
  1532. "configuration (%d).\n", rc);
  1533. return rc;
  1534. }
  1535. il_clear_ucode_stations(il,
  1536. &il->ctx);
  1537. il_restore_stations(il,
  1538. &il->ctx);
  1539. }
  1540. D_INFO("Sending RXON\n"
  1541. "* with%s RXON_FILTER_ASSOC_MSK\n"
  1542. "* channel = %d\n"
  1543. "* bssid = %pM\n",
  1544. (new_assoc ? "" : "out"),
  1545. le16_to_cpu(staging_rxon->channel),
  1546. staging_rxon->bssid_addr);
  1547. /*
  1548. * reserved4 and 5 could have been filled by the iwlcore code.
  1549. * Let's clear them before pushing to the 3945.
  1550. */
  1551. staging_rxon->reserved4 = 0;
  1552. staging_rxon->reserved5 = 0;
  1553. il_set_rxon_hwcrypto(il, ctx, !il3945_mod_params.sw_crypto);
  1554. /* Apply the new configuration */
  1555. rc = il_send_cmd_pdu(il, REPLY_RXON,
  1556. sizeof(struct il3945_rxon_cmd),
  1557. staging_rxon);
  1558. if (rc) {
  1559. IL_ERR("Error setting new configuration (%d).\n", rc);
  1560. return rc;
  1561. }
  1562. memcpy(active_rxon, staging_rxon, sizeof(*active_rxon));
  1563. if (!new_assoc) {
  1564. il_clear_ucode_stations(il,
  1565. &il->ctx);
  1566. il_restore_stations(il,
  1567. &il->ctx);
  1568. }
  1569. /* If we issue a new RXON command which required a tune then we must
  1570. * send a new TXPOWER command or we won't be able to Tx any frames */
  1571. rc = il_set_tx_power(il, il->tx_power_next, true);
  1572. if (rc) {
  1573. IL_ERR("Error setting Tx power (%d).\n", rc);
  1574. return rc;
  1575. }
  1576. /* Init the hardware's rate fallback order based on the band */
  1577. rc = il3945_init_hw_rate_table(il);
  1578. if (rc) {
  1579. IL_ERR("Error setting HW rate table: %02X\n", rc);
  1580. return -EIO;
  1581. }
  1582. return 0;
  1583. }
  1584. /**
  1585. * il3945_reg_txpower_periodic - called when time to check our temperature.
  1586. *
  1587. * -- reset periodic timer
  1588. * -- see if temp has changed enough to warrant re-calibration ... if so:
  1589. * -- correct coeffs for temp (can reset temp timer)
  1590. * -- save this temp as "last",
  1591. * -- send new set of gain settings to NIC
  1592. * NOTE: This should continue working, even when we're not associated,
  1593. * so we can keep our internal table of scan powers current. */
  1594. void il3945_reg_txpower_periodic(struct il_priv *il)
  1595. {
  1596. /* This will kick in the "brute force"
  1597. * il3945_hw_reg_comp_txpower_temp() below */
  1598. if (!il3945_is_temp_calib_needed(il))
  1599. goto reschedule;
  1600. /* Set up a new set of temp-adjusted TxPowers, send to NIC.
  1601. * This is based *only* on current temperature,
  1602. * ignoring any previous power measurements */
  1603. il3945_hw_reg_comp_txpower_temp(il);
  1604. reschedule:
  1605. queue_delayed_work(il->workqueue,
  1606. &il->_3945.thermal_periodic, REG_RECALIB_PERIOD * HZ);
  1607. }
  1608. static void il3945_bg_reg_txpower_periodic(struct work_struct *work)
  1609. {
  1610. struct il_priv *il = container_of(work, struct il_priv,
  1611. _3945.thermal_periodic.work);
  1612. if (test_bit(S_EXIT_PENDING, &il->status))
  1613. return;
  1614. mutex_lock(&il->mutex);
  1615. il3945_reg_txpower_periodic(il);
  1616. mutex_unlock(&il->mutex);
  1617. }
  1618. /**
  1619. * il3945_hw_reg_get_ch_grp_idx - find the channel-group idx (0-4)
  1620. * for the channel.
  1621. *
  1622. * This function is used when initializing channel-info structs.
  1623. *
  1624. * NOTE: These channel groups do *NOT* match the bands above!
  1625. * These channel groups are based on factory-tested channels;
  1626. * on A-band, EEPROM's "group frequency" entries represent the top
  1627. * channel in each group 1-4. Group 5 All B/G channels are in group 0.
  1628. */
  1629. static u16 il3945_hw_reg_get_ch_grp_idx(struct il_priv *il,
  1630. const struct il_channel_info *ch_info)
  1631. {
  1632. struct il3945_eeprom *eeprom = (struct il3945_eeprom *)il->eeprom;
  1633. struct il3945_eeprom_txpower_group *ch_grp = &eeprom->groups[0];
  1634. u8 group;
  1635. u16 group_idx = 0; /* based on factory calib frequencies */
  1636. u8 grp_channel;
  1637. /* Find the group idx for the channel ... don't use idx 1(?) */
  1638. if (il_is_channel_a_band(ch_info)) {
  1639. for (group = 1; group < 5; group++) {
  1640. grp_channel = ch_grp[group].group_channel;
  1641. if (ch_info->channel <= grp_channel) {
  1642. group_idx = group;
  1643. break;
  1644. }
  1645. }
  1646. /* group 4 has a few channels *above* its factory cal freq */
  1647. if (group == 5)
  1648. group_idx = 4;
  1649. } else
  1650. group_idx = 0; /* 2.4 GHz, group 0 */
  1651. D_POWER("Chnl %d mapped to grp %d\n", ch_info->channel,
  1652. group_idx);
  1653. return group_idx;
  1654. }
  1655. /**
  1656. * il3945_hw_reg_get_matched_power_idx - Interpolate to get nominal idx
  1657. *
  1658. * Interpolate to get nominal (i.e. at factory calibration temperature) idx
  1659. * into radio/DSP gain settings table for requested power.
  1660. */
  1661. static int il3945_hw_reg_get_matched_power_idx(struct il_priv *il,
  1662. s8 requested_power,
  1663. s32 setting_idx, s32 *new_idx)
  1664. {
  1665. const struct il3945_eeprom_txpower_group *chnl_grp = NULL;
  1666. struct il3945_eeprom *eeprom = (struct il3945_eeprom *)il->eeprom;
  1667. s32 idx0, idx1;
  1668. s32 power = 2 * requested_power;
  1669. s32 i;
  1670. const struct il3945_eeprom_txpower_sample *samples;
  1671. s32 gains0, gains1;
  1672. s32 res;
  1673. s32 denominator;
  1674. chnl_grp = &eeprom->groups[setting_idx];
  1675. samples = chnl_grp->samples;
  1676. for (i = 0; i < 5; i++) {
  1677. if (power == samples[i].power) {
  1678. *new_idx = samples[i].gain_idx;
  1679. return 0;
  1680. }
  1681. }
  1682. if (power > samples[1].power) {
  1683. idx0 = 0;
  1684. idx1 = 1;
  1685. } else if (power > samples[2].power) {
  1686. idx0 = 1;
  1687. idx1 = 2;
  1688. } else if (power > samples[3].power) {
  1689. idx0 = 2;
  1690. idx1 = 3;
  1691. } else {
  1692. idx0 = 3;
  1693. idx1 = 4;
  1694. }
  1695. denominator = (s32) samples[idx1].power - (s32) samples[idx0].power;
  1696. if (denominator == 0)
  1697. return -EINVAL;
  1698. gains0 = (s32) samples[idx0].gain_idx * (1 << 19);
  1699. gains1 = (s32) samples[idx1].gain_idx * (1 << 19);
  1700. res = gains0 + (gains1 - gains0) *
  1701. ((s32) power - (s32) samples[idx0].power) / denominator +
  1702. (1 << 18);
  1703. *new_idx = res >> 19;
  1704. return 0;
  1705. }
  1706. static void il3945_hw_reg_init_channel_groups(struct il_priv *il)
  1707. {
  1708. u32 i;
  1709. s32 rate_idx;
  1710. struct il3945_eeprom *eeprom = (struct il3945_eeprom *)il->eeprom;
  1711. const struct il3945_eeprom_txpower_group *group;
  1712. D_POWER("Initializing factory calib info from EEPROM\n");
  1713. for (i = 0; i < IL_NUM_TX_CALIB_GROUPS; i++) {
  1714. s8 *clip_pwrs; /* table of power levels for each rate */
  1715. s8 satur_pwr; /* saturation power for each chnl group */
  1716. group = &eeprom->groups[i];
  1717. /* sanity check on factory saturation power value */
  1718. if (group->saturation_power < 40) {
  1719. IL_WARN("Error: saturation power is %d, "
  1720. "less than minimum expected 40\n",
  1721. group->saturation_power);
  1722. return;
  1723. }
  1724. /*
  1725. * Derive requested power levels for each rate, based on
  1726. * hardware capabilities (saturation power for band).
  1727. * Basic value is 3dB down from saturation, with further
  1728. * power reductions for highest 3 data rates. These
  1729. * backoffs provide headroom for high rate modulation
  1730. * power peaks, without too much distortion (clipping).
  1731. */
  1732. /* we'll fill in this array with h/w max power levels */
  1733. clip_pwrs = (s8 *) il->_3945.clip_groups[i].clip_powers;
  1734. /* divide factory saturation power by 2 to find -3dB level */
  1735. satur_pwr = (s8) (group->saturation_power >> 1);
  1736. /* fill in channel group's nominal powers for each rate */
  1737. for (rate_idx = 0;
  1738. rate_idx < RATE_COUNT_3945; rate_idx++, clip_pwrs++) {
  1739. switch (rate_idx) {
  1740. case RATE_36M_IDX_TBL:
  1741. if (i == 0) /* B/G */
  1742. *clip_pwrs = satur_pwr;
  1743. else /* A */
  1744. *clip_pwrs = satur_pwr - 5;
  1745. break;
  1746. case RATE_48M_IDX_TBL:
  1747. if (i == 0)
  1748. *clip_pwrs = satur_pwr - 7;
  1749. else
  1750. *clip_pwrs = satur_pwr - 10;
  1751. break;
  1752. case RATE_54M_IDX_TBL:
  1753. if (i == 0)
  1754. *clip_pwrs = satur_pwr - 9;
  1755. else
  1756. *clip_pwrs = satur_pwr - 12;
  1757. break;
  1758. default:
  1759. *clip_pwrs = satur_pwr;
  1760. break;
  1761. }
  1762. }
  1763. }
  1764. }
  1765. /**
  1766. * il3945_txpower_set_from_eeprom - Set channel power info based on EEPROM
  1767. *
  1768. * Second pass (during init) to set up il->channel_info
  1769. *
  1770. * Set up Tx-power settings in our channel info database for each VALID
  1771. * (for this geo/SKU) channel, at all Tx data rates, based on eeprom values
  1772. * and current temperature.
  1773. *
  1774. * Since this is based on current temperature (at init time), these values may
  1775. * not be valid for very long, but it gives us a starting/default point,
  1776. * and allows us to active (i.e. using Tx) scan.
  1777. *
  1778. * This does *not* write values to NIC, just sets up our internal table.
  1779. */
  1780. int il3945_txpower_set_from_eeprom(struct il_priv *il)
  1781. {
  1782. struct il_channel_info *ch_info = NULL;
  1783. struct il3945_channel_power_info *pwr_info;
  1784. struct il3945_eeprom *eeprom = (struct il3945_eeprom *)il->eeprom;
  1785. int delta_idx;
  1786. u8 rate_idx;
  1787. u8 scan_tbl_idx;
  1788. const s8 *clip_pwrs; /* array of power levels for each rate */
  1789. u8 gain, dsp_atten;
  1790. s8 power;
  1791. u8 pwr_idx, base_pwr_idx, a_band;
  1792. u8 i;
  1793. int temperature;
  1794. /* save temperature reference,
  1795. * so we can determine next time to calibrate */
  1796. temperature = il3945_hw_reg_txpower_get_temperature(il);
  1797. il->last_temperature = temperature;
  1798. il3945_hw_reg_init_channel_groups(il);
  1799. /* initialize Tx power info for each and every channel, 2.4 and 5.x */
  1800. for (i = 0, ch_info = il->channel_info; i < il->channel_count;
  1801. i++, ch_info++) {
  1802. a_band = il_is_channel_a_band(ch_info);
  1803. if (!il_is_channel_valid(ch_info))
  1804. continue;
  1805. /* find this channel's channel group (*not* "band") idx */
  1806. ch_info->group_idx =
  1807. il3945_hw_reg_get_ch_grp_idx(il, ch_info);
  1808. /* Get this chnlgrp's rate->max/clip-powers table */
  1809. clip_pwrs = il->_3945.clip_groups[ch_info->group_idx].clip_powers;
  1810. /* calculate power idx *adjustment* value according to
  1811. * diff between current temperature and factory temperature */
  1812. delta_idx = il3945_hw_reg_adjust_power_by_temp(temperature,
  1813. eeprom->groups[ch_info->group_idx].
  1814. temperature);
  1815. D_POWER("Delta idx for channel %d: %d [%d]\n",
  1816. ch_info->channel, delta_idx, temperature +
  1817. IL_TEMP_CONVERT);
  1818. /* set tx power value for all OFDM rates */
  1819. for (rate_idx = 0; rate_idx < IL_OFDM_RATES;
  1820. rate_idx++) {
  1821. s32 uninitialized_var(power_idx);
  1822. int rc;
  1823. /* use channel group's clip-power table,
  1824. * but don't exceed channel's max power */
  1825. s8 pwr = min(ch_info->max_power_avg,
  1826. clip_pwrs[rate_idx]);
  1827. pwr_info = &ch_info->power_info[rate_idx];
  1828. /* get base (i.e. at factory-measured temperature)
  1829. * power table idx for this rate's power */
  1830. rc = il3945_hw_reg_get_matched_power_idx(il, pwr,
  1831. ch_info->group_idx,
  1832. &power_idx);
  1833. if (rc) {
  1834. IL_ERR("Invalid power idx\n");
  1835. return rc;
  1836. }
  1837. pwr_info->base_power_idx = (u8) power_idx;
  1838. /* temperature compensate */
  1839. power_idx += delta_idx;
  1840. /* stay within range of gain table */
  1841. power_idx = il3945_hw_reg_fix_power_idx(power_idx);
  1842. /* fill 1 OFDM rate's il3945_channel_power_info struct */
  1843. pwr_info->requested_power = pwr;
  1844. pwr_info->power_table_idx = (u8) power_idx;
  1845. pwr_info->tpc.tx_gain =
  1846. power_gain_table[a_band][power_idx].tx_gain;
  1847. pwr_info->tpc.dsp_atten =
  1848. power_gain_table[a_band][power_idx].dsp_atten;
  1849. }
  1850. /* set tx power for CCK rates, based on OFDM 12 Mbit settings*/
  1851. pwr_info = &ch_info->power_info[RATE_12M_IDX_TBL];
  1852. power = pwr_info->requested_power +
  1853. IL_CCK_FROM_OFDM_POWER_DIFF;
  1854. pwr_idx = pwr_info->power_table_idx +
  1855. IL_CCK_FROM_OFDM_IDX_DIFF;
  1856. base_pwr_idx = pwr_info->base_power_idx +
  1857. IL_CCK_FROM_OFDM_IDX_DIFF;
  1858. /* stay within table range */
  1859. pwr_idx = il3945_hw_reg_fix_power_idx(pwr_idx);
  1860. gain = power_gain_table[a_band][pwr_idx].tx_gain;
  1861. dsp_atten = power_gain_table[a_band][pwr_idx].dsp_atten;
  1862. /* fill each CCK rate's il3945_channel_power_info structure
  1863. * NOTE: All CCK-rate Txpwrs are the same for a given chnl!
  1864. * NOTE: CCK rates start at end of OFDM rates! */
  1865. for (rate_idx = 0;
  1866. rate_idx < IL_CCK_RATES; rate_idx++) {
  1867. pwr_info = &ch_info->power_info[rate_idx+IL_OFDM_RATES];
  1868. pwr_info->requested_power = power;
  1869. pwr_info->power_table_idx = pwr_idx;
  1870. pwr_info->base_power_idx = base_pwr_idx;
  1871. pwr_info->tpc.tx_gain = gain;
  1872. pwr_info->tpc.dsp_atten = dsp_atten;
  1873. }
  1874. /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
  1875. for (scan_tbl_idx = 0;
  1876. scan_tbl_idx < IL_NUM_SCAN_RATES; scan_tbl_idx++) {
  1877. s32 actual_idx = (scan_tbl_idx == 0) ?
  1878. RATE_1M_IDX_TBL : RATE_6M_IDX_TBL;
  1879. il3945_hw_reg_set_scan_power(il, scan_tbl_idx,
  1880. actual_idx, clip_pwrs, ch_info, a_band);
  1881. }
  1882. }
  1883. return 0;
  1884. }
  1885. int il3945_hw_rxq_stop(struct il_priv *il)
  1886. {
  1887. int rc;
  1888. il_wr(il, FH39_RCSR_CONFIG(0), 0);
  1889. rc = il_poll_bit(il, FH39_RSSR_STATUS,
  1890. FH39_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
  1891. if (rc < 0)
  1892. IL_ERR("Can't stop Rx DMA.\n");
  1893. return 0;
  1894. }
  1895. int il3945_hw_tx_queue_init(struct il_priv *il, struct il_tx_queue *txq)
  1896. {
  1897. int txq_id = txq->q.id;
  1898. struct il3945_shared *shared_data = il->_3945.shared_virt;
  1899. shared_data->tx_base_ptr[txq_id] = cpu_to_le32((u32)txq->q.dma_addr);
  1900. il_wr(il, FH39_CBCC_CTRL(txq_id), 0);
  1901. il_wr(il, FH39_CBCC_BASE(txq_id), 0);
  1902. il_wr(il, FH39_TCSR_CONFIG(txq_id),
  1903. FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT |
  1904. FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF |
  1905. FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD |
  1906. FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL |
  1907. FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE);
  1908. /* fake read to flush all prev. writes */
  1909. _il_rd(il, FH39_TSSR_CBB_BASE);
  1910. return 0;
  1911. }
  1912. /*
  1913. * HCMD utils
  1914. */
  1915. static u16 il3945_get_hcmd_size(u8 cmd_id, u16 len)
  1916. {
  1917. switch (cmd_id) {
  1918. case REPLY_RXON:
  1919. return sizeof(struct il3945_rxon_cmd);
  1920. case POWER_TBL_CMD:
  1921. return sizeof(struct il3945_powertable_cmd);
  1922. default:
  1923. return len;
  1924. }
  1925. }
  1926. static u16 il3945_build_addsta_hcmd(const struct il_addsta_cmd *cmd,
  1927. u8 *data)
  1928. {
  1929. struct il3945_addsta_cmd *addsta = (struct il3945_addsta_cmd *)data;
  1930. addsta->mode = cmd->mode;
  1931. memcpy(&addsta->sta, &cmd->sta, sizeof(struct sta_id_modify));
  1932. memcpy(&addsta->key, &cmd->key, sizeof(struct il4965_keyinfo));
  1933. addsta->station_flags = cmd->station_flags;
  1934. addsta->station_flags_msk = cmd->station_flags_msk;
  1935. addsta->tid_disable_tx = cpu_to_le16(0);
  1936. addsta->rate_n_flags = cmd->rate_n_flags;
  1937. addsta->add_immediate_ba_tid = cmd->add_immediate_ba_tid;
  1938. addsta->remove_immediate_ba_tid = cmd->remove_immediate_ba_tid;
  1939. addsta->add_immediate_ba_ssn = cmd->add_immediate_ba_ssn;
  1940. return (u16)sizeof(struct il3945_addsta_cmd);
  1941. }
  1942. static int il3945_add_bssid_station(struct il_priv *il,
  1943. const u8 *addr, u8 *sta_id_r)
  1944. {
  1945. struct il_rxon_context *ctx = &il->ctx;
  1946. int ret;
  1947. u8 sta_id;
  1948. unsigned long flags;
  1949. if (sta_id_r)
  1950. *sta_id_r = IL_INVALID_STATION;
  1951. ret = il_add_station_common(il, ctx, addr, 0, NULL, &sta_id);
  1952. if (ret) {
  1953. IL_ERR("Unable to add station %pM\n", addr);
  1954. return ret;
  1955. }
  1956. if (sta_id_r)
  1957. *sta_id_r = sta_id;
  1958. spin_lock_irqsave(&il->sta_lock, flags);
  1959. il->stations[sta_id].used |= IL_STA_LOCAL;
  1960. spin_unlock_irqrestore(&il->sta_lock, flags);
  1961. return 0;
  1962. }
  1963. static int il3945_manage_ibss_station(struct il_priv *il,
  1964. struct ieee80211_vif *vif, bool add)
  1965. {
  1966. struct il_vif_priv *vif_priv = (void *)vif->drv_priv;
  1967. int ret;
  1968. if (add) {
  1969. ret = il3945_add_bssid_station(il, vif->bss_conf.bssid,
  1970. &vif_priv->ibss_bssid_sta_id);
  1971. if (ret)
  1972. return ret;
  1973. il3945_sync_sta(il, vif_priv->ibss_bssid_sta_id,
  1974. (il->band == IEEE80211_BAND_5GHZ) ?
  1975. RATE_6M_PLCP : RATE_1M_PLCP);
  1976. il3945_rate_scale_init(il->hw, vif_priv->ibss_bssid_sta_id);
  1977. return 0;
  1978. }
  1979. return il_remove_station(il, vif_priv->ibss_bssid_sta_id,
  1980. vif->bss_conf.bssid);
  1981. }
  1982. /**
  1983. * il3945_init_hw_rate_table - Initialize the hardware rate fallback table
  1984. */
  1985. int il3945_init_hw_rate_table(struct il_priv *il)
  1986. {
  1987. int rc, i, idx, prev_idx;
  1988. struct il3945_rate_scaling_cmd rate_cmd = {
  1989. .reserved = {0, 0, 0},
  1990. };
  1991. struct il3945_rate_scaling_info *table = rate_cmd.table;
  1992. for (i = 0; i < ARRAY_SIZE(il3945_rates); i++) {
  1993. idx = il3945_rates[i].table_rs_idx;
  1994. table[idx].rate_n_flags =
  1995. il3945_hw_set_rate_n_flags(il3945_rates[i].plcp, 0);
  1996. table[idx].try_cnt = il->retry_rate;
  1997. prev_idx = il3945_get_prev_ieee_rate(i);
  1998. table[idx].next_rate_idx =
  1999. il3945_rates[prev_idx].table_rs_idx;
  2000. }
  2001. switch (il->band) {
  2002. case IEEE80211_BAND_5GHZ:
  2003. D_RATE("Select A mode rate scale\n");
  2004. /* If one of the following CCK rates is used,
  2005. * have it fall back to the 6M OFDM rate */
  2006. for (i = RATE_1M_IDX_TBL;
  2007. i <= RATE_11M_IDX_TBL; i++)
  2008. table[i].next_rate_idx =
  2009. il3945_rates[IL_FIRST_OFDM_RATE].table_rs_idx;
  2010. /* Don't fall back to CCK rates */
  2011. table[RATE_12M_IDX_TBL].next_rate_idx =
  2012. RATE_9M_IDX_TBL;
  2013. /* Don't drop out of OFDM rates */
  2014. table[RATE_6M_IDX_TBL].next_rate_idx =
  2015. il3945_rates[IL_FIRST_OFDM_RATE].table_rs_idx;
  2016. break;
  2017. case IEEE80211_BAND_2GHZ:
  2018. D_RATE("Select B/G mode rate scale\n");
  2019. /* If an OFDM rate is used, have it fall back to the
  2020. * 1M CCK rates */
  2021. if (!(il->_3945.sta_supp_rates & IL_OFDM_RATES_MASK) &&
  2022. il_is_associated(il)) {
  2023. idx = IL_FIRST_CCK_RATE;
  2024. for (i = RATE_6M_IDX_TBL;
  2025. i <= RATE_54M_IDX_TBL; i++)
  2026. table[i].next_rate_idx =
  2027. il3945_rates[idx].table_rs_idx;
  2028. idx = RATE_11M_IDX_TBL;
  2029. /* CCK shouldn't fall back to OFDM... */
  2030. table[idx].next_rate_idx = RATE_5M_IDX_TBL;
  2031. }
  2032. break;
  2033. default:
  2034. WARN_ON(1);
  2035. break;
  2036. }
  2037. /* Update the rate scaling for control frame Tx */
  2038. rate_cmd.table_id = 0;
  2039. rc = il_send_cmd_pdu(il, REPLY_RATE_SCALE, sizeof(rate_cmd),
  2040. &rate_cmd);
  2041. if (rc)
  2042. return rc;
  2043. /* Update the rate scaling for data frame Tx */
  2044. rate_cmd.table_id = 1;
  2045. return il_send_cmd_pdu(il, REPLY_RATE_SCALE, sizeof(rate_cmd),
  2046. &rate_cmd);
  2047. }
  2048. /* Called when initializing driver */
  2049. int il3945_hw_set_hw_params(struct il_priv *il)
  2050. {
  2051. memset((void *)&il->hw_params, 0,
  2052. sizeof(struct il_hw_params));
  2053. il->_3945.shared_virt =
  2054. dma_alloc_coherent(&il->pci_dev->dev,
  2055. sizeof(struct il3945_shared),
  2056. &il->_3945.shared_phys, GFP_KERNEL);
  2057. if (!il->_3945.shared_virt) {
  2058. IL_ERR("failed to allocate pci memory\n");
  2059. return -ENOMEM;
  2060. }
  2061. /* Assign number of Usable TX queues */
  2062. il->hw_params.max_txq_num = il->cfg->base_params->num_of_queues;
  2063. il->hw_params.tfd_size = sizeof(struct il3945_tfd);
  2064. il->hw_params.rx_page_order = get_order(IL_RX_BUF_SIZE_3K);
  2065. il->hw_params.max_rxq_size = RX_QUEUE_SIZE;
  2066. il->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
  2067. il->hw_params.max_stations = IL3945_STATION_COUNT;
  2068. il->ctx.bcast_sta_id = IL3945_BROADCAST_ID;
  2069. il->sta_key_max_num = STA_KEY_MAX_NUM;
  2070. il->hw_params.rx_wrt_ptr_reg = FH39_RSCSR_CHNL0_WPTR;
  2071. il->hw_params.max_beacon_itrvl = IL39_MAX_UCODE_BEACON_INTERVAL;
  2072. il->hw_params.beacon_time_tsf_bits = IL3945_EXT_BEACON_TIME_POS;
  2073. return 0;
  2074. }
  2075. unsigned int il3945_hw_get_beacon_cmd(struct il_priv *il,
  2076. struct il3945_frame *frame, u8 rate)
  2077. {
  2078. struct il3945_tx_beacon_cmd *tx_beacon_cmd;
  2079. unsigned int frame_size;
  2080. tx_beacon_cmd = (struct il3945_tx_beacon_cmd *)&frame->u;
  2081. memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
  2082. tx_beacon_cmd->tx.sta_id =
  2083. il->ctx.bcast_sta_id;
  2084. tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  2085. frame_size = il3945_fill_beacon_frame(il,
  2086. tx_beacon_cmd->frame,
  2087. sizeof(frame->u) - sizeof(*tx_beacon_cmd));
  2088. BUG_ON(frame_size > MAX_MPDU_SIZE);
  2089. tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
  2090. tx_beacon_cmd->tx.rate = rate;
  2091. tx_beacon_cmd->tx.tx_flags = (TX_CMD_FLG_SEQ_CTL_MSK |
  2092. TX_CMD_FLG_TSF_MSK);
  2093. /* supp_rates[0] == OFDM start at IL_FIRST_OFDM_RATE*/
  2094. tx_beacon_cmd->tx.supp_rates[0] =
  2095. (IL_OFDM_BASIC_RATES_MASK >> IL_FIRST_OFDM_RATE) & 0xFF;
  2096. tx_beacon_cmd->tx.supp_rates[1] =
  2097. (IL_CCK_BASIC_RATES_MASK & 0xF);
  2098. return sizeof(struct il3945_tx_beacon_cmd) + frame_size;
  2099. }
  2100. void il3945_hw_rx_handler_setup(struct il_priv *il)
  2101. {
  2102. il->rx_handlers[REPLY_TX] = il3945_rx_reply_tx;
  2103. il->rx_handlers[REPLY_3945_RX] = il3945_rx_reply_rx;
  2104. }
  2105. void il3945_hw_setup_deferred_work(struct il_priv *il)
  2106. {
  2107. INIT_DELAYED_WORK(&il->_3945.thermal_periodic,
  2108. il3945_bg_reg_txpower_periodic);
  2109. }
  2110. void il3945_hw_cancel_deferred_work(struct il_priv *il)
  2111. {
  2112. cancel_delayed_work(&il->_3945.thermal_periodic);
  2113. }
  2114. /* check contents of special bootstrap uCode SRAM */
  2115. static int il3945_verify_bsm(struct il_priv *il)
  2116. {
  2117. __le32 *image = il->ucode_boot.v_addr;
  2118. u32 len = il->ucode_boot.len;
  2119. u32 reg;
  2120. u32 val;
  2121. D_INFO("Begin verify bsm\n");
  2122. /* verify BSM SRAM contents */
  2123. val = il_rd_prph(il, BSM_WR_DWCOUNT_REG);
  2124. for (reg = BSM_SRAM_LOWER_BOUND;
  2125. reg < BSM_SRAM_LOWER_BOUND + len;
  2126. reg += sizeof(u32), image++) {
  2127. val = il_rd_prph(il, reg);
  2128. if (val != le32_to_cpu(*image)) {
  2129. IL_ERR("BSM uCode verification failed at "
  2130. "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
  2131. BSM_SRAM_LOWER_BOUND,
  2132. reg - BSM_SRAM_LOWER_BOUND, len,
  2133. val, le32_to_cpu(*image));
  2134. return -EIO;
  2135. }
  2136. }
  2137. D_INFO("BSM bootstrap uCode image OK\n");
  2138. return 0;
  2139. }
  2140. /******************************************************************************
  2141. *
  2142. * EEPROM related functions
  2143. *
  2144. ******************************************************************************/
  2145. /*
  2146. * Clear the OWNER_MSK, to establish driver (instead of uCode running on
  2147. * embedded controller) as EEPROM reader; each read is a series of pulses
  2148. * to/from the EEPROM chip, not a single event, so even reads could conflict
  2149. * if they weren't arbitrated by some ownership mechanism. Here, the driver
  2150. * simply claims ownership, which should be safe when this function is called
  2151. * (i.e. before loading uCode!).
  2152. */
  2153. static int il3945_eeprom_acquire_semaphore(struct il_priv *il)
  2154. {
  2155. _il_clear_bit(il, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK);
  2156. return 0;
  2157. }
  2158. static void il3945_eeprom_release_semaphore(struct il_priv *il)
  2159. {
  2160. return;
  2161. }
  2162. /**
  2163. * il3945_load_bsm - Load bootstrap instructions
  2164. *
  2165. * BSM operation:
  2166. *
  2167. * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
  2168. * in special SRAM that does not power down during RFKILL. When powering back
  2169. * up after power-saving sleeps (or during initial uCode load), the BSM loads
  2170. * the bootstrap program into the on-board processor, and starts it.
  2171. *
  2172. * The bootstrap program loads (via DMA) instructions and data for a new
  2173. * program from host DRAM locations indicated by the host driver in the
  2174. * BSM_DRAM_* registers. Once the new program is loaded, it starts
  2175. * automatically.
  2176. *
  2177. * When initializing the NIC, the host driver points the BSM to the
  2178. * "initialize" uCode image. This uCode sets up some internal data, then
  2179. * notifies host via "initialize alive" that it is complete.
  2180. *
  2181. * The host then replaces the BSM_DRAM_* pointer values to point to the
  2182. * normal runtime uCode instructions and a backup uCode data cache buffer
  2183. * (filled initially with starting data values for the on-board processor),
  2184. * then triggers the "initialize" uCode to load and launch the runtime uCode,
  2185. * which begins normal operation.
  2186. *
  2187. * When doing a power-save shutdown, runtime uCode saves data SRAM into
  2188. * the backup data cache in DRAM before SRAM is powered down.
  2189. *
  2190. * When powering back up, the BSM loads the bootstrap program. This reloads
  2191. * the runtime uCode instructions and the backup data cache into SRAM,
  2192. * and re-launches the runtime uCode from where it left off.
  2193. */
  2194. static int il3945_load_bsm(struct il_priv *il)
  2195. {
  2196. __le32 *image = il->ucode_boot.v_addr;
  2197. u32 len = il->ucode_boot.len;
  2198. dma_addr_t pinst;
  2199. dma_addr_t pdata;
  2200. u32 inst_len;
  2201. u32 data_len;
  2202. int rc;
  2203. int i;
  2204. u32 done;
  2205. u32 reg_offset;
  2206. D_INFO("Begin load bsm\n");
  2207. /* make sure bootstrap program is no larger than BSM's SRAM size */
  2208. if (len > IL39_MAX_BSM_SIZE)
  2209. return -EINVAL;
  2210. /* Tell bootstrap uCode where to find the "Initialize" uCode
  2211. * in host DRAM ... host DRAM physical address bits 31:0 for 3945.
  2212. * NOTE: il3945_initialize_alive_start() will replace these values,
  2213. * after the "initialize" uCode has run, to point to
  2214. * runtime/protocol instructions and backup data cache. */
  2215. pinst = il->ucode_init.p_addr;
  2216. pdata = il->ucode_init_data.p_addr;
  2217. inst_len = il->ucode_init.len;
  2218. data_len = il->ucode_init_data.len;
  2219. il_wr_prph(il, BSM_DRAM_INST_PTR_REG, pinst);
  2220. il_wr_prph(il, BSM_DRAM_DATA_PTR_REG, pdata);
  2221. il_wr_prph(il, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
  2222. il_wr_prph(il, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
  2223. /* Fill BSM memory with bootstrap instructions */
  2224. for (reg_offset = BSM_SRAM_LOWER_BOUND;
  2225. reg_offset < BSM_SRAM_LOWER_BOUND + len;
  2226. reg_offset += sizeof(u32), image++)
  2227. _il_wr_prph(il, reg_offset,
  2228. le32_to_cpu(*image));
  2229. rc = il3945_verify_bsm(il);
  2230. if (rc)
  2231. return rc;
  2232. /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
  2233. il_wr_prph(il, BSM_WR_MEM_SRC_REG, 0x0);
  2234. il_wr_prph(il, BSM_WR_MEM_DST_REG,
  2235. IL39_RTC_INST_LOWER_BOUND);
  2236. il_wr_prph(il, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
  2237. /* Load bootstrap code into instruction SRAM now,
  2238. * to prepare to load "initialize" uCode */
  2239. il_wr_prph(il, BSM_WR_CTRL_REG,
  2240. BSM_WR_CTRL_REG_BIT_START);
  2241. /* Wait for load of bootstrap uCode to finish */
  2242. for (i = 0; i < 100; i++) {
  2243. done = il_rd_prph(il, BSM_WR_CTRL_REG);
  2244. if (!(done & BSM_WR_CTRL_REG_BIT_START))
  2245. break;
  2246. udelay(10);
  2247. }
  2248. if (i < 100)
  2249. D_INFO("BSM write complete, poll %d iterations\n", i);
  2250. else {
  2251. IL_ERR("BSM write did not complete!\n");
  2252. return -EIO;
  2253. }
  2254. /* Enable future boot loads whenever power management unit triggers it
  2255. * (e.g. when powering back up after power-save shutdown) */
  2256. il_wr_prph(il, BSM_WR_CTRL_REG,
  2257. BSM_WR_CTRL_REG_BIT_START_EN);
  2258. return 0;
  2259. }
  2260. static struct il_hcmd_ops il3945_hcmd = {
  2261. .rxon_assoc = il3945_send_rxon_assoc,
  2262. .commit_rxon = il3945_commit_rxon,
  2263. };
  2264. static struct il_lib_ops il3945_lib = {
  2265. .txq_attach_buf_to_tfd = il3945_hw_txq_attach_buf_to_tfd,
  2266. .txq_free_tfd = il3945_hw_txq_free_tfd,
  2267. .txq_init = il3945_hw_tx_queue_init,
  2268. .load_ucode = il3945_load_bsm,
  2269. .dump_nic_error_log = il3945_dump_nic_error_log,
  2270. .apm_ops = {
  2271. .init = il3945_apm_init,
  2272. .config = il3945_nic_config,
  2273. },
  2274. .eeprom_ops = {
  2275. .regulatory_bands = {
  2276. EEPROM_REGULATORY_BAND_1_CHANNELS,
  2277. EEPROM_REGULATORY_BAND_2_CHANNELS,
  2278. EEPROM_REGULATORY_BAND_3_CHANNELS,
  2279. EEPROM_REGULATORY_BAND_4_CHANNELS,
  2280. EEPROM_REGULATORY_BAND_5_CHANNELS,
  2281. EEPROM_REGULATORY_BAND_NO_HT40,
  2282. EEPROM_REGULATORY_BAND_NO_HT40,
  2283. },
  2284. .acquire_semaphore = il3945_eeprom_acquire_semaphore,
  2285. .release_semaphore = il3945_eeprom_release_semaphore,
  2286. },
  2287. .send_tx_power = il3945_send_tx_power,
  2288. .is_valid_rtc_data_addr = il3945_hw_valid_rtc_data_addr,
  2289. .debugfs_ops = {
  2290. .rx_stats_read = il3945_ucode_rx_stats_read,
  2291. .tx_stats_read = il3945_ucode_tx_stats_read,
  2292. .general_stats_read = il3945_ucode_general_stats_read,
  2293. },
  2294. };
  2295. static const struct il_legacy_ops il3945_legacy_ops = {
  2296. .post_associate = il3945_post_associate,
  2297. .config_ap = il3945_config_ap,
  2298. .manage_ibss_station = il3945_manage_ibss_station,
  2299. };
  2300. static struct il_hcmd_utils_ops il3945_hcmd_utils = {
  2301. .get_hcmd_size = il3945_get_hcmd_size,
  2302. .build_addsta_hcmd = il3945_build_addsta_hcmd,
  2303. .request_scan = il3945_request_scan,
  2304. .post_scan = il3945_post_scan,
  2305. };
  2306. static const struct il_ops il3945_ops = {
  2307. .lib = &il3945_lib,
  2308. .hcmd = &il3945_hcmd,
  2309. .utils = &il3945_hcmd_utils,
  2310. .led = &il3945_led_ops,
  2311. .legacy = &il3945_legacy_ops,
  2312. .ieee80211_ops = &il3945_hw_ops,
  2313. };
  2314. static struct il_base_params il3945_base_params = {
  2315. .eeprom_size = IL3945_EEPROM_IMG_SIZE,
  2316. .num_of_queues = IL39_NUM_QUEUES,
  2317. .pll_cfg_val = CSR39_ANA_PLL_CFG_VAL,
  2318. .set_l0s = false,
  2319. .use_bsm = true,
  2320. .led_compensation = 64,
  2321. .wd_timeout = IL_DEF_WD_TIMEOUT,
  2322. };
  2323. static struct il_cfg il3945_bg_cfg = {
  2324. .name = "3945BG",
  2325. .fw_name_pre = IL3945_FW_PRE,
  2326. .ucode_api_max = IL3945_UCODE_API_MAX,
  2327. .ucode_api_min = IL3945_UCODE_API_MIN,
  2328. .sku = IL_SKU_G,
  2329. .eeprom_ver = EEPROM_3945_EEPROM_VERSION,
  2330. .ops = &il3945_ops,
  2331. .mod_params = &il3945_mod_params,
  2332. .base_params = &il3945_base_params,
  2333. .led_mode = IL_LED_BLINK,
  2334. };
  2335. static struct il_cfg il3945_abg_cfg = {
  2336. .name = "3945ABG",
  2337. .fw_name_pre = IL3945_FW_PRE,
  2338. .ucode_api_max = IL3945_UCODE_API_MAX,
  2339. .ucode_api_min = IL3945_UCODE_API_MIN,
  2340. .sku = IL_SKU_A|IL_SKU_G,
  2341. .eeprom_ver = EEPROM_3945_EEPROM_VERSION,
  2342. .ops = &il3945_ops,
  2343. .mod_params = &il3945_mod_params,
  2344. .base_params = &il3945_base_params,
  2345. .led_mode = IL_LED_BLINK,
  2346. };
  2347. DEFINE_PCI_DEVICE_TABLE(il3945_hw_card_ids) = {
  2348. {IL_PCI_DEVICE(0x4222, 0x1005, il3945_bg_cfg)},
  2349. {IL_PCI_DEVICE(0x4222, 0x1034, il3945_bg_cfg)},
  2350. {IL_PCI_DEVICE(0x4222, 0x1044, il3945_bg_cfg)},
  2351. {IL_PCI_DEVICE(0x4227, 0x1014, il3945_bg_cfg)},
  2352. {IL_PCI_DEVICE(0x4222, PCI_ANY_ID, il3945_abg_cfg)},
  2353. {IL_PCI_DEVICE(0x4227, PCI_ANY_ID, il3945_abg_cfg)},
  2354. {0}
  2355. };
  2356. MODULE_DEVICE_TABLE(pci, il3945_hw_card_ids);