board-bockw.c 6.7 KB

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  1. /*
  2. * Bock-W board support
  3. *
  4. * Copyright (C) 2013 Renesas Solutions Corp.
  5. * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License as published by
  9. * the Free Software Foundation; version 2 of the License.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  19. */
  20. #include <linux/mfd/tmio.h>
  21. #include <linux/mmc/host.h>
  22. #include <linux/mmc/sh_mmcif.h>
  23. #include <linux/mtd/partitions.h>
  24. #include <linux/pinctrl/machine.h>
  25. #include <linux/platform_device.h>
  26. #include <linux/regulator/fixed.h>
  27. #include <linux/regulator/machine.h>
  28. #include <linux/smsc911x.h>
  29. #include <linux/spi/spi.h>
  30. #include <linux/spi/flash.h>
  31. #include <mach/common.h>
  32. #include <mach/irqs.h>
  33. #include <mach/r8a7778.h>
  34. #include <asm/mach/arch.h>
  35. /*
  36. * CN9(Upper side) SCIF/RCAN selection
  37. *
  38. * 1,4 3,6
  39. * SW40 SCIF RCAN
  40. * SW41 SCIF RCAN
  41. */
  42. /*
  43. * MMC (CN26) pin
  44. *
  45. * SW6 (D2) 3 pin
  46. * SW7 (D5) ON
  47. * SW8 (D3) 3 pin
  48. * SW10 (D4) 1 pin
  49. * SW12 (CLK) 1 pin
  50. * SW13 (D6) 3 pin
  51. * SW14 (CMD) ON
  52. * SW15 (D6) 1 pin
  53. * SW16 (D0) ON
  54. * SW17 (D1) ON
  55. * SW18 (D7) 3 pin
  56. * SW19 (MMC) 1 pin
  57. */
  58. /* Dummy supplies, where voltage doesn't matter */
  59. static struct regulator_consumer_supply dummy_supplies[] = {
  60. REGULATOR_SUPPLY("vddvario", "smsc911x"),
  61. REGULATOR_SUPPLY("vdd33a", "smsc911x"),
  62. };
  63. static struct smsc911x_platform_config smsc911x_data = {
  64. .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
  65. .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
  66. .flags = SMSC911X_USE_32BIT,
  67. .phy_interface = PHY_INTERFACE_MODE_MII,
  68. };
  69. static struct resource smsc911x_resources[] = {
  70. DEFINE_RES_MEM(0x18300000, 0x1000),
  71. DEFINE_RES_IRQ(irq_pin(0)), /* IRQ 0 */
  72. };
  73. /* USB */
  74. static struct rcar_phy_platform_data usb_phy_platform_data __initdata;
  75. /* SDHI */
  76. static struct sh_mobile_sdhi_info sdhi0_info = {
  77. .tmio_caps = MMC_CAP_SD_HIGHSPEED,
  78. .tmio_ocr_mask = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34,
  79. .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT,
  80. };
  81. static struct sh_eth_plat_data ether_platform_data __initdata = {
  82. .phy = 0x01,
  83. .edmac_endian = EDMAC_LITTLE_ENDIAN,
  84. .register_type = SH_ETH_REG_FAST_RCAR,
  85. .phy_interface = PHY_INTERFACE_MODE_RMII,
  86. /*
  87. * Although the LINK signal is available on the board, it's connected to
  88. * the link/activity LED output of the PHY, thus the link disappears and
  89. * reappears after each packet. We'd be better off ignoring such signal
  90. * and getting the link state from the PHY indirectly.
  91. */
  92. .no_ether_link = 1,
  93. };
  94. /* I2C */
  95. static struct i2c_board_info i2c0_devices[] = {
  96. {
  97. I2C_BOARD_INFO("rx8581", 0x51),
  98. },
  99. };
  100. /* HSPI*/
  101. static struct mtd_partition m25p80_spi_flash_partitions[] = {
  102. {
  103. .name = "data(spi)",
  104. .size = 0x0100000,
  105. .offset = 0,
  106. },
  107. };
  108. static struct flash_platform_data spi_flash_data = {
  109. .name = "m25p80",
  110. .type = "s25fl008k",
  111. .parts = m25p80_spi_flash_partitions,
  112. .nr_parts = ARRAY_SIZE(m25p80_spi_flash_partitions),
  113. };
  114. static struct spi_board_info spi_board_info[] __initdata = {
  115. {
  116. .modalias = "m25p80",
  117. .max_speed_hz = 104000000,
  118. .chip_select = 0,
  119. .bus_num = 0,
  120. .mode = SPI_MODE_0,
  121. .platform_data = &spi_flash_data,
  122. },
  123. };
  124. /* MMC */
  125. static struct resource mmc_resources[] __initdata = {
  126. DEFINE_RES_MEM(0xffe4e000, 0x100),
  127. DEFINE_RES_IRQ(gic_iid(0x5d)),
  128. };
  129. static struct sh_mmcif_plat_data sh_mmcif_plat = {
  130. .sup_pclk = 0,
  131. .ocr = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34,
  132. .caps = MMC_CAP_4_BIT_DATA |
  133. MMC_CAP_8_BIT_DATA |
  134. MMC_CAP_NEEDS_POLL,
  135. };
  136. static const struct pinctrl_map bockw_pinctrl_map[] = {
  137. /* Ether */
  138. PIN_MAP_MUX_GROUP_DEFAULT("r8a777x-ether", "pfc-r8a7778",
  139. "ether_rmii", "ether"),
  140. /* HSPI0 */
  141. PIN_MAP_MUX_GROUP_DEFAULT("sh-hspi.0", "pfc-r8a7778",
  142. "hspi0_a", "hspi0"),
  143. /* MMC */
  144. PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif", "pfc-r8a7778",
  145. "mmc_data8", "mmc"),
  146. PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif", "pfc-r8a7778",
  147. "mmc_ctrl", "mmc"),
  148. /* SCIF0 */
  149. PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-r8a7778",
  150. "scif0_data_a", "scif0"),
  151. PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-r8a7778",
  152. "scif0_ctrl", "scif0"),
  153. /* USB */
  154. PIN_MAP_MUX_GROUP_DEFAULT("ehci-platform", "pfc-r8a7778",
  155. "usb0", "usb0"),
  156. PIN_MAP_MUX_GROUP_DEFAULT("ehci-platform", "pfc-r8a7778",
  157. "usb1", "usb1"),
  158. /* SDHI0 */
  159. PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7778",
  160. "sdhi0", "sdhi0"),
  161. };
  162. #define FPGA 0x18200000
  163. #define IRQ0MR 0x30
  164. #define PFC 0xfffc0000
  165. #define PUPR4 0x110
  166. static void __init bockw_init(void)
  167. {
  168. void __iomem *base;
  169. r8a7778_clock_init();
  170. r8a7778_init_irq_extpin(1);
  171. r8a7778_add_standard_devices();
  172. r8a7778_add_usb_phy_device(&usb_phy_platform_data);
  173. r8a7778_add_ether_device(&ether_platform_data);
  174. r8a7778_add_i2c_device(0);
  175. r8a7778_add_hspi_device(0);
  176. i2c_register_board_info(0, i2c0_devices,
  177. ARRAY_SIZE(i2c0_devices));
  178. spi_register_board_info(spi_board_info,
  179. ARRAY_SIZE(spi_board_info));
  180. pinctrl_register_mappings(bockw_pinctrl_map,
  181. ARRAY_SIZE(bockw_pinctrl_map));
  182. r8a7778_pinmux_init();
  183. platform_device_register_resndata(
  184. &platform_bus, "sh_mmcif", -1,
  185. mmc_resources, ARRAY_SIZE(mmc_resources),
  186. &sh_mmcif_plat, sizeof(struct sh_mmcif_plat_data));
  187. /* for SMSC */
  188. base = ioremap_nocache(FPGA, SZ_1M);
  189. if (base) {
  190. /*
  191. * CAUTION
  192. *
  193. * IRQ0/1 is cascaded interrupt from FPGA.
  194. * it should be cared in the future
  195. * Now, it is assuming IRQ0 was used only from SMSC.
  196. */
  197. u16 val = ioread16(base + IRQ0MR);
  198. val &= ~(1 << 4); /* enable SMSC911x */
  199. iowrite16(val, base + IRQ0MR);
  200. iounmap(base);
  201. regulator_register_fixed(0, dummy_supplies,
  202. ARRAY_SIZE(dummy_supplies));
  203. platform_device_register_resndata(
  204. &platform_bus, "smsc911x", -1,
  205. smsc911x_resources, ARRAY_SIZE(smsc911x_resources),
  206. &smsc911x_data, sizeof(smsc911x_data));
  207. }
  208. /* for SDHI */
  209. base = ioremap_nocache(PFC, 0x200);
  210. if (base) {
  211. /*
  212. * FIXME
  213. *
  214. * SDHI CD/WP pin needs pull-up
  215. */
  216. iowrite32(ioread32(base + PUPR4) | (3 << 26), base + PUPR4);
  217. iounmap(base);
  218. r8a7778_sdhi_init(0, &sdhi0_info);
  219. }
  220. }
  221. static const char *bockw_boards_compat_dt[] __initdata = {
  222. "renesas,bockw",
  223. NULL,
  224. };
  225. DT_MACHINE_START(BOCKW_DT, "bockw")
  226. .init_early = r8a7778_init_delay,
  227. .init_irq = r8a7778_init_irq_dt,
  228. .init_machine = bockw_init,
  229. .init_time = shmobile_timer_init,
  230. .dt_compat = bockw_boards_compat_dt,
  231. .init_late = r8a7778_init_late,
  232. MACHINE_END