iwl-agn.c 97 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved.
  4. *
  5. * Portions of this file are derived from the ipw3945 project, as well
  6. * as portions of the ieee80211 subsystem header files.
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of version 2 of the GNU General Public License as
  10. * published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15. * more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along with
  18. * this program; if not, write to the Free Software Foundation, Inc.,
  19. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20. *
  21. * The full GNU General Public License is included in this distribution in the
  22. * file called LICENSE.
  23. *
  24. * Contact Information:
  25. * Intel Linux Wireless <ilw@linux.intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *
  28. *****************************************************************************/
  29. #include <linux/kernel.h>
  30. #include <linux/module.h>
  31. #include <linux/init.h>
  32. #include <linux/pci.h>
  33. #include <linux/dma-mapping.h>
  34. #include <linux/delay.h>
  35. #include <linux/skbuff.h>
  36. #include <linux/netdevice.h>
  37. #include <linux/wireless.h>
  38. #include <linux/firmware.h>
  39. #include <linux/etherdevice.h>
  40. #include <linux/if_arp.h>
  41. #include <net/mac80211.h>
  42. #include <asm/div64.h>
  43. #define DRV_NAME "iwlagn"
  44. #include "iwl-eeprom.h"
  45. #include "iwl-dev.h"
  46. #include "iwl-core.h"
  47. #include "iwl-io.h"
  48. #include "iwl-helpers.h"
  49. #include "iwl-sta.h"
  50. #include "iwl-calib.h"
  51. /******************************************************************************
  52. *
  53. * module boiler plate
  54. *
  55. ******************************************************************************/
  56. /*
  57. * module name, copyright, version, etc.
  58. */
  59. #define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
  60. #ifdef CONFIG_IWLWIFI_DEBUG
  61. #define VD "d"
  62. #else
  63. #define VD
  64. #endif
  65. #ifdef CONFIG_IWLWIFI_SPECTRUM_MEASUREMENT
  66. #define VS "s"
  67. #else
  68. #define VS
  69. #endif
  70. #define DRV_VERSION IWLWIFI_VERSION VD VS
  71. MODULE_DESCRIPTION(DRV_DESCRIPTION);
  72. MODULE_VERSION(DRV_VERSION);
  73. MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
  74. MODULE_LICENSE("GPL");
  75. MODULE_ALIAS("iwl4965");
  76. /*************** STATION TABLE MANAGEMENT ****
  77. * mac80211 should be examined to determine if sta_info is duplicating
  78. * the functionality provided here
  79. */
  80. /**************************************************************/
  81. /**
  82. * iwl_commit_rxon - commit staging_rxon to hardware
  83. *
  84. * The RXON command in staging_rxon is committed to the hardware and
  85. * the active_rxon structure is updated with the new data. This
  86. * function correctly transitions out of the RXON_ASSOC_MSK state if
  87. * a HW tune is required based on the RXON structure changes.
  88. */
  89. int iwl_commit_rxon(struct iwl_priv *priv)
  90. {
  91. /* cast away the const for active_rxon in this function */
  92. struct iwl_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
  93. int ret;
  94. bool new_assoc =
  95. !!(priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK);
  96. if (!iwl_is_alive(priv))
  97. return -EBUSY;
  98. /* always get timestamp with Rx frame */
  99. priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
  100. ret = iwl_check_rxon_cmd(priv);
  101. if (ret) {
  102. IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n");
  103. return -EINVAL;
  104. }
  105. /* If we don't need to send a full RXON, we can use
  106. * iwl_rxon_assoc_cmd which is used to reconfigure filter
  107. * and other flags for the current radio configuration. */
  108. if (!iwl_full_rxon_required(priv)) {
  109. ret = iwl_send_rxon_assoc(priv);
  110. if (ret) {
  111. IWL_ERR(priv, "Error setting RXON_ASSOC (%d)\n", ret);
  112. return ret;
  113. }
  114. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  115. iwl_print_rx_config_cmd(priv);
  116. return 0;
  117. }
  118. /* station table will be cleared */
  119. priv->assoc_station_added = 0;
  120. /* If we are currently associated and the new config requires
  121. * an RXON_ASSOC and the new config wants the associated mask enabled,
  122. * we must clear the associated from the active configuration
  123. * before we apply the new config */
  124. if (iwl_is_associated(priv) && new_assoc) {
  125. IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
  126. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  127. ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
  128. sizeof(struct iwl_rxon_cmd),
  129. &priv->active_rxon);
  130. /* If the mask clearing failed then we set
  131. * active_rxon back to what it was previously */
  132. if (ret) {
  133. active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
  134. IWL_ERR(priv, "Error clearing ASSOC_MSK (%d)\n", ret);
  135. return ret;
  136. }
  137. }
  138. IWL_DEBUG_INFO(priv, "Sending RXON\n"
  139. "* with%s RXON_FILTER_ASSOC_MSK\n"
  140. "* channel = %d\n"
  141. "* bssid = %pM\n",
  142. (new_assoc ? "" : "out"),
  143. le16_to_cpu(priv->staging_rxon.channel),
  144. priv->staging_rxon.bssid_addr);
  145. iwl_set_rxon_hwcrypto(priv, !priv->cfg->mod_params->sw_crypto);
  146. /* Apply the new configuration
  147. * RXON unassoc clears the station table in uCode, send it before
  148. * we add the bcast station. If assoc bit is set, we will send RXON
  149. * after having added the bcast and bssid station.
  150. */
  151. if (!new_assoc) {
  152. ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
  153. sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
  154. if (ret) {
  155. IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
  156. return ret;
  157. }
  158. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  159. }
  160. iwl_clear_stations_table(priv);
  161. priv->start_calib = 0;
  162. /* Add the broadcast address so we can send broadcast frames */
  163. iwl_add_bcast_station(priv);
  164. /* If we have set the ASSOC_MSK and we are in BSS mode then
  165. * add the IWL_AP_ID to the station rate table */
  166. if (new_assoc) {
  167. if (priv->iw_mode == NL80211_IFTYPE_STATION) {
  168. ret = iwl_rxon_add_station(priv,
  169. priv->active_rxon.bssid_addr, 1);
  170. if (ret == IWL_INVALID_STATION) {
  171. IWL_ERR(priv,
  172. "Error adding AP address for TX.\n");
  173. return -EIO;
  174. }
  175. priv->assoc_station_added = 1;
  176. if (priv->default_wep_key &&
  177. iwl_send_static_wepkey_cmd(priv, 0))
  178. IWL_ERR(priv,
  179. "Could not send WEP static key.\n");
  180. }
  181. /*
  182. * allow CTS-to-self if possible for new association.
  183. * this is relevant only for 5000 series and up,
  184. * but will not damage 4965
  185. */
  186. priv->staging_rxon.flags |= RXON_FLG_SELF_CTS_EN;
  187. /* Apply the new configuration
  188. * RXON assoc doesn't clear the station table in uCode,
  189. */
  190. ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
  191. sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
  192. if (ret) {
  193. IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
  194. return ret;
  195. }
  196. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  197. }
  198. iwl_print_rx_config_cmd(priv);
  199. iwl_init_sensitivity(priv);
  200. /* If we issue a new RXON command which required a tune then we must
  201. * send a new TXPOWER command or we won't be able to Tx any frames */
  202. ret = iwl_set_tx_power(priv, priv->tx_power_user_lmt, true);
  203. if (ret) {
  204. IWL_ERR(priv, "Error sending TX power (%d)\n", ret);
  205. return ret;
  206. }
  207. return 0;
  208. }
  209. void iwl_update_chain_flags(struct iwl_priv *priv)
  210. {
  211. if (priv->cfg->ops->hcmd->set_rxon_chain)
  212. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  213. iwlcore_commit_rxon(priv);
  214. }
  215. static void iwl_clear_free_frames(struct iwl_priv *priv)
  216. {
  217. struct list_head *element;
  218. IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
  219. priv->frames_count);
  220. while (!list_empty(&priv->free_frames)) {
  221. element = priv->free_frames.next;
  222. list_del(element);
  223. kfree(list_entry(element, struct iwl_frame, list));
  224. priv->frames_count--;
  225. }
  226. if (priv->frames_count) {
  227. IWL_WARN(priv, "%d frames still in use. Did we lose one?\n",
  228. priv->frames_count);
  229. priv->frames_count = 0;
  230. }
  231. }
  232. static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv)
  233. {
  234. struct iwl_frame *frame;
  235. struct list_head *element;
  236. if (list_empty(&priv->free_frames)) {
  237. frame = kzalloc(sizeof(*frame), GFP_KERNEL);
  238. if (!frame) {
  239. IWL_ERR(priv, "Could not allocate frame!\n");
  240. return NULL;
  241. }
  242. priv->frames_count++;
  243. return frame;
  244. }
  245. element = priv->free_frames.next;
  246. list_del(element);
  247. return list_entry(element, struct iwl_frame, list);
  248. }
  249. static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame)
  250. {
  251. memset(frame, 0, sizeof(*frame));
  252. list_add(&frame->list, &priv->free_frames);
  253. }
  254. static unsigned int iwl_fill_beacon_frame(struct iwl_priv *priv,
  255. struct ieee80211_hdr *hdr,
  256. int left)
  257. {
  258. if (!iwl_is_associated(priv) || !priv->ibss_beacon ||
  259. ((priv->iw_mode != NL80211_IFTYPE_ADHOC) &&
  260. (priv->iw_mode != NL80211_IFTYPE_AP)))
  261. return 0;
  262. if (priv->ibss_beacon->len > left)
  263. return 0;
  264. memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
  265. return priv->ibss_beacon->len;
  266. }
  267. static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
  268. struct iwl_frame *frame, u8 rate)
  269. {
  270. struct iwl_tx_beacon_cmd *tx_beacon_cmd;
  271. unsigned int frame_size;
  272. tx_beacon_cmd = &frame->u.beacon;
  273. memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
  274. tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
  275. tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  276. frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame,
  277. sizeof(frame->u) - sizeof(*tx_beacon_cmd));
  278. BUG_ON(frame_size > MAX_MPDU_SIZE);
  279. tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
  280. if ((rate == IWL_RATE_1M_PLCP) || (rate >= IWL_RATE_2M_PLCP))
  281. tx_beacon_cmd->tx.rate_n_flags =
  282. iwl_hw_set_rate_n_flags(rate, RATE_MCS_CCK_MSK);
  283. else
  284. tx_beacon_cmd->tx.rate_n_flags =
  285. iwl_hw_set_rate_n_flags(rate, 0);
  286. tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
  287. TX_CMD_FLG_TSF_MSK |
  288. TX_CMD_FLG_STA_RATE_MSK;
  289. return sizeof(*tx_beacon_cmd) + frame_size;
  290. }
  291. static int iwl_send_beacon_cmd(struct iwl_priv *priv)
  292. {
  293. struct iwl_frame *frame;
  294. unsigned int frame_size;
  295. int rc;
  296. u8 rate;
  297. frame = iwl_get_free_frame(priv);
  298. if (!frame) {
  299. IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
  300. "command.\n");
  301. return -ENOMEM;
  302. }
  303. rate = iwl_rate_get_lowest_plcp(priv);
  304. frame_size = iwl_hw_get_beacon_cmd(priv, frame, rate);
  305. rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
  306. &frame->u.cmd[0]);
  307. iwl_free_frame(priv, frame);
  308. return rc;
  309. }
  310. static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
  311. {
  312. struct iwl_tfd_tb *tb = &tfd->tbs[idx];
  313. dma_addr_t addr = get_unaligned_le32(&tb->lo);
  314. if (sizeof(dma_addr_t) > sizeof(u32))
  315. addr |=
  316. ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
  317. return addr;
  318. }
  319. static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
  320. {
  321. struct iwl_tfd_tb *tb = &tfd->tbs[idx];
  322. return le16_to_cpu(tb->hi_n_len) >> 4;
  323. }
  324. static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
  325. dma_addr_t addr, u16 len)
  326. {
  327. struct iwl_tfd_tb *tb = &tfd->tbs[idx];
  328. u16 hi_n_len = len << 4;
  329. put_unaligned_le32(addr, &tb->lo);
  330. if (sizeof(dma_addr_t) > sizeof(u32))
  331. hi_n_len |= ((addr >> 16) >> 16) & 0xF;
  332. tb->hi_n_len = cpu_to_le16(hi_n_len);
  333. tfd->num_tbs = idx + 1;
  334. }
  335. static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
  336. {
  337. return tfd->num_tbs & 0x1f;
  338. }
  339. /**
  340. * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
  341. * @priv - driver private data
  342. * @txq - tx queue
  343. *
  344. * Does NOT advance any TFD circular buffer read/write indexes
  345. * Does NOT free the TFD itself (which is within circular buffer)
  346. */
  347. void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
  348. {
  349. struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds;
  350. struct iwl_tfd *tfd;
  351. struct pci_dev *dev = priv->pci_dev;
  352. int index = txq->q.read_ptr;
  353. int i;
  354. int num_tbs;
  355. tfd = &tfd_tmp[index];
  356. /* Sanity check on number of chunks */
  357. num_tbs = iwl_tfd_get_num_tbs(tfd);
  358. if (num_tbs >= IWL_NUM_OF_TBS) {
  359. IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
  360. /* @todo issue fatal error, it is quite serious situation */
  361. return;
  362. }
  363. /* Unmap tx_cmd */
  364. if (num_tbs)
  365. pci_unmap_single(dev,
  366. pci_unmap_addr(&txq->meta[index], mapping),
  367. pci_unmap_len(&txq->meta[index], len),
  368. PCI_DMA_BIDIRECTIONAL);
  369. /* Unmap chunks, if any. */
  370. for (i = 1; i < num_tbs; i++) {
  371. pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i),
  372. iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE);
  373. if (txq->txb) {
  374. dev_kfree_skb(txq->txb[txq->q.read_ptr].skb[i - 1]);
  375. txq->txb[txq->q.read_ptr].skb[i - 1] = NULL;
  376. }
  377. }
  378. }
  379. int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
  380. struct iwl_tx_queue *txq,
  381. dma_addr_t addr, u16 len,
  382. u8 reset, u8 pad)
  383. {
  384. struct iwl_queue *q;
  385. struct iwl_tfd *tfd, *tfd_tmp;
  386. u32 num_tbs;
  387. q = &txq->q;
  388. tfd_tmp = (struct iwl_tfd *)txq->tfds;
  389. tfd = &tfd_tmp[q->write_ptr];
  390. if (reset)
  391. memset(tfd, 0, sizeof(*tfd));
  392. num_tbs = iwl_tfd_get_num_tbs(tfd);
  393. /* Each TFD can point to a maximum 20 Tx buffers */
  394. if (num_tbs >= IWL_NUM_OF_TBS) {
  395. IWL_ERR(priv, "Error can not send more than %d chunks\n",
  396. IWL_NUM_OF_TBS);
  397. return -EINVAL;
  398. }
  399. BUG_ON(addr & ~DMA_BIT_MASK(36));
  400. if (unlikely(addr & ~IWL_TX_DMA_MASK))
  401. IWL_ERR(priv, "Unaligned address = %llx\n",
  402. (unsigned long long)addr);
  403. iwl_tfd_set_tb(tfd, num_tbs, addr, len);
  404. return 0;
  405. }
  406. /*
  407. * Tell nic where to find circular buffer of Tx Frame Descriptors for
  408. * given Tx queue, and enable the DMA channel used for that queue.
  409. *
  410. * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
  411. * channels supported in hardware.
  412. */
  413. int iwl_hw_tx_queue_init(struct iwl_priv *priv,
  414. struct iwl_tx_queue *txq)
  415. {
  416. int txq_id = txq->q.id;
  417. /* Circular buffer (TFD queue in DRAM) physical base address */
  418. iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
  419. txq->q.dma_addr >> 8);
  420. return 0;
  421. }
  422. /******************************************************************************
  423. *
  424. * Generic RX handler implementations
  425. *
  426. ******************************************************************************/
  427. static void iwl_rx_reply_alive(struct iwl_priv *priv,
  428. struct iwl_rx_mem_buffer *rxb)
  429. {
  430. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  431. struct iwl_alive_resp *palive;
  432. struct delayed_work *pwork;
  433. palive = &pkt->u.alive_frame;
  434. IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
  435. "0x%01X 0x%01X\n",
  436. palive->is_valid, palive->ver_type,
  437. palive->ver_subtype);
  438. if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
  439. IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
  440. memcpy(&priv->card_alive_init,
  441. &pkt->u.alive_frame,
  442. sizeof(struct iwl_init_alive_resp));
  443. pwork = &priv->init_alive_start;
  444. } else {
  445. IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
  446. memcpy(&priv->card_alive, &pkt->u.alive_frame,
  447. sizeof(struct iwl_alive_resp));
  448. pwork = &priv->alive_start;
  449. }
  450. /* We delay the ALIVE response by 5ms to
  451. * give the HW RF Kill time to activate... */
  452. if (palive->is_valid == UCODE_VALID_OK)
  453. queue_delayed_work(priv->workqueue, pwork,
  454. msecs_to_jiffies(5));
  455. else
  456. IWL_WARN(priv, "uCode did not respond OK.\n");
  457. }
  458. static void iwl_bg_beacon_update(struct work_struct *work)
  459. {
  460. struct iwl_priv *priv =
  461. container_of(work, struct iwl_priv, beacon_update);
  462. struct sk_buff *beacon;
  463. /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
  464. beacon = ieee80211_beacon_get(priv->hw, priv->vif);
  465. if (!beacon) {
  466. IWL_ERR(priv, "update beacon failed\n");
  467. return;
  468. }
  469. mutex_lock(&priv->mutex);
  470. /* new beacon skb is allocated every time; dispose previous.*/
  471. if (priv->ibss_beacon)
  472. dev_kfree_skb(priv->ibss_beacon);
  473. priv->ibss_beacon = beacon;
  474. mutex_unlock(&priv->mutex);
  475. iwl_send_beacon_cmd(priv);
  476. }
  477. /**
  478. * iwl_bg_statistics_periodic - Timer callback to queue statistics
  479. *
  480. * This callback is provided in order to send a statistics request.
  481. *
  482. * This timer function is continually reset to execute within
  483. * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
  484. * was received. We need to ensure we receive the statistics in order
  485. * to update the temperature used for calibrating the TXPOWER.
  486. */
  487. static void iwl_bg_statistics_periodic(unsigned long data)
  488. {
  489. struct iwl_priv *priv = (struct iwl_priv *)data;
  490. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  491. return;
  492. /* dont send host command if rf-kill is on */
  493. if (!iwl_is_ready_rf(priv))
  494. return;
  495. iwl_send_statistics_request(priv, CMD_ASYNC);
  496. }
  497. static void iwl_rx_beacon_notif(struct iwl_priv *priv,
  498. struct iwl_rx_mem_buffer *rxb)
  499. {
  500. #ifdef CONFIG_IWLWIFI_DEBUG
  501. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  502. struct iwl4965_beacon_notif *beacon =
  503. (struct iwl4965_beacon_notif *)pkt->u.raw;
  504. u8 rate = iwl_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
  505. IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d "
  506. "tsf %d %d rate %d\n",
  507. le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK,
  508. beacon->beacon_notify_hdr.failure_frame,
  509. le32_to_cpu(beacon->ibss_mgr_status),
  510. le32_to_cpu(beacon->high_tsf),
  511. le32_to_cpu(beacon->low_tsf), rate);
  512. #endif
  513. if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
  514. (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
  515. queue_work(priv->workqueue, &priv->beacon_update);
  516. }
  517. /* Handle notification from uCode that card's power state is changing
  518. * due to software, hardware, or critical temperature RFKILL */
  519. static void iwl_rx_card_state_notif(struct iwl_priv *priv,
  520. struct iwl_rx_mem_buffer *rxb)
  521. {
  522. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  523. u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
  524. unsigned long status = priv->status;
  525. IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s\n",
  526. (flags & HW_CARD_DISABLED) ? "Kill" : "On",
  527. (flags & SW_CARD_DISABLED) ? "Kill" : "On");
  528. if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED |
  529. RF_CARD_DISABLED)) {
  530. iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
  531. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  532. iwl_write_direct32(priv, HBUS_TARG_MBX_C,
  533. HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
  534. if (!(flags & RXON_CARD_DISABLED)) {
  535. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  536. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  537. iwl_write_direct32(priv, HBUS_TARG_MBX_C,
  538. HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
  539. }
  540. if (flags & RF_CARD_DISABLED)
  541. iwl_tt_enter_ct_kill(priv);
  542. }
  543. if (!(flags & RF_CARD_DISABLED))
  544. iwl_tt_exit_ct_kill(priv);
  545. if (flags & HW_CARD_DISABLED)
  546. set_bit(STATUS_RF_KILL_HW, &priv->status);
  547. else
  548. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  549. if (!(flags & RXON_CARD_DISABLED))
  550. iwl_scan_cancel(priv);
  551. if ((test_bit(STATUS_RF_KILL_HW, &status) !=
  552. test_bit(STATUS_RF_KILL_HW, &priv->status)))
  553. wiphy_rfkill_set_hw_state(priv->hw->wiphy,
  554. test_bit(STATUS_RF_KILL_HW, &priv->status));
  555. else
  556. wake_up_interruptible(&priv->wait_command_queue);
  557. }
  558. int iwl_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
  559. {
  560. if (src == IWL_PWR_SRC_VAUX) {
  561. if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
  562. iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
  563. APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
  564. ~APMG_PS_CTRL_MSK_PWR_SRC);
  565. } else {
  566. iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
  567. APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
  568. ~APMG_PS_CTRL_MSK_PWR_SRC);
  569. }
  570. return 0;
  571. }
  572. /**
  573. * iwl_setup_rx_handlers - Initialize Rx handler callbacks
  574. *
  575. * Setup the RX handlers for each of the reply types sent from the uCode
  576. * to the host.
  577. *
  578. * This function chains into the hardware specific files for them to setup
  579. * any hardware specific handlers as well.
  580. */
  581. static void iwl_setup_rx_handlers(struct iwl_priv *priv)
  582. {
  583. priv->rx_handlers[REPLY_ALIVE] = iwl_rx_reply_alive;
  584. priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error;
  585. priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa;
  586. priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif;
  587. priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
  588. iwl_rx_pm_debug_statistics_notif;
  589. priv->rx_handlers[BEACON_NOTIFICATION] = iwl_rx_beacon_notif;
  590. /*
  591. * The same handler is used for both the REPLY to a discrete
  592. * statistics request from the host as well as for the periodic
  593. * statistics notifications (after received beacons) from the uCode.
  594. */
  595. priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl_rx_statistics;
  596. priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl_rx_statistics;
  597. iwl_setup_spectrum_handlers(priv);
  598. iwl_setup_rx_scan_handlers(priv);
  599. /* status change handler */
  600. priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl_rx_card_state_notif;
  601. priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
  602. iwl_rx_missed_beacon_notif;
  603. /* Rx handlers */
  604. priv->rx_handlers[REPLY_RX_PHY_CMD] = iwl_rx_reply_rx_phy;
  605. priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwl_rx_reply_rx;
  606. /* block ack */
  607. priv->rx_handlers[REPLY_COMPRESSED_BA] = iwl_rx_reply_compressed_ba;
  608. /* Set up hardware specific Rx handlers */
  609. priv->cfg->ops->lib->rx_handler_setup(priv);
  610. }
  611. /**
  612. * iwl_rx_handle - Main entry function for receiving responses from uCode
  613. *
  614. * Uses the priv->rx_handlers callback function array to invoke
  615. * the appropriate handlers, including command responses,
  616. * frame-received notifications, and other notifications.
  617. */
  618. void iwl_rx_handle(struct iwl_priv *priv)
  619. {
  620. struct iwl_rx_mem_buffer *rxb;
  621. struct iwl_rx_packet *pkt;
  622. struct iwl_rx_queue *rxq = &priv->rxq;
  623. u32 r, i;
  624. int reclaim;
  625. unsigned long flags;
  626. u8 fill_rx = 0;
  627. u32 count = 8;
  628. int total_empty;
  629. /* uCode's read index (stored in shared DRAM) indicates the last Rx
  630. * buffer that the driver may process (last buffer filled by ucode). */
  631. r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
  632. i = rxq->read;
  633. /* Rx interrupt, but nothing sent from uCode */
  634. if (i == r)
  635. IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
  636. /* calculate total frames need to be restock after handling RX */
  637. total_empty = r - rxq->write_actual;
  638. if (total_empty < 0)
  639. total_empty += RX_QUEUE_SIZE;
  640. if (total_empty > (RX_QUEUE_SIZE / 2))
  641. fill_rx = 1;
  642. while (i != r) {
  643. rxb = rxq->queue[i];
  644. /* If an RXB doesn't have a Rx queue slot associated with it,
  645. * then a bug has been introduced in the queue refilling
  646. * routines -- catch it here */
  647. BUG_ON(rxb == NULL);
  648. rxq->queue[i] = NULL;
  649. pci_unmap_page(priv->pci_dev, rxb->page_dma,
  650. PAGE_SIZE << priv->hw_params.rx_page_order,
  651. PCI_DMA_FROMDEVICE);
  652. pkt = rxb_addr(rxb);
  653. trace_iwlwifi_dev_rx(priv, pkt,
  654. le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK);
  655. /* Reclaim a command buffer only if this packet is a response
  656. * to a (driver-originated) command.
  657. * If the packet (e.g. Rx frame) originated from uCode,
  658. * there is no command buffer to reclaim.
  659. * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
  660. * but apparently a few don't get set; catch them here. */
  661. reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
  662. (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
  663. (pkt->hdr.cmd != REPLY_RX) &&
  664. (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
  665. (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
  666. (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
  667. (pkt->hdr.cmd != REPLY_TX);
  668. /* Based on type of command response or notification,
  669. * handle those that need handling via function in
  670. * rx_handlers table. See iwl_setup_rx_handlers() */
  671. if (priv->rx_handlers[pkt->hdr.cmd]) {
  672. IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
  673. i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
  674. priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
  675. priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
  676. } else {
  677. /* No handling needed */
  678. IWL_DEBUG_RX(priv,
  679. "r %d i %d No handler needed for %s, 0x%02x\n",
  680. r, i, get_cmd_string(pkt->hdr.cmd),
  681. pkt->hdr.cmd);
  682. }
  683. /*
  684. * XXX: After here, we should always check rxb->page
  685. * against NULL before touching it or its virtual
  686. * memory (pkt). Because some rx_handler might have
  687. * already taken or freed the pages.
  688. */
  689. if (reclaim) {
  690. /* Invoke any callbacks, transfer the buffer to caller,
  691. * and fire off the (possibly) blocking iwl_send_cmd()
  692. * as we reclaim the driver command queue */
  693. if (rxb->page)
  694. iwl_tx_cmd_complete(priv, rxb);
  695. else
  696. IWL_WARN(priv, "Claim null rxb?\n");
  697. }
  698. /* Reuse the page if possible. For notification packets and
  699. * SKBs that fail to Rx correctly, add them back into the
  700. * rx_free list for reuse later. */
  701. spin_lock_irqsave(&rxq->lock, flags);
  702. if (rxb->page != NULL) {
  703. rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page,
  704. 0, PAGE_SIZE << priv->hw_params.rx_page_order,
  705. PCI_DMA_FROMDEVICE);
  706. list_add_tail(&rxb->list, &rxq->rx_free);
  707. rxq->free_count++;
  708. } else
  709. list_add_tail(&rxb->list, &rxq->rx_used);
  710. spin_unlock_irqrestore(&rxq->lock, flags);
  711. i = (i + 1) & RX_QUEUE_MASK;
  712. /* If there are a lot of unused frames,
  713. * restock the Rx queue so ucode wont assert. */
  714. if (fill_rx) {
  715. count++;
  716. if (count >= 8) {
  717. rxq->read = i;
  718. iwl_rx_replenish_now(priv);
  719. count = 0;
  720. }
  721. }
  722. }
  723. /* Backtrack one entry */
  724. rxq->read = i;
  725. if (fill_rx)
  726. iwl_rx_replenish_now(priv);
  727. else
  728. iwl_rx_queue_restock(priv);
  729. }
  730. /* call this function to flush any scheduled tasklet */
  731. static inline void iwl_synchronize_irq(struct iwl_priv *priv)
  732. {
  733. /* wait to make sure we flush pending tasklet*/
  734. synchronize_irq(priv->pci_dev->irq);
  735. tasklet_kill(&priv->irq_tasklet);
  736. }
  737. static void iwl_irq_tasklet_legacy(struct iwl_priv *priv)
  738. {
  739. u32 inta, handled = 0;
  740. u32 inta_fh;
  741. unsigned long flags;
  742. u32 i;
  743. #ifdef CONFIG_IWLWIFI_DEBUG
  744. u32 inta_mask;
  745. #endif
  746. spin_lock_irqsave(&priv->lock, flags);
  747. /* Ack/clear/reset pending uCode interrupts.
  748. * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
  749. * and will clear only when CSR_FH_INT_STATUS gets cleared. */
  750. inta = iwl_read32(priv, CSR_INT);
  751. iwl_write32(priv, CSR_INT, inta);
  752. /* Ack/clear/reset pending flow-handler (DMA) interrupts.
  753. * Any new interrupts that happen after this, either while we're
  754. * in this tasklet, or later, will show up in next ISR/tasklet. */
  755. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  756. iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
  757. #ifdef CONFIG_IWLWIFI_DEBUG
  758. if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
  759. /* just for debug */
  760. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  761. IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
  762. inta, inta_mask, inta_fh);
  763. }
  764. #endif
  765. spin_unlock_irqrestore(&priv->lock, flags);
  766. /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
  767. * atomic, make sure that inta covers all the interrupts that
  768. * we've discovered, even if FH interrupt came in just after
  769. * reading CSR_INT. */
  770. if (inta_fh & CSR49_FH_INT_RX_MASK)
  771. inta |= CSR_INT_BIT_FH_RX;
  772. if (inta_fh & CSR49_FH_INT_TX_MASK)
  773. inta |= CSR_INT_BIT_FH_TX;
  774. /* Now service all interrupt bits discovered above. */
  775. if (inta & CSR_INT_BIT_HW_ERR) {
  776. IWL_ERR(priv, "Hardware error detected. Restarting.\n");
  777. /* Tell the device to stop sending interrupts */
  778. iwl_disable_interrupts(priv);
  779. priv->isr_stats.hw++;
  780. iwl_irq_handle_error(priv);
  781. handled |= CSR_INT_BIT_HW_ERR;
  782. return;
  783. }
  784. #ifdef CONFIG_IWLWIFI_DEBUG
  785. if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
  786. /* NIC fires this, but we don't use it, redundant with WAKEUP */
  787. if (inta & CSR_INT_BIT_SCD) {
  788. IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
  789. "the frame/frames.\n");
  790. priv->isr_stats.sch++;
  791. }
  792. /* Alive notification via Rx interrupt will do the real work */
  793. if (inta & CSR_INT_BIT_ALIVE) {
  794. IWL_DEBUG_ISR(priv, "Alive interrupt\n");
  795. priv->isr_stats.alive++;
  796. }
  797. }
  798. #endif
  799. /* Safely ignore these bits for debug checks below */
  800. inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
  801. /* HW RF KILL switch toggled */
  802. if (inta & CSR_INT_BIT_RF_KILL) {
  803. int hw_rf_kill = 0;
  804. if (!(iwl_read32(priv, CSR_GP_CNTRL) &
  805. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
  806. hw_rf_kill = 1;
  807. IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
  808. hw_rf_kill ? "disable radio" : "enable radio");
  809. priv->isr_stats.rfkill++;
  810. /* driver only loads ucode once setting the interface up.
  811. * the driver allows loading the ucode even if the radio
  812. * is killed. Hence update the killswitch state here. The
  813. * rfkill handler will care about restarting if needed.
  814. */
  815. if (!test_bit(STATUS_ALIVE, &priv->status)) {
  816. if (hw_rf_kill)
  817. set_bit(STATUS_RF_KILL_HW, &priv->status);
  818. else
  819. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  820. wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
  821. }
  822. handled |= CSR_INT_BIT_RF_KILL;
  823. }
  824. /* Chip got too hot and stopped itself */
  825. if (inta & CSR_INT_BIT_CT_KILL) {
  826. IWL_ERR(priv, "Microcode CT kill error detected.\n");
  827. priv->isr_stats.ctkill++;
  828. handled |= CSR_INT_BIT_CT_KILL;
  829. }
  830. /* Error detected by uCode */
  831. if (inta & CSR_INT_BIT_SW_ERR) {
  832. IWL_ERR(priv, "Microcode SW error detected. "
  833. " Restarting 0x%X.\n", inta);
  834. priv->isr_stats.sw++;
  835. priv->isr_stats.sw_err = inta;
  836. iwl_irq_handle_error(priv);
  837. handled |= CSR_INT_BIT_SW_ERR;
  838. }
  839. /*
  840. * uCode wakes up after power-down sleep.
  841. * Tell device about any new tx or host commands enqueued,
  842. * and about any Rx buffers made available while asleep.
  843. */
  844. if (inta & CSR_INT_BIT_WAKEUP) {
  845. IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
  846. iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
  847. for (i = 0; i < priv->hw_params.max_txq_num; i++)
  848. iwl_txq_update_write_ptr(priv, &priv->txq[i]);
  849. priv->isr_stats.wakeup++;
  850. handled |= CSR_INT_BIT_WAKEUP;
  851. }
  852. /* All uCode command responses, including Tx command responses,
  853. * Rx "responses" (frame-received notification), and other
  854. * notifications from uCode come through here*/
  855. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
  856. iwl_rx_handle(priv);
  857. priv->isr_stats.rx++;
  858. iwl_leds_background(priv);
  859. handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
  860. }
  861. /* This "Tx" DMA channel is used only for loading uCode */
  862. if (inta & CSR_INT_BIT_FH_TX) {
  863. IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
  864. priv->isr_stats.tx++;
  865. handled |= CSR_INT_BIT_FH_TX;
  866. /* Wake up uCode load routine, now that load is complete */
  867. priv->ucode_write_complete = 1;
  868. wake_up_interruptible(&priv->wait_command_queue);
  869. }
  870. if (inta & ~handled) {
  871. IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
  872. priv->isr_stats.unhandled++;
  873. }
  874. if (inta & ~(priv->inta_mask)) {
  875. IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
  876. inta & ~priv->inta_mask);
  877. IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh);
  878. }
  879. /* Re-enable all interrupts */
  880. /* only Re-enable if diabled by irq */
  881. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  882. iwl_enable_interrupts(priv);
  883. #ifdef CONFIG_IWLWIFI_DEBUG
  884. if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
  885. inta = iwl_read32(priv, CSR_INT);
  886. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  887. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  888. IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
  889. "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
  890. }
  891. #endif
  892. }
  893. /* tasklet for iwlagn interrupt */
  894. static void iwl_irq_tasklet(struct iwl_priv *priv)
  895. {
  896. u32 inta = 0;
  897. u32 handled = 0;
  898. unsigned long flags;
  899. #ifdef CONFIG_IWLWIFI_DEBUG
  900. u32 inta_mask;
  901. #endif
  902. spin_lock_irqsave(&priv->lock, flags);
  903. /* Ack/clear/reset pending uCode interrupts.
  904. * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
  905. */
  906. iwl_write32(priv, CSR_INT, priv->inta);
  907. inta = priv->inta;
  908. #ifdef CONFIG_IWLWIFI_DEBUG
  909. if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
  910. /* just for debug */
  911. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  912. IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ",
  913. inta, inta_mask);
  914. }
  915. #endif
  916. spin_unlock_irqrestore(&priv->lock, flags);
  917. /* saved interrupt in inta variable now we can reset priv->inta */
  918. priv->inta = 0;
  919. /* Now service all interrupt bits discovered above. */
  920. if (inta & CSR_INT_BIT_HW_ERR) {
  921. IWL_ERR(priv, "Hardware error detected. Restarting.\n");
  922. /* Tell the device to stop sending interrupts */
  923. iwl_disable_interrupts(priv);
  924. priv->isr_stats.hw++;
  925. iwl_irq_handle_error(priv);
  926. handled |= CSR_INT_BIT_HW_ERR;
  927. return;
  928. }
  929. #ifdef CONFIG_IWLWIFI_DEBUG
  930. if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
  931. /* NIC fires this, but we don't use it, redundant with WAKEUP */
  932. if (inta & CSR_INT_BIT_SCD) {
  933. IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
  934. "the frame/frames.\n");
  935. priv->isr_stats.sch++;
  936. }
  937. /* Alive notification via Rx interrupt will do the real work */
  938. if (inta & CSR_INT_BIT_ALIVE) {
  939. IWL_DEBUG_ISR(priv, "Alive interrupt\n");
  940. priv->isr_stats.alive++;
  941. }
  942. }
  943. #endif
  944. /* Safely ignore these bits for debug checks below */
  945. inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
  946. /* HW RF KILL switch toggled */
  947. if (inta & CSR_INT_BIT_RF_KILL) {
  948. int hw_rf_kill = 0;
  949. if (!(iwl_read32(priv, CSR_GP_CNTRL) &
  950. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
  951. hw_rf_kill = 1;
  952. IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
  953. hw_rf_kill ? "disable radio" : "enable radio");
  954. priv->isr_stats.rfkill++;
  955. /* driver only loads ucode once setting the interface up.
  956. * the driver allows loading the ucode even if the radio
  957. * is killed. Hence update the killswitch state here. The
  958. * rfkill handler will care about restarting if needed.
  959. */
  960. if (!test_bit(STATUS_ALIVE, &priv->status)) {
  961. if (hw_rf_kill)
  962. set_bit(STATUS_RF_KILL_HW, &priv->status);
  963. else
  964. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  965. wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
  966. }
  967. handled |= CSR_INT_BIT_RF_KILL;
  968. }
  969. /* Chip got too hot and stopped itself */
  970. if (inta & CSR_INT_BIT_CT_KILL) {
  971. IWL_ERR(priv, "Microcode CT kill error detected.\n");
  972. priv->isr_stats.ctkill++;
  973. handled |= CSR_INT_BIT_CT_KILL;
  974. }
  975. /* Error detected by uCode */
  976. if (inta & CSR_INT_BIT_SW_ERR) {
  977. IWL_ERR(priv, "Microcode SW error detected. "
  978. " Restarting 0x%X.\n", inta);
  979. priv->isr_stats.sw++;
  980. priv->isr_stats.sw_err = inta;
  981. iwl_irq_handle_error(priv);
  982. handled |= CSR_INT_BIT_SW_ERR;
  983. }
  984. /* uCode wakes up after power-down sleep */
  985. if (inta & CSR_INT_BIT_WAKEUP) {
  986. IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
  987. iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
  988. iwl_txq_update_write_ptr(priv, &priv->txq[0]);
  989. iwl_txq_update_write_ptr(priv, &priv->txq[1]);
  990. iwl_txq_update_write_ptr(priv, &priv->txq[2]);
  991. iwl_txq_update_write_ptr(priv, &priv->txq[3]);
  992. iwl_txq_update_write_ptr(priv, &priv->txq[4]);
  993. iwl_txq_update_write_ptr(priv, &priv->txq[5]);
  994. priv->isr_stats.wakeup++;
  995. handled |= CSR_INT_BIT_WAKEUP;
  996. }
  997. /* All uCode command responses, including Tx command responses,
  998. * Rx "responses" (frame-received notification), and other
  999. * notifications from uCode come through here*/
  1000. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
  1001. CSR_INT_BIT_RX_PERIODIC)) {
  1002. IWL_DEBUG_ISR(priv, "Rx interrupt\n");
  1003. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
  1004. handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
  1005. iwl_write32(priv, CSR_FH_INT_STATUS,
  1006. CSR49_FH_INT_RX_MASK);
  1007. }
  1008. if (inta & CSR_INT_BIT_RX_PERIODIC) {
  1009. handled |= CSR_INT_BIT_RX_PERIODIC;
  1010. iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC);
  1011. }
  1012. /* Sending RX interrupt require many steps to be done in the
  1013. * the device:
  1014. * 1- write interrupt to current index in ICT table.
  1015. * 2- dma RX frame.
  1016. * 3- update RX shared data to indicate last write index.
  1017. * 4- send interrupt.
  1018. * This could lead to RX race, driver could receive RX interrupt
  1019. * but the shared data changes does not reflect this.
  1020. * this could lead to RX race, RX periodic will solve this race
  1021. */
  1022. iwl_write32(priv, CSR_INT_PERIODIC_REG,
  1023. CSR_INT_PERIODIC_DIS);
  1024. iwl_rx_handle(priv);
  1025. /* Only set RX periodic if real RX is received. */
  1026. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
  1027. iwl_write32(priv, CSR_INT_PERIODIC_REG,
  1028. CSR_INT_PERIODIC_ENA);
  1029. priv->isr_stats.rx++;
  1030. iwl_leds_background(priv);
  1031. }
  1032. /* This "Tx" DMA channel is used only for loading uCode */
  1033. if (inta & CSR_INT_BIT_FH_TX) {
  1034. iwl_write32(priv, CSR_FH_INT_STATUS, CSR49_FH_INT_TX_MASK);
  1035. IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
  1036. priv->isr_stats.tx++;
  1037. handled |= CSR_INT_BIT_FH_TX;
  1038. /* Wake up uCode load routine, now that load is complete */
  1039. priv->ucode_write_complete = 1;
  1040. wake_up_interruptible(&priv->wait_command_queue);
  1041. }
  1042. if (inta & ~handled) {
  1043. IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
  1044. priv->isr_stats.unhandled++;
  1045. }
  1046. if (inta & ~(priv->inta_mask)) {
  1047. IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
  1048. inta & ~priv->inta_mask);
  1049. }
  1050. /* Re-enable all interrupts */
  1051. /* only Re-enable if diabled by irq */
  1052. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  1053. iwl_enable_interrupts(priv);
  1054. }
  1055. /******************************************************************************
  1056. *
  1057. * uCode download functions
  1058. *
  1059. ******************************************************************************/
  1060. static void iwl_dealloc_ucode_pci(struct iwl_priv *priv)
  1061. {
  1062. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
  1063. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
  1064. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  1065. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
  1066. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  1067. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
  1068. }
  1069. static void iwl_nic_start(struct iwl_priv *priv)
  1070. {
  1071. /* Remove all resets to allow NIC to operate */
  1072. iwl_write32(priv, CSR_RESET, 0);
  1073. }
  1074. /**
  1075. * iwl_read_ucode - Read uCode images from disk file.
  1076. *
  1077. * Copy into buffers for card to fetch via bus-mastering
  1078. */
  1079. static int iwl_read_ucode(struct iwl_priv *priv)
  1080. {
  1081. struct iwl_ucode_header *ucode;
  1082. int ret = -EINVAL, index;
  1083. const struct firmware *ucode_raw;
  1084. const char *name_pre = priv->cfg->fw_name_pre;
  1085. const unsigned int api_max = priv->cfg->ucode_api_max;
  1086. const unsigned int api_min = priv->cfg->ucode_api_min;
  1087. char buf[25];
  1088. u8 *src;
  1089. size_t len;
  1090. u32 api_ver, build;
  1091. u32 inst_size, data_size, init_size, init_data_size, boot_size;
  1092. u16 eeprom_ver;
  1093. /* Ask kernel firmware_class module to get the boot firmware off disk.
  1094. * request_firmware() is synchronous, file is in memory on return. */
  1095. for (index = api_max; index >= api_min; index--) {
  1096. sprintf(buf, "%s%d%s", name_pre, index, ".ucode");
  1097. ret = request_firmware(&ucode_raw, buf, &priv->pci_dev->dev);
  1098. if (ret < 0) {
  1099. IWL_ERR(priv, "%s firmware file req failed: %d\n",
  1100. buf, ret);
  1101. if (ret == -ENOENT)
  1102. continue;
  1103. else
  1104. goto error;
  1105. } else {
  1106. if (index < api_max)
  1107. IWL_ERR(priv, "Loaded firmware %s, "
  1108. "which is deprecated. "
  1109. "Please use API v%u instead.\n",
  1110. buf, api_max);
  1111. IWL_DEBUG_INFO(priv, "Got firmware '%s' file (%zd bytes) from disk\n",
  1112. buf, ucode_raw->size);
  1113. break;
  1114. }
  1115. }
  1116. if (ret < 0)
  1117. goto error;
  1118. /* Make sure that we got at least the v1 header! */
  1119. if (ucode_raw->size < priv->cfg->ops->ucode->get_header_size(1)) {
  1120. IWL_ERR(priv, "File size way too small!\n");
  1121. ret = -EINVAL;
  1122. goto err_release;
  1123. }
  1124. /* Data from ucode file: header followed by uCode images */
  1125. ucode = (struct iwl_ucode_header *)ucode_raw->data;
  1126. priv->ucode_ver = le32_to_cpu(ucode->ver);
  1127. api_ver = IWL_UCODE_API(priv->ucode_ver);
  1128. build = priv->cfg->ops->ucode->get_build(ucode, api_ver);
  1129. inst_size = priv->cfg->ops->ucode->get_inst_size(ucode, api_ver);
  1130. data_size = priv->cfg->ops->ucode->get_data_size(ucode, api_ver);
  1131. init_size = priv->cfg->ops->ucode->get_init_size(ucode, api_ver);
  1132. init_data_size =
  1133. priv->cfg->ops->ucode->get_init_data_size(ucode, api_ver);
  1134. boot_size = priv->cfg->ops->ucode->get_boot_size(ucode, api_ver);
  1135. src = priv->cfg->ops->ucode->get_data(ucode, api_ver);
  1136. /* api_ver should match the api version forming part of the
  1137. * firmware filename ... but we don't check for that and only rely
  1138. * on the API version read from firmware header from here on forward */
  1139. if (api_ver < api_min || api_ver > api_max) {
  1140. IWL_ERR(priv, "Driver unable to support your firmware API. "
  1141. "Driver supports v%u, firmware is v%u.\n",
  1142. api_max, api_ver);
  1143. priv->ucode_ver = 0;
  1144. ret = -EINVAL;
  1145. goto err_release;
  1146. }
  1147. if (api_ver != api_max)
  1148. IWL_ERR(priv, "Firmware has old API version. Expected v%u, "
  1149. "got v%u. New firmware can be obtained "
  1150. "from http://www.intellinuxwireless.org.\n",
  1151. api_max, api_ver);
  1152. IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u\n",
  1153. IWL_UCODE_MAJOR(priv->ucode_ver),
  1154. IWL_UCODE_MINOR(priv->ucode_ver),
  1155. IWL_UCODE_API(priv->ucode_ver),
  1156. IWL_UCODE_SERIAL(priv->ucode_ver));
  1157. snprintf(priv->hw->wiphy->fw_version,
  1158. sizeof(priv->hw->wiphy->fw_version),
  1159. "%u.%u.%u.%u",
  1160. IWL_UCODE_MAJOR(priv->ucode_ver),
  1161. IWL_UCODE_MINOR(priv->ucode_ver),
  1162. IWL_UCODE_API(priv->ucode_ver),
  1163. IWL_UCODE_SERIAL(priv->ucode_ver));
  1164. if (build)
  1165. IWL_DEBUG_INFO(priv, "Build %u\n", build);
  1166. eeprom_ver = iwl_eeprom_query16(priv, EEPROM_VERSION);
  1167. IWL_DEBUG_INFO(priv, "NVM Type: %s, version: 0x%x\n",
  1168. (priv->nvm_device_type == NVM_DEVICE_TYPE_OTP)
  1169. ? "OTP" : "EEPROM", eeprom_ver);
  1170. IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
  1171. priv->ucode_ver);
  1172. IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %u\n",
  1173. inst_size);
  1174. IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %u\n",
  1175. data_size);
  1176. IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %u\n",
  1177. init_size);
  1178. IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %u\n",
  1179. init_data_size);
  1180. IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %u\n",
  1181. boot_size);
  1182. /* Verify size of file vs. image size info in file's header */
  1183. if (ucode_raw->size !=
  1184. priv->cfg->ops->ucode->get_header_size(api_ver) +
  1185. inst_size + data_size + init_size +
  1186. init_data_size + boot_size) {
  1187. IWL_DEBUG_INFO(priv,
  1188. "uCode file size %d does not match expected size\n",
  1189. (int)ucode_raw->size);
  1190. ret = -EINVAL;
  1191. goto err_release;
  1192. }
  1193. /* Verify that uCode images will fit in card's SRAM */
  1194. if (inst_size > priv->hw_params.max_inst_size) {
  1195. IWL_DEBUG_INFO(priv, "uCode instr len %d too large to fit in\n",
  1196. inst_size);
  1197. ret = -EINVAL;
  1198. goto err_release;
  1199. }
  1200. if (data_size > priv->hw_params.max_data_size) {
  1201. IWL_DEBUG_INFO(priv, "uCode data len %d too large to fit in\n",
  1202. data_size);
  1203. ret = -EINVAL;
  1204. goto err_release;
  1205. }
  1206. if (init_size > priv->hw_params.max_inst_size) {
  1207. IWL_INFO(priv, "uCode init instr len %d too large to fit in\n",
  1208. init_size);
  1209. ret = -EINVAL;
  1210. goto err_release;
  1211. }
  1212. if (init_data_size > priv->hw_params.max_data_size) {
  1213. IWL_INFO(priv, "uCode init data len %d too large to fit in\n",
  1214. init_data_size);
  1215. ret = -EINVAL;
  1216. goto err_release;
  1217. }
  1218. if (boot_size > priv->hw_params.max_bsm_size) {
  1219. IWL_INFO(priv, "uCode boot instr len %d too large to fit in\n",
  1220. boot_size);
  1221. ret = -EINVAL;
  1222. goto err_release;
  1223. }
  1224. /* Allocate ucode buffers for card's bus-master loading ... */
  1225. /* Runtime instructions and 2 copies of data:
  1226. * 1) unmodified from disk
  1227. * 2) backup cache for save/restore during power-downs */
  1228. priv->ucode_code.len = inst_size;
  1229. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
  1230. priv->ucode_data.len = data_size;
  1231. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
  1232. priv->ucode_data_backup.len = data_size;
  1233. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  1234. if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
  1235. !priv->ucode_data_backup.v_addr)
  1236. goto err_pci_alloc;
  1237. /* Initialization instructions and data */
  1238. if (init_size && init_data_size) {
  1239. priv->ucode_init.len = init_size;
  1240. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
  1241. priv->ucode_init_data.len = init_data_size;
  1242. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  1243. if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
  1244. goto err_pci_alloc;
  1245. }
  1246. /* Bootstrap (instructions only, no data) */
  1247. if (boot_size) {
  1248. priv->ucode_boot.len = boot_size;
  1249. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
  1250. if (!priv->ucode_boot.v_addr)
  1251. goto err_pci_alloc;
  1252. }
  1253. /* Copy images into buffers for card's bus-master reads ... */
  1254. /* Runtime instructions (first block of data in file) */
  1255. len = inst_size;
  1256. IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n", len);
  1257. memcpy(priv->ucode_code.v_addr, src, len);
  1258. src += len;
  1259. IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
  1260. priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
  1261. /* Runtime data (2nd block)
  1262. * NOTE: Copy into backup buffer will be done in iwl_up() */
  1263. len = data_size;
  1264. IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n", len);
  1265. memcpy(priv->ucode_data.v_addr, src, len);
  1266. memcpy(priv->ucode_data_backup.v_addr, src, len);
  1267. src += len;
  1268. /* Initialization instructions (3rd block) */
  1269. if (init_size) {
  1270. len = init_size;
  1271. IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n",
  1272. len);
  1273. memcpy(priv->ucode_init.v_addr, src, len);
  1274. src += len;
  1275. }
  1276. /* Initialization data (4th block) */
  1277. if (init_data_size) {
  1278. len = init_data_size;
  1279. IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n",
  1280. len);
  1281. memcpy(priv->ucode_init_data.v_addr, src, len);
  1282. src += len;
  1283. }
  1284. /* Bootstrap instructions (5th block) */
  1285. len = boot_size;
  1286. IWL_DEBUG_INFO(priv, "Copying (but not loading) boot instr len %Zd\n", len);
  1287. memcpy(priv->ucode_boot.v_addr, src, len);
  1288. /* We have our copies now, allow OS release its copies */
  1289. release_firmware(ucode_raw);
  1290. return 0;
  1291. err_pci_alloc:
  1292. IWL_ERR(priv, "failed to allocate pci memory\n");
  1293. ret = -ENOMEM;
  1294. iwl_dealloc_ucode_pci(priv);
  1295. err_release:
  1296. release_firmware(ucode_raw);
  1297. error:
  1298. return ret;
  1299. }
  1300. #ifdef CONFIG_IWLWIFI_DEBUG
  1301. static const char *desc_lookup_text[] = {
  1302. "OK",
  1303. "FAIL",
  1304. "BAD_PARAM",
  1305. "BAD_CHECKSUM",
  1306. "NMI_INTERRUPT_WDG",
  1307. "SYSASSERT",
  1308. "FATAL_ERROR",
  1309. "BAD_COMMAND",
  1310. "HW_ERROR_TUNE_LOCK",
  1311. "HW_ERROR_TEMPERATURE",
  1312. "ILLEGAL_CHAN_FREQ",
  1313. "VCC_NOT_STABLE",
  1314. "FH_ERROR",
  1315. "NMI_INTERRUPT_HOST",
  1316. "NMI_INTERRUPT_ACTION_PT",
  1317. "NMI_INTERRUPT_UNKNOWN",
  1318. "UCODE_VERSION_MISMATCH",
  1319. "HW_ERROR_ABS_LOCK",
  1320. "HW_ERROR_CAL_LOCK_FAIL",
  1321. "NMI_INTERRUPT_INST_ACTION_PT",
  1322. "NMI_INTERRUPT_DATA_ACTION_PT",
  1323. "NMI_TRM_HW_ER",
  1324. "NMI_INTERRUPT_TRM",
  1325. "NMI_INTERRUPT_BREAK_POINT"
  1326. "DEBUG_0",
  1327. "DEBUG_1",
  1328. "DEBUG_2",
  1329. "DEBUG_3",
  1330. "UNKNOWN"
  1331. };
  1332. static const char *desc_lookup(int i)
  1333. {
  1334. int max = ARRAY_SIZE(desc_lookup_text) - 1;
  1335. if (i < 0 || i > max)
  1336. i = max;
  1337. return desc_lookup_text[i];
  1338. }
  1339. #define ERROR_START_OFFSET (1 * sizeof(u32))
  1340. #define ERROR_ELEM_SIZE (7 * sizeof(u32))
  1341. void iwl_dump_nic_error_log(struct iwl_priv *priv)
  1342. {
  1343. u32 data2, line;
  1344. u32 desc, time, count, base, data1;
  1345. u32 blink1, blink2, ilink1, ilink2;
  1346. if (priv->ucode_type == UCODE_INIT)
  1347. base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
  1348. else
  1349. base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
  1350. if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
  1351. IWL_ERR(priv, "Not valid error log pointer 0x%08X\n", base);
  1352. return;
  1353. }
  1354. count = iwl_read_targ_mem(priv, base);
  1355. if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
  1356. IWL_ERR(priv, "Start IWL Error Log Dump:\n");
  1357. IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
  1358. priv->status, count);
  1359. }
  1360. desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
  1361. blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
  1362. blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
  1363. ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
  1364. ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
  1365. data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
  1366. data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
  1367. line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
  1368. time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
  1369. trace_iwlwifi_dev_ucode_error(priv, desc, time, data1, data2, line,
  1370. blink1, blink2, ilink1, ilink2);
  1371. IWL_ERR(priv, "Desc Time "
  1372. "data1 data2 line\n");
  1373. IWL_ERR(priv, "%-28s (#%02d) %010u 0x%08X 0x%08X %u\n",
  1374. desc_lookup(desc), desc, time, data1, data2, line);
  1375. IWL_ERR(priv, "blink1 blink2 ilink1 ilink2\n");
  1376. IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X\n", blink1, blink2,
  1377. ilink1, ilink2);
  1378. }
  1379. #define EVENT_START_OFFSET (4 * sizeof(u32))
  1380. /**
  1381. * iwl_print_event_log - Dump error event log to syslog
  1382. *
  1383. */
  1384. static void iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
  1385. u32 num_events, u32 mode)
  1386. {
  1387. u32 i;
  1388. u32 base; /* SRAM byte address of event log header */
  1389. u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
  1390. u32 ptr; /* SRAM byte address of log data */
  1391. u32 ev, time, data; /* event log data */
  1392. if (num_events == 0)
  1393. return;
  1394. if (priv->ucode_type == UCODE_INIT)
  1395. base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
  1396. else
  1397. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  1398. if (mode == 0)
  1399. event_size = 2 * sizeof(u32);
  1400. else
  1401. event_size = 3 * sizeof(u32);
  1402. ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
  1403. /* "time" is actually "data" for mode 0 (no timestamp).
  1404. * place event id # at far right for easier visual parsing. */
  1405. for (i = 0; i < num_events; i++) {
  1406. ev = iwl_read_targ_mem(priv, ptr);
  1407. ptr += sizeof(u32);
  1408. time = iwl_read_targ_mem(priv, ptr);
  1409. ptr += sizeof(u32);
  1410. if (mode == 0) {
  1411. /* data, ev */
  1412. trace_iwlwifi_dev_ucode_event(priv, 0, time, ev);
  1413. IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n", time, ev);
  1414. } else {
  1415. data = iwl_read_targ_mem(priv, ptr);
  1416. ptr += sizeof(u32);
  1417. IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n",
  1418. time, data, ev);
  1419. trace_iwlwifi_dev_ucode_event(priv, time, data, ev);
  1420. }
  1421. }
  1422. }
  1423. void iwl_dump_nic_event_log(struct iwl_priv *priv)
  1424. {
  1425. u32 base; /* SRAM byte address of event log header */
  1426. u32 capacity; /* event log capacity in # entries */
  1427. u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
  1428. u32 num_wraps; /* # times uCode wrapped to top of log */
  1429. u32 next_entry; /* index of next entry to be written by uCode */
  1430. u32 size; /* # entries that we'll print */
  1431. if (priv->ucode_type == UCODE_INIT)
  1432. base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
  1433. else
  1434. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  1435. if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
  1436. IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
  1437. return;
  1438. }
  1439. /* event log header */
  1440. capacity = iwl_read_targ_mem(priv, base);
  1441. mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
  1442. num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
  1443. next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
  1444. size = num_wraps ? capacity : next_entry;
  1445. /* bail out if nothing in log */
  1446. if (size == 0) {
  1447. IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
  1448. return;
  1449. }
  1450. IWL_ERR(priv, "Start IWL Event Log Dump: display count %d, wraps %d\n",
  1451. size, num_wraps);
  1452. /* if uCode has wrapped back to top of log, start at the oldest entry,
  1453. * i.e the next one that uCode would fill. */
  1454. if (num_wraps)
  1455. iwl_print_event_log(priv, next_entry,
  1456. capacity - next_entry, mode);
  1457. /* (then/else) start at top of log */
  1458. iwl_print_event_log(priv, 0, next_entry, mode);
  1459. }
  1460. #endif
  1461. /**
  1462. * iwl_alive_start - called after REPLY_ALIVE notification received
  1463. * from protocol/runtime uCode (initialization uCode's
  1464. * Alive gets handled by iwl_init_alive_start()).
  1465. */
  1466. static void iwl_alive_start(struct iwl_priv *priv)
  1467. {
  1468. int ret = 0;
  1469. IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
  1470. if (priv->card_alive.is_valid != UCODE_VALID_OK) {
  1471. /* We had an error bringing up the hardware, so take it
  1472. * all the way back down so we can try again */
  1473. IWL_DEBUG_INFO(priv, "Alive failed.\n");
  1474. goto restart;
  1475. }
  1476. /* Initialize uCode has loaded Runtime uCode ... verify inst image.
  1477. * This is a paranoid check, because we would not have gotten the
  1478. * "runtime" alive if code weren't properly loaded. */
  1479. if (iwl_verify_ucode(priv)) {
  1480. /* Runtime instruction load was bad;
  1481. * take it all the way back down so we can try again */
  1482. IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
  1483. goto restart;
  1484. }
  1485. iwl_clear_stations_table(priv);
  1486. ret = priv->cfg->ops->lib->alive_notify(priv);
  1487. if (ret) {
  1488. IWL_WARN(priv,
  1489. "Could not complete ALIVE transition [ntf]: %d\n", ret);
  1490. goto restart;
  1491. }
  1492. /* After the ALIVE response, we can send host commands to the uCode */
  1493. set_bit(STATUS_ALIVE, &priv->status);
  1494. if (iwl_is_rfkill(priv))
  1495. return;
  1496. ieee80211_wake_queues(priv->hw);
  1497. priv->active_rate = priv->rates_mask;
  1498. priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
  1499. /* Configure Tx antenna selection based on H/W config */
  1500. if (priv->cfg->ops->hcmd->set_tx_ant)
  1501. priv->cfg->ops->hcmd->set_tx_ant(priv, priv->cfg->valid_tx_ant);
  1502. if (iwl_is_associated(priv)) {
  1503. struct iwl_rxon_cmd *active_rxon =
  1504. (struct iwl_rxon_cmd *)&priv->active_rxon;
  1505. /* apply any changes in staging */
  1506. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  1507. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  1508. } else {
  1509. /* Initialize our rx_config data */
  1510. iwl_connection_init_rx_config(priv, priv->iw_mode);
  1511. if (priv->cfg->ops->hcmd->set_rxon_chain)
  1512. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  1513. memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
  1514. }
  1515. /* Configure Bluetooth device coexistence support */
  1516. iwl_send_bt_config(priv);
  1517. iwl_reset_run_time_calib(priv);
  1518. /* Configure the adapter for unassociated operation */
  1519. iwlcore_commit_rxon(priv);
  1520. /* At this point, the NIC is initialized and operational */
  1521. iwl_rf_kill_ct_config(priv);
  1522. iwl_leds_init(priv);
  1523. IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
  1524. set_bit(STATUS_READY, &priv->status);
  1525. wake_up_interruptible(&priv->wait_command_queue);
  1526. iwl_power_update_mode(priv, true);
  1527. /* reassociate for ADHOC mode */
  1528. if (priv->vif && (priv->iw_mode == NL80211_IFTYPE_ADHOC)) {
  1529. struct sk_buff *beacon = ieee80211_beacon_get(priv->hw,
  1530. priv->vif);
  1531. if (beacon)
  1532. iwl_mac_beacon_update(priv->hw, beacon);
  1533. }
  1534. if (test_and_clear_bit(STATUS_MODE_PENDING, &priv->status))
  1535. iwl_set_mode(priv, priv->iw_mode);
  1536. return;
  1537. restart:
  1538. queue_work(priv->workqueue, &priv->restart);
  1539. }
  1540. static void iwl_cancel_deferred_work(struct iwl_priv *priv);
  1541. static void __iwl_down(struct iwl_priv *priv)
  1542. {
  1543. unsigned long flags;
  1544. int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
  1545. IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
  1546. if (!exit_pending)
  1547. set_bit(STATUS_EXIT_PENDING, &priv->status);
  1548. iwl_clear_stations_table(priv);
  1549. /* Unblock any waiting calls */
  1550. wake_up_interruptible_all(&priv->wait_command_queue);
  1551. /* Wipe out the EXIT_PENDING status bit if we are not actually
  1552. * exiting the module */
  1553. if (!exit_pending)
  1554. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  1555. /* stop and reset the on-board processor */
  1556. iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
  1557. /* tell the device to stop sending interrupts */
  1558. spin_lock_irqsave(&priv->lock, flags);
  1559. iwl_disable_interrupts(priv);
  1560. spin_unlock_irqrestore(&priv->lock, flags);
  1561. iwl_synchronize_irq(priv);
  1562. if (priv->mac80211_registered)
  1563. ieee80211_stop_queues(priv->hw);
  1564. /* If we have not previously called iwl_init() then
  1565. * clear all bits but the RF Kill bit and return */
  1566. if (!iwl_is_init(priv)) {
  1567. priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  1568. STATUS_RF_KILL_HW |
  1569. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  1570. STATUS_GEO_CONFIGURED |
  1571. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  1572. STATUS_EXIT_PENDING;
  1573. goto exit;
  1574. }
  1575. /* ...otherwise clear out all the status bits but the RF Kill
  1576. * bit and continue taking the NIC down. */
  1577. priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  1578. STATUS_RF_KILL_HW |
  1579. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  1580. STATUS_GEO_CONFIGURED |
  1581. test_bit(STATUS_FW_ERROR, &priv->status) <<
  1582. STATUS_FW_ERROR |
  1583. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  1584. STATUS_EXIT_PENDING;
  1585. /* device going down, Stop using ICT table */
  1586. iwl_disable_ict(priv);
  1587. spin_lock_irqsave(&priv->lock, flags);
  1588. iwl_clear_bit(priv, CSR_GP_CNTRL,
  1589. CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  1590. spin_unlock_irqrestore(&priv->lock, flags);
  1591. iwl_txq_ctx_stop(priv);
  1592. iwl_rxq_stop(priv);
  1593. iwl_write_prph(priv, APMG_CLK_DIS_REG,
  1594. APMG_CLK_VAL_DMA_CLK_RQT);
  1595. udelay(5);
  1596. /* Stop the device, and put it in low power state */
  1597. priv->cfg->ops->lib->apm_ops.stop(priv);
  1598. exit:
  1599. memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
  1600. if (priv->ibss_beacon)
  1601. dev_kfree_skb(priv->ibss_beacon);
  1602. priv->ibss_beacon = NULL;
  1603. /* clear out any free frames */
  1604. iwl_clear_free_frames(priv);
  1605. }
  1606. static void iwl_down(struct iwl_priv *priv)
  1607. {
  1608. mutex_lock(&priv->mutex);
  1609. __iwl_down(priv);
  1610. mutex_unlock(&priv->mutex);
  1611. iwl_cancel_deferred_work(priv);
  1612. }
  1613. #define HW_READY_TIMEOUT (50)
  1614. static int iwl_set_hw_ready(struct iwl_priv *priv)
  1615. {
  1616. int ret = 0;
  1617. iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  1618. CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
  1619. /* See if we got it */
  1620. ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
  1621. CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
  1622. CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
  1623. HW_READY_TIMEOUT);
  1624. if (ret != -ETIMEDOUT)
  1625. priv->hw_ready = true;
  1626. else
  1627. priv->hw_ready = false;
  1628. IWL_DEBUG_INFO(priv, "hardware %s\n",
  1629. (priv->hw_ready == 1) ? "ready" : "not ready");
  1630. return ret;
  1631. }
  1632. static int iwl_prepare_card_hw(struct iwl_priv *priv)
  1633. {
  1634. int ret = 0;
  1635. IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter \n");
  1636. ret = iwl_set_hw_ready(priv);
  1637. if (priv->hw_ready)
  1638. return ret;
  1639. /* If HW is not ready, prepare the conditions to check again */
  1640. iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  1641. CSR_HW_IF_CONFIG_REG_PREPARE);
  1642. ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
  1643. ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
  1644. CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
  1645. /* HW should be ready by now, check again. */
  1646. if (ret != -ETIMEDOUT)
  1647. iwl_set_hw_ready(priv);
  1648. return ret;
  1649. }
  1650. #define MAX_HW_RESTARTS 5
  1651. static int __iwl_up(struct iwl_priv *priv)
  1652. {
  1653. int i;
  1654. int ret;
  1655. if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  1656. IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
  1657. return -EIO;
  1658. }
  1659. if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
  1660. IWL_ERR(priv, "ucode not available for device bringup\n");
  1661. return -EIO;
  1662. }
  1663. iwl_prepare_card_hw(priv);
  1664. if (!priv->hw_ready) {
  1665. IWL_WARN(priv, "Exit HW not ready\n");
  1666. return -EIO;
  1667. }
  1668. /* If platform's RF_KILL switch is NOT set to KILL */
  1669. if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
  1670. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  1671. else
  1672. set_bit(STATUS_RF_KILL_HW, &priv->status);
  1673. if (iwl_is_rfkill(priv)) {
  1674. wiphy_rfkill_set_hw_state(priv->hw->wiphy, true);
  1675. iwl_enable_interrupts(priv);
  1676. IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
  1677. return 0;
  1678. }
  1679. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  1680. ret = iwl_hw_nic_init(priv);
  1681. if (ret) {
  1682. IWL_ERR(priv, "Unable to init nic\n");
  1683. return ret;
  1684. }
  1685. /* make sure rfkill handshake bits are cleared */
  1686. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  1687. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  1688. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  1689. /* clear (again), then enable host interrupts */
  1690. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  1691. iwl_enable_interrupts(priv);
  1692. /* really make sure rfkill handshake bits are cleared */
  1693. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  1694. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  1695. /* Copy original ucode data image from disk into backup cache.
  1696. * This will be used to initialize the on-board processor's
  1697. * data SRAM for a clean start when the runtime program first loads. */
  1698. memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
  1699. priv->ucode_data.len);
  1700. for (i = 0; i < MAX_HW_RESTARTS; i++) {
  1701. iwl_clear_stations_table(priv);
  1702. /* load bootstrap state machine,
  1703. * load bootstrap program into processor's memory,
  1704. * prepare to load the "initialize" uCode */
  1705. ret = priv->cfg->ops->lib->load_ucode(priv);
  1706. if (ret) {
  1707. IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n",
  1708. ret);
  1709. continue;
  1710. }
  1711. /* start card; "initialize" will load runtime ucode */
  1712. iwl_nic_start(priv);
  1713. IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
  1714. return 0;
  1715. }
  1716. set_bit(STATUS_EXIT_PENDING, &priv->status);
  1717. __iwl_down(priv);
  1718. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  1719. /* tried to restart and config the device for as long as our
  1720. * patience could withstand */
  1721. IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
  1722. return -EIO;
  1723. }
  1724. /*****************************************************************************
  1725. *
  1726. * Workqueue callbacks
  1727. *
  1728. *****************************************************************************/
  1729. static void iwl_bg_init_alive_start(struct work_struct *data)
  1730. {
  1731. struct iwl_priv *priv =
  1732. container_of(data, struct iwl_priv, init_alive_start.work);
  1733. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1734. return;
  1735. mutex_lock(&priv->mutex);
  1736. priv->cfg->ops->lib->init_alive_start(priv);
  1737. mutex_unlock(&priv->mutex);
  1738. }
  1739. static void iwl_bg_alive_start(struct work_struct *data)
  1740. {
  1741. struct iwl_priv *priv =
  1742. container_of(data, struct iwl_priv, alive_start.work);
  1743. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1744. return;
  1745. /* enable dram interrupt */
  1746. iwl_reset_ict(priv);
  1747. mutex_lock(&priv->mutex);
  1748. iwl_alive_start(priv);
  1749. mutex_unlock(&priv->mutex);
  1750. }
  1751. static void iwl_bg_run_time_calib_work(struct work_struct *work)
  1752. {
  1753. struct iwl_priv *priv = container_of(work, struct iwl_priv,
  1754. run_time_calib_work);
  1755. mutex_lock(&priv->mutex);
  1756. if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
  1757. test_bit(STATUS_SCANNING, &priv->status)) {
  1758. mutex_unlock(&priv->mutex);
  1759. return;
  1760. }
  1761. if (priv->start_calib) {
  1762. iwl_chain_noise_calibration(priv, &priv->statistics);
  1763. iwl_sensitivity_calibration(priv, &priv->statistics);
  1764. }
  1765. mutex_unlock(&priv->mutex);
  1766. return;
  1767. }
  1768. static void iwl_bg_up(struct work_struct *data)
  1769. {
  1770. struct iwl_priv *priv = container_of(data, struct iwl_priv, up);
  1771. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1772. return;
  1773. mutex_lock(&priv->mutex);
  1774. __iwl_up(priv);
  1775. mutex_unlock(&priv->mutex);
  1776. }
  1777. static void iwl_bg_restart(struct work_struct *data)
  1778. {
  1779. struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
  1780. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1781. return;
  1782. if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
  1783. mutex_lock(&priv->mutex);
  1784. priv->vif = NULL;
  1785. priv->is_open = 0;
  1786. mutex_unlock(&priv->mutex);
  1787. iwl_down(priv);
  1788. ieee80211_restart_hw(priv->hw);
  1789. } else {
  1790. iwl_down(priv);
  1791. queue_work(priv->workqueue, &priv->up);
  1792. }
  1793. }
  1794. static void iwl_bg_rx_replenish(struct work_struct *data)
  1795. {
  1796. struct iwl_priv *priv =
  1797. container_of(data, struct iwl_priv, rx_replenish);
  1798. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1799. return;
  1800. mutex_lock(&priv->mutex);
  1801. iwl_rx_replenish(priv);
  1802. mutex_unlock(&priv->mutex);
  1803. }
  1804. #define IWL_DELAY_NEXT_SCAN (HZ*2)
  1805. void iwl_post_associate(struct iwl_priv *priv)
  1806. {
  1807. struct ieee80211_conf *conf = NULL;
  1808. int ret = 0;
  1809. unsigned long flags;
  1810. if (priv->iw_mode == NL80211_IFTYPE_AP) {
  1811. IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__);
  1812. return;
  1813. }
  1814. IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n",
  1815. priv->assoc_id, priv->active_rxon.bssid_addr);
  1816. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1817. return;
  1818. if (!priv->vif || !priv->is_open)
  1819. return;
  1820. iwl_scan_cancel_timeout(priv, 200);
  1821. conf = ieee80211_get_hw_conf(priv->hw);
  1822. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  1823. iwlcore_commit_rxon(priv);
  1824. iwl_setup_rxon_timing(priv);
  1825. ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  1826. sizeof(priv->rxon_timing), &priv->rxon_timing);
  1827. if (ret)
  1828. IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
  1829. "Attempting to continue.\n");
  1830. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  1831. iwl_set_rxon_ht(priv, &priv->current_ht_config);
  1832. if (priv->cfg->ops->hcmd->set_rxon_chain)
  1833. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  1834. priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
  1835. IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n",
  1836. priv->assoc_id, priv->beacon_int);
  1837. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
  1838. priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  1839. else
  1840. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  1841. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  1842. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
  1843. priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  1844. else
  1845. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  1846. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  1847. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  1848. }
  1849. iwlcore_commit_rxon(priv);
  1850. switch (priv->iw_mode) {
  1851. case NL80211_IFTYPE_STATION:
  1852. break;
  1853. case NL80211_IFTYPE_ADHOC:
  1854. /* assume default assoc id */
  1855. priv->assoc_id = 1;
  1856. iwl_rxon_add_station(priv, priv->bssid, 0);
  1857. iwl_send_beacon_cmd(priv);
  1858. break;
  1859. default:
  1860. IWL_ERR(priv, "%s Should not be called in %d mode\n",
  1861. __func__, priv->iw_mode);
  1862. break;
  1863. }
  1864. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  1865. priv->assoc_station_added = 1;
  1866. spin_lock_irqsave(&priv->lock, flags);
  1867. iwl_activate_qos(priv, 0);
  1868. spin_unlock_irqrestore(&priv->lock, flags);
  1869. /* the chain noise calibration will enabled PM upon completion
  1870. * If chain noise has already been run, then we need to enable
  1871. * power management here */
  1872. if (priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE)
  1873. iwl_power_update_mode(priv, false);
  1874. /* Enable Rx differential gain and sensitivity calibrations */
  1875. iwl_chain_noise_reset(priv);
  1876. priv->start_calib = 1;
  1877. }
  1878. /*****************************************************************************
  1879. *
  1880. * mac80211 entry point functions
  1881. *
  1882. *****************************************************************************/
  1883. #define UCODE_READY_TIMEOUT (4 * HZ)
  1884. /*
  1885. * Not a mac80211 entry point function, but it fits in with all the
  1886. * other mac80211 functions grouped here.
  1887. */
  1888. static int iwl_setup_mac(struct iwl_priv *priv)
  1889. {
  1890. int ret;
  1891. struct ieee80211_hw *hw = priv->hw;
  1892. hw->rate_control_algorithm = "iwl-agn-rs";
  1893. /* Tell mac80211 our characteristics */
  1894. hw->flags = IEEE80211_HW_SIGNAL_DBM |
  1895. IEEE80211_HW_NOISE_DBM |
  1896. IEEE80211_HW_AMPDU_AGGREGATION |
  1897. IEEE80211_HW_SPECTRUM_MGMT;
  1898. if (!priv->cfg->broken_powersave)
  1899. hw->flags |= IEEE80211_HW_SUPPORTS_PS |
  1900. IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
  1901. hw->sta_data_size = sizeof(struct iwl_station_priv);
  1902. hw->wiphy->interface_modes =
  1903. BIT(NL80211_IFTYPE_STATION) |
  1904. BIT(NL80211_IFTYPE_ADHOC);
  1905. hw->wiphy->custom_regulatory = true;
  1906. /* Firmware does not support this */
  1907. hw->wiphy->disable_beacon_hints = true;
  1908. /*
  1909. * For now, disable PS by default because it affects
  1910. * RX performance significantly.
  1911. */
  1912. hw->wiphy->ps_default = false;
  1913. hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX;
  1914. /* we create the 802.11 header and a zero-length SSID element */
  1915. hw->wiphy->max_scan_ie_len = IWL_MAX_PROBE_REQUEST - 24 - 2;
  1916. /* Default value; 4 EDCA QOS priorities */
  1917. hw->queues = 4;
  1918. hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
  1919. if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
  1920. priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
  1921. &priv->bands[IEEE80211_BAND_2GHZ];
  1922. if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
  1923. priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
  1924. &priv->bands[IEEE80211_BAND_5GHZ];
  1925. ret = ieee80211_register_hw(priv->hw);
  1926. if (ret) {
  1927. IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
  1928. return ret;
  1929. }
  1930. priv->mac80211_registered = 1;
  1931. return 0;
  1932. }
  1933. static int iwl_mac_start(struct ieee80211_hw *hw)
  1934. {
  1935. struct iwl_priv *priv = hw->priv;
  1936. int ret;
  1937. IWL_DEBUG_MAC80211(priv, "enter\n");
  1938. /* we should be verifying the device is ready to be opened */
  1939. mutex_lock(&priv->mutex);
  1940. /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
  1941. * ucode filename and max sizes are card-specific. */
  1942. if (!priv->ucode_code.len) {
  1943. ret = iwl_read_ucode(priv);
  1944. if (ret) {
  1945. IWL_ERR(priv, "Could not read microcode: %d\n", ret);
  1946. mutex_unlock(&priv->mutex);
  1947. return ret;
  1948. }
  1949. }
  1950. ret = __iwl_up(priv);
  1951. mutex_unlock(&priv->mutex);
  1952. if (ret)
  1953. return ret;
  1954. if (iwl_is_rfkill(priv))
  1955. goto out;
  1956. IWL_DEBUG_INFO(priv, "Start UP work done.\n");
  1957. /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
  1958. * mac80211 will not be run successfully. */
  1959. ret = wait_event_interruptible_timeout(priv->wait_command_queue,
  1960. test_bit(STATUS_READY, &priv->status),
  1961. UCODE_READY_TIMEOUT);
  1962. if (!ret) {
  1963. if (!test_bit(STATUS_READY, &priv->status)) {
  1964. IWL_ERR(priv, "START_ALIVE timeout after %dms.\n",
  1965. jiffies_to_msecs(UCODE_READY_TIMEOUT));
  1966. return -ETIMEDOUT;
  1967. }
  1968. }
  1969. iwl_led_start(priv);
  1970. out:
  1971. priv->is_open = 1;
  1972. IWL_DEBUG_MAC80211(priv, "leave\n");
  1973. return 0;
  1974. }
  1975. static void iwl_mac_stop(struct ieee80211_hw *hw)
  1976. {
  1977. struct iwl_priv *priv = hw->priv;
  1978. IWL_DEBUG_MAC80211(priv, "enter\n");
  1979. if (!priv->is_open)
  1980. return;
  1981. priv->is_open = 0;
  1982. if (iwl_is_ready_rf(priv) || test_bit(STATUS_SCAN_HW, &priv->status)) {
  1983. /* stop mac, cancel any scan request and clear
  1984. * RXON_FILTER_ASSOC_MSK BIT
  1985. */
  1986. mutex_lock(&priv->mutex);
  1987. iwl_scan_cancel_timeout(priv, 100);
  1988. mutex_unlock(&priv->mutex);
  1989. }
  1990. iwl_down(priv);
  1991. flush_workqueue(priv->workqueue);
  1992. /* enable interrupts again in order to receive rfkill changes */
  1993. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  1994. iwl_enable_interrupts(priv);
  1995. IWL_DEBUG_MAC80211(priv, "leave\n");
  1996. }
  1997. static int iwl_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
  1998. {
  1999. struct iwl_priv *priv = hw->priv;
  2000. IWL_DEBUG_MACDUMP(priv, "enter\n");
  2001. IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
  2002. ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
  2003. if (iwl_tx_skb(priv, skb))
  2004. dev_kfree_skb_any(skb);
  2005. IWL_DEBUG_MACDUMP(priv, "leave\n");
  2006. return NETDEV_TX_OK;
  2007. }
  2008. void iwl_config_ap(struct iwl_priv *priv)
  2009. {
  2010. int ret = 0;
  2011. unsigned long flags;
  2012. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2013. return;
  2014. /* The following should be done only at AP bring up */
  2015. if (!iwl_is_associated(priv)) {
  2016. /* RXON - unassoc (to set timing command) */
  2017. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  2018. iwlcore_commit_rxon(priv);
  2019. /* RXON Timing */
  2020. iwl_setup_rxon_timing(priv);
  2021. ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  2022. sizeof(priv->rxon_timing), &priv->rxon_timing);
  2023. if (ret)
  2024. IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
  2025. "Attempting to continue.\n");
  2026. if (priv->cfg->ops->hcmd->set_rxon_chain)
  2027. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  2028. /* FIXME: what should be the assoc_id for AP? */
  2029. priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
  2030. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
  2031. priv->staging_rxon.flags |=
  2032. RXON_FLG_SHORT_PREAMBLE_MSK;
  2033. else
  2034. priv->staging_rxon.flags &=
  2035. ~RXON_FLG_SHORT_PREAMBLE_MSK;
  2036. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  2037. if (priv->assoc_capability &
  2038. WLAN_CAPABILITY_SHORT_SLOT_TIME)
  2039. priv->staging_rxon.flags |=
  2040. RXON_FLG_SHORT_SLOT_MSK;
  2041. else
  2042. priv->staging_rxon.flags &=
  2043. ~RXON_FLG_SHORT_SLOT_MSK;
  2044. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  2045. priv->staging_rxon.flags &=
  2046. ~RXON_FLG_SHORT_SLOT_MSK;
  2047. }
  2048. /* restore RXON assoc */
  2049. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  2050. iwlcore_commit_rxon(priv);
  2051. spin_lock_irqsave(&priv->lock, flags);
  2052. iwl_activate_qos(priv, 1);
  2053. spin_unlock_irqrestore(&priv->lock, flags);
  2054. iwl_add_bcast_station(priv);
  2055. }
  2056. iwl_send_beacon_cmd(priv);
  2057. /* FIXME - we need to add code here to detect a totally new
  2058. * configuration, reset the AP, unassoc, rxon timing, assoc,
  2059. * clear sta table, add BCAST sta... */
  2060. }
  2061. static void iwl_mac_update_tkip_key(struct ieee80211_hw *hw,
  2062. struct ieee80211_key_conf *keyconf, const u8 *addr,
  2063. u32 iv32, u16 *phase1key)
  2064. {
  2065. struct iwl_priv *priv = hw->priv;
  2066. IWL_DEBUG_MAC80211(priv, "enter\n");
  2067. iwl_update_tkip_key(priv, keyconf, addr, iv32, phase1key);
  2068. IWL_DEBUG_MAC80211(priv, "leave\n");
  2069. }
  2070. static int iwl_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
  2071. struct ieee80211_vif *vif,
  2072. struct ieee80211_sta *sta,
  2073. struct ieee80211_key_conf *key)
  2074. {
  2075. struct iwl_priv *priv = hw->priv;
  2076. const u8 *addr;
  2077. int ret;
  2078. u8 sta_id;
  2079. bool is_default_wep_key = false;
  2080. IWL_DEBUG_MAC80211(priv, "enter\n");
  2081. if (priv->cfg->mod_params->sw_crypto) {
  2082. IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
  2083. return -EOPNOTSUPP;
  2084. }
  2085. addr = sta ? sta->addr : iwl_bcast_addr;
  2086. sta_id = iwl_find_station(priv, addr);
  2087. if (sta_id == IWL_INVALID_STATION) {
  2088. IWL_DEBUG_MAC80211(priv, "leave - %pM not in station map.\n",
  2089. addr);
  2090. return -EINVAL;
  2091. }
  2092. mutex_lock(&priv->mutex);
  2093. iwl_scan_cancel_timeout(priv, 100);
  2094. mutex_unlock(&priv->mutex);
  2095. /* If we are getting WEP group key and we didn't receive any key mapping
  2096. * so far, we are in legacy wep mode (group key only), otherwise we are
  2097. * in 1X mode.
  2098. * In legacy wep mode, we use another host command to the uCode */
  2099. if (key->alg == ALG_WEP && sta_id == priv->hw_params.bcast_sta_id &&
  2100. priv->iw_mode != NL80211_IFTYPE_AP) {
  2101. if (cmd == SET_KEY)
  2102. is_default_wep_key = !priv->key_mapping_key;
  2103. else
  2104. is_default_wep_key =
  2105. (key->hw_key_idx == HW_KEY_DEFAULT);
  2106. }
  2107. switch (cmd) {
  2108. case SET_KEY:
  2109. if (is_default_wep_key)
  2110. ret = iwl_set_default_wep_key(priv, key);
  2111. else
  2112. ret = iwl_set_dynamic_key(priv, key, sta_id);
  2113. IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
  2114. break;
  2115. case DISABLE_KEY:
  2116. if (is_default_wep_key)
  2117. ret = iwl_remove_default_wep_key(priv, key);
  2118. else
  2119. ret = iwl_remove_dynamic_key(priv, key, sta_id);
  2120. IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
  2121. break;
  2122. default:
  2123. ret = -EINVAL;
  2124. }
  2125. IWL_DEBUG_MAC80211(priv, "leave\n");
  2126. return ret;
  2127. }
  2128. static int iwl_mac_ampdu_action(struct ieee80211_hw *hw,
  2129. enum ieee80211_ampdu_mlme_action action,
  2130. struct ieee80211_sta *sta, u16 tid, u16 *ssn)
  2131. {
  2132. struct iwl_priv *priv = hw->priv;
  2133. int ret;
  2134. IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
  2135. sta->addr, tid);
  2136. if (!(priv->cfg->sku & IWL_SKU_N))
  2137. return -EACCES;
  2138. switch (action) {
  2139. case IEEE80211_AMPDU_RX_START:
  2140. IWL_DEBUG_HT(priv, "start Rx\n");
  2141. return iwl_sta_rx_agg_start(priv, sta->addr, tid, *ssn);
  2142. case IEEE80211_AMPDU_RX_STOP:
  2143. IWL_DEBUG_HT(priv, "stop Rx\n");
  2144. ret = iwl_sta_rx_agg_stop(priv, sta->addr, tid);
  2145. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2146. return 0;
  2147. else
  2148. return ret;
  2149. case IEEE80211_AMPDU_TX_START:
  2150. IWL_DEBUG_HT(priv, "start Tx\n");
  2151. return iwl_tx_agg_start(priv, sta->addr, tid, ssn);
  2152. case IEEE80211_AMPDU_TX_STOP:
  2153. IWL_DEBUG_HT(priv, "stop Tx\n");
  2154. ret = iwl_tx_agg_stop(priv, sta->addr, tid);
  2155. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2156. return 0;
  2157. else
  2158. return ret;
  2159. default:
  2160. IWL_DEBUG_HT(priv, "unknown\n");
  2161. return -EINVAL;
  2162. break;
  2163. }
  2164. return 0;
  2165. }
  2166. static int iwl_mac_get_stats(struct ieee80211_hw *hw,
  2167. struct ieee80211_low_level_stats *stats)
  2168. {
  2169. struct iwl_priv *priv = hw->priv;
  2170. priv = hw->priv;
  2171. IWL_DEBUG_MAC80211(priv, "enter\n");
  2172. IWL_DEBUG_MAC80211(priv, "leave\n");
  2173. return 0;
  2174. }
  2175. /*****************************************************************************
  2176. *
  2177. * sysfs attributes
  2178. *
  2179. *****************************************************************************/
  2180. #ifdef CONFIG_IWLWIFI_DEBUG
  2181. /*
  2182. * The following adds a new attribute to the sysfs representation
  2183. * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
  2184. * used for controlling the debug level.
  2185. *
  2186. * See the level definitions in iwl for details.
  2187. *
  2188. * The debug_level being managed using sysfs below is a per device debug
  2189. * level that is used instead of the global debug level if it (the per
  2190. * device debug level) is set.
  2191. */
  2192. static ssize_t show_debug_level(struct device *d,
  2193. struct device_attribute *attr, char *buf)
  2194. {
  2195. struct iwl_priv *priv = dev_get_drvdata(d);
  2196. return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv));
  2197. }
  2198. static ssize_t store_debug_level(struct device *d,
  2199. struct device_attribute *attr,
  2200. const char *buf, size_t count)
  2201. {
  2202. struct iwl_priv *priv = dev_get_drvdata(d);
  2203. unsigned long val;
  2204. int ret;
  2205. ret = strict_strtoul(buf, 0, &val);
  2206. if (ret)
  2207. IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
  2208. else {
  2209. priv->debug_level = val;
  2210. if (iwl_alloc_traffic_mem(priv))
  2211. IWL_ERR(priv,
  2212. "Not enough memory to generate traffic log\n");
  2213. }
  2214. return strnlen(buf, count);
  2215. }
  2216. static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
  2217. show_debug_level, store_debug_level);
  2218. #endif /* CONFIG_IWLWIFI_DEBUG */
  2219. static ssize_t show_temperature(struct device *d,
  2220. struct device_attribute *attr, char *buf)
  2221. {
  2222. struct iwl_priv *priv = dev_get_drvdata(d);
  2223. if (!iwl_is_alive(priv))
  2224. return -EAGAIN;
  2225. return sprintf(buf, "%d\n", priv->temperature);
  2226. }
  2227. static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
  2228. static ssize_t show_tx_power(struct device *d,
  2229. struct device_attribute *attr, char *buf)
  2230. {
  2231. struct iwl_priv *priv = dev_get_drvdata(d);
  2232. if (!iwl_is_ready_rf(priv))
  2233. return sprintf(buf, "off\n");
  2234. else
  2235. return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
  2236. }
  2237. static ssize_t store_tx_power(struct device *d,
  2238. struct device_attribute *attr,
  2239. const char *buf, size_t count)
  2240. {
  2241. struct iwl_priv *priv = dev_get_drvdata(d);
  2242. unsigned long val;
  2243. int ret;
  2244. ret = strict_strtoul(buf, 10, &val);
  2245. if (ret)
  2246. IWL_INFO(priv, "%s is not in decimal form.\n", buf);
  2247. else {
  2248. ret = iwl_set_tx_power(priv, val, false);
  2249. if (ret)
  2250. IWL_ERR(priv, "failed setting tx power (0x%d).\n",
  2251. ret);
  2252. else
  2253. ret = count;
  2254. }
  2255. return ret;
  2256. }
  2257. static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
  2258. static ssize_t show_flags(struct device *d,
  2259. struct device_attribute *attr, char *buf)
  2260. {
  2261. struct iwl_priv *priv = dev_get_drvdata(d);
  2262. return sprintf(buf, "0x%04X\n", priv->active_rxon.flags);
  2263. }
  2264. static ssize_t store_flags(struct device *d,
  2265. struct device_attribute *attr,
  2266. const char *buf, size_t count)
  2267. {
  2268. struct iwl_priv *priv = dev_get_drvdata(d);
  2269. unsigned long val;
  2270. u32 flags;
  2271. int ret = strict_strtoul(buf, 0, &val);
  2272. if (ret)
  2273. return ret;
  2274. flags = (u32)val;
  2275. mutex_lock(&priv->mutex);
  2276. if (le32_to_cpu(priv->staging_rxon.flags) != flags) {
  2277. /* Cancel any currently running scans... */
  2278. if (iwl_scan_cancel_timeout(priv, 100))
  2279. IWL_WARN(priv, "Could not cancel scan.\n");
  2280. else {
  2281. IWL_DEBUG_INFO(priv, "Commit rxon.flags = 0x%04X\n", flags);
  2282. priv->staging_rxon.flags = cpu_to_le32(flags);
  2283. iwlcore_commit_rxon(priv);
  2284. }
  2285. }
  2286. mutex_unlock(&priv->mutex);
  2287. return count;
  2288. }
  2289. static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags);
  2290. static ssize_t show_filter_flags(struct device *d,
  2291. struct device_attribute *attr, char *buf)
  2292. {
  2293. struct iwl_priv *priv = dev_get_drvdata(d);
  2294. return sprintf(buf, "0x%04X\n",
  2295. le32_to_cpu(priv->active_rxon.filter_flags));
  2296. }
  2297. static ssize_t store_filter_flags(struct device *d,
  2298. struct device_attribute *attr,
  2299. const char *buf, size_t count)
  2300. {
  2301. struct iwl_priv *priv = dev_get_drvdata(d);
  2302. unsigned long val;
  2303. u32 filter_flags;
  2304. int ret = strict_strtoul(buf, 0, &val);
  2305. if (ret)
  2306. return ret;
  2307. filter_flags = (u32)val;
  2308. mutex_lock(&priv->mutex);
  2309. if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) {
  2310. /* Cancel any currently running scans... */
  2311. if (iwl_scan_cancel_timeout(priv, 100))
  2312. IWL_WARN(priv, "Could not cancel scan.\n");
  2313. else {
  2314. IWL_DEBUG_INFO(priv, "Committing rxon.filter_flags = "
  2315. "0x%04X\n", filter_flags);
  2316. priv->staging_rxon.filter_flags =
  2317. cpu_to_le32(filter_flags);
  2318. iwlcore_commit_rxon(priv);
  2319. }
  2320. }
  2321. mutex_unlock(&priv->mutex);
  2322. return count;
  2323. }
  2324. static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags,
  2325. store_filter_flags);
  2326. static ssize_t show_statistics(struct device *d,
  2327. struct device_attribute *attr, char *buf)
  2328. {
  2329. struct iwl_priv *priv = dev_get_drvdata(d);
  2330. u32 size = sizeof(struct iwl_notif_statistics);
  2331. u32 len = 0, ofs = 0;
  2332. u8 *data = (u8 *)&priv->statistics;
  2333. int rc = 0;
  2334. if (!iwl_is_alive(priv))
  2335. return -EAGAIN;
  2336. mutex_lock(&priv->mutex);
  2337. rc = iwl_send_statistics_request(priv, 0);
  2338. mutex_unlock(&priv->mutex);
  2339. if (rc) {
  2340. len = sprintf(buf,
  2341. "Error sending statistics request: 0x%08X\n", rc);
  2342. return len;
  2343. }
  2344. while (size && (PAGE_SIZE - len)) {
  2345. hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
  2346. PAGE_SIZE - len, 1);
  2347. len = strlen(buf);
  2348. if (PAGE_SIZE - len)
  2349. buf[len++] = '\n';
  2350. ofs += 16;
  2351. size -= min(size, 16U);
  2352. }
  2353. return len;
  2354. }
  2355. static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL);
  2356. static ssize_t show_rts_ht_protection(struct device *d,
  2357. struct device_attribute *attr, char *buf)
  2358. {
  2359. struct iwl_priv *priv = dev_get_drvdata(d);
  2360. return sprintf(buf, "%s\n",
  2361. priv->cfg->use_rts_for_ht ? "RTS/CTS" : "CTS-to-self");
  2362. }
  2363. static ssize_t store_rts_ht_protection(struct device *d,
  2364. struct device_attribute *attr,
  2365. const char *buf, size_t count)
  2366. {
  2367. struct iwl_priv *priv = dev_get_drvdata(d);
  2368. unsigned long val;
  2369. int ret;
  2370. ret = strict_strtoul(buf, 10, &val);
  2371. if (ret)
  2372. IWL_INFO(priv, "Input is not in decimal form.\n");
  2373. else {
  2374. if (!iwl_is_associated(priv))
  2375. priv->cfg->use_rts_for_ht = val ? true : false;
  2376. else
  2377. IWL_ERR(priv, "Sta associated with AP - "
  2378. "Change protection mechanism is not allowed\n");
  2379. ret = count;
  2380. }
  2381. return ret;
  2382. }
  2383. static DEVICE_ATTR(rts_ht_protection, S_IWUSR | S_IRUGO,
  2384. show_rts_ht_protection, store_rts_ht_protection);
  2385. /*****************************************************************************
  2386. *
  2387. * driver setup and teardown
  2388. *
  2389. *****************************************************************************/
  2390. static void iwl_setup_deferred_work(struct iwl_priv *priv)
  2391. {
  2392. priv->workqueue = create_singlethread_workqueue(DRV_NAME);
  2393. init_waitqueue_head(&priv->wait_command_queue);
  2394. INIT_WORK(&priv->up, iwl_bg_up);
  2395. INIT_WORK(&priv->restart, iwl_bg_restart);
  2396. INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
  2397. INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
  2398. INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
  2399. INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start);
  2400. INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start);
  2401. iwl_setup_scan_deferred_work(priv);
  2402. if (priv->cfg->ops->lib->setup_deferred_work)
  2403. priv->cfg->ops->lib->setup_deferred_work(priv);
  2404. init_timer(&priv->statistics_periodic);
  2405. priv->statistics_periodic.data = (unsigned long)priv;
  2406. priv->statistics_periodic.function = iwl_bg_statistics_periodic;
  2407. if (!priv->cfg->use_isr_legacy)
  2408. tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
  2409. iwl_irq_tasklet, (unsigned long)priv);
  2410. else
  2411. tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
  2412. iwl_irq_tasklet_legacy, (unsigned long)priv);
  2413. }
  2414. static void iwl_cancel_deferred_work(struct iwl_priv *priv)
  2415. {
  2416. if (priv->cfg->ops->lib->cancel_deferred_work)
  2417. priv->cfg->ops->lib->cancel_deferred_work(priv);
  2418. cancel_delayed_work_sync(&priv->init_alive_start);
  2419. cancel_delayed_work(&priv->scan_check);
  2420. cancel_delayed_work(&priv->alive_start);
  2421. cancel_work_sync(&priv->beacon_update);
  2422. del_timer_sync(&priv->statistics_periodic);
  2423. }
  2424. static void iwl_init_hw_rates(struct iwl_priv *priv,
  2425. struct ieee80211_rate *rates)
  2426. {
  2427. int i;
  2428. for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) {
  2429. rates[i].bitrate = iwl_rates[i].ieee * 5;
  2430. rates[i].hw_value = i; /* Rate scaling will work on indexes */
  2431. rates[i].hw_value_short = i;
  2432. rates[i].flags = 0;
  2433. if ((i >= IWL_FIRST_CCK_RATE) && (i <= IWL_LAST_CCK_RATE)) {
  2434. /*
  2435. * If CCK != 1M then set short preamble rate flag.
  2436. */
  2437. rates[i].flags |=
  2438. (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
  2439. 0 : IEEE80211_RATE_SHORT_PREAMBLE;
  2440. }
  2441. }
  2442. }
  2443. static int iwl_init_drv(struct iwl_priv *priv)
  2444. {
  2445. int ret;
  2446. priv->ibss_beacon = NULL;
  2447. spin_lock_init(&priv->lock);
  2448. spin_lock_init(&priv->sta_lock);
  2449. spin_lock_init(&priv->hcmd_lock);
  2450. INIT_LIST_HEAD(&priv->free_frames);
  2451. mutex_init(&priv->mutex);
  2452. /* Clear the driver's (not device's) station table */
  2453. iwl_clear_stations_table(priv);
  2454. priv->ieee_channels = NULL;
  2455. priv->ieee_rates = NULL;
  2456. priv->band = IEEE80211_BAND_2GHZ;
  2457. priv->iw_mode = NL80211_IFTYPE_STATION;
  2458. if (priv->cfg->support_sm_ps)
  2459. priv->current_ht_config.sm_ps = WLAN_HT_CAP_SM_PS_DYNAMIC;
  2460. else
  2461. priv->current_ht_config.sm_ps = WLAN_HT_CAP_SM_PS_DISABLED;
  2462. /* Choose which receivers/antennas to use */
  2463. if (priv->cfg->ops->hcmd->set_rxon_chain)
  2464. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  2465. iwl_init_scan_params(priv);
  2466. iwl_reset_qos(priv);
  2467. priv->qos_data.qos_active = 0;
  2468. priv->qos_data.qos_cap.val = 0;
  2469. priv->rates_mask = IWL_RATES_MASK;
  2470. /* Set the tx_power_user_lmt to the lowest power level
  2471. * this value will get overwritten by channel max power avg
  2472. * from eeprom */
  2473. priv->tx_power_user_lmt = IWL_TX_POWER_TARGET_POWER_MIN;
  2474. ret = iwl_init_channel_map(priv);
  2475. if (ret) {
  2476. IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
  2477. goto err;
  2478. }
  2479. ret = iwlcore_init_geos(priv);
  2480. if (ret) {
  2481. IWL_ERR(priv, "initializing geos failed: %d\n", ret);
  2482. goto err_free_channel_map;
  2483. }
  2484. iwl_init_hw_rates(priv, priv->ieee_rates);
  2485. return 0;
  2486. err_free_channel_map:
  2487. iwl_free_channel_map(priv);
  2488. err:
  2489. return ret;
  2490. }
  2491. static void iwl_uninit_drv(struct iwl_priv *priv)
  2492. {
  2493. iwl_calib_free_results(priv);
  2494. iwlcore_free_geos(priv);
  2495. iwl_free_channel_map(priv);
  2496. kfree(priv->scan);
  2497. }
  2498. static struct attribute *iwl_sysfs_entries[] = {
  2499. &dev_attr_flags.attr,
  2500. &dev_attr_filter_flags.attr,
  2501. &dev_attr_statistics.attr,
  2502. &dev_attr_temperature.attr,
  2503. &dev_attr_tx_power.attr,
  2504. &dev_attr_rts_ht_protection.attr,
  2505. #ifdef CONFIG_IWLWIFI_DEBUG
  2506. &dev_attr_debug_level.attr,
  2507. #endif
  2508. NULL
  2509. };
  2510. static struct attribute_group iwl_attribute_group = {
  2511. .name = NULL, /* put in device directory */
  2512. .attrs = iwl_sysfs_entries,
  2513. };
  2514. static struct ieee80211_ops iwl_hw_ops = {
  2515. .tx = iwl_mac_tx,
  2516. .start = iwl_mac_start,
  2517. .stop = iwl_mac_stop,
  2518. .add_interface = iwl_mac_add_interface,
  2519. .remove_interface = iwl_mac_remove_interface,
  2520. .config = iwl_mac_config,
  2521. .configure_filter = iwl_configure_filter,
  2522. .set_key = iwl_mac_set_key,
  2523. .update_tkip_key = iwl_mac_update_tkip_key,
  2524. .get_stats = iwl_mac_get_stats,
  2525. .get_tx_stats = iwl_mac_get_tx_stats,
  2526. .conf_tx = iwl_mac_conf_tx,
  2527. .reset_tsf = iwl_mac_reset_tsf,
  2528. .bss_info_changed = iwl_bss_info_changed,
  2529. .ampdu_action = iwl_mac_ampdu_action,
  2530. .hw_scan = iwl_mac_hw_scan
  2531. };
  2532. static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  2533. {
  2534. int err = 0;
  2535. struct iwl_priv *priv;
  2536. struct ieee80211_hw *hw;
  2537. struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
  2538. unsigned long flags;
  2539. u16 pci_cmd;
  2540. /************************
  2541. * 1. Allocating HW data
  2542. ************************/
  2543. /* Disabling hardware scan means that mac80211 will perform scans
  2544. * "the hard way", rather than using device's scan. */
  2545. if (cfg->mod_params->disable_hw_scan) {
  2546. if (iwl_debug_level & IWL_DL_INFO)
  2547. dev_printk(KERN_DEBUG, &(pdev->dev),
  2548. "Disabling hw_scan\n");
  2549. iwl_hw_ops.hw_scan = NULL;
  2550. }
  2551. hw = iwl_alloc_all(cfg, &iwl_hw_ops);
  2552. if (!hw) {
  2553. err = -ENOMEM;
  2554. goto out;
  2555. }
  2556. priv = hw->priv;
  2557. /* At this point both hw and priv are allocated. */
  2558. SET_IEEE80211_DEV(hw, &pdev->dev);
  2559. IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
  2560. priv->cfg = cfg;
  2561. priv->pci_dev = pdev;
  2562. priv->inta_mask = CSR_INI_SET_MASK;
  2563. #ifdef CONFIG_IWLWIFI_DEBUG
  2564. atomic_set(&priv->restrict_refcnt, 0);
  2565. #endif
  2566. if (iwl_alloc_traffic_mem(priv))
  2567. IWL_ERR(priv, "Not enough memory to generate traffic log\n");
  2568. /**************************
  2569. * 2. Initializing PCI bus
  2570. **************************/
  2571. if (pci_enable_device(pdev)) {
  2572. err = -ENODEV;
  2573. goto out_ieee80211_free_hw;
  2574. }
  2575. pci_set_master(pdev);
  2576. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
  2577. if (!err)
  2578. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
  2579. if (err) {
  2580. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  2581. if (!err)
  2582. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
  2583. /* both attempts failed: */
  2584. if (err) {
  2585. IWL_WARN(priv, "No suitable DMA available.\n");
  2586. goto out_pci_disable_device;
  2587. }
  2588. }
  2589. err = pci_request_regions(pdev, DRV_NAME);
  2590. if (err)
  2591. goto out_pci_disable_device;
  2592. pci_set_drvdata(pdev, priv);
  2593. /***********************
  2594. * 3. Read REV register
  2595. ***********************/
  2596. priv->hw_base = pci_iomap(pdev, 0, 0);
  2597. if (!priv->hw_base) {
  2598. err = -ENODEV;
  2599. goto out_pci_release_regions;
  2600. }
  2601. IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
  2602. (unsigned long long) pci_resource_len(pdev, 0));
  2603. IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
  2604. /* this spin lock will be used in apm_ops.init and EEPROM access
  2605. * we should init now
  2606. */
  2607. spin_lock_init(&priv->reg_lock);
  2608. iwl_hw_detect(priv);
  2609. IWL_INFO(priv, "Detected Intel Wireless WiFi Link %s REV=0x%X\n",
  2610. priv->cfg->name, priv->hw_rev);
  2611. /* We disable the RETRY_TIMEOUT register (0x41) to keep
  2612. * PCI Tx retries from interfering with C3 CPU state */
  2613. pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
  2614. iwl_prepare_card_hw(priv);
  2615. if (!priv->hw_ready) {
  2616. IWL_WARN(priv, "Failed, HW not ready\n");
  2617. goto out_iounmap;
  2618. }
  2619. /*****************
  2620. * 4. Read EEPROM
  2621. *****************/
  2622. /* Read the EEPROM */
  2623. err = iwl_eeprom_init(priv);
  2624. if (err) {
  2625. IWL_ERR(priv, "Unable to init EEPROM\n");
  2626. goto out_iounmap;
  2627. }
  2628. err = iwl_eeprom_check_version(priv);
  2629. if (err)
  2630. goto out_free_eeprom;
  2631. /* extract MAC Address */
  2632. iwl_eeprom_get_mac(priv, priv->mac_addr);
  2633. IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->mac_addr);
  2634. SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
  2635. /************************
  2636. * 5. Setup HW constants
  2637. ************************/
  2638. if (iwl_set_hw_params(priv)) {
  2639. IWL_ERR(priv, "failed to set hw parameters\n");
  2640. goto out_free_eeprom;
  2641. }
  2642. /*******************
  2643. * 6. Setup priv
  2644. *******************/
  2645. err = iwl_init_drv(priv);
  2646. if (err)
  2647. goto out_free_eeprom;
  2648. /* At this point both hw and priv are initialized. */
  2649. /********************
  2650. * 7. Setup services
  2651. ********************/
  2652. spin_lock_irqsave(&priv->lock, flags);
  2653. iwl_disable_interrupts(priv);
  2654. spin_unlock_irqrestore(&priv->lock, flags);
  2655. pci_enable_msi(priv->pci_dev);
  2656. iwl_alloc_isr_ict(priv);
  2657. err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr,
  2658. IRQF_SHARED, DRV_NAME, priv);
  2659. if (err) {
  2660. IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
  2661. goto out_disable_msi;
  2662. }
  2663. err = sysfs_create_group(&pdev->dev.kobj, &iwl_attribute_group);
  2664. if (err) {
  2665. IWL_ERR(priv, "failed to create sysfs device attributes\n");
  2666. goto out_free_irq;
  2667. }
  2668. iwl_setup_deferred_work(priv);
  2669. iwl_setup_rx_handlers(priv);
  2670. /**********************************
  2671. * 8. Setup and register mac80211
  2672. **********************************/
  2673. /* enable interrupts if needed: hw bug w/a */
  2674. pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
  2675. if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
  2676. pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
  2677. pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
  2678. }
  2679. iwl_enable_interrupts(priv);
  2680. err = iwl_setup_mac(priv);
  2681. if (err)
  2682. goto out_remove_sysfs;
  2683. err = iwl_dbgfs_register(priv, DRV_NAME);
  2684. if (err)
  2685. IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
  2686. /* If platform's RF_KILL switch is NOT set to KILL */
  2687. if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
  2688. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  2689. else
  2690. set_bit(STATUS_RF_KILL_HW, &priv->status);
  2691. wiphy_rfkill_set_hw_state(priv->hw->wiphy,
  2692. test_bit(STATUS_RF_KILL_HW, &priv->status));
  2693. iwl_power_initialize(priv);
  2694. iwl_tt_initialize(priv);
  2695. return 0;
  2696. out_remove_sysfs:
  2697. destroy_workqueue(priv->workqueue);
  2698. priv->workqueue = NULL;
  2699. sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
  2700. out_free_irq:
  2701. free_irq(priv->pci_dev->irq, priv);
  2702. iwl_free_isr_ict(priv);
  2703. out_disable_msi:
  2704. pci_disable_msi(priv->pci_dev);
  2705. iwl_uninit_drv(priv);
  2706. out_free_eeprom:
  2707. iwl_eeprom_free(priv);
  2708. out_iounmap:
  2709. pci_iounmap(pdev, priv->hw_base);
  2710. out_pci_release_regions:
  2711. pci_set_drvdata(pdev, NULL);
  2712. pci_release_regions(pdev);
  2713. out_pci_disable_device:
  2714. pci_disable_device(pdev);
  2715. out_ieee80211_free_hw:
  2716. iwl_free_traffic_mem(priv);
  2717. ieee80211_free_hw(priv->hw);
  2718. out:
  2719. return err;
  2720. }
  2721. static void __devexit iwl_pci_remove(struct pci_dev *pdev)
  2722. {
  2723. struct iwl_priv *priv = pci_get_drvdata(pdev);
  2724. unsigned long flags;
  2725. if (!priv)
  2726. return;
  2727. IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
  2728. iwl_dbgfs_unregister(priv);
  2729. sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
  2730. /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
  2731. * to be called and iwl_down since we are removing the device
  2732. * we need to set STATUS_EXIT_PENDING bit.
  2733. */
  2734. set_bit(STATUS_EXIT_PENDING, &priv->status);
  2735. if (priv->mac80211_registered) {
  2736. ieee80211_unregister_hw(priv->hw);
  2737. priv->mac80211_registered = 0;
  2738. } else {
  2739. iwl_down(priv);
  2740. }
  2741. /*
  2742. * Make sure device is reset to low power before unloading driver.
  2743. * This may be redundant with iwl_down(), but there are paths to
  2744. * run iwl_down() without calling apm_ops.stop(), and there are
  2745. * paths to avoid running iwl_down() at all before leaving driver.
  2746. * This (inexpensive) call *makes sure* device is reset.
  2747. */
  2748. priv->cfg->ops->lib->apm_ops.stop(priv);
  2749. iwl_tt_exit(priv);
  2750. /* make sure we flush any pending irq or
  2751. * tasklet for the driver
  2752. */
  2753. spin_lock_irqsave(&priv->lock, flags);
  2754. iwl_disable_interrupts(priv);
  2755. spin_unlock_irqrestore(&priv->lock, flags);
  2756. iwl_synchronize_irq(priv);
  2757. iwl_dealloc_ucode_pci(priv);
  2758. if (priv->rxq.bd)
  2759. iwl_rx_queue_free(priv, &priv->rxq);
  2760. iwl_hw_txq_ctx_free(priv);
  2761. iwl_clear_stations_table(priv);
  2762. iwl_eeprom_free(priv);
  2763. /*netif_stop_queue(dev); */
  2764. flush_workqueue(priv->workqueue);
  2765. /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
  2766. * priv->workqueue... so we can't take down the workqueue
  2767. * until now... */
  2768. destroy_workqueue(priv->workqueue);
  2769. priv->workqueue = NULL;
  2770. iwl_free_traffic_mem(priv);
  2771. free_irq(priv->pci_dev->irq, priv);
  2772. pci_disable_msi(priv->pci_dev);
  2773. pci_iounmap(pdev, priv->hw_base);
  2774. pci_release_regions(pdev);
  2775. pci_disable_device(pdev);
  2776. pci_set_drvdata(pdev, NULL);
  2777. iwl_uninit_drv(priv);
  2778. iwl_free_isr_ict(priv);
  2779. if (priv->ibss_beacon)
  2780. dev_kfree_skb(priv->ibss_beacon);
  2781. ieee80211_free_hw(priv->hw);
  2782. }
  2783. /*****************************************************************************
  2784. *
  2785. * driver and module entry point
  2786. *
  2787. *****************************************************************************/
  2788. /* Hardware specific file defines the PCI IDs table for that hardware module */
  2789. static struct pci_device_id iwl_hw_card_ids[] = {
  2790. #ifdef CONFIG_IWL4965
  2791. {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_agn_cfg)},
  2792. {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_agn_cfg)},
  2793. #endif /* CONFIG_IWL4965 */
  2794. #ifdef CONFIG_IWL5000
  2795. {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bg_cfg)},
  2796. {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bg_cfg)},
  2797. {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)},
  2798. {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)},
  2799. {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)},
  2800. {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)},
  2801. {IWL_PCI_DEVICE(0x4232, PCI_ANY_ID, iwl5100_agn_cfg)},
  2802. {IWL_PCI_DEVICE(0x4235, PCI_ANY_ID, iwl5300_agn_cfg)},
  2803. {IWL_PCI_DEVICE(0x4236, PCI_ANY_ID, iwl5300_agn_cfg)},
  2804. {IWL_PCI_DEVICE(0x4237, PCI_ANY_ID, iwl5100_agn_cfg)},
  2805. /* 5350 WiFi/WiMax */
  2806. {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)},
  2807. {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)},
  2808. {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)},
  2809. /* 5150 Wifi/WiMax */
  2810. {IWL_PCI_DEVICE(0x423C, PCI_ANY_ID, iwl5150_agn_cfg)},
  2811. {IWL_PCI_DEVICE(0x423D, PCI_ANY_ID, iwl5150_agn_cfg)},
  2812. /* 6x00 Series */
  2813. {IWL_PCI_DEVICE(0x008D, 0x1301, iwl6000h_2agn_cfg)},
  2814. {IWL_PCI_DEVICE(0x008D, 0x1321, iwl6000h_2agn_cfg)},
  2815. {IWL_PCI_DEVICE(0x008D, 0x1326, iwl6000h_2abg_cfg)},
  2816. {IWL_PCI_DEVICE(0x008D, 0x1306, iwl6000h_2abg_cfg)},
  2817. {IWL_PCI_DEVICE(0x008D, 0x1307, iwl6000h_2bg_cfg)},
  2818. {IWL_PCI_DEVICE(0x008E, 0x1311, iwl6000h_2agn_cfg)},
  2819. {IWL_PCI_DEVICE(0x008E, 0x1316, iwl6000h_2abg_cfg)},
  2820. {IWL_PCI_DEVICE(0x422B, 0x1101, iwl6000_3agn_cfg)},
  2821. {IWL_PCI_DEVICE(0x422B, 0x1121, iwl6000_3agn_cfg)},
  2822. {IWL_PCI_DEVICE(0x422C, 0x1301, iwl6000i_2agn_cfg)},
  2823. {IWL_PCI_DEVICE(0x422C, 0x1306, iwl6000i_2abg_cfg)},
  2824. {IWL_PCI_DEVICE(0x422C, 0x1307, iwl6000i_2bg_cfg)},
  2825. {IWL_PCI_DEVICE(0x422C, 0x1321, iwl6000i_2agn_cfg)},
  2826. {IWL_PCI_DEVICE(0x422C, 0x1326, iwl6000i_2abg_cfg)},
  2827. {IWL_PCI_DEVICE(0x4238, 0x1111, iwl6000_3agn_cfg)},
  2828. {IWL_PCI_DEVICE(0x4239, 0x1311, iwl6000i_2agn_cfg)},
  2829. {IWL_PCI_DEVICE(0x4239, 0x1316, iwl6000i_2abg_cfg)},
  2830. /* 6x50 WiFi/WiMax Series */
  2831. {IWL_PCI_DEVICE(0x0086, 0x1101, iwl6050_3agn_cfg)},
  2832. {IWL_PCI_DEVICE(0x0086, 0x1121, iwl6050_3agn_cfg)},
  2833. {IWL_PCI_DEVICE(0x0087, 0x1301, iwl6050_2agn_cfg)},
  2834. {IWL_PCI_DEVICE(0x0087, 0x1306, iwl6050_2abg_cfg)},
  2835. {IWL_PCI_DEVICE(0x0087, 0x1321, iwl6050_2agn_cfg)},
  2836. {IWL_PCI_DEVICE(0x0087, 0x1326, iwl6050_2abg_cfg)},
  2837. {IWL_PCI_DEVICE(0x0088, 0x1111, iwl6050_3agn_cfg)},
  2838. {IWL_PCI_DEVICE(0x0089, 0x1311, iwl6050_2agn_cfg)},
  2839. {IWL_PCI_DEVICE(0x0089, 0x1316, iwl6050_2abg_cfg)},
  2840. /* 1000 Series WiFi */
  2841. {IWL_PCI_DEVICE(0x0083, 0x1205, iwl1000_bgn_cfg)},
  2842. {IWL_PCI_DEVICE(0x0083, 0x1305, iwl1000_bgn_cfg)},
  2843. {IWL_PCI_DEVICE(0x0083, 0x1225, iwl1000_bgn_cfg)},
  2844. {IWL_PCI_DEVICE(0x0083, 0x1325, iwl1000_bgn_cfg)},
  2845. {IWL_PCI_DEVICE(0x0084, 0x1215, iwl1000_bgn_cfg)},
  2846. {IWL_PCI_DEVICE(0x0084, 0x1315, iwl1000_bgn_cfg)},
  2847. {IWL_PCI_DEVICE(0x0083, 0x1206, iwl1000_bg_cfg)},
  2848. {IWL_PCI_DEVICE(0x0083, 0x1306, iwl1000_bg_cfg)},
  2849. {IWL_PCI_DEVICE(0x0083, 0x1226, iwl1000_bg_cfg)},
  2850. {IWL_PCI_DEVICE(0x0083, 0x1326, iwl1000_bg_cfg)},
  2851. {IWL_PCI_DEVICE(0x0084, 0x1216, iwl1000_bg_cfg)},
  2852. {IWL_PCI_DEVICE(0x0084, 0x1316, iwl1000_bg_cfg)},
  2853. #endif /* CONFIG_IWL5000 */
  2854. {0}
  2855. };
  2856. MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
  2857. static struct pci_driver iwl_driver = {
  2858. .name = DRV_NAME,
  2859. .id_table = iwl_hw_card_ids,
  2860. .probe = iwl_pci_probe,
  2861. .remove = __devexit_p(iwl_pci_remove),
  2862. #ifdef CONFIG_PM
  2863. .suspend = iwl_pci_suspend,
  2864. .resume = iwl_pci_resume,
  2865. #endif
  2866. };
  2867. static int __init iwl_init(void)
  2868. {
  2869. int ret;
  2870. printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
  2871. printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
  2872. ret = iwlagn_rate_control_register();
  2873. if (ret) {
  2874. printk(KERN_ERR DRV_NAME
  2875. "Unable to register rate control algorithm: %d\n", ret);
  2876. return ret;
  2877. }
  2878. ret = pci_register_driver(&iwl_driver);
  2879. if (ret) {
  2880. printk(KERN_ERR DRV_NAME "Unable to initialize PCI module\n");
  2881. goto error_register;
  2882. }
  2883. return ret;
  2884. error_register:
  2885. iwlagn_rate_control_unregister();
  2886. return ret;
  2887. }
  2888. static void __exit iwl_exit(void)
  2889. {
  2890. pci_unregister_driver(&iwl_driver);
  2891. iwlagn_rate_control_unregister();
  2892. }
  2893. module_exit(iwl_exit);
  2894. module_init(iwl_init);
  2895. #ifdef CONFIG_IWLWIFI_DEBUG
  2896. module_param_named(debug50, iwl_debug_level, uint, S_IRUGO);
  2897. MODULE_PARM_DESC(debug50, "50XX debug output mask (deprecated)");
  2898. module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR);
  2899. MODULE_PARM_DESC(debug, "debug output mask");
  2900. #endif