ax88179_178a.c 37 KB

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  1. /*
  2. * ASIX AX88179/178A USB 3.0/2.0 to Gigabit Ethernet Devices
  3. *
  4. * Copyright (C) 2011-2013 ASIX
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License
  8. * as published by the Free Software Foundation; either version 2
  9. * of the License, or (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19. */
  20. #include <linux/module.h>
  21. #include <linux/etherdevice.h>
  22. #include <linux/mii.h>
  23. #include <linux/usb.h>
  24. #include <linux/crc32.h>
  25. #include <linux/usb/usbnet.h>
  26. #define AX88179_PHY_ID 0x03
  27. #define AX_EEPROM_LEN 0x100
  28. #define AX88179_EEPROM_MAGIC 0x17900b95
  29. #define AX_MCAST_FLTSIZE 8
  30. #define AX_MAX_MCAST 64
  31. #define AX_INT_PPLS_LINK ((u32)BIT(16))
  32. #define AX_RXHDR_L4_TYPE_MASK 0x1c
  33. #define AX_RXHDR_L4_TYPE_UDP 4
  34. #define AX_RXHDR_L4_TYPE_TCP 16
  35. #define AX_RXHDR_L3CSUM_ERR 2
  36. #define AX_RXHDR_L4CSUM_ERR 1
  37. #define AX_RXHDR_CRC_ERR ((u32)BIT(31))
  38. #define AX_RXHDR_DROP_ERR ((u32)BIT(30))
  39. #define AX_ACCESS_MAC 0x01
  40. #define AX_ACCESS_PHY 0x02
  41. #define AX_ACCESS_EEPROM 0x04
  42. #define AX_ACCESS_EFUS 0x05
  43. #define AX_PAUSE_WATERLVL_HIGH 0x54
  44. #define AX_PAUSE_WATERLVL_LOW 0x55
  45. #define PHYSICAL_LINK_STATUS 0x02
  46. #define AX_USB_SS 0x04
  47. #define AX_USB_HS 0x02
  48. #define GENERAL_STATUS 0x03
  49. /* Check AX88179 version. UA1:Bit2 = 0, UA2:Bit2 = 1 */
  50. #define AX_SECLD 0x04
  51. #define AX_SROM_ADDR 0x07
  52. #define AX_SROM_CMD 0x0a
  53. #define EEP_RD 0x04
  54. #define EEP_BUSY 0x10
  55. #define AX_SROM_DATA_LOW 0x08
  56. #define AX_SROM_DATA_HIGH 0x09
  57. #define AX_RX_CTL 0x0b
  58. #define AX_RX_CTL_DROPCRCERR 0x0100
  59. #define AX_RX_CTL_IPE 0x0200
  60. #define AX_RX_CTL_START 0x0080
  61. #define AX_RX_CTL_AP 0x0020
  62. #define AX_RX_CTL_AM 0x0010
  63. #define AX_RX_CTL_AB 0x0008
  64. #define AX_RX_CTL_AMALL 0x0002
  65. #define AX_RX_CTL_PRO 0x0001
  66. #define AX_RX_CTL_STOP 0x0000
  67. #define AX_NODE_ID 0x10
  68. #define AX_MULFLTARY 0x16
  69. #define AX_MEDIUM_STATUS_MODE 0x22
  70. #define AX_MEDIUM_GIGAMODE 0x01
  71. #define AX_MEDIUM_FULL_DUPLEX 0x02
  72. #define AX_MEDIUM_ALWAYS_ONE 0x04
  73. #define AX_MEDIUM_EN_125MHZ 0x08
  74. #define AX_MEDIUM_RXFLOW_CTRLEN 0x10
  75. #define AX_MEDIUM_TXFLOW_CTRLEN 0x20
  76. #define AX_MEDIUM_RECEIVE_EN 0x100
  77. #define AX_MEDIUM_PS 0x200
  78. #define AX_MEDIUM_JUMBO_EN 0x8040
  79. #define AX_MONITOR_MOD 0x24
  80. #define AX_MONITOR_MODE_RWLC 0x02
  81. #define AX_MONITOR_MODE_RWMP 0x04
  82. #define AX_MONITOR_MODE_PMEPOL 0x20
  83. #define AX_MONITOR_MODE_PMETYPE 0x40
  84. #define AX_GPIO_CTRL 0x25
  85. #define AX_GPIO_CTRL_GPIO3EN 0x80
  86. #define AX_GPIO_CTRL_GPIO2EN 0x40
  87. #define AX_GPIO_CTRL_GPIO1EN 0x20
  88. #define AX_PHYPWR_RSTCTL 0x26
  89. #define AX_PHYPWR_RSTCTL_BZ 0x0010
  90. #define AX_PHYPWR_RSTCTL_IPRL 0x0020
  91. #define AX_PHYPWR_RSTCTL_AT 0x1000
  92. #define AX_RX_BULKIN_QCTRL 0x2e
  93. #define AX_CLK_SELECT 0x33
  94. #define AX_CLK_SELECT_BCS 0x01
  95. #define AX_CLK_SELECT_ACS 0x02
  96. #define AX_CLK_SELECT_ULR 0x08
  97. #define AX_RXCOE_CTL 0x34
  98. #define AX_RXCOE_IP 0x01
  99. #define AX_RXCOE_TCP 0x02
  100. #define AX_RXCOE_UDP 0x04
  101. #define AX_RXCOE_TCPV6 0x20
  102. #define AX_RXCOE_UDPV6 0x40
  103. #define AX_TXCOE_CTL 0x35
  104. #define AX_TXCOE_IP 0x01
  105. #define AX_TXCOE_TCP 0x02
  106. #define AX_TXCOE_UDP 0x04
  107. #define AX_TXCOE_TCPV6 0x20
  108. #define AX_TXCOE_UDPV6 0x40
  109. #define AX_LEDCTRL 0x73
  110. #define GMII_PHY_PHYSR 0x11
  111. #define GMII_PHY_PHYSR_SMASK 0xc000
  112. #define GMII_PHY_PHYSR_GIGA 0x8000
  113. #define GMII_PHY_PHYSR_100 0x4000
  114. #define GMII_PHY_PHYSR_FULL 0x2000
  115. #define GMII_PHY_PHYSR_LINK 0x400
  116. #define GMII_LED_ACT 0x1a
  117. #define GMII_LED_ACTIVE_MASK 0xff8f
  118. #define GMII_LED0_ACTIVE BIT(4)
  119. #define GMII_LED1_ACTIVE BIT(5)
  120. #define GMII_LED2_ACTIVE BIT(6)
  121. #define GMII_LED_LINK 0x1c
  122. #define GMII_LED_LINK_MASK 0xf888
  123. #define GMII_LED0_LINK_10 BIT(0)
  124. #define GMII_LED0_LINK_100 BIT(1)
  125. #define GMII_LED0_LINK_1000 BIT(2)
  126. #define GMII_LED1_LINK_10 BIT(4)
  127. #define GMII_LED1_LINK_100 BIT(5)
  128. #define GMII_LED1_LINK_1000 BIT(6)
  129. #define GMII_LED2_LINK_10 BIT(8)
  130. #define GMII_LED2_LINK_100 BIT(9)
  131. #define GMII_LED2_LINK_1000 BIT(10)
  132. #define LED0_ACTIVE BIT(0)
  133. #define LED0_LINK_10 BIT(1)
  134. #define LED0_LINK_100 BIT(2)
  135. #define LED0_LINK_1000 BIT(3)
  136. #define LED0_FD BIT(4)
  137. #define LED0_USB3_MASK 0x001f
  138. #define LED1_ACTIVE BIT(5)
  139. #define LED1_LINK_10 BIT(6)
  140. #define LED1_LINK_100 BIT(7)
  141. #define LED1_LINK_1000 BIT(8)
  142. #define LED1_FD BIT(9)
  143. #define LED1_USB3_MASK 0x03e0
  144. #define LED2_ACTIVE BIT(10)
  145. #define LED2_LINK_1000 BIT(13)
  146. #define LED2_LINK_100 BIT(12)
  147. #define LED2_LINK_10 BIT(11)
  148. #define LED2_FD BIT(14)
  149. #define LED_VALID BIT(15)
  150. #define LED2_USB3_MASK 0x7c00
  151. #define GMII_PHYPAGE 0x1e
  152. #define GMII_PHY_PAGE_SELECT 0x1f
  153. #define GMII_PHY_PGSEL_EXT 0x0007
  154. #define GMII_PHY_PGSEL_PAGE0 0x0000
  155. struct ax88179_data {
  156. u16 rxctl;
  157. u16 reserved;
  158. };
  159. struct ax88179_int_data {
  160. __le32 intdata1;
  161. __le32 intdata2;
  162. };
  163. static const struct {
  164. unsigned char ctrl, timer_l, timer_h, size, ifg;
  165. } AX88179_BULKIN_SIZE[] = {
  166. {7, 0x4f, 0, 0x12, 0xff},
  167. {7, 0x20, 3, 0x16, 0xff},
  168. {7, 0xae, 7, 0x18, 0xff},
  169. {7, 0xcc, 0x4c, 0x18, 8},
  170. };
  171. static int __ax88179_read_cmd(struct usbnet *dev, u8 cmd, u16 value, u16 index,
  172. u16 size, void *data, int in_pm)
  173. {
  174. int ret;
  175. int (*fn)(struct usbnet *, u8, u8, u16, u16, void *, u16);
  176. BUG_ON(!dev);
  177. if (!in_pm)
  178. fn = usbnet_read_cmd;
  179. else
  180. fn = usbnet_read_cmd_nopm;
  181. ret = fn(dev, cmd, USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  182. value, index, data, size);
  183. if (unlikely(ret < 0))
  184. netdev_warn(dev->net, "Failed to read reg index 0x%04x: %d\n",
  185. index, ret);
  186. return ret;
  187. }
  188. static int __ax88179_write_cmd(struct usbnet *dev, u8 cmd, u16 value, u16 index,
  189. u16 size, void *data, int in_pm)
  190. {
  191. int ret;
  192. int (*fn)(struct usbnet *, u8, u8, u16, u16, const void *, u16);
  193. BUG_ON(!dev);
  194. if (!in_pm)
  195. fn = usbnet_write_cmd;
  196. else
  197. fn = usbnet_write_cmd_nopm;
  198. ret = fn(dev, cmd, USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  199. value, index, data, size);
  200. if (unlikely(ret < 0))
  201. netdev_warn(dev->net, "Failed to write reg index 0x%04x: %d\n",
  202. index, ret);
  203. return ret;
  204. }
  205. static void ax88179_write_cmd_async(struct usbnet *dev, u8 cmd, u16 value,
  206. u16 index, u16 size, void *data)
  207. {
  208. u16 buf;
  209. if (2 == size) {
  210. buf = *((u16 *)data);
  211. cpu_to_le16s(&buf);
  212. usbnet_write_cmd_async(dev, cmd, USB_DIR_OUT | USB_TYPE_VENDOR |
  213. USB_RECIP_DEVICE, value, index, &buf,
  214. size);
  215. } else {
  216. usbnet_write_cmd_async(dev, cmd, USB_DIR_OUT | USB_TYPE_VENDOR |
  217. USB_RECIP_DEVICE, value, index, data,
  218. size);
  219. }
  220. }
  221. static int ax88179_read_cmd_nopm(struct usbnet *dev, u8 cmd, u16 value,
  222. u16 index, u16 size, void *data)
  223. {
  224. int ret;
  225. if (2 == size) {
  226. u16 buf;
  227. ret = __ax88179_read_cmd(dev, cmd, value, index, size, &buf, 1);
  228. le16_to_cpus(&buf);
  229. *((u16 *)data) = buf;
  230. } else if (4 == size) {
  231. u32 buf;
  232. ret = __ax88179_read_cmd(dev, cmd, value, index, size, &buf, 1);
  233. le32_to_cpus(&buf);
  234. *((u32 *)data) = buf;
  235. } else {
  236. ret = __ax88179_read_cmd(dev, cmd, value, index, size, data, 1);
  237. }
  238. return ret;
  239. }
  240. static int ax88179_write_cmd_nopm(struct usbnet *dev, u8 cmd, u16 value,
  241. u16 index, u16 size, void *data)
  242. {
  243. int ret;
  244. if (2 == size) {
  245. u16 buf;
  246. buf = *((u16 *)data);
  247. cpu_to_le16s(&buf);
  248. ret = __ax88179_write_cmd(dev, cmd, value, index,
  249. size, &buf, 1);
  250. } else {
  251. ret = __ax88179_write_cmd(dev, cmd, value, index,
  252. size, data, 1);
  253. }
  254. return ret;
  255. }
  256. static int ax88179_read_cmd(struct usbnet *dev, u8 cmd, u16 value, u16 index,
  257. u16 size, void *data)
  258. {
  259. int ret;
  260. if (2 == size) {
  261. u16 buf;
  262. ret = __ax88179_read_cmd(dev, cmd, value, index, size, &buf, 0);
  263. le16_to_cpus(&buf);
  264. *((u16 *)data) = buf;
  265. } else if (4 == size) {
  266. u32 buf;
  267. ret = __ax88179_read_cmd(dev, cmd, value, index, size, &buf, 0);
  268. le32_to_cpus(&buf);
  269. *((u32 *)data) = buf;
  270. } else {
  271. ret = __ax88179_read_cmd(dev, cmd, value, index, size, data, 0);
  272. }
  273. return ret;
  274. }
  275. static int ax88179_write_cmd(struct usbnet *dev, u8 cmd, u16 value, u16 index,
  276. u16 size, void *data)
  277. {
  278. int ret;
  279. if (2 == size) {
  280. u16 buf;
  281. buf = *((u16 *)data);
  282. cpu_to_le16s(&buf);
  283. ret = __ax88179_write_cmd(dev, cmd, value, index,
  284. size, &buf, 0);
  285. } else {
  286. ret = __ax88179_write_cmd(dev, cmd, value, index,
  287. size, data, 0);
  288. }
  289. return ret;
  290. }
  291. static void ax88179_status(struct usbnet *dev, struct urb *urb)
  292. {
  293. struct ax88179_int_data *event;
  294. u32 link;
  295. if (urb->actual_length < 8)
  296. return;
  297. event = urb->transfer_buffer;
  298. le32_to_cpus((void *)&event->intdata1);
  299. link = (((__force u32)event->intdata1) & AX_INT_PPLS_LINK) >> 16;
  300. if (netif_carrier_ok(dev->net) != link) {
  301. usbnet_link_change(dev, link, 1);
  302. netdev_info(dev->net, "ax88179 - Link status is: %d\n", link);
  303. }
  304. }
  305. static int ax88179_mdio_read(struct net_device *netdev, int phy_id, int loc)
  306. {
  307. struct usbnet *dev = netdev_priv(netdev);
  308. u16 res;
  309. ax88179_read_cmd(dev, AX_ACCESS_PHY, phy_id, (__u16)loc, 2, &res);
  310. return res;
  311. }
  312. static void ax88179_mdio_write(struct net_device *netdev, int phy_id, int loc,
  313. int val)
  314. {
  315. struct usbnet *dev = netdev_priv(netdev);
  316. u16 res = (u16) val;
  317. ax88179_write_cmd(dev, AX_ACCESS_PHY, phy_id, (__u16)loc, 2, &res);
  318. }
  319. static int ax88179_suspend(struct usb_interface *intf, pm_message_t message)
  320. {
  321. struct usbnet *dev = usb_get_intfdata(intf);
  322. u16 tmp16;
  323. u8 tmp8;
  324. usbnet_suspend(intf, message);
  325. /* Disable RX path */
  326. ax88179_read_cmd_nopm(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE,
  327. 2, 2, &tmp16);
  328. tmp16 &= ~AX_MEDIUM_RECEIVE_EN;
  329. ax88179_write_cmd_nopm(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE,
  330. 2, 2, &tmp16);
  331. /* Force bulk-in zero length */
  332. ax88179_read_cmd_nopm(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL,
  333. 2, 2, &tmp16);
  334. tmp16 |= AX_PHYPWR_RSTCTL_BZ | AX_PHYPWR_RSTCTL_IPRL;
  335. ax88179_write_cmd_nopm(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL,
  336. 2, 2, &tmp16);
  337. /* change clock */
  338. tmp8 = 0;
  339. ax88179_write_cmd_nopm(dev, AX_ACCESS_MAC, AX_CLK_SELECT, 1, 1, &tmp8);
  340. /* Configure RX control register => stop operation */
  341. tmp16 = AX_RX_CTL_STOP;
  342. ax88179_write_cmd_nopm(dev, AX_ACCESS_MAC, AX_RX_CTL, 2, 2, &tmp16);
  343. return 0;
  344. }
  345. /* This function is used to enable the autodetach function. */
  346. /* This function is determined by offset 0x43 of EEPROM */
  347. static int ax88179_auto_detach(struct usbnet *dev, int in_pm)
  348. {
  349. u16 tmp16;
  350. u8 tmp8;
  351. int (*fnr)(struct usbnet *, u8, u16, u16, u16, void *);
  352. int (*fnw)(struct usbnet *, u8, u16, u16, u16, void *);
  353. if (!in_pm) {
  354. fnr = ax88179_read_cmd;
  355. fnw = ax88179_write_cmd;
  356. } else {
  357. fnr = ax88179_read_cmd_nopm;
  358. fnw = ax88179_write_cmd_nopm;
  359. }
  360. if (fnr(dev, AX_ACCESS_EEPROM, 0x43, 1, 2, &tmp16) < 0)
  361. return 0;
  362. if ((tmp16 == 0xFFFF) || (!(tmp16 & 0x0100)))
  363. return 0;
  364. /* Enable Auto Detach bit */
  365. tmp8 = 0;
  366. fnr(dev, AX_ACCESS_MAC, AX_CLK_SELECT, 1, 1, &tmp8);
  367. tmp8 |= AX_CLK_SELECT_ULR;
  368. fnw(dev, AX_ACCESS_MAC, AX_CLK_SELECT, 1, 1, &tmp8);
  369. fnr(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 2, 2, &tmp16);
  370. tmp16 |= AX_PHYPWR_RSTCTL_AT;
  371. fnw(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 2, 2, &tmp16);
  372. return 0;
  373. }
  374. static int ax88179_resume(struct usb_interface *intf)
  375. {
  376. struct usbnet *dev = usb_get_intfdata(intf);
  377. u16 tmp16;
  378. u8 tmp8;
  379. usbnet_link_change(dev, 0, 0);
  380. /* Power up ethernet PHY */
  381. tmp16 = 0;
  382. ax88179_write_cmd_nopm(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL,
  383. 2, 2, &tmp16);
  384. udelay(1000);
  385. tmp16 = AX_PHYPWR_RSTCTL_IPRL;
  386. ax88179_write_cmd_nopm(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL,
  387. 2, 2, &tmp16);
  388. msleep(200);
  389. /* Ethernet PHY Auto Detach*/
  390. ax88179_auto_detach(dev, 1);
  391. /* Enable clock */
  392. ax88179_read_cmd_nopm(dev, AX_ACCESS_MAC, AX_CLK_SELECT, 1, 1, &tmp8);
  393. tmp8 |= AX_CLK_SELECT_ACS | AX_CLK_SELECT_BCS;
  394. ax88179_write_cmd_nopm(dev, AX_ACCESS_MAC, AX_CLK_SELECT, 1, 1, &tmp8);
  395. msleep(100);
  396. /* Configure RX control register => start operation */
  397. tmp16 = AX_RX_CTL_DROPCRCERR | AX_RX_CTL_IPE | AX_RX_CTL_START |
  398. AX_RX_CTL_AP | AX_RX_CTL_AMALL | AX_RX_CTL_AB;
  399. ax88179_write_cmd_nopm(dev, AX_ACCESS_MAC, AX_RX_CTL, 2, 2, &tmp16);
  400. return usbnet_resume(intf);
  401. }
  402. static void
  403. ax88179_get_wol(struct net_device *net, struct ethtool_wolinfo *wolinfo)
  404. {
  405. struct usbnet *dev = netdev_priv(net);
  406. u8 opt;
  407. if (ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_MONITOR_MOD,
  408. 1, 1, &opt) < 0) {
  409. wolinfo->supported = 0;
  410. wolinfo->wolopts = 0;
  411. return;
  412. }
  413. wolinfo->supported = WAKE_PHY | WAKE_MAGIC;
  414. wolinfo->wolopts = 0;
  415. if (opt & AX_MONITOR_MODE_RWLC)
  416. wolinfo->wolopts |= WAKE_PHY;
  417. if (opt & AX_MONITOR_MODE_RWMP)
  418. wolinfo->wolopts |= WAKE_MAGIC;
  419. }
  420. static int
  421. ax88179_set_wol(struct net_device *net, struct ethtool_wolinfo *wolinfo)
  422. {
  423. struct usbnet *dev = netdev_priv(net);
  424. u8 opt = 0;
  425. if (wolinfo->wolopts & WAKE_PHY)
  426. opt |= AX_MONITOR_MODE_RWLC;
  427. if (wolinfo->wolopts & WAKE_MAGIC)
  428. opt |= AX_MONITOR_MODE_RWMP;
  429. if (ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_MONITOR_MOD,
  430. 1, 1, &opt) < 0)
  431. return -EINVAL;
  432. return 0;
  433. }
  434. static int ax88179_get_eeprom_len(struct net_device *net)
  435. {
  436. return AX_EEPROM_LEN;
  437. }
  438. static int
  439. ax88179_get_eeprom(struct net_device *net, struct ethtool_eeprom *eeprom,
  440. u8 *data)
  441. {
  442. struct usbnet *dev = netdev_priv(net);
  443. u16 *eeprom_buff;
  444. int first_word, last_word;
  445. int i, ret;
  446. if (eeprom->len == 0)
  447. return -EINVAL;
  448. eeprom->magic = AX88179_EEPROM_MAGIC;
  449. first_word = eeprom->offset >> 1;
  450. last_word = (eeprom->offset + eeprom->len - 1) >> 1;
  451. eeprom_buff = kmalloc(sizeof(u16) * (last_word - first_word + 1),
  452. GFP_KERNEL);
  453. if (!eeprom_buff)
  454. return -ENOMEM;
  455. /* ax88179/178A returns 2 bytes from eeprom on read */
  456. for (i = first_word; i <= last_word; i++) {
  457. ret = __ax88179_read_cmd(dev, AX_ACCESS_EEPROM, i, 1, 2,
  458. &eeprom_buff[i - first_word],
  459. 0);
  460. if (ret < 0) {
  461. kfree(eeprom_buff);
  462. return -EIO;
  463. }
  464. }
  465. memcpy(data, (u8 *)eeprom_buff + (eeprom->offset & 1), eeprom->len);
  466. kfree(eeprom_buff);
  467. return 0;
  468. }
  469. static int ax88179_get_settings(struct net_device *net, struct ethtool_cmd *cmd)
  470. {
  471. struct usbnet *dev = netdev_priv(net);
  472. return mii_ethtool_gset(&dev->mii, cmd);
  473. }
  474. static int ax88179_set_settings(struct net_device *net, struct ethtool_cmd *cmd)
  475. {
  476. struct usbnet *dev = netdev_priv(net);
  477. return mii_ethtool_sset(&dev->mii, cmd);
  478. }
  479. static int ax88179_ioctl(struct net_device *net, struct ifreq *rq, int cmd)
  480. {
  481. struct usbnet *dev = netdev_priv(net);
  482. return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL);
  483. }
  484. static const struct ethtool_ops ax88179_ethtool_ops = {
  485. .get_link = ethtool_op_get_link,
  486. .get_msglevel = usbnet_get_msglevel,
  487. .set_msglevel = usbnet_set_msglevel,
  488. .get_wol = ax88179_get_wol,
  489. .set_wol = ax88179_set_wol,
  490. .get_eeprom_len = ax88179_get_eeprom_len,
  491. .get_eeprom = ax88179_get_eeprom,
  492. .get_settings = ax88179_get_settings,
  493. .set_settings = ax88179_set_settings,
  494. .nway_reset = usbnet_nway_reset,
  495. };
  496. static void ax88179_set_multicast(struct net_device *net)
  497. {
  498. struct usbnet *dev = netdev_priv(net);
  499. struct ax88179_data *data = (struct ax88179_data *)dev->data;
  500. u8 *m_filter = ((u8 *)dev->data) + 12;
  501. data->rxctl = (AX_RX_CTL_START | AX_RX_CTL_AB | AX_RX_CTL_IPE);
  502. if (net->flags & IFF_PROMISC) {
  503. data->rxctl |= AX_RX_CTL_PRO;
  504. } else if (net->flags & IFF_ALLMULTI ||
  505. netdev_mc_count(net) > AX_MAX_MCAST) {
  506. data->rxctl |= AX_RX_CTL_AMALL;
  507. } else if (netdev_mc_empty(net)) {
  508. /* just broadcast and directed */
  509. } else {
  510. /* We use the 20 byte dev->data for our 8 byte filter buffer
  511. * to avoid allocating memory that is tricky to free later
  512. */
  513. u32 crc_bits;
  514. struct netdev_hw_addr *ha;
  515. memset(m_filter, 0, AX_MCAST_FLTSIZE);
  516. netdev_for_each_mc_addr(ha, net) {
  517. crc_bits = ether_crc(ETH_ALEN, ha->addr) >> 26;
  518. *(m_filter + (crc_bits >> 3)) |= (1 << (crc_bits & 7));
  519. }
  520. ax88179_write_cmd_async(dev, AX_ACCESS_MAC, AX_MULFLTARY,
  521. AX_MCAST_FLTSIZE, AX_MCAST_FLTSIZE,
  522. m_filter);
  523. data->rxctl |= AX_RX_CTL_AM;
  524. }
  525. ax88179_write_cmd_async(dev, AX_ACCESS_MAC, AX_RX_CTL,
  526. 2, 2, &data->rxctl);
  527. }
  528. static int
  529. ax88179_set_features(struct net_device *net, netdev_features_t features)
  530. {
  531. u8 tmp;
  532. struct usbnet *dev = netdev_priv(net);
  533. netdev_features_t changed = net->features ^ features;
  534. if (changed & NETIF_F_IP_CSUM) {
  535. ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_TXCOE_CTL, 1, 1, &tmp);
  536. tmp ^= AX_TXCOE_TCP | AX_TXCOE_UDP;
  537. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_TXCOE_CTL, 1, 1, &tmp);
  538. }
  539. if (changed & NETIF_F_IPV6_CSUM) {
  540. ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_TXCOE_CTL, 1, 1, &tmp);
  541. tmp ^= AX_TXCOE_TCPV6 | AX_TXCOE_UDPV6;
  542. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_TXCOE_CTL, 1, 1, &tmp);
  543. }
  544. if (changed & NETIF_F_RXCSUM) {
  545. ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_RXCOE_CTL, 1, 1, &tmp);
  546. tmp ^= AX_RXCOE_IP | AX_RXCOE_TCP | AX_RXCOE_UDP |
  547. AX_RXCOE_TCPV6 | AX_RXCOE_UDPV6;
  548. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RXCOE_CTL, 1, 1, &tmp);
  549. }
  550. return 0;
  551. }
  552. static int ax88179_change_mtu(struct net_device *net, int new_mtu)
  553. {
  554. struct usbnet *dev = netdev_priv(net);
  555. u16 tmp16;
  556. if (new_mtu <= 0 || new_mtu > 4088)
  557. return -EINVAL;
  558. net->mtu = new_mtu;
  559. dev->hard_mtu = net->mtu + net->hard_header_len;
  560. if (net->mtu > 1500) {
  561. ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE,
  562. 2, 2, &tmp16);
  563. tmp16 |= AX_MEDIUM_JUMBO_EN;
  564. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE,
  565. 2, 2, &tmp16);
  566. } else {
  567. ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE,
  568. 2, 2, &tmp16);
  569. tmp16 &= ~AX_MEDIUM_JUMBO_EN;
  570. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE,
  571. 2, 2, &tmp16);
  572. }
  573. /* max qlen depend on hard_mtu and rx_urb_size */
  574. usbnet_update_max_qlen(dev);
  575. return 0;
  576. }
  577. static int ax88179_set_mac_addr(struct net_device *net, void *p)
  578. {
  579. struct usbnet *dev = netdev_priv(net);
  580. struct sockaddr *addr = p;
  581. if (netif_running(net))
  582. return -EBUSY;
  583. if (!is_valid_ether_addr(addr->sa_data))
  584. return -EADDRNOTAVAIL;
  585. memcpy(net->dev_addr, addr->sa_data, ETH_ALEN);
  586. /* Set the MAC address */
  587. return ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_NODE_ID, ETH_ALEN,
  588. ETH_ALEN, net->dev_addr);
  589. }
  590. static const struct net_device_ops ax88179_netdev_ops = {
  591. .ndo_open = usbnet_open,
  592. .ndo_stop = usbnet_stop,
  593. .ndo_start_xmit = usbnet_start_xmit,
  594. .ndo_tx_timeout = usbnet_tx_timeout,
  595. .ndo_change_mtu = ax88179_change_mtu,
  596. .ndo_set_mac_address = ax88179_set_mac_addr,
  597. .ndo_validate_addr = eth_validate_addr,
  598. .ndo_do_ioctl = ax88179_ioctl,
  599. .ndo_set_rx_mode = ax88179_set_multicast,
  600. .ndo_set_features = ax88179_set_features,
  601. };
  602. static int ax88179_check_eeprom(struct usbnet *dev)
  603. {
  604. u8 i, buf, eeprom[20];
  605. u16 csum, delay = HZ / 10;
  606. unsigned long jtimeout;
  607. /* Read EEPROM content */
  608. for (i = 0; i < 6; i++) {
  609. buf = i;
  610. if (ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_SROM_ADDR,
  611. 1, 1, &buf) < 0)
  612. return -EINVAL;
  613. buf = EEP_RD;
  614. if (ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_SROM_CMD,
  615. 1, 1, &buf) < 0)
  616. return -EINVAL;
  617. jtimeout = jiffies + delay;
  618. do {
  619. ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_SROM_CMD,
  620. 1, 1, &buf);
  621. if (time_after(jiffies, jtimeout))
  622. return -EINVAL;
  623. } while (buf & EEP_BUSY);
  624. __ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_SROM_DATA_LOW,
  625. 2, 2, &eeprom[i * 2], 0);
  626. if ((i == 0) && (eeprom[0] == 0xFF))
  627. return -EINVAL;
  628. }
  629. csum = eeprom[6] + eeprom[7] + eeprom[8] + eeprom[9];
  630. csum = (csum >> 8) + (csum & 0xff);
  631. if ((csum + eeprom[10]) != 0xff)
  632. return -EINVAL;
  633. return 0;
  634. }
  635. static int ax88179_check_efuse(struct usbnet *dev, u16 *ledmode)
  636. {
  637. u8 i;
  638. u8 efuse[64];
  639. u16 csum = 0;
  640. if (ax88179_read_cmd(dev, AX_ACCESS_EFUS, 0, 64, 64, efuse) < 0)
  641. return -EINVAL;
  642. if (*efuse == 0xFF)
  643. return -EINVAL;
  644. for (i = 0; i < 64; i++)
  645. csum = csum + efuse[i];
  646. while (csum > 255)
  647. csum = (csum & 0x00FF) + ((csum >> 8) & 0x00FF);
  648. if (csum != 0xFF)
  649. return -EINVAL;
  650. *ledmode = (efuse[51] << 8) | efuse[52];
  651. return 0;
  652. }
  653. static int ax88179_convert_old_led(struct usbnet *dev, u16 *ledvalue)
  654. {
  655. u16 led;
  656. /* Loaded the old eFuse LED Mode */
  657. if (ax88179_read_cmd(dev, AX_ACCESS_EEPROM, 0x3C, 1, 2, &led) < 0)
  658. return -EINVAL;
  659. led >>= 8;
  660. switch (led) {
  661. case 0xFF:
  662. led = LED0_ACTIVE | LED1_LINK_10 | LED1_LINK_100 |
  663. LED1_LINK_1000 | LED2_ACTIVE | LED2_LINK_10 |
  664. LED2_LINK_100 | LED2_LINK_1000 | LED_VALID;
  665. break;
  666. case 0xFE:
  667. led = LED0_ACTIVE | LED1_LINK_1000 | LED2_LINK_100 | LED_VALID;
  668. break;
  669. case 0xFD:
  670. led = LED0_ACTIVE | LED1_LINK_1000 | LED2_LINK_100 |
  671. LED2_LINK_10 | LED_VALID;
  672. break;
  673. case 0xFC:
  674. led = LED0_ACTIVE | LED1_ACTIVE | LED1_LINK_1000 | LED2_ACTIVE |
  675. LED2_LINK_100 | LED2_LINK_10 | LED_VALID;
  676. break;
  677. default:
  678. led = LED0_ACTIVE | LED1_LINK_10 | LED1_LINK_100 |
  679. LED1_LINK_1000 | LED2_ACTIVE | LED2_LINK_10 |
  680. LED2_LINK_100 | LED2_LINK_1000 | LED_VALID;
  681. break;
  682. }
  683. *ledvalue = led;
  684. return 0;
  685. }
  686. static int ax88179_led_setting(struct usbnet *dev)
  687. {
  688. u8 ledfd, value = 0;
  689. u16 tmp, ledact, ledlink, ledvalue = 0, delay = HZ / 10;
  690. unsigned long jtimeout;
  691. /* Check AX88179 version. UA1 or UA2*/
  692. ax88179_read_cmd(dev, AX_ACCESS_MAC, GENERAL_STATUS, 1, 1, &value);
  693. if (!(value & AX_SECLD)) { /* UA1 */
  694. value = AX_GPIO_CTRL_GPIO3EN | AX_GPIO_CTRL_GPIO2EN |
  695. AX_GPIO_CTRL_GPIO1EN;
  696. if (ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_GPIO_CTRL,
  697. 1, 1, &value) < 0)
  698. return -EINVAL;
  699. }
  700. /* Check EEPROM */
  701. if (!ax88179_check_eeprom(dev)) {
  702. value = 0x42;
  703. if (ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_SROM_ADDR,
  704. 1, 1, &value) < 0)
  705. return -EINVAL;
  706. value = EEP_RD;
  707. if (ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_SROM_CMD,
  708. 1, 1, &value) < 0)
  709. return -EINVAL;
  710. jtimeout = jiffies + delay;
  711. do {
  712. ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_SROM_CMD,
  713. 1, 1, &value);
  714. if (time_after(jiffies, jtimeout))
  715. return -EINVAL;
  716. } while (value & EEP_BUSY);
  717. ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_SROM_DATA_HIGH,
  718. 1, 1, &value);
  719. ledvalue = (value << 8);
  720. ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_SROM_DATA_LOW,
  721. 1, 1, &value);
  722. ledvalue |= value;
  723. /* load internal ROM for defaule setting */
  724. if ((ledvalue == 0xFFFF) || ((ledvalue & LED_VALID) == 0))
  725. ax88179_convert_old_led(dev, &ledvalue);
  726. } else if (!ax88179_check_efuse(dev, &ledvalue)) {
  727. if ((ledvalue == 0xFFFF) || ((ledvalue & LED_VALID) == 0))
  728. ax88179_convert_old_led(dev, &ledvalue);
  729. } else {
  730. ax88179_convert_old_led(dev, &ledvalue);
  731. }
  732. tmp = GMII_PHY_PGSEL_EXT;
  733. ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID,
  734. GMII_PHY_PAGE_SELECT, 2, &tmp);
  735. tmp = 0x2c;
  736. ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID,
  737. GMII_PHYPAGE, 2, &tmp);
  738. ax88179_read_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID,
  739. GMII_LED_ACT, 2, &ledact);
  740. ax88179_read_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID,
  741. GMII_LED_LINK, 2, &ledlink);
  742. ledact &= GMII_LED_ACTIVE_MASK;
  743. ledlink &= GMII_LED_LINK_MASK;
  744. if (ledvalue & LED0_ACTIVE)
  745. ledact |= GMII_LED0_ACTIVE;
  746. if (ledvalue & LED1_ACTIVE)
  747. ledact |= GMII_LED1_ACTIVE;
  748. if (ledvalue & LED2_ACTIVE)
  749. ledact |= GMII_LED2_ACTIVE;
  750. if (ledvalue & LED0_LINK_10)
  751. ledlink |= GMII_LED0_LINK_10;
  752. if (ledvalue & LED1_LINK_10)
  753. ledlink |= GMII_LED1_LINK_10;
  754. if (ledvalue & LED2_LINK_10)
  755. ledlink |= GMII_LED2_LINK_10;
  756. if (ledvalue & LED0_LINK_100)
  757. ledlink |= GMII_LED0_LINK_100;
  758. if (ledvalue & LED1_LINK_100)
  759. ledlink |= GMII_LED1_LINK_100;
  760. if (ledvalue & LED2_LINK_100)
  761. ledlink |= GMII_LED2_LINK_100;
  762. if (ledvalue & LED0_LINK_1000)
  763. ledlink |= GMII_LED0_LINK_1000;
  764. if (ledvalue & LED1_LINK_1000)
  765. ledlink |= GMII_LED1_LINK_1000;
  766. if (ledvalue & LED2_LINK_1000)
  767. ledlink |= GMII_LED2_LINK_1000;
  768. tmp = ledact;
  769. ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID,
  770. GMII_LED_ACT, 2, &tmp);
  771. tmp = ledlink;
  772. ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID,
  773. GMII_LED_LINK, 2, &tmp);
  774. tmp = GMII_PHY_PGSEL_PAGE0;
  775. ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID,
  776. GMII_PHY_PAGE_SELECT, 2, &tmp);
  777. /* LED full duplex setting */
  778. ledfd = 0;
  779. if (ledvalue & LED0_FD)
  780. ledfd |= 0x01;
  781. else if ((ledvalue & LED0_USB3_MASK) == 0)
  782. ledfd |= 0x02;
  783. if (ledvalue & LED1_FD)
  784. ledfd |= 0x04;
  785. else if ((ledvalue & LED1_USB3_MASK) == 0)
  786. ledfd |= 0x08;
  787. if (ledvalue & LED2_FD)
  788. ledfd |= 0x10;
  789. else if ((ledvalue & LED2_USB3_MASK) == 0)
  790. ledfd |= 0x20;
  791. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_LEDCTRL, 1, 1, &ledfd);
  792. return 0;
  793. }
  794. static int ax88179_bind(struct usbnet *dev, struct usb_interface *intf)
  795. {
  796. u8 buf[5];
  797. u16 *tmp16;
  798. u8 *tmp;
  799. struct ax88179_data *ax179_data = (struct ax88179_data *)dev->data;
  800. usbnet_get_endpoints(dev, intf);
  801. tmp16 = (u16 *)buf;
  802. tmp = (u8 *)buf;
  803. memset(ax179_data, 0, sizeof(*ax179_data));
  804. /* Power up ethernet PHY */
  805. *tmp16 = 0;
  806. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 2, 2, tmp16);
  807. *tmp16 = AX_PHYPWR_RSTCTL_IPRL;
  808. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 2, 2, tmp16);
  809. msleep(200);
  810. *tmp = AX_CLK_SELECT_ACS | AX_CLK_SELECT_BCS;
  811. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_CLK_SELECT, 1, 1, tmp);
  812. msleep(100);
  813. ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_NODE_ID, ETH_ALEN,
  814. ETH_ALEN, dev->net->dev_addr);
  815. memcpy(dev->net->perm_addr, dev->net->dev_addr, ETH_ALEN);
  816. /* RX bulk configuration */
  817. memcpy(tmp, &AX88179_BULKIN_SIZE[0], 5);
  818. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RX_BULKIN_QCTRL, 5, 5, tmp);
  819. dev->rx_urb_size = 1024 * 20;
  820. *tmp = 0x34;
  821. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_PAUSE_WATERLVL_LOW, 1, 1, tmp);
  822. *tmp = 0x52;
  823. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_PAUSE_WATERLVL_HIGH,
  824. 1, 1, tmp);
  825. dev->net->netdev_ops = &ax88179_netdev_ops;
  826. dev->net->ethtool_ops = &ax88179_ethtool_ops;
  827. dev->net->needed_headroom = 8;
  828. /* Initialize MII structure */
  829. dev->mii.dev = dev->net;
  830. dev->mii.mdio_read = ax88179_mdio_read;
  831. dev->mii.mdio_write = ax88179_mdio_write;
  832. dev->mii.phy_id_mask = 0xff;
  833. dev->mii.reg_num_mask = 0xff;
  834. dev->mii.phy_id = 0x03;
  835. dev->mii.supports_gmii = 1;
  836. dev->net->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
  837. NETIF_F_RXCSUM;
  838. dev->net->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
  839. NETIF_F_RXCSUM;
  840. /* Enable checksum offload */
  841. *tmp = AX_RXCOE_IP | AX_RXCOE_TCP | AX_RXCOE_UDP |
  842. AX_RXCOE_TCPV6 | AX_RXCOE_UDPV6;
  843. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RXCOE_CTL, 1, 1, tmp);
  844. *tmp = AX_TXCOE_IP | AX_TXCOE_TCP | AX_TXCOE_UDP |
  845. AX_TXCOE_TCPV6 | AX_TXCOE_UDPV6;
  846. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_TXCOE_CTL, 1, 1, tmp);
  847. /* Configure RX control register => start operation */
  848. *tmp16 = AX_RX_CTL_DROPCRCERR | AX_RX_CTL_IPE | AX_RX_CTL_START |
  849. AX_RX_CTL_AP | AX_RX_CTL_AMALL | AX_RX_CTL_AB;
  850. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RX_CTL, 2, 2, tmp16);
  851. *tmp = AX_MONITOR_MODE_PMETYPE | AX_MONITOR_MODE_PMEPOL |
  852. AX_MONITOR_MODE_RWMP;
  853. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_MONITOR_MOD, 1, 1, tmp);
  854. /* Configure default medium type => giga */
  855. *tmp16 = AX_MEDIUM_RECEIVE_EN | AX_MEDIUM_TXFLOW_CTRLEN |
  856. AX_MEDIUM_RXFLOW_CTRLEN | AX_MEDIUM_ALWAYS_ONE |
  857. AX_MEDIUM_FULL_DUPLEX | AX_MEDIUM_GIGAMODE;
  858. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE,
  859. 2, 2, tmp16);
  860. ax88179_led_setting(dev);
  861. /* Restart autoneg */
  862. mii_nway_restart(&dev->mii);
  863. usbnet_link_change(dev, 0, 0);
  864. return 0;
  865. }
  866. static void ax88179_unbind(struct usbnet *dev, struct usb_interface *intf)
  867. {
  868. u16 tmp16;
  869. /* Configure RX control register => stop operation */
  870. tmp16 = AX_RX_CTL_STOP;
  871. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RX_CTL, 2, 2, &tmp16);
  872. tmp16 = 0;
  873. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_CLK_SELECT, 1, 1, &tmp16);
  874. /* Power down ethernet PHY */
  875. tmp16 = 0;
  876. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 2, 2, &tmp16);
  877. }
  878. static void
  879. ax88179_rx_checksum(struct sk_buff *skb, u32 *pkt_hdr)
  880. {
  881. skb->ip_summed = CHECKSUM_NONE;
  882. /* checksum error bit is set */
  883. if ((*pkt_hdr & AX_RXHDR_L3CSUM_ERR) ||
  884. (*pkt_hdr & AX_RXHDR_L4CSUM_ERR))
  885. return;
  886. /* It must be a TCP or UDP packet with a valid checksum */
  887. if (((*pkt_hdr & AX_RXHDR_L4_TYPE_MASK) == AX_RXHDR_L4_TYPE_TCP) ||
  888. ((*pkt_hdr & AX_RXHDR_L4_TYPE_MASK) == AX_RXHDR_L4_TYPE_UDP))
  889. skb->ip_summed = CHECKSUM_UNNECESSARY;
  890. }
  891. static int ax88179_rx_fixup(struct usbnet *dev, struct sk_buff *skb)
  892. {
  893. struct sk_buff *ax_skb;
  894. int pkt_cnt;
  895. u32 rx_hdr;
  896. u16 hdr_off;
  897. u32 *pkt_hdr;
  898. skb_trim(skb, skb->len - 4);
  899. memcpy(&rx_hdr, skb_tail_pointer(skb), 4);
  900. le32_to_cpus(&rx_hdr);
  901. pkt_cnt = (u16)rx_hdr;
  902. hdr_off = (u16)(rx_hdr >> 16);
  903. pkt_hdr = (u32 *)(skb->data + hdr_off);
  904. while (pkt_cnt--) {
  905. u16 pkt_len;
  906. le32_to_cpus(pkt_hdr);
  907. pkt_len = (*pkt_hdr >> 16) & 0x1fff;
  908. /* Check CRC or runt packet */
  909. if ((*pkt_hdr & AX_RXHDR_CRC_ERR) ||
  910. (*pkt_hdr & AX_RXHDR_DROP_ERR)) {
  911. skb_pull(skb, (pkt_len + 7) & 0xFFF8);
  912. pkt_hdr++;
  913. continue;
  914. }
  915. if (pkt_cnt == 0) {
  916. /* Skip IP alignment psudo header */
  917. skb_pull(skb, 2);
  918. skb->len = pkt_len;
  919. skb_set_tail_pointer(skb, pkt_len);
  920. skb->truesize = pkt_len + sizeof(struct sk_buff);
  921. ax88179_rx_checksum(skb, pkt_hdr);
  922. return 1;
  923. }
  924. ax_skb = skb_clone(skb, GFP_ATOMIC);
  925. if (ax_skb) {
  926. ax_skb->len = pkt_len;
  927. ax_skb->data = skb->data + 2;
  928. skb_set_tail_pointer(ax_skb, pkt_len);
  929. ax_skb->truesize = pkt_len + sizeof(struct sk_buff);
  930. ax88179_rx_checksum(ax_skb, pkt_hdr);
  931. usbnet_skb_return(dev, ax_skb);
  932. } else {
  933. return 0;
  934. }
  935. skb_pull(skb, (pkt_len + 7) & 0xFFF8);
  936. pkt_hdr++;
  937. }
  938. return 1;
  939. }
  940. static struct sk_buff *
  941. ax88179_tx_fixup(struct usbnet *dev, struct sk_buff *skb, gfp_t flags)
  942. {
  943. u32 tx_hdr1, tx_hdr2;
  944. int frame_size = dev->maxpacket;
  945. int mss = skb_shinfo(skb)->gso_size;
  946. int headroom;
  947. tx_hdr1 = skb->len;
  948. tx_hdr2 = mss;
  949. if (((skb->len + 8) % frame_size) == 0)
  950. tx_hdr2 |= 0x80008000; /* Enable padding */
  951. headroom = skb_headroom(skb) - 8;
  952. if ((skb_header_cloned(skb) || headroom < 0) &&
  953. pskb_expand_head(skb, headroom < 0 ? 8 : 0, 0, GFP_ATOMIC)) {
  954. dev_kfree_skb_any(skb);
  955. return NULL;
  956. }
  957. skb_push(skb, 4);
  958. cpu_to_le32s(&tx_hdr2);
  959. skb_copy_to_linear_data(skb, &tx_hdr2, 4);
  960. skb_push(skb, 4);
  961. cpu_to_le32s(&tx_hdr1);
  962. skb_copy_to_linear_data(skb, &tx_hdr1, 4);
  963. return skb;
  964. }
  965. static int ax88179_link_reset(struct usbnet *dev)
  966. {
  967. struct ax88179_data *ax179_data = (struct ax88179_data *)dev->data;
  968. u8 tmp[5], link_sts;
  969. u16 mode, tmp16, delay = HZ / 10;
  970. u32 tmp32 = 0x40000000;
  971. unsigned long jtimeout;
  972. jtimeout = jiffies + delay;
  973. while (tmp32 & 0x40000000) {
  974. mode = 0;
  975. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RX_CTL, 2, 2, &mode);
  976. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RX_CTL, 2, 2,
  977. &ax179_data->rxctl);
  978. /*link up, check the usb device control TX FIFO full or empty*/
  979. ax88179_read_cmd(dev, 0x81, 0x8c, 0, 4, &tmp32);
  980. if (time_after(jiffies, jtimeout))
  981. return 0;
  982. }
  983. mode = AX_MEDIUM_RECEIVE_EN | AX_MEDIUM_TXFLOW_CTRLEN |
  984. AX_MEDIUM_RXFLOW_CTRLEN | AX_MEDIUM_ALWAYS_ONE;
  985. ax88179_read_cmd(dev, AX_ACCESS_MAC, PHYSICAL_LINK_STATUS,
  986. 1, 1, &link_sts);
  987. ax88179_read_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID,
  988. GMII_PHY_PHYSR, 2, &tmp16);
  989. if (!(tmp16 & GMII_PHY_PHYSR_LINK)) {
  990. return 0;
  991. } else if (GMII_PHY_PHYSR_GIGA == (tmp16 & GMII_PHY_PHYSR_SMASK)) {
  992. mode |= AX_MEDIUM_GIGAMODE | AX_MEDIUM_EN_125MHZ;
  993. if (dev->net->mtu > 1500)
  994. mode |= AX_MEDIUM_JUMBO_EN;
  995. if (link_sts & AX_USB_SS)
  996. memcpy(tmp, &AX88179_BULKIN_SIZE[0], 5);
  997. else if (link_sts & AX_USB_HS)
  998. memcpy(tmp, &AX88179_BULKIN_SIZE[1], 5);
  999. else
  1000. memcpy(tmp, &AX88179_BULKIN_SIZE[3], 5);
  1001. } else if (GMII_PHY_PHYSR_100 == (tmp16 & GMII_PHY_PHYSR_SMASK)) {
  1002. mode |= AX_MEDIUM_PS;
  1003. if (link_sts & (AX_USB_SS | AX_USB_HS))
  1004. memcpy(tmp, &AX88179_BULKIN_SIZE[2], 5);
  1005. else
  1006. memcpy(tmp, &AX88179_BULKIN_SIZE[3], 5);
  1007. } else {
  1008. memcpy(tmp, &AX88179_BULKIN_SIZE[3], 5);
  1009. }
  1010. /* RX bulk configuration */
  1011. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RX_BULKIN_QCTRL, 5, 5, tmp);
  1012. dev->rx_urb_size = (1024 * (tmp[3] + 2));
  1013. if (tmp16 & GMII_PHY_PHYSR_FULL)
  1014. mode |= AX_MEDIUM_FULL_DUPLEX;
  1015. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE,
  1016. 2, 2, &mode);
  1017. netif_carrier_on(dev->net);
  1018. return 0;
  1019. }
  1020. static int ax88179_reset(struct usbnet *dev)
  1021. {
  1022. u8 buf[5];
  1023. u16 *tmp16;
  1024. u8 *tmp;
  1025. tmp16 = (u16 *)buf;
  1026. tmp = (u8 *)buf;
  1027. /* Power up ethernet PHY */
  1028. *tmp16 = 0;
  1029. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 2, 2, tmp16);
  1030. *tmp16 = AX_PHYPWR_RSTCTL_IPRL;
  1031. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 2, 2, tmp16);
  1032. msleep(200);
  1033. *tmp = AX_CLK_SELECT_ACS | AX_CLK_SELECT_BCS;
  1034. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_CLK_SELECT, 1, 1, tmp);
  1035. msleep(100);
  1036. /* Ethernet PHY Auto Detach*/
  1037. ax88179_auto_detach(dev, 0);
  1038. ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_NODE_ID, ETH_ALEN, ETH_ALEN,
  1039. dev->net->dev_addr);
  1040. memcpy(dev->net->perm_addr, dev->net->dev_addr, ETH_ALEN);
  1041. /* RX bulk configuration */
  1042. memcpy(tmp, &AX88179_BULKIN_SIZE[0], 5);
  1043. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RX_BULKIN_QCTRL, 5, 5, tmp);
  1044. dev->rx_urb_size = 1024 * 20;
  1045. *tmp = 0x34;
  1046. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_PAUSE_WATERLVL_LOW, 1, 1, tmp);
  1047. *tmp = 0x52;
  1048. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_PAUSE_WATERLVL_HIGH,
  1049. 1, 1, tmp);
  1050. dev->net->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
  1051. NETIF_F_RXCSUM;
  1052. dev->net->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
  1053. NETIF_F_RXCSUM;
  1054. /* Enable checksum offload */
  1055. *tmp = AX_RXCOE_IP | AX_RXCOE_TCP | AX_RXCOE_UDP |
  1056. AX_RXCOE_TCPV6 | AX_RXCOE_UDPV6;
  1057. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RXCOE_CTL, 1, 1, tmp);
  1058. *tmp = AX_TXCOE_IP | AX_TXCOE_TCP | AX_TXCOE_UDP |
  1059. AX_TXCOE_TCPV6 | AX_TXCOE_UDPV6;
  1060. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_TXCOE_CTL, 1, 1, tmp);
  1061. /* Configure RX control register => start operation */
  1062. *tmp16 = AX_RX_CTL_DROPCRCERR | AX_RX_CTL_IPE | AX_RX_CTL_START |
  1063. AX_RX_CTL_AP | AX_RX_CTL_AMALL | AX_RX_CTL_AB;
  1064. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RX_CTL, 2, 2, tmp16);
  1065. *tmp = AX_MONITOR_MODE_PMETYPE | AX_MONITOR_MODE_PMEPOL |
  1066. AX_MONITOR_MODE_RWMP;
  1067. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_MONITOR_MOD, 1, 1, tmp);
  1068. /* Configure default medium type => giga */
  1069. *tmp16 = AX_MEDIUM_RECEIVE_EN | AX_MEDIUM_TXFLOW_CTRLEN |
  1070. AX_MEDIUM_RXFLOW_CTRLEN | AX_MEDIUM_ALWAYS_ONE |
  1071. AX_MEDIUM_FULL_DUPLEX | AX_MEDIUM_GIGAMODE;
  1072. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE,
  1073. 2, 2, tmp16);
  1074. ax88179_led_setting(dev);
  1075. /* Restart autoneg */
  1076. mii_nway_restart(&dev->mii);
  1077. usbnet_link_change(dev, 0, 0);
  1078. return 0;
  1079. }
  1080. static int ax88179_stop(struct usbnet *dev)
  1081. {
  1082. u16 tmp16;
  1083. ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE,
  1084. 2, 2, &tmp16);
  1085. tmp16 &= ~AX_MEDIUM_RECEIVE_EN;
  1086. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE,
  1087. 2, 2, &tmp16);
  1088. return 0;
  1089. }
  1090. static const struct driver_info ax88179_info = {
  1091. .description = "ASIX AX88179 USB 3.0 Gigabit Ethernet",
  1092. .bind = ax88179_bind,
  1093. .unbind = ax88179_unbind,
  1094. .status = ax88179_status,
  1095. .link_reset = ax88179_link_reset,
  1096. .reset = ax88179_reset,
  1097. .stop = ax88179_stop,
  1098. .flags = FLAG_ETHER | FLAG_FRAMING_AX,
  1099. .rx_fixup = ax88179_rx_fixup,
  1100. .tx_fixup = ax88179_tx_fixup,
  1101. };
  1102. static const struct driver_info ax88178a_info = {
  1103. .description = "ASIX AX88178A USB 2.0 Gigabit Ethernet",
  1104. .bind = ax88179_bind,
  1105. .unbind = ax88179_unbind,
  1106. .status = ax88179_status,
  1107. .link_reset = ax88179_link_reset,
  1108. .reset = ax88179_reset,
  1109. .stop = ax88179_stop,
  1110. .flags = FLAG_ETHER | FLAG_FRAMING_AX,
  1111. .rx_fixup = ax88179_rx_fixup,
  1112. .tx_fixup = ax88179_tx_fixup,
  1113. };
  1114. static const struct driver_info sitecom_info = {
  1115. .description = "Sitecom USB 3.0 to Gigabit Adapter",
  1116. .bind = ax88179_bind,
  1117. .unbind = ax88179_unbind,
  1118. .status = ax88179_status,
  1119. .link_reset = ax88179_link_reset,
  1120. .reset = ax88179_reset,
  1121. .stop = ax88179_stop,
  1122. .flags = FLAG_ETHER | FLAG_FRAMING_AX,
  1123. .rx_fixup = ax88179_rx_fixup,
  1124. .tx_fixup = ax88179_tx_fixup,
  1125. };
  1126. static const struct usb_device_id products[] = {
  1127. {
  1128. /* ASIX AX88179 10/100/1000 */
  1129. USB_DEVICE(0x0b95, 0x1790),
  1130. .driver_info = (unsigned long)&ax88179_info,
  1131. }, {
  1132. /* ASIX AX88178A 10/100/1000 */
  1133. USB_DEVICE(0x0b95, 0x178a),
  1134. .driver_info = (unsigned long)&ax88178a_info,
  1135. }, {
  1136. /* Sitecom USB 3.0 to Gigabit Adapter */
  1137. USB_DEVICE(0x0df6, 0x0072),
  1138. .driver_info = (unsigned long) &sitecom_info,
  1139. },
  1140. { },
  1141. };
  1142. MODULE_DEVICE_TABLE(usb, products);
  1143. static struct usb_driver ax88179_178a_driver = {
  1144. .name = "ax88179_178a",
  1145. .id_table = products,
  1146. .probe = usbnet_probe,
  1147. .suspend = ax88179_suspend,
  1148. .resume = ax88179_resume,
  1149. .reset_resume = ax88179_resume,
  1150. .disconnect = usbnet_disconnect,
  1151. .supports_autosuspend = 1,
  1152. .disable_hub_initiated_lpm = 1,
  1153. };
  1154. module_usb_driver(ax88179_178a_driver);
  1155. MODULE_DESCRIPTION("ASIX AX88179/178A based USB 3.0/2.0 Gigabit Ethernet Devices");
  1156. MODULE_LICENSE("GPL");