tg3.c 458 KB

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  1. /*
  2. * tg3.c: Broadcom Tigon3 ethernet driver.
  3. *
  4. * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
  5. * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
  6. * Copyright (C) 2004 Sun Microsystems Inc.
  7. * Copyright (C) 2005-2013 Broadcom Corporation.
  8. *
  9. * Firmware is:
  10. * Derived from proprietary unpublished source code,
  11. * Copyright (C) 2000-2003 Broadcom Corporation.
  12. *
  13. * Permission is hereby granted for the distribution of this firmware
  14. * data in hexadecimal or equivalent format, provided this copyright
  15. * notice is accompanying it.
  16. */
  17. #include <linux/module.h>
  18. #include <linux/moduleparam.h>
  19. #include <linux/stringify.h>
  20. #include <linux/kernel.h>
  21. #include <linux/types.h>
  22. #include <linux/compiler.h>
  23. #include <linux/slab.h>
  24. #include <linux/delay.h>
  25. #include <linux/in.h>
  26. #include <linux/init.h>
  27. #include <linux/interrupt.h>
  28. #include <linux/ioport.h>
  29. #include <linux/pci.h>
  30. #include <linux/netdevice.h>
  31. #include <linux/etherdevice.h>
  32. #include <linux/skbuff.h>
  33. #include <linux/ethtool.h>
  34. #include <linux/mdio.h>
  35. #include <linux/mii.h>
  36. #include <linux/phy.h>
  37. #include <linux/brcmphy.h>
  38. #include <linux/if_vlan.h>
  39. #include <linux/ip.h>
  40. #include <linux/tcp.h>
  41. #include <linux/workqueue.h>
  42. #include <linux/prefetch.h>
  43. #include <linux/dma-mapping.h>
  44. #include <linux/firmware.h>
  45. #include <linux/ssb/ssb_driver_gige.h>
  46. #include <linux/hwmon.h>
  47. #include <linux/hwmon-sysfs.h>
  48. #include <net/checksum.h>
  49. #include <net/ip.h>
  50. #include <linux/io.h>
  51. #include <asm/byteorder.h>
  52. #include <linux/uaccess.h>
  53. #include <uapi/linux/net_tstamp.h>
  54. #include <linux/ptp_clock_kernel.h>
  55. #ifdef CONFIG_SPARC
  56. #include <asm/idprom.h>
  57. #include <asm/prom.h>
  58. #endif
  59. #define BAR_0 0
  60. #define BAR_2 2
  61. #include "tg3.h"
  62. /* Functions & macros to verify TG3_FLAGS types */
  63. static inline int _tg3_flag(enum TG3_FLAGS flag, unsigned long *bits)
  64. {
  65. return test_bit(flag, bits);
  66. }
  67. static inline void _tg3_flag_set(enum TG3_FLAGS flag, unsigned long *bits)
  68. {
  69. set_bit(flag, bits);
  70. }
  71. static inline void _tg3_flag_clear(enum TG3_FLAGS flag, unsigned long *bits)
  72. {
  73. clear_bit(flag, bits);
  74. }
  75. #define tg3_flag(tp, flag) \
  76. _tg3_flag(TG3_FLAG_##flag, (tp)->tg3_flags)
  77. #define tg3_flag_set(tp, flag) \
  78. _tg3_flag_set(TG3_FLAG_##flag, (tp)->tg3_flags)
  79. #define tg3_flag_clear(tp, flag) \
  80. _tg3_flag_clear(TG3_FLAG_##flag, (tp)->tg3_flags)
  81. #define DRV_MODULE_NAME "tg3"
  82. #define TG3_MAJ_NUM 3
  83. #define TG3_MIN_NUM 133
  84. #define DRV_MODULE_VERSION \
  85. __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
  86. #define DRV_MODULE_RELDATE "Jul 29, 2013"
  87. #define RESET_KIND_SHUTDOWN 0
  88. #define RESET_KIND_INIT 1
  89. #define RESET_KIND_SUSPEND 2
  90. #define TG3_DEF_RX_MODE 0
  91. #define TG3_DEF_TX_MODE 0
  92. #define TG3_DEF_MSG_ENABLE \
  93. (NETIF_MSG_DRV | \
  94. NETIF_MSG_PROBE | \
  95. NETIF_MSG_LINK | \
  96. NETIF_MSG_TIMER | \
  97. NETIF_MSG_IFDOWN | \
  98. NETIF_MSG_IFUP | \
  99. NETIF_MSG_RX_ERR | \
  100. NETIF_MSG_TX_ERR)
  101. #define TG3_GRC_LCLCTL_PWRSW_DELAY 100
  102. /* length of time before we decide the hardware is borked,
  103. * and dev->tx_timeout() should be called to fix the problem
  104. */
  105. #define TG3_TX_TIMEOUT (5 * HZ)
  106. /* hardware minimum and maximum for a single frame's data payload */
  107. #define TG3_MIN_MTU 60
  108. #define TG3_MAX_MTU(tp) \
  109. (tg3_flag(tp, JUMBO_CAPABLE) ? 9000 : 1500)
  110. /* These numbers seem to be hard coded in the NIC firmware somehow.
  111. * You can't change the ring sizes, but you can change where you place
  112. * them in the NIC onboard memory.
  113. */
  114. #define TG3_RX_STD_RING_SIZE(tp) \
  115. (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
  116. TG3_RX_STD_MAX_SIZE_5717 : TG3_RX_STD_MAX_SIZE_5700)
  117. #define TG3_DEF_RX_RING_PENDING 200
  118. #define TG3_RX_JMB_RING_SIZE(tp) \
  119. (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
  120. TG3_RX_JMB_MAX_SIZE_5717 : TG3_RX_JMB_MAX_SIZE_5700)
  121. #define TG3_DEF_RX_JUMBO_RING_PENDING 100
  122. /* Do not place this n-ring entries value into the tp struct itself,
  123. * we really want to expose these constants to GCC so that modulo et
  124. * al. operations are done with shifts and masks instead of with
  125. * hw multiply/modulo instructions. Another solution would be to
  126. * replace things like '% foo' with '& (foo - 1)'.
  127. */
  128. #define TG3_TX_RING_SIZE 512
  129. #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
  130. #define TG3_RX_STD_RING_BYTES(tp) \
  131. (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp))
  132. #define TG3_RX_JMB_RING_BYTES(tp) \
  133. (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp))
  134. #define TG3_RX_RCB_RING_BYTES(tp) \
  135. (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
  136. #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
  137. TG3_TX_RING_SIZE)
  138. #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
  139. #define TG3_DMA_BYTE_ENAB 64
  140. #define TG3_RX_STD_DMA_SZ 1536
  141. #define TG3_RX_JMB_DMA_SZ 9046
  142. #define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
  143. #define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
  144. #define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
  145. #define TG3_RX_STD_BUFF_RING_SIZE(tp) \
  146. (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp))
  147. #define TG3_RX_JMB_BUFF_RING_SIZE(tp) \
  148. (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp))
  149. /* Due to a hardware bug, the 5701 can only DMA to memory addresses
  150. * that are at least dword aligned when used in PCIX mode. The driver
  151. * works around this bug by double copying the packet. This workaround
  152. * is built into the normal double copy length check for efficiency.
  153. *
  154. * However, the double copy is only necessary on those architectures
  155. * where unaligned memory accesses are inefficient. For those architectures
  156. * where unaligned memory accesses incur little penalty, we can reintegrate
  157. * the 5701 in the normal rx path. Doing so saves a device structure
  158. * dereference by hardcoding the double copy threshold in place.
  159. */
  160. #define TG3_RX_COPY_THRESHOLD 256
  161. #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
  162. #define TG3_RX_COPY_THRESH(tp) TG3_RX_COPY_THRESHOLD
  163. #else
  164. #define TG3_RX_COPY_THRESH(tp) ((tp)->rx_copy_thresh)
  165. #endif
  166. #if (NET_IP_ALIGN != 0)
  167. #define TG3_RX_OFFSET(tp) ((tp)->rx_offset)
  168. #else
  169. #define TG3_RX_OFFSET(tp) (NET_SKB_PAD)
  170. #endif
  171. /* minimum number of free TX descriptors required to wake up TX process */
  172. #define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
  173. #define TG3_TX_BD_DMA_MAX_2K 2048
  174. #define TG3_TX_BD_DMA_MAX_4K 4096
  175. #define TG3_RAW_IP_ALIGN 2
  176. #define TG3_FW_UPDATE_TIMEOUT_SEC 5
  177. #define TG3_FW_UPDATE_FREQ_SEC (TG3_FW_UPDATE_TIMEOUT_SEC / 2)
  178. #define FIRMWARE_TG3 "tigon/tg3.bin"
  179. #define FIRMWARE_TG357766 "tigon/tg357766.bin"
  180. #define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
  181. #define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
  182. static char version[] =
  183. DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
  184. MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
  185. MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
  186. MODULE_LICENSE("GPL");
  187. MODULE_VERSION(DRV_MODULE_VERSION);
  188. MODULE_FIRMWARE(FIRMWARE_TG3);
  189. MODULE_FIRMWARE(FIRMWARE_TG3TSO);
  190. MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
  191. static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
  192. module_param(tg3_debug, int, 0);
  193. MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
  194. #define TG3_DRV_DATA_FLAG_10_100_ONLY 0x0001
  195. #define TG3_DRV_DATA_FLAG_5705_10_100 0x0002
  196. static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
  197. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
  198. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
  199. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
  200. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
  201. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
  202. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
  203. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
  204. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
  205. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
  206. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
  207. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
  208. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
  209. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
  210. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
  211. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
  212. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
  213. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
  214. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
  215. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901),
  216. .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
  217. TG3_DRV_DATA_FLAG_5705_10_100},
  218. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2),
  219. .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
  220. TG3_DRV_DATA_FLAG_5705_10_100},
  221. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
  222. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F),
  223. .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
  224. TG3_DRV_DATA_FLAG_5705_10_100},
  225. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
  226. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
  227. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
  228. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
  229. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
  230. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F),
  231. .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
  232. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
  233. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
  234. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
  235. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
  236. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F),
  237. .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
  238. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
  239. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
  240. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
  241. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
  242. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
  243. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
  244. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
  245. {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5787M,
  246. PCI_VENDOR_ID_LENOVO,
  247. TG3PCI_SUBDEVICE_ID_LENOVO_5787M),
  248. .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
  249. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
  250. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F),
  251. .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
  252. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
  253. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
  254. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
  255. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
  256. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
  257. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
  258. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
  259. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
  260. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
  261. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
  262. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
  263. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
  264. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
  265. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
  266. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
  267. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
  268. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
  269. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
  270. {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780,
  271. PCI_VENDOR_ID_AI, TG3PCI_SUBDEVICE_ID_ACER_57780_A),
  272. .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
  273. {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780,
  274. PCI_VENDOR_ID_AI, TG3PCI_SUBDEVICE_ID_ACER_57780_B),
  275. .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
  276. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
  277. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
  278. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790),
  279. .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
  280. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
  281. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
  282. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717_C)},
  283. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
  284. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
  285. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
  286. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
  287. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
  288. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791),
  289. .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
  290. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795),
  291. .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
  292. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
  293. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5720)},
  294. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57762)},
  295. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57766)},
  296. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5762)},
  297. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5725)},
  298. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5727)},
  299. {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
  300. {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
  301. {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
  302. {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
  303. {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
  304. {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
  305. {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
  306. {PCI_DEVICE(0x10cf, 0x11a2)}, /* Fujitsu 1000base-SX with BCM5703SKHB */
  307. {}
  308. };
  309. MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
  310. static const struct {
  311. const char string[ETH_GSTRING_LEN];
  312. } ethtool_stats_keys[] = {
  313. { "rx_octets" },
  314. { "rx_fragments" },
  315. { "rx_ucast_packets" },
  316. { "rx_mcast_packets" },
  317. { "rx_bcast_packets" },
  318. { "rx_fcs_errors" },
  319. { "rx_align_errors" },
  320. { "rx_xon_pause_rcvd" },
  321. { "rx_xoff_pause_rcvd" },
  322. { "rx_mac_ctrl_rcvd" },
  323. { "rx_xoff_entered" },
  324. { "rx_frame_too_long_errors" },
  325. { "rx_jabbers" },
  326. { "rx_undersize_packets" },
  327. { "rx_in_length_errors" },
  328. { "rx_out_length_errors" },
  329. { "rx_64_or_less_octet_packets" },
  330. { "rx_65_to_127_octet_packets" },
  331. { "rx_128_to_255_octet_packets" },
  332. { "rx_256_to_511_octet_packets" },
  333. { "rx_512_to_1023_octet_packets" },
  334. { "rx_1024_to_1522_octet_packets" },
  335. { "rx_1523_to_2047_octet_packets" },
  336. { "rx_2048_to_4095_octet_packets" },
  337. { "rx_4096_to_8191_octet_packets" },
  338. { "rx_8192_to_9022_octet_packets" },
  339. { "tx_octets" },
  340. { "tx_collisions" },
  341. { "tx_xon_sent" },
  342. { "tx_xoff_sent" },
  343. { "tx_flow_control" },
  344. { "tx_mac_errors" },
  345. { "tx_single_collisions" },
  346. { "tx_mult_collisions" },
  347. { "tx_deferred" },
  348. { "tx_excessive_collisions" },
  349. { "tx_late_collisions" },
  350. { "tx_collide_2times" },
  351. { "tx_collide_3times" },
  352. { "tx_collide_4times" },
  353. { "tx_collide_5times" },
  354. { "tx_collide_6times" },
  355. { "tx_collide_7times" },
  356. { "tx_collide_8times" },
  357. { "tx_collide_9times" },
  358. { "tx_collide_10times" },
  359. { "tx_collide_11times" },
  360. { "tx_collide_12times" },
  361. { "tx_collide_13times" },
  362. { "tx_collide_14times" },
  363. { "tx_collide_15times" },
  364. { "tx_ucast_packets" },
  365. { "tx_mcast_packets" },
  366. { "tx_bcast_packets" },
  367. { "tx_carrier_sense_errors" },
  368. { "tx_discards" },
  369. { "tx_errors" },
  370. { "dma_writeq_full" },
  371. { "dma_write_prioq_full" },
  372. { "rxbds_empty" },
  373. { "rx_discards" },
  374. { "rx_errors" },
  375. { "rx_threshold_hit" },
  376. { "dma_readq_full" },
  377. { "dma_read_prioq_full" },
  378. { "tx_comp_queue_full" },
  379. { "ring_set_send_prod_index" },
  380. { "ring_status_update" },
  381. { "nic_irqs" },
  382. { "nic_avoided_irqs" },
  383. { "nic_tx_threshold_hit" },
  384. { "mbuf_lwm_thresh_hit" },
  385. };
  386. #define TG3_NUM_STATS ARRAY_SIZE(ethtool_stats_keys)
  387. #define TG3_NVRAM_TEST 0
  388. #define TG3_LINK_TEST 1
  389. #define TG3_REGISTER_TEST 2
  390. #define TG3_MEMORY_TEST 3
  391. #define TG3_MAC_LOOPB_TEST 4
  392. #define TG3_PHY_LOOPB_TEST 5
  393. #define TG3_EXT_LOOPB_TEST 6
  394. #define TG3_INTERRUPT_TEST 7
  395. static const struct {
  396. const char string[ETH_GSTRING_LEN];
  397. } ethtool_test_keys[] = {
  398. [TG3_NVRAM_TEST] = { "nvram test (online) " },
  399. [TG3_LINK_TEST] = { "link test (online) " },
  400. [TG3_REGISTER_TEST] = { "register test (offline)" },
  401. [TG3_MEMORY_TEST] = { "memory test (offline)" },
  402. [TG3_MAC_LOOPB_TEST] = { "mac loopback test (offline)" },
  403. [TG3_PHY_LOOPB_TEST] = { "phy loopback test (offline)" },
  404. [TG3_EXT_LOOPB_TEST] = { "ext loopback test (offline)" },
  405. [TG3_INTERRUPT_TEST] = { "interrupt test (offline)" },
  406. };
  407. #define TG3_NUM_TEST ARRAY_SIZE(ethtool_test_keys)
  408. static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
  409. {
  410. writel(val, tp->regs + off);
  411. }
  412. static u32 tg3_read32(struct tg3 *tp, u32 off)
  413. {
  414. return readl(tp->regs + off);
  415. }
  416. static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
  417. {
  418. writel(val, tp->aperegs + off);
  419. }
  420. static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
  421. {
  422. return readl(tp->aperegs + off);
  423. }
  424. static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
  425. {
  426. unsigned long flags;
  427. spin_lock_irqsave(&tp->indirect_lock, flags);
  428. pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
  429. pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
  430. spin_unlock_irqrestore(&tp->indirect_lock, flags);
  431. }
  432. static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
  433. {
  434. writel(val, tp->regs + off);
  435. readl(tp->regs + off);
  436. }
  437. static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
  438. {
  439. unsigned long flags;
  440. u32 val;
  441. spin_lock_irqsave(&tp->indirect_lock, flags);
  442. pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
  443. pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
  444. spin_unlock_irqrestore(&tp->indirect_lock, flags);
  445. return val;
  446. }
  447. static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
  448. {
  449. unsigned long flags;
  450. if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
  451. pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
  452. TG3_64BIT_REG_LOW, val);
  453. return;
  454. }
  455. if (off == TG3_RX_STD_PROD_IDX_REG) {
  456. pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
  457. TG3_64BIT_REG_LOW, val);
  458. return;
  459. }
  460. spin_lock_irqsave(&tp->indirect_lock, flags);
  461. pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
  462. pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
  463. spin_unlock_irqrestore(&tp->indirect_lock, flags);
  464. /* In indirect mode when disabling interrupts, we also need
  465. * to clear the interrupt bit in the GRC local ctrl register.
  466. */
  467. if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
  468. (val == 0x1)) {
  469. pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
  470. tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
  471. }
  472. }
  473. static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
  474. {
  475. unsigned long flags;
  476. u32 val;
  477. spin_lock_irqsave(&tp->indirect_lock, flags);
  478. pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
  479. pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
  480. spin_unlock_irqrestore(&tp->indirect_lock, flags);
  481. return val;
  482. }
  483. /* usec_wait specifies the wait time in usec when writing to certain registers
  484. * where it is unsafe to read back the register without some delay.
  485. * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
  486. * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
  487. */
  488. static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
  489. {
  490. if (tg3_flag(tp, PCIX_TARGET_HWBUG) || tg3_flag(tp, ICH_WORKAROUND))
  491. /* Non-posted methods */
  492. tp->write32(tp, off, val);
  493. else {
  494. /* Posted method */
  495. tg3_write32(tp, off, val);
  496. if (usec_wait)
  497. udelay(usec_wait);
  498. tp->read32(tp, off);
  499. }
  500. /* Wait again after the read for the posted method to guarantee that
  501. * the wait time is met.
  502. */
  503. if (usec_wait)
  504. udelay(usec_wait);
  505. }
  506. static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
  507. {
  508. tp->write32_mbox(tp, off, val);
  509. if (tg3_flag(tp, FLUSH_POSTED_WRITES) ||
  510. (!tg3_flag(tp, MBOX_WRITE_REORDER) &&
  511. !tg3_flag(tp, ICH_WORKAROUND)))
  512. tp->read32_mbox(tp, off);
  513. }
  514. static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
  515. {
  516. void __iomem *mbox = tp->regs + off;
  517. writel(val, mbox);
  518. if (tg3_flag(tp, TXD_MBOX_HWBUG))
  519. writel(val, mbox);
  520. if (tg3_flag(tp, MBOX_WRITE_REORDER) ||
  521. tg3_flag(tp, FLUSH_POSTED_WRITES))
  522. readl(mbox);
  523. }
  524. static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
  525. {
  526. return readl(tp->regs + off + GRCMBOX_BASE);
  527. }
  528. static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
  529. {
  530. writel(val, tp->regs + off + GRCMBOX_BASE);
  531. }
  532. #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
  533. #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
  534. #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
  535. #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
  536. #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
  537. #define tw32(reg, val) tp->write32(tp, reg, val)
  538. #define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0)
  539. #define tw32_wait_f(reg, val, us) _tw32_flush(tp, (reg), (val), (us))
  540. #define tr32(reg) tp->read32(tp, reg)
  541. static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
  542. {
  543. unsigned long flags;
  544. if (tg3_asic_rev(tp) == ASIC_REV_5906 &&
  545. (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
  546. return;
  547. spin_lock_irqsave(&tp->indirect_lock, flags);
  548. if (tg3_flag(tp, SRAM_USE_CONFIG)) {
  549. pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
  550. pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
  551. /* Always leave this as zero. */
  552. pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
  553. } else {
  554. tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
  555. tw32_f(TG3PCI_MEM_WIN_DATA, val);
  556. /* Always leave this as zero. */
  557. tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
  558. }
  559. spin_unlock_irqrestore(&tp->indirect_lock, flags);
  560. }
  561. static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
  562. {
  563. unsigned long flags;
  564. if (tg3_asic_rev(tp) == ASIC_REV_5906 &&
  565. (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
  566. *val = 0;
  567. return;
  568. }
  569. spin_lock_irqsave(&tp->indirect_lock, flags);
  570. if (tg3_flag(tp, SRAM_USE_CONFIG)) {
  571. pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
  572. pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
  573. /* Always leave this as zero. */
  574. pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
  575. } else {
  576. tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
  577. *val = tr32(TG3PCI_MEM_WIN_DATA);
  578. /* Always leave this as zero. */
  579. tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
  580. }
  581. spin_unlock_irqrestore(&tp->indirect_lock, flags);
  582. }
  583. static void tg3_ape_lock_init(struct tg3 *tp)
  584. {
  585. int i;
  586. u32 regbase, bit;
  587. if (tg3_asic_rev(tp) == ASIC_REV_5761)
  588. regbase = TG3_APE_LOCK_GRANT;
  589. else
  590. regbase = TG3_APE_PER_LOCK_GRANT;
  591. /* Make sure the driver hasn't any stale locks. */
  592. for (i = TG3_APE_LOCK_PHY0; i <= TG3_APE_LOCK_GPIO; i++) {
  593. switch (i) {
  594. case TG3_APE_LOCK_PHY0:
  595. case TG3_APE_LOCK_PHY1:
  596. case TG3_APE_LOCK_PHY2:
  597. case TG3_APE_LOCK_PHY3:
  598. bit = APE_LOCK_GRANT_DRIVER;
  599. break;
  600. default:
  601. if (!tp->pci_fn)
  602. bit = APE_LOCK_GRANT_DRIVER;
  603. else
  604. bit = 1 << tp->pci_fn;
  605. }
  606. tg3_ape_write32(tp, regbase + 4 * i, bit);
  607. }
  608. }
  609. static int tg3_ape_lock(struct tg3 *tp, int locknum)
  610. {
  611. int i, off;
  612. int ret = 0;
  613. u32 status, req, gnt, bit;
  614. if (!tg3_flag(tp, ENABLE_APE))
  615. return 0;
  616. switch (locknum) {
  617. case TG3_APE_LOCK_GPIO:
  618. if (tg3_asic_rev(tp) == ASIC_REV_5761)
  619. return 0;
  620. case TG3_APE_LOCK_GRC:
  621. case TG3_APE_LOCK_MEM:
  622. if (!tp->pci_fn)
  623. bit = APE_LOCK_REQ_DRIVER;
  624. else
  625. bit = 1 << tp->pci_fn;
  626. break;
  627. case TG3_APE_LOCK_PHY0:
  628. case TG3_APE_LOCK_PHY1:
  629. case TG3_APE_LOCK_PHY2:
  630. case TG3_APE_LOCK_PHY3:
  631. bit = APE_LOCK_REQ_DRIVER;
  632. break;
  633. default:
  634. return -EINVAL;
  635. }
  636. if (tg3_asic_rev(tp) == ASIC_REV_5761) {
  637. req = TG3_APE_LOCK_REQ;
  638. gnt = TG3_APE_LOCK_GRANT;
  639. } else {
  640. req = TG3_APE_PER_LOCK_REQ;
  641. gnt = TG3_APE_PER_LOCK_GRANT;
  642. }
  643. off = 4 * locknum;
  644. tg3_ape_write32(tp, req + off, bit);
  645. /* Wait for up to 1 millisecond to acquire lock. */
  646. for (i = 0; i < 100; i++) {
  647. status = tg3_ape_read32(tp, gnt + off);
  648. if (status == bit)
  649. break;
  650. if (pci_channel_offline(tp->pdev))
  651. break;
  652. udelay(10);
  653. }
  654. if (status != bit) {
  655. /* Revoke the lock request. */
  656. tg3_ape_write32(tp, gnt + off, bit);
  657. ret = -EBUSY;
  658. }
  659. return ret;
  660. }
  661. static void tg3_ape_unlock(struct tg3 *tp, int locknum)
  662. {
  663. u32 gnt, bit;
  664. if (!tg3_flag(tp, ENABLE_APE))
  665. return;
  666. switch (locknum) {
  667. case TG3_APE_LOCK_GPIO:
  668. if (tg3_asic_rev(tp) == ASIC_REV_5761)
  669. return;
  670. case TG3_APE_LOCK_GRC:
  671. case TG3_APE_LOCK_MEM:
  672. if (!tp->pci_fn)
  673. bit = APE_LOCK_GRANT_DRIVER;
  674. else
  675. bit = 1 << tp->pci_fn;
  676. break;
  677. case TG3_APE_LOCK_PHY0:
  678. case TG3_APE_LOCK_PHY1:
  679. case TG3_APE_LOCK_PHY2:
  680. case TG3_APE_LOCK_PHY3:
  681. bit = APE_LOCK_GRANT_DRIVER;
  682. break;
  683. default:
  684. return;
  685. }
  686. if (tg3_asic_rev(tp) == ASIC_REV_5761)
  687. gnt = TG3_APE_LOCK_GRANT;
  688. else
  689. gnt = TG3_APE_PER_LOCK_GRANT;
  690. tg3_ape_write32(tp, gnt + 4 * locknum, bit);
  691. }
  692. static int tg3_ape_event_lock(struct tg3 *tp, u32 timeout_us)
  693. {
  694. u32 apedata;
  695. while (timeout_us) {
  696. if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
  697. return -EBUSY;
  698. apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
  699. if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
  700. break;
  701. tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
  702. udelay(10);
  703. timeout_us -= (timeout_us > 10) ? 10 : timeout_us;
  704. }
  705. return timeout_us ? 0 : -EBUSY;
  706. }
  707. static int tg3_ape_wait_for_event(struct tg3 *tp, u32 timeout_us)
  708. {
  709. u32 i, apedata;
  710. for (i = 0; i < timeout_us / 10; i++) {
  711. apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
  712. if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
  713. break;
  714. udelay(10);
  715. }
  716. return i == timeout_us / 10;
  717. }
  718. static int tg3_ape_scratchpad_read(struct tg3 *tp, u32 *data, u32 base_off,
  719. u32 len)
  720. {
  721. int err;
  722. u32 i, bufoff, msgoff, maxlen, apedata;
  723. if (!tg3_flag(tp, APE_HAS_NCSI))
  724. return 0;
  725. apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
  726. if (apedata != APE_SEG_SIG_MAGIC)
  727. return -ENODEV;
  728. apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
  729. if (!(apedata & APE_FW_STATUS_READY))
  730. return -EAGAIN;
  731. bufoff = tg3_ape_read32(tp, TG3_APE_SEG_MSG_BUF_OFF) +
  732. TG3_APE_SHMEM_BASE;
  733. msgoff = bufoff + 2 * sizeof(u32);
  734. maxlen = tg3_ape_read32(tp, TG3_APE_SEG_MSG_BUF_LEN);
  735. while (len) {
  736. u32 length;
  737. /* Cap xfer sizes to scratchpad limits. */
  738. length = (len > maxlen) ? maxlen : len;
  739. len -= length;
  740. apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
  741. if (!(apedata & APE_FW_STATUS_READY))
  742. return -EAGAIN;
  743. /* Wait for up to 1 msec for APE to service previous event. */
  744. err = tg3_ape_event_lock(tp, 1000);
  745. if (err)
  746. return err;
  747. apedata = APE_EVENT_STATUS_DRIVER_EVNT |
  748. APE_EVENT_STATUS_SCRTCHPD_READ |
  749. APE_EVENT_STATUS_EVENT_PENDING;
  750. tg3_ape_write32(tp, TG3_APE_EVENT_STATUS, apedata);
  751. tg3_ape_write32(tp, bufoff, base_off);
  752. tg3_ape_write32(tp, bufoff + sizeof(u32), length);
  753. tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
  754. tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
  755. base_off += length;
  756. if (tg3_ape_wait_for_event(tp, 30000))
  757. return -EAGAIN;
  758. for (i = 0; length; i += 4, length -= 4) {
  759. u32 val = tg3_ape_read32(tp, msgoff + i);
  760. memcpy(data, &val, sizeof(u32));
  761. data++;
  762. }
  763. }
  764. return 0;
  765. }
  766. static int tg3_ape_send_event(struct tg3 *tp, u32 event)
  767. {
  768. int err;
  769. u32 apedata;
  770. apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
  771. if (apedata != APE_SEG_SIG_MAGIC)
  772. return -EAGAIN;
  773. apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
  774. if (!(apedata & APE_FW_STATUS_READY))
  775. return -EAGAIN;
  776. /* Wait for up to 1 millisecond for APE to service previous event. */
  777. err = tg3_ape_event_lock(tp, 1000);
  778. if (err)
  779. return err;
  780. tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
  781. event | APE_EVENT_STATUS_EVENT_PENDING);
  782. tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
  783. tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
  784. return 0;
  785. }
  786. static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
  787. {
  788. u32 event;
  789. u32 apedata;
  790. if (!tg3_flag(tp, ENABLE_APE))
  791. return;
  792. switch (kind) {
  793. case RESET_KIND_INIT:
  794. tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
  795. APE_HOST_SEG_SIG_MAGIC);
  796. tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
  797. APE_HOST_SEG_LEN_MAGIC);
  798. apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
  799. tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
  800. tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
  801. APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM));
  802. tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
  803. APE_HOST_BEHAV_NO_PHYLOCK);
  804. tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE,
  805. TG3_APE_HOST_DRVR_STATE_START);
  806. event = APE_EVENT_STATUS_STATE_START;
  807. break;
  808. case RESET_KIND_SHUTDOWN:
  809. /* With the interface we are currently using,
  810. * APE does not track driver state. Wiping
  811. * out the HOST SEGMENT SIGNATURE forces
  812. * the APE to assume OS absent status.
  813. */
  814. tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
  815. if (device_may_wakeup(&tp->pdev->dev) &&
  816. tg3_flag(tp, WOL_ENABLE)) {
  817. tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED,
  818. TG3_APE_HOST_WOL_SPEED_AUTO);
  819. apedata = TG3_APE_HOST_DRVR_STATE_WOL;
  820. } else
  821. apedata = TG3_APE_HOST_DRVR_STATE_UNLOAD;
  822. tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata);
  823. event = APE_EVENT_STATUS_STATE_UNLOAD;
  824. break;
  825. default:
  826. return;
  827. }
  828. event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
  829. tg3_ape_send_event(tp, event);
  830. }
  831. static void tg3_disable_ints(struct tg3 *tp)
  832. {
  833. int i;
  834. tw32(TG3PCI_MISC_HOST_CTRL,
  835. (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
  836. for (i = 0; i < tp->irq_max; i++)
  837. tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
  838. }
  839. static void tg3_enable_ints(struct tg3 *tp)
  840. {
  841. int i;
  842. tp->irq_sync = 0;
  843. wmb();
  844. tw32(TG3PCI_MISC_HOST_CTRL,
  845. (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
  846. tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
  847. for (i = 0; i < tp->irq_cnt; i++) {
  848. struct tg3_napi *tnapi = &tp->napi[i];
  849. tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
  850. if (tg3_flag(tp, 1SHOT_MSI))
  851. tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
  852. tp->coal_now |= tnapi->coal_now;
  853. }
  854. /* Force an initial interrupt */
  855. if (!tg3_flag(tp, TAGGED_STATUS) &&
  856. (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
  857. tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
  858. else
  859. tw32(HOSTCC_MODE, tp->coal_now);
  860. tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
  861. }
  862. static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
  863. {
  864. struct tg3 *tp = tnapi->tp;
  865. struct tg3_hw_status *sblk = tnapi->hw_status;
  866. unsigned int work_exists = 0;
  867. /* check for phy events */
  868. if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
  869. if (sblk->status & SD_STATUS_LINK_CHG)
  870. work_exists = 1;
  871. }
  872. /* check for TX work to do */
  873. if (sblk->idx[0].tx_consumer != tnapi->tx_cons)
  874. work_exists = 1;
  875. /* check for RX work to do */
  876. if (tnapi->rx_rcb_prod_idx &&
  877. *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
  878. work_exists = 1;
  879. return work_exists;
  880. }
  881. /* tg3_int_reenable
  882. * similar to tg3_enable_ints, but it accurately determines whether there
  883. * is new work pending and can return without flushing the PIO write
  884. * which reenables interrupts
  885. */
  886. static void tg3_int_reenable(struct tg3_napi *tnapi)
  887. {
  888. struct tg3 *tp = tnapi->tp;
  889. tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
  890. mmiowb();
  891. /* When doing tagged status, this work check is unnecessary.
  892. * The last_tag we write above tells the chip which piece of
  893. * work we've completed.
  894. */
  895. if (!tg3_flag(tp, TAGGED_STATUS) && tg3_has_work(tnapi))
  896. tw32(HOSTCC_MODE, tp->coalesce_mode |
  897. HOSTCC_MODE_ENABLE | tnapi->coal_now);
  898. }
  899. static void tg3_switch_clocks(struct tg3 *tp)
  900. {
  901. u32 clock_ctrl;
  902. u32 orig_clock_ctrl;
  903. if (tg3_flag(tp, CPMU_PRESENT) || tg3_flag(tp, 5780_CLASS))
  904. return;
  905. clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
  906. orig_clock_ctrl = clock_ctrl;
  907. clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
  908. CLOCK_CTRL_CLKRUN_OENABLE |
  909. 0x1f);
  910. tp->pci_clock_ctrl = clock_ctrl;
  911. if (tg3_flag(tp, 5705_PLUS)) {
  912. if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
  913. tw32_wait_f(TG3PCI_CLOCK_CTRL,
  914. clock_ctrl | CLOCK_CTRL_625_CORE, 40);
  915. }
  916. } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
  917. tw32_wait_f(TG3PCI_CLOCK_CTRL,
  918. clock_ctrl |
  919. (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
  920. 40);
  921. tw32_wait_f(TG3PCI_CLOCK_CTRL,
  922. clock_ctrl | (CLOCK_CTRL_ALTCLK),
  923. 40);
  924. }
  925. tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
  926. }
  927. #define PHY_BUSY_LOOPS 5000
  928. static int __tg3_readphy(struct tg3 *tp, unsigned int phy_addr, int reg,
  929. u32 *val)
  930. {
  931. u32 frame_val;
  932. unsigned int loops;
  933. int ret;
  934. if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
  935. tw32_f(MAC_MI_MODE,
  936. (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
  937. udelay(80);
  938. }
  939. tg3_ape_lock(tp, tp->phy_ape_lock);
  940. *val = 0x0;
  941. frame_val = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
  942. MI_COM_PHY_ADDR_MASK);
  943. frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
  944. MI_COM_REG_ADDR_MASK);
  945. frame_val |= (MI_COM_CMD_READ | MI_COM_START);
  946. tw32_f(MAC_MI_COM, frame_val);
  947. loops = PHY_BUSY_LOOPS;
  948. while (loops != 0) {
  949. udelay(10);
  950. frame_val = tr32(MAC_MI_COM);
  951. if ((frame_val & MI_COM_BUSY) == 0) {
  952. udelay(5);
  953. frame_val = tr32(MAC_MI_COM);
  954. break;
  955. }
  956. loops -= 1;
  957. }
  958. ret = -EBUSY;
  959. if (loops != 0) {
  960. *val = frame_val & MI_COM_DATA_MASK;
  961. ret = 0;
  962. }
  963. if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
  964. tw32_f(MAC_MI_MODE, tp->mi_mode);
  965. udelay(80);
  966. }
  967. tg3_ape_unlock(tp, tp->phy_ape_lock);
  968. return ret;
  969. }
  970. static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
  971. {
  972. return __tg3_readphy(tp, tp->phy_addr, reg, val);
  973. }
  974. static int __tg3_writephy(struct tg3 *tp, unsigned int phy_addr, int reg,
  975. u32 val)
  976. {
  977. u32 frame_val;
  978. unsigned int loops;
  979. int ret;
  980. if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
  981. (reg == MII_CTRL1000 || reg == MII_TG3_AUX_CTRL))
  982. return 0;
  983. if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
  984. tw32_f(MAC_MI_MODE,
  985. (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
  986. udelay(80);
  987. }
  988. tg3_ape_lock(tp, tp->phy_ape_lock);
  989. frame_val = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
  990. MI_COM_PHY_ADDR_MASK);
  991. frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
  992. MI_COM_REG_ADDR_MASK);
  993. frame_val |= (val & MI_COM_DATA_MASK);
  994. frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
  995. tw32_f(MAC_MI_COM, frame_val);
  996. loops = PHY_BUSY_LOOPS;
  997. while (loops != 0) {
  998. udelay(10);
  999. frame_val = tr32(MAC_MI_COM);
  1000. if ((frame_val & MI_COM_BUSY) == 0) {
  1001. udelay(5);
  1002. frame_val = tr32(MAC_MI_COM);
  1003. break;
  1004. }
  1005. loops -= 1;
  1006. }
  1007. ret = -EBUSY;
  1008. if (loops != 0)
  1009. ret = 0;
  1010. if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
  1011. tw32_f(MAC_MI_MODE, tp->mi_mode);
  1012. udelay(80);
  1013. }
  1014. tg3_ape_unlock(tp, tp->phy_ape_lock);
  1015. return ret;
  1016. }
  1017. static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
  1018. {
  1019. return __tg3_writephy(tp, tp->phy_addr, reg, val);
  1020. }
  1021. static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
  1022. {
  1023. int err;
  1024. err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
  1025. if (err)
  1026. goto done;
  1027. err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
  1028. if (err)
  1029. goto done;
  1030. err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
  1031. MII_TG3_MMD_CTRL_DATA_NOINC | devad);
  1032. if (err)
  1033. goto done;
  1034. err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val);
  1035. done:
  1036. return err;
  1037. }
  1038. static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val)
  1039. {
  1040. int err;
  1041. err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
  1042. if (err)
  1043. goto done;
  1044. err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
  1045. if (err)
  1046. goto done;
  1047. err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
  1048. MII_TG3_MMD_CTRL_DATA_NOINC | devad);
  1049. if (err)
  1050. goto done;
  1051. err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val);
  1052. done:
  1053. return err;
  1054. }
  1055. static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val)
  1056. {
  1057. int err;
  1058. err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
  1059. if (!err)
  1060. err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val);
  1061. return err;
  1062. }
  1063. static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
  1064. {
  1065. int err;
  1066. err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
  1067. if (!err)
  1068. err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
  1069. return err;
  1070. }
  1071. static int tg3_phy_auxctl_read(struct tg3 *tp, int reg, u32 *val)
  1072. {
  1073. int err;
  1074. err = tg3_writephy(tp, MII_TG3_AUX_CTRL,
  1075. (reg << MII_TG3_AUXCTL_MISC_RDSEL_SHIFT) |
  1076. MII_TG3_AUXCTL_SHDWSEL_MISC);
  1077. if (!err)
  1078. err = tg3_readphy(tp, MII_TG3_AUX_CTRL, val);
  1079. return err;
  1080. }
  1081. static int tg3_phy_auxctl_write(struct tg3 *tp, int reg, u32 set)
  1082. {
  1083. if (reg == MII_TG3_AUXCTL_SHDWSEL_MISC)
  1084. set |= MII_TG3_AUXCTL_MISC_WREN;
  1085. return tg3_writephy(tp, MII_TG3_AUX_CTRL, set | reg);
  1086. }
  1087. static int tg3_phy_toggle_auxctl_smdsp(struct tg3 *tp, bool enable)
  1088. {
  1089. u32 val;
  1090. int err;
  1091. err = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
  1092. if (err)
  1093. return err;
  1094. if (enable)
  1095. val |= MII_TG3_AUXCTL_ACTL_SMDSP_ENA;
  1096. else
  1097. val &= ~MII_TG3_AUXCTL_ACTL_SMDSP_ENA;
  1098. err = tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
  1099. val | MII_TG3_AUXCTL_ACTL_TX_6DB);
  1100. return err;
  1101. }
  1102. static int tg3_bmcr_reset(struct tg3 *tp)
  1103. {
  1104. u32 phy_control;
  1105. int limit, err;
  1106. /* OK, reset it, and poll the BMCR_RESET bit until it
  1107. * clears or we time out.
  1108. */
  1109. phy_control = BMCR_RESET;
  1110. err = tg3_writephy(tp, MII_BMCR, phy_control);
  1111. if (err != 0)
  1112. return -EBUSY;
  1113. limit = 5000;
  1114. while (limit--) {
  1115. err = tg3_readphy(tp, MII_BMCR, &phy_control);
  1116. if (err != 0)
  1117. return -EBUSY;
  1118. if ((phy_control & BMCR_RESET) == 0) {
  1119. udelay(40);
  1120. break;
  1121. }
  1122. udelay(10);
  1123. }
  1124. if (limit < 0)
  1125. return -EBUSY;
  1126. return 0;
  1127. }
  1128. static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
  1129. {
  1130. struct tg3 *tp = bp->priv;
  1131. u32 val;
  1132. spin_lock_bh(&tp->lock);
  1133. if (tg3_readphy(tp, reg, &val))
  1134. val = -EIO;
  1135. spin_unlock_bh(&tp->lock);
  1136. return val;
  1137. }
  1138. static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
  1139. {
  1140. struct tg3 *tp = bp->priv;
  1141. u32 ret = 0;
  1142. spin_lock_bh(&tp->lock);
  1143. if (tg3_writephy(tp, reg, val))
  1144. ret = -EIO;
  1145. spin_unlock_bh(&tp->lock);
  1146. return ret;
  1147. }
  1148. static int tg3_mdio_reset(struct mii_bus *bp)
  1149. {
  1150. return 0;
  1151. }
  1152. static void tg3_mdio_config_5785(struct tg3 *tp)
  1153. {
  1154. u32 val;
  1155. struct phy_device *phydev;
  1156. phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
  1157. switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
  1158. case PHY_ID_BCM50610:
  1159. case PHY_ID_BCM50610M:
  1160. val = MAC_PHYCFG2_50610_LED_MODES;
  1161. break;
  1162. case PHY_ID_BCMAC131:
  1163. val = MAC_PHYCFG2_AC131_LED_MODES;
  1164. break;
  1165. case PHY_ID_RTL8211C:
  1166. val = MAC_PHYCFG2_RTL8211C_LED_MODES;
  1167. break;
  1168. case PHY_ID_RTL8201E:
  1169. val = MAC_PHYCFG2_RTL8201E_LED_MODES;
  1170. break;
  1171. default:
  1172. return;
  1173. }
  1174. if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
  1175. tw32(MAC_PHYCFG2, val);
  1176. val = tr32(MAC_PHYCFG1);
  1177. val &= ~(MAC_PHYCFG1_RGMII_INT |
  1178. MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
  1179. val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
  1180. tw32(MAC_PHYCFG1, val);
  1181. return;
  1182. }
  1183. if (!tg3_flag(tp, RGMII_INBAND_DISABLE))
  1184. val |= MAC_PHYCFG2_EMODE_MASK_MASK |
  1185. MAC_PHYCFG2_FMODE_MASK_MASK |
  1186. MAC_PHYCFG2_GMODE_MASK_MASK |
  1187. MAC_PHYCFG2_ACT_MASK_MASK |
  1188. MAC_PHYCFG2_QUAL_MASK_MASK |
  1189. MAC_PHYCFG2_INBAND_ENABLE;
  1190. tw32(MAC_PHYCFG2, val);
  1191. val = tr32(MAC_PHYCFG1);
  1192. val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
  1193. MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
  1194. if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
  1195. if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
  1196. val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
  1197. if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
  1198. val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
  1199. }
  1200. val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
  1201. MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
  1202. tw32(MAC_PHYCFG1, val);
  1203. val = tr32(MAC_EXT_RGMII_MODE);
  1204. val &= ~(MAC_RGMII_MODE_RX_INT_B |
  1205. MAC_RGMII_MODE_RX_QUALITY |
  1206. MAC_RGMII_MODE_RX_ACTIVITY |
  1207. MAC_RGMII_MODE_RX_ENG_DET |
  1208. MAC_RGMII_MODE_TX_ENABLE |
  1209. MAC_RGMII_MODE_TX_LOWPWR |
  1210. MAC_RGMII_MODE_TX_RESET);
  1211. if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
  1212. if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
  1213. val |= MAC_RGMII_MODE_RX_INT_B |
  1214. MAC_RGMII_MODE_RX_QUALITY |
  1215. MAC_RGMII_MODE_RX_ACTIVITY |
  1216. MAC_RGMII_MODE_RX_ENG_DET;
  1217. if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
  1218. val |= MAC_RGMII_MODE_TX_ENABLE |
  1219. MAC_RGMII_MODE_TX_LOWPWR |
  1220. MAC_RGMII_MODE_TX_RESET;
  1221. }
  1222. tw32(MAC_EXT_RGMII_MODE, val);
  1223. }
  1224. static void tg3_mdio_start(struct tg3 *tp)
  1225. {
  1226. tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
  1227. tw32_f(MAC_MI_MODE, tp->mi_mode);
  1228. udelay(80);
  1229. if (tg3_flag(tp, MDIOBUS_INITED) &&
  1230. tg3_asic_rev(tp) == ASIC_REV_5785)
  1231. tg3_mdio_config_5785(tp);
  1232. }
  1233. static int tg3_mdio_init(struct tg3 *tp)
  1234. {
  1235. int i;
  1236. u32 reg;
  1237. struct phy_device *phydev;
  1238. if (tg3_flag(tp, 5717_PLUS)) {
  1239. u32 is_serdes;
  1240. tp->phy_addr = tp->pci_fn + 1;
  1241. if (tg3_chip_rev_id(tp) != CHIPREV_ID_5717_A0)
  1242. is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
  1243. else
  1244. is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
  1245. TG3_CPMU_PHY_STRAP_IS_SERDES;
  1246. if (is_serdes)
  1247. tp->phy_addr += 7;
  1248. } else
  1249. tp->phy_addr = TG3_PHY_MII_ADDR;
  1250. tg3_mdio_start(tp);
  1251. if (!tg3_flag(tp, USE_PHYLIB) || tg3_flag(tp, MDIOBUS_INITED))
  1252. return 0;
  1253. tp->mdio_bus = mdiobus_alloc();
  1254. if (tp->mdio_bus == NULL)
  1255. return -ENOMEM;
  1256. tp->mdio_bus->name = "tg3 mdio bus";
  1257. snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
  1258. (tp->pdev->bus->number << 8) | tp->pdev->devfn);
  1259. tp->mdio_bus->priv = tp;
  1260. tp->mdio_bus->parent = &tp->pdev->dev;
  1261. tp->mdio_bus->read = &tg3_mdio_read;
  1262. tp->mdio_bus->write = &tg3_mdio_write;
  1263. tp->mdio_bus->reset = &tg3_mdio_reset;
  1264. tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
  1265. tp->mdio_bus->irq = &tp->mdio_irq[0];
  1266. for (i = 0; i < PHY_MAX_ADDR; i++)
  1267. tp->mdio_bus->irq[i] = PHY_POLL;
  1268. /* The bus registration will look for all the PHYs on the mdio bus.
  1269. * Unfortunately, it does not ensure the PHY is powered up before
  1270. * accessing the PHY ID registers. A chip reset is the
  1271. * quickest way to bring the device back to an operational state..
  1272. */
  1273. if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
  1274. tg3_bmcr_reset(tp);
  1275. i = mdiobus_register(tp->mdio_bus);
  1276. if (i) {
  1277. dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
  1278. mdiobus_free(tp->mdio_bus);
  1279. return i;
  1280. }
  1281. phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
  1282. if (!phydev || !phydev->drv) {
  1283. dev_warn(&tp->pdev->dev, "No PHY devices\n");
  1284. mdiobus_unregister(tp->mdio_bus);
  1285. mdiobus_free(tp->mdio_bus);
  1286. return -ENODEV;
  1287. }
  1288. switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
  1289. case PHY_ID_BCM57780:
  1290. phydev->interface = PHY_INTERFACE_MODE_GMII;
  1291. phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
  1292. break;
  1293. case PHY_ID_BCM50610:
  1294. case PHY_ID_BCM50610M:
  1295. phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
  1296. PHY_BRCM_RX_REFCLK_UNUSED |
  1297. PHY_BRCM_DIS_TXCRXC_NOENRGY |
  1298. PHY_BRCM_AUTO_PWRDWN_ENABLE;
  1299. if (tg3_flag(tp, RGMII_INBAND_DISABLE))
  1300. phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
  1301. if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
  1302. phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
  1303. if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
  1304. phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
  1305. /* fallthru */
  1306. case PHY_ID_RTL8211C:
  1307. phydev->interface = PHY_INTERFACE_MODE_RGMII;
  1308. break;
  1309. case PHY_ID_RTL8201E:
  1310. case PHY_ID_BCMAC131:
  1311. phydev->interface = PHY_INTERFACE_MODE_MII;
  1312. phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
  1313. tp->phy_flags |= TG3_PHYFLG_IS_FET;
  1314. break;
  1315. }
  1316. tg3_flag_set(tp, MDIOBUS_INITED);
  1317. if (tg3_asic_rev(tp) == ASIC_REV_5785)
  1318. tg3_mdio_config_5785(tp);
  1319. return 0;
  1320. }
  1321. static void tg3_mdio_fini(struct tg3 *tp)
  1322. {
  1323. if (tg3_flag(tp, MDIOBUS_INITED)) {
  1324. tg3_flag_clear(tp, MDIOBUS_INITED);
  1325. mdiobus_unregister(tp->mdio_bus);
  1326. mdiobus_free(tp->mdio_bus);
  1327. }
  1328. }
  1329. /* tp->lock is held. */
  1330. static inline void tg3_generate_fw_event(struct tg3 *tp)
  1331. {
  1332. u32 val;
  1333. val = tr32(GRC_RX_CPU_EVENT);
  1334. val |= GRC_RX_CPU_DRIVER_EVENT;
  1335. tw32_f(GRC_RX_CPU_EVENT, val);
  1336. tp->last_event_jiffies = jiffies;
  1337. }
  1338. #define TG3_FW_EVENT_TIMEOUT_USEC 2500
  1339. /* tp->lock is held. */
  1340. static void tg3_wait_for_event_ack(struct tg3 *tp)
  1341. {
  1342. int i;
  1343. unsigned int delay_cnt;
  1344. long time_remain;
  1345. /* If enough time has passed, no wait is necessary. */
  1346. time_remain = (long)(tp->last_event_jiffies + 1 +
  1347. usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
  1348. (long)jiffies;
  1349. if (time_remain < 0)
  1350. return;
  1351. /* Check if we can shorten the wait time. */
  1352. delay_cnt = jiffies_to_usecs(time_remain);
  1353. if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
  1354. delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
  1355. delay_cnt = (delay_cnt >> 3) + 1;
  1356. for (i = 0; i < delay_cnt; i++) {
  1357. if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
  1358. break;
  1359. if (pci_channel_offline(tp->pdev))
  1360. break;
  1361. udelay(8);
  1362. }
  1363. }
  1364. /* tp->lock is held. */
  1365. static void tg3_phy_gather_ump_data(struct tg3 *tp, u32 *data)
  1366. {
  1367. u32 reg, val;
  1368. val = 0;
  1369. if (!tg3_readphy(tp, MII_BMCR, &reg))
  1370. val = reg << 16;
  1371. if (!tg3_readphy(tp, MII_BMSR, &reg))
  1372. val |= (reg & 0xffff);
  1373. *data++ = val;
  1374. val = 0;
  1375. if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
  1376. val = reg << 16;
  1377. if (!tg3_readphy(tp, MII_LPA, &reg))
  1378. val |= (reg & 0xffff);
  1379. *data++ = val;
  1380. val = 0;
  1381. if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {
  1382. if (!tg3_readphy(tp, MII_CTRL1000, &reg))
  1383. val = reg << 16;
  1384. if (!tg3_readphy(tp, MII_STAT1000, &reg))
  1385. val |= (reg & 0xffff);
  1386. }
  1387. *data++ = val;
  1388. if (!tg3_readphy(tp, MII_PHYADDR, &reg))
  1389. val = reg << 16;
  1390. else
  1391. val = 0;
  1392. *data++ = val;
  1393. }
  1394. /* tp->lock is held. */
  1395. static void tg3_ump_link_report(struct tg3 *tp)
  1396. {
  1397. u32 data[4];
  1398. if (!tg3_flag(tp, 5780_CLASS) || !tg3_flag(tp, ENABLE_ASF))
  1399. return;
  1400. tg3_phy_gather_ump_data(tp, data);
  1401. tg3_wait_for_event_ack(tp);
  1402. tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
  1403. tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
  1404. tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x0, data[0]);
  1405. tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x4, data[1]);
  1406. tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x8, data[2]);
  1407. tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0xc, data[3]);
  1408. tg3_generate_fw_event(tp);
  1409. }
  1410. /* tp->lock is held. */
  1411. static void tg3_stop_fw(struct tg3 *tp)
  1412. {
  1413. if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
  1414. /* Wait for RX cpu to ACK the previous event. */
  1415. tg3_wait_for_event_ack(tp);
  1416. tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
  1417. tg3_generate_fw_event(tp);
  1418. /* Wait for RX cpu to ACK this event. */
  1419. tg3_wait_for_event_ack(tp);
  1420. }
  1421. }
  1422. /* tp->lock is held. */
  1423. static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
  1424. {
  1425. tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
  1426. NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
  1427. if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
  1428. switch (kind) {
  1429. case RESET_KIND_INIT:
  1430. tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
  1431. DRV_STATE_START);
  1432. break;
  1433. case RESET_KIND_SHUTDOWN:
  1434. tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
  1435. DRV_STATE_UNLOAD);
  1436. break;
  1437. case RESET_KIND_SUSPEND:
  1438. tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
  1439. DRV_STATE_SUSPEND);
  1440. break;
  1441. default:
  1442. break;
  1443. }
  1444. }
  1445. }
  1446. /* tp->lock is held. */
  1447. static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
  1448. {
  1449. if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
  1450. switch (kind) {
  1451. case RESET_KIND_INIT:
  1452. tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
  1453. DRV_STATE_START_DONE);
  1454. break;
  1455. case RESET_KIND_SHUTDOWN:
  1456. tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
  1457. DRV_STATE_UNLOAD_DONE);
  1458. break;
  1459. default:
  1460. break;
  1461. }
  1462. }
  1463. }
  1464. /* tp->lock is held. */
  1465. static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
  1466. {
  1467. if (tg3_flag(tp, ENABLE_ASF)) {
  1468. switch (kind) {
  1469. case RESET_KIND_INIT:
  1470. tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
  1471. DRV_STATE_START);
  1472. break;
  1473. case RESET_KIND_SHUTDOWN:
  1474. tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
  1475. DRV_STATE_UNLOAD);
  1476. break;
  1477. case RESET_KIND_SUSPEND:
  1478. tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
  1479. DRV_STATE_SUSPEND);
  1480. break;
  1481. default:
  1482. break;
  1483. }
  1484. }
  1485. }
  1486. static int tg3_poll_fw(struct tg3 *tp)
  1487. {
  1488. int i;
  1489. u32 val;
  1490. if (tg3_flag(tp, NO_FWARE_REPORTED))
  1491. return 0;
  1492. if (tg3_flag(tp, IS_SSB_CORE)) {
  1493. /* We don't use firmware. */
  1494. return 0;
  1495. }
  1496. if (tg3_asic_rev(tp) == ASIC_REV_5906) {
  1497. /* Wait up to 20ms for init done. */
  1498. for (i = 0; i < 200; i++) {
  1499. if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
  1500. return 0;
  1501. if (pci_channel_offline(tp->pdev))
  1502. return -ENODEV;
  1503. udelay(100);
  1504. }
  1505. return -ENODEV;
  1506. }
  1507. /* Wait for firmware initialization to complete. */
  1508. for (i = 0; i < 100000; i++) {
  1509. tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
  1510. if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
  1511. break;
  1512. if (pci_channel_offline(tp->pdev)) {
  1513. if (!tg3_flag(tp, NO_FWARE_REPORTED)) {
  1514. tg3_flag_set(tp, NO_FWARE_REPORTED);
  1515. netdev_info(tp->dev, "No firmware running\n");
  1516. }
  1517. break;
  1518. }
  1519. udelay(10);
  1520. }
  1521. /* Chip might not be fitted with firmware. Some Sun onboard
  1522. * parts are configured like that. So don't signal the timeout
  1523. * of the above loop as an error, but do report the lack of
  1524. * running firmware once.
  1525. */
  1526. if (i >= 100000 && !tg3_flag(tp, NO_FWARE_REPORTED)) {
  1527. tg3_flag_set(tp, NO_FWARE_REPORTED);
  1528. netdev_info(tp->dev, "No firmware running\n");
  1529. }
  1530. if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0) {
  1531. /* The 57765 A0 needs a little more
  1532. * time to do some important work.
  1533. */
  1534. mdelay(10);
  1535. }
  1536. return 0;
  1537. }
  1538. static void tg3_link_report(struct tg3 *tp)
  1539. {
  1540. if (!netif_carrier_ok(tp->dev)) {
  1541. netif_info(tp, link, tp->dev, "Link is down\n");
  1542. tg3_ump_link_report(tp);
  1543. } else if (netif_msg_link(tp)) {
  1544. netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
  1545. (tp->link_config.active_speed == SPEED_1000 ?
  1546. 1000 :
  1547. (tp->link_config.active_speed == SPEED_100 ?
  1548. 100 : 10)),
  1549. (tp->link_config.active_duplex == DUPLEX_FULL ?
  1550. "full" : "half"));
  1551. netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
  1552. (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
  1553. "on" : "off",
  1554. (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
  1555. "on" : "off");
  1556. if (tp->phy_flags & TG3_PHYFLG_EEE_CAP)
  1557. netdev_info(tp->dev, "EEE is %s\n",
  1558. tp->setlpicnt ? "enabled" : "disabled");
  1559. tg3_ump_link_report(tp);
  1560. }
  1561. tp->link_up = netif_carrier_ok(tp->dev);
  1562. }
  1563. static u32 tg3_decode_flowctrl_1000T(u32 adv)
  1564. {
  1565. u32 flowctrl = 0;
  1566. if (adv & ADVERTISE_PAUSE_CAP) {
  1567. flowctrl |= FLOW_CTRL_RX;
  1568. if (!(adv & ADVERTISE_PAUSE_ASYM))
  1569. flowctrl |= FLOW_CTRL_TX;
  1570. } else if (adv & ADVERTISE_PAUSE_ASYM)
  1571. flowctrl |= FLOW_CTRL_TX;
  1572. return flowctrl;
  1573. }
  1574. static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
  1575. {
  1576. u16 miireg;
  1577. if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
  1578. miireg = ADVERTISE_1000XPAUSE;
  1579. else if (flow_ctrl & FLOW_CTRL_TX)
  1580. miireg = ADVERTISE_1000XPSE_ASYM;
  1581. else if (flow_ctrl & FLOW_CTRL_RX)
  1582. miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
  1583. else
  1584. miireg = 0;
  1585. return miireg;
  1586. }
  1587. static u32 tg3_decode_flowctrl_1000X(u32 adv)
  1588. {
  1589. u32 flowctrl = 0;
  1590. if (adv & ADVERTISE_1000XPAUSE) {
  1591. flowctrl |= FLOW_CTRL_RX;
  1592. if (!(adv & ADVERTISE_1000XPSE_ASYM))
  1593. flowctrl |= FLOW_CTRL_TX;
  1594. } else if (adv & ADVERTISE_1000XPSE_ASYM)
  1595. flowctrl |= FLOW_CTRL_TX;
  1596. return flowctrl;
  1597. }
  1598. static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
  1599. {
  1600. u8 cap = 0;
  1601. if (lcladv & rmtadv & ADVERTISE_1000XPAUSE) {
  1602. cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
  1603. } else if (lcladv & rmtadv & ADVERTISE_1000XPSE_ASYM) {
  1604. if (lcladv & ADVERTISE_1000XPAUSE)
  1605. cap = FLOW_CTRL_RX;
  1606. if (rmtadv & ADVERTISE_1000XPAUSE)
  1607. cap = FLOW_CTRL_TX;
  1608. }
  1609. return cap;
  1610. }
  1611. static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
  1612. {
  1613. u8 autoneg;
  1614. u8 flowctrl = 0;
  1615. u32 old_rx_mode = tp->rx_mode;
  1616. u32 old_tx_mode = tp->tx_mode;
  1617. if (tg3_flag(tp, USE_PHYLIB))
  1618. autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
  1619. else
  1620. autoneg = tp->link_config.autoneg;
  1621. if (autoneg == AUTONEG_ENABLE && tg3_flag(tp, PAUSE_AUTONEG)) {
  1622. if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
  1623. flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
  1624. else
  1625. flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
  1626. } else
  1627. flowctrl = tp->link_config.flowctrl;
  1628. tp->link_config.active_flowctrl = flowctrl;
  1629. if (flowctrl & FLOW_CTRL_RX)
  1630. tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
  1631. else
  1632. tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
  1633. if (old_rx_mode != tp->rx_mode)
  1634. tw32_f(MAC_RX_MODE, tp->rx_mode);
  1635. if (flowctrl & FLOW_CTRL_TX)
  1636. tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
  1637. else
  1638. tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
  1639. if (old_tx_mode != tp->tx_mode)
  1640. tw32_f(MAC_TX_MODE, tp->tx_mode);
  1641. }
  1642. static void tg3_adjust_link(struct net_device *dev)
  1643. {
  1644. u8 oldflowctrl, linkmesg = 0;
  1645. u32 mac_mode, lcl_adv, rmt_adv;
  1646. struct tg3 *tp = netdev_priv(dev);
  1647. struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
  1648. spin_lock_bh(&tp->lock);
  1649. mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
  1650. MAC_MODE_HALF_DUPLEX);
  1651. oldflowctrl = tp->link_config.active_flowctrl;
  1652. if (phydev->link) {
  1653. lcl_adv = 0;
  1654. rmt_adv = 0;
  1655. if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
  1656. mac_mode |= MAC_MODE_PORT_MODE_MII;
  1657. else if (phydev->speed == SPEED_1000 ||
  1658. tg3_asic_rev(tp) != ASIC_REV_5785)
  1659. mac_mode |= MAC_MODE_PORT_MODE_GMII;
  1660. else
  1661. mac_mode |= MAC_MODE_PORT_MODE_MII;
  1662. if (phydev->duplex == DUPLEX_HALF)
  1663. mac_mode |= MAC_MODE_HALF_DUPLEX;
  1664. else {
  1665. lcl_adv = mii_advertise_flowctrl(
  1666. tp->link_config.flowctrl);
  1667. if (phydev->pause)
  1668. rmt_adv = LPA_PAUSE_CAP;
  1669. if (phydev->asym_pause)
  1670. rmt_adv |= LPA_PAUSE_ASYM;
  1671. }
  1672. tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
  1673. } else
  1674. mac_mode |= MAC_MODE_PORT_MODE_GMII;
  1675. if (mac_mode != tp->mac_mode) {
  1676. tp->mac_mode = mac_mode;
  1677. tw32_f(MAC_MODE, tp->mac_mode);
  1678. udelay(40);
  1679. }
  1680. if (tg3_asic_rev(tp) == ASIC_REV_5785) {
  1681. if (phydev->speed == SPEED_10)
  1682. tw32(MAC_MI_STAT,
  1683. MAC_MI_STAT_10MBPS_MODE |
  1684. MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
  1685. else
  1686. tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
  1687. }
  1688. if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
  1689. tw32(MAC_TX_LENGTHS,
  1690. ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
  1691. (6 << TX_LENGTHS_IPG_SHIFT) |
  1692. (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
  1693. else
  1694. tw32(MAC_TX_LENGTHS,
  1695. ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
  1696. (6 << TX_LENGTHS_IPG_SHIFT) |
  1697. (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
  1698. if (phydev->link != tp->old_link ||
  1699. phydev->speed != tp->link_config.active_speed ||
  1700. phydev->duplex != tp->link_config.active_duplex ||
  1701. oldflowctrl != tp->link_config.active_flowctrl)
  1702. linkmesg = 1;
  1703. tp->old_link = phydev->link;
  1704. tp->link_config.active_speed = phydev->speed;
  1705. tp->link_config.active_duplex = phydev->duplex;
  1706. spin_unlock_bh(&tp->lock);
  1707. if (linkmesg)
  1708. tg3_link_report(tp);
  1709. }
  1710. static int tg3_phy_init(struct tg3 *tp)
  1711. {
  1712. struct phy_device *phydev;
  1713. if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)
  1714. return 0;
  1715. /* Bring the PHY back to a known state. */
  1716. tg3_bmcr_reset(tp);
  1717. phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
  1718. /* Attach the MAC to the PHY. */
  1719. phydev = phy_connect(tp->dev, dev_name(&phydev->dev),
  1720. tg3_adjust_link, phydev->interface);
  1721. if (IS_ERR(phydev)) {
  1722. dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
  1723. return PTR_ERR(phydev);
  1724. }
  1725. /* Mask with MAC supported features. */
  1726. switch (phydev->interface) {
  1727. case PHY_INTERFACE_MODE_GMII:
  1728. case PHY_INTERFACE_MODE_RGMII:
  1729. if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
  1730. phydev->supported &= (PHY_GBIT_FEATURES |
  1731. SUPPORTED_Pause |
  1732. SUPPORTED_Asym_Pause);
  1733. break;
  1734. }
  1735. /* fallthru */
  1736. case PHY_INTERFACE_MODE_MII:
  1737. phydev->supported &= (PHY_BASIC_FEATURES |
  1738. SUPPORTED_Pause |
  1739. SUPPORTED_Asym_Pause);
  1740. break;
  1741. default:
  1742. phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
  1743. return -EINVAL;
  1744. }
  1745. tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED;
  1746. phydev->advertising = phydev->supported;
  1747. return 0;
  1748. }
  1749. static void tg3_phy_start(struct tg3 *tp)
  1750. {
  1751. struct phy_device *phydev;
  1752. if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
  1753. return;
  1754. phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
  1755. if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
  1756. tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
  1757. phydev->speed = tp->link_config.speed;
  1758. phydev->duplex = tp->link_config.duplex;
  1759. phydev->autoneg = tp->link_config.autoneg;
  1760. phydev->advertising = tp->link_config.advertising;
  1761. }
  1762. phy_start(phydev);
  1763. phy_start_aneg(phydev);
  1764. }
  1765. static void tg3_phy_stop(struct tg3 *tp)
  1766. {
  1767. if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
  1768. return;
  1769. phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
  1770. }
  1771. static void tg3_phy_fini(struct tg3 *tp)
  1772. {
  1773. if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
  1774. phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
  1775. tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED;
  1776. }
  1777. }
  1778. static int tg3_phy_set_extloopbk(struct tg3 *tp)
  1779. {
  1780. int err;
  1781. u32 val;
  1782. if (tp->phy_flags & TG3_PHYFLG_IS_FET)
  1783. return 0;
  1784. if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
  1785. /* Cannot do read-modify-write on 5401 */
  1786. err = tg3_phy_auxctl_write(tp,
  1787. MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
  1788. MII_TG3_AUXCTL_ACTL_EXTLOOPBK |
  1789. 0x4c20);
  1790. goto done;
  1791. }
  1792. err = tg3_phy_auxctl_read(tp,
  1793. MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
  1794. if (err)
  1795. return err;
  1796. val |= MII_TG3_AUXCTL_ACTL_EXTLOOPBK;
  1797. err = tg3_phy_auxctl_write(tp,
  1798. MII_TG3_AUXCTL_SHDWSEL_AUXCTL, val);
  1799. done:
  1800. return err;
  1801. }
  1802. static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
  1803. {
  1804. u32 phytest;
  1805. if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
  1806. u32 phy;
  1807. tg3_writephy(tp, MII_TG3_FET_TEST,
  1808. phytest | MII_TG3_FET_SHADOW_EN);
  1809. if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
  1810. if (enable)
  1811. phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
  1812. else
  1813. phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
  1814. tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
  1815. }
  1816. tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
  1817. }
  1818. }
  1819. static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
  1820. {
  1821. u32 reg;
  1822. if (!tg3_flag(tp, 5705_PLUS) ||
  1823. (tg3_flag(tp, 5717_PLUS) &&
  1824. (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
  1825. return;
  1826. if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
  1827. tg3_phy_fet_toggle_apd(tp, enable);
  1828. return;
  1829. }
  1830. reg = MII_TG3_MISC_SHDW_WREN |
  1831. MII_TG3_MISC_SHDW_SCR5_SEL |
  1832. MII_TG3_MISC_SHDW_SCR5_LPED |
  1833. MII_TG3_MISC_SHDW_SCR5_DLPTLM |
  1834. MII_TG3_MISC_SHDW_SCR5_SDTL |
  1835. MII_TG3_MISC_SHDW_SCR5_C125OE;
  1836. if (tg3_asic_rev(tp) != ASIC_REV_5784 || !enable)
  1837. reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
  1838. tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
  1839. reg = MII_TG3_MISC_SHDW_WREN |
  1840. MII_TG3_MISC_SHDW_APD_SEL |
  1841. MII_TG3_MISC_SHDW_APD_WKTM_84MS;
  1842. if (enable)
  1843. reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
  1844. tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
  1845. }
  1846. static void tg3_phy_toggle_automdix(struct tg3 *tp, bool enable)
  1847. {
  1848. u32 phy;
  1849. if (!tg3_flag(tp, 5705_PLUS) ||
  1850. (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
  1851. return;
  1852. if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
  1853. u32 ephy;
  1854. if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
  1855. u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
  1856. tg3_writephy(tp, MII_TG3_FET_TEST,
  1857. ephy | MII_TG3_FET_SHADOW_EN);
  1858. if (!tg3_readphy(tp, reg, &phy)) {
  1859. if (enable)
  1860. phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
  1861. else
  1862. phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
  1863. tg3_writephy(tp, reg, phy);
  1864. }
  1865. tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
  1866. }
  1867. } else {
  1868. int ret;
  1869. ret = tg3_phy_auxctl_read(tp,
  1870. MII_TG3_AUXCTL_SHDWSEL_MISC, &phy);
  1871. if (!ret) {
  1872. if (enable)
  1873. phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
  1874. else
  1875. phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
  1876. tg3_phy_auxctl_write(tp,
  1877. MII_TG3_AUXCTL_SHDWSEL_MISC, phy);
  1878. }
  1879. }
  1880. }
  1881. static void tg3_phy_set_wirespeed(struct tg3 *tp)
  1882. {
  1883. int ret;
  1884. u32 val;
  1885. if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
  1886. return;
  1887. ret = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, &val);
  1888. if (!ret)
  1889. tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_MISC,
  1890. val | MII_TG3_AUXCTL_MISC_WIRESPD_EN);
  1891. }
  1892. static void tg3_phy_apply_otp(struct tg3 *tp)
  1893. {
  1894. u32 otp, phy;
  1895. if (!tp->phy_otp)
  1896. return;
  1897. otp = tp->phy_otp;
  1898. if (tg3_phy_toggle_auxctl_smdsp(tp, true))
  1899. return;
  1900. phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
  1901. phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
  1902. tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
  1903. phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
  1904. ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
  1905. tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
  1906. phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
  1907. phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
  1908. tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
  1909. phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
  1910. tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
  1911. phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
  1912. tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
  1913. phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
  1914. ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
  1915. tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
  1916. tg3_phy_toggle_auxctl_smdsp(tp, false);
  1917. }
  1918. static void tg3_eee_pull_config(struct tg3 *tp, struct ethtool_eee *eee)
  1919. {
  1920. u32 val;
  1921. struct ethtool_eee *dest = &tp->eee;
  1922. if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
  1923. return;
  1924. if (eee)
  1925. dest = eee;
  1926. if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, TG3_CL45_D7_EEERES_STAT, &val))
  1927. return;
  1928. /* Pull eee_active */
  1929. if (val == TG3_CL45_D7_EEERES_STAT_LP_1000T ||
  1930. val == TG3_CL45_D7_EEERES_STAT_LP_100TX) {
  1931. dest->eee_active = 1;
  1932. } else
  1933. dest->eee_active = 0;
  1934. /* Pull lp advertised settings */
  1935. if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE, &val))
  1936. return;
  1937. dest->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(val);
  1938. /* Pull advertised and eee_enabled settings */
  1939. if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, &val))
  1940. return;
  1941. dest->eee_enabled = !!val;
  1942. dest->advertised = mmd_eee_adv_to_ethtool_adv_t(val);
  1943. /* Pull tx_lpi_enabled */
  1944. val = tr32(TG3_CPMU_EEE_MODE);
  1945. dest->tx_lpi_enabled = !!(val & TG3_CPMU_EEEMD_LPI_IN_TX);
  1946. /* Pull lpi timer value */
  1947. dest->tx_lpi_timer = tr32(TG3_CPMU_EEE_DBTMR1) & 0xffff;
  1948. }
  1949. static void tg3_phy_eee_adjust(struct tg3 *tp, bool current_link_up)
  1950. {
  1951. u32 val;
  1952. if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
  1953. return;
  1954. tp->setlpicnt = 0;
  1955. if (tp->link_config.autoneg == AUTONEG_ENABLE &&
  1956. current_link_up &&
  1957. tp->link_config.active_duplex == DUPLEX_FULL &&
  1958. (tp->link_config.active_speed == SPEED_100 ||
  1959. tp->link_config.active_speed == SPEED_1000)) {
  1960. u32 eeectl;
  1961. if (tp->link_config.active_speed == SPEED_1000)
  1962. eeectl = TG3_CPMU_EEE_CTRL_EXIT_16_5_US;
  1963. else
  1964. eeectl = TG3_CPMU_EEE_CTRL_EXIT_36_US;
  1965. tw32(TG3_CPMU_EEE_CTRL, eeectl);
  1966. tg3_eee_pull_config(tp, NULL);
  1967. if (tp->eee.eee_active)
  1968. tp->setlpicnt = 2;
  1969. }
  1970. if (!tp->setlpicnt) {
  1971. if (current_link_up &&
  1972. !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
  1973. tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0000);
  1974. tg3_phy_toggle_auxctl_smdsp(tp, false);
  1975. }
  1976. val = tr32(TG3_CPMU_EEE_MODE);
  1977. tw32(TG3_CPMU_EEE_MODE, val & ~TG3_CPMU_EEEMD_LPI_ENABLE);
  1978. }
  1979. }
  1980. static void tg3_phy_eee_enable(struct tg3 *tp)
  1981. {
  1982. u32 val;
  1983. if (tp->link_config.active_speed == SPEED_1000 &&
  1984. (tg3_asic_rev(tp) == ASIC_REV_5717 ||
  1985. tg3_asic_rev(tp) == ASIC_REV_5719 ||
  1986. tg3_flag(tp, 57765_CLASS)) &&
  1987. !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
  1988. val = MII_TG3_DSP_TAP26_ALNOKO |
  1989. MII_TG3_DSP_TAP26_RMRXSTO;
  1990. tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
  1991. tg3_phy_toggle_auxctl_smdsp(tp, false);
  1992. }
  1993. val = tr32(TG3_CPMU_EEE_MODE);
  1994. tw32(TG3_CPMU_EEE_MODE, val | TG3_CPMU_EEEMD_LPI_ENABLE);
  1995. }
  1996. static int tg3_wait_macro_done(struct tg3 *tp)
  1997. {
  1998. int limit = 100;
  1999. while (limit--) {
  2000. u32 tmp32;
  2001. if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {
  2002. if ((tmp32 & 0x1000) == 0)
  2003. break;
  2004. }
  2005. }
  2006. if (limit < 0)
  2007. return -EBUSY;
  2008. return 0;
  2009. }
  2010. static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
  2011. {
  2012. static const u32 test_pat[4][6] = {
  2013. { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
  2014. { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
  2015. { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
  2016. { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
  2017. };
  2018. int chan;
  2019. for (chan = 0; chan < 4; chan++) {
  2020. int i;
  2021. tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
  2022. (chan * 0x2000) | 0x0200);
  2023. tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
  2024. for (i = 0; i < 6; i++)
  2025. tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
  2026. test_pat[chan][i]);
  2027. tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
  2028. if (tg3_wait_macro_done(tp)) {
  2029. *resetp = 1;
  2030. return -EBUSY;
  2031. }
  2032. tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
  2033. (chan * 0x2000) | 0x0200);
  2034. tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
  2035. if (tg3_wait_macro_done(tp)) {
  2036. *resetp = 1;
  2037. return -EBUSY;
  2038. }
  2039. tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
  2040. if (tg3_wait_macro_done(tp)) {
  2041. *resetp = 1;
  2042. return -EBUSY;
  2043. }
  2044. for (i = 0; i < 6; i += 2) {
  2045. u32 low, high;
  2046. if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
  2047. tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
  2048. tg3_wait_macro_done(tp)) {
  2049. *resetp = 1;
  2050. return -EBUSY;
  2051. }
  2052. low &= 0x7fff;
  2053. high &= 0x000f;
  2054. if (low != test_pat[chan][i] ||
  2055. high != test_pat[chan][i+1]) {
  2056. tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
  2057. tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
  2058. tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
  2059. return -EBUSY;
  2060. }
  2061. }
  2062. }
  2063. return 0;
  2064. }
  2065. static int tg3_phy_reset_chanpat(struct tg3 *tp)
  2066. {
  2067. int chan;
  2068. for (chan = 0; chan < 4; chan++) {
  2069. int i;
  2070. tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
  2071. (chan * 0x2000) | 0x0200);
  2072. tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
  2073. for (i = 0; i < 6; i++)
  2074. tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
  2075. tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
  2076. if (tg3_wait_macro_done(tp))
  2077. return -EBUSY;
  2078. }
  2079. return 0;
  2080. }
  2081. static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
  2082. {
  2083. u32 reg32, phy9_orig;
  2084. int retries, do_phy_reset, err;
  2085. retries = 10;
  2086. do_phy_reset = 1;
  2087. do {
  2088. if (do_phy_reset) {
  2089. err = tg3_bmcr_reset(tp);
  2090. if (err)
  2091. return err;
  2092. do_phy_reset = 0;
  2093. }
  2094. /* Disable transmitter and interrupt. */
  2095. if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
  2096. continue;
  2097. reg32 |= 0x3000;
  2098. tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
  2099. /* Set full-duplex, 1000 mbps. */
  2100. tg3_writephy(tp, MII_BMCR,
  2101. BMCR_FULLDPLX | BMCR_SPEED1000);
  2102. /* Set to master mode. */
  2103. if (tg3_readphy(tp, MII_CTRL1000, &phy9_orig))
  2104. continue;
  2105. tg3_writephy(tp, MII_CTRL1000,
  2106. CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER);
  2107. err = tg3_phy_toggle_auxctl_smdsp(tp, true);
  2108. if (err)
  2109. return err;
  2110. /* Block the PHY control access. */
  2111. tg3_phydsp_write(tp, 0x8005, 0x0800);
  2112. err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
  2113. if (!err)
  2114. break;
  2115. } while (--retries);
  2116. err = tg3_phy_reset_chanpat(tp);
  2117. if (err)
  2118. return err;
  2119. tg3_phydsp_write(tp, 0x8005, 0x0000);
  2120. tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
  2121. tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
  2122. tg3_phy_toggle_auxctl_smdsp(tp, false);
  2123. tg3_writephy(tp, MII_CTRL1000, phy9_orig);
  2124. if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
  2125. reg32 &= ~0x3000;
  2126. tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
  2127. } else if (!err)
  2128. err = -EBUSY;
  2129. return err;
  2130. }
  2131. static void tg3_carrier_off(struct tg3 *tp)
  2132. {
  2133. netif_carrier_off(tp->dev);
  2134. tp->link_up = false;
  2135. }
  2136. static void tg3_warn_mgmt_link_flap(struct tg3 *tp)
  2137. {
  2138. if (tg3_flag(tp, ENABLE_ASF))
  2139. netdev_warn(tp->dev,
  2140. "Management side-band traffic will be interrupted during phy settings change\n");
  2141. }
  2142. /* This will reset the tigon3 PHY if there is no valid
  2143. * link unless the FORCE argument is non-zero.
  2144. */
  2145. static int tg3_phy_reset(struct tg3 *tp)
  2146. {
  2147. u32 val, cpmuctrl;
  2148. int err;
  2149. if (tg3_asic_rev(tp) == ASIC_REV_5906) {
  2150. val = tr32(GRC_MISC_CFG);
  2151. tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
  2152. udelay(40);
  2153. }
  2154. err = tg3_readphy(tp, MII_BMSR, &val);
  2155. err |= tg3_readphy(tp, MII_BMSR, &val);
  2156. if (err != 0)
  2157. return -EBUSY;
  2158. if (netif_running(tp->dev) && tp->link_up) {
  2159. netif_carrier_off(tp->dev);
  2160. tg3_link_report(tp);
  2161. }
  2162. if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
  2163. tg3_asic_rev(tp) == ASIC_REV_5704 ||
  2164. tg3_asic_rev(tp) == ASIC_REV_5705) {
  2165. err = tg3_phy_reset_5703_4_5(tp);
  2166. if (err)
  2167. return err;
  2168. goto out;
  2169. }
  2170. cpmuctrl = 0;
  2171. if (tg3_asic_rev(tp) == ASIC_REV_5784 &&
  2172. tg3_chip_rev(tp) != CHIPREV_5784_AX) {
  2173. cpmuctrl = tr32(TG3_CPMU_CTRL);
  2174. if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
  2175. tw32(TG3_CPMU_CTRL,
  2176. cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
  2177. }
  2178. err = tg3_bmcr_reset(tp);
  2179. if (err)
  2180. return err;
  2181. if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
  2182. val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
  2183. tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val);
  2184. tw32(TG3_CPMU_CTRL, cpmuctrl);
  2185. }
  2186. if (tg3_chip_rev(tp) == CHIPREV_5784_AX ||
  2187. tg3_chip_rev(tp) == CHIPREV_5761_AX) {
  2188. val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
  2189. if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
  2190. CPMU_LSPD_1000MB_MACCLK_12_5) {
  2191. val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
  2192. udelay(40);
  2193. tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
  2194. }
  2195. }
  2196. if (tg3_flag(tp, 5717_PLUS) &&
  2197. (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
  2198. return 0;
  2199. tg3_phy_apply_otp(tp);
  2200. if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
  2201. tg3_phy_toggle_apd(tp, true);
  2202. else
  2203. tg3_phy_toggle_apd(tp, false);
  2204. out:
  2205. if ((tp->phy_flags & TG3_PHYFLG_ADC_BUG) &&
  2206. !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
  2207. tg3_phydsp_write(tp, 0x201f, 0x2aaa);
  2208. tg3_phydsp_write(tp, 0x000a, 0x0323);
  2209. tg3_phy_toggle_auxctl_smdsp(tp, false);
  2210. }
  2211. if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
  2212. tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
  2213. tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
  2214. }
  2215. if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
  2216. if (!tg3_phy_toggle_auxctl_smdsp(tp, true)) {
  2217. tg3_phydsp_write(tp, 0x000a, 0x310b);
  2218. tg3_phydsp_write(tp, 0x201f, 0x9506);
  2219. tg3_phydsp_write(tp, 0x401f, 0x14e2);
  2220. tg3_phy_toggle_auxctl_smdsp(tp, false);
  2221. }
  2222. } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
  2223. if (!tg3_phy_toggle_auxctl_smdsp(tp, true)) {
  2224. tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
  2225. if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
  2226. tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
  2227. tg3_writephy(tp, MII_TG3_TEST1,
  2228. MII_TG3_TEST1_TRIM_EN | 0x4);
  2229. } else
  2230. tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
  2231. tg3_phy_toggle_auxctl_smdsp(tp, false);
  2232. }
  2233. }
  2234. /* Set Extended packet length bit (bit 14) on all chips that */
  2235. /* support jumbo frames */
  2236. if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
  2237. /* Cannot do read-modify-write on 5401 */
  2238. tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
  2239. } else if (tg3_flag(tp, JUMBO_CAPABLE)) {
  2240. /* Set bit 14 with read-modify-write to preserve other bits */
  2241. err = tg3_phy_auxctl_read(tp,
  2242. MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
  2243. if (!err)
  2244. tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
  2245. val | MII_TG3_AUXCTL_ACTL_EXTPKTLEN);
  2246. }
  2247. /* Set phy register 0x10 bit 0 to high fifo elasticity to support
  2248. * jumbo frames transmission.
  2249. */
  2250. if (tg3_flag(tp, JUMBO_CAPABLE)) {
  2251. if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val))
  2252. tg3_writephy(tp, MII_TG3_EXT_CTRL,
  2253. val | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
  2254. }
  2255. if (tg3_asic_rev(tp) == ASIC_REV_5906) {
  2256. /* adjust output voltage */
  2257. tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
  2258. }
  2259. if (tg3_chip_rev_id(tp) == CHIPREV_ID_5762_A0)
  2260. tg3_phydsp_write(tp, 0xffb, 0x4000);
  2261. tg3_phy_toggle_automdix(tp, true);
  2262. tg3_phy_set_wirespeed(tp);
  2263. return 0;
  2264. }
  2265. #define TG3_GPIO_MSG_DRVR_PRES 0x00000001
  2266. #define TG3_GPIO_MSG_NEED_VAUX 0x00000002
  2267. #define TG3_GPIO_MSG_MASK (TG3_GPIO_MSG_DRVR_PRES | \
  2268. TG3_GPIO_MSG_NEED_VAUX)
  2269. #define TG3_GPIO_MSG_ALL_DRVR_PRES_MASK \
  2270. ((TG3_GPIO_MSG_DRVR_PRES << 0) | \
  2271. (TG3_GPIO_MSG_DRVR_PRES << 4) | \
  2272. (TG3_GPIO_MSG_DRVR_PRES << 8) | \
  2273. (TG3_GPIO_MSG_DRVR_PRES << 12))
  2274. #define TG3_GPIO_MSG_ALL_NEED_VAUX_MASK \
  2275. ((TG3_GPIO_MSG_NEED_VAUX << 0) | \
  2276. (TG3_GPIO_MSG_NEED_VAUX << 4) | \
  2277. (TG3_GPIO_MSG_NEED_VAUX << 8) | \
  2278. (TG3_GPIO_MSG_NEED_VAUX << 12))
  2279. static inline u32 tg3_set_function_status(struct tg3 *tp, u32 newstat)
  2280. {
  2281. u32 status, shift;
  2282. if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
  2283. tg3_asic_rev(tp) == ASIC_REV_5719)
  2284. status = tg3_ape_read32(tp, TG3_APE_GPIO_MSG);
  2285. else
  2286. status = tr32(TG3_CPMU_DRV_STATUS);
  2287. shift = TG3_APE_GPIO_MSG_SHIFT + 4 * tp->pci_fn;
  2288. status &= ~(TG3_GPIO_MSG_MASK << shift);
  2289. status |= (newstat << shift);
  2290. if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
  2291. tg3_asic_rev(tp) == ASIC_REV_5719)
  2292. tg3_ape_write32(tp, TG3_APE_GPIO_MSG, status);
  2293. else
  2294. tw32(TG3_CPMU_DRV_STATUS, status);
  2295. return status >> TG3_APE_GPIO_MSG_SHIFT;
  2296. }
  2297. static inline int tg3_pwrsrc_switch_to_vmain(struct tg3 *tp)
  2298. {
  2299. if (!tg3_flag(tp, IS_NIC))
  2300. return 0;
  2301. if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
  2302. tg3_asic_rev(tp) == ASIC_REV_5719 ||
  2303. tg3_asic_rev(tp) == ASIC_REV_5720) {
  2304. if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
  2305. return -EIO;
  2306. tg3_set_function_status(tp, TG3_GPIO_MSG_DRVR_PRES);
  2307. tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
  2308. TG3_GRC_LCLCTL_PWRSW_DELAY);
  2309. tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
  2310. } else {
  2311. tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
  2312. TG3_GRC_LCLCTL_PWRSW_DELAY);
  2313. }
  2314. return 0;
  2315. }
  2316. static void tg3_pwrsrc_die_with_vmain(struct tg3 *tp)
  2317. {
  2318. u32 grc_local_ctrl;
  2319. if (!tg3_flag(tp, IS_NIC) ||
  2320. tg3_asic_rev(tp) == ASIC_REV_5700 ||
  2321. tg3_asic_rev(tp) == ASIC_REV_5701)
  2322. return;
  2323. grc_local_ctrl = tp->grc_local_ctrl | GRC_LCLCTRL_GPIO_OE1;
  2324. tw32_wait_f(GRC_LOCAL_CTRL,
  2325. grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
  2326. TG3_GRC_LCLCTL_PWRSW_DELAY);
  2327. tw32_wait_f(GRC_LOCAL_CTRL,
  2328. grc_local_ctrl,
  2329. TG3_GRC_LCLCTL_PWRSW_DELAY);
  2330. tw32_wait_f(GRC_LOCAL_CTRL,
  2331. grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
  2332. TG3_GRC_LCLCTL_PWRSW_DELAY);
  2333. }
  2334. static void tg3_pwrsrc_switch_to_vaux(struct tg3 *tp)
  2335. {
  2336. if (!tg3_flag(tp, IS_NIC))
  2337. return;
  2338. if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
  2339. tg3_asic_rev(tp) == ASIC_REV_5701) {
  2340. tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
  2341. (GRC_LCLCTRL_GPIO_OE0 |
  2342. GRC_LCLCTRL_GPIO_OE1 |
  2343. GRC_LCLCTRL_GPIO_OE2 |
  2344. GRC_LCLCTRL_GPIO_OUTPUT0 |
  2345. GRC_LCLCTRL_GPIO_OUTPUT1),
  2346. TG3_GRC_LCLCTL_PWRSW_DELAY);
  2347. } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
  2348. tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
  2349. /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
  2350. u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
  2351. GRC_LCLCTRL_GPIO_OE1 |
  2352. GRC_LCLCTRL_GPIO_OE2 |
  2353. GRC_LCLCTRL_GPIO_OUTPUT0 |
  2354. GRC_LCLCTRL_GPIO_OUTPUT1 |
  2355. tp->grc_local_ctrl;
  2356. tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
  2357. TG3_GRC_LCLCTL_PWRSW_DELAY);
  2358. grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
  2359. tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
  2360. TG3_GRC_LCLCTL_PWRSW_DELAY);
  2361. grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
  2362. tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
  2363. TG3_GRC_LCLCTL_PWRSW_DELAY);
  2364. } else {
  2365. u32 no_gpio2;
  2366. u32 grc_local_ctrl = 0;
  2367. /* Workaround to prevent overdrawing Amps. */
  2368. if (tg3_asic_rev(tp) == ASIC_REV_5714) {
  2369. grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
  2370. tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
  2371. grc_local_ctrl,
  2372. TG3_GRC_LCLCTL_PWRSW_DELAY);
  2373. }
  2374. /* On 5753 and variants, GPIO2 cannot be used. */
  2375. no_gpio2 = tp->nic_sram_data_cfg &
  2376. NIC_SRAM_DATA_CFG_NO_GPIO2;
  2377. grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
  2378. GRC_LCLCTRL_GPIO_OE1 |
  2379. GRC_LCLCTRL_GPIO_OE2 |
  2380. GRC_LCLCTRL_GPIO_OUTPUT1 |
  2381. GRC_LCLCTRL_GPIO_OUTPUT2;
  2382. if (no_gpio2) {
  2383. grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
  2384. GRC_LCLCTRL_GPIO_OUTPUT2);
  2385. }
  2386. tw32_wait_f(GRC_LOCAL_CTRL,
  2387. tp->grc_local_ctrl | grc_local_ctrl,
  2388. TG3_GRC_LCLCTL_PWRSW_DELAY);
  2389. grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
  2390. tw32_wait_f(GRC_LOCAL_CTRL,
  2391. tp->grc_local_ctrl | grc_local_ctrl,
  2392. TG3_GRC_LCLCTL_PWRSW_DELAY);
  2393. if (!no_gpio2) {
  2394. grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
  2395. tw32_wait_f(GRC_LOCAL_CTRL,
  2396. tp->grc_local_ctrl | grc_local_ctrl,
  2397. TG3_GRC_LCLCTL_PWRSW_DELAY);
  2398. }
  2399. }
  2400. }
  2401. static void tg3_frob_aux_power_5717(struct tg3 *tp, bool wol_enable)
  2402. {
  2403. u32 msg = 0;
  2404. /* Serialize power state transitions */
  2405. if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
  2406. return;
  2407. if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE) || wol_enable)
  2408. msg = TG3_GPIO_MSG_NEED_VAUX;
  2409. msg = tg3_set_function_status(tp, msg);
  2410. if (msg & TG3_GPIO_MSG_ALL_DRVR_PRES_MASK)
  2411. goto done;
  2412. if (msg & TG3_GPIO_MSG_ALL_NEED_VAUX_MASK)
  2413. tg3_pwrsrc_switch_to_vaux(tp);
  2414. else
  2415. tg3_pwrsrc_die_with_vmain(tp);
  2416. done:
  2417. tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
  2418. }
  2419. static void tg3_frob_aux_power(struct tg3 *tp, bool include_wol)
  2420. {
  2421. bool need_vaux = false;
  2422. /* The GPIOs do something completely different on 57765. */
  2423. if (!tg3_flag(tp, IS_NIC) || tg3_flag(tp, 57765_CLASS))
  2424. return;
  2425. if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
  2426. tg3_asic_rev(tp) == ASIC_REV_5719 ||
  2427. tg3_asic_rev(tp) == ASIC_REV_5720) {
  2428. tg3_frob_aux_power_5717(tp, include_wol ?
  2429. tg3_flag(tp, WOL_ENABLE) != 0 : 0);
  2430. return;
  2431. }
  2432. if (tp->pdev_peer && tp->pdev_peer != tp->pdev) {
  2433. struct net_device *dev_peer;
  2434. dev_peer = pci_get_drvdata(tp->pdev_peer);
  2435. /* remove_one() may have been run on the peer. */
  2436. if (dev_peer) {
  2437. struct tg3 *tp_peer = netdev_priv(dev_peer);
  2438. if (tg3_flag(tp_peer, INIT_COMPLETE))
  2439. return;
  2440. if ((include_wol && tg3_flag(tp_peer, WOL_ENABLE)) ||
  2441. tg3_flag(tp_peer, ENABLE_ASF))
  2442. need_vaux = true;
  2443. }
  2444. }
  2445. if ((include_wol && tg3_flag(tp, WOL_ENABLE)) ||
  2446. tg3_flag(tp, ENABLE_ASF))
  2447. need_vaux = true;
  2448. if (need_vaux)
  2449. tg3_pwrsrc_switch_to_vaux(tp);
  2450. else
  2451. tg3_pwrsrc_die_with_vmain(tp);
  2452. }
  2453. static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
  2454. {
  2455. if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
  2456. return 1;
  2457. else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
  2458. if (speed != SPEED_10)
  2459. return 1;
  2460. } else if (speed == SPEED_10)
  2461. return 1;
  2462. return 0;
  2463. }
  2464. static bool tg3_phy_power_bug(struct tg3 *tp)
  2465. {
  2466. switch (tg3_asic_rev(tp)) {
  2467. case ASIC_REV_5700:
  2468. case ASIC_REV_5704:
  2469. return true;
  2470. case ASIC_REV_5780:
  2471. if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
  2472. return true;
  2473. return false;
  2474. case ASIC_REV_5717:
  2475. if (!tp->pci_fn)
  2476. return true;
  2477. return false;
  2478. case ASIC_REV_5719:
  2479. case ASIC_REV_5720:
  2480. if ((tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
  2481. !tp->pci_fn)
  2482. return true;
  2483. return false;
  2484. }
  2485. return false;
  2486. }
  2487. static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
  2488. {
  2489. u32 val;
  2490. if (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)
  2491. return;
  2492. if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
  2493. if (tg3_asic_rev(tp) == ASIC_REV_5704) {
  2494. u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
  2495. u32 serdes_cfg = tr32(MAC_SERDES_CFG);
  2496. sg_dig_ctrl |=
  2497. SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
  2498. tw32(SG_DIG_CTRL, sg_dig_ctrl);
  2499. tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
  2500. }
  2501. return;
  2502. }
  2503. if (tg3_asic_rev(tp) == ASIC_REV_5906) {
  2504. tg3_bmcr_reset(tp);
  2505. val = tr32(GRC_MISC_CFG);
  2506. tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
  2507. udelay(40);
  2508. return;
  2509. } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
  2510. u32 phytest;
  2511. if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
  2512. u32 phy;
  2513. tg3_writephy(tp, MII_ADVERTISE, 0);
  2514. tg3_writephy(tp, MII_BMCR,
  2515. BMCR_ANENABLE | BMCR_ANRESTART);
  2516. tg3_writephy(tp, MII_TG3_FET_TEST,
  2517. phytest | MII_TG3_FET_SHADOW_EN);
  2518. if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
  2519. phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
  2520. tg3_writephy(tp,
  2521. MII_TG3_FET_SHDW_AUXMODE4,
  2522. phy);
  2523. }
  2524. tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
  2525. }
  2526. return;
  2527. } else if (do_low_power) {
  2528. tg3_writephy(tp, MII_TG3_EXT_CTRL,
  2529. MII_TG3_EXT_CTRL_FORCE_LED_OFF);
  2530. val = MII_TG3_AUXCTL_PCTL_100TX_LPWR |
  2531. MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
  2532. MII_TG3_AUXCTL_PCTL_VREG_11V;
  2533. tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, val);
  2534. }
  2535. /* The PHY should not be powered down on some chips because
  2536. * of bugs.
  2537. */
  2538. if (tg3_phy_power_bug(tp))
  2539. return;
  2540. if (tg3_chip_rev(tp) == CHIPREV_5784_AX ||
  2541. tg3_chip_rev(tp) == CHIPREV_5761_AX) {
  2542. val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
  2543. val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
  2544. val |= CPMU_LSPD_1000MB_MACCLK_12_5;
  2545. tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
  2546. }
  2547. tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
  2548. }
  2549. /* tp->lock is held. */
  2550. static int tg3_nvram_lock(struct tg3 *tp)
  2551. {
  2552. if (tg3_flag(tp, NVRAM)) {
  2553. int i;
  2554. if (tp->nvram_lock_cnt == 0) {
  2555. tw32(NVRAM_SWARB, SWARB_REQ_SET1);
  2556. for (i = 0; i < 8000; i++) {
  2557. if (tr32(NVRAM_SWARB) & SWARB_GNT1)
  2558. break;
  2559. udelay(20);
  2560. }
  2561. if (i == 8000) {
  2562. tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
  2563. return -ENODEV;
  2564. }
  2565. }
  2566. tp->nvram_lock_cnt++;
  2567. }
  2568. return 0;
  2569. }
  2570. /* tp->lock is held. */
  2571. static void tg3_nvram_unlock(struct tg3 *tp)
  2572. {
  2573. if (tg3_flag(tp, NVRAM)) {
  2574. if (tp->nvram_lock_cnt > 0)
  2575. tp->nvram_lock_cnt--;
  2576. if (tp->nvram_lock_cnt == 0)
  2577. tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
  2578. }
  2579. }
  2580. /* tp->lock is held. */
  2581. static void tg3_enable_nvram_access(struct tg3 *tp)
  2582. {
  2583. if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
  2584. u32 nvaccess = tr32(NVRAM_ACCESS);
  2585. tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
  2586. }
  2587. }
  2588. /* tp->lock is held. */
  2589. static void tg3_disable_nvram_access(struct tg3 *tp)
  2590. {
  2591. if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
  2592. u32 nvaccess = tr32(NVRAM_ACCESS);
  2593. tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
  2594. }
  2595. }
  2596. static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
  2597. u32 offset, u32 *val)
  2598. {
  2599. u32 tmp;
  2600. int i;
  2601. if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
  2602. return -EINVAL;
  2603. tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
  2604. EEPROM_ADDR_DEVID_MASK |
  2605. EEPROM_ADDR_READ);
  2606. tw32(GRC_EEPROM_ADDR,
  2607. tmp |
  2608. (0 << EEPROM_ADDR_DEVID_SHIFT) |
  2609. ((offset << EEPROM_ADDR_ADDR_SHIFT) &
  2610. EEPROM_ADDR_ADDR_MASK) |
  2611. EEPROM_ADDR_READ | EEPROM_ADDR_START);
  2612. for (i = 0; i < 1000; i++) {
  2613. tmp = tr32(GRC_EEPROM_ADDR);
  2614. if (tmp & EEPROM_ADDR_COMPLETE)
  2615. break;
  2616. msleep(1);
  2617. }
  2618. if (!(tmp & EEPROM_ADDR_COMPLETE))
  2619. return -EBUSY;
  2620. tmp = tr32(GRC_EEPROM_DATA);
  2621. /*
  2622. * The data will always be opposite the native endian
  2623. * format. Perform a blind byteswap to compensate.
  2624. */
  2625. *val = swab32(tmp);
  2626. return 0;
  2627. }
  2628. #define NVRAM_CMD_TIMEOUT 10000
  2629. static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
  2630. {
  2631. int i;
  2632. tw32(NVRAM_CMD, nvram_cmd);
  2633. for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
  2634. udelay(10);
  2635. if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
  2636. udelay(10);
  2637. break;
  2638. }
  2639. }
  2640. if (i == NVRAM_CMD_TIMEOUT)
  2641. return -EBUSY;
  2642. return 0;
  2643. }
  2644. static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
  2645. {
  2646. if (tg3_flag(tp, NVRAM) &&
  2647. tg3_flag(tp, NVRAM_BUFFERED) &&
  2648. tg3_flag(tp, FLASH) &&
  2649. !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
  2650. (tp->nvram_jedecnum == JEDEC_ATMEL))
  2651. addr = ((addr / tp->nvram_pagesize) <<
  2652. ATMEL_AT45DB0X1B_PAGE_POS) +
  2653. (addr % tp->nvram_pagesize);
  2654. return addr;
  2655. }
  2656. static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
  2657. {
  2658. if (tg3_flag(tp, NVRAM) &&
  2659. tg3_flag(tp, NVRAM_BUFFERED) &&
  2660. tg3_flag(tp, FLASH) &&
  2661. !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
  2662. (tp->nvram_jedecnum == JEDEC_ATMEL))
  2663. addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
  2664. tp->nvram_pagesize) +
  2665. (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
  2666. return addr;
  2667. }
  2668. /* NOTE: Data read in from NVRAM is byteswapped according to
  2669. * the byteswapping settings for all other register accesses.
  2670. * tg3 devices are BE devices, so on a BE machine, the data
  2671. * returned will be exactly as it is seen in NVRAM. On a LE
  2672. * machine, the 32-bit value will be byteswapped.
  2673. */
  2674. static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
  2675. {
  2676. int ret;
  2677. if (!tg3_flag(tp, NVRAM))
  2678. return tg3_nvram_read_using_eeprom(tp, offset, val);
  2679. offset = tg3_nvram_phys_addr(tp, offset);
  2680. if (offset > NVRAM_ADDR_MSK)
  2681. return -EINVAL;
  2682. ret = tg3_nvram_lock(tp);
  2683. if (ret)
  2684. return ret;
  2685. tg3_enable_nvram_access(tp);
  2686. tw32(NVRAM_ADDR, offset);
  2687. ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
  2688. NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
  2689. if (ret == 0)
  2690. *val = tr32(NVRAM_RDDATA);
  2691. tg3_disable_nvram_access(tp);
  2692. tg3_nvram_unlock(tp);
  2693. return ret;
  2694. }
  2695. /* Ensures NVRAM data is in bytestream format. */
  2696. static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
  2697. {
  2698. u32 v;
  2699. int res = tg3_nvram_read(tp, offset, &v);
  2700. if (!res)
  2701. *val = cpu_to_be32(v);
  2702. return res;
  2703. }
  2704. static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
  2705. u32 offset, u32 len, u8 *buf)
  2706. {
  2707. int i, j, rc = 0;
  2708. u32 val;
  2709. for (i = 0; i < len; i += 4) {
  2710. u32 addr;
  2711. __be32 data;
  2712. addr = offset + i;
  2713. memcpy(&data, buf + i, 4);
  2714. /*
  2715. * The SEEPROM interface expects the data to always be opposite
  2716. * the native endian format. We accomplish this by reversing
  2717. * all the operations that would have been performed on the
  2718. * data from a call to tg3_nvram_read_be32().
  2719. */
  2720. tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
  2721. val = tr32(GRC_EEPROM_ADDR);
  2722. tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
  2723. val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
  2724. EEPROM_ADDR_READ);
  2725. tw32(GRC_EEPROM_ADDR, val |
  2726. (0 << EEPROM_ADDR_DEVID_SHIFT) |
  2727. (addr & EEPROM_ADDR_ADDR_MASK) |
  2728. EEPROM_ADDR_START |
  2729. EEPROM_ADDR_WRITE);
  2730. for (j = 0; j < 1000; j++) {
  2731. val = tr32(GRC_EEPROM_ADDR);
  2732. if (val & EEPROM_ADDR_COMPLETE)
  2733. break;
  2734. msleep(1);
  2735. }
  2736. if (!(val & EEPROM_ADDR_COMPLETE)) {
  2737. rc = -EBUSY;
  2738. break;
  2739. }
  2740. }
  2741. return rc;
  2742. }
  2743. /* offset and length are dword aligned */
  2744. static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
  2745. u8 *buf)
  2746. {
  2747. int ret = 0;
  2748. u32 pagesize = tp->nvram_pagesize;
  2749. u32 pagemask = pagesize - 1;
  2750. u32 nvram_cmd;
  2751. u8 *tmp;
  2752. tmp = kmalloc(pagesize, GFP_KERNEL);
  2753. if (tmp == NULL)
  2754. return -ENOMEM;
  2755. while (len) {
  2756. int j;
  2757. u32 phy_addr, page_off, size;
  2758. phy_addr = offset & ~pagemask;
  2759. for (j = 0; j < pagesize; j += 4) {
  2760. ret = tg3_nvram_read_be32(tp, phy_addr + j,
  2761. (__be32 *) (tmp + j));
  2762. if (ret)
  2763. break;
  2764. }
  2765. if (ret)
  2766. break;
  2767. page_off = offset & pagemask;
  2768. size = pagesize;
  2769. if (len < size)
  2770. size = len;
  2771. len -= size;
  2772. memcpy(tmp + page_off, buf, size);
  2773. offset = offset + (pagesize - page_off);
  2774. tg3_enable_nvram_access(tp);
  2775. /*
  2776. * Before we can erase the flash page, we need
  2777. * to issue a special "write enable" command.
  2778. */
  2779. nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
  2780. if (tg3_nvram_exec_cmd(tp, nvram_cmd))
  2781. break;
  2782. /* Erase the target page */
  2783. tw32(NVRAM_ADDR, phy_addr);
  2784. nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
  2785. NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
  2786. if (tg3_nvram_exec_cmd(tp, nvram_cmd))
  2787. break;
  2788. /* Issue another write enable to start the write. */
  2789. nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
  2790. if (tg3_nvram_exec_cmd(tp, nvram_cmd))
  2791. break;
  2792. for (j = 0; j < pagesize; j += 4) {
  2793. __be32 data;
  2794. data = *((__be32 *) (tmp + j));
  2795. tw32(NVRAM_WRDATA, be32_to_cpu(data));
  2796. tw32(NVRAM_ADDR, phy_addr + j);
  2797. nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
  2798. NVRAM_CMD_WR;
  2799. if (j == 0)
  2800. nvram_cmd |= NVRAM_CMD_FIRST;
  2801. else if (j == (pagesize - 4))
  2802. nvram_cmd |= NVRAM_CMD_LAST;
  2803. ret = tg3_nvram_exec_cmd(tp, nvram_cmd);
  2804. if (ret)
  2805. break;
  2806. }
  2807. if (ret)
  2808. break;
  2809. }
  2810. nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
  2811. tg3_nvram_exec_cmd(tp, nvram_cmd);
  2812. kfree(tmp);
  2813. return ret;
  2814. }
  2815. /* offset and length are dword aligned */
  2816. static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
  2817. u8 *buf)
  2818. {
  2819. int i, ret = 0;
  2820. for (i = 0; i < len; i += 4, offset += 4) {
  2821. u32 page_off, phy_addr, nvram_cmd;
  2822. __be32 data;
  2823. memcpy(&data, buf + i, 4);
  2824. tw32(NVRAM_WRDATA, be32_to_cpu(data));
  2825. page_off = offset % tp->nvram_pagesize;
  2826. phy_addr = tg3_nvram_phys_addr(tp, offset);
  2827. nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
  2828. if (page_off == 0 || i == 0)
  2829. nvram_cmd |= NVRAM_CMD_FIRST;
  2830. if (page_off == (tp->nvram_pagesize - 4))
  2831. nvram_cmd |= NVRAM_CMD_LAST;
  2832. if (i == (len - 4))
  2833. nvram_cmd |= NVRAM_CMD_LAST;
  2834. if ((nvram_cmd & NVRAM_CMD_FIRST) ||
  2835. !tg3_flag(tp, FLASH) ||
  2836. !tg3_flag(tp, 57765_PLUS))
  2837. tw32(NVRAM_ADDR, phy_addr);
  2838. if (tg3_asic_rev(tp) != ASIC_REV_5752 &&
  2839. !tg3_flag(tp, 5755_PLUS) &&
  2840. (tp->nvram_jedecnum == JEDEC_ST) &&
  2841. (nvram_cmd & NVRAM_CMD_FIRST)) {
  2842. u32 cmd;
  2843. cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
  2844. ret = tg3_nvram_exec_cmd(tp, cmd);
  2845. if (ret)
  2846. break;
  2847. }
  2848. if (!tg3_flag(tp, FLASH)) {
  2849. /* We always do complete word writes to eeprom. */
  2850. nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
  2851. }
  2852. ret = tg3_nvram_exec_cmd(tp, nvram_cmd);
  2853. if (ret)
  2854. break;
  2855. }
  2856. return ret;
  2857. }
  2858. /* offset and length are dword aligned */
  2859. static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
  2860. {
  2861. int ret;
  2862. if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
  2863. tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
  2864. ~GRC_LCLCTRL_GPIO_OUTPUT1);
  2865. udelay(40);
  2866. }
  2867. if (!tg3_flag(tp, NVRAM)) {
  2868. ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
  2869. } else {
  2870. u32 grc_mode;
  2871. ret = tg3_nvram_lock(tp);
  2872. if (ret)
  2873. return ret;
  2874. tg3_enable_nvram_access(tp);
  2875. if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM))
  2876. tw32(NVRAM_WRITE1, 0x406);
  2877. grc_mode = tr32(GRC_MODE);
  2878. tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
  2879. if (tg3_flag(tp, NVRAM_BUFFERED) || !tg3_flag(tp, FLASH)) {
  2880. ret = tg3_nvram_write_block_buffered(tp, offset, len,
  2881. buf);
  2882. } else {
  2883. ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
  2884. buf);
  2885. }
  2886. grc_mode = tr32(GRC_MODE);
  2887. tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
  2888. tg3_disable_nvram_access(tp);
  2889. tg3_nvram_unlock(tp);
  2890. }
  2891. if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
  2892. tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
  2893. udelay(40);
  2894. }
  2895. return ret;
  2896. }
  2897. #define RX_CPU_SCRATCH_BASE 0x30000
  2898. #define RX_CPU_SCRATCH_SIZE 0x04000
  2899. #define TX_CPU_SCRATCH_BASE 0x34000
  2900. #define TX_CPU_SCRATCH_SIZE 0x04000
  2901. /* tp->lock is held. */
  2902. static int tg3_pause_cpu(struct tg3 *tp, u32 cpu_base)
  2903. {
  2904. int i;
  2905. const int iters = 10000;
  2906. for (i = 0; i < iters; i++) {
  2907. tw32(cpu_base + CPU_STATE, 0xffffffff);
  2908. tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
  2909. if (tr32(cpu_base + CPU_MODE) & CPU_MODE_HALT)
  2910. break;
  2911. if (pci_channel_offline(tp->pdev))
  2912. return -EBUSY;
  2913. }
  2914. return (i == iters) ? -EBUSY : 0;
  2915. }
  2916. /* tp->lock is held. */
  2917. static int tg3_rxcpu_pause(struct tg3 *tp)
  2918. {
  2919. int rc = tg3_pause_cpu(tp, RX_CPU_BASE);
  2920. tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
  2921. tw32_f(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
  2922. udelay(10);
  2923. return rc;
  2924. }
  2925. /* tp->lock is held. */
  2926. static int tg3_txcpu_pause(struct tg3 *tp)
  2927. {
  2928. return tg3_pause_cpu(tp, TX_CPU_BASE);
  2929. }
  2930. /* tp->lock is held. */
  2931. static void tg3_resume_cpu(struct tg3 *tp, u32 cpu_base)
  2932. {
  2933. tw32(cpu_base + CPU_STATE, 0xffffffff);
  2934. tw32_f(cpu_base + CPU_MODE, 0x00000000);
  2935. }
  2936. /* tp->lock is held. */
  2937. static void tg3_rxcpu_resume(struct tg3 *tp)
  2938. {
  2939. tg3_resume_cpu(tp, RX_CPU_BASE);
  2940. }
  2941. /* tp->lock is held. */
  2942. static int tg3_halt_cpu(struct tg3 *tp, u32 cpu_base)
  2943. {
  2944. int rc;
  2945. BUG_ON(cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS));
  2946. if (tg3_asic_rev(tp) == ASIC_REV_5906) {
  2947. u32 val = tr32(GRC_VCPU_EXT_CTRL);
  2948. tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
  2949. return 0;
  2950. }
  2951. if (cpu_base == RX_CPU_BASE) {
  2952. rc = tg3_rxcpu_pause(tp);
  2953. } else {
  2954. /*
  2955. * There is only an Rx CPU for the 5750 derivative in the
  2956. * BCM4785.
  2957. */
  2958. if (tg3_flag(tp, IS_SSB_CORE))
  2959. return 0;
  2960. rc = tg3_txcpu_pause(tp);
  2961. }
  2962. if (rc) {
  2963. netdev_err(tp->dev, "%s timed out, %s CPU\n",
  2964. __func__, cpu_base == RX_CPU_BASE ? "RX" : "TX");
  2965. return -ENODEV;
  2966. }
  2967. /* Clear firmware's nvram arbitration. */
  2968. if (tg3_flag(tp, NVRAM))
  2969. tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
  2970. return 0;
  2971. }
  2972. static int tg3_fw_data_len(struct tg3 *tp,
  2973. const struct tg3_firmware_hdr *fw_hdr)
  2974. {
  2975. int fw_len;
  2976. /* Non fragmented firmware have one firmware header followed by a
  2977. * contiguous chunk of data to be written. The length field in that
  2978. * header is not the length of data to be written but the complete
  2979. * length of the bss. The data length is determined based on
  2980. * tp->fw->size minus headers.
  2981. *
  2982. * Fragmented firmware have a main header followed by multiple
  2983. * fragments. Each fragment is identical to non fragmented firmware
  2984. * with a firmware header followed by a contiguous chunk of data. In
  2985. * the main header, the length field is unused and set to 0xffffffff.
  2986. * In each fragment header the length is the entire size of that
  2987. * fragment i.e. fragment data + header length. Data length is
  2988. * therefore length field in the header minus TG3_FW_HDR_LEN.
  2989. */
  2990. if (tp->fw_len == 0xffffffff)
  2991. fw_len = be32_to_cpu(fw_hdr->len);
  2992. else
  2993. fw_len = tp->fw->size;
  2994. return (fw_len - TG3_FW_HDR_LEN) / sizeof(u32);
  2995. }
  2996. /* tp->lock is held. */
  2997. static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base,
  2998. u32 cpu_scratch_base, int cpu_scratch_size,
  2999. const struct tg3_firmware_hdr *fw_hdr)
  3000. {
  3001. int err, i;
  3002. void (*write_op)(struct tg3 *, u32, u32);
  3003. int total_len = tp->fw->size;
  3004. if (cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS)) {
  3005. netdev_err(tp->dev,
  3006. "%s: Trying to load TX cpu firmware which is 5705\n",
  3007. __func__);
  3008. return -EINVAL;
  3009. }
  3010. if (tg3_flag(tp, 5705_PLUS) && tg3_asic_rev(tp) != ASIC_REV_57766)
  3011. write_op = tg3_write_mem;
  3012. else
  3013. write_op = tg3_write_indirect_reg32;
  3014. if (tg3_asic_rev(tp) != ASIC_REV_57766) {
  3015. /* It is possible that bootcode is still loading at this point.
  3016. * Get the nvram lock first before halting the cpu.
  3017. */
  3018. int lock_err = tg3_nvram_lock(tp);
  3019. err = tg3_halt_cpu(tp, cpu_base);
  3020. if (!lock_err)
  3021. tg3_nvram_unlock(tp);
  3022. if (err)
  3023. goto out;
  3024. for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
  3025. write_op(tp, cpu_scratch_base + i, 0);
  3026. tw32(cpu_base + CPU_STATE, 0xffffffff);
  3027. tw32(cpu_base + CPU_MODE,
  3028. tr32(cpu_base + CPU_MODE) | CPU_MODE_HALT);
  3029. } else {
  3030. /* Subtract additional main header for fragmented firmware and
  3031. * advance to the first fragment
  3032. */
  3033. total_len -= TG3_FW_HDR_LEN;
  3034. fw_hdr++;
  3035. }
  3036. do {
  3037. u32 *fw_data = (u32 *)(fw_hdr + 1);
  3038. for (i = 0; i < tg3_fw_data_len(tp, fw_hdr); i++)
  3039. write_op(tp, cpu_scratch_base +
  3040. (be32_to_cpu(fw_hdr->base_addr) & 0xffff) +
  3041. (i * sizeof(u32)),
  3042. be32_to_cpu(fw_data[i]));
  3043. total_len -= be32_to_cpu(fw_hdr->len);
  3044. /* Advance to next fragment */
  3045. fw_hdr = (struct tg3_firmware_hdr *)
  3046. ((void *)fw_hdr + be32_to_cpu(fw_hdr->len));
  3047. } while (total_len > 0);
  3048. err = 0;
  3049. out:
  3050. return err;
  3051. }
  3052. /* tp->lock is held. */
  3053. static int tg3_pause_cpu_and_set_pc(struct tg3 *tp, u32 cpu_base, u32 pc)
  3054. {
  3055. int i;
  3056. const int iters = 5;
  3057. tw32(cpu_base + CPU_STATE, 0xffffffff);
  3058. tw32_f(cpu_base + CPU_PC, pc);
  3059. for (i = 0; i < iters; i++) {
  3060. if (tr32(cpu_base + CPU_PC) == pc)
  3061. break;
  3062. tw32(cpu_base + CPU_STATE, 0xffffffff);
  3063. tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
  3064. tw32_f(cpu_base + CPU_PC, pc);
  3065. udelay(1000);
  3066. }
  3067. return (i == iters) ? -EBUSY : 0;
  3068. }
  3069. /* tp->lock is held. */
  3070. static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
  3071. {
  3072. const struct tg3_firmware_hdr *fw_hdr;
  3073. int err;
  3074. fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
  3075. /* Firmware blob starts with version numbers, followed by
  3076. start address and length. We are setting complete length.
  3077. length = end_address_of_bss - start_address_of_text.
  3078. Remainder is the blob to be loaded contiguously
  3079. from start address. */
  3080. err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
  3081. RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
  3082. fw_hdr);
  3083. if (err)
  3084. return err;
  3085. err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
  3086. TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
  3087. fw_hdr);
  3088. if (err)
  3089. return err;
  3090. /* Now startup only the RX cpu. */
  3091. err = tg3_pause_cpu_and_set_pc(tp, RX_CPU_BASE,
  3092. be32_to_cpu(fw_hdr->base_addr));
  3093. if (err) {
  3094. netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x "
  3095. "should be %08x\n", __func__,
  3096. tr32(RX_CPU_BASE + CPU_PC),
  3097. be32_to_cpu(fw_hdr->base_addr));
  3098. return -ENODEV;
  3099. }
  3100. tg3_rxcpu_resume(tp);
  3101. return 0;
  3102. }
  3103. static int tg3_validate_rxcpu_state(struct tg3 *tp)
  3104. {
  3105. const int iters = 1000;
  3106. int i;
  3107. u32 val;
  3108. /* Wait for boot code to complete initialization and enter service
  3109. * loop. It is then safe to download service patches
  3110. */
  3111. for (i = 0; i < iters; i++) {
  3112. if (tr32(RX_CPU_HWBKPT) == TG3_SBROM_IN_SERVICE_LOOP)
  3113. break;
  3114. udelay(10);
  3115. }
  3116. if (i == iters) {
  3117. netdev_err(tp->dev, "Boot code not ready for service patches\n");
  3118. return -EBUSY;
  3119. }
  3120. val = tg3_read_indirect_reg32(tp, TG3_57766_FW_HANDSHAKE);
  3121. if (val & 0xff) {
  3122. netdev_warn(tp->dev,
  3123. "Other patches exist. Not downloading EEE patch\n");
  3124. return -EEXIST;
  3125. }
  3126. return 0;
  3127. }
  3128. /* tp->lock is held. */
  3129. static void tg3_load_57766_firmware(struct tg3 *tp)
  3130. {
  3131. struct tg3_firmware_hdr *fw_hdr;
  3132. if (!tg3_flag(tp, NO_NVRAM))
  3133. return;
  3134. if (tg3_validate_rxcpu_state(tp))
  3135. return;
  3136. if (!tp->fw)
  3137. return;
  3138. /* This firmware blob has a different format than older firmware
  3139. * releases as given below. The main difference is we have fragmented
  3140. * data to be written to non-contiguous locations.
  3141. *
  3142. * In the beginning we have a firmware header identical to other
  3143. * firmware which consists of version, base addr and length. The length
  3144. * here is unused and set to 0xffffffff.
  3145. *
  3146. * This is followed by a series of firmware fragments which are
  3147. * individually identical to previous firmware. i.e. they have the
  3148. * firmware header and followed by data for that fragment. The version
  3149. * field of the individual fragment header is unused.
  3150. */
  3151. fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
  3152. if (be32_to_cpu(fw_hdr->base_addr) != TG3_57766_FW_BASE_ADDR)
  3153. return;
  3154. if (tg3_rxcpu_pause(tp))
  3155. return;
  3156. /* tg3_load_firmware_cpu() will always succeed for the 57766 */
  3157. tg3_load_firmware_cpu(tp, 0, TG3_57766_FW_BASE_ADDR, 0, fw_hdr);
  3158. tg3_rxcpu_resume(tp);
  3159. }
  3160. /* tp->lock is held. */
  3161. static int tg3_load_tso_firmware(struct tg3 *tp)
  3162. {
  3163. const struct tg3_firmware_hdr *fw_hdr;
  3164. unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
  3165. int err;
  3166. if (!tg3_flag(tp, FW_TSO))
  3167. return 0;
  3168. fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
  3169. /* Firmware blob starts with version numbers, followed by
  3170. start address and length. We are setting complete length.
  3171. length = end_address_of_bss - start_address_of_text.
  3172. Remainder is the blob to be loaded contiguously
  3173. from start address. */
  3174. cpu_scratch_size = tp->fw_len;
  3175. if (tg3_asic_rev(tp) == ASIC_REV_5705) {
  3176. cpu_base = RX_CPU_BASE;
  3177. cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
  3178. } else {
  3179. cpu_base = TX_CPU_BASE;
  3180. cpu_scratch_base = TX_CPU_SCRATCH_BASE;
  3181. cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
  3182. }
  3183. err = tg3_load_firmware_cpu(tp, cpu_base,
  3184. cpu_scratch_base, cpu_scratch_size,
  3185. fw_hdr);
  3186. if (err)
  3187. return err;
  3188. /* Now startup the cpu. */
  3189. err = tg3_pause_cpu_and_set_pc(tp, cpu_base,
  3190. be32_to_cpu(fw_hdr->base_addr));
  3191. if (err) {
  3192. netdev_err(tp->dev,
  3193. "%s fails to set CPU PC, is %08x should be %08x\n",
  3194. __func__, tr32(cpu_base + CPU_PC),
  3195. be32_to_cpu(fw_hdr->base_addr));
  3196. return -ENODEV;
  3197. }
  3198. tg3_resume_cpu(tp, cpu_base);
  3199. return 0;
  3200. }
  3201. /* tp->lock is held. */
  3202. static void __tg3_set_mac_addr(struct tg3 *tp, bool skip_mac_1)
  3203. {
  3204. u32 addr_high, addr_low;
  3205. int i;
  3206. addr_high = ((tp->dev->dev_addr[0] << 8) |
  3207. tp->dev->dev_addr[1]);
  3208. addr_low = ((tp->dev->dev_addr[2] << 24) |
  3209. (tp->dev->dev_addr[3] << 16) |
  3210. (tp->dev->dev_addr[4] << 8) |
  3211. (tp->dev->dev_addr[5] << 0));
  3212. for (i = 0; i < 4; i++) {
  3213. if (i == 1 && skip_mac_1)
  3214. continue;
  3215. tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
  3216. tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
  3217. }
  3218. if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
  3219. tg3_asic_rev(tp) == ASIC_REV_5704) {
  3220. for (i = 0; i < 12; i++) {
  3221. tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
  3222. tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
  3223. }
  3224. }
  3225. addr_high = (tp->dev->dev_addr[0] +
  3226. tp->dev->dev_addr[1] +
  3227. tp->dev->dev_addr[2] +
  3228. tp->dev->dev_addr[3] +
  3229. tp->dev->dev_addr[4] +
  3230. tp->dev->dev_addr[5]) &
  3231. TX_BACKOFF_SEED_MASK;
  3232. tw32(MAC_TX_BACKOFF_SEED, addr_high);
  3233. }
  3234. static void tg3_enable_register_access(struct tg3 *tp)
  3235. {
  3236. /*
  3237. * Make sure register accesses (indirect or otherwise) will function
  3238. * correctly.
  3239. */
  3240. pci_write_config_dword(tp->pdev,
  3241. TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl);
  3242. }
  3243. static int tg3_power_up(struct tg3 *tp)
  3244. {
  3245. int err;
  3246. tg3_enable_register_access(tp);
  3247. err = pci_set_power_state(tp->pdev, PCI_D0);
  3248. if (!err) {
  3249. /* Switch out of Vaux if it is a NIC */
  3250. tg3_pwrsrc_switch_to_vmain(tp);
  3251. } else {
  3252. netdev_err(tp->dev, "Transition to D0 failed\n");
  3253. }
  3254. return err;
  3255. }
  3256. static int tg3_setup_phy(struct tg3 *, bool);
  3257. static int tg3_power_down_prepare(struct tg3 *tp)
  3258. {
  3259. u32 misc_host_ctrl;
  3260. bool device_should_wake, do_low_power;
  3261. tg3_enable_register_access(tp);
  3262. /* Restore the CLKREQ setting. */
  3263. if (tg3_flag(tp, CLKREQ_BUG))
  3264. pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL,
  3265. PCI_EXP_LNKCTL_CLKREQ_EN);
  3266. misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
  3267. tw32(TG3PCI_MISC_HOST_CTRL,
  3268. misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
  3269. device_should_wake = device_may_wakeup(&tp->pdev->dev) &&
  3270. tg3_flag(tp, WOL_ENABLE);
  3271. if (tg3_flag(tp, USE_PHYLIB)) {
  3272. do_low_power = false;
  3273. if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) &&
  3274. !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
  3275. struct phy_device *phydev;
  3276. u32 phyid, advertising;
  3277. phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
  3278. tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
  3279. tp->link_config.speed = phydev->speed;
  3280. tp->link_config.duplex = phydev->duplex;
  3281. tp->link_config.autoneg = phydev->autoneg;
  3282. tp->link_config.advertising = phydev->advertising;
  3283. advertising = ADVERTISED_TP |
  3284. ADVERTISED_Pause |
  3285. ADVERTISED_Autoneg |
  3286. ADVERTISED_10baseT_Half;
  3287. if (tg3_flag(tp, ENABLE_ASF) || device_should_wake) {
  3288. if (tg3_flag(tp, WOL_SPEED_100MB))
  3289. advertising |=
  3290. ADVERTISED_100baseT_Half |
  3291. ADVERTISED_100baseT_Full |
  3292. ADVERTISED_10baseT_Full;
  3293. else
  3294. advertising |= ADVERTISED_10baseT_Full;
  3295. }
  3296. phydev->advertising = advertising;
  3297. phy_start_aneg(phydev);
  3298. phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
  3299. if (phyid != PHY_ID_BCMAC131) {
  3300. phyid &= PHY_BCM_OUI_MASK;
  3301. if (phyid == PHY_BCM_OUI_1 ||
  3302. phyid == PHY_BCM_OUI_2 ||
  3303. phyid == PHY_BCM_OUI_3)
  3304. do_low_power = true;
  3305. }
  3306. }
  3307. } else {
  3308. do_low_power = true;
  3309. if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER))
  3310. tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
  3311. if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
  3312. tg3_setup_phy(tp, false);
  3313. }
  3314. if (tg3_asic_rev(tp) == ASIC_REV_5906) {
  3315. u32 val;
  3316. val = tr32(GRC_VCPU_EXT_CTRL);
  3317. tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
  3318. } else if (!tg3_flag(tp, ENABLE_ASF)) {
  3319. int i;
  3320. u32 val;
  3321. for (i = 0; i < 200; i++) {
  3322. tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
  3323. if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
  3324. break;
  3325. msleep(1);
  3326. }
  3327. }
  3328. if (tg3_flag(tp, WOL_CAP))
  3329. tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
  3330. WOL_DRV_STATE_SHUTDOWN |
  3331. WOL_DRV_WOL |
  3332. WOL_SET_MAGIC_PKT);
  3333. if (device_should_wake) {
  3334. u32 mac_mode;
  3335. if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
  3336. if (do_low_power &&
  3337. !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
  3338. tg3_phy_auxctl_write(tp,
  3339. MII_TG3_AUXCTL_SHDWSEL_PWRCTL,
  3340. MII_TG3_AUXCTL_PCTL_WOL_EN |
  3341. MII_TG3_AUXCTL_PCTL_100TX_LPWR |
  3342. MII_TG3_AUXCTL_PCTL_CL_AB_TXDAC);
  3343. udelay(40);
  3344. }
  3345. if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
  3346. mac_mode = MAC_MODE_PORT_MODE_GMII;
  3347. else if (tp->phy_flags &
  3348. TG3_PHYFLG_KEEP_LINK_ON_PWRDN) {
  3349. if (tp->link_config.active_speed == SPEED_1000)
  3350. mac_mode = MAC_MODE_PORT_MODE_GMII;
  3351. else
  3352. mac_mode = MAC_MODE_PORT_MODE_MII;
  3353. } else
  3354. mac_mode = MAC_MODE_PORT_MODE_MII;
  3355. mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
  3356. if (tg3_asic_rev(tp) == ASIC_REV_5700) {
  3357. u32 speed = tg3_flag(tp, WOL_SPEED_100MB) ?
  3358. SPEED_100 : SPEED_10;
  3359. if (tg3_5700_link_polarity(tp, speed))
  3360. mac_mode |= MAC_MODE_LINK_POLARITY;
  3361. else
  3362. mac_mode &= ~MAC_MODE_LINK_POLARITY;
  3363. }
  3364. } else {
  3365. mac_mode = MAC_MODE_PORT_MODE_TBI;
  3366. }
  3367. if (!tg3_flag(tp, 5750_PLUS))
  3368. tw32(MAC_LED_CTRL, tp->led_ctrl);
  3369. mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
  3370. if ((tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS)) &&
  3371. (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)))
  3372. mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
  3373. if (tg3_flag(tp, ENABLE_APE))
  3374. mac_mode |= MAC_MODE_APE_TX_EN |
  3375. MAC_MODE_APE_RX_EN |
  3376. MAC_MODE_TDE_ENABLE;
  3377. tw32_f(MAC_MODE, mac_mode);
  3378. udelay(100);
  3379. tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
  3380. udelay(10);
  3381. }
  3382. if (!tg3_flag(tp, WOL_SPEED_100MB) &&
  3383. (tg3_asic_rev(tp) == ASIC_REV_5700 ||
  3384. tg3_asic_rev(tp) == ASIC_REV_5701)) {
  3385. u32 base_val;
  3386. base_val = tp->pci_clock_ctrl;
  3387. base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
  3388. CLOCK_CTRL_TXCLK_DISABLE);
  3389. tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
  3390. CLOCK_CTRL_PWRDOWN_PLL133, 40);
  3391. } else if (tg3_flag(tp, 5780_CLASS) ||
  3392. tg3_flag(tp, CPMU_PRESENT) ||
  3393. tg3_asic_rev(tp) == ASIC_REV_5906) {
  3394. /* do nothing */
  3395. } else if (!(tg3_flag(tp, 5750_PLUS) && tg3_flag(tp, ENABLE_ASF))) {
  3396. u32 newbits1, newbits2;
  3397. if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
  3398. tg3_asic_rev(tp) == ASIC_REV_5701) {
  3399. newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
  3400. CLOCK_CTRL_TXCLK_DISABLE |
  3401. CLOCK_CTRL_ALTCLK);
  3402. newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
  3403. } else if (tg3_flag(tp, 5705_PLUS)) {
  3404. newbits1 = CLOCK_CTRL_625_CORE;
  3405. newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
  3406. } else {
  3407. newbits1 = CLOCK_CTRL_ALTCLK;
  3408. newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
  3409. }
  3410. tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
  3411. 40);
  3412. tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
  3413. 40);
  3414. if (!tg3_flag(tp, 5705_PLUS)) {
  3415. u32 newbits3;
  3416. if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
  3417. tg3_asic_rev(tp) == ASIC_REV_5701) {
  3418. newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
  3419. CLOCK_CTRL_TXCLK_DISABLE |
  3420. CLOCK_CTRL_44MHZ_CORE);
  3421. } else {
  3422. newbits3 = CLOCK_CTRL_44MHZ_CORE;
  3423. }
  3424. tw32_wait_f(TG3PCI_CLOCK_CTRL,
  3425. tp->pci_clock_ctrl | newbits3, 40);
  3426. }
  3427. }
  3428. if (!(device_should_wake) && !tg3_flag(tp, ENABLE_ASF))
  3429. tg3_power_down_phy(tp, do_low_power);
  3430. tg3_frob_aux_power(tp, true);
  3431. /* Workaround for unstable PLL clock */
  3432. if ((!tg3_flag(tp, IS_SSB_CORE)) &&
  3433. ((tg3_chip_rev(tp) == CHIPREV_5750_AX) ||
  3434. (tg3_chip_rev(tp) == CHIPREV_5750_BX))) {
  3435. u32 val = tr32(0x7d00);
  3436. val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
  3437. tw32(0x7d00, val);
  3438. if (!tg3_flag(tp, ENABLE_ASF)) {
  3439. int err;
  3440. err = tg3_nvram_lock(tp);
  3441. tg3_halt_cpu(tp, RX_CPU_BASE);
  3442. if (!err)
  3443. tg3_nvram_unlock(tp);
  3444. }
  3445. }
  3446. tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
  3447. tg3_ape_driver_state_change(tp, RESET_KIND_SHUTDOWN);
  3448. return 0;
  3449. }
  3450. static void tg3_power_down(struct tg3 *tp)
  3451. {
  3452. pci_wake_from_d3(tp->pdev, tg3_flag(tp, WOL_ENABLE));
  3453. pci_set_power_state(tp->pdev, PCI_D3hot);
  3454. }
  3455. static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
  3456. {
  3457. switch (val & MII_TG3_AUX_STAT_SPDMASK) {
  3458. case MII_TG3_AUX_STAT_10HALF:
  3459. *speed = SPEED_10;
  3460. *duplex = DUPLEX_HALF;
  3461. break;
  3462. case MII_TG3_AUX_STAT_10FULL:
  3463. *speed = SPEED_10;
  3464. *duplex = DUPLEX_FULL;
  3465. break;
  3466. case MII_TG3_AUX_STAT_100HALF:
  3467. *speed = SPEED_100;
  3468. *duplex = DUPLEX_HALF;
  3469. break;
  3470. case MII_TG3_AUX_STAT_100FULL:
  3471. *speed = SPEED_100;
  3472. *duplex = DUPLEX_FULL;
  3473. break;
  3474. case MII_TG3_AUX_STAT_1000HALF:
  3475. *speed = SPEED_1000;
  3476. *duplex = DUPLEX_HALF;
  3477. break;
  3478. case MII_TG3_AUX_STAT_1000FULL:
  3479. *speed = SPEED_1000;
  3480. *duplex = DUPLEX_FULL;
  3481. break;
  3482. default:
  3483. if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
  3484. *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
  3485. SPEED_10;
  3486. *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
  3487. DUPLEX_HALF;
  3488. break;
  3489. }
  3490. *speed = SPEED_UNKNOWN;
  3491. *duplex = DUPLEX_UNKNOWN;
  3492. break;
  3493. }
  3494. }
  3495. static int tg3_phy_autoneg_cfg(struct tg3 *tp, u32 advertise, u32 flowctrl)
  3496. {
  3497. int err = 0;
  3498. u32 val, new_adv;
  3499. new_adv = ADVERTISE_CSMA;
  3500. new_adv |= ethtool_adv_to_mii_adv_t(advertise) & ADVERTISE_ALL;
  3501. new_adv |= mii_advertise_flowctrl(flowctrl);
  3502. err = tg3_writephy(tp, MII_ADVERTISE, new_adv);
  3503. if (err)
  3504. goto done;
  3505. if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
  3506. new_adv = ethtool_adv_to_mii_ctrl1000_t(advertise);
  3507. if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
  3508. tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0)
  3509. new_adv |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER;
  3510. err = tg3_writephy(tp, MII_CTRL1000, new_adv);
  3511. if (err)
  3512. goto done;
  3513. }
  3514. if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
  3515. goto done;
  3516. tw32(TG3_CPMU_EEE_MODE,
  3517. tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE);
  3518. err = tg3_phy_toggle_auxctl_smdsp(tp, true);
  3519. if (!err) {
  3520. u32 err2;
  3521. val = 0;
  3522. /* Advertise 100-BaseTX EEE ability */
  3523. if (advertise & ADVERTISED_100baseT_Full)
  3524. val |= MDIO_AN_EEE_ADV_100TX;
  3525. /* Advertise 1000-BaseT EEE ability */
  3526. if (advertise & ADVERTISED_1000baseT_Full)
  3527. val |= MDIO_AN_EEE_ADV_1000T;
  3528. if (!tp->eee.eee_enabled) {
  3529. val = 0;
  3530. tp->eee.advertised = 0;
  3531. } else {
  3532. tp->eee.advertised = advertise &
  3533. (ADVERTISED_100baseT_Full |
  3534. ADVERTISED_1000baseT_Full);
  3535. }
  3536. err = tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
  3537. if (err)
  3538. val = 0;
  3539. switch (tg3_asic_rev(tp)) {
  3540. case ASIC_REV_5717:
  3541. case ASIC_REV_57765:
  3542. case ASIC_REV_57766:
  3543. case ASIC_REV_5719:
  3544. /* If we advertised any eee advertisements above... */
  3545. if (val)
  3546. val = MII_TG3_DSP_TAP26_ALNOKO |
  3547. MII_TG3_DSP_TAP26_RMRXSTO |
  3548. MII_TG3_DSP_TAP26_OPCSINPT;
  3549. tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
  3550. /* Fall through */
  3551. case ASIC_REV_5720:
  3552. case ASIC_REV_5762:
  3553. if (!tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val))
  3554. tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2, val |
  3555. MII_TG3_DSP_CH34TP2_HIBW01);
  3556. }
  3557. err2 = tg3_phy_toggle_auxctl_smdsp(tp, false);
  3558. if (!err)
  3559. err = err2;
  3560. }
  3561. done:
  3562. return err;
  3563. }
  3564. static void tg3_phy_copper_begin(struct tg3 *tp)
  3565. {
  3566. if (tp->link_config.autoneg == AUTONEG_ENABLE ||
  3567. (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
  3568. u32 adv, fc;
  3569. if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) &&
  3570. !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)) {
  3571. adv = ADVERTISED_10baseT_Half |
  3572. ADVERTISED_10baseT_Full;
  3573. if (tg3_flag(tp, WOL_SPEED_100MB))
  3574. adv |= ADVERTISED_100baseT_Half |
  3575. ADVERTISED_100baseT_Full;
  3576. if (tp->phy_flags & TG3_PHYFLG_1G_ON_VAUX_OK)
  3577. adv |= ADVERTISED_1000baseT_Half |
  3578. ADVERTISED_1000baseT_Full;
  3579. fc = FLOW_CTRL_TX | FLOW_CTRL_RX;
  3580. } else {
  3581. adv = tp->link_config.advertising;
  3582. if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
  3583. adv &= ~(ADVERTISED_1000baseT_Half |
  3584. ADVERTISED_1000baseT_Full);
  3585. fc = tp->link_config.flowctrl;
  3586. }
  3587. tg3_phy_autoneg_cfg(tp, adv, fc);
  3588. if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) &&
  3589. (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)) {
  3590. /* Normally during power down we want to autonegotiate
  3591. * the lowest possible speed for WOL. However, to avoid
  3592. * link flap, we leave it untouched.
  3593. */
  3594. return;
  3595. }
  3596. tg3_writephy(tp, MII_BMCR,
  3597. BMCR_ANENABLE | BMCR_ANRESTART);
  3598. } else {
  3599. int i;
  3600. u32 bmcr, orig_bmcr;
  3601. tp->link_config.active_speed = tp->link_config.speed;
  3602. tp->link_config.active_duplex = tp->link_config.duplex;
  3603. if (tg3_asic_rev(tp) == ASIC_REV_5714) {
  3604. /* With autoneg disabled, 5715 only links up when the
  3605. * advertisement register has the configured speed
  3606. * enabled.
  3607. */
  3608. tg3_writephy(tp, MII_ADVERTISE, ADVERTISE_ALL);
  3609. }
  3610. bmcr = 0;
  3611. switch (tp->link_config.speed) {
  3612. default:
  3613. case SPEED_10:
  3614. break;
  3615. case SPEED_100:
  3616. bmcr |= BMCR_SPEED100;
  3617. break;
  3618. case SPEED_1000:
  3619. bmcr |= BMCR_SPEED1000;
  3620. break;
  3621. }
  3622. if (tp->link_config.duplex == DUPLEX_FULL)
  3623. bmcr |= BMCR_FULLDPLX;
  3624. if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
  3625. (bmcr != orig_bmcr)) {
  3626. tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
  3627. for (i = 0; i < 1500; i++) {
  3628. u32 tmp;
  3629. udelay(10);
  3630. if (tg3_readphy(tp, MII_BMSR, &tmp) ||
  3631. tg3_readphy(tp, MII_BMSR, &tmp))
  3632. continue;
  3633. if (!(tmp & BMSR_LSTATUS)) {
  3634. udelay(40);
  3635. break;
  3636. }
  3637. }
  3638. tg3_writephy(tp, MII_BMCR, bmcr);
  3639. udelay(40);
  3640. }
  3641. }
  3642. }
  3643. static int tg3_phy_pull_config(struct tg3 *tp)
  3644. {
  3645. int err;
  3646. u32 val;
  3647. err = tg3_readphy(tp, MII_BMCR, &val);
  3648. if (err)
  3649. goto done;
  3650. if (!(val & BMCR_ANENABLE)) {
  3651. tp->link_config.autoneg = AUTONEG_DISABLE;
  3652. tp->link_config.advertising = 0;
  3653. tg3_flag_clear(tp, PAUSE_AUTONEG);
  3654. err = -EIO;
  3655. switch (val & (BMCR_SPEED1000 | BMCR_SPEED100)) {
  3656. case 0:
  3657. if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
  3658. goto done;
  3659. tp->link_config.speed = SPEED_10;
  3660. break;
  3661. case BMCR_SPEED100:
  3662. if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
  3663. goto done;
  3664. tp->link_config.speed = SPEED_100;
  3665. break;
  3666. case BMCR_SPEED1000:
  3667. if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
  3668. tp->link_config.speed = SPEED_1000;
  3669. break;
  3670. }
  3671. /* Fall through */
  3672. default:
  3673. goto done;
  3674. }
  3675. if (val & BMCR_FULLDPLX)
  3676. tp->link_config.duplex = DUPLEX_FULL;
  3677. else
  3678. tp->link_config.duplex = DUPLEX_HALF;
  3679. tp->link_config.flowctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
  3680. err = 0;
  3681. goto done;
  3682. }
  3683. tp->link_config.autoneg = AUTONEG_ENABLE;
  3684. tp->link_config.advertising = ADVERTISED_Autoneg;
  3685. tg3_flag_set(tp, PAUSE_AUTONEG);
  3686. if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
  3687. u32 adv;
  3688. err = tg3_readphy(tp, MII_ADVERTISE, &val);
  3689. if (err)
  3690. goto done;
  3691. adv = mii_adv_to_ethtool_adv_t(val & ADVERTISE_ALL);
  3692. tp->link_config.advertising |= adv | ADVERTISED_TP;
  3693. tp->link_config.flowctrl = tg3_decode_flowctrl_1000T(val);
  3694. } else {
  3695. tp->link_config.advertising |= ADVERTISED_FIBRE;
  3696. }
  3697. if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
  3698. u32 adv;
  3699. if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
  3700. err = tg3_readphy(tp, MII_CTRL1000, &val);
  3701. if (err)
  3702. goto done;
  3703. adv = mii_ctrl1000_to_ethtool_adv_t(val);
  3704. } else {
  3705. err = tg3_readphy(tp, MII_ADVERTISE, &val);
  3706. if (err)
  3707. goto done;
  3708. adv = tg3_decode_flowctrl_1000X(val);
  3709. tp->link_config.flowctrl = adv;
  3710. val &= (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL);
  3711. adv = mii_adv_to_ethtool_adv_x(val);
  3712. }
  3713. tp->link_config.advertising |= adv;
  3714. }
  3715. done:
  3716. return err;
  3717. }
  3718. static int tg3_init_5401phy_dsp(struct tg3 *tp)
  3719. {
  3720. int err;
  3721. /* Turn off tap power management. */
  3722. /* Set Extended packet length bit */
  3723. err = tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
  3724. err |= tg3_phydsp_write(tp, 0x0012, 0x1804);
  3725. err |= tg3_phydsp_write(tp, 0x0013, 0x1204);
  3726. err |= tg3_phydsp_write(tp, 0x8006, 0x0132);
  3727. err |= tg3_phydsp_write(tp, 0x8006, 0x0232);
  3728. err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);
  3729. udelay(40);
  3730. return err;
  3731. }
  3732. static bool tg3_phy_eee_config_ok(struct tg3 *tp)
  3733. {
  3734. struct ethtool_eee eee;
  3735. if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
  3736. return true;
  3737. tg3_eee_pull_config(tp, &eee);
  3738. if (tp->eee.eee_enabled) {
  3739. if (tp->eee.advertised != eee.advertised ||
  3740. tp->eee.tx_lpi_timer != eee.tx_lpi_timer ||
  3741. tp->eee.tx_lpi_enabled != eee.tx_lpi_enabled)
  3742. return false;
  3743. } else {
  3744. /* EEE is disabled but we're advertising */
  3745. if (eee.advertised)
  3746. return false;
  3747. }
  3748. return true;
  3749. }
  3750. static bool tg3_phy_copper_an_config_ok(struct tg3 *tp, u32 *lcladv)
  3751. {
  3752. u32 advmsk, tgtadv, advertising;
  3753. advertising = tp->link_config.advertising;
  3754. tgtadv = ethtool_adv_to_mii_adv_t(advertising) & ADVERTISE_ALL;
  3755. advmsk = ADVERTISE_ALL;
  3756. if (tp->link_config.active_duplex == DUPLEX_FULL) {
  3757. tgtadv |= mii_advertise_flowctrl(tp->link_config.flowctrl);
  3758. advmsk |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
  3759. }
  3760. if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
  3761. return false;
  3762. if ((*lcladv & advmsk) != tgtadv)
  3763. return false;
  3764. if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
  3765. u32 tg3_ctrl;
  3766. tgtadv = ethtool_adv_to_mii_ctrl1000_t(advertising);
  3767. if (tg3_readphy(tp, MII_CTRL1000, &tg3_ctrl))
  3768. return false;
  3769. if (tgtadv &&
  3770. (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
  3771. tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0)) {
  3772. tgtadv |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER;
  3773. tg3_ctrl &= (ADVERTISE_1000HALF | ADVERTISE_1000FULL |
  3774. CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER);
  3775. } else {
  3776. tg3_ctrl &= (ADVERTISE_1000HALF | ADVERTISE_1000FULL);
  3777. }
  3778. if (tg3_ctrl != tgtadv)
  3779. return false;
  3780. }
  3781. return true;
  3782. }
  3783. static bool tg3_phy_copper_fetch_rmtadv(struct tg3 *tp, u32 *rmtadv)
  3784. {
  3785. u32 lpeth = 0;
  3786. if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
  3787. u32 val;
  3788. if (tg3_readphy(tp, MII_STAT1000, &val))
  3789. return false;
  3790. lpeth = mii_stat1000_to_ethtool_lpa_t(val);
  3791. }
  3792. if (tg3_readphy(tp, MII_LPA, rmtadv))
  3793. return false;
  3794. lpeth |= mii_lpa_to_ethtool_lpa_t(*rmtadv);
  3795. tp->link_config.rmt_adv = lpeth;
  3796. return true;
  3797. }
  3798. static bool tg3_test_and_report_link_chg(struct tg3 *tp, bool curr_link_up)
  3799. {
  3800. if (curr_link_up != tp->link_up) {
  3801. if (curr_link_up) {
  3802. netif_carrier_on(tp->dev);
  3803. } else {
  3804. netif_carrier_off(tp->dev);
  3805. if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
  3806. tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
  3807. }
  3808. tg3_link_report(tp);
  3809. return true;
  3810. }
  3811. return false;
  3812. }
  3813. static void tg3_clear_mac_status(struct tg3 *tp)
  3814. {
  3815. tw32(MAC_EVENT, 0);
  3816. tw32_f(MAC_STATUS,
  3817. MAC_STATUS_SYNC_CHANGED |
  3818. MAC_STATUS_CFG_CHANGED |
  3819. MAC_STATUS_MI_COMPLETION |
  3820. MAC_STATUS_LNKSTATE_CHANGED);
  3821. udelay(40);
  3822. }
  3823. static void tg3_setup_eee(struct tg3 *tp)
  3824. {
  3825. u32 val;
  3826. val = TG3_CPMU_EEE_LNKIDL_PCIE_NL0 |
  3827. TG3_CPMU_EEE_LNKIDL_UART_IDL;
  3828. if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0)
  3829. val |= TG3_CPMU_EEE_LNKIDL_APE_TX_MT;
  3830. tw32_f(TG3_CPMU_EEE_LNKIDL_CTRL, val);
  3831. tw32_f(TG3_CPMU_EEE_CTRL,
  3832. TG3_CPMU_EEE_CTRL_EXIT_20_1_US);
  3833. val = TG3_CPMU_EEEMD_ERLY_L1_XIT_DET |
  3834. (tp->eee.tx_lpi_enabled ? TG3_CPMU_EEEMD_LPI_IN_TX : 0) |
  3835. TG3_CPMU_EEEMD_LPI_IN_RX |
  3836. TG3_CPMU_EEEMD_EEE_ENABLE;
  3837. if (tg3_asic_rev(tp) != ASIC_REV_5717)
  3838. val |= TG3_CPMU_EEEMD_SND_IDX_DET_EN;
  3839. if (tg3_flag(tp, ENABLE_APE))
  3840. val |= TG3_CPMU_EEEMD_APE_TX_DET_EN;
  3841. tw32_f(TG3_CPMU_EEE_MODE, tp->eee.eee_enabled ? val : 0);
  3842. tw32_f(TG3_CPMU_EEE_DBTMR1,
  3843. TG3_CPMU_DBTMR1_PCIEXIT_2047US |
  3844. (tp->eee.tx_lpi_timer & 0xffff));
  3845. tw32_f(TG3_CPMU_EEE_DBTMR2,
  3846. TG3_CPMU_DBTMR2_APE_TX_2047US |
  3847. TG3_CPMU_DBTMR2_TXIDXEQ_2047US);
  3848. }
  3849. static int tg3_setup_copper_phy(struct tg3 *tp, bool force_reset)
  3850. {
  3851. bool current_link_up;
  3852. u32 bmsr, val;
  3853. u32 lcl_adv, rmt_adv;
  3854. u16 current_speed;
  3855. u8 current_duplex;
  3856. int i, err;
  3857. tg3_clear_mac_status(tp);
  3858. if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
  3859. tw32_f(MAC_MI_MODE,
  3860. (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
  3861. udelay(80);
  3862. }
  3863. tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, 0);
  3864. /* Some third-party PHYs need to be reset on link going
  3865. * down.
  3866. */
  3867. if ((tg3_asic_rev(tp) == ASIC_REV_5703 ||
  3868. tg3_asic_rev(tp) == ASIC_REV_5704 ||
  3869. tg3_asic_rev(tp) == ASIC_REV_5705) &&
  3870. tp->link_up) {
  3871. tg3_readphy(tp, MII_BMSR, &bmsr);
  3872. if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
  3873. !(bmsr & BMSR_LSTATUS))
  3874. force_reset = true;
  3875. }
  3876. if (force_reset)
  3877. tg3_phy_reset(tp);
  3878. if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
  3879. tg3_readphy(tp, MII_BMSR, &bmsr);
  3880. if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
  3881. !tg3_flag(tp, INIT_COMPLETE))
  3882. bmsr = 0;
  3883. if (!(bmsr & BMSR_LSTATUS)) {
  3884. err = tg3_init_5401phy_dsp(tp);
  3885. if (err)
  3886. return err;
  3887. tg3_readphy(tp, MII_BMSR, &bmsr);
  3888. for (i = 0; i < 1000; i++) {
  3889. udelay(10);
  3890. if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
  3891. (bmsr & BMSR_LSTATUS)) {
  3892. udelay(40);
  3893. break;
  3894. }
  3895. }
  3896. if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
  3897. TG3_PHY_REV_BCM5401_B0 &&
  3898. !(bmsr & BMSR_LSTATUS) &&
  3899. tp->link_config.active_speed == SPEED_1000) {
  3900. err = tg3_phy_reset(tp);
  3901. if (!err)
  3902. err = tg3_init_5401phy_dsp(tp);
  3903. if (err)
  3904. return err;
  3905. }
  3906. }
  3907. } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
  3908. tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0) {
  3909. /* 5701 {A0,B0} CRC bug workaround */
  3910. tg3_writephy(tp, 0x15, 0x0a75);
  3911. tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
  3912. tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
  3913. tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
  3914. }
  3915. /* Clear pending interrupts... */
  3916. tg3_readphy(tp, MII_TG3_ISTAT, &val);
  3917. tg3_readphy(tp, MII_TG3_ISTAT, &val);
  3918. if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT)
  3919. tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
  3920. else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET))
  3921. tg3_writephy(tp, MII_TG3_IMASK, ~0);
  3922. if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
  3923. tg3_asic_rev(tp) == ASIC_REV_5701) {
  3924. if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
  3925. tg3_writephy(tp, MII_TG3_EXT_CTRL,
  3926. MII_TG3_EXT_CTRL_LNK3_LED_MODE);
  3927. else
  3928. tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
  3929. }
  3930. current_link_up = false;
  3931. current_speed = SPEED_UNKNOWN;
  3932. current_duplex = DUPLEX_UNKNOWN;
  3933. tp->phy_flags &= ~TG3_PHYFLG_MDIX_STATE;
  3934. tp->link_config.rmt_adv = 0;
  3935. if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) {
  3936. err = tg3_phy_auxctl_read(tp,
  3937. MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
  3938. &val);
  3939. if (!err && !(val & (1 << 10))) {
  3940. tg3_phy_auxctl_write(tp,
  3941. MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
  3942. val | (1 << 10));
  3943. goto relink;
  3944. }
  3945. }
  3946. bmsr = 0;
  3947. for (i = 0; i < 100; i++) {
  3948. tg3_readphy(tp, MII_BMSR, &bmsr);
  3949. if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
  3950. (bmsr & BMSR_LSTATUS))
  3951. break;
  3952. udelay(40);
  3953. }
  3954. if (bmsr & BMSR_LSTATUS) {
  3955. u32 aux_stat, bmcr;
  3956. tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
  3957. for (i = 0; i < 2000; i++) {
  3958. udelay(10);
  3959. if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
  3960. aux_stat)
  3961. break;
  3962. }
  3963. tg3_aux_stat_to_speed_duplex(tp, aux_stat,
  3964. &current_speed,
  3965. &current_duplex);
  3966. bmcr = 0;
  3967. for (i = 0; i < 200; i++) {
  3968. tg3_readphy(tp, MII_BMCR, &bmcr);
  3969. if (tg3_readphy(tp, MII_BMCR, &bmcr))
  3970. continue;
  3971. if (bmcr && bmcr != 0x7fff)
  3972. break;
  3973. udelay(10);
  3974. }
  3975. lcl_adv = 0;
  3976. rmt_adv = 0;
  3977. tp->link_config.active_speed = current_speed;
  3978. tp->link_config.active_duplex = current_duplex;
  3979. if (tp->link_config.autoneg == AUTONEG_ENABLE) {
  3980. bool eee_config_ok = tg3_phy_eee_config_ok(tp);
  3981. if ((bmcr & BMCR_ANENABLE) &&
  3982. eee_config_ok &&
  3983. tg3_phy_copper_an_config_ok(tp, &lcl_adv) &&
  3984. tg3_phy_copper_fetch_rmtadv(tp, &rmt_adv))
  3985. current_link_up = true;
  3986. /* EEE settings changes take effect only after a phy
  3987. * reset. If we have skipped a reset due to Link Flap
  3988. * Avoidance being enabled, do it now.
  3989. */
  3990. if (!eee_config_ok &&
  3991. (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) &&
  3992. !force_reset) {
  3993. tg3_setup_eee(tp);
  3994. tg3_phy_reset(tp);
  3995. }
  3996. } else {
  3997. if (!(bmcr & BMCR_ANENABLE) &&
  3998. tp->link_config.speed == current_speed &&
  3999. tp->link_config.duplex == current_duplex) {
  4000. current_link_up = true;
  4001. }
  4002. }
  4003. if (current_link_up &&
  4004. tp->link_config.active_duplex == DUPLEX_FULL) {
  4005. u32 reg, bit;
  4006. if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
  4007. reg = MII_TG3_FET_GEN_STAT;
  4008. bit = MII_TG3_FET_GEN_STAT_MDIXSTAT;
  4009. } else {
  4010. reg = MII_TG3_EXT_STAT;
  4011. bit = MII_TG3_EXT_STAT_MDIX;
  4012. }
  4013. if (!tg3_readphy(tp, reg, &val) && (val & bit))
  4014. tp->phy_flags |= TG3_PHYFLG_MDIX_STATE;
  4015. tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
  4016. }
  4017. }
  4018. relink:
  4019. if (!current_link_up || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
  4020. tg3_phy_copper_begin(tp);
  4021. if (tg3_flag(tp, ROBOSWITCH)) {
  4022. current_link_up = true;
  4023. /* FIXME: when BCM5325 switch is used use 100 MBit/s */
  4024. current_speed = SPEED_1000;
  4025. current_duplex = DUPLEX_FULL;
  4026. tp->link_config.active_speed = current_speed;
  4027. tp->link_config.active_duplex = current_duplex;
  4028. }
  4029. tg3_readphy(tp, MII_BMSR, &bmsr);
  4030. if ((!tg3_readphy(tp, MII_BMSR, &bmsr) && (bmsr & BMSR_LSTATUS)) ||
  4031. (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
  4032. current_link_up = true;
  4033. }
  4034. tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
  4035. if (current_link_up) {
  4036. if (tp->link_config.active_speed == SPEED_100 ||
  4037. tp->link_config.active_speed == SPEED_10)
  4038. tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
  4039. else
  4040. tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
  4041. } else if (tp->phy_flags & TG3_PHYFLG_IS_FET)
  4042. tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
  4043. else
  4044. tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
  4045. /* In order for the 5750 core in BCM4785 chip to work properly
  4046. * in RGMII mode, the Led Control Register must be set up.
  4047. */
  4048. if (tg3_flag(tp, RGMII_MODE)) {
  4049. u32 led_ctrl = tr32(MAC_LED_CTRL);
  4050. led_ctrl &= ~(LED_CTRL_1000MBPS_ON | LED_CTRL_100MBPS_ON);
  4051. if (tp->link_config.active_speed == SPEED_10)
  4052. led_ctrl |= LED_CTRL_LNKLED_OVERRIDE;
  4053. else if (tp->link_config.active_speed == SPEED_100)
  4054. led_ctrl |= (LED_CTRL_LNKLED_OVERRIDE |
  4055. LED_CTRL_100MBPS_ON);
  4056. else if (tp->link_config.active_speed == SPEED_1000)
  4057. led_ctrl |= (LED_CTRL_LNKLED_OVERRIDE |
  4058. LED_CTRL_1000MBPS_ON);
  4059. tw32(MAC_LED_CTRL, led_ctrl);
  4060. udelay(40);
  4061. }
  4062. tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
  4063. if (tp->link_config.active_duplex == DUPLEX_HALF)
  4064. tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
  4065. if (tg3_asic_rev(tp) == ASIC_REV_5700) {
  4066. if (current_link_up &&
  4067. tg3_5700_link_polarity(tp, tp->link_config.active_speed))
  4068. tp->mac_mode |= MAC_MODE_LINK_POLARITY;
  4069. else
  4070. tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
  4071. }
  4072. /* ??? Without this setting Netgear GA302T PHY does not
  4073. * ??? send/receive packets...
  4074. */
  4075. if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
  4076. tg3_chip_rev_id(tp) == CHIPREV_ID_5700_ALTIMA) {
  4077. tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
  4078. tw32_f(MAC_MI_MODE, tp->mi_mode);
  4079. udelay(80);
  4080. }
  4081. tw32_f(MAC_MODE, tp->mac_mode);
  4082. udelay(40);
  4083. tg3_phy_eee_adjust(tp, current_link_up);
  4084. if (tg3_flag(tp, USE_LINKCHG_REG)) {
  4085. /* Polled via timer. */
  4086. tw32_f(MAC_EVENT, 0);
  4087. } else {
  4088. tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
  4089. }
  4090. udelay(40);
  4091. if (tg3_asic_rev(tp) == ASIC_REV_5700 &&
  4092. current_link_up &&
  4093. tp->link_config.active_speed == SPEED_1000 &&
  4094. (tg3_flag(tp, PCIX_MODE) || tg3_flag(tp, PCI_HIGH_SPEED))) {
  4095. udelay(120);
  4096. tw32_f(MAC_STATUS,
  4097. (MAC_STATUS_SYNC_CHANGED |
  4098. MAC_STATUS_CFG_CHANGED));
  4099. udelay(40);
  4100. tg3_write_mem(tp,
  4101. NIC_SRAM_FIRMWARE_MBOX,
  4102. NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
  4103. }
  4104. /* Prevent send BD corruption. */
  4105. if (tg3_flag(tp, CLKREQ_BUG)) {
  4106. if (tp->link_config.active_speed == SPEED_100 ||
  4107. tp->link_config.active_speed == SPEED_10)
  4108. pcie_capability_clear_word(tp->pdev, PCI_EXP_LNKCTL,
  4109. PCI_EXP_LNKCTL_CLKREQ_EN);
  4110. else
  4111. pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL,
  4112. PCI_EXP_LNKCTL_CLKREQ_EN);
  4113. }
  4114. tg3_test_and_report_link_chg(tp, current_link_up);
  4115. return 0;
  4116. }
  4117. struct tg3_fiber_aneginfo {
  4118. int state;
  4119. #define ANEG_STATE_UNKNOWN 0
  4120. #define ANEG_STATE_AN_ENABLE 1
  4121. #define ANEG_STATE_RESTART_INIT 2
  4122. #define ANEG_STATE_RESTART 3
  4123. #define ANEG_STATE_DISABLE_LINK_OK 4
  4124. #define ANEG_STATE_ABILITY_DETECT_INIT 5
  4125. #define ANEG_STATE_ABILITY_DETECT 6
  4126. #define ANEG_STATE_ACK_DETECT_INIT 7
  4127. #define ANEG_STATE_ACK_DETECT 8
  4128. #define ANEG_STATE_COMPLETE_ACK_INIT 9
  4129. #define ANEG_STATE_COMPLETE_ACK 10
  4130. #define ANEG_STATE_IDLE_DETECT_INIT 11
  4131. #define ANEG_STATE_IDLE_DETECT 12
  4132. #define ANEG_STATE_LINK_OK 13
  4133. #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
  4134. #define ANEG_STATE_NEXT_PAGE_WAIT 15
  4135. u32 flags;
  4136. #define MR_AN_ENABLE 0x00000001
  4137. #define MR_RESTART_AN 0x00000002
  4138. #define MR_AN_COMPLETE 0x00000004
  4139. #define MR_PAGE_RX 0x00000008
  4140. #define MR_NP_LOADED 0x00000010
  4141. #define MR_TOGGLE_TX 0x00000020
  4142. #define MR_LP_ADV_FULL_DUPLEX 0x00000040
  4143. #define MR_LP_ADV_HALF_DUPLEX 0x00000080
  4144. #define MR_LP_ADV_SYM_PAUSE 0x00000100
  4145. #define MR_LP_ADV_ASYM_PAUSE 0x00000200
  4146. #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
  4147. #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
  4148. #define MR_LP_ADV_NEXT_PAGE 0x00001000
  4149. #define MR_TOGGLE_RX 0x00002000
  4150. #define MR_NP_RX 0x00004000
  4151. #define MR_LINK_OK 0x80000000
  4152. unsigned long link_time, cur_time;
  4153. u32 ability_match_cfg;
  4154. int ability_match_count;
  4155. char ability_match, idle_match, ack_match;
  4156. u32 txconfig, rxconfig;
  4157. #define ANEG_CFG_NP 0x00000080
  4158. #define ANEG_CFG_ACK 0x00000040
  4159. #define ANEG_CFG_RF2 0x00000020
  4160. #define ANEG_CFG_RF1 0x00000010
  4161. #define ANEG_CFG_PS2 0x00000001
  4162. #define ANEG_CFG_PS1 0x00008000
  4163. #define ANEG_CFG_HD 0x00004000
  4164. #define ANEG_CFG_FD 0x00002000
  4165. #define ANEG_CFG_INVAL 0x00001f06
  4166. };
  4167. #define ANEG_OK 0
  4168. #define ANEG_DONE 1
  4169. #define ANEG_TIMER_ENAB 2
  4170. #define ANEG_FAILED -1
  4171. #define ANEG_STATE_SETTLE_TIME 10000
  4172. static int tg3_fiber_aneg_smachine(struct tg3 *tp,
  4173. struct tg3_fiber_aneginfo *ap)
  4174. {
  4175. u16 flowctrl;
  4176. unsigned long delta;
  4177. u32 rx_cfg_reg;
  4178. int ret;
  4179. if (ap->state == ANEG_STATE_UNKNOWN) {
  4180. ap->rxconfig = 0;
  4181. ap->link_time = 0;
  4182. ap->cur_time = 0;
  4183. ap->ability_match_cfg = 0;
  4184. ap->ability_match_count = 0;
  4185. ap->ability_match = 0;
  4186. ap->idle_match = 0;
  4187. ap->ack_match = 0;
  4188. }
  4189. ap->cur_time++;
  4190. if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
  4191. rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
  4192. if (rx_cfg_reg != ap->ability_match_cfg) {
  4193. ap->ability_match_cfg = rx_cfg_reg;
  4194. ap->ability_match = 0;
  4195. ap->ability_match_count = 0;
  4196. } else {
  4197. if (++ap->ability_match_count > 1) {
  4198. ap->ability_match = 1;
  4199. ap->ability_match_cfg = rx_cfg_reg;
  4200. }
  4201. }
  4202. if (rx_cfg_reg & ANEG_CFG_ACK)
  4203. ap->ack_match = 1;
  4204. else
  4205. ap->ack_match = 0;
  4206. ap->idle_match = 0;
  4207. } else {
  4208. ap->idle_match = 1;
  4209. ap->ability_match_cfg = 0;
  4210. ap->ability_match_count = 0;
  4211. ap->ability_match = 0;
  4212. ap->ack_match = 0;
  4213. rx_cfg_reg = 0;
  4214. }
  4215. ap->rxconfig = rx_cfg_reg;
  4216. ret = ANEG_OK;
  4217. switch (ap->state) {
  4218. case ANEG_STATE_UNKNOWN:
  4219. if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
  4220. ap->state = ANEG_STATE_AN_ENABLE;
  4221. /* fallthru */
  4222. case ANEG_STATE_AN_ENABLE:
  4223. ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
  4224. if (ap->flags & MR_AN_ENABLE) {
  4225. ap->link_time = 0;
  4226. ap->cur_time = 0;
  4227. ap->ability_match_cfg = 0;
  4228. ap->ability_match_count = 0;
  4229. ap->ability_match = 0;
  4230. ap->idle_match = 0;
  4231. ap->ack_match = 0;
  4232. ap->state = ANEG_STATE_RESTART_INIT;
  4233. } else {
  4234. ap->state = ANEG_STATE_DISABLE_LINK_OK;
  4235. }
  4236. break;
  4237. case ANEG_STATE_RESTART_INIT:
  4238. ap->link_time = ap->cur_time;
  4239. ap->flags &= ~(MR_NP_LOADED);
  4240. ap->txconfig = 0;
  4241. tw32(MAC_TX_AUTO_NEG, 0);
  4242. tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
  4243. tw32_f(MAC_MODE, tp->mac_mode);
  4244. udelay(40);
  4245. ret = ANEG_TIMER_ENAB;
  4246. ap->state = ANEG_STATE_RESTART;
  4247. /* fallthru */
  4248. case ANEG_STATE_RESTART:
  4249. delta = ap->cur_time - ap->link_time;
  4250. if (delta > ANEG_STATE_SETTLE_TIME)
  4251. ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
  4252. else
  4253. ret = ANEG_TIMER_ENAB;
  4254. break;
  4255. case ANEG_STATE_DISABLE_LINK_OK:
  4256. ret = ANEG_DONE;
  4257. break;
  4258. case ANEG_STATE_ABILITY_DETECT_INIT:
  4259. ap->flags &= ~(MR_TOGGLE_TX);
  4260. ap->txconfig = ANEG_CFG_FD;
  4261. flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
  4262. if (flowctrl & ADVERTISE_1000XPAUSE)
  4263. ap->txconfig |= ANEG_CFG_PS1;
  4264. if (flowctrl & ADVERTISE_1000XPSE_ASYM)
  4265. ap->txconfig |= ANEG_CFG_PS2;
  4266. tw32(MAC_TX_AUTO_NEG, ap->txconfig);
  4267. tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
  4268. tw32_f(MAC_MODE, tp->mac_mode);
  4269. udelay(40);
  4270. ap->state = ANEG_STATE_ABILITY_DETECT;
  4271. break;
  4272. case ANEG_STATE_ABILITY_DETECT:
  4273. if (ap->ability_match != 0 && ap->rxconfig != 0)
  4274. ap->state = ANEG_STATE_ACK_DETECT_INIT;
  4275. break;
  4276. case ANEG_STATE_ACK_DETECT_INIT:
  4277. ap->txconfig |= ANEG_CFG_ACK;
  4278. tw32(MAC_TX_AUTO_NEG, ap->txconfig);
  4279. tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
  4280. tw32_f(MAC_MODE, tp->mac_mode);
  4281. udelay(40);
  4282. ap->state = ANEG_STATE_ACK_DETECT;
  4283. /* fallthru */
  4284. case ANEG_STATE_ACK_DETECT:
  4285. if (ap->ack_match != 0) {
  4286. if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
  4287. (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
  4288. ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
  4289. } else {
  4290. ap->state = ANEG_STATE_AN_ENABLE;
  4291. }
  4292. } else if (ap->ability_match != 0 &&
  4293. ap->rxconfig == 0) {
  4294. ap->state = ANEG_STATE_AN_ENABLE;
  4295. }
  4296. break;
  4297. case ANEG_STATE_COMPLETE_ACK_INIT:
  4298. if (ap->rxconfig & ANEG_CFG_INVAL) {
  4299. ret = ANEG_FAILED;
  4300. break;
  4301. }
  4302. ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
  4303. MR_LP_ADV_HALF_DUPLEX |
  4304. MR_LP_ADV_SYM_PAUSE |
  4305. MR_LP_ADV_ASYM_PAUSE |
  4306. MR_LP_ADV_REMOTE_FAULT1 |
  4307. MR_LP_ADV_REMOTE_FAULT2 |
  4308. MR_LP_ADV_NEXT_PAGE |
  4309. MR_TOGGLE_RX |
  4310. MR_NP_RX);
  4311. if (ap->rxconfig & ANEG_CFG_FD)
  4312. ap->flags |= MR_LP_ADV_FULL_DUPLEX;
  4313. if (ap->rxconfig & ANEG_CFG_HD)
  4314. ap->flags |= MR_LP_ADV_HALF_DUPLEX;
  4315. if (ap->rxconfig & ANEG_CFG_PS1)
  4316. ap->flags |= MR_LP_ADV_SYM_PAUSE;
  4317. if (ap->rxconfig & ANEG_CFG_PS2)
  4318. ap->flags |= MR_LP_ADV_ASYM_PAUSE;
  4319. if (ap->rxconfig & ANEG_CFG_RF1)
  4320. ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
  4321. if (ap->rxconfig & ANEG_CFG_RF2)
  4322. ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
  4323. if (ap->rxconfig & ANEG_CFG_NP)
  4324. ap->flags |= MR_LP_ADV_NEXT_PAGE;
  4325. ap->link_time = ap->cur_time;
  4326. ap->flags ^= (MR_TOGGLE_TX);
  4327. if (ap->rxconfig & 0x0008)
  4328. ap->flags |= MR_TOGGLE_RX;
  4329. if (ap->rxconfig & ANEG_CFG_NP)
  4330. ap->flags |= MR_NP_RX;
  4331. ap->flags |= MR_PAGE_RX;
  4332. ap->state = ANEG_STATE_COMPLETE_ACK;
  4333. ret = ANEG_TIMER_ENAB;
  4334. break;
  4335. case ANEG_STATE_COMPLETE_ACK:
  4336. if (ap->ability_match != 0 &&
  4337. ap->rxconfig == 0) {
  4338. ap->state = ANEG_STATE_AN_ENABLE;
  4339. break;
  4340. }
  4341. delta = ap->cur_time - ap->link_time;
  4342. if (delta > ANEG_STATE_SETTLE_TIME) {
  4343. if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
  4344. ap->state = ANEG_STATE_IDLE_DETECT_INIT;
  4345. } else {
  4346. if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
  4347. !(ap->flags & MR_NP_RX)) {
  4348. ap->state = ANEG_STATE_IDLE_DETECT_INIT;
  4349. } else {
  4350. ret = ANEG_FAILED;
  4351. }
  4352. }
  4353. }
  4354. break;
  4355. case ANEG_STATE_IDLE_DETECT_INIT:
  4356. ap->link_time = ap->cur_time;
  4357. tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
  4358. tw32_f(MAC_MODE, tp->mac_mode);
  4359. udelay(40);
  4360. ap->state = ANEG_STATE_IDLE_DETECT;
  4361. ret = ANEG_TIMER_ENAB;
  4362. break;
  4363. case ANEG_STATE_IDLE_DETECT:
  4364. if (ap->ability_match != 0 &&
  4365. ap->rxconfig == 0) {
  4366. ap->state = ANEG_STATE_AN_ENABLE;
  4367. break;
  4368. }
  4369. delta = ap->cur_time - ap->link_time;
  4370. if (delta > ANEG_STATE_SETTLE_TIME) {
  4371. /* XXX another gem from the Broadcom driver :( */
  4372. ap->state = ANEG_STATE_LINK_OK;
  4373. }
  4374. break;
  4375. case ANEG_STATE_LINK_OK:
  4376. ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
  4377. ret = ANEG_DONE;
  4378. break;
  4379. case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
  4380. /* ??? unimplemented */
  4381. break;
  4382. case ANEG_STATE_NEXT_PAGE_WAIT:
  4383. /* ??? unimplemented */
  4384. break;
  4385. default:
  4386. ret = ANEG_FAILED;
  4387. break;
  4388. }
  4389. return ret;
  4390. }
  4391. static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
  4392. {
  4393. int res = 0;
  4394. struct tg3_fiber_aneginfo aninfo;
  4395. int status = ANEG_FAILED;
  4396. unsigned int tick;
  4397. u32 tmp;
  4398. tw32_f(MAC_TX_AUTO_NEG, 0);
  4399. tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
  4400. tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
  4401. udelay(40);
  4402. tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
  4403. udelay(40);
  4404. memset(&aninfo, 0, sizeof(aninfo));
  4405. aninfo.flags |= MR_AN_ENABLE;
  4406. aninfo.state = ANEG_STATE_UNKNOWN;
  4407. aninfo.cur_time = 0;
  4408. tick = 0;
  4409. while (++tick < 195000) {
  4410. status = tg3_fiber_aneg_smachine(tp, &aninfo);
  4411. if (status == ANEG_DONE || status == ANEG_FAILED)
  4412. break;
  4413. udelay(1);
  4414. }
  4415. tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
  4416. tw32_f(MAC_MODE, tp->mac_mode);
  4417. udelay(40);
  4418. *txflags = aninfo.txconfig;
  4419. *rxflags = aninfo.flags;
  4420. if (status == ANEG_DONE &&
  4421. (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
  4422. MR_LP_ADV_FULL_DUPLEX)))
  4423. res = 1;
  4424. return res;
  4425. }
  4426. static void tg3_init_bcm8002(struct tg3 *tp)
  4427. {
  4428. u32 mac_status = tr32(MAC_STATUS);
  4429. int i;
  4430. /* Reset when initting first time or we have a link. */
  4431. if (tg3_flag(tp, INIT_COMPLETE) &&
  4432. !(mac_status & MAC_STATUS_PCS_SYNCED))
  4433. return;
  4434. /* Set PLL lock range. */
  4435. tg3_writephy(tp, 0x16, 0x8007);
  4436. /* SW reset */
  4437. tg3_writephy(tp, MII_BMCR, BMCR_RESET);
  4438. /* Wait for reset to complete. */
  4439. /* XXX schedule_timeout() ... */
  4440. for (i = 0; i < 500; i++)
  4441. udelay(10);
  4442. /* Config mode; select PMA/Ch 1 regs. */
  4443. tg3_writephy(tp, 0x10, 0x8411);
  4444. /* Enable auto-lock and comdet, select txclk for tx. */
  4445. tg3_writephy(tp, 0x11, 0x0a10);
  4446. tg3_writephy(tp, 0x18, 0x00a0);
  4447. tg3_writephy(tp, 0x16, 0x41ff);
  4448. /* Assert and deassert POR. */
  4449. tg3_writephy(tp, 0x13, 0x0400);
  4450. udelay(40);
  4451. tg3_writephy(tp, 0x13, 0x0000);
  4452. tg3_writephy(tp, 0x11, 0x0a50);
  4453. udelay(40);
  4454. tg3_writephy(tp, 0x11, 0x0a10);
  4455. /* Wait for signal to stabilize */
  4456. /* XXX schedule_timeout() ... */
  4457. for (i = 0; i < 15000; i++)
  4458. udelay(10);
  4459. /* Deselect the channel register so we can read the PHYID
  4460. * later.
  4461. */
  4462. tg3_writephy(tp, 0x10, 0x8011);
  4463. }
  4464. static bool tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
  4465. {
  4466. u16 flowctrl;
  4467. bool current_link_up;
  4468. u32 sg_dig_ctrl, sg_dig_status;
  4469. u32 serdes_cfg, expected_sg_dig_ctrl;
  4470. int workaround, port_a;
  4471. serdes_cfg = 0;
  4472. expected_sg_dig_ctrl = 0;
  4473. workaround = 0;
  4474. port_a = 1;
  4475. current_link_up = false;
  4476. if (tg3_chip_rev_id(tp) != CHIPREV_ID_5704_A0 &&
  4477. tg3_chip_rev_id(tp) != CHIPREV_ID_5704_A1) {
  4478. workaround = 1;
  4479. if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
  4480. port_a = 0;
  4481. /* preserve bits 0-11,13,14 for signal pre-emphasis */
  4482. /* preserve bits 20-23 for voltage regulator */
  4483. serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
  4484. }
  4485. sg_dig_ctrl = tr32(SG_DIG_CTRL);
  4486. if (tp->link_config.autoneg != AUTONEG_ENABLE) {
  4487. if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
  4488. if (workaround) {
  4489. u32 val = serdes_cfg;
  4490. if (port_a)
  4491. val |= 0xc010000;
  4492. else
  4493. val |= 0x4010000;
  4494. tw32_f(MAC_SERDES_CFG, val);
  4495. }
  4496. tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
  4497. }
  4498. if (mac_status & MAC_STATUS_PCS_SYNCED) {
  4499. tg3_setup_flow_control(tp, 0, 0);
  4500. current_link_up = true;
  4501. }
  4502. goto out;
  4503. }
  4504. /* Want auto-negotiation. */
  4505. expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
  4506. flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
  4507. if (flowctrl & ADVERTISE_1000XPAUSE)
  4508. expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
  4509. if (flowctrl & ADVERTISE_1000XPSE_ASYM)
  4510. expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
  4511. if (sg_dig_ctrl != expected_sg_dig_ctrl) {
  4512. if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) &&
  4513. tp->serdes_counter &&
  4514. ((mac_status & (MAC_STATUS_PCS_SYNCED |
  4515. MAC_STATUS_RCVD_CFG)) ==
  4516. MAC_STATUS_PCS_SYNCED)) {
  4517. tp->serdes_counter--;
  4518. current_link_up = true;
  4519. goto out;
  4520. }
  4521. restart_autoneg:
  4522. if (workaround)
  4523. tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
  4524. tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
  4525. udelay(5);
  4526. tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
  4527. tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
  4528. tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
  4529. } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
  4530. MAC_STATUS_SIGNAL_DET)) {
  4531. sg_dig_status = tr32(SG_DIG_STATUS);
  4532. mac_status = tr32(MAC_STATUS);
  4533. if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
  4534. (mac_status & MAC_STATUS_PCS_SYNCED)) {
  4535. u32 local_adv = 0, remote_adv = 0;
  4536. if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
  4537. local_adv |= ADVERTISE_1000XPAUSE;
  4538. if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
  4539. local_adv |= ADVERTISE_1000XPSE_ASYM;
  4540. if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
  4541. remote_adv |= LPA_1000XPAUSE;
  4542. if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
  4543. remote_adv |= LPA_1000XPAUSE_ASYM;
  4544. tp->link_config.rmt_adv =
  4545. mii_adv_to_ethtool_adv_x(remote_adv);
  4546. tg3_setup_flow_control(tp, local_adv, remote_adv);
  4547. current_link_up = true;
  4548. tp->serdes_counter = 0;
  4549. tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
  4550. } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
  4551. if (tp->serdes_counter)
  4552. tp->serdes_counter--;
  4553. else {
  4554. if (workaround) {
  4555. u32 val = serdes_cfg;
  4556. if (port_a)
  4557. val |= 0xc010000;
  4558. else
  4559. val |= 0x4010000;
  4560. tw32_f(MAC_SERDES_CFG, val);
  4561. }
  4562. tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
  4563. udelay(40);
  4564. /* Link parallel detection - link is up */
  4565. /* only if we have PCS_SYNC and not */
  4566. /* receiving config code words */
  4567. mac_status = tr32(MAC_STATUS);
  4568. if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
  4569. !(mac_status & MAC_STATUS_RCVD_CFG)) {
  4570. tg3_setup_flow_control(tp, 0, 0);
  4571. current_link_up = true;
  4572. tp->phy_flags |=
  4573. TG3_PHYFLG_PARALLEL_DETECT;
  4574. tp->serdes_counter =
  4575. SERDES_PARALLEL_DET_TIMEOUT;
  4576. } else
  4577. goto restart_autoneg;
  4578. }
  4579. }
  4580. } else {
  4581. tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
  4582. tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
  4583. }
  4584. out:
  4585. return current_link_up;
  4586. }
  4587. static bool tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
  4588. {
  4589. bool current_link_up = false;
  4590. if (!(mac_status & MAC_STATUS_PCS_SYNCED))
  4591. goto out;
  4592. if (tp->link_config.autoneg == AUTONEG_ENABLE) {
  4593. u32 txflags, rxflags;
  4594. int i;
  4595. if (fiber_autoneg(tp, &txflags, &rxflags)) {
  4596. u32 local_adv = 0, remote_adv = 0;
  4597. if (txflags & ANEG_CFG_PS1)
  4598. local_adv |= ADVERTISE_1000XPAUSE;
  4599. if (txflags & ANEG_CFG_PS2)
  4600. local_adv |= ADVERTISE_1000XPSE_ASYM;
  4601. if (rxflags & MR_LP_ADV_SYM_PAUSE)
  4602. remote_adv |= LPA_1000XPAUSE;
  4603. if (rxflags & MR_LP_ADV_ASYM_PAUSE)
  4604. remote_adv |= LPA_1000XPAUSE_ASYM;
  4605. tp->link_config.rmt_adv =
  4606. mii_adv_to_ethtool_adv_x(remote_adv);
  4607. tg3_setup_flow_control(tp, local_adv, remote_adv);
  4608. current_link_up = true;
  4609. }
  4610. for (i = 0; i < 30; i++) {
  4611. udelay(20);
  4612. tw32_f(MAC_STATUS,
  4613. (MAC_STATUS_SYNC_CHANGED |
  4614. MAC_STATUS_CFG_CHANGED));
  4615. udelay(40);
  4616. if ((tr32(MAC_STATUS) &
  4617. (MAC_STATUS_SYNC_CHANGED |
  4618. MAC_STATUS_CFG_CHANGED)) == 0)
  4619. break;
  4620. }
  4621. mac_status = tr32(MAC_STATUS);
  4622. if (!current_link_up &&
  4623. (mac_status & MAC_STATUS_PCS_SYNCED) &&
  4624. !(mac_status & MAC_STATUS_RCVD_CFG))
  4625. current_link_up = true;
  4626. } else {
  4627. tg3_setup_flow_control(tp, 0, 0);
  4628. /* Forcing 1000FD link up. */
  4629. current_link_up = true;
  4630. tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
  4631. udelay(40);
  4632. tw32_f(MAC_MODE, tp->mac_mode);
  4633. udelay(40);
  4634. }
  4635. out:
  4636. return current_link_up;
  4637. }
  4638. static int tg3_setup_fiber_phy(struct tg3 *tp, bool force_reset)
  4639. {
  4640. u32 orig_pause_cfg;
  4641. u16 orig_active_speed;
  4642. u8 orig_active_duplex;
  4643. u32 mac_status;
  4644. bool current_link_up;
  4645. int i;
  4646. orig_pause_cfg = tp->link_config.active_flowctrl;
  4647. orig_active_speed = tp->link_config.active_speed;
  4648. orig_active_duplex = tp->link_config.active_duplex;
  4649. if (!tg3_flag(tp, HW_AUTONEG) &&
  4650. tp->link_up &&
  4651. tg3_flag(tp, INIT_COMPLETE)) {
  4652. mac_status = tr32(MAC_STATUS);
  4653. mac_status &= (MAC_STATUS_PCS_SYNCED |
  4654. MAC_STATUS_SIGNAL_DET |
  4655. MAC_STATUS_CFG_CHANGED |
  4656. MAC_STATUS_RCVD_CFG);
  4657. if (mac_status == (MAC_STATUS_PCS_SYNCED |
  4658. MAC_STATUS_SIGNAL_DET)) {
  4659. tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
  4660. MAC_STATUS_CFG_CHANGED));
  4661. return 0;
  4662. }
  4663. }
  4664. tw32_f(MAC_TX_AUTO_NEG, 0);
  4665. tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
  4666. tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
  4667. tw32_f(MAC_MODE, tp->mac_mode);
  4668. udelay(40);
  4669. if (tp->phy_id == TG3_PHY_ID_BCM8002)
  4670. tg3_init_bcm8002(tp);
  4671. /* Enable link change event even when serdes polling. */
  4672. tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
  4673. udelay(40);
  4674. current_link_up = false;
  4675. tp->link_config.rmt_adv = 0;
  4676. mac_status = tr32(MAC_STATUS);
  4677. if (tg3_flag(tp, HW_AUTONEG))
  4678. current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
  4679. else
  4680. current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
  4681. tp->napi[0].hw_status->status =
  4682. (SD_STATUS_UPDATED |
  4683. (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
  4684. for (i = 0; i < 100; i++) {
  4685. tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
  4686. MAC_STATUS_CFG_CHANGED));
  4687. udelay(5);
  4688. if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
  4689. MAC_STATUS_CFG_CHANGED |
  4690. MAC_STATUS_LNKSTATE_CHANGED)) == 0)
  4691. break;
  4692. }
  4693. mac_status = tr32(MAC_STATUS);
  4694. if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
  4695. current_link_up = false;
  4696. if (tp->link_config.autoneg == AUTONEG_ENABLE &&
  4697. tp->serdes_counter == 0) {
  4698. tw32_f(MAC_MODE, (tp->mac_mode |
  4699. MAC_MODE_SEND_CONFIGS));
  4700. udelay(1);
  4701. tw32_f(MAC_MODE, tp->mac_mode);
  4702. }
  4703. }
  4704. if (current_link_up) {
  4705. tp->link_config.active_speed = SPEED_1000;
  4706. tp->link_config.active_duplex = DUPLEX_FULL;
  4707. tw32(MAC_LED_CTRL, (tp->led_ctrl |
  4708. LED_CTRL_LNKLED_OVERRIDE |
  4709. LED_CTRL_1000MBPS_ON));
  4710. } else {
  4711. tp->link_config.active_speed = SPEED_UNKNOWN;
  4712. tp->link_config.active_duplex = DUPLEX_UNKNOWN;
  4713. tw32(MAC_LED_CTRL, (tp->led_ctrl |
  4714. LED_CTRL_LNKLED_OVERRIDE |
  4715. LED_CTRL_TRAFFIC_OVERRIDE));
  4716. }
  4717. if (!tg3_test_and_report_link_chg(tp, current_link_up)) {
  4718. u32 now_pause_cfg = tp->link_config.active_flowctrl;
  4719. if (orig_pause_cfg != now_pause_cfg ||
  4720. orig_active_speed != tp->link_config.active_speed ||
  4721. orig_active_duplex != tp->link_config.active_duplex)
  4722. tg3_link_report(tp);
  4723. }
  4724. return 0;
  4725. }
  4726. static int tg3_setup_fiber_mii_phy(struct tg3 *tp, bool force_reset)
  4727. {
  4728. int err = 0;
  4729. u32 bmsr, bmcr;
  4730. u16 current_speed = SPEED_UNKNOWN;
  4731. u8 current_duplex = DUPLEX_UNKNOWN;
  4732. bool current_link_up = false;
  4733. u32 local_adv, remote_adv, sgsr;
  4734. if ((tg3_asic_rev(tp) == ASIC_REV_5719 ||
  4735. tg3_asic_rev(tp) == ASIC_REV_5720) &&
  4736. !tg3_readphy(tp, SERDES_TG3_1000X_STATUS, &sgsr) &&
  4737. (sgsr & SERDES_TG3_SGMII_MODE)) {
  4738. if (force_reset)
  4739. tg3_phy_reset(tp);
  4740. tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
  4741. if (!(sgsr & SERDES_TG3_LINK_UP)) {
  4742. tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
  4743. } else {
  4744. current_link_up = true;
  4745. if (sgsr & SERDES_TG3_SPEED_1000) {
  4746. current_speed = SPEED_1000;
  4747. tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
  4748. } else if (sgsr & SERDES_TG3_SPEED_100) {
  4749. current_speed = SPEED_100;
  4750. tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
  4751. } else {
  4752. current_speed = SPEED_10;
  4753. tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
  4754. }
  4755. if (sgsr & SERDES_TG3_FULL_DUPLEX)
  4756. current_duplex = DUPLEX_FULL;
  4757. else
  4758. current_duplex = DUPLEX_HALF;
  4759. }
  4760. tw32_f(MAC_MODE, tp->mac_mode);
  4761. udelay(40);
  4762. tg3_clear_mac_status(tp);
  4763. goto fiber_setup_done;
  4764. }
  4765. tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
  4766. tw32_f(MAC_MODE, tp->mac_mode);
  4767. udelay(40);
  4768. tg3_clear_mac_status(tp);
  4769. if (force_reset)
  4770. tg3_phy_reset(tp);
  4771. tp->link_config.rmt_adv = 0;
  4772. err |= tg3_readphy(tp, MII_BMSR, &bmsr);
  4773. err |= tg3_readphy(tp, MII_BMSR, &bmsr);
  4774. if (tg3_asic_rev(tp) == ASIC_REV_5714) {
  4775. if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
  4776. bmsr |= BMSR_LSTATUS;
  4777. else
  4778. bmsr &= ~BMSR_LSTATUS;
  4779. }
  4780. err |= tg3_readphy(tp, MII_BMCR, &bmcr);
  4781. if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
  4782. (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
  4783. /* do nothing, just check for link up at the end */
  4784. } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
  4785. u32 adv, newadv;
  4786. err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
  4787. newadv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
  4788. ADVERTISE_1000XPAUSE |
  4789. ADVERTISE_1000XPSE_ASYM |
  4790. ADVERTISE_SLCT);
  4791. newadv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
  4792. newadv |= ethtool_adv_to_mii_adv_x(tp->link_config.advertising);
  4793. if ((newadv != adv) || !(bmcr & BMCR_ANENABLE)) {
  4794. tg3_writephy(tp, MII_ADVERTISE, newadv);
  4795. bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
  4796. tg3_writephy(tp, MII_BMCR, bmcr);
  4797. tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
  4798. tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
  4799. tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
  4800. return err;
  4801. }
  4802. } else {
  4803. u32 new_bmcr;
  4804. bmcr &= ~BMCR_SPEED1000;
  4805. new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
  4806. if (tp->link_config.duplex == DUPLEX_FULL)
  4807. new_bmcr |= BMCR_FULLDPLX;
  4808. if (new_bmcr != bmcr) {
  4809. /* BMCR_SPEED1000 is a reserved bit that needs
  4810. * to be set on write.
  4811. */
  4812. new_bmcr |= BMCR_SPEED1000;
  4813. /* Force a linkdown */
  4814. if (tp->link_up) {
  4815. u32 adv;
  4816. err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
  4817. adv &= ~(ADVERTISE_1000XFULL |
  4818. ADVERTISE_1000XHALF |
  4819. ADVERTISE_SLCT);
  4820. tg3_writephy(tp, MII_ADVERTISE, adv);
  4821. tg3_writephy(tp, MII_BMCR, bmcr |
  4822. BMCR_ANRESTART |
  4823. BMCR_ANENABLE);
  4824. udelay(10);
  4825. tg3_carrier_off(tp);
  4826. }
  4827. tg3_writephy(tp, MII_BMCR, new_bmcr);
  4828. bmcr = new_bmcr;
  4829. err |= tg3_readphy(tp, MII_BMSR, &bmsr);
  4830. err |= tg3_readphy(tp, MII_BMSR, &bmsr);
  4831. if (tg3_asic_rev(tp) == ASIC_REV_5714) {
  4832. if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
  4833. bmsr |= BMSR_LSTATUS;
  4834. else
  4835. bmsr &= ~BMSR_LSTATUS;
  4836. }
  4837. tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
  4838. }
  4839. }
  4840. if (bmsr & BMSR_LSTATUS) {
  4841. current_speed = SPEED_1000;
  4842. current_link_up = true;
  4843. if (bmcr & BMCR_FULLDPLX)
  4844. current_duplex = DUPLEX_FULL;
  4845. else
  4846. current_duplex = DUPLEX_HALF;
  4847. local_adv = 0;
  4848. remote_adv = 0;
  4849. if (bmcr & BMCR_ANENABLE) {
  4850. u32 common;
  4851. err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
  4852. err |= tg3_readphy(tp, MII_LPA, &remote_adv);
  4853. common = local_adv & remote_adv;
  4854. if (common & (ADVERTISE_1000XHALF |
  4855. ADVERTISE_1000XFULL)) {
  4856. if (common & ADVERTISE_1000XFULL)
  4857. current_duplex = DUPLEX_FULL;
  4858. else
  4859. current_duplex = DUPLEX_HALF;
  4860. tp->link_config.rmt_adv =
  4861. mii_adv_to_ethtool_adv_x(remote_adv);
  4862. } else if (!tg3_flag(tp, 5780_CLASS)) {
  4863. /* Link is up via parallel detect */
  4864. } else {
  4865. current_link_up = false;
  4866. }
  4867. }
  4868. }
  4869. fiber_setup_done:
  4870. if (current_link_up && current_duplex == DUPLEX_FULL)
  4871. tg3_setup_flow_control(tp, local_adv, remote_adv);
  4872. tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
  4873. if (tp->link_config.active_duplex == DUPLEX_HALF)
  4874. tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
  4875. tw32_f(MAC_MODE, tp->mac_mode);
  4876. udelay(40);
  4877. tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
  4878. tp->link_config.active_speed = current_speed;
  4879. tp->link_config.active_duplex = current_duplex;
  4880. tg3_test_and_report_link_chg(tp, current_link_up);
  4881. return err;
  4882. }
  4883. static void tg3_serdes_parallel_detect(struct tg3 *tp)
  4884. {
  4885. if (tp->serdes_counter) {
  4886. /* Give autoneg time to complete. */
  4887. tp->serdes_counter--;
  4888. return;
  4889. }
  4890. if (!tp->link_up &&
  4891. (tp->link_config.autoneg == AUTONEG_ENABLE)) {
  4892. u32 bmcr;
  4893. tg3_readphy(tp, MII_BMCR, &bmcr);
  4894. if (bmcr & BMCR_ANENABLE) {
  4895. u32 phy1, phy2;
  4896. /* Select shadow register 0x1f */
  4897. tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00);
  4898. tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1);
  4899. /* Select expansion interrupt status register */
  4900. tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
  4901. MII_TG3_DSP_EXP1_INT_STAT);
  4902. tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
  4903. tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
  4904. if ((phy1 & 0x10) && !(phy2 & 0x20)) {
  4905. /* We have signal detect and not receiving
  4906. * config code words, link is up by parallel
  4907. * detection.
  4908. */
  4909. bmcr &= ~BMCR_ANENABLE;
  4910. bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
  4911. tg3_writephy(tp, MII_BMCR, bmcr);
  4912. tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT;
  4913. }
  4914. }
  4915. } else if (tp->link_up &&
  4916. (tp->link_config.autoneg == AUTONEG_ENABLE) &&
  4917. (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
  4918. u32 phy2;
  4919. /* Select expansion interrupt status register */
  4920. tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
  4921. MII_TG3_DSP_EXP1_INT_STAT);
  4922. tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
  4923. if (phy2 & 0x20) {
  4924. u32 bmcr;
  4925. /* Config code words received, turn on autoneg. */
  4926. tg3_readphy(tp, MII_BMCR, &bmcr);
  4927. tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
  4928. tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
  4929. }
  4930. }
  4931. }
  4932. static int tg3_setup_phy(struct tg3 *tp, bool force_reset)
  4933. {
  4934. u32 val;
  4935. int err;
  4936. if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
  4937. err = tg3_setup_fiber_phy(tp, force_reset);
  4938. else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
  4939. err = tg3_setup_fiber_mii_phy(tp, force_reset);
  4940. else
  4941. err = tg3_setup_copper_phy(tp, force_reset);
  4942. if (tg3_chip_rev(tp) == CHIPREV_5784_AX) {
  4943. u32 scale;
  4944. val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
  4945. if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
  4946. scale = 65;
  4947. else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
  4948. scale = 6;
  4949. else
  4950. scale = 12;
  4951. val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
  4952. val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
  4953. tw32(GRC_MISC_CFG, val);
  4954. }
  4955. val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
  4956. (6 << TX_LENGTHS_IPG_SHIFT);
  4957. if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
  4958. tg3_asic_rev(tp) == ASIC_REV_5762)
  4959. val |= tr32(MAC_TX_LENGTHS) &
  4960. (TX_LENGTHS_JMB_FRM_LEN_MSK |
  4961. TX_LENGTHS_CNT_DWN_VAL_MSK);
  4962. if (tp->link_config.active_speed == SPEED_1000 &&
  4963. tp->link_config.active_duplex == DUPLEX_HALF)
  4964. tw32(MAC_TX_LENGTHS, val |
  4965. (0xff << TX_LENGTHS_SLOT_TIME_SHIFT));
  4966. else
  4967. tw32(MAC_TX_LENGTHS, val |
  4968. (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
  4969. if (!tg3_flag(tp, 5705_PLUS)) {
  4970. if (tp->link_up) {
  4971. tw32(HOSTCC_STAT_COAL_TICKS,
  4972. tp->coal.stats_block_coalesce_usecs);
  4973. } else {
  4974. tw32(HOSTCC_STAT_COAL_TICKS, 0);
  4975. }
  4976. }
  4977. if (tg3_flag(tp, ASPM_WORKAROUND)) {
  4978. val = tr32(PCIE_PWR_MGMT_THRESH);
  4979. if (!tp->link_up)
  4980. val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
  4981. tp->pwrmgmt_thresh;
  4982. else
  4983. val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
  4984. tw32(PCIE_PWR_MGMT_THRESH, val);
  4985. }
  4986. return err;
  4987. }
  4988. /* tp->lock must be held */
  4989. static u64 tg3_refclk_read(struct tg3 *tp)
  4990. {
  4991. u64 stamp = tr32(TG3_EAV_REF_CLCK_LSB);
  4992. return stamp | (u64)tr32(TG3_EAV_REF_CLCK_MSB) << 32;
  4993. }
  4994. /* tp->lock must be held */
  4995. static void tg3_refclk_write(struct tg3 *tp, u64 newval)
  4996. {
  4997. u32 clock_ctl = tr32(TG3_EAV_REF_CLCK_CTL);
  4998. tw32(TG3_EAV_REF_CLCK_CTL, clock_ctl | TG3_EAV_REF_CLCK_CTL_STOP);
  4999. tw32(TG3_EAV_REF_CLCK_LSB, newval & 0xffffffff);
  5000. tw32(TG3_EAV_REF_CLCK_MSB, newval >> 32);
  5001. tw32_f(TG3_EAV_REF_CLCK_CTL, clock_ctl | TG3_EAV_REF_CLCK_CTL_RESUME);
  5002. }
  5003. static inline void tg3_full_lock(struct tg3 *tp, int irq_sync);
  5004. static inline void tg3_full_unlock(struct tg3 *tp);
  5005. static int tg3_get_ts_info(struct net_device *dev, struct ethtool_ts_info *info)
  5006. {
  5007. struct tg3 *tp = netdev_priv(dev);
  5008. info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
  5009. SOF_TIMESTAMPING_RX_SOFTWARE |
  5010. SOF_TIMESTAMPING_SOFTWARE;
  5011. if (tg3_flag(tp, PTP_CAPABLE)) {
  5012. info->so_timestamping |= SOF_TIMESTAMPING_TX_HARDWARE |
  5013. SOF_TIMESTAMPING_RX_HARDWARE |
  5014. SOF_TIMESTAMPING_RAW_HARDWARE;
  5015. }
  5016. if (tp->ptp_clock)
  5017. info->phc_index = ptp_clock_index(tp->ptp_clock);
  5018. else
  5019. info->phc_index = -1;
  5020. info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON);
  5021. info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
  5022. (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
  5023. (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
  5024. (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT);
  5025. return 0;
  5026. }
  5027. static int tg3_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
  5028. {
  5029. struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
  5030. bool neg_adj = false;
  5031. u32 correction = 0;
  5032. if (ppb < 0) {
  5033. neg_adj = true;
  5034. ppb = -ppb;
  5035. }
  5036. /* Frequency adjustment is performed using hardware with a 24 bit
  5037. * accumulator and a programmable correction value. On each clk, the
  5038. * correction value gets added to the accumulator and when it
  5039. * overflows, the time counter is incremented/decremented.
  5040. *
  5041. * So conversion from ppb to correction value is
  5042. * ppb * (1 << 24) / 1000000000
  5043. */
  5044. correction = div_u64((u64)ppb * (1 << 24), 1000000000ULL) &
  5045. TG3_EAV_REF_CLK_CORRECT_MASK;
  5046. tg3_full_lock(tp, 0);
  5047. if (correction)
  5048. tw32(TG3_EAV_REF_CLK_CORRECT_CTL,
  5049. TG3_EAV_REF_CLK_CORRECT_EN |
  5050. (neg_adj ? TG3_EAV_REF_CLK_CORRECT_NEG : 0) | correction);
  5051. else
  5052. tw32(TG3_EAV_REF_CLK_CORRECT_CTL, 0);
  5053. tg3_full_unlock(tp);
  5054. return 0;
  5055. }
  5056. static int tg3_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
  5057. {
  5058. struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
  5059. tg3_full_lock(tp, 0);
  5060. tp->ptp_adjust += delta;
  5061. tg3_full_unlock(tp);
  5062. return 0;
  5063. }
  5064. static int tg3_ptp_gettime(struct ptp_clock_info *ptp, struct timespec *ts)
  5065. {
  5066. u64 ns;
  5067. u32 remainder;
  5068. struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
  5069. tg3_full_lock(tp, 0);
  5070. ns = tg3_refclk_read(tp);
  5071. ns += tp->ptp_adjust;
  5072. tg3_full_unlock(tp);
  5073. ts->tv_sec = div_u64_rem(ns, 1000000000, &remainder);
  5074. ts->tv_nsec = remainder;
  5075. return 0;
  5076. }
  5077. static int tg3_ptp_settime(struct ptp_clock_info *ptp,
  5078. const struct timespec *ts)
  5079. {
  5080. u64 ns;
  5081. struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
  5082. ns = timespec_to_ns(ts);
  5083. tg3_full_lock(tp, 0);
  5084. tg3_refclk_write(tp, ns);
  5085. tp->ptp_adjust = 0;
  5086. tg3_full_unlock(tp);
  5087. return 0;
  5088. }
  5089. static int tg3_ptp_enable(struct ptp_clock_info *ptp,
  5090. struct ptp_clock_request *rq, int on)
  5091. {
  5092. struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
  5093. u32 clock_ctl;
  5094. int rval = 0;
  5095. switch (rq->type) {
  5096. case PTP_CLK_REQ_PEROUT:
  5097. if (rq->perout.index != 0)
  5098. return -EINVAL;
  5099. tg3_full_lock(tp, 0);
  5100. clock_ctl = tr32(TG3_EAV_REF_CLCK_CTL);
  5101. clock_ctl &= ~TG3_EAV_CTL_TSYNC_GPIO_MASK;
  5102. if (on) {
  5103. u64 nsec;
  5104. nsec = rq->perout.start.sec * 1000000000ULL +
  5105. rq->perout.start.nsec;
  5106. if (rq->perout.period.sec || rq->perout.period.nsec) {
  5107. netdev_warn(tp->dev,
  5108. "Device supports only a one-shot timesync output, period must be 0\n");
  5109. rval = -EINVAL;
  5110. goto err_out;
  5111. }
  5112. if (nsec & (1ULL << 63)) {
  5113. netdev_warn(tp->dev,
  5114. "Start value (nsec) is over limit. Maximum size of start is only 63 bits\n");
  5115. rval = -EINVAL;
  5116. goto err_out;
  5117. }
  5118. tw32(TG3_EAV_WATCHDOG0_LSB, (nsec & 0xffffffff));
  5119. tw32(TG3_EAV_WATCHDOG0_MSB,
  5120. TG3_EAV_WATCHDOG0_EN |
  5121. ((nsec >> 32) & TG3_EAV_WATCHDOG_MSB_MASK));
  5122. tw32(TG3_EAV_REF_CLCK_CTL,
  5123. clock_ctl | TG3_EAV_CTL_TSYNC_WDOG0);
  5124. } else {
  5125. tw32(TG3_EAV_WATCHDOG0_MSB, 0);
  5126. tw32(TG3_EAV_REF_CLCK_CTL, clock_ctl);
  5127. }
  5128. err_out:
  5129. tg3_full_unlock(tp);
  5130. return rval;
  5131. default:
  5132. break;
  5133. }
  5134. return -EOPNOTSUPP;
  5135. }
  5136. static const struct ptp_clock_info tg3_ptp_caps = {
  5137. .owner = THIS_MODULE,
  5138. .name = "tg3 clock",
  5139. .max_adj = 250000000,
  5140. .n_alarm = 0,
  5141. .n_ext_ts = 0,
  5142. .n_per_out = 1,
  5143. .pps = 0,
  5144. .adjfreq = tg3_ptp_adjfreq,
  5145. .adjtime = tg3_ptp_adjtime,
  5146. .gettime = tg3_ptp_gettime,
  5147. .settime = tg3_ptp_settime,
  5148. .enable = tg3_ptp_enable,
  5149. };
  5150. static void tg3_hwclock_to_timestamp(struct tg3 *tp, u64 hwclock,
  5151. struct skb_shared_hwtstamps *timestamp)
  5152. {
  5153. memset(timestamp, 0, sizeof(struct skb_shared_hwtstamps));
  5154. timestamp->hwtstamp = ns_to_ktime((hwclock & TG3_TSTAMP_MASK) +
  5155. tp->ptp_adjust);
  5156. }
  5157. /* tp->lock must be held */
  5158. static void tg3_ptp_init(struct tg3 *tp)
  5159. {
  5160. if (!tg3_flag(tp, PTP_CAPABLE))
  5161. return;
  5162. /* Initialize the hardware clock to the system time. */
  5163. tg3_refclk_write(tp, ktime_to_ns(ktime_get_real()));
  5164. tp->ptp_adjust = 0;
  5165. tp->ptp_info = tg3_ptp_caps;
  5166. }
  5167. /* tp->lock must be held */
  5168. static void tg3_ptp_resume(struct tg3 *tp)
  5169. {
  5170. if (!tg3_flag(tp, PTP_CAPABLE))
  5171. return;
  5172. tg3_refclk_write(tp, ktime_to_ns(ktime_get_real()) + tp->ptp_adjust);
  5173. tp->ptp_adjust = 0;
  5174. }
  5175. static void tg3_ptp_fini(struct tg3 *tp)
  5176. {
  5177. if (!tg3_flag(tp, PTP_CAPABLE) || !tp->ptp_clock)
  5178. return;
  5179. ptp_clock_unregister(tp->ptp_clock);
  5180. tp->ptp_clock = NULL;
  5181. tp->ptp_adjust = 0;
  5182. }
  5183. static inline int tg3_irq_sync(struct tg3 *tp)
  5184. {
  5185. return tp->irq_sync;
  5186. }
  5187. static inline void tg3_rd32_loop(struct tg3 *tp, u32 *dst, u32 off, u32 len)
  5188. {
  5189. int i;
  5190. dst = (u32 *)((u8 *)dst + off);
  5191. for (i = 0; i < len; i += sizeof(u32))
  5192. *dst++ = tr32(off + i);
  5193. }
  5194. static void tg3_dump_legacy_regs(struct tg3 *tp, u32 *regs)
  5195. {
  5196. tg3_rd32_loop(tp, regs, TG3PCI_VENDOR, 0xb0);
  5197. tg3_rd32_loop(tp, regs, MAILBOX_INTERRUPT_0, 0x200);
  5198. tg3_rd32_loop(tp, regs, MAC_MODE, 0x4f0);
  5199. tg3_rd32_loop(tp, regs, SNDDATAI_MODE, 0xe0);
  5200. tg3_rd32_loop(tp, regs, SNDDATAC_MODE, 0x04);
  5201. tg3_rd32_loop(tp, regs, SNDBDS_MODE, 0x80);
  5202. tg3_rd32_loop(tp, regs, SNDBDI_MODE, 0x48);
  5203. tg3_rd32_loop(tp, regs, SNDBDC_MODE, 0x04);
  5204. tg3_rd32_loop(tp, regs, RCVLPC_MODE, 0x20);
  5205. tg3_rd32_loop(tp, regs, RCVLPC_SELLST_BASE, 0x15c);
  5206. tg3_rd32_loop(tp, regs, RCVDBDI_MODE, 0x0c);
  5207. tg3_rd32_loop(tp, regs, RCVDBDI_JUMBO_BD, 0x3c);
  5208. tg3_rd32_loop(tp, regs, RCVDBDI_BD_PROD_IDX_0, 0x44);
  5209. tg3_rd32_loop(tp, regs, RCVDCC_MODE, 0x04);
  5210. tg3_rd32_loop(tp, regs, RCVBDI_MODE, 0x20);
  5211. tg3_rd32_loop(tp, regs, RCVCC_MODE, 0x14);
  5212. tg3_rd32_loop(tp, regs, RCVLSC_MODE, 0x08);
  5213. tg3_rd32_loop(tp, regs, MBFREE_MODE, 0x08);
  5214. tg3_rd32_loop(tp, regs, HOSTCC_MODE, 0x100);
  5215. if (tg3_flag(tp, SUPPORT_MSIX))
  5216. tg3_rd32_loop(tp, regs, HOSTCC_RXCOL_TICKS_VEC1, 0x180);
  5217. tg3_rd32_loop(tp, regs, MEMARB_MODE, 0x10);
  5218. tg3_rd32_loop(tp, regs, BUFMGR_MODE, 0x58);
  5219. tg3_rd32_loop(tp, regs, RDMAC_MODE, 0x08);
  5220. tg3_rd32_loop(tp, regs, WDMAC_MODE, 0x08);
  5221. tg3_rd32_loop(tp, regs, RX_CPU_MODE, 0x04);
  5222. tg3_rd32_loop(tp, regs, RX_CPU_STATE, 0x04);
  5223. tg3_rd32_loop(tp, regs, RX_CPU_PGMCTR, 0x04);
  5224. tg3_rd32_loop(tp, regs, RX_CPU_HWBKPT, 0x04);
  5225. if (!tg3_flag(tp, 5705_PLUS)) {
  5226. tg3_rd32_loop(tp, regs, TX_CPU_MODE, 0x04);
  5227. tg3_rd32_loop(tp, regs, TX_CPU_STATE, 0x04);
  5228. tg3_rd32_loop(tp, regs, TX_CPU_PGMCTR, 0x04);
  5229. }
  5230. tg3_rd32_loop(tp, regs, GRCMBOX_INTERRUPT_0, 0x110);
  5231. tg3_rd32_loop(tp, regs, FTQ_RESET, 0x120);
  5232. tg3_rd32_loop(tp, regs, MSGINT_MODE, 0x0c);
  5233. tg3_rd32_loop(tp, regs, DMAC_MODE, 0x04);
  5234. tg3_rd32_loop(tp, regs, GRC_MODE, 0x4c);
  5235. if (tg3_flag(tp, NVRAM))
  5236. tg3_rd32_loop(tp, regs, NVRAM_CMD, 0x24);
  5237. }
  5238. static void tg3_dump_state(struct tg3 *tp)
  5239. {
  5240. int i;
  5241. u32 *regs;
  5242. regs = kzalloc(TG3_REG_BLK_SIZE, GFP_ATOMIC);
  5243. if (!regs)
  5244. return;
  5245. if (tg3_flag(tp, PCI_EXPRESS)) {
  5246. /* Read up to but not including private PCI registers */
  5247. for (i = 0; i < TG3_PCIE_TLDLPL_PORT; i += sizeof(u32))
  5248. regs[i / sizeof(u32)] = tr32(i);
  5249. } else
  5250. tg3_dump_legacy_regs(tp, regs);
  5251. for (i = 0; i < TG3_REG_BLK_SIZE / sizeof(u32); i += 4) {
  5252. if (!regs[i + 0] && !regs[i + 1] &&
  5253. !regs[i + 2] && !regs[i + 3])
  5254. continue;
  5255. netdev_err(tp->dev, "0x%08x: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
  5256. i * 4,
  5257. regs[i + 0], regs[i + 1], regs[i + 2], regs[i + 3]);
  5258. }
  5259. kfree(regs);
  5260. for (i = 0; i < tp->irq_cnt; i++) {
  5261. struct tg3_napi *tnapi = &tp->napi[i];
  5262. /* SW status block */
  5263. netdev_err(tp->dev,
  5264. "%d: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
  5265. i,
  5266. tnapi->hw_status->status,
  5267. tnapi->hw_status->status_tag,
  5268. tnapi->hw_status->rx_jumbo_consumer,
  5269. tnapi->hw_status->rx_consumer,
  5270. tnapi->hw_status->rx_mini_consumer,
  5271. tnapi->hw_status->idx[0].rx_producer,
  5272. tnapi->hw_status->idx[0].tx_consumer);
  5273. netdev_err(tp->dev,
  5274. "%d: NAPI info [%08x:%08x:(%04x:%04x:%04x):%04x:(%04x:%04x:%04x:%04x)]\n",
  5275. i,
  5276. tnapi->last_tag, tnapi->last_irq_tag,
  5277. tnapi->tx_prod, tnapi->tx_cons, tnapi->tx_pending,
  5278. tnapi->rx_rcb_ptr,
  5279. tnapi->prodring.rx_std_prod_idx,
  5280. tnapi->prodring.rx_std_cons_idx,
  5281. tnapi->prodring.rx_jmb_prod_idx,
  5282. tnapi->prodring.rx_jmb_cons_idx);
  5283. }
  5284. }
  5285. /* This is called whenever we suspect that the system chipset is re-
  5286. * ordering the sequence of MMIO to the tx send mailbox. The symptom
  5287. * is bogus tx completions. We try to recover by setting the
  5288. * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
  5289. * in the workqueue.
  5290. */
  5291. static void tg3_tx_recover(struct tg3 *tp)
  5292. {
  5293. BUG_ON(tg3_flag(tp, MBOX_WRITE_REORDER) ||
  5294. tp->write32_tx_mbox == tg3_write_indirect_mbox);
  5295. netdev_warn(tp->dev,
  5296. "The system may be re-ordering memory-mapped I/O "
  5297. "cycles to the network device, attempting to recover. "
  5298. "Please report the problem to the driver maintainer "
  5299. "and include system chipset information.\n");
  5300. tg3_flag_set(tp, TX_RECOVERY_PENDING);
  5301. }
  5302. static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
  5303. {
  5304. /* Tell compiler to fetch tx indices from memory. */
  5305. barrier();
  5306. return tnapi->tx_pending -
  5307. ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
  5308. }
  5309. /* Tigon3 never reports partial packet sends. So we do not
  5310. * need special logic to handle SKBs that have not had all
  5311. * of their frags sent yet, like SunGEM does.
  5312. */
  5313. static void tg3_tx(struct tg3_napi *tnapi)
  5314. {
  5315. struct tg3 *tp = tnapi->tp;
  5316. u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
  5317. u32 sw_idx = tnapi->tx_cons;
  5318. struct netdev_queue *txq;
  5319. int index = tnapi - tp->napi;
  5320. unsigned int pkts_compl = 0, bytes_compl = 0;
  5321. if (tg3_flag(tp, ENABLE_TSS))
  5322. index--;
  5323. txq = netdev_get_tx_queue(tp->dev, index);
  5324. while (sw_idx != hw_idx) {
  5325. struct tg3_tx_ring_info *ri = &tnapi->tx_buffers[sw_idx];
  5326. struct sk_buff *skb = ri->skb;
  5327. int i, tx_bug = 0;
  5328. if (unlikely(skb == NULL)) {
  5329. tg3_tx_recover(tp);
  5330. return;
  5331. }
  5332. if (tnapi->tx_ring[sw_idx].len_flags & TXD_FLAG_HWTSTAMP) {
  5333. struct skb_shared_hwtstamps timestamp;
  5334. u64 hwclock = tr32(TG3_TX_TSTAMP_LSB);
  5335. hwclock |= (u64)tr32(TG3_TX_TSTAMP_MSB) << 32;
  5336. tg3_hwclock_to_timestamp(tp, hwclock, &timestamp);
  5337. skb_tstamp_tx(skb, &timestamp);
  5338. }
  5339. pci_unmap_single(tp->pdev,
  5340. dma_unmap_addr(ri, mapping),
  5341. skb_headlen(skb),
  5342. PCI_DMA_TODEVICE);
  5343. ri->skb = NULL;
  5344. while (ri->fragmented) {
  5345. ri->fragmented = false;
  5346. sw_idx = NEXT_TX(sw_idx);
  5347. ri = &tnapi->tx_buffers[sw_idx];
  5348. }
  5349. sw_idx = NEXT_TX(sw_idx);
  5350. for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
  5351. ri = &tnapi->tx_buffers[sw_idx];
  5352. if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
  5353. tx_bug = 1;
  5354. pci_unmap_page(tp->pdev,
  5355. dma_unmap_addr(ri, mapping),
  5356. skb_frag_size(&skb_shinfo(skb)->frags[i]),
  5357. PCI_DMA_TODEVICE);
  5358. while (ri->fragmented) {
  5359. ri->fragmented = false;
  5360. sw_idx = NEXT_TX(sw_idx);
  5361. ri = &tnapi->tx_buffers[sw_idx];
  5362. }
  5363. sw_idx = NEXT_TX(sw_idx);
  5364. }
  5365. pkts_compl++;
  5366. bytes_compl += skb->len;
  5367. dev_kfree_skb(skb);
  5368. if (unlikely(tx_bug)) {
  5369. tg3_tx_recover(tp);
  5370. return;
  5371. }
  5372. }
  5373. netdev_tx_completed_queue(txq, pkts_compl, bytes_compl);
  5374. tnapi->tx_cons = sw_idx;
  5375. /* Need to make the tx_cons update visible to tg3_start_xmit()
  5376. * before checking for netif_queue_stopped(). Without the
  5377. * memory barrier, there is a small possibility that tg3_start_xmit()
  5378. * will miss it and cause the queue to be stopped forever.
  5379. */
  5380. smp_mb();
  5381. if (unlikely(netif_tx_queue_stopped(txq) &&
  5382. (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
  5383. __netif_tx_lock(txq, smp_processor_id());
  5384. if (netif_tx_queue_stopped(txq) &&
  5385. (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
  5386. netif_tx_wake_queue(txq);
  5387. __netif_tx_unlock(txq);
  5388. }
  5389. }
  5390. static void tg3_frag_free(bool is_frag, void *data)
  5391. {
  5392. if (is_frag)
  5393. put_page(virt_to_head_page(data));
  5394. else
  5395. kfree(data);
  5396. }
  5397. static void tg3_rx_data_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
  5398. {
  5399. unsigned int skb_size = SKB_DATA_ALIGN(map_sz + TG3_RX_OFFSET(tp)) +
  5400. SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
  5401. if (!ri->data)
  5402. return;
  5403. pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),
  5404. map_sz, PCI_DMA_FROMDEVICE);
  5405. tg3_frag_free(skb_size <= PAGE_SIZE, ri->data);
  5406. ri->data = NULL;
  5407. }
  5408. /* Returns size of skb allocated or < 0 on error.
  5409. *
  5410. * We only need to fill in the address because the other members
  5411. * of the RX descriptor are invariant, see tg3_init_rings.
  5412. *
  5413. * Note the purposeful assymetry of cpu vs. chip accesses. For
  5414. * posting buffers we only dirty the first cache line of the RX
  5415. * descriptor (containing the address). Whereas for the RX status
  5416. * buffers the cpu only reads the last cacheline of the RX descriptor
  5417. * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
  5418. */
  5419. static int tg3_alloc_rx_data(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
  5420. u32 opaque_key, u32 dest_idx_unmasked,
  5421. unsigned int *frag_size)
  5422. {
  5423. struct tg3_rx_buffer_desc *desc;
  5424. struct ring_info *map;
  5425. u8 *data;
  5426. dma_addr_t mapping;
  5427. int skb_size, data_size, dest_idx;
  5428. switch (opaque_key) {
  5429. case RXD_OPAQUE_RING_STD:
  5430. dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
  5431. desc = &tpr->rx_std[dest_idx];
  5432. map = &tpr->rx_std_buffers[dest_idx];
  5433. data_size = tp->rx_pkt_map_sz;
  5434. break;
  5435. case RXD_OPAQUE_RING_JUMBO:
  5436. dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
  5437. desc = &tpr->rx_jmb[dest_idx].std;
  5438. map = &tpr->rx_jmb_buffers[dest_idx];
  5439. data_size = TG3_RX_JMB_MAP_SZ;
  5440. break;
  5441. default:
  5442. return -EINVAL;
  5443. }
  5444. /* Do not overwrite any of the map or rp information
  5445. * until we are sure we can commit to a new buffer.
  5446. *
  5447. * Callers depend upon this behavior and assume that
  5448. * we leave everything unchanged if we fail.
  5449. */
  5450. skb_size = SKB_DATA_ALIGN(data_size + TG3_RX_OFFSET(tp)) +
  5451. SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
  5452. if (skb_size <= PAGE_SIZE) {
  5453. data = netdev_alloc_frag(skb_size);
  5454. *frag_size = skb_size;
  5455. } else {
  5456. data = kmalloc(skb_size, GFP_ATOMIC);
  5457. *frag_size = 0;
  5458. }
  5459. if (!data)
  5460. return -ENOMEM;
  5461. mapping = pci_map_single(tp->pdev,
  5462. data + TG3_RX_OFFSET(tp),
  5463. data_size,
  5464. PCI_DMA_FROMDEVICE);
  5465. if (unlikely(pci_dma_mapping_error(tp->pdev, mapping))) {
  5466. tg3_frag_free(skb_size <= PAGE_SIZE, data);
  5467. return -EIO;
  5468. }
  5469. map->data = data;
  5470. dma_unmap_addr_set(map, mapping, mapping);
  5471. desc->addr_hi = ((u64)mapping >> 32);
  5472. desc->addr_lo = ((u64)mapping & 0xffffffff);
  5473. return data_size;
  5474. }
  5475. /* We only need to move over in the address because the other
  5476. * members of the RX descriptor are invariant. See notes above
  5477. * tg3_alloc_rx_data for full details.
  5478. */
  5479. static void tg3_recycle_rx(struct tg3_napi *tnapi,
  5480. struct tg3_rx_prodring_set *dpr,
  5481. u32 opaque_key, int src_idx,
  5482. u32 dest_idx_unmasked)
  5483. {
  5484. struct tg3 *tp = tnapi->tp;
  5485. struct tg3_rx_buffer_desc *src_desc, *dest_desc;
  5486. struct ring_info *src_map, *dest_map;
  5487. struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring;
  5488. int dest_idx;
  5489. switch (opaque_key) {
  5490. case RXD_OPAQUE_RING_STD:
  5491. dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
  5492. dest_desc = &dpr->rx_std[dest_idx];
  5493. dest_map = &dpr->rx_std_buffers[dest_idx];
  5494. src_desc = &spr->rx_std[src_idx];
  5495. src_map = &spr->rx_std_buffers[src_idx];
  5496. break;
  5497. case RXD_OPAQUE_RING_JUMBO:
  5498. dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
  5499. dest_desc = &dpr->rx_jmb[dest_idx].std;
  5500. dest_map = &dpr->rx_jmb_buffers[dest_idx];
  5501. src_desc = &spr->rx_jmb[src_idx].std;
  5502. src_map = &spr->rx_jmb_buffers[src_idx];
  5503. break;
  5504. default:
  5505. return;
  5506. }
  5507. dest_map->data = src_map->data;
  5508. dma_unmap_addr_set(dest_map, mapping,
  5509. dma_unmap_addr(src_map, mapping));
  5510. dest_desc->addr_hi = src_desc->addr_hi;
  5511. dest_desc->addr_lo = src_desc->addr_lo;
  5512. /* Ensure that the update to the skb happens after the physical
  5513. * addresses have been transferred to the new BD location.
  5514. */
  5515. smp_wmb();
  5516. src_map->data = NULL;
  5517. }
  5518. /* The RX ring scheme is composed of multiple rings which post fresh
  5519. * buffers to the chip, and one special ring the chip uses to report
  5520. * status back to the host.
  5521. *
  5522. * The special ring reports the status of received packets to the
  5523. * host. The chip does not write into the original descriptor the
  5524. * RX buffer was obtained from. The chip simply takes the original
  5525. * descriptor as provided by the host, updates the status and length
  5526. * field, then writes this into the next status ring entry.
  5527. *
  5528. * Each ring the host uses to post buffers to the chip is described
  5529. * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
  5530. * it is first placed into the on-chip ram. When the packet's length
  5531. * is known, it walks down the TG3_BDINFO entries to select the ring.
  5532. * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
  5533. * which is within the range of the new packet's length is chosen.
  5534. *
  5535. * The "separate ring for rx status" scheme may sound queer, but it makes
  5536. * sense from a cache coherency perspective. If only the host writes
  5537. * to the buffer post rings, and only the chip writes to the rx status
  5538. * rings, then cache lines never move beyond shared-modified state.
  5539. * If both the host and chip were to write into the same ring, cache line
  5540. * eviction could occur since both entities want it in an exclusive state.
  5541. */
  5542. static int tg3_rx(struct tg3_napi *tnapi, int budget)
  5543. {
  5544. struct tg3 *tp = tnapi->tp;
  5545. u32 work_mask, rx_std_posted = 0;
  5546. u32 std_prod_idx, jmb_prod_idx;
  5547. u32 sw_idx = tnapi->rx_rcb_ptr;
  5548. u16 hw_idx;
  5549. int received;
  5550. struct tg3_rx_prodring_set *tpr = &tnapi->prodring;
  5551. hw_idx = *(tnapi->rx_rcb_prod_idx);
  5552. /*
  5553. * We need to order the read of hw_idx and the read of
  5554. * the opaque cookie.
  5555. */
  5556. rmb();
  5557. work_mask = 0;
  5558. received = 0;
  5559. std_prod_idx = tpr->rx_std_prod_idx;
  5560. jmb_prod_idx = tpr->rx_jmb_prod_idx;
  5561. while (sw_idx != hw_idx && budget > 0) {
  5562. struct ring_info *ri;
  5563. struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
  5564. unsigned int len;
  5565. struct sk_buff *skb;
  5566. dma_addr_t dma_addr;
  5567. u32 opaque_key, desc_idx, *post_ptr;
  5568. u8 *data;
  5569. u64 tstamp = 0;
  5570. desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
  5571. opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
  5572. if (opaque_key == RXD_OPAQUE_RING_STD) {
  5573. ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx];
  5574. dma_addr = dma_unmap_addr(ri, mapping);
  5575. data = ri->data;
  5576. post_ptr = &std_prod_idx;
  5577. rx_std_posted++;
  5578. } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
  5579. ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx];
  5580. dma_addr = dma_unmap_addr(ri, mapping);
  5581. data = ri->data;
  5582. post_ptr = &jmb_prod_idx;
  5583. } else
  5584. goto next_pkt_nopost;
  5585. work_mask |= opaque_key;
  5586. if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
  5587. (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
  5588. drop_it:
  5589. tg3_recycle_rx(tnapi, tpr, opaque_key,
  5590. desc_idx, *post_ptr);
  5591. drop_it_no_recycle:
  5592. /* Other statistics kept track of by card. */
  5593. tp->rx_dropped++;
  5594. goto next_pkt;
  5595. }
  5596. prefetch(data + TG3_RX_OFFSET(tp));
  5597. len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
  5598. ETH_FCS_LEN;
  5599. if ((desc->type_flags & RXD_FLAG_PTPSTAT_MASK) ==
  5600. RXD_FLAG_PTPSTAT_PTPV1 ||
  5601. (desc->type_flags & RXD_FLAG_PTPSTAT_MASK) ==
  5602. RXD_FLAG_PTPSTAT_PTPV2) {
  5603. tstamp = tr32(TG3_RX_TSTAMP_LSB);
  5604. tstamp |= (u64)tr32(TG3_RX_TSTAMP_MSB) << 32;
  5605. }
  5606. if (len > TG3_RX_COPY_THRESH(tp)) {
  5607. int skb_size;
  5608. unsigned int frag_size;
  5609. skb_size = tg3_alloc_rx_data(tp, tpr, opaque_key,
  5610. *post_ptr, &frag_size);
  5611. if (skb_size < 0)
  5612. goto drop_it;
  5613. pci_unmap_single(tp->pdev, dma_addr, skb_size,
  5614. PCI_DMA_FROMDEVICE);
  5615. skb = build_skb(data, frag_size);
  5616. if (!skb) {
  5617. tg3_frag_free(frag_size != 0, data);
  5618. goto drop_it_no_recycle;
  5619. }
  5620. skb_reserve(skb, TG3_RX_OFFSET(tp));
  5621. /* Ensure that the update to the data happens
  5622. * after the usage of the old DMA mapping.
  5623. */
  5624. smp_wmb();
  5625. ri->data = NULL;
  5626. } else {
  5627. tg3_recycle_rx(tnapi, tpr, opaque_key,
  5628. desc_idx, *post_ptr);
  5629. skb = netdev_alloc_skb(tp->dev,
  5630. len + TG3_RAW_IP_ALIGN);
  5631. if (skb == NULL)
  5632. goto drop_it_no_recycle;
  5633. skb_reserve(skb, TG3_RAW_IP_ALIGN);
  5634. pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
  5635. memcpy(skb->data,
  5636. data + TG3_RX_OFFSET(tp),
  5637. len);
  5638. pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
  5639. }
  5640. skb_put(skb, len);
  5641. if (tstamp)
  5642. tg3_hwclock_to_timestamp(tp, tstamp,
  5643. skb_hwtstamps(skb));
  5644. if ((tp->dev->features & NETIF_F_RXCSUM) &&
  5645. (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
  5646. (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
  5647. >> RXD_TCPCSUM_SHIFT) == 0xffff))
  5648. skb->ip_summed = CHECKSUM_UNNECESSARY;
  5649. else
  5650. skb_checksum_none_assert(skb);
  5651. skb->protocol = eth_type_trans(skb, tp->dev);
  5652. if (len > (tp->dev->mtu + ETH_HLEN) &&
  5653. skb->protocol != htons(ETH_P_8021Q)) {
  5654. dev_kfree_skb(skb);
  5655. goto drop_it_no_recycle;
  5656. }
  5657. if (desc->type_flags & RXD_FLAG_VLAN &&
  5658. !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG))
  5659. __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
  5660. desc->err_vlan & RXD_VLAN_MASK);
  5661. napi_gro_receive(&tnapi->napi, skb);
  5662. received++;
  5663. budget--;
  5664. next_pkt:
  5665. (*post_ptr)++;
  5666. if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
  5667. tpr->rx_std_prod_idx = std_prod_idx &
  5668. tp->rx_std_ring_mask;
  5669. tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
  5670. tpr->rx_std_prod_idx);
  5671. work_mask &= ~RXD_OPAQUE_RING_STD;
  5672. rx_std_posted = 0;
  5673. }
  5674. next_pkt_nopost:
  5675. sw_idx++;
  5676. sw_idx &= tp->rx_ret_ring_mask;
  5677. /* Refresh hw_idx to see if there is new work */
  5678. if (sw_idx == hw_idx) {
  5679. hw_idx = *(tnapi->rx_rcb_prod_idx);
  5680. rmb();
  5681. }
  5682. }
  5683. /* ACK the status ring. */
  5684. tnapi->rx_rcb_ptr = sw_idx;
  5685. tw32_rx_mbox(tnapi->consmbox, sw_idx);
  5686. /* Refill RX ring(s). */
  5687. if (!tg3_flag(tp, ENABLE_RSS)) {
  5688. /* Sync BD data before updating mailbox */
  5689. wmb();
  5690. if (work_mask & RXD_OPAQUE_RING_STD) {
  5691. tpr->rx_std_prod_idx = std_prod_idx &
  5692. tp->rx_std_ring_mask;
  5693. tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
  5694. tpr->rx_std_prod_idx);
  5695. }
  5696. if (work_mask & RXD_OPAQUE_RING_JUMBO) {
  5697. tpr->rx_jmb_prod_idx = jmb_prod_idx &
  5698. tp->rx_jmb_ring_mask;
  5699. tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
  5700. tpr->rx_jmb_prod_idx);
  5701. }
  5702. mmiowb();
  5703. } else if (work_mask) {
  5704. /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
  5705. * updated before the producer indices can be updated.
  5706. */
  5707. smp_wmb();
  5708. tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask;
  5709. tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask;
  5710. if (tnapi != &tp->napi[1]) {
  5711. tp->rx_refill = true;
  5712. napi_schedule(&tp->napi[1].napi);
  5713. }
  5714. }
  5715. return received;
  5716. }
  5717. static void tg3_poll_link(struct tg3 *tp)
  5718. {
  5719. /* handle link change and other phy events */
  5720. if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
  5721. struct tg3_hw_status *sblk = tp->napi[0].hw_status;
  5722. if (sblk->status & SD_STATUS_LINK_CHG) {
  5723. sblk->status = SD_STATUS_UPDATED |
  5724. (sblk->status & ~SD_STATUS_LINK_CHG);
  5725. spin_lock(&tp->lock);
  5726. if (tg3_flag(tp, USE_PHYLIB)) {
  5727. tw32_f(MAC_STATUS,
  5728. (MAC_STATUS_SYNC_CHANGED |
  5729. MAC_STATUS_CFG_CHANGED |
  5730. MAC_STATUS_MI_COMPLETION |
  5731. MAC_STATUS_LNKSTATE_CHANGED));
  5732. udelay(40);
  5733. } else
  5734. tg3_setup_phy(tp, false);
  5735. spin_unlock(&tp->lock);
  5736. }
  5737. }
  5738. }
  5739. static int tg3_rx_prodring_xfer(struct tg3 *tp,
  5740. struct tg3_rx_prodring_set *dpr,
  5741. struct tg3_rx_prodring_set *spr)
  5742. {
  5743. u32 si, di, cpycnt, src_prod_idx;
  5744. int i, err = 0;
  5745. while (1) {
  5746. src_prod_idx = spr->rx_std_prod_idx;
  5747. /* Make sure updates to the rx_std_buffers[] entries and the
  5748. * standard producer index are seen in the correct order.
  5749. */
  5750. smp_rmb();
  5751. if (spr->rx_std_cons_idx == src_prod_idx)
  5752. break;
  5753. if (spr->rx_std_cons_idx < src_prod_idx)
  5754. cpycnt = src_prod_idx - spr->rx_std_cons_idx;
  5755. else
  5756. cpycnt = tp->rx_std_ring_mask + 1 -
  5757. spr->rx_std_cons_idx;
  5758. cpycnt = min(cpycnt,
  5759. tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx);
  5760. si = spr->rx_std_cons_idx;
  5761. di = dpr->rx_std_prod_idx;
  5762. for (i = di; i < di + cpycnt; i++) {
  5763. if (dpr->rx_std_buffers[i].data) {
  5764. cpycnt = i - di;
  5765. err = -ENOSPC;
  5766. break;
  5767. }
  5768. }
  5769. if (!cpycnt)
  5770. break;
  5771. /* Ensure that updates to the rx_std_buffers ring and the
  5772. * shadowed hardware producer ring from tg3_recycle_skb() are
  5773. * ordered correctly WRT the skb check above.
  5774. */
  5775. smp_rmb();
  5776. memcpy(&dpr->rx_std_buffers[di],
  5777. &spr->rx_std_buffers[si],
  5778. cpycnt * sizeof(struct ring_info));
  5779. for (i = 0; i < cpycnt; i++, di++, si++) {
  5780. struct tg3_rx_buffer_desc *sbd, *dbd;
  5781. sbd = &spr->rx_std[si];
  5782. dbd = &dpr->rx_std[di];
  5783. dbd->addr_hi = sbd->addr_hi;
  5784. dbd->addr_lo = sbd->addr_lo;
  5785. }
  5786. spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) &
  5787. tp->rx_std_ring_mask;
  5788. dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) &
  5789. tp->rx_std_ring_mask;
  5790. }
  5791. while (1) {
  5792. src_prod_idx = spr->rx_jmb_prod_idx;
  5793. /* Make sure updates to the rx_jmb_buffers[] entries and
  5794. * the jumbo producer index are seen in the correct order.
  5795. */
  5796. smp_rmb();
  5797. if (spr->rx_jmb_cons_idx == src_prod_idx)
  5798. break;
  5799. if (spr->rx_jmb_cons_idx < src_prod_idx)
  5800. cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
  5801. else
  5802. cpycnt = tp->rx_jmb_ring_mask + 1 -
  5803. spr->rx_jmb_cons_idx;
  5804. cpycnt = min(cpycnt,
  5805. tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx);
  5806. si = spr->rx_jmb_cons_idx;
  5807. di = dpr->rx_jmb_prod_idx;
  5808. for (i = di; i < di + cpycnt; i++) {
  5809. if (dpr->rx_jmb_buffers[i].data) {
  5810. cpycnt = i - di;
  5811. err = -ENOSPC;
  5812. break;
  5813. }
  5814. }
  5815. if (!cpycnt)
  5816. break;
  5817. /* Ensure that updates to the rx_jmb_buffers ring and the
  5818. * shadowed hardware producer ring from tg3_recycle_skb() are
  5819. * ordered correctly WRT the skb check above.
  5820. */
  5821. smp_rmb();
  5822. memcpy(&dpr->rx_jmb_buffers[di],
  5823. &spr->rx_jmb_buffers[si],
  5824. cpycnt * sizeof(struct ring_info));
  5825. for (i = 0; i < cpycnt; i++, di++, si++) {
  5826. struct tg3_rx_buffer_desc *sbd, *dbd;
  5827. sbd = &spr->rx_jmb[si].std;
  5828. dbd = &dpr->rx_jmb[di].std;
  5829. dbd->addr_hi = sbd->addr_hi;
  5830. dbd->addr_lo = sbd->addr_lo;
  5831. }
  5832. spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) &
  5833. tp->rx_jmb_ring_mask;
  5834. dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) &
  5835. tp->rx_jmb_ring_mask;
  5836. }
  5837. return err;
  5838. }
  5839. static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
  5840. {
  5841. struct tg3 *tp = tnapi->tp;
  5842. /* run TX completion thread */
  5843. if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
  5844. tg3_tx(tnapi);
  5845. if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
  5846. return work_done;
  5847. }
  5848. if (!tnapi->rx_rcb_prod_idx)
  5849. return work_done;
  5850. /* run RX thread, within the bounds set by NAPI.
  5851. * All RX "locking" is done by ensuring outside
  5852. * code synchronizes with tg3->napi.poll()
  5853. */
  5854. if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
  5855. work_done += tg3_rx(tnapi, budget - work_done);
  5856. if (tg3_flag(tp, ENABLE_RSS) && tnapi == &tp->napi[1]) {
  5857. struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring;
  5858. int i, err = 0;
  5859. u32 std_prod_idx = dpr->rx_std_prod_idx;
  5860. u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
  5861. tp->rx_refill = false;
  5862. for (i = 1; i <= tp->rxq_cnt; i++)
  5863. err |= tg3_rx_prodring_xfer(tp, dpr,
  5864. &tp->napi[i].prodring);
  5865. wmb();
  5866. if (std_prod_idx != dpr->rx_std_prod_idx)
  5867. tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
  5868. dpr->rx_std_prod_idx);
  5869. if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
  5870. tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
  5871. dpr->rx_jmb_prod_idx);
  5872. mmiowb();
  5873. if (err)
  5874. tw32_f(HOSTCC_MODE, tp->coal_now);
  5875. }
  5876. return work_done;
  5877. }
  5878. static inline void tg3_reset_task_schedule(struct tg3 *tp)
  5879. {
  5880. if (!test_and_set_bit(TG3_FLAG_RESET_TASK_PENDING, tp->tg3_flags))
  5881. schedule_work(&tp->reset_task);
  5882. }
  5883. static inline void tg3_reset_task_cancel(struct tg3 *tp)
  5884. {
  5885. cancel_work_sync(&tp->reset_task);
  5886. tg3_flag_clear(tp, RESET_TASK_PENDING);
  5887. tg3_flag_clear(tp, TX_RECOVERY_PENDING);
  5888. }
  5889. static int tg3_poll_msix(struct napi_struct *napi, int budget)
  5890. {
  5891. struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
  5892. struct tg3 *tp = tnapi->tp;
  5893. int work_done = 0;
  5894. struct tg3_hw_status *sblk = tnapi->hw_status;
  5895. while (1) {
  5896. work_done = tg3_poll_work(tnapi, work_done, budget);
  5897. if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
  5898. goto tx_recovery;
  5899. if (unlikely(work_done >= budget))
  5900. break;
  5901. /* tp->last_tag is used in tg3_int_reenable() below
  5902. * to tell the hw how much work has been processed,
  5903. * so we must read it before checking for more work.
  5904. */
  5905. tnapi->last_tag = sblk->status_tag;
  5906. tnapi->last_irq_tag = tnapi->last_tag;
  5907. rmb();
  5908. /* check for RX/TX work to do */
  5909. if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
  5910. *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
  5911. /* This test here is not race free, but will reduce
  5912. * the number of interrupts by looping again.
  5913. */
  5914. if (tnapi == &tp->napi[1] && tp->rx_refill)
  5915. continue;
  5916. napi_complete(napi);
  5917. /* Reenable interrupts. */
  5918. tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
  5919. /* This test here is synchronized by napi_schedule()
  5920. * and napi_complete() to close the race condition.
  5921. */
  5922. if (unlikely(tnapi == &tp->napi[1] && tp->rx_refill)) {
  5923. tw32(HOSTCC_MODE, tp->coalesce_mode |
  5924. HOSTCC_MODE_ENABLE |
  5925. tnapi->coal_now);
  5926. }
  5927. mmiowb();
  5928. break;
  5929. }
  5930. }
  5931. return work_done;
  5932. tx_recovery:
  5933. /* work_done is guaranteed to be less than budget. */
  5934. napi_complete(napi);
  5935. tg3_reset_task_schedule(tp);
  5936. return work_done;
  5937. }
  5938. static void tg3_process_error(struct tg3 *tp)
  5939. {
  5940. u32 val;
  5941. bool real_error = false;
  5942. if (tg3_flag(tp, ERROR_PROCESSED))
  5943. return;
  5944. /* Check Flow Attention register */
  5945. val = tr32(HOSTCC_FLOW_ATTN);
  5946. if (val & ~HOSTCC_FLOW_ATTN_MBUF_LWM) {
  5947. netdev_err(tp->dev, "FLOW Attention error. Resetting chip.\n");
  5948. real_error = true;
  5949. }
  5950. if (tr32(MSGINT_STATUS) & ~MSGINT_STATUS_MSI_REQ) {
  5951. netdev_err(tp->dev, "MSI Status error. Resetting chip.\n");
  5952. real_error = true;
  5953. }
  5954. if (tr32(RDMAC_STATUS) || tr32(WDMAC_STATUS)) {
  5955. netdev_err(tp->dev, "DMA Status error. Resetting chip.\n");
  5956. real_error = true;
  5957. }
  5958. if (!real_error)
  5959. return;
  5960. tg3_dump_state(tp);
  5961. tg3_flag_set(tp, ERROR_PROCESSED);
  5962. tg3_reset_task_schedule(tp);
  5963. }
  5964. static int tg3_poll(struct napi_struct *napi, int budget)
  5965. {
  5966. struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
  5967. struct tg3 *tp = tnapi->tp;
  5968. int work_done = 0;
  5969. struct tg3_hw_status *sblk = tnapi->hw_status;
  5970. while (1) {
  5971. if (sblk->status & SD_STATUS_ERROR)
  5972. tg3_process_error(tp);
  5973. tg3_poll_link(tp);
  5974. work_done = tg3_poll_work(tnapi, work_done, budget);
  5975. if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
  5976. goto tx_recovery;
  5977. if (unlikely(work_done >= budget))
  5978. break;
  5979. if (tg3_flag(tp, TAGGED_STATUS)) {
  5980. /* tp->last_tag is used in tg3_int_reenable() below
  5981. * to tell the hw how much work has been processed,
  5982. * so we must read it before checking for more work.
  5983. */
  5984. tnapi->last_tag = sblk->status_tag;
  5985. tnapi->last_irq_tag = tnapi->last_tag;
  5986. rmb();
  5987. } else
  5988. sblk->status &= ~SD_STATUS_UPDATED;
  5989. if (likely(!tg3_has_work(tnapi))) {
  5990. napi_complete(napi);
  5991. tg3_int_reenable(tnapi);
  5992. break;
  5993. }
  5994. }
  5995. return work_done;
  5996. tx_recovery:
  5997. /* work_done is guaranteed to be less than budget. */
  5998. napi_complete(napi);
  5999. tg3_reset_task_schedule(tp);
  6000. return work_done;
  6001. }
  6002. static void tg3_napi_disable(struct tg3 *tp)
  6003. {
  6004. int i;
  6005. for (i = tp->irq_cnt - 1; i >= 0; i--)
  6006. napi_disable(&tp->napi[i].napi);
  6007. }
  6008. static void tg3_napi_enable(struct tg3 *tp)
  6009. {
  6010. int i;
  6011. for (i = 0; i < tp->irq_cnt; i++)
  6012. napi_enable(&tp->napi[i].napi);
  6013. }
  6014. static void tg3_napi_init(struct tg3 *tp)
  6015. {
  6016. int i;
  6017. netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll, 64);
  6018. for (i = 1; i < tp->irq_cnt; i++)
  6019. netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix, 64);
  6020. }
  6021. static void tg3_napi_fini(struct tg3 *tp)
  6022. {
  6023. int i;
  6024. for (i = 0; i < tp->irq_cnt; i++)
  6025. netif_napi_del(&tp->napi[i].napi);
  6026. }
  6027. static inline void tg3_netif_stop(struct tg3 *tp)
  6028. {
  6029. tp->dev->trans_start = jiffies; /* prevent tx timeout */
  6030. tg3_napi_disable(tp);
  6031. netif_carrier_off(tp->dev);
  6032. netif_tx_disable(tp->dev);
  6033. }
  6034. /* tp->lock must be held */
  6035. static inline void tg3_netif_start(struct tg3 *tp)
  6036. {
  6037. tg3_ptp_resume(tp);
  6038. /* NOTE: unconditional netif_tx_wake_all_queues is only
  6039. * appropriate so long as all callers are assured to
  6040. * have free tx slots (such as after tg3_init_hw)
  6041. */
  6042. netif_tx_wake_all_queues(tp->dev);
  6043. if (tp->link_up)
  6044. netif_carrier_on(tp->dev);
  6045. tg3_napi_enable(tp);
  6046. tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
  6047. tg3_enable_ints(tp);
  6048. }
  6049. static void tg3_irq_quiesce(struct tg3 *tp)
  6050. {
  6051. int i;
  6052. BUG_ON(tp->irq_sync);
  6053. tp->irq_sync = 1;
  6054. smp_mb();
  6055. for (i = 0; i < tp->irq_cnt; i++)
  6056. synchronize_irq(tp->napi[i].irq_vec);
  6057. }
  6058. /* Fully shutdown all tg3 driver activity elsewhere in the system.
  6059. * If irq_sync is non-zero, then the IRQ handler must be synchronized
  6060. * with as well. Most of the time, this is not necessary except when
  6061. * shutting down the device.
  6062. */
  6063. static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
  6064. {
  6065. spin_lock_bh(&tp->lock);
  6066. if (irq_sync)
  6067. tg3_irq_quiesce(tp);
  6068. }
  6069. static inline void tg3_full_unlock(struct tg3 *tp)
  6070. {
  6071. spin_unlock_bh(&tp->lock);
  6072. }
  6073. /* One-shot MSI handler - Chip automatically disables interrupt
  6074. * after sending MSI so driver doesn't have to do it.
  6075. */
  6076. static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
  6077. {
  6078. struct tg3_napi *tnapi = dev_id;
  6079. struct tg3 *tp = tnapi->tp;
  6080. prefetch(tnapi->hw_status);
  6081. if (tnapi->rx_rcb)
  6082. prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
  6083. if (likely(!tg3_irq_sync(tp)))
  6084. napi_schedule(&tnapi->napi);
  6085. return IRQ_HANDLED;
  6086. }
  6087. /* MSI ISR - No need to check for interrupt sharing and no need to
  6088. * flush status block and interrupt mailbox. PCI ordering rules
  6089. * guarantee that MSI will arrive after the status block.
  6090. */
  6091. static irqreturn_t tg3_msi(int irq, void *dev_id)
  6092. {
  6093. struct tg3_napi *tnapi = dev_id;
  6094. struct tg3 *tp = tnapi->tp;
  6095. prefetch(tnapi->hw_status);
  6096. if (tnapi->rx_rcb)
  6097. prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
  6098. /*
  6099. * Writing any value to intr-mbox-0 clears PCI INTA# and
  6100. * chip-internal interrupt pending events.
  6101. * Writing non-zero to intr-mbox-0 additional tells the
  6102. * NIC to stop sending us irqs, engaging "in-intr-handler"
  6103. * event coalescing.
  6104. */
  6105. tw32_mailbox(tnapi->int_mbox, 0x00000001);
  6106. if (likely(!tg3_irq_sync(tp)))
  6107. napi_schedule(&tnapi->napi);
  6108. return IRQ_RETVAL(1);
  6109. }
  6110. static irqreturn_t tg3_interrupt(int irq, void *dev_id)
  6111. {
  6112. struct tg3_napi *tnapi = dev_id;
  6113. struct tg3 *tp = tnapi->tp;
  6114. struct tg3_hw_status *sblk = tnapi->hw_status;
  6115. unsigned int handled = 1;
  6116. /* In INTx mode, it is possible for the interrupt to arrive at
  6117. * the CPU before the status block posted prior to the interrupt.
  6118. * Reading the PCI State register will confirm whether the
  6119. * interrupt is ours and will flush the status block.
  6120. */
  6121. if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
  6122. if (tg3_flag(tp, CHIP_RESETTING) ||
  6123. (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
  6124. handled = 0;
  6125. goto out;
  6126. }
  6127. }
  6128. /*
  6129. * Writing any value to intr-mbox-0 clears PCI INTA# and
  6130. * chip-internal interrupt pending events.
  6131. * Writing non-zero to intr-mbox-0 additional tells the
  6132. * NIC to stop sending us irqs, engaging "in-intr-handler"
  6133. * event coalescing.
  6134. *
  6135. * Flush the mailbox to de-assert the IRQ immediately to prevent
  6136. * spurious interrupts. The flush impacts performance but
  6137. * excessive spurious interrupts can be worse in some cases.
  6138. */
  6139. tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
  6140. if (tg3_irq_sync(tp))
  6141. goto out;
  6142. sblk->status &= ~SD_STATUS_UPDATED;
  6143. if (likely(tg3_has_work(tnapi))) {
  6144. prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
  6145. napi_schedule(&tnapi->napi);
  6146. } else {
  6147. /* No work, shared interrupt perhaps? re-enable
  6148. * interrupts, and flush that PCI write
  6149. */
  6150. tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
  6151. 0x00000000);
  6152. }
  6153. out:
  6154. return IRQ_RETVAL(handled);
  6155. }
  6156. static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
  6157. {
  6158. struct tg3_napi *tnapi = dev_id;
  6159. struct tg3 *tp = tnapi->tp;
  6160. struct tg3_hw_status *sblk = tnapi->hw_status;
  6161. unsigned int handled = 1;
  6162. /* In INTx mode, it is possible for the interrupt to arrive at
  6163. * the CPU before the status block posted prior to the interrupt.
  6164. * Reading the PCI State register will confirm whether the
  6165. * interrupt is ours and will flush the status block.
  6166. */
  6167. if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
  6168. if (tg3_flag(tp, CHIP_RESETTING) ||
  6169. (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
  6170. handled = 0;
  6171. goto out;
  6172. }
  6173. }
  6174. /*
  6175. * writing any value to intr-mbox-0 clears PCI INTA# and
  6176. * chip-internal interrupt pending events.
  6177. * writing non-zero to intr-mbox-0 additional tells the
  6178. * NIC to stop sending us irqs, engaging "in-intr-handler"
  6179. * event coalescing.
  6180. *
  6181. * Flush the mailbox to de-assert the IRQ immediately to prevent
  6182. * spurious interrupts. The flush impacts performance but
  6183. * excessive spurious interrupts can be worse in some cases.
  6184. */
  6185. tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
  6186. /*
  6187. * In a shared interrupt configuration, sometimes other devices'
  6188. * interrupts will scream. We record the current status tag here
  6189. * so that the above check can report that the screaming interrupts
  6190. * are unhandled. Eventually they will be silenced.
  6191. */
  6192. tnapi->last_irq_tag = sblk->status_tag;
  6193. if (tg3_irq_sync(tp))
  6194. goto out;
  6195. prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
  6196. napi_schedule(&tnapi->napi);
  6197. out:
  6198. return IRQ_RETVAL(handled);
  6199. }
  6200. /* ISR for interrupt test */
  6201. static irqreturn_t tg3_test_isr(int irq, void *dev_id)
  6202. {
  6203. struct tg3_napi *tnapi = dev_id;
  6204. struct tg3 *tp = tnapi->tp;
  6205. struct tg3_hw_status *sblk = tnapi->hw_status;
  6206. if ((sblk->status & SD_STATUS_UPDATED) ||
  6207. !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
  6208. tg3_disable_ints(tp);
  6209. return IRQ_RETVAL(1);
  6210. }
  6211. return IRQ_RETVAL(0);
  6212. }
  6213. #ifdef CONFIG_NET_POLL_CONTROLLER
  6214. static void tg3_poll_controller(struct net_device *dev)
  6215. {
  6216. int i;
  6217. struct tg3 *tp = netdev_priv(dev);
  6218. if (tg3_irq_sync(tp))
  6219. return;
  6220. for (i = 0; i < tp->irq_cnt; i++)
  6221. tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
  6222. }
  6223. #endif
  6224. static void tg3_tx_timeout(struct net_device *dev)
  6225. {
  6226. struct tg3 *tp = netdev_priv(dev);
  6227. if (netif_msg_tx_err(tp)) {
  6228. netdev_err(dev, "transmit timed out, resetting\n");
  6229. tg3_dump_state(tp);
  6230. }
  6231. tg3_reset_task_schedule(tp);
  6232. }
  6233. /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
  6234. static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
  6235. {
  6236. u32 base = (u32) mapping & 0xffffffff;
  6237. return (base > 0xffffdcc0) && (base + len + 8 < base);
  6238. }
  6239. /* Test for TSO DMA buffers that cross into regions which are within MSS bytes
  6240. * of any 4GB boundaries: 4G, 8G, etc
  6241. */
  6242. static inline int tg3_4g_tso_overflow_test(struct tg3 *tp, dma_addr_t mapping,
  6243. u32 len, u32 mss)
  6244. {
  6245. if (tg3_asic_rev(tp) == ASIC_REV_5762 && mss) {
  6246. u32 base = (u32) mapping & 0xffffffff;
  6247. return ((base + len + (mss & 0x3fff)) < base);
  6248. }
  6249. return 0;
  6250. }
  6251. /* Test for DMA addresses > 40-bit */
  6252. static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
  6253. int len)
  6254. {
  6255. #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
  6256. if (tg3_flag(tp, 40BIT_DMA_BUG))
  6257. return ((u64) mapping + len) > DMA_BIT_MASK(40);
  6258. return 0;
  6259. #else
  6260. return 0;
  6261. #endif
  6262. }
  6263. static inline void tg3_tx_set_bd(struct tg3_tx_buffer_desc *txbd,
  6264. dma_addr_t mapping, u32 len, u32 flags,
  6265. u32 mss, u32 vlan)
  6266. {
  6267. txbd->addr_hi = ((u64) mapping >> 32);
  6268. txbd->addr_lo = ((u64) mapping & 0xffffffff);
  6269. txbd->len_flags = (len << TXD_LEN_SHIFT) | (flags & 0x0000ffff);
  6270. txbd->vlan_tag = (mss << TXD_MSS_SHIFT) | (vlan << TXD_VLAN_TAG_SHIFT);
  6271. }
  6272. static bool tg3_tx_frag_set(struct tg3_napi *tnapi, u32 *entry, u32 *budget,
  6273. dma_addr_t map, u32 len, u32 flags,
  6274. u32 mss, u32 vlan)
  6275. {
  6276. struct tg3 *tp = tnapi->tp;
  6277. bool hwbug = false;
  6278. if (tg3_flag(tp, SHORT_DMA_BUG) && len <= 8)
  6279. hwbug = true;
  6280. if (tg3_4g_overflow_test(map, len))
  6281. hwbug = true;
  6282. if (tg3_4g_tso_overflow_test(tp, map, len, mss))
  6283. hwbug = true;
  6284. if (tg3_40bit_overflow_test(tp, map, len))
  6285. hwbug = true;
  6286. if (tp->dma_limit) {
  6287. u32 prvidx = *entry;
  6288. u32 tmp_flag = flags & ~TXD_FLAG_END;
  6289. while (len > tp->dma_limit && *budget) {
  6290. u32 frag_len = tp->dma_limit;
  6291. len -= tp->dma_limit;
  6292. /* Avoid the 8byte DMA problem */
  6293. if (len <= 8) {
  6294. len += tp->dma_limit / 2;
  6295. frag_len = tp->dma_limit / 2;
  6296. }
  6297. tnapi->tx_buffers[*entry].fragmented = true;
  6298. tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
  6299. frag_len, tmp_flag, mss, vlan);
  6300. *budget -= 1;
  6301. prvidx = *entry;
  6302. *entry = NEXT_TX(*entry);
  6303. map += frag_len;
  6304. }
  6305. if (len) {
  6306. if (*budget) {
  6307. tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
  6308. len, flags, mss, vlan);
  6309. *budget -= 1;
  6310. *entry = NEXT_TX(*entry);
  6311. } else {
  6312. hwbug = true;
  6313. tnapi->tx_buffers[prvidx].fragmented = false;
  6314. }
  6315. }
  6316. } else {
  6317. tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
  6318. len, flags, mss, vlan);
  6319. *entry = NEXT_TX(*entry);
  6320. }
  6321. return hwbug;
  6322. }
  6323. static void tg3_tx_skb_unmap(struct tg3_napi *tnapi, u32 entry, int last)
  6324. {
  6325. int i;
  6326. struct sk_buff *skb;
  6327. struct tg3_tx_ring_info *txb = &tnapi->tx_buffers[entry];
  6328. skb = txb->skb;
  6329. txb->skb = NULL;
  6330. pci_unmap_single(tnapi->tp->pdev,
  6331. dma_unmap_addr(txb, mapping),
  6332. skb_headlen(skb),
  6333. PCI_DMA_TODEVICE);
  6334. while (txb->fragmented) {
  6335. txb->fragmented = false;
  6336. entry = NEXT_TX(entry);
  6337. txb = &tnapi->tx_buffers[entry];
  6338. }
  6339. for (i = 0; i <= last; i++) {
  6340. const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
  6341. entry = NEXT_TX(entry);
  6342. txb = &tnapi->tx_buffers[entry];
  6343. pci_unmap_page(tnapi->tp->pdev,
  6344. dma_unmap_addr(txb, mapping),
  6345. skb_frag_size(frag), PCI_DMA_TODEVICE);
  6346. while (txb->fragmented) {
  6347. txb->fragmented = false;
  6348. entry = NEXT_TX(entry);
  6349. txb = &tnapi->tx_buffers[entry];
  6350. }
  6351. }
  6352. }
  6353. /* Workaround 4GB and 40-bit hardware DMA bugs. */
  6354. static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
  6355. struct sk_buff **pskb,
  6356. u32 *entry, u32 *budget,
  6357. u32 base_flags, u32 mss, u32 vlan)
  6358. {
  6359. struct tg3 *tp = tnapi->tp;
  6360. struct sk_buff *new_skb, *skb = *pskb;
  6361. dma_addr_t new_addr = 0;
  6362. int ret = 0;
  6363. if (tg3_asic_rev(tp) != ASIC_REV_5701)
  6364. new_skb = skb_copy(skb, GFP_ATOMIC);
  6365. else {
  6366. int more_headroom = 4 - ((unsigned long)skb->data & 3);
  6367. new_skb = skb_copy_expand(skb,
  6368. skb_headroom(skb) + more_headroom,
  6369. skb_tailroom(skb), GFP_ATOMIC);
  6370. }
  6371. if (!new_skb) {
  6372. ret = -1;
  6373. } else {
  6374. /* New SKB is guaranteed to be linear. */
  6375. new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
  6376. PCI_DMA_TODEVICE);
  6377. /* Make sure the mapping succeeded */
  6378. if (pci_dma_mapping_error(tp->pdev, new_addr)) {
  6379. dev_kfree_skb(new_skb);
  6380. ret = -1;
  6381. } else {
  6382. u32 save_entry = *entry;
  6383. base_flags |= TXD_FLAG_END;
  6384. tnapi->tx_buffers[*entry].skb = new_skb;
  6385. dma_unmap_addr_set(&tnapi->tx_buffers[*entry],
  6386. mapping, new_addr);
  6387. if (tg3_tx_frag_set(tnapi, entry, budget, new_addr,
  6388. new_skb->len, base_flags,
  6389. mss, vlan)) {
  6390. tg3_tx_skb_unmap(tnapi, save_entry, -1);
  6391. dev_kfree_skb(new_skb);
  6392. ret = -1;
  6393. }
  6394. }
  6395. }
  6396. dev_kfree_skb(skb);
  6397. *pskb = new_skb;
  6398. return ret;
  6399. }
  6400. static netdev_tx_t tg3_start_xmit(struct sk_buff *, struct net_device *);
  6401. /* Use GSO to workaround a rare TSO bug that may be triggered when the
  6402. * TSO header is greater than 80 bytes.
  6403. */
  6404. static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
  6405. {
  6406. struct sk_buff *segs, *nskb;
  6407. u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
  6408. /* Estimate the number of fragments in the worst case */
  6409. if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
  6410. netif_stop_queue(tp->dev);
  6411. /* netif_tx_stop_queue() must be done before checking
  6412. * checking tx index in tg3_tx_avail() below, because in
  6413. * tg3_tx(), we update tx index before checking for
  6414. * netif_tx_queue_stopped().
  6415. */
  6416. smp_mb();
  6417. if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
  6418. return NETDEV_TX_BUSY;
  6419. netif_wake_queue(tp->dev);
  6420. }
  6421. segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
  6422. if (IS_ERR(segs))
  6423. goto tg3_tso_bug_end;
  6424. do {
  6425. nskb = segs;
  6426. segs = segs->next;
  6427. nskb->next = NULL;
  6428. tg3_start_xmit(nskb, tp->dev);
  6429. } while (segs);
  6430. tg3_tso_bug_end:
  6431. dev_kfree_skb(skb);
  6432. return NETDEV_TX_OK;
  6433. }
  6434. /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
  6435. * support TG3_FLAG_HW_TSO_1 or firmware TSO only.
  6436. */
  6437. static netdev_tx_t tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
  6438. {
  6439. struct tg3 *tp = netdev_priv(dev);
  6440. u32 len, entry, base_flags, mss, vlan = 0;
  6441. u32 budget;
  6442. int i = -1, would_hit_hwbug;
  6443. dma_addr_t mapping;
  6444. struct tg3_napi *tnapi;
  6445. struct netdev_queue *txq;
  6446. unsigned int last;
  6447. txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
  6448. tnapi = &tp->napi[skb_get_queue_mapping(skb)];
  6449. if (tg3_flag(tp, ENABLE_TSS))
  6450. tnapi++;
  6451. budget = tg3_tx_avail(tnapi);
  6452. /* We are running in BH disabled context with netif_tx_lock
  6453. * and TX reclaim runs via tp->napi.poll inside of a software
  6454. * interrupt. Furthermore, IRQ processing runs lockless so we have
  6455. * no IRQ context deadlocks to worry about either. Rejoice!
  6456. */
  6457. if (unlikely(budget <= (skb_shinfo(skb)->nr_frags + 1))) {
  6458. if (!netif_tx_queue_stopped(txq)) {
  6459. netif_tx_stop_queue(txq);
  6460. /* This is a hard error, log it. */
  6461. netdev_err(dev,
  6462. "BUG! Tx Ring full when queue awake!\n");
  6463. }
  6464. return NETDEV_TX_BUSY;
  6465. }
  6466. entry = tnapi->tx_prod;
  6467. base_flags = 0;
  6468. if (skb->ip_summed == CHECKSUM_PARTIAL)
  6469. base_flags |= TXD_FLAG_TCPUDP_CSUM;
  6470. mss = skb_shinfo(skb)->gso_size;
  6471. if (mss) {
  6472. struct iphdr *iph;
  6473. u32 tcp_opt_len, hdr_len;
  6474. if (skb_header_cloned(skb) &&
  6475. pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
  6476. goto drop;
  6477. iph = ip_hdr(skb);
  6478. tcp_opt_len = tcp_optlen(skb);
  6479. hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb) - ETH_HLEN;
  6480. if (!skb_is_gso_v6(skb)) {
  6481. iph->check = 0;
  6482. iph->tot_len = htons(mss + hdr_len);
  6483. }
  6484. if (unlikely((ETH_HLEN + hdr_len) > 80) &&
  6485. tg3_flag(tp, TSO_BUG))
  6486. return tg3_tso_bug(tp, skb);
  6487. base_flags |= (TXD_FLAG_CPU_PRE_DMA |
  6488. TXD_FLAG_CPU_POST_DMA);
  6489. if (tg3_flag(tp, HW_TSO_1) ||
  6490. tg3_flag(tp, HW_TSO_2) ||
  6491. tg3_flag(tp, HW_TSO_3)) {
  6492. tcp_hdr(skb)->check = 0;
  6493. base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
  6494. } else
  6495. tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
  6496. iph->daddr, 0,
  6497. IPPROTO_TCP,
  6498. 0);
  6499. if (tg3_flag(tp, HW_TSO_3)) {
  6500. mss |= (hdr_len & 0xc) << 12;
  6501. if (hdr_len & 0x10)
  6502. base_flags |= 0x00000010;
  6503. base_flags |= (hdr_len & 0x3e0) << 5;
  6504. } else if (tg3_flag(tp, HW_TSO_2))
  6505. mss |= hdr_len << 9;
  6506. else if (tg3_flag(tp, HW_TSO_1) ||
  6507. tg3_asic_rev(tp) == ASIC_REV_5705) {
  6508. if (tcp_opt_len || iph->ihl > 5) {
  6509. int tsflags;
  6510. tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
  6511. mss |= (tsflags << 11);
  6512. }
  6513. } else {
  6514. if (tcp_opt_len || iph->ihl > 5) {
  6515. int tsflags;
  6516. tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
  6517. base_flags |= tsflags << 12;
  6518. }
  6519. }
  6520. }
  6521. if (tg3_flag(tp, USE_JUMBO_BDFLAG) &&
  6522. !mss && skb->len > VLAN_ETH_FRAME_LEN)
  6523. base_flags |= TXD_FLAG_JMB_PKT;
  6524. if (vlan_tx_tag_present(skb)) {
  6525. base_flags |= TXD_FLAG_VLAN;
  6526. vlan = vlan_tx_tag_get(skb);
  6527. }
  6528. if ((unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) &&
  6529. tg3_flag(tp, TX_TSTAMP_EN)) {
  6530. skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
  6531. base_flags |= TXD_FLAG_HWTSTAMP;
  6532. }
  6533. len = skb_headlen(skb);
  6534. mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
  6535. if (pci_dma_mapping_error(tp->pdev, mapping))
  6536. goto drop;
  6537. tnapi->tx_buffers[entry].skb = skb;
  6538. dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
  6539. would_hit_hwbug = 0;
  6540. if (tg3_flag(tp, 5701_DMA_BUG))
  6541. would_hit_hwbug = 1;
  6542. if (tg3_tx_frag_set(tnapi, &entry, &budget, mapping, len, base_flags |
  6543. ((skb_shinfo(skb)->nr_frags == 0) ? TXD_FLAG_END : 0),
  6544. mss, vlan)) {
  6545. would_hit_hwbug = 1;
  6546. } else if (skb_shinfo(skb)->nr_frags > 0) {
  6547. u32 tmp_mss = mss;
  6548. if (!tg3_flag(tp, HW_TSO_1) &&
  6549. !tg3_flag(tp, HW_TSO_2) &&
  6550. !tg3_flag(tp, HW_TSO_3))
  6551. tmp_mss = 0;
  6552. /* Now loop through additional data
  6553. * fragments, and queue them.
  6554. */
  6555. last = skb_shinfo(skb)->nr_frags - 1;
  6556. for (i = 0; i <= last; i++) {
  6557. skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
  6558. len = skb_frag_size(frag);
  6559. mapping = skb_frag_dma_map(&tp->pdev->dev, frag, 0,
  6560. len, DMA_TO_DEVICE);
  6561. tnapi->tx_buffers[entry].skb = NULL;
  6562. dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
  6563. mapping);
  6564. if (dma_mapping_error(&tp->pdev->dev, mapping))
  6565. goto dma_error;
  6566. if (!budget ||
  6567. tg3_tx_frag_set(tnapi, &entry, &budget, mapping,
  6568. len, base_flags |
  6569. ((i == last) ? TXD_FLAG_END : 0),
  6570. tmp_mss, vlan)) {
  6571. would_hit_hwbug = 1;
  6572. break;
  6573. }
  6574. }
  6575. }
  6576. if (would_hit_hwbug) {
  6577. tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, i);
  6578. /* If the workaround fails due to memory/mapping
  6579. * failure, silently drop this packet.
  6580. */
  6581. entry = tnapi->tx_prod;
  6582. budget = tg3_tx_avail(tnapi);
  6583. if (tigon3_dma_hwbug_workaround(tnapi, &skb, &entry, &budget,
  6584. base_flags, mss, vlan))
  6585. goto drop_nofree;
  6586. }
  6587. skb_tx_timestamp(skb);
  6588. netdev_tx_sent_queue(txq, skb->len);
  6589. /* Sync BD data before updating mailbox */
  6590. wmb();
  6591. /* Packets are ready, update Tx producer idx local and on card. */
  6592. tw32_tx_mbox(tnapi->prodmbox, entry);
  6593. tnapi->tx_prod = entry;
  6594. if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
  6595. netif_tx_stop_queue(txq);
  6596. /* netif_tx_stop_queue() must be done before checking
  6597. * checking tx index in tg3_tx_avail() below, because in
  6598. * tg3_tx(), we update tx index before checking for
  6599. * netif_tx_queue_stopped().
  6600. */
  6601. smp_mb();
  6602. if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
  6603. netif_tx_wake_queue(txq);
  6604. }
  6605. mmiowb();
  6606. return NETDEV_TX_OK;
  6607. dma_error:
  6608. tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, --i);
  6609. tnapi->tx_buffers[tnapi->tx_prod].skb = NULL;
  6610. drop:
  6611. dev_kfree_skb(skb);
  6612. drop_nofree:
  6613. tp->tx_dropped++;
  6614. return NETDEV_TX_OK;
  6615. }
  6616. static void tg3_mac_loopback(struct tg3 *tp, bool enable)
  6617. {
  6618. if (enable) {
  6619. tp->mac_mode &= ~(MAC_MODE_HALF_DUPLEX |
  6620. MAC_MODE_PORT_MODE_MASK);
  6621. tp->mac_mode |= MAC_MODE_PORT_INT_LPBACK;
  6622. if (!tg3_flag(tp, 5705_PLUS))
  6623. tp->mac_mode |= MAC_MODE_LINK_POLARITY;
  6624. if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
  6625. tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
  6626. else
  6627. tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
  6628. } else {
  6629. tp->mac_mode &= ~MAC_MODE_PORT_INT_LPBACK;
  6630. if (tg3_flag(tp, 5705_PLUS) ||
  6631. (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) ||
  6632. tg3_asic_rev(tp) == ASIC_REV_5700)
  6633. tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
  6634. }
  6635. tw32(MAC_MODE, tp->mac_mode);
  6636. udelay(40);
  6637. }
  6638. static int tg3_phy_lpbk_set(struct tg3 *tp, u32 speed, bool extlpbk)
  6639. {
  6640. u32 val, bmcr, mac_mode, ptest = 0;
  6641. tg3_phy_toggle_apd(tp, false);
  6642. tg3_phy_toggle_automdix(tp, false);
  6643. if (extlpbk && tg3_phy_set_extloopbk(tp))
  6644. return -EIO;
  6645. bmcr = BMCR_FULLDPLX;
  6646. switch (speed) {
  6647. case SPEED_10:
  6648. break;
  6649. case SPEED_100:
  6650. bmcr |= BMCR_SPEED100;
  6651. break;
  6652. case SPEED_1000:
  6653. default:
  6654. if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
  6655. speed = SPEED_100;
  6656. bmcr |= BMCR_SPEED100;
  6657. } else {
  6658. speed = SPEED_1000;
  6659. bmcr |= BMCR_SPEED1000;
  6660. }
  6661. }
  6662. if (extlpbk) {
  6663. if (!(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
  6664. tg3_readphy(tp, MII_CTRL1000, &val);
  6665. val |= CTL1000_AS_MASTER |
  6666. CTL1000_ENABLE_MASTER;
  6667. tg3_writephy(tp, MII_CTRL1000, val);
  6668. } else {
  6669. ptest = MII_TG3_FET_PTEST_TRIM_SEL |
  6670. MII_TG3_FET_PTEST_TRIM_2;
  6671. tg3_writephy(tp, MII_TG3_FET_PTEST, ptest);
  6672. }
  6673. } else
  6674. bmcr |= BMCR_LOOPBACK;
  6675. tg3_writephy(tp, MII_BMCR, bmcr);
  6676. /* The write needs to be flushed for the FETs */
  6677. if (tp->phy_flags & TG3_PHYFLG_IS_FET)
  6678. tg3_readphy(tp, MII_BMCR, &bmcr);
  6679. udelay(40);
  6680. if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
  6681. tg3_asic_rev(tp) == ASIC_REV_5785) {
  6682. tg3_writephy(tp, MII_TG3_FET_PTEST, ptest |
  6683. MII_TG3_FET_PTEST_FRC_TX_LINK |
  6684. MII_TG3_FET_PTEST_FRC_TX_LOCK);
  6685. /* The write needs to be flushed for the AC131 */
  6686. tg3_readphy(tp, MII_TG3_FET_PTEST, &val);
  6687. }
  6688. /* Reset to prevent losing 1st rx packet intermittently */
  6689. if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
  6690. tg3_flag(tp, 5780_CLASS)) {
  6691. tw32_f(MAC_RX_MODE, RX_MODE_RESET);
  6692. udelay(10);
  6693. tw32_f(MAC_RX_MODE, tp->rx_mode);
  6694. }
  6695. mac_mode = tp->mac_mode &
  6696. ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
  6697. if (speed == SPEED_1000)
  6698. mac_mode |= MAC_MODE_PORT_MODE_GMII;
  6699. else
  6700. mac_mode |= MAC_MODE_PORT_MODE_MII;
  6701. if (tg3_asic_rev(tp) == ASIC_REV_5700) {
  6702. u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK;
  6703. if (masked_phy_id == TG3_PHY_ID_BCM5401)
  6704. mac_mode &= ~MAC_MODE_LINK_POLARITY;
  6705. else if (masked_phy_id == TG3_PHY_ID_BCM5411)
  6706. mac_mode |= MAC_MODE_LINK_POLARITY;
  6707. tg3_writephy(tp, MII_TG3_EXT_CTRL,
  6708. MII_TG3_EXT_CTRL_LNK3_LED_MODE);
  6709. }
  6710. tw32(MAC_MODE, mac_mode);
  6711. udelay(40);
  6712. return 0;
  6713. }
  6714. static void tg3_set_loopback(struct net_device *dev, netdev_features_t features)
  6715. {
  6716. struct tg3 *tp = netdev_priv(dev);
  6717. if (features & NETIF_F_LOOPBACK) {
  6718. if (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)
  6719. return;
  6720. spin_lock_bh(&tp->lock);
  6721. tg3_mac_loopback(tp, true);
  6722. netif_carrier_on(tp->dev);
  6723. spin_unlock_bh(&tp->lock);
  6724. netdev_info(dev, "Internal MAC loopback mode enabled.\n");
  6725. } else {
  6726. if (!(tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
  6727. return;
  6728. spin_lock_bh(&tp->lock);
  6729. tg3_mac_loopback(tp, false);
  6730. /* Force link status check */
  6731. tg3_setup_phy(tp, true);
  6732. spin_unlock_bh(&tp->lock);
  6733. netdev_info(dev, "Internal MAC loopback mode disabled.\n");
  6734. }
  6735. }
  6736. static netdev_features_t tg3_fix_features(struct net_device *dev,
  6737. netdev_features_t features)
  6738. {
  6739. struct tg3 *tp = netdev_priv(dev);
  6740. if (dev->mtu > ETH_DATA_LEN && tg3_flag(tp, 5780_CLASS))
  6741. features &= ~NETIF_F_ALL_TSO;
  6742. return features;
  6743. }
  6744. static int tg3_set_features(struct net_device *dev, netdev_features_t features)
  6745. {
  6746. netdev_features_t changed = dev->features ^ features;
  6747. if ((changed & NETIF_F_LOOPBACK) && netif_running(dev))
  6748. tg3_set_loopback(dev, features);
  6749. return 0;
  6750. }
  6751. static void tg3_rx_prodring_free(struct tg3 *tp,
  6752. struct tg3_rx_prodring_set *tpr)
  6753. {
  6754. int i;
  6755. if (tpr != &tp->napi[0].prodring) {
  6756. for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
  6757. i = (i + 1) & tp->rx_std_ring_mask)
  6758. tg3_rx_data_free(tp, &tpr->rx_std_buffers[i],
  6759. tp->rx_pkt_map_sz);
  6760. if (tg3_flag(tp, JUMBO_CAPABLE)) {
  6761. for (i = tpr->rx_jmb_cons_idx;
  6762. i != tpr->rx_jmb_prod_idx;
  6763. i = (i + 1) & tp->rx_jmb_ring_mask) {
  6764. tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i],
  6765. TG3_RX_JMB_MAP_SZ);
  6766. }
  6767. }
  6768. return;
  6769. }
  6770. for (i = 0; i <= tp->rx_std_ring_mask; i++)
  6771. tg3_rx_data_free(tp, &tpr->rx_std_buffers[i],
  6772. tp->rx_pkt_map_sz);
  6773. if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {
  6774. for (i = 0; i <= tp->rx_jmb_ring_mask; i++)
  6775. tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i],
  6776. TG3_RX_JMB_MAP_SZ);
  6777. }
  6778. }
  6779. /* Initialize rx rings for packet processing.
  6780. *
  6781. * The chip has been shut down and the driver detached from
  6782. * the networking, so no interrupts or new tx packets will
  6783. * end up in the driver. tp->{tx,}lock are held and thus
  6784. * we may not sleep.
  6785. */
  6786. static int tg3_rx_prodring_alloc(struct tg3 *tp,
  6787. struct tg3_rx_prodring_set *tpr)
  6788. {
  6789. u32 i, rx_pkt_dma_sz;
  6790. tpr->rx_std_cons_idx = 0;
  6791. tpr->rx_std_prod_idx = 0;
  6792. tpr->rx_jmb_cons_idx = 0;
  6793. tpr->rx_jmb_prod_idx = 0;
  6794. if (tpr != &tp->napi[0].prodring) {
  6795. memset(&tpr->rx_std_buffers[0], 0,
  6796. TG3_RX_STD_BUFF_RING_SIZE(tp));
  6797. if (tpr->rx_jmb_buffers)
  6798. memset(&tpr->rx_jmb_buffers[0], 0,
  6799. TG3_RX_JMB_BUFF_RING_SIZE(tp));
  6800. goto done;
  6801. }
  6802. /* Zero out all descriptors. */
  6803. memset(tpr->rx_std, 0, TG3_RX_STD_RING_BYTES(tp));
  6804. rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
  6805. if (tg3_flag(tp, 5780_CLASS) &&
  6806. tp->dev->mtu > ETH_DATA_LEN)
  6807. rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
  6808. tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
  6809. /* Initialize invariants of the rings, we only set this
  6810. * stuff once. This works because the card does not
  6811. * write into the rx buffer posting rings.
  6812. */
  6813. for (i = 0; i <= tp->rx_std_ring_mask; i++) {
  6814. struct tg3_rx_buffer_desc *rxd;
  6815. rxd = &tpr->rx_std[i];
  6816. rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
  6817. rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
  6818. rxd->opaque = (RXD_OPAQUE_RING_STD |
  6819. (i << RXD_OPAQUE_INDEX_SHIFT));
  6820. }
  6821. /* Now allocate fresh SKBs for each rx ring. */
  6822. for (i = 0; i < tp->rx_pending; i++) {
  6823. unsigned int frag_size;
  6824. if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_STD, i,
  6825. &frag_size) < 0) {
  6826. netdev_warn(tp->dev,
  6827. "Using a smaller RX standard ring. Only "
  6828. "%d out of %d buffers were allocated "
  6829. "successfully\n", i, tp->rx_pending);
  6830. if (i == 0)
  6831. goto initfail;
  6832. tp->rx_pending = i;
  6833. break;
  6834. }
  6835. }
  6836. if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
  6837. goto done;
  6838. memset(tpr->rx_jmb, 0, TG3_RX_JMB_RING_BYTES(tp));
  6839. if (!tg3_flag(tp, JUMBO_RING_ENABLE))
  6840. goto done;
  6841. for (i = 0; i <= tp->rx_jmb_ring_mask; i++) {
  6842. struct tg3_rx_buffer_desc *rxd;
  6843. rxd = &tpr->rx_jmb[i].std;
  6844. rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
  6845. rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
  6846. RXD_FLAG_JUMBO;
  6847. rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
  6848. (i << RXD_OPAQUE_INDEX_SHIFT));
  6849. }
  6850. for (i = 0; i < tp->rx_jumbo_pending; i++) {
  6851. unsigned int frag_size;
  6852. if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_JUMBO, i,
  6853. &frag_size) < 0) {
  6854. netdev_warn(tp->dev,
  6855. "Using a smaller RX jumbo ring. Only %d "
  6856. "out of %d buffers were allocated "
  6857. "successfully\n", i, tp->rx_jumbo_pending);
  6858. if (i == 0)
  6859. goto initfail;
  6860. tp->rx_jumbo_pending = i;
  6861. break;
  6862. }
  6863. }
  6864. done:
  6865. return 0;
  6866. initfail:
  6867. tg3_rx_prodring_free(tp, tpr);
  6868. return -ENOMEM;
  6869. }
  6870. static void tg3_rx_prodring_fini(struct tg3 *tp,
  6871. struct tg3_rx_prodring_set *tpr)
  6872. {
  6873. kfree(tpr->rx_std_buffers);
  6874. tpr->rx_std_buffers = NULL;
  6875. kfree(tpr->rx_jmb_buffers);
  6876. tpr->rx_jmb_buffers = NULL;
  6877. if (tpr->rx_std) {
  6878. dma_free_coherent(&tp->pdev->dev, TG3_RX_STD_RING_BYTES(tp),
  6879. tpr->rx_std, tpr->rx_std_mapping);
  6880. tpr->rx_std = NULL;
  6881. }
  6882. if (tpr->rx_jmb) {
  6883. dma_free_coherent(&tp->pdev->dev, TG3_RX_JMB_RING_BYTES(tp),
  6884. tpr->rx_jmb, tpr->rx_jmb_mapping);
  6885. tpr->rx_jmb = NULL;
  6886. }
  6887. }
  6888. static int tg3_rx_prodring_init(struct tg3 *tp,
  6889. struct tg3_rx_prodring_set *tpr)
  6890. {
  6891. tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE(tp),
  6892. GFP_KERNEL);
  6893. if (!tpr->rx_std_buffers)
  6894. return -ENOMEM;
  6895. tpr->rx_std = dma_alloc_coherent(&tp->pdev->dev,
  6896. TG3_RX_STD_RING_BYTES(tp),
  6897. &tpr->rx_std_mapping,
  6898. GFP_KERNEL);
  6899. if (!tpr->rx_std)
  6900. goto err_out;
  6901. if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {
  6902. tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp),
  6903. GFP_KERNEL);
  6904. if (!tpr->rx_jmb_buffers)
  6905. goto err_out;
  6906. tpr->rx_jmb = dma_alloc_coherent(&tp->pdev->dev,
  6907. TG3_RX_JMB_RING_BYTES(tp),
  6908. &tpr->rx_jmb_mapping,
  6909. GFP_KERNEL);
  6910. if (!tpr->rx_jmb)
  6911. goto err_out;
  6912. }
  6913. return 0;
  6914. err_out:
  6915. tg3_rx_prodring_fini(tp, tpr);
  6916. return -ENOMEM;
  6917. }
  6918. /* Free up pending packets in all rx/tx rings.
  6919. *
  6920. * The chip has been shut down and the driver detached from
  6921. * the networking, so no interrupts or new tx packets will
  6922. * end up in the driver. tp->{tx,}lock is not held and we are not
  6923. * in an interrupt context and thus may sleep.
  6924. */
  6925. static void tg3_free_rings(struct tg3 *tp)
  6926. {
  6927. int i, j;
  6928. for (j = 0; j < tp->irq_cnt; j++) {
  6929. struct tg3_napi *tnapi = &tp->napi[j];
  6930. tg3_rx_prodring_free(tp, &tnapi->prodring);
  6931. if (!tnapi->tx_buffers)
  6932. continue;
  6933. for (i = 0; i < TG3_TX_RING_SIZE; i++) {
  6934. struct sk_buff *skb = tnapi->tx_buffers[i].skb;
  6935. if (!skb)
  6936. continue;
  6937. tg3_tx_skb_unmap(tnapi, i,
  6938. skb_shinfo(skb)->nr_frags - 1);
  6939. dev_kfree_skb_any(skb);
  6940. }
  6941. netdev_tx_reset_queue(netdev_get_tx_queue(tp->dev, j));
  6942. }
  6943. }
  6944. /* Initialize tx/rx rings for packet processing.
  6945. *
  6946. * The chip has been shut down and the driver detached from
  6947. * the networking, so no interrupts or new tx packets will
  6948. * end up in the driver. tp->{tx,}lock are held and thus
  6949. * we may not sleep.
  6950. */
  6951. static int tg3_init_rings(struct tg3 *tp)
  6952. {
  6953. int i;
  6954. /* Free up all the SKBs. */
  6955. tg3_free_rings(tp);
  6956. for (i = 0; i < tp->irq_cnt; i++) {
  6957. struct tg3_napi *tnapi = &tp->napi[i];
  6958. tnapi->last_tag = 0;
  6959. tnapi->last_irq_tag = 0;
  6960. tnapi->hw_status->status = 0;
  6961. tnapi->hw_status->status_tag = 0;
  6962. memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
  6963. tnapi->tx_prod = 0;
  6964. tnapi->tx_cons = 0;
  6965. if (tnapi->tx_ring)
  6966. memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
  6967. tnapi->rx_rcb_ptr = 0;
  6968. if (tnapi->rx_rcb)
  6969. memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
  6970. if (tg3_rx_prodring_alloc(tp, &tnapi->prodring)) {
  6971. tg3_free_rings(tp);
  6972. return -ENOMEM;
  6973. }
  6974. }
  6975. return 0;
  6976. }
  6977. static void tg3_mem_tx_release(struct tg3 *tp)
  6978. {
  6979. int i;
  6980. for (i = 0; i < tp->irq_max; i++) {
  6981. struct tg3_napi *tnapi = &tp->napi[i];
  6982. if (tnapi->tx_ring) {
  6983. dma_free_coherent(&tp->pdev->dev, TG3_TX_RING_BYTES,
  6984. tnapi->tx_ring, tnapi->tx_desc_mapping);
  6985. tnapi->tx_ring = NULL;
  6986. }
  6987. kfree(tnapi->tx_buffers);
  6988. tnapi->tx_buffers = NULL;
  6989. }
  6990. }
  6991. static int tg3_mem_tx_acquire(struct tg3 *tp)
  6992. {
  6993. int i;
  6994. struct tg3_napi *tnapi = &tp->napi[0];
  6995. /* If multivector TSS is enabled, vector 0 does not handle
  6996. * tx interrupts. Don't allocate any resources for it.
  6997. */
  6998. if (tg3_flag(tp, ENABLE_TSS))
  6999. tnapi++;
  7000. for (i = 0; i < tp->txq_cnt; i++, tnapi++) {
  7001. tnapi->tx_buffers = kzalloc(sizeof(struct tg3_tx_ring_info) *
  7002. TG3_TX_RING_SIZE, GFP_KERNEL);
  7003. if (!tnapi->tx_buffers)
  7004. goto err_out;
  7005. tnapi->tx_ring = dma_alloc_coherent(&tp->pdev->dev,
  7006. TG3_TX_RING_BYTES,
  7007. &tnapi->tx_desc_mapping,
  7008. GFP_KERNEL);
  7009. if (!tnapi->tx_ring)
  7010. goto err_out;
  7011. }
  7012. return 0;
  7013. err_out:
  7014. tg3_mem_tx_release(tp);
  7015. return -ENOMEM;
  7016. }
  7017. static void tg3_mem_rx_release(struct tg3 *tp)
  7018. {
  7019. int i;
  7020. for (i = 0; i < tp->irq_max; i++) {
  7021. struct tg3_napi *tnapi = &tp->napi[i];
  7022. tg3_rx_prodring_fini(tp, &tnapi->prodring);
  7023. if (!tnapi->rx_rcb)
  7024. continue;
  7025. dma_free_coherent(&tp->pdev->dev,
  7026. TG3_RX_RCB_RING_BYTES(tp),
  7027. tnapi->rx_rcb,
  7028. tnapi->rx_rcb_mapping);
  7029. tnapi->rx_rcb = NULL;
  7030. }
  7031. }
  7032. static int tg3_mem_rx_acquire(struct tg3 *tp)
  7033. {
  7034. unsigned int i, limit;
  7035. limit = tp->rxq_cnt;
  7036. /* If RSS is enabled, we need a (dummy) producer ring
  7037. * set on vector zero. This is the true hw prodring.
  7038. */
  7039. if (tg3_flag(tp, ENABLE_RSS))
  7040. limit++;
  7041. for (i = 0; i < limit; i++) {
  7042. struct tg3_napi *tnapi = &tp->napi[i];
  7043. if (tg3_rx_prodring_init(tp, &tnapi->prodring))
  7044. goto err_out;
  7045. /* If multivector RSS is enabled, vector 0
  7046. * does not handle rx or tx interrupts.
  7047. * Don't allocate any resources for it.
  7048. */
  7049. if (!i && tg3_flag(tp, ENABLE_RSS))
  7050. continue;
  7051. tnapi->rx_rcb = dma_zalloc_coherent(&tp->pdev->dev,
  7052. TG3_RX_RCB_RING_BYTES(tp),
  7053. &tnapi->rx_rcb_mapping,
  7054. GFP_KERNEL);
  7055. if (!tnapi->rx_rcb)
  7056. goto err_out;
  7057. }
  7058. return 0;
  7059. err_out:
  7060. tg3_mem_rx_release(tp);
  7061. return -ENOMEM;
  7062. }
  7063. /*
  7064. * Must not be invoked with interrupt sources disabled and
  7065. * the hardware shutdown down.
  7066. */
  7067. static void tg3_free_consistent(struct tg3 *tp)
  7068. {
  7069. int i;
  7070. for (i = 0; i < tp->irq_cnt; i++) {
  7071. struct tg3_napi *tnapi = &tp->napi[i];
  7072. if (tnapi->hw_status) {
  7073. dma_free_coherent(&tp->pdev->dev, TG3_HW_STATUS_SIZE,
  7074. tnapi->hw_status,
  7075. tnapi->status_mapping);
  7076. tnapi->hw_status = NULL;
  7077. }
  7078. }
  7079. tg3_mem_rx_release(tp);
  7080. tg3_mem_tx_release(tp);
  7081. if (tp->hw_stats) {
  7082. dma_free_coherent(&tp->pdev->dev, sizeof(struct tg3_hw_stats),
  7083. tp->hw_stats, tp->stats_mapping);
  7084. tp->hw_stats = NULL;
  7085. }
  7086. }
  7087. /*
  7088. * Must not be invoked with interrupt sources disabled and
  7089. * the hardware shutdown down. Can sleep.
  7090. */
  7091. static int tg3_alloc_consistent(struct tg3 *tp)
  7092. {
  7093. int i;
  7094. tp->hw_stats = dma_zalloc_coherent(&tp->pdev->dev,
  7095. sizeof(struct tg3_hw_stats),
  7096. &tp->stats_mapping, GFP_KERNEL);
  7097. if (!tp->hw_stats)
  7098. goto err_out;
  7099. for (i = 0; i < tp->irq_cnt; i++) {
  7100. struct tg3_napi *tnapi = &tp->napi[i];
  7101. struct tg3_hw_status *sblk;
  7102. tnapi->hw_status = dma_zalloc_coherent(&tp->pdev->dev,
  7103. TG3_HW_STATUS_SIZE,
  7104. &tnapi->status_mapping,
  7105. GFP_KERNEL);
  7106. if (!tnapi->hw_status)
  7107. goto err_out;
  7108. sblk = tnapi->hw_status;
  7109. if (tg3_flag(tp, ENABLE_RSS)) {
  7110. u16 *prodptr = NULL;
  7111. /*
  7112. * When RSS is enabled, the status block format changes
  7113. * slightly. The "rx_jumbo_consumer", "reserved",
  7114. * and "rx_mini_consumer" members get mapped to the
  7115. * other three rx return ring producer indexes.
  7116. */
  7117. switch (i) {
  7118. case 1:
  7119. prodptr = &sblk->idx[0].rx_producer;
  7120. break;
  7121. case 2:
  7122. prodptr = &sblk->rx_jumbo_consumer;
  7123. break;
  7124. case 3:
  7125. prodptr = &sblk->reserved;
  7126. break;
  7127. case 4:
  7128. prodptr = &sblk->rx_mini_consumer;
  7129. break;
  7130. }
  7131. tnapi->rx_rcb_prod_idx = prodptr;
  7132. } else {
  7133. tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
  7134. }
  7135. }
  7136. if (tg3_mem_tx_acquire(tp) || tg3_mem_rx_acquire(tp))
  7137. goto err_out;
  7138. return 0;
  7139. err_out:
  7140. tg3_free_consistent(tp);
  7141. return -ENOMEM;
  7142. }
  7143. #define MAX_WAIT_CNT 1000
  7144. /* To stop a block, clear the enable bit and poll till it
  7145. * clears. tp->lock is held.
  7146. */
  7147. static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, bool silent)
  7148. {
  7149. unsigned int i;
  7150. u32 val;
  7151. if (tg3_flag(tp, 5705_PLUS)) {
  7152. switch (ofs) {
  7153. case RCVLSC_MODE:
  7154. case DMAC_MODE:
  7155. case MBFREE_MODE:
  7156. case BUFMGR_MODE:
  7157. case MEMARB_MODE:
  7158. /* We can't enable/disable these bits of the
  7159. * 5705/5750, just say success.
  7160. */
  7161. return 0;
  7162. default:
  7163. break;
  7164. }
  7165. }
  7166. val = tr32(ofs);
  7167. val &= ~enable_bit;
  7168. tw32_f(ofs, val);
  7169. for (i = 0; i < MAX_WAIT_CNT; i++) {
  7170. if (pci_channel_offline(tp->pdev)) {
  7171. dev_err(&tp->pdev->dev,
  7172. "tg3_stop_block device offline, "
  7173. "ofs=%lx enable_bit=%x\n",
  7174. ofs, enable_bit);
  7175. return -ENODEV;
  7176. }
  7177. udelay(100);
  7178. val = tr32(ofs);
  7179. if ((val & enable_bit) == 0)
  7180. break;
  7181. }
  7182. if (i == MAX_WAIT_CNT && !silent) {
  7183. dev_err(&tp->pdev->dev,
  7184. "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
  7185. ofs, enable_bit);
  7186. return -ENODEV;
  7187. }
  7188. return 0;
  7189. }
  7190. /* tp->lock is held. */
  7191. static int tg3_abort_hw(struct tg3 *tp, bool silent)
  7192. {
  7193. int i, err;
  7194. tg3_disable_ints(tp);
  7195. if (pci_channel_offline(tp->pdev)) {
  7196. tp->rx_mode &= ~(RX_MODE_ENABLE | TX_MODE_ENABLE);
  7197. tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
  7198. err = -ENODEV;
  7199. goto err_no_dev;
  7200. }
  7201. tp->rx_mode &= ~RX_MODE_ENABLE;
  7202. tw32_f(MAC_RX_MODE, tp->rx_mode);
  7203. udelay(10);
  7204. err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
  7205. err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
  7206. err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
  7207. err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
  7208. err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
  7209. err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
  7210. err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
  7211. err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
  7212. err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
  7213. err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
  7214. err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
  7215. err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
  7216. err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
  7217. tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
  7218. tw32_f(MAC_MODE, tp->mac_mode);
  7219. udelay(40);
  7220. tp->tx_mode &= ~TX_MODE_ENABLE;
  7221. tw32_f(MAC_TX_MODE, tp->tx_mode);
  7222. for (i = 0; i < MAX_WAIT_CNT; i++) {
  7223. udelay(100);
  7224. if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
  7225. break;
  7226. }
  7227. if (i >= MAX_WAIT_CNT) {
  7228. dev_err(&tp->pdev->dev,
  7229. "%s timed out, TX_MODE_ENABLE will not clear "
  7230. "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE));
  7231. err |= -ENODEV;
  7232. }
  7233. err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
  7234. err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
  7235. err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
  7236. tw32(FTQ_RESET, 0xffffffff);
  7237. tw32(FTQ_RESET, 0x00000000);
  7238. err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
  7239. err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
  7240. err_no_dev:
  7241. for (i = 0; i < tp->irq_cnt; i++) {
  7242. struct tg3_napi *tnapi = &tp->napi[i];
  7243. if (tnapi->hw_status)
  7244. memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
  7245. }
  7246. return err;
  7247. }
  7248. /* Save PCI command register before chip reset */
  7249. static void tg3_save_pci_state(struct tg3 *tp)
  7250. {
  7251. pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
  7252. }
  7253. /* Restore PCI state after chip reset */
  7254. static void tg3_restore_pci_state(struct tg3 *tp)
  7255. {
  7256. u32 val;
  7257. /* Re-enable indirect register accesses. */
  7258. pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
  7259. tp->misc_host_ctrl);
  7260. /* Set MAX PCI retry to zero. */
  7261. val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
  7262. if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0 &&
  7263. tg3_flag(tp, PCIX_MODE))
  7264. val |= PCISTATE_RETRY_SAME_DMA;
  7265. /* Allow reads and writes to the APE register and memory space. */
  7266. if (tg3_flag(tp, ENABLE_APE))
  7267. val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
  7268. PCISTATE_ALLOW_APE_SHMEM_WR |
  7269. PCISTATE_ALLOW_APE_PSPACE_WR;
  7270. pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
  7271. pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
  7272. if (!tg3_flag(tp, PCI_EXPRESS)) {
  7273. pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
  7274. tp->pci_cacheline_sz);
  7275. pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
  7276. tp->pci_lat_timer);
  7277. }
  7278. /* Make sure PCI-X relaxed ordering bit is clear. */
  7279. if (tg3_flag(tp, PCIX_MODE)) {
  7280. u16 pcix_cmd;
  7281. pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
  7282. &pcix_cmd);
  7283. pcix_cmd &= ~PCI_X_CMD_ERO;
  7284. pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
  7285. pcix_cmd);
  7286. }
  7287. if (tg3_flag(tp, 5780_CLASS)) {
  7288. /* Chip reset on 5780 will reset MSI enable bit,
  7289. * so need to restore it.
  7290. */
  7291. if (tg3_flag(tp, USING_MSI)) {
  7292. u16 ctrl;
  7293. pci_read_config_word(tp->pdev,
  7294. tp->msi_cap + PCI_MSI_FLAGS,
  7295. &ctrl);
  7296. pci_write_config_word(tp->pdev,
  7297. tp->msi_cap + PCI_MSI_FLAGS,
  7298. ctrl | PCI_MSI_FLAGS_ENABLE);
  7299. val = tr32(MSGINT_MODE);
  7300. tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
  7301. }
  7302. }
  7303. }
  7304. /* tp->lock is held. */
  7305. static int tg3_chip_reset(struct tg3 *tp)
  7306. {
  7307. u32 val;
  7308. void (*write_op)(struct tg3 *, u32, u32);
  7309. int i, err;
  7310. tg3_nvram_lock(tp);
  7311. tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
  7312. /* No matching tg3_nvram_unlock() after this because
  7313. * chip reset below will undo the nvram lock.
  7314. */
  7315. tp->nvram_lock_cnt = 0;
  7316. /* GRC_MISC_CFG core clock reset will clear the memory
  7317. * enable bit in PCI register 4 and the MSI enable bit
  7318. * on some chips, so we save relevant registers here.
  7319. */
  7320. tg3_save_pci_state(tp);
  7321. if (tg3_asic_rev(tp) == ASIC_REV_5752 ||
  7322. tg3_flag(tp, 5755_PLUS))
  7323. tw32(GRC_FASTBOOT_PC, 0);
  7324. /*
  7325. * We must avoid the readl() that normally takes place.
  7326. * It locks machines, causes machine checks, and other
  7327. * fun things. So, temporarily disable the 5701
  7328. * hardware workaround, while we do the reset.
  7329. */
  7330. write_op = tp->write32;
  7331. if (write_op == tg3_write_flush_reg32)
  7332. tp->write32 = tg3_write32;
  7333. /* Prevent the irq handler from reading or writing PCI registers
  7334. * during chip reset when the memory enable bit in the PCI command
  7335. * register may be cleared. The chip does not generate interrupt
  7336. * at this time, but the irq handler may still be called due to irq
  7337. * sharing or irqpoll.
  7338. */
  7339. tg3_flag_set(tp, CHIP_RESETTING);
  7340. for (i = 0; i < tp->irq_cnt; i++) {
  7341. struct tg3_napi *tnapi = &tp->napi[i];
  7342. if (tnapi->hw_status) {
  7343. tnapi->hw_status->status = 0;
  7344. tnapi->hw_status->status_tag = 0;
  7345. }
  7346. tnapi->last_tag = 0;
  7347. tnapi->last_irq_tag = 0;
  7348. }
  7349. smp_mb();
  7350. for (i = 0; i < tp->irq_cnt; i++)
  7351. synchronize_irq(tp->napi[i].irq_vec);
  7352. if (tg3_asic_rev(tp) == ASIC_REV_57780) {
  7353. val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
  7354. tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
  7355. }
  7356. /* do the reset */
  7357. val = GRC_MISC_CFG_CORECLK_RESET;
  7358. if (tg3_flag(tp, PCI_EXPRESS)) {
  7359. /* Force PCIe 1.0a mode */
  7360. if (tg3_asic_rev(tp) != ASIC_REV_5785 &&
  7361. !tg3_flag(tp, 57765_PLUS) &&
  7362. tr32(TG3_PCIE_PHY_TSTCTL) ==
  7363. (TG3_PCIE_PHY_TSTCTL_PCIE10 | TG3_PCIE_PHY_TSTCTL_PSCRAM))
  7364. tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM);
  7365. if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0) {
  7366. tw32(GRC_MISC_CFG, (1 << 29));
  7367. val |= (1 << 29);
  7368. }
  7369. }
  7370. if (tg3_asic_rev(tp) == ASIC_REV_5906) {
  7371. tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
  7372. tw32(GRC_VCPU_EXT_CTRL,
  7373. tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
  7374. }
  7375. /* Manage gphy power for all CPMU absent PCIe devices. */
  7376. if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, CPMU_PRESENT))
  7377. val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
  7378. tw32(GRC_MISC_CFG, val);
  7379. /* restore 5701 hardware bug workaround write method */
  7380. tp->write32 = write_op;
  7381. /* Unfortunately, we have to delay before the PCI read back.
  7382. * Some 575X chips even will not respond to a PCI cfg access
  7383. * when the reset command is given to the chip.
  7384. *
  7385. * How do these hardware designers expect things to work
  7386. * properly if the PCI write is posted for a long period
  7387. * of time? It is always necessary to have some method by
  7388. * which a register read back can occur to push the write
  7389. * out which does the reset.
  7390. *
  7391. * For most tg3 variants the trick below was working.
  7392. * Ho hum...
  7393. */
  7394. udelay(120);
  7395. /* Flush PCI posted writes. The normal MMIO registers
  7396. * are inaccessible at this time so this is the only
  7397. * way to make this reliably (actually, this is no longer
  7398. * the case, see above). I tried to use indirect
  7399. * register read/write but this upset some 5701 variants.
  7400. */
  7401. pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
  7402. udelay(120);
  7403. if (tg3_flag(tp, PCI_EXPRESS) && pci_is_pcie(tp->pdev)) {
  7404. u16 val16;
  7405. if (tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A0) {
  7406. int j;
  7407. u32 cfg_val;
  7408. /* Wait for link training to complete. */
  7409. for (j = 0; j < 5000; j++)
  7410. udelay(100);
  7411. pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
  7412. pci_write_config_dword(tp->pdev, 0xc4,
  7413. cfg_val | (1 << 15));
  7414. }
  7415. /* Clear the "no snoop" and "relaxed ordering" bits. */
  7416. val16 = PCI_EXP_DEVCTL_RELAX_EN | PCI_EXP_DEVCTL_NOSNOOP_EN;
  7417. /*
  7418. * Older PCIe devices only support the 128 byte
  7419. * MPS setting. Enforce the restriction.
  7420. */
  7421. if (!tg3_flag(tp, CPMU_PRESENT))
  7422. val16 |= PCI_EXP_DEVCTL_PAYLOAD;
  7423. pcie_capability_clear_word(tp->pdev, PCI_EXP_DEVCTL, val16);
  7424. /* Clear error status */
  7425. pcie_capability_write_word(tp->pdev, PCI_EXP_DEVSTA,
  7426. PCI_EXP_DEVSTA_CED |
  7427. PCI_EXP_DEVSTA_NFED |
  7428. PCI_EXP_DEVSTA_FED |
  7429. PCI_EXP_DEVSTA_URD);
  7430. }
  7431. tg3_restore_pci_state(tp);
  7432. tg3_flag_clear(tp, CHIP_RESETTING);
  7433. tg3_flag_clear(tp, ERROR_PROCESSED);
  7434. val = 0;
  7435. if (tg3_flag(tp, 5780_CLASS))
  7436. val = tr32(MEMARB_MODE);
  7437. tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
  7438. if (tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A3) {
  7439. tg3_stop_fw(tp);
  7440. tw32(0x5000, 0x400);
  7441. }
  7442. if (tg3_flag(tp, IS_SSB_CORE)) {
  7443. /*
  7444. * BCM4785: In order to avoid repercussions from using
  7445. * potentially defective internal ROM, stop the Rx RISC CPU,
  7446. * which is not required.
  7447. */
  7448. tg3_stop_fw(tp);
  7449. tg3_halt_cpu(tp, RX_CPU_BASE);
  7450. }
  7451. err = tg3_poll_fw(tp);
  7452. if (err)
  7453. return err;
  7454. tw32(GRC_MODE, tp->grc_mode);
  7455. if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A0) {
  7456. val = tr32(0xc4);
  7457. tw32(0xc4, val | (1 << 15));
  7458. }
  7459. if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
  7460. tg3_asic_rev(tp) == ASIC_REV_5705) {
  7461. tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
  7462. if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A0)
  7463. tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
  7464. tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
  7465. }
  7466. if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
  7467. tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
  7468. val = tp->mac_mode;
  7469. } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
  7470. tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
  7471. val = tp->mac_mode;
  7472. } else
  7473. val = 0;
  7474. tw32_f(MAC_MODE, val);
  7475. udelay(40);
  7476. tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
  7477. tg3_mdio_start(tp);
  7478. if (tg3_flag(tp, PCI_EXPRESS) &&
  7479. tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0 &&
  7480. tg3_asic_rev(tp) != ASIC_REV_5785 &&
  7481. !tg3_flag(tp, 57765_PLUS)) {
  7482. val = tr32(0x7c00);
  7483. tw32(0x7c00, val | (1 << 25));
  7484. }
  7485. if (tg3_asic_rev(tp) == ASIC_REV_5720) {
  7486. val = tr32(TG3_CPMU_CLCK_ORIDE);
  7487. tw32(TG3_CPMU_CLCK_ORIDE, val & ~CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
  7488. }
  7489. /* Reprobe ASF enable state. */
  7490. tg3_flag_clear(tp, ENABLE_ASF);
  7491. tp->phy_flags &= ~(TG3_PHYFLG_1G_ON_VAUX_OK |
  7492. TG3_PHYFLG_KEEP_LINK_ON_PWRDN);
  7493. tg3_flag_clear(tp, ASF_NEW_HANDSHAKE);
  7494. tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
  7495. if (val == NIC_SRAM_DATA_SIG_MAGIC) {
  7496. u32 nic_cfg;
  7497. tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
  7498. if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
  7499. tg3_flag_set(tp, ENABLE_ASF);
  7500. tp->last_event_jiffies = jiffies;
  7501. if (tg3_flag(tp, 5750_PLUS))
  7502. tg3_flag_set(tp, ASF_NEW_HANDSHAKE);
  7503. tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &nic_cfg);
  7504. if (nic_cfg & NIC_SRAM_1G_ON_VAUX_OK)
  7505. tp->phy_flags |= TG3_PHYFLG_1G_ON_VAUX_OK;
  7506. if (nic_cfg & NIC_SRAM_LNK_FLAP_AVOID)
  7507. tp->phy_flags |= TG3_PHYFLG_KEEP_LINK_ON_PWRDN;
  7508. }
  7509. }
  7510. return 0;
  7511. }
  7512. static void tg3_get_nstats(struct tg3 *, struct rtnl_link_stats64 *);
  7513. static void tg3_get_estats(struct tg3 *, struct tg3_ethtool_stats *);
  7514. /* tp->lock is held. */
  7515. static int tg3_halt(struct tg3 *tp, int kind, bool silent)
  7516. {
  7517. int err;
  7518. tg3_stop_fw(tp);
  7519. tg3_write_sig_pre_reset(tp, kind);
  7520. tg3_abort_hw(tp, silent);
  7521. err = tg3_chip_reset(tp);
  7522. __tg3_set_mac_addr(tp, false);
  7523. tg3_write_sig_legacy(tp, kind);
  7524. tg3_write_sig_post_reset(tp, kind);
  7525. if (tp->hw_stats) {
  7526. /* Save the stats across chip resets... */
  7527. tg3_get_nstats(tp, &tp->net_stats_prev);
  7528. tg3_get_estats(tp, &tp->estats_prev);
  7529. /* And make sure the next sample is new data */
  7530. memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
  7531. }
  7532. if (err)
  7533. return err;
  7534. return 0;
  7535. }
  7536. static int tg3_set_mac_addr(struct net_device *dev, void *p)
  7537. {
  7538. struct tg3 *tp = netdev_priv(dev);
  7539. struct sockaddr *addr = p;
  7540. int err = 0;
  7541. bool skip_mac_1 = false;
  7542. if (!is_valid_ether_addr(addr->sa_data))
  7543. return -EADDRNOTAVAIL;
  7544. memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
  7545. if (!netif_running(dev))
  7546. return 0;
  7547. if (tg3_flag(tp, ENABLE_ASF)) {
  7548. u32 addr0_high, addr0_low, addr1_high, addr1_low;
  7549. addr0_high = tr32(MAC_ADDR_0_HIGH);
  7550. addr0_low = tr32(MAC_ADDR_0_LOW);
  7551. addr1_high = tr32(MAC_ADDR_1_HIGH);
  7552. addr1_low = tr32(MAC_ADDR_1_LOW);
  7553. /* Skip MAC addr 1 if ASF is using it. */
  7554. if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
  7555. !(addr1_high == 0 && addr1_low == 0))
  7556. skip_mac_1 = true;
  7557. }
  7558. spin_lock_bh(&tp->lock);
  7559. __tg3_set_mac_addr(tp, skip_mac_1);
  7560. spin_unlock_bh(&tp->lock);
  7561. return err;
  7562. }
  7563. /* tp->lock is held. */
  7564. static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
  7565. dma_addr_t mapping, u32 maxlen_flags,
  7566. u32 nic_addr)
  7567. {
  7568. tg3_write_mem(tp,
  7569. (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
  7570. ((u64) mapping >> 32));
  7571. tg3_write_mem(tp,
  7572. (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
  7573. ((u64) mapping & 0xffffffff));
  7574. tg3_write_mem(tp,
  7575. (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
  7576. maxlen_flags);
  7577. if (!tg3_flag(tp, 5705_PLUS))
  7578. tg3_write_mem(tp,
  7579. (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
  7580. nic_addr);
  7581. }
  7582. static void tg3_coal_tx_init(struct tg3 *tp, struct ethtool_coalesce *ec)
  7583. {
  7584. int i = 0;
  7585. if (!tg3_flag(tp, ENABLE_TSS)) {
  7586. tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
  7587. tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
  7588. tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
  7589. } else {
  7590. tw32(HOSTCC_TXCOL_TICKS, 0);
  7591. tw32(HOSTCC_TXMAX_FRAMES, 0);
  7592. tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
  7593. for (; i < tp->txq_cnt; i++) {
  7594. u32 reg;
  7595. reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
  7596. tw32(reg, ec->tx_coalesce_usecs);
  7597. reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
  7598. tw32(reg, ec->tx_max_coalesced_frames);
  7599. reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
  7600. tw32(reg, ec->tx_max_coalesced_frames_irq);
  7601. }
  7602. }
  7603. for (; i < tp->irq_max - 1; i++) {
  7604. tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
  7605. tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
  7606. tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
  7607. }
  7608. }
  7609. static void tg3_coal_rx_init(struct tg3 *tp, struct ethtool_coalesce *ec)
  7610. {
  7611. int i = 0;
  7612. u32 limit = tp->rxq_cnt;
  7613. if (!tg3_flag(tp, ENABLE_RSS)) {
  7614. tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
  7615. tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
  7616. tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
  7617. limit--;
  7618. } else {
  7619. tw32(HOSTCC_RXCOL_TICKS, 0);
  7620. tw32(HOSTCC_RXMAX_FRAMES, 0);
  7621. tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
  7622. }
  7623. for (; i < limit; i++) {
  7624. u32 reg;
  7625. reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
  7626. tw32(reg, ec->rx_coalesce_usecs);
  7627. reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
  7628. tw32(reg, ec->rx_max_coalesced_frames);
  7629. reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
  7630. tw32(reg, ec->rx_max_coalesced_frames_irq);
  7631. }
  7632. for (; i < tp->irq_max - 1; i++) {
  7633. tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
  7634. tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
  7635. tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
  7636. }
  7637. }
  7638. static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
  7639. {
  7640. tg3_coal_tx_init(tp, ec);
  7641. tg3_coal_rx_init(tp, ec);
  7642. if (!tg3_flag(tp, 5705_PLUS)) {
  7643. u32 val = ec->stats_block_coalesce_usecs;
  7644. tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
  7645. tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
  7646. if (!tp->link_up)
  7647. val = 0;
  7648. tw32(HOSTCC_STAT_COAL_TICKS, val);
  7649. }
  7650. }
  7651. /* tp->lock is held. */
  7652. static void tg3_tx_rcbs_disable(struct tg3 *tp)
  7653. {
  7654. u32 txrcb, limit;
  7655. /* Disable all transmit rings but the first. */
  7656. if (!tg3_flag(tp, 5705_PLUS))
  7657. limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
  7658. else if (tg3_flag(tp, 5717_PLUS))
  7659. limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4;
  7660. else if (tg3_flag(tp, 57765_CLASS) ||
  7661. tg3_asic_rev(tp) == ASIC_REV_5762)
  7662. limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
  7663. else
  7664. limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
  7665. for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
  7666. txrcb < limit; txrcb += TG3_BDINFO_SIZE)
  7667. tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
  7668. BDINFO_FLAGS_DISABLED);
  7669. }
  7670. /* tp->lock is held. */
  7671. static void tg3_tx_rcbs_init(struct tg3 *tp)
  7672. {
  7673. int i = 0;
  7674. u32 txrcb = NIC_SRAM_SEND_RCB;
  7675. if (tg3_flag(tp, ENABLE_TSS))
  7676. i++;
  7677. for (; i < tp->irq_max; i++, txrcb += TG3_BDINFO_SIZE) {
  7678. struct tg3_napi *tnapi = &tp->napi[i];
  7679. if (!tnapi->tx_ring)
  7680. continue;
  7681. tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
  7682. (TG3_TX_RING_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT),
  7683. NIC_SRAM_TX_BUFFER_DESC);
  7684. }
  7685. }
  7686. /* tp->lock is held. */
  7687. static void tg3_rx_ret_rcbs_disable(struct tg3 *tp)
  7688. {
  7689. u32 rxrcb, limit;
  7690. /* Disable all receive return rings but the first. */
  7691. if (tg3_flag(tp, 5717_PLUS))
  7692. limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
  7693. else if (!tg3_flag(tp, 5705_PLUS))
  7694. limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
  7695. else if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
  7696. tg3_asic_rev(tp) == ASIC_REV_5762 ||
  7697. tg3_flag(tp, 57765_CLASS))
  7698. limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
  7699. else
  7700. limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
  7701. for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
  7702. rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
  7703. tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
  7704. BDINFO_FLAGS_DISABLED);
  7705. }
  7706. /* tp->lock is held. */
  7707. static void tg3_rx_ret_rcbs_init(struct tg3 *tp)
  7708. {
  7709. int i = 0;
  7710. u32 rxrcb = NIC_SRAM_RCV_RET_RCB;
  7711. if (tg3_flag(tp, ENABLE_RSS))
  7712. i++;
  7713. for (; i < tp->irq_max; i++, rxrcb += TG3_BDINFO_SIZE) {
  7714. struct tg3_napi *tnapi = &tp->napi[i];
  7715. if (!tnapi->rx_rcb)
  7716. continue;
  7717. tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
  7718. (tp->rx_ret_ring_mask + 1) <<
  7719. BDINFO_FLAGS_MAXLEN_SHIFT, 0);
  7720. }
  7721. }
  7722. /* tp->lock is held. */
  7723. static void tg3_rings_reset(struct tg3 *tp)
  7724. {
  7725. int i;
  7726. u32 stblk;
  7727. struct tg3_napi *tnapi = &tp->napi[0];
  7728. tg3_tx_rcbs_disable(tp);
  7729. tg3_rx_ret_rcbs_disable(tp);
  7730. /* Disable interrupts */
  7731. tw32_mailbox_f(tp->napi[0].int_mbox, 1);
  7732. tp->napi[0].chk_msi_cnt = 0;
  7733. tp->napi[0].last_rx_cons = 0;
  7734. tp->napi[0].last_tx_cons = 0;
  7735. /* Zero mailbox registers. */
  7736. if (tg3_flag(tp, SUPPORT_MSIX)) {
  7737. for (i = 1; i < tp->irq_max; i++) {
  7738. tp->napi[i].tx_prod = 0;
  7739. tp->napi[i].tx_cons = 0;
  7740. if (tg3_flag(tp, ENABLE_TSS))
  7741. tw32_mailbox(tp->napi[i].prodmbox, 0);
  7742. tw32_rx_mbox(tp->napi[i].consmbox, 0);
  7743. tw32_mailbox_f(tp->napi[i].int_mbox, 1);
  7744. tp->napi[i].chk_msi_cnt = 0;
  7745. tp->napi[i].last_rx_cons = 0;
  7746. tp->napi[i].last_tx_cons = 0;
  7747. }
  7748. if (!tg3_flag(tp, ENABLE_TSS))
  7749. tw32_mailbox(tp->napi[0].prodmbox, 0);
  7750. } else {
  7751. tp->napi[0].tx_prod = 0;
  7752. tp->napi[0].tx_cons = 0;
  7753. tw32_mailbox(tp->napi[0].prodmbox, 0);
  7754. tw32_rx_mbox(tp->napi[0].consmbox, 0);
  7755. }
  7756. /* Make sure the NIC-based send BD rings are disabled. */
  7757. if (!tg3_flag(tp, 5705_PLUS)) {
  7758. u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
  7759. for (i = 0; i < 16; i++)
  7760. tw32_tx_mbox(mbox + i * 8, 0);
  7761. }
  7762. /* Clear status block in ram. */
  7763. memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
  7764. /* Set status block DMA address */
  7765. tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
  7766. ((u64) tnapi->status_mapping >> 32));
  7767. tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
  7768. ((u64) tnapi->status_mapping & 0xffffffff));
  7769. stblk = HOSTCC_STATBLCK_RING1;
  7770. for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
  7771. u64 mapping = (u64)tnapi->status_mapping;
  7772. tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
  7773. tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
  7774. stblk += 8;
  7775. /* Clear status block in ram. */
  7776. memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
  7777. }
  7778. tg3_tx_rcbs_init(tp);
  7779. tg3_rx_ret_rcbs_init(tp);
  7780. }
  7781. static void tg3_setup_rxbd_thresholds(struct tg3 *tp)
  7782. {
  7783. u32 val, bdcache_maxcnt, host_rep_thresh, nic_rep_thresh;
  7784. if (!tg3_flag(tp, 5750_PLUS) ||
  7785. tg3_flag(tp, 5780_CLASS) ||
  7786. tg3_asic_rev(tp) == ASIC_REV_5750 ||
  7787. tg3_asic_rev(tp) == ASIC_REV_5752 ||
  7788. tg3_flag(tp, 57765_PLUS))
  7789. bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5700;
  7790. else if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
  7791. tg3_asic_rev(tp) == ASIC_REV_5787)
  7792. bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5755;
  7793. else
  7794. bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5906;
  7795. nic_rep_thresh = min(bdcache_maxcnt / 2, tp->rx_std_max_post);
  7796. host_rep_thresh = max_t(u32, tp->rx_pending / 8, 1);
  7797. val = min(nic_rep_thresh, host_rep_thresh);
  7798. tw32(RCVBDI_STD_THRESH, val);
  7799. if (tg3_flag(tp, 57765_PLUS))
  7800. tw32(STD_REPLENISH_LWM, bdcache_maxcnt);
  7801. if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
  7802. return;
  7803. bdcache_maxcnt = TG3_SRAM_RX_JMB_BDCACHE_SIZE_5700;
  7804. host_rep_thresh = max_t(u32, tp->rx_jumbo_pending / 8, 1);
  7805. val = min(bdcache_maxcnt / 2, host_rep_thresh);
  7806. tw32(RCVBDI_JUMBO_THRESH, val);
  7807. if (tg3_flag(tp, 57765_PLUS))
  7808. tw32(JMB_REPLENISH_LWM, bdcache_maxcnt);
  7809. }
  7810. static inline u32 calc_crc(unsigned char *buf, int len)
  7811. {
  7812. u32 reg;
  7813. u32 tmp;
  7814. int j, k;
  7815. reg = 0xffffffff;
  7816. for (j = 0; j < len; j++) {
  7817. reg ^= buf[j];
  7818. for (k = 0; k < 8; k++) {
  7819. tmp = reg & 0x01;
  7820. reg >>= 1;
  7821. if (tmp)
  7822. reg ^= 0xedb88320;
  7823. }
  7824. }
  7825. return ~reg;
  7826. }
  7827. static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
  7828. {
  7829. /* accept or reject all multicast frames */
  7830. tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
  7831. tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
  7832. tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
  7833. tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
  7834. }
  7835. static void __tg3_set_rx_mode(struct net_device *dev)
  7836. {
  7837. struct tg3 *tp = netdev_priv(dev);
  7838. u32 rx_mode;
  7839. rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
  7840. RX_MODE_KEEP_VLAN_TAG);
  7841. #if !defined(CONFIG_VLAN_8021Q) && !defined(CONFIG_VLAN_8021Q_MODULE)
  7842. /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
  7843. * flag clear.
  7844. */
  7845. if (!tg3_flag(tp, ENABLE_ASF))
  7846. rx_mode |= RX_MODE_KEEP_VLAN_TAG;
  7847. #endif
  7848. if (dev->flags & IFF_PROMISC) {
  7849. /* Promiscuous mode. */
  7850. rx_mode |= RX_MODE_PROMISC;
  7851. } else if (dev->flags & IFF_ALLMULTI) {
  7852. /* Accept all multicast. */
  7853. tg3_set_multi(tp, 1);
  7854. } else if (netdev_mc_empty(dev)) {
  7855. /* Reject all multicast. */
  7856. tg3_set_multi(tp, 0);
  7857. } else {
  7858. /* Accept one or more multicast(s). */
  7859. struct netdev_hw_addr *ha;
  7860. u32 mc_filter[4] = { 0, };
  7861. u32 regidx;
  7862. u32 bit;
  7863. u32 crc;
  7864. netdev_for_each_mc_addr(ha, dev) {
  7865. crc = calc_crc(ha->addr, ETH_ALEN);
  7866. bit = ~crc & 0x7f;
  7867. regidx = (bit & 0x60) >> 5;
  7868. bit &= 0x1f;
  7869. mc_filter[regidx] |= (1 << bit);
  7870. }
  7871. tw32(MAC_HASH_REG_0, mc_filter[0]);
  7872. tw32(MAC_HASH_REG_1, mc_filter[1]);
  7873. tw32(MAC_HASH_REG_2, mc_filter[2]);
  7874. tw32(MAC_HASH_REG_3, mc_filter[3]);
  7875. }
  7876. if (rx_mode != tp->rx_mode) {
  7877. tp->rx_mode = rx_mode;
  7878. tw32_f(MAC_RX_MODE, rx_mode);
  7879. udelay(10);
  7880. }
  7881. }
  7882. static void tg3_rss_init_dflt_indir_tbl(struct tg3 *tp, u32 qcnt)
  7883. {
  7884. int i;
  7885. for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
  7886. tp->rss_ind_tbl[i] = ethtool_rxfh_indir_default(i, qcnt);
  7887. }
  7888. static void tg3_rss_check_indir_tbl(struct tg3 *tp)
  7889. {
  7890. int i;
  7891. if (!tg3_flag(tp, SUPPORT_MSIX))
  7892. return;
  7893. if (tp->rxq_cnt == 1) {
  7894. memset(&tp->rss_ind_tbl[0], 0, sizeof(tp->rss_ind_tbl));
  7895. return;
  7896. }
  7897. /* Validate table against current IRQ count */
  7898. for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
  7899. if (tp->rss_ind_tbl[i] >= tp->rxq_cnt)
  7900. break;
  7901. }
  7902. if (i != TG3_RSS_INDIR_TBL_SIZE)
  7903. tg3_rss_init_dflt_indir_tbl(tp, tp->rxq_cnt);
  7904. }
  7905. static void tg3_rss_write_indir_tbl(struct tg3 *tp)
  7906. {
  7907. int i = 0;
  7908. u32 reg = MAC_RSS_INDIR_TBL_0;
  7909. while (i < TG3_RSS_INDIR_TBL_SIZE) {
  7910. u32 val = tp->rss_ind_tbl[i];
  7911. i++;
  7912. for (; i % 8; i++) {
  7913. val <<= 4;
  7914. val |= tp->rss_ind_tbl[i];
  7915. }
  7916. tw32(reg, val);
  7917. reg += 4;
  7918. }
  7919. }
  7920. static inline u32 tg3_lso_rd_dma_workaround_bit(struct tg3 *tp)
  7921. {
  7922. if (tg3_asic_rev(tp) == ASIC_REV_5719)
  7923. return TG3_LSO_RD_DMA_TX_LENGTH_WA_5719;
  7924. else
  7925. return TG3_LSO_RD_DMA_TX_LENGTH_WA_5720;
  7926. }
  7927. /* tp->lock is held. */
  7928. static int tg3_reset_hw(struct tg3 *tp, bool reset_phy)
  7929. {
  7930. u32 val, rdmac_mode;
  7931. int i, err, limit;
  7932. struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
  7933. tg3_disable_ints(tp);
  7934. tg3_stop_fw(tp);
  7935. tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
  7936. if (tg3_flag(tp, INIT_COMPLETE))
  7937. tg3_abort_hw(tp, 1);
  7938. if ((tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) &&
  7939. !(tp->phy_flags & TG3_PHYFLG_USER_CONFIGURED)) {
  7940. tg3_phy_pull_config(tp);
  7941. tg3_eee_pull_config(tp, NULL);
  7942. tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
  7943. }
  7944. /* Enable MAC control of LPI */
  7945. if (tp->phy_flags & TG3_PHYFLG_EEE_CAP)
  7946. tg3_setup_eee(tp);
  7947. if (reset_phy)
  7948. tg3_phy_reset(tp);
  7949. err = tg3_chip_reset(tp);
  7950. if (err)
  7951. return err;
  7952. tg3_write_sig_legacy(tp, RESET_KIND_INIT);
  7953. if (tg3_chip_rev(tp) == CHIPREV_5784_AX) {
  7954. val = tr32(TG3_CPMU_CTRL);
  7955. val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
  7956. tw32(TG3_CPMU_CTRL, val);
  7957. val = tr32(TG3_CPMU_LSPD_10MB_CLK);
  7958. val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
  7959. val |= CPMU_LSPD_10MB_MACCLK_6_25;
  7960. tw32(TG3_CPMU_LSPD_10MB_CLK, val);
  7961. val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
  7962. val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
  7963. val |= CPMU_LNK_AWARE_MACCLK_6_25;
  7964. tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
  7965. val = tr32(TG3_CPMU_HST_ACC);
  7966. val &= ~CPMU_HST_ACC_MACCLK_MASK;
  7967. val |= CPMU_HST_ACC_MACCLK_6_25;
  7968. tw32(TG3_CPMU_HST_ACC, val);
  7969. }
  7970. if (tg3_asic_rev(tp) == ASIC_REV_57780) {
  7971. val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
  7972. val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
  7973. PCIE_PWR_MGMT_L1_THRESH_4MS;
  7974. tw32(PCIE_PWR_MGMT_THRESH, val);
  7975. val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
  7976. tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
  7977. tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
  7978. val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
  7979. tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
  7980. }
  7981. if (tg3_flag(tp, L1PLLPD_EN)) {
  7982. u32 grc_mode = tr32(GRC_MODE);
  7983. /* Access the lower 1K of PL PCIE block registers. */
  7984. val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
  7985. tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
  7986. val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
  7987. tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
  7988. val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
  7989. tw32(GRC_MODE, grc_mode);
  7990. }
  7991. if (tg3_flag(tp, 57765_CLASS)) {
  7992. if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0) {
  7993. u32 grc_mode = tr32(GRC_MODE);
  7994. /* Access the lower 1K of PL PCIE block registers. */
  7995. val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
  7996. tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
  7997. val = tr32(TG3_PCIE_TLDLPL_PORT +
  7998. TG3_PCIE_PL_LO_PHYCTL5);
  7999. tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5,
  8000. val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ);
  8001. tw32(GRC_MODE, grc_mode);
  8002. }
  8003. if (tg3_chip_rev(tp) != CHIPREV_57765_AX) {
  8004. u32 grc_mode;
  8005. /* Fix transmit hangs */
  8006. val = tr32(TG3_CPMU_PADRNG_CTL);
  8007. val |= TG3_CPMU_PADRNG_CTL_RDIV2;
  8008. tw32(TG3_CPMU_PADRNG_CTL, val);
  8009. grc_mode = tr32(GRC_MODE);
  8010. /* Access the lower 1K of DL PCIE block registers. */
  8011. val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
  8012. tw32(GRC_MODE, val | GRC_MODE_PCIE_DL_SEL);
  8013. val = tr32(TG3_PCIE_TLDLPL_PORT +
  8014. TG3_PCIE_DL_LO_FTSMAX);
  8015. val &= ~TG3_PCIE_DL_LO_FTSMAX_MSK;
  8016. tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_DL_LO_FTSMAX,
  8017. val | TG3_PCIE_DL_LO_FTSMAX_VAL);
  8018. tw32(GRC_MODE, grc_mode);
  8019. }
  8020. val = tr32(TG3_CPMU_LSPD_10MB_CLK);
  8021. val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
  8022. val |= CPMU_LSPD_10MB_MACCLK_6_25;
  8023. tw32(TG3_CPMU_LSPD_10MB_CLK, val);
  8024. }
  8025. /* This works around an issue with Athlon chipsets on
  8026. * B3 tigon3 silicon. This bit has no effect on any
  8027. * other revision. But do not set this on PCI Express
  8028. * chips and don't even touch the clocks if the CPMU is present.
  8029. */
  8030. if (!tg3_flag(tp, CPMU_PRESENT)) {
  8031. if (!tg3_flag(tp, PCI_EXPRESS))
  8032. tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
  8033. tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
  8034. }
  8035. if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0 &&
  8036. tg3_flag(tp, PCIX_MODE)) {
  8037. val = tr32(TG3PCI_PCISTATE);
  8038. val |= PCISTATE_RETRY_SAME_DMA;
  8039. tw32(TG3PCI_PCISTATE, val);
  8040. }
  8041. if (tg3_flag(tp, ENABLE_APE)) {
  8042. /* Allow reads and writes to the
  8043. * APE register and memory space.
  8044. */
  8045. val = tr32(TG3PCI_PCISTATE);
  8046. val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
  8047. PCISTATE_ALLOW_APE_SHMEM_WR |
  8048. PCISTATE_ALLOW_APE_PSPACE_WR;
  8049. tw32(TG3PCI_PCISTATE, val);
  8050. }
  8051. if (tg3_chip_rev(tp) == CHIPREV_5704_BX) {
  8052. /* Enable some hw fixes. */
  8053. val = tr32(TG3PCI_MSI_DATA);
  8054. val |= (1 << 26) | (1 << 28) | (1 << 29);
  8055. tw32(TG3PCI_MSI_DATA, val);
  8056. }
  8057. /* Descriptor ring init may make accesses to the
  8058. * NIC SRAM area to setup the TX descriptors, so we
  8059. * can only do this after the hardware has been
  8060. * successfully reset.
  8061. */
  8062. err = tg3_init_rings(tp);
  8063. if (err)
  8064. return err;
  8065. if (tg3_flag(tp, 57765_PLUS)) {
  8066. val = tr32(TG3PCI_DMA_RW_CTRL) &
  8067. ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
  8068. if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0)
  8069. val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK;
  8070. if (!tg3_flag(tp, 57765_CLASS) &&
  8071. tg3_asic_rev(tp) != ASIC_REV_5717 &&
  8072. tg3_asic_rev(tp) != ASIC_REV_5762)
  8073. val |= DMA_RWCTRL_TAGGED_STAT_WA;
  8074. tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
  8075. } else if (tg3_asic_rev(tp) != ASIC_REV_5784 &&
  8076. tg3_asic_rev(tp) != ASIC_REV_5761) {
  8077. /* This value is determined during the probe time DMA
  8078. * engine test, tg3_test_dma.
  8079. */
  8080. tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
  8081. }
  8082. tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
  8083. GRC_MODE_4X_NIC_SEND_RINGS |
  8084. GRC_MODE_NO_TX_PHDR_CSUM |
  8085. GRC_MODE_NO_RX_PHDR_CSUM);
  8086. tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
  8087. /* Pseudo-header checksum is done by hardware logic and not
  8088. * the offload processers, so make the chip do the pseudo-
  8089. * header checksums on receive. For transmit it is more
  8090. * convenient to do the pseudo-header checksum in software
  8091. * as Linux does that on transmit for us in all cases.
  8092. */
  8093. tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
  8094. val = GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP;
  8095. if (tp->rxptpctl)
  8096. tw32(TG3_RX_PTP_CTL,
  8097. tp->rxptpctl | TG3_RX_PTP_CTL_HWTS_INTERLOCK);
  8098. if (tg3_flag(tp, PTP_CAPABLE))
  8099. val |= GRC_MODE_TIME_SYNC_ENABLE;
  8100. tw32(GRC_MODE, tp->grc_mode | val);
  8101. /* Setup the timer prescalar register. Clock is always 66Mhz. */
  8102. val = tr32(GRC_MISC_CFG);
  8103. val &= ~0xff;
  8104. val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
  8105. tw32(GRC_MISC_CFG, val);
  8106. /* Initialize MBUF/DESC pool. */
  8107. if (tg3_flag(tp, 5750_PLUS)) {
  8108. /* Do nothing. */
  8109. } else if (tg3_asic_rev(tp) != ASIC_REV_5705) {
  8110. tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
  8111. if (tg3_asic_rev(tp) == ASIC_REV_5704)
  8112. tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
  8113. else
  8114. tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
  8115. tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
  8116. tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
  8117. } else if (tg3_flag(tp, TSO_CAPABLE)) {
  8118. int fw_len;
  8119. fw_len = tp->fw_len;
  8120. fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
  8121. tw32(BUFMGR_MB_POOL_ADDR,
  8122. NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
  8123. tw32(BUFMGR_MB_POOL_SIZE,
  8124. NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
  8125. }
  8126. if (tp->dev->mtu <= ETH_DATA_LEN) {
  8127. tw32(BUFMGR_MB_RDMA_LOW_WATER,
  8128. tp->bufmgr_config.mbuf_read_dma_low_water);
  8129. tw32(BUFMGR_MB_MACRX_LOW_WATER,
  8130. tp->bufmgr_config.mbuf_mac_rx_low_water);
  8131. tw32(BUFMGR_MB_HIGH_WATER,
  8132. tp->bufmgr_config.mbuf_high_water);
  8133. } else {
  8134. tw32(BUFMGR_MB_RDMA_LOW_WATER,
  8135. tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
  8136. tw32(BUFMGR_MB_MACRX_LOW_WATER,
  8137. tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
  8138. tw32(BUFMGR_MB_HIGH_WATER,
  8139. tp->bufmgr_config.mbuf_high_water_jumbo);
  8140. }
  8141. tw32(BUFMGR_DMA_LOW_WATER,
  8142. tp->bufmgr_config.dma_low_water);
  8143. tw32(BUFMGR_DMA_HIGH_WATER,
  8144. tp->bufmgr_config.dma_high_water);
  8145. val = BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE;
  8146. if (tg3_asic_rev(tp) == ASIC_REV_5719)
  8147. val |= BUFMGR_MODE_NO_TX_UNDERRUN;
  8148. if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
  8149. tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
  8150. tg3_chip_rev_id(tp) == CHIPREV_ID_5720_A0)
  8151. val |= BUFMGR_MODE_MBLOW_ATTN_ENAB;
  8152. tw32(BUFMGR_MODE, val);
  8153. for (i = 0; i < 2000; i++) {
  8154. if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
  8155. break;
  8156. udelay(10);
  8157. }
  8158. if (i >= 2000) {
  8159. netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__);
  8160. return -ENODEV;
  8161. }
  8162. if (tg3_chip_rev_id(tp) == CHIPREV_ID_5906_A1)
  8163. tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
  8164. tg3_setup_rxbd_thresholds(tp);
  8165. /* Initialize TG3_BDINFO's at:
  8166. * RCVDBDI_STD_BD: standard eth size rx ring
  8167. * RCVDBDI_JUMBO_BD: jumbo frame rx ring
  8168. * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
  8169. *
  8170. * like so:
  8171. * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
  8172. * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
  8173. * ring attribute flags
  8174. * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
  8175. *
  8176. * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
  8177. * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
  8178. *
  8179. * The size of each ring is fixed in the firmware, but the location is
  8180. * configurable.
  8181. */
  8182. tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
  8183. ((u64) tpr->rx_std_mapping >> 32));
  8184. tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
  8185. ((u64) tpr->rx_std_mapping & 0xffffffff));
  8186. if (!tg3_flag(tp, 5717_PLUS))
  8187. tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
  8188. NIC_SRAM_RX_BUFFER_DESC);
  8189. /* Disable the mini ring */
  8190. if (!tg3_flag(tp, 5705_PLUS))
  8191. tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
  8192. BDINFO_FLAGS_DISABLED);
  8193. /* Program the jumbo buffer descriptor ring control
  8194. * blocks on those devices that have them.
  8195. */
  8196. if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
  8197. (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))) {
  8198. if (tg3_flag(tp, JUMBO_RING_ENABLE)) {
  8199. tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
  8200. ((u64) tpr->rx_jmb_mapping >> 32));
  8201. tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
  8202. ((u64) tpr->rx_jmb_mapping & 0xffffffff));
  8203. val = TG3_RX_JMB_RING_SIZE(tp) <<
  8204. BDINFO_FLAGS_MAXLEN_SHIFT;
  8205. tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
  8206. val | BDINFO_FLAGS_USE_EXT_RECV);
  8207. if (!tg3_flag(tp, USE_JUMBO_BDFLAG) ||
  8208. tg3_flag(tp, 57765_CLASS) ||
  8209. tg3_asic_rev(tp) == ASIC_REV_5762)
  8210. tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
  8211. NIC_SRAM_RX_JUMBO_BUFFER_DESC);
  8212. } else {
  8213. tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
  8214. BDINFO_FLAGS_DISABLED);
  8215. }
  8216. if (tg3_flag(tp, 57765_PLUS)) {
  8217. val = TG3_RX_STD_RING_SIZE(tp);
  8218. val <<= BDINFO_FLAGS_MAXLEN_SHIFT;
  8219. val |= (TG3_RX_STD_DMA_SZ << 2);
  8220. } else
  8221. val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT;
  8222. } else
  8223. val = TG3_RX_STD_MAX_SIZE_5700 << BDINFO_FLAGS_MAXLEN_SHIFT;
  8224. tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
  8225. tpr->rx_std_prod_idx = tp->rx_pending;
  8226. tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
  8227. tpr->rx_jmb_prod_idx =
  8228. tg3_flag(tp, JUMBO_RING_ENABLE) ? tp->rx_jumbo_pending : 0;
  8229. tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
  8230. tg3_rings_reset(tp);
  8231. /* Initialize MAC address and backoff seed. */
  8232. __tg3_set_mac_addr(tp, false);
  8233. /* MTU + ethernet header + FCS + optional VLAN tag */
  8234. tw32(MAC_RX_MTU_SIZE,
  8235. tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
  8236. /* The slot time is changed by tg3_setup_phy if we
  8237. * run at gigabit with half duplex.
  8238. */
  8239. val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
  8240. (6 << TX_LENGTHS_IPG_SHIFT) |
  8241. (32 << TX_LENGTHS_SLOT_TIME_SHIFT);
  8242. if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
  8243. tg3_asic_rev(tp) == ASIC_REV_5762)
  8244. val |= tr32(MAC_TX_LENGTHS) &
  8245. (TX_LENGTHS_JMB_FRM_LEN_MSK |
  8246. TX_LENGTHS_CNT_DWN_VAL_MSK);
  8247. tw32(MAC_TX_LENGTHS, val);
  8248. /* Receive rules. */
  8249. tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
  8250. tw32(RCVLPC_CONFIG, 0x0181);
  8251. /* Calculate RDMAC_MODE setting early, we need it to determine
  8252. * the RCVLPC_STATE_ENABLE mask.
  8253. */
  8254. rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
  8255. RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
  8256. RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
  8257. RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
  8258. RDMAC_MODE_LNGREAD_ENAB);
  8259. if (tg3_asic_rev(tp) == ASIC_REV_5717)
  8260. rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS;
  8261. if (tg3_asic_rev(tp) == ASIC_REV_5784 ||
  8262. tg3_asic_rev(tp) == ASIC_REV_5785 ||
  8263. tg3_asic_rev(tp) == ASIC_REV_57780)
  8264. rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
  8265. RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
  8266. RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
  8267. if (tg3_asic_rev(tp) == ASIC_REV_5705 &&
  8268. tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) {
  8269. if (tg3_flag(tp, TSO_CAPABLE) &&
  8270. tg3_asic_rev(tp) == ASIC_REV_5705) {
  8271. rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
  8272. } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
  8273. !tg3_flag(tp, IS_5788)) {
  8274. rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
  8275. }
  8276. }
  8277. if (tg3_flag(tp, PCI_EXPRESS))
  8278. rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
  8279. if (tg3_asic_rev(tp) == ASIC_REV_57766) {
  8280. tp->dma_limit = 0;
  8281. if (tp->dev->mtu <= ETH_DATA_LEN) {
  8282. rdmac_mode |= RDMAC_MODE_JMB_2K_MMRR;
  8283. tp->dma_limit = TG3_TX_BD_DMA_MAX_2K;
  8284. }
  8285. }
  8286. if (tg3_flag(tp, HW_TSO_1) ||
  8287. tg3_flag(tp, HW_TSO_2) ||
  8288. tg3_flag(tp, HW_TSO_3))
  8289. rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
  8290. if (tg3_flag(tp, 57765_PLUS) ||
  8291. tg3_asic_rev(tp) == ASIC_REV_5785 ||
  8292. tg3_asic_rev(tp) == ASIC_REV_57780)
  8293. rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
  8294. if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
  8295. tg3_asic_rev(tp) == ASIC_REV_5762)
  8296. rdmac_mode |= tr32(RDMAC_MODE) & RDMAC_MODE_H2BNC_VLAN_DET;
  8297. if (tg3_asic_rev(tp) == ASIC_REV_5761 ||
  8298. tg3_asic_rev(tp) == ASIC_REV_5784 ||
  8299. tg3_asic_rev(tp) == ASIC_REV_5785 ||
  8300. tg3_asic_rev(tp) == ASIC_REV_57780 ||
  8301. tg3_flag(tp, 57765_PLUS)) {
  8302. u32 tgtreg;
  8303. if (tg3_asic_rev(tp) == ASIC_REV_5762)
  8304. tgtreg = TG3_RDMA_RSRVCTRL_REG2;
  8305. else
  8306. tgtreg = TG3_RDMA_RSRVCTRL_REG;
  8307. val = tr32(tgtreg);
  8308. if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
  8309. tg3_asic_rev(tp) == ASIC_REV_5762) {
  8310. val &= ~(TG3_RDMA_RSRVCTRL_TXMRGN_MASK |
  8311. TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK |
  8312. TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK);
  8313. val |= TG3_RDMA_RSRVCTRL_TXMRGN_320B |
  8314. TG3_RDMA_RSRVCTRL_FIFO_LWM_1_5K |
  8315. TG3_RDMA_RSRVCTRL_FIFO_HWM_1_5K;
  8316. }
  8317. tw32(tgtreg, val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
  8318. }
  8319. if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
  8320. tg3_asic_rev(tp) == ASIC_REV_5720 ||
  8321. tg3_asic_rev(tp) == ASIC_REV_5762) {
  8322. u32 tgtreg;
  8323. if (tg3_asic_rev(tp) == ASIC_REV_5762)
  8324. tgtreg = TG3_LSO_RD_DMA_CRPTEN_CTRL2;
  8325. else
  8326. tgtreg = TG3_LSO_RD_DMA_CRPTEN_CTRL;
  8327. val = tr32(tgtreg);
  8328. tw32(tgtreg, val |
  8329. TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K |
  8330. TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K);
  8331. }
  8332. /* Receive/send statistics. */
  8333. if (tg3_flag(tp, 5750_PLUS)) {
  8334. val = tr32(RCVLPC_STATS_ENABLE);
  8335. val &= ~RCVLPC_STATSENAB_DACK_FIX;
  8336. tw32(RCVLPC_STATS_ENABLE, val);
  8337. } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
  8338. tg3_flag(tp, TSO_CAPABLE)) {
  8339. val = tr32(RCVLPC_STATS_ENABLE);
  8340. val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
  8341. tw32(RCVLPC_STATS_ENABLE, val);
  8342. } else {
  8343. tw32(RCVLPC_STATS_ENABLE, 0xffffff);
  8344. }
  8345. tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
  8346. tw32(SNDDATAI_STATSENAB, 0xffffff);
  8347. tw32(SNDDATAI_STATSCTRL,
  8348. (SNDDATAI_SCTRL_ENABLE |
  8349. SNDDATAI_SCTRL_FASTUPD));
  8350. /* Setup host coalescing engine. */
  8351. tw32(HOSTCC_MODE, 0);
  8352. for (i = 0; i < 2000; i++) {
  8353. if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
  8354. break;
  8355. udelay(10);
  8356. }
  8357. __tg3_set_coalesce(tp, &tp->coal);
  8358. if (!tg3_flag(tp, 5705_PLUS)) {
  8359. /* Status/statistics block address. See tg3_timer,
  8360. * the tg3_periodic_fetch_stats call there, and
  8361. * tg3_get_stats to see how this works for 5705/5750 chips.
  8362. */
  8363. tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
  8364. ((u64) tp->stats_mapping >> 32));
  8365. tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
  8366. ((u64) tp->stats_mapping & 0xffffffff));
  8367. tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
  8368. tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
  8369. /* Clear statistics and status block memory areas */
  8370. for (i = NIC_SRAM_STATS_BLK;
  8371. i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
  8372. i += sizeof(u32)) {
  8373. tg3_write_mem(tp, i, 0);
  8374. udelay(40);
  8375. }
  8376. }
  8377. tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
  8378. tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
  8379. tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
  8380. if (!tg3_flag(tp, 5705_PLUS))
  8381. tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
  8382. if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
  8383. tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
  8384. /* reset to prevent losing 1st rx packet intermittently */
  8385. tw32_f(MAC_RX_MODE, RX_MODE_RESET);
  8386. udelay(10);
  8387. }
  8388. tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
  8389. MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE |
  8390. MAC_MODE_FHDE_ENABLE;
  8391. if (tg3_flag(tp, ENABLE_APE))
  8392. tp->mac_mode |= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
  8393. if (!tg3_flag(tp, 5705_PLUS) &&
  8394. !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
  8395. tg3_asic_rev(tp) != ASIC_REV_5700)
  8396. tp->mac_mode |= MAC_MODE_LINK_POLARITY;
  8397. tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
  8398. udelay(40);
  8399. /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
  8400. * If TG3_FLAG_IS_NIC is zero, we should read the
  8401. * register to preserve the GPIO settings for LOMs. The GPIOs,
  8402. * whether used as inputs or outputs, are set by boot code after
  8403. * reset.
  8404. */
  8405. if (!tg3_flag(tp, IS_NIC)) {
  8406. u32 gpio_mask;
  8407. gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
  8408. GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
  8409. GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
  8410. if (tg3_asic_rev(tp) == ASIC_REV_5752)
  8411. gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
  8412. GRC_LCLCTRL_GPIO_OUTPUT3;
  8413. if (tg3_asic_rev(tp) == ASIC_REV_5755)
  8414. gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
  8415. tp->grc_local_ctrl &= ~gpio_mask;
  8416. tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
  8417. /* GPIO1 must be driven high for eeprom write protect */
  8418. if (tg3_flag(tp, EEPROM_WRITE_PROT))
  8419. tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
  8420. GRC_LCLCTRL_GPIO_OUTPUT1);
  8421. }
  8422. tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
  8423. udelay(100);
  8424. if (tg3_flag(tp, USING_MSIX)) {
  8425. val = tr32(MSGINT_MODE);
  8426. val |= MSGINT_MODE_ENABLE;
  8427. if (tp->irq_cnt > 1)
  8428. val |= MSGINT_MODE_MULTIVEC_EN;
  8429. if (!tg3_flag(tp, 1SHOT_MSI))
  8430. val |= MSGINT_MODE_ONE_SHOT_DISABLE;
  8431. tw32(MSGINT_MODE, val);
  8432. }
  8433. if (!tg3_flag(tp, 5705_PLUS)) {
  8434. tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
  8435. udelay(40);
  8436. }
  8437. val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
  8438. WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
  8439. WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
  8440. WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
  8441. WDMAC_MODE_LNGREAD_ENAB);
  8442. if (tg3_asic_rev(tp) == ASIC_REV_5705 &&
  8443. tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) {
  8444. if (tg3_flag(tp, TSO_CAPABLE) &&
  8445. (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A1 ||
  8446. tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A2)) {
  8447. /* nothing */
  8448. } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
  8449. !tg3_flag(tp, IS_5788)) {
  8450. val |= WDMAC_MODE_RX_ACCEL;
  8451. }
  8452. }
  8453. /* Enable host coalescing bug fix */
  8454. if (tg3_flag(tp, 5755_PLUS))
  8455. val |= WDMAC_MODE_STATUS_TAG_FIX;
  8456. if (tg3_asic_rev(tp) == ASIC_REV_5785)
  8457. val |= WDMAC_MODE_BURST_ALL_DATA;
  8458. tw32_f(WDMAC_MODE, val);
  8459. udelay(40);
  8460. if (tg3_flag(tp, PCIX_MODE)) {
  8461. u16 pcix_cmd;
  8462. pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
  8463. &pcix_cmd);
  8464. if (tg3_asic_rev(tp) == ASIC_REV_5703) {
  8465. pcix_cmd &= ~PCI_X_CMD_MAX_READ;
  8466. pcix_cmd |= PCI_X_CMD_READ_2K;
  8467. } else if (tg3_asic_rev(tp) == ASIC_REV_5704) {
  8468. pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
  8469. pcix_cmd |= PCI_X_CMD_READ_2K;
  8470. }
  8471. pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
  8472. pcix_cmd);
  8473. }
  8474. tw32_f(RDMAC_MODE, rdmac_mode);
  8475. udelay(40);
  8476. if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
  8477. tg3_asic_rev(tp) == ASIC_REV_5720) {
  8478. for (i = 0; i < TG3_NUM_RDMA_CHANNELS; i++) {
  8479. if (tr32(TG3_RDMA_LENGTH + (i << 2)) > TG3_MAX_MTU(tp))
  8480. break;
  8481. }
  8482. if (i < TG3_NUM_RDMA_CHANNELS) {
  8483. val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
  8484. val |= tg3_lso_rd_dma_workaround_bit(tp);
  8485. tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val);
  8486. tg3_flag_set(tp, 5719_5720_RDMA_BUG);
  8487. }
  8488. }
  8489. tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
  8490. if (!tg3_flag(tp, 5705_PLUS))
  8491. tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
  8492. if (tg3_asic_rev(tp) == ASIC_REV_5761)
  8493. tw32(SNDDATAC_MODE,
  8494. SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
  8495. else
  8496. tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
  8497. tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
  8498. tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
  8499. val = RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ;
  8500. if (tg3_flag(tp, LRG_PROD_RING_CAP))
  8501. val |= RCVDBDI_MODE_LRG_RING_SZ;
  8502. tw32(RCVDBDI_MODE, val);
  8503. tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
  8504. if (tg3_flag(tp, HW_TSO_1) ||
  8505. tg3_flag(tp, HW_TSO_2) ||
  8506. tg3_flag(tp, HW_TSO_3))
  8507. tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
  8508. val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
  8509. if (tg3_flag(tp, ENABLE_TSS))
  8510. val |= SNDBDI_MODE_MULTI_TXQ_EN;
  8511. tw32(SNDBDI_MODE, val);
  8512. tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
  8513. if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0) {
  8514. err = tg3_load_5701_a0_firmware_fix(tp);
  8515. if (err)
  8516. return err;
  8517. }
  8518. if (tg3_asic_rev(tp) == ASIC_REV_57766) {
  8519. /* Ignore any errors for the firmware download. If download
  8520. * fails, the device will operate with EEE disabled
  8521. */
  8522. tg3_load_57766_firmware(tp);
  8523. }
  8524. if (tg3_flag(tp, TSO_CAPABLE)) {
  8525. err = tg3_load_tso_firmware(tp);
  8526. if (err)
  8527. return err;
  8528. }
  8529. tp->tx_mode = TX_MODE_ENABLE;
  8530. if (tg3_flag(tp, 5755_PLUS) ||
  8531. tg3_asic_rev(tp) == ASIC_REV_5906)
  8532. tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX;
  8533. if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
  8534. tg3_asic_rev(tp) == ASIC_REV_5762) {
  8535. val = TX_MODE_JMB_FRM_LEN | TX_MODE_CNT_DN_MODE;
  8536. tp->tx_mode &= ~val;
  8537. tp->tx_mode |= tr32(MAC_TX_MODE) & val;
  8538. }
  8539. tw32_f(MAC_TX_MODE, tp->tx_mode);
  8540. udelay(100);
  8541. if (tg3_flag(tp, ENABLE_RSS)) {
  8542. tg3_rss_write_indir_tbl(tp);
  8543. /* Setup the "secret" hash key. */
  8544. tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
  8545. tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
  8546. tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
  8547. tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
  8548. tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
  8549. tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
  8550. tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
  8551. tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
  8552. tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
  8553. tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
  8554. }
  8555. tp->rx_mode = RX_MODE_ENABLE;
  8556. if (tg3_flag(tp, 5755_PLUS))
  8557. tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
  8558. if (tg3_asic_rev(tp) == ASIC_REV_5762)
  8559. tp->rx_mode |= RX_MODE_IPV4_FRAG_FIX;
  8560. if (tg3_flag(tp, ENABLE_RSS))
  8561. tp->rx_mode |= RX_MODE_RSS_ENABLE |
  8562. RX_MODE_RSS_ITBL_HASH_BITS_7 |
  8563. RX_MODE_RSS_IPV6_HASH_EN |
  8564. RX_MODE_RSS_TCP_IPV6_HASH_EN |
  8565. RX_MODE_RSS_IPV4_HASH_EN |
  8566. RX_MODE_RSS_TCP_IPV4_HASH_EN;
  8567. tw32_f(MAC_RX_MODE, tp->rx_mode);
  8568. udelay(10);
  8569. tw32(MAC_LED_CTRL, tp->led_ctrl);
  8570. tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
  8571. if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
  8572. tw32_f(MAC_RX_MODE, RX_MODE_RESET);
  8573. udelay(10);
  8574. }
  8575. tw32_f(MAC_RX_MODE, tp->rx_mode);
  8576. udelay(10);
  8577. if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
  8578. if ((tg3_asic_rev(tp) == ASIC_REV_5704) &&
  8579. !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) {
  8580. /* Set drive transmission level to 1.2V */
  8581. /* only if the signal pre-emphasis bit is not set */
  8582. val = tr32(MAC_SERDES_CFG);
  8583. val &= 0xfffff000;
  8584. val |= 0x880;
  8585. tw32(MAC_SERDES_CFG, val);
  8586. }
  8587. if (tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A1)
  8588. tw32(MAC_SERDES_CFG, 0x616000);
  8589. }
  8590. /* Prevent chip from dropping frames when flow control
  8591. * is enabled.
  8592. */
  8593. if (tg3_flag(tp, 57765_CLASS))
  8594. val = 1;
  8595. else
  8596. val = 2;
  8597. tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
  8598. if (tg3_asic_rev(tp) == ASIC_REV_5704 &&
  8599. (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
  8600. /* Use hardware link auto-negotiation */
  8601. tg3_flag_set(tp, HW_AUTONEG);
  8602. }
  8603. if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
  8604. tg3_asic_rev(tp) == ASIC_REV_5714) {
  8605. u32 tmp;
  8606. tmp = tr32(SERDES_RX_CTRL);
  8607. tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
  8608. tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
  8609. tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
  8610. tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
  8611. }
  8612. if (!tg3_flag(tp, USE_PHYLIB)) {
  8613. if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
  8614. tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
  8615. err = tg3_setup_phy(tp, false);
  8616. if (err)
  8617. return err;
  8618. if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
  8619. !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
  8620. u32 tmp;
  8621. /* Clear CRC stats. */
  8622. if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
  8623. tg3_writephy(tp, MII_TG3_TEST1,
  8624. tmp | MII_TG3_TEST1_CRC_EN);
  8625. tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &tmp);
  8626. }
  8627. }
  8628. }
  8629. __tg3_set_rx_mode(tp->dev);
  8630. /* Initialize receive rules. */
  8631. tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
  8632. tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
  8633. tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
  8634. tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
  8635. if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS))
  8636. limit = 8;
  8637. else
  8638. limit = 16;
  8639. if (tg3_flag(tp, ENABLE_ASF))
  8640. limit -= 4;
  8641. switch (limit) {
  8642. case 16:
  8643. tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
  8644. case 15:
  8645. tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
  8646. case 14:
  8647. tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
  8648. case 13:
  8649. tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
  8650. case 12:
  8651. tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
  8652. case 11:
  8653. tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
  8654. case 10:
  8655. tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
  8656. case 9:
  8657. tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
  8658. case 8:
  8659. tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
  8660. case 7:
  8661. tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
  8662. case 6:
  8663. tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
  8664. case 5:
  8665. tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
  8666. case 4:
  8667. /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
  8668. case 3:
  8669. /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
  8670. case 2:
  8671. case 1:
  8672. default:
  8673. break;
  8674. }
  8675. if (tg3_flag(tp, ENABLE_APE))
  8676. /* Write our heartbeat update interval to APE. */
  8677. tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
  8678. APE_HOST_HEARTBEAT_INT_DISABLE);
  8679. tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
  8680. return 0;
  8681. }
  8682. /* Called at device open time to get the chip ready for
  8683. * packet processing. Invoked with tp->lock held.
  8684. */
  8685. static int tg3_init_hw(struct tg3 *tp, bool reset_phy)
  8686. {
  8687. /* Chip may have been just powered on. If so, the boot code may still
  8688. * be running initialization. Wait for it to finish to avoid races in
  8689. * accessing the hardware.
  8690. */
  8691. tg3_enable_register_access(tp);
  8692. tg3_poll_fw(tp);
  8693. tg3_switch_clocks(tp);
  8694. tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
  8695. return tg3_reset_hw(tp, reset_phy);
  8696. }
  8697. static void tg3_sd_scan_scratchpad(struct tg3 *tp, struct tg3_ocir *ocir)
  8698. {
  8699. int i;
  8700. for (i = 0; i < TG3_SD_NUM_RECS; i++, ocir++) {
  8701. u32 off = i * TG3_OCIR_LEN, len = TG3_OCIR_LEN;
  8702. tg3_ape_scratchpad_read(tp, (u32 *) ocir, off, len);
  8703. off += len;
  8704. if (ocir->signature != TG3_OCIR_SIG_MAGIC ||
  8705. !(ocir->version_flags & TG3_OCIR_FLAG_ACTIVE))
  8706. memset(ocir, 0, TG3_OCIR_LEN);
  8707. }
  8708. }
  8709. /* sysfs attributes for hwmon */
  8710. static ssize_t tg3_show_temp(struct device *dev,
  8711. struct device_attribute *devattr, char *buf)
  8712. {
  8713. struct pci_dev *pdev = to_pci_dev(dev);
  8714. struct net_device *netdev = pci_get_drvdata(pdev);
  8715. struct tg3 *tp = netdev_priv(netdev);
  8716. struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
  8717. u32 temperature;
  8718. spin_lock_bh(&tp->lock);
  8719. tg3_ape_scratchpad_read(tp, &temperature, attr->index,
  8720. sizeof(temperature));
  8721. spin_unlock_bh(&tp->lock);
  8722. return sprintf(buf, "%u\n", temperature);
  8723. }
  8724. static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, tg3_show_temp, NULL,
  8725. TG3_TEMP_SENSOR_OFFSET);
  8726. static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, tg3_show_temp, NULL,
  8727. TG3_TEMP_CAUTION_OFFSET);
  8728. static SENSOR_DEVICE_ATTR(temp1_max, S_IRUGO, tg3_show_temp, NULL,
  8729. TG3_TEMP_MAX_OFFSET);
  8730. static struct attribute *tg3_attributes[] = {
  8731. &sensor_dev_attr_temp1_input.dev_attr.attr,
  8732. &sensor_dev_attr_temp1_crit.dev_attr.attr,
  8733. &sensor_dev_attr_temp1_max.dev_attr.attr,
  8734. NULL
  8735. };
  8736. static const struct attribute_group tg3_group = {
  8737. .attrs = tg3_attributes,
  8738. };
  8739. static void tg3_hwmon_close(struct tg3 *tp)
  8740. {
  8741. if (tp->hwmon_dev) {
  8742. hwmon_device_unregister(tp->hwmon_dev);
  8743. tp->hwmon_dev = NULL;
  8744. sysfs_remove_group(&tp->pdev->dev.kobj, &tg3_group);
  8745. }
  8746. }
  8747. static void tg3_hwmon_open(struct tg3 *tp)
  8748. {
  8749. int i, err;
  8750. u32 size = 0;
  8751. struct pci_dev *pdev = tp->pdev;
  8752. struct tg3_ocir ocirs[TG3_SD_NUM_RECS];
  8753. tg3_sd_scan_scratchpad(tp, ocirs);
  8754. for (i = 0; i < TG3_SD_NUM_RECS; i++) {
  8755. if (!ocirs[i].src_data_length)
  8756. continue;
  8757. size += ocirs[i].src_hdr_length;
  8758. size += ocirs[i].src_data_length;
  8759. }
  8760. if (!size)
  8761. return;
  8762. /* Register hwmon sysfs hooks */
  8763. err = sysfs_create_group(&pdev->dev.kobj, &tg3_group);
  8764. if (err) {
  8765. dev_err(&pdev->dev, "Cannot create sysfs group, aborting\n");
  8766. return;
  8767. }
  8768. tp->hwmon_dev = hwmon_device_register(&pdev->dev);
  8769. if (IS_ERR(tp->hwmon_dev)) {
  8770. tp->hwmon_dev = NULL;
  8771. dev_err(&pdev->dev, "Cannot register hwmon device, aborting\n");
  8772. sysfs_remove_group(&pdev->dev.kobj, &tg3_group);
  8773. }
  8774. }
  8775. #define TG3_STAT_ADD32(PSTAT, REG) \
  8776. do { u32 __val = tr32(REG); \
  8777. (PSTAT)->low += __val; \
  8778. if ((PSTAT)->low < __val) \
  8779. (PSTAT)->high += 1; \
  8780. } while (0)
  8781. static void tg3_periodic_fetch_stats(struct tg3 *tp)
  8782. {
  8783. struct tg3_hw_stats *sp = tp->hw_stats;
  8784. if (!tp->link_up)
  8785. return;
  8786. TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
  8787. TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
  8788. TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
  8789. TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
  8790. TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
  8791. TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
  8792. TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
  8793. TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
  8794. TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
  8795. TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
  8796. TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
  8797. TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
  8798. TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
  8799. if (unlikely(tg3_flag(tp, 5719_5720_RDMA_BUG) &&
  8800. (sp->tx_ucast_packets.low + sp->tx_mcast_packets.low +
  8801. sp->tx_bcast_packets.low) > TG3_NUM_RDMA_CHANNELS)) {
  8802. u32 val;
  8803. val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
  8804. val &= ~tg3_lso_rd_dma_workaround_bit(tp);
  8805. tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val);
  8806. tg3_flag_clear(tp, 5719_5720_RDMA_BUG);
  8807. }
  8808. TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
  8809. TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
  8810. TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
  8811. TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
  8812. TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
  8813. TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
  8814. TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
  8815. TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
  8816. TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
  8817. TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
  8818. TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
  8819. TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
  8820. TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
  8821. TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
  8822. TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
  8823. if (tg3_asic_rev(tp) != ASIC_REV_5717 &&
  8824. tg3_chip_rev_id(tp) != CHIPREV_ID_5719_A0 &&
  8825. tg3_chip_rev_id(tp) != CHIPREV_ID_5720_A0) {
  8826. TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
  8827. } else {
  8828. u32 val = tr32(HOSTCC_FLOW_ATTN);
  8829. val = (val & HOSTCC_FLOW_ATTN_MBUF_LWM) ? 1 : 0;
  8830. if (val) {
  8831. tw32(HOSTCC_FLOW_ATTN, HOSTCC_FLOW_ATTN_MBUF_LWM);
  8832. sp->rx_discards.low += val;
  8833. if (sp->rx_discards.low < val)
  8834. sp->rx_discards.high += 1;
  8835. }
  8836. sp->mbuf_lwm_thresh_hit = sp->rx_discards;
  8837. }
  8838. TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
  8839. }
  8840. static void tg3_chk_missed_msi(struct tg3 *tp)
  8841. {
  8842. u32 i;
  8843. for (i = 0; i < tp->irq_cnt; i++) {
  8844. struct tg3_napi *tnapi = &tp->napi[i];
  8845. if (tg3_has_work(tnapi)) {
  8846. if (tnapi->last_rx_cons == tnapi->rx_rcb_ptr &&
  8847. tnapi->last_tx_cons == tnapi->tx_cons) {
  8848. if (tnapi->chk_msi_cnt < 1) {
  8849. tnapi->chk_msi_cnt++;
  8850. return;
  8851. }
  8852. tg3_msi(0, tnapi);
  8853. }
  8854. }
  8855. tnapi->chk_msi_cnt = 0;
  8856. tnapi->last_rx_cons = tnapi->rx_rcb_ptr;
  8857. tnapi->last_tx_cons = tnapi->tx_cons;
  8858. }
  8859. }
  8860. static void tg3_timer(unsigned long __opaque)
  8861. {
  8862. struct tg3 *tp = (struct tg3 *) __opaque;
  8863. if (tp->irq_sync || tg3_flag(tp, RESET_TASK_PENDING))
  8864. goto restart_timer;
  8865. spin_lock(&tp->lock);
  8866. if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
  8867. tg3_flag(tp, 57765_CLASS))
  8868. tg3_chk_missed_msi(tp);
  8869. if (tg3_flag(tp, FLUSH_POSTED_WRITES)) {
  8870. /* BCM4785: Flush posted writes from GbE to host memory. */
  8871. tr32(HOSTCC_MODE);
  8872. }
  8873. if (!tg3_flag(tp, TAGGED_STATUS)) {
  8874. /* All of this garbage is because when using non-tagged
  8875. * IRQ status the mailbox/status_block protocol the chip
  8876. * uses with the cpu is race prone.
  8877. */
  8878. if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
  8879. tw32(GRC_LOCAL_CTRL,
  8880. tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
  8881. } else {
  8882. tw32(HOSTCC_MODE, tp->coalesce_mode |
  8883. HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
  8884. }
  8885. if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
  8886. spin_unlock(&tp->lock);
  8887. tg3_reset_task_schedule(tp);
  8888. goto restart_timer;
  8889. }
  8890. }
  8891. /* This part only runs once per second. */
  8892. if (!--tp->timer_counter) {
  8893. if (tg3_flag(tp, 5705_PLUS))
  8894. tg3_periodic_fetch_stats(tp);
  8895. if (tp->setlpicnt && !--tp->setlpicnt)
  8896. tg3_phy_eee_enable(tp);
  8897. if (tg3_flag(tp, USE_LINKCHG_REG)) {
  8898. u32 mac_stat;
  8899. int phy_event;
  8900. mac_stat = tr32(MAC_STATUS);
  8901. phy_event = 0;
  8902. if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) {
  8903. if (mac_stat & MAC_STATUS_MI_INTERRUPT)
  8904. phy_event = 1;
  8905. } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
  8906. phy_event = 1;
  8907. if (phy_event)
  8908. tg3_setup_phy(tp, false);
  8909. } else if (tg3_flag(tp, POLL_SERDES)) {
  8910. u32 mac_stat = tr32(MAC_STATUS);
  8911. int need_setup = 0;
  8912. if (tp->link_up &&
  8913. (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
  8914. need_setup = 1;
  8915. }
  8916. if (!tp->link_up &&
  8917. (mac_stat & (MAC_STATUS_PCS_SYNCED |
  8918. MAC_STATUS_SIGNAL_DET))) {
  8919. need_setup = 1;
  8920. }
  8921. if (need_setup) {
  8922. if (!tp->serdes_counter) {
  8923. tw32_f(MAC_MODE,
  8924. (tp->mac_mode &
  8925. ~MAC_MODE_PORT_MODE_MASK));
  8926. udelay(40);
  8927. tw32_f(MAC_MODE, tp->mac_mode);
  8928. udelay(40);
  8929. }
  8930. tg3_setup_phy(tp, false);
  8931. }
  8932. } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
  8933. tg3_flag(tp, 5780_CLASS)) {
  8934. tg3_serdes_parallel_detect(tp);
  8935. }
  8936. tp->timer_counter = tp->timer_multiplier;
  8937. }
  8938. /* Heartbeat is only sent once every 2 seconds.
  8939. *
  8940. * The heartbeat is to tell the ASF firmware that the host
  8941. * driver is still alive. In the event that the OS crashes,
  8942. * ASF needs to reset the hardware to free up the FIFO space
  8943. * that may be filled with rx packets destined for the host.
  8944. * If the FIFO is full, ASF will no longer function properly.
  8945. *
  8946. * Unintended resets have been reported on real time kernels
  8947. * where the timer doesn't run on time. Netpoll will also have
  8948. * same problem.
  8949. *
  8950. * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
  8951. * to check the ring condition when the heartbeat is expiring
  8952. * before doing the reset. This will prevent most unintended
  8953. * resets.
  8954. */
  8955. if (!--tp->asf_counter) {
  8956. if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
  8957. tg3_wait_for_event_ack(tp);
  8958. tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
  8959. FWCMD_NICDRV_ALIVE3);
  8960. tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
  8961. tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX,
  8962. TG3_FW_UPDATE_TIMEOUT_SEC);
  8963. tg3_generate_fw_event(tp);
  8964. }
  8965. tp->asf_counter = tp->asf_multiplier;
  8966. }
  8967. spin_unlock(&tp->lock);
  8968. restart_timer:
  8969. tp->timer.expires = jiffies + tp->timer_offset;
  8970. add_timer(&tp->timer);
  8971. }
  8972. static void tg3_timer_init(struct tg3 *tp)
  8973. {
  8974. if (tg3_flag(tp, TAGGED_STATUS) &&
  8975. tg3_asic_rev(tp) != ASIC_REV_5717 &&
  8976. !tg3_flag(tp, 57765_CLASS))
  8977. tp->timer_offset = HZ;
  8978. else
  8979. tp->timer_offset = HZ / 10;
  8980. BUG_ON(tp->timer_offset > HZ);
  8981. tp->timer_multiplier = (HZ / tp->timer_offset);
  8982. tp->asf_multiplier = (HZ / tp->timer_offset) *
  8983. TG3_FW_UPDATE_FREQ_SEC;
  8984. init_timer(&tp->timer);
  8985. tp->timer.data = (unsigned long) tp;
  8986. tp->timer.function = tg3_timer;
  8987. }
  8988. static void tg3_timer_start(struct tg3 *tp)
  8989. {
  8990. tp->asf_counter = tp->asf_multiplier;
  8991. tp->timer_counter = tp->timer_multiplier;
  8992. tp->timer.expires = jiffies + tp->timer_offset;
  8993. add_timer(&tp->timer);
  8994. }
  8995. static void tg3_timer_stop(struct tg3 *tp)
  8996. {
  8997. del_timer_sync(&tp->timer);
  8998. }
  8999. /* Restart hardware after configuration changes, self-test, etc.
  9000. * Invoked with tp->lock held.
  9001. */
  9002. static int tg3_restart_hw(struct tg3 *tp, bool reset_phy)
  9003. __releases(tp->lock)
  9004. __acquires(tp->lock)
  9005. {
  9006. int err;
  9007. err = tg3_init_hw(tp, reset_phy);
  9008. if (err) {
  9009. netdev_err(tp->dev,
  9010. "Failed to re-initialize device, aborting\n");
  9011. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  9012. tg3_full_unlock(tp);
  9013. tg3_timer_stop(tp);
  9014. tp->irq_sync = 0;
  9015. tg3_napi_enable(tp);
  9016. dev_close(tp->dev);
  9017. tg3_full_lock(tp, 0);
  9018. }
  9019. return err;
  9020. }
  9021. static void tg3_reset_task(struct work_struct *work)
  9022. {
  9023. struct tg3 *tp = container_of(work, struct tg3, reset_task);
  9024. int err;
  9025. tg3_full_lock(tp, 0);
  9026. if (!netif_running(tp->dev)) {
  9027. tg3_flag_clear(tp, RESET_TASK_PENDING);
  9028. tg3_full_unlock(tp);
  9029. return;
  9030. }
  9031. tg3_full_unlock(tp);
  9032. tg3_phy_stop(tp);
  9033. tg3_netif_stop(tp);
  9034. tg3_full_lock(tp, 1);
  9035. if (tg3_flag(tp, TX_RECOVERY_PENDING)) {
  9036. tp->write32_tx_mbox = tg3_write32_tx_mbox;
  9037. tp->write32_rx_mbox = tg3_write_flush_reg32;
  9038. tg3_flag_set(tp, MBOX_WRITE_REORDER);
  9039. tg3_flag_clear(tp, TX_RECOVERY_PENDING);
  9040. }
  9041. tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
  9042. err = tg3_init_hw(tp, true);
  9043. if (err)
  9044. goto out;
  9045. tg3_netif_start(tp);
  9046. out:
  9047. tg3_full_unlock(tp);
  9048. if (!err)
  9049. tg3_phy_start(tp);
  9050. tg3_flag_clear(tp, RESET_TASK_PENDING);
  9051. }
  9052. static int tg3_request_irq(struct tg3 *tp, int irq_num)
  9053. {
  9054. irq_handler_t fn;
  9055. unsigned long flags;
  9056. char *name;
  9057. struct tg3_napi *tnapi = &tp->napi[irq_num];
  9058. if (tp->irq_cnt == 1)
  9059. name = tp->dev->name;
  9060. else {
  9061. name = &tnapi->irq_lbl[0];
  9062. snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
  9063. name[IFNAMSIZ-1] = 0;
  9064. }
  9065. if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {
  9066. fn = tg3_msi;
  9067. if (tg3_flag(tp, 1SHOT_MSI))
  9068. fn = tg3_msi_1shot;
  9069. flags = 0;
  9070. } else {
  9071. fn = tg3_interrupt;
  9072. if (tg3_flag(tp, TAGGED_STATUS))
  9073. fn = tg3_interrupt_tagged;
  9074. flags = IRQF_SHARED;
  9075. }
  9076. return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
  9077. }
  9078. static int tg3_test_interrupt(struct tg3 *tp)
  9079. {
  9080. struct tg3_napi *tnapi = &tp->napi[0];
  9081. struct net_device *dev = tp->dev;
  9082. int err, i, intr_ok = 0;
  9083. u32 val;
  9084. if (!netif_running(dev))
  9085. return -ENODEV;
  9086. tg3_disable_ints(tp);
  9087. free_irq(tnapi->irq_vec, tnapi);
  9088. /*
  9089. * Turn off MSI one shot mode. Otherwise this test has no
  9090. * observable way to know whether the interrupt was delivered.
  9091. */
  9092. if (tg3_flag(tp, 57765_PLUS)) {
  9093. val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
  9094. tw32(MSGINT_MODE, val);
  9095. }
  9096. err = request_irq(tnapi->irq_vec, tg3_test_isr,
  9097. IRQF_SHARED, dev->name, tnapi);
  9098. if (err)
  9099. return err;
  9100. tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
  9101. tg3_enable_ints(tp);
  9102. tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
  9103. tnapi->coal_now);
  9104. for (i = 0; i < 5; i++) {
  9105. u32 int_mbox, misc_host_ctrl;
  9106. int_mbox = tr32_mailbox(tnapi->int_mbox);
  9107. misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
  9108. if ((int_mbox != 0) ||
  9109. (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
  9110. intr_ok = 1;
  9111. break;
  9112. }
  9113. if (tg3_flag(tp, 57765_PLUS) &&
  9114. tnapi->hw_status->status_tag != tnapi->last_tag)
  9115. tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
  9116. msleep(10);
  9117. }
  9118. tg3_disable_ints(tp);
  9119. free_irq(tnapi->irq_vec, tnapi);
  9120. err = tg3_request_irq(tp, 0);
  9121. if (err)
  9122. return err;
  9123. if (intr_ok) {
  9124. /* Reenable MSI one shot mode. */
  9125. if (tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, 1SHOT_MSI)) {
  9126. val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
  9127. tw32(MSGINT_MODE, val);
  9128. }
  9129. return 0;
  9130. }
  9131. return -EIO;
  9132. }
  9133. /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
  9134. * successfully restored
  9135. */
  9136. static int tg3_test_msi(struct tg3 *tp)
  9137. {
  9138. int err;
  9139. u16 pci_cmd;
  9140. if (!tg3_flag(tp, USING_MSI))
  9141. return 0;
  9142. /* Turn off SERR reporting in case MSI terminates with Master
  9143. * Abort.
  9144. */
  9145. pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
  9146. pci_write_config_word(tp->pdev, PCI_COMMAND,
  9147. pci_cmd & ~PCI_COMMAND_SERR);
  9148. err = tg3_test_interrupt(tp);
  9149. pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
  9150. if (!err)
  9151. return 0;
  9152. /* other failures */
  9153. if (err != -EIO)
  9154. return err;
  9155. /* MSI test failed, go back to INTx mode */
  9156. netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching "
  9157. "to INTx mode. Please report this failure to the PCI "
  9158. "maintainer and include system chipset information\n");
  9159. free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
  9160. pci_disable_msi(tp->pdev);
  9161. tg3_flag_clear(tp, USING_MSI);
  9162. tp->napi[0].irq_vec = tp->pdev->irq;
  9163. err = tg3_request_irq(tp, 0);
  9164. if (err)
  9165. return err;
  9166. /* Need to reset the chip because the MSI cycle may have terminated
  9167. * with Master Abort.
  9168. */
  9169. tg3_full_lock(tp, 1);
  9170. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  9171. err = tg3_init_hw(tp, true);
  9172. tg3_full_unlock(tp);
  9173. if (err)
  9174. free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
  9175. return err;
  9176. }
  9177. static int tg3_request_firmware(struct tg3 *tp)
  9178. {
  9179. const struct tg3_firmware_hdr *fw_hdr;
  9180. if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
  9181. netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",
  9182. tp->fw_needed);
  9183. return -ENOENT;
  9184. }
  9185. fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
  9186. /* Firmware blob starts with version numbers, followed by
  9187. * start address and _full_ length including BSS sections
  9188. * (which must be longer than the actual data, of course
  9189. */
  9190. tp->fw_len = be32_to_cpu(fw_hdr->len); /* includes bss */
  9191. if (tp->fw_len < (tp->fw->size - TG3_FW_HDR_LEN)) {
  9192. netdev_err(tp->dev, "bogus length %d in \"%s\"\n",
  9193. tp->fw_len, tp->fw_needed);
  9194. release_firmware(tp->fw);
  9195. tp->fw = NULL;
  9196. return -EINVAL;
  9197. }
  9198. /* We no longer need firmware; we have it. */
  9199. tp->fw_needed = NULL;
  9200. return 0;
  9201. }
  9202. static u32 tg3_irq_count(struct tg3 *tp)
  9203. {
  9204. u32 irq_cnt = max(tp->rxq_cnt, tp->txq_cnt);
  9205. if (irq_cnt > 1) {
  9206. /* We want as many rx rings enabled as there are cpus.
  9207. * In multiqueue MSI-X mode, the first MSI-X vector
  9208. * only deals with link interrupts, etc, so we add
  9209. * one to the number of vectors we are requesting.
  9210. */
  9211. irq_cnt = min_t(unsigned, irq_cnt + 1, tp->irq_max);
  9212. }
  9213. return irq_cnt;
  9214. }
  9215. static bool tg3_enable_msix(struct tg3 *tp)
  9216. {
  9217. int i, rc;
  9218. struct msix_entry msix_ent[TG3_IRQ_MAX_VECS];
  9219. tp->txq_cnt = tp->txq_req;
  9220. tp->rxq_cnt = tp->rxq_req;
  9221. if (!tp->rxq_cnt)
  9222. tp->rxq_cnt = netif_get_num_default_rss_queues();
  9223. if (tp->rxq_cnt > tp->rxq_max)
  9224. tp->rxq_cnt = tp->rxq_max;
  9225. /* Disable multiple TX rings by default. Simple round-robin hardware
  9226. * scheduling of the TX rings can cause starvation of rings with
  9227. * small packets when other rings have TSO or jumbo packets.
  9228. */
  9229. if (!tp->txq_req)
  9230. tp->txq_cnt = 1;
  9231. tp->irq_cnt = tg3_irq_count(tp);
  9232. for (i = 0; i < tp->irq_max; i++) {
  9233. msix_ent[i].entry = i;
  9234. msix_ent[i].vector = 0;
  9235. }
  9236. rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
  9237. if (rc < 0) {
  9238. return false;
  9239. } else if (rc != 0) {
  9240. if (pci_enable_msix(tp->pdev, msix_ent, rc))
  9241. return false;
  9242. netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n",
  9243. tp->irq_cnt, rc);
  9244. tp->irq_cnt = rc;
  9245. tp->rxq_cnt = max(rc - 1, 1);
  9246. if (tp->txq_cnt)
  9247. tp->txq_cnt = min(tp->rxq_cnt, tp->txq_max);
  9248. }
  9249. for (i = 0; i < tp->irq_max; i++)
  9250. tp->napi[i].irq_vec = msix_ent[i].vector;
  9251. if (netif_set_real_num_rx_queues(tp->dev, tp->rxq_cnt)) {
  9252. pci_disable_msix(tp->pdev);
  9253. return false;
  9254. }
  9255. if (tp->irq_cnt == 1)
  9256. return true;
  9257. tg3_flag_set(tp, ENABLE_RSS);
  9258. if (tp->txq_cnt > 1)
  9259. tg3_flag_set(tp, ENABLE_TSS);
  9260. netif_set_real_num_tx_queues(tp->dev, tp->txq_cnt);
  9261. return true;
  9262. }
  9263. static void tg3_ints_init(struct tg3 *tp)
  9264. {
  9265. if ((tg3_flag(tp, SUPPORT_MSI) || tg3_flag(tp, SUPPORT_MSIX)) &&
  9266. !tg3_flag(tp, TAGGED_STATUS)) {
  9267. /* All MSI supporting chips should support tagged
  9268. * status. Assert that this is the case.
  9269. */
  9270. netdev_warn(tp->dev,
  9271. "MSI without TAGGED_STATUS? Not using MSI\n");
  9272. goto defcfg;
  9273. }
  9274. if (tg3_flag(tp, SUPPORT_MSIX) && tg3_enable_msix(tp))
  9275. tg3_flag_set(tp, USING_MSIX);
  9276. else if (tg3_flag(tp, SUPPORT_MSI) && pci_enable_msi(tp->pdev) == 0)
  9277. tg3_flag_set(tp, USING_MSI);
  9278. if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {
  9279. u32 msi_mode = tr32(MSGINT_MODE);
  9280. if (tg3_flag(tp, USING_MSIX) && tp->irq_cnt > 1)
  9281. msi_mode |= MSGINT_MODE_MULTIVEC_EN;
  9282. if (!tg3_flag(tp, 1SHOT_MSI))
  9283. msi_mode |= MSGINT_MODE_ONE_SHOT_DISABLE;
  9284. tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
  9285. }
  9286. defcfg:
  9287. if (!tg3_flag(tp, USING_MSIX)) {
  9288. tp->irq_cnt = 1;
  9289. tp->napi[0].irq_vec = tp->pdev->irq;
  9290. }
  9291. if (tp->irq_cnt == 1) {
  9292. tp->txq_cnt = 1;
  9293. tp->rxq_cnt = 1;
  9294. netif_set_real_num_tx_queues(tp->dev, 1);
  9295. netif_set_real_num_rx_queues(tp->dev, 1);
  9296. }
  9297. }
  9298. static void tg3_ints_fini(struct tg3 *tp)
  9299. {
  9300. if (tg3_flag(tp, USING_MSIX))
  9301. pci_disable_msix(tp->pdev);
  9302. else if (tg3_flag(tp, USING_MSI))
  9303. pci_disable_msi(tp->pdev);
  9304. tg3_flag_clear(tp, USING_MSI);
  9305. tg3_flag_clear(tp, USING_MSIX);
  9306. tg3_flag_clear(tp, ENABLE_RSS);
  9307. tg3_flag_clear(tp, ENABLE_TSS);
  9308. }
  9309. static int tg3_start(struct tg3 *tp, bool reset_phy, bool test_irq,
  9310. bool init)
  9311. {
  9312. struct net_device *dev = tp->dev;
  9313. int i, err;
  9314. /*
  9315. * Setup interrupts first so we know how
  9316. * many NAPI resources to allocate
  9317. */
  9318. tg3_ints_init(tp);
  9319. tg3_rss_check_indir_tbl(tp);
  9320. /* The placement of this call is tied
  9321. * to the setup and use of Host TX descriptors.
  9322. */
  9323. err = tg3_alloc_consistent(tp);
  9324. if (err)
  9325. goto out_ints_fini;
  9326. tg3_napi_init(tp);
  9327. tg3_napi_enable(tp);
  9328. for (i = 0; i < tp->irq_cnt; i++) {
  9329. struct tg3_napi *tnapi = &tp->napi[i];
  9330. err = tg3_request_irq(tp, i);
  9331. if (err) {
  9332. for (i--; i >= 0; i--) {
  9333. tnapi = &tp->napi[i];
  9334. free_irq(tnapi->irq_vec, tnapi);
  9335. }
  9336. goto out_napi_fini;
  9337. }
  9338. }
  9339. tg3_full_lock(tp, 0);
  9340. if (init)
  9341. tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
  9342. err = tg3_init_hw(tp, reset_phy);
  9343. if (err) {
  9344. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  9345. tg3_free_rings(tp);
  9346. }
  9347. tg3_full_unlock(tp);
  9348. if (err)
  9349. goto out_free_irq;
  9350. if (test_irq && tg3_flag(tp, USING_MSI)) {
  9351. err = tg3_test_msi(tp);
  9352. if (err) {
  9353. tg3_full_lock(tp, 0);
  9354. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  9355. tg3_free_rings(tp);
  9356. tg3_full_unlock(tp);
  9357. goto out_napi_fini;
  9358. }
  9359. if (!tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, USING_MSI)) {
  9360. u32 val = tr32(PCIE_TRANSACTION_CFG);
  9361. tw32(PCIE_TRANSACTION_CFG,
  9362. val | PCIE_TRANS_CFG_1SHOT_MSI);
  9363. }
  9364. }
  9365. tg3_phy_start(tp);
  9366. tg3_hwmon_open(tp);
  9367. tg3_full_lock(tp, 0);
  9368. tg3_timer_start(tp);
  9369. tg3_flag_set(tp, INIT_COMPLETE);
  9370. tg3_enable_ints(tp);
  9371. if (init)
  9372. tg3_ptp_init(tp);
  9373. else
  9374. tg3_ptp_resume(tp);
  9375. tg3_full_unlock(tp);
  9376. netif_tx_start_all_queues(dev);
  9377. /*
  9378. * Reset loopback feature if it was turned on while the device was down
  9379. * make sure that it's installed properly now.
  9380. */
  9381. if (dev->features & NETIF_F_LOOPBACK)
  9382. tg3_set_loopback(dev, dev->features);
  9383. return 0;
  9384. out_free_irq:
  9385. for (i = tp->irq_cnt - 1; i >= 0; i--) {
  9386. struct tg3_napi *tnapi = &tp->napi[i];
  9387. free_irq(tnapi->irq_vec, tnapi);
  9388. }
  9389. out_napi_fini:
  9390. tg3_napi_disable(tp);
  9391. tg3_napi_fini(tp);
  9392. tg3_free_consistent(tp);
  9393. out_ints_fini:
  9394. tg3_ints_fini(tp);
  9395. return err;
  9396. }
  9397. static void tg3_stop(struct tg3 *tp)
  9398. {
  9399. int i;
  9400. tg3_reset_task_cancel(tp);
  9401. tg3_netif_stop(tp);
  9402. tg3_timer_stop(tp);
  9403. tg3_hwmon_close(tp);
  9404. tg3_phy_stop(tp);
  9405. tg3_full_lock(tp, 1);
  9406. tg3_disable_ints(tp);
  9407. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  9408. tg3_free_rings(tp);
  9409. tg3_flag_clear(tp, INIT_COMPLETE);
  9410. tg3_full_unlock(tp);
  9411. for (i = tp->irq_cnt - 1; i >= 0; i--) {
  9412. struct tg3_napi *tnapi = &tp->napi[i];
  9413. free_irq(tnapi->irq_vec, tnapi);
  9414. }
  9415. tg3_ints_fini(tp);
  9416. tg3_napi_fini(tp);
  9417. tg3_free_consistent(tp);
  9418. }
  9419. static int tg3_open(struct net_device *dev)
  9420. {
  9421. struct tg3 *tp = netdev_priv(dev);
  9422. int err;
  9423. if (tp->fw_needed) {
  9424. err = tg3_request_firmware(tp);
  9425. if (tg3_asic_rev(tp) == ASIC_REV_57766) {
  9426. if (err) {
  9427. netdev_warn(tp->dev, "EEE capability disabled\n");
  9428. tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP;
  9429. } else if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) {
  9430. netdev_warn(tp->dev, "EEE capability restored\n");
  9431. tp->phy_flags |= TG3_PHYFLG_EEE_CAP;
  9432. }
  9433. } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0) {
  9434. if (err)
  9435. return err;
  9436. } else if (err) {
  9437. netdev_warn(tp->dev, "TSO capability disabled\n");
  9438. tg3_flag_clear(tp, TSO_CAPABLE);
  9439. } else if (!tg3_flag(tp, TSO_CAPABLE)) {
  9440. netdev_notice(tp->dev, "TSO capability restored\n");
  9441. tg3_flag_set(tp, TSO_CAPABLE);
  9442. }
  9443. }
  9444. tg3_carrier_off(tp);
  9445. err = tg3_power_up(tp);
  9446. if (err)
  9447. return err;
  9448. tg3_full_lock(tp, 0);
  9449. tg3_disable_ints(tp);
  9450. tg3_flag_clear(tp, INIT_COMPLETE);
  9451. tg3_full_unlock(tp);
  9452. err = tg3_start(tp,
  9453. !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN),
  9454. true, true);
  9455. if (err) {
  9456. tg3_frob_aux_power(tp, false);
  9457. pci_set_power_state(tp->pdev, PCI_D3hot);
  9458. }
  9459. if (tg3_flag(tp, PTP_CAPABLE)) {
  9460. tp->ptp_clock = ptp_clock_register(&tp->ptp_info,
  9461. &tp->pdev->dev);
  9462. if (IS_ERR(tp->ptp_clock))
  9463. tp->ptp_clock = NULL;
  9464. }
  9465. return err;
  9466. }
  9467. static int tg3_close(struct net_device *dev)
  9468. {
  9469. struct tg3 *tp = netdev_priv(dev);
  9470. tg3_ptp_fini(tp);
  9471. tg3_stop(tp);
  9472. /* Clear stats across close / open calls */
  9473. memset(&tp->net_stats_prev, 0, sizeof(tp->net_stats_prev));
  9474. memset(&tp->estats_prev, 0, sizeof(tp->estats_prev));
  9475. tg3_power_down_prepare(tp);
  9476. tg3_carrier_off(tp);
  9477. return 0;
  9478. }
  9479. static inline u64 get_stat64(tg3_stat64_t *val)
  9480. {
  9481. return ((u64)val->high << 32) | ((u64)val->low);
  9482. }
  9483. static u64 tg3_calc_crc_errors(struct tg3 *tp)
  9484. {
  9485. struct tg3_hw_stats *hw_stats = tp->hw_stats;
  9486. if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
  9487. (tg3_asic_rev(tp) == ASIC_REV_5700 ||
  9488. tg3_asic_rev(tp) == ASIC_REV_5701)) {
  9489. u32 val;
  9490. if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
  9491. tg3_writephy(tp, MII_TG3_TEST1,
  9492. val | MII_TG3_TEST1_CRC_EN);
  9493. tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &val);
  9494. } else
  9495. val = 0;
  9496. tp->phy_crc_errors += val;
  9497. return tp->phy_crc_errors;
  9498. }
  9499. return get_stat64(&hw_stats->rx_fcs_errors);
  9500. }
  9501. #define ESTAT_ADD(member) \
  9502. estats->member = old_estats->member + \
  9503. get_stat64(&hw_stats->member)
  9504. static void tg3_get_estats(struct tg3 *tp, struct tg3_ethtool_stats *estats)
  9505. {
  9506. struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
  9507. struct tg3_hw_stats *hw_stats = tp->hw_stats;
  9508. ESTAT_ADD(rx_octets);
  9509. ESTAT_ADD(rx_fragments);
  9510. ESTAT_ADD(rx_ucast_packets);
  9511. ESTAT_ADD(rx_mcast_packets);
  9512. ESTAT_ADD(rx_bcast_packets);
  9513. ESTAT_ADD(rx_fcs_errors);
  9514. ESTAT_ADD(rx_align_errors);
  9515. ESTAT_ADD(rx_xon_pause_rcvd);
  9516. ESTAT_ADD(rx_xoff_pause_rcvd);
  9517. ESTAT_ADD(rx_mac_ctrl_rcvd);
  9518. ESTAT_ADD(rx_xoff_entered);
  9519. ESTAT_ADD(rx_frame_too_long_errors);
  9520. ESTAT_ADD(rx_jabbers);
  9521. ESTAT_ADD(rx_undersize_packets);
  9522. ESTAT_ADD(rx_in_length_errors);
  9523. ESTAT_ADD(rx_out_length_errors);
  9524. ESTAT_ADD(rx_64_or_less_octet_packets);
  9525. ESTAT_ADD(rx_65_to_127_octet_packets);
  9526. ESTAT_ADD(rx_128_to_255_octet_packets);
  9527. ESTAT_ADD(rx_256_to_511_octet_packets);
  9528. ESTAT_ADD(rx_512_to_1023_octet_packets);
  9529. ESTAT_ADD(rx_1024_to_1522_octet_packets);
  9530. ESTAT_ADD(rx_1523_to_2047_octet_packets);
  9531. ESTAT_ADD(rx_2048_to_4095_octet_packets);
  9532. ESTAT_ADD(rx_4096_to_8191_octet_packets);
  9533. ESTAT_ADD(rx_8192_to_9022_octet_packets);
  9534. ESTAT_ADD(tx_octets);
  9535. ESTAT_ADD(tx_collisions);
  9536. ESTAT_ADD(tx_xon_sent);
  9537. ESTAT_ADD(tx_xoff_sent);
  9538. ESTAT_ADD(tx_flow_control);
  9539. ESTAT_ADD(tx_mac_errors);
  9540. ESTAT_ADD(tx_single_collisions);
  9541. ESTAT_ADD(tx_mult_collisions);
  9542. ESTAT_ADD(tx_deferred);
  9543. ESTAT_ADD(tx_excessive_collisions);
  9544. ESTAT_ADD(tx_late_collisions);
  9545. ESTAT_ADD(tx_collide_2times);
  9546. ESTAT_ADD(tx_collide_3times);
  9547. ESTAT_ADD(tx_collide_4times);
  9548. ESTAT_ADD(tx_collide_5times);
  9549. ESTAT_ADD(tx_collide_6times);
  9550. ESTAT_ADD(tx_collide_7times);
  9551. ESTAT_ADD(tx_collide_8times);
  9552. ESTAT_ADD(tx_collide_9times);
  9553. ESTAT_ADD(tx_collide_10times);
  9554. ESTAT_ADD(tx_collide_11times);
  9555. ESTAT_ADD(tx_collide_12times);
  9556. ESTAT_ADD(tx_collide_13times);
  9557. ESTAT_ADD(tx_collide_14times);
  9558. ESTAT_ADD(tx_collide_15times);
  9559. ESTAT_ADD(tx_ucast_packets);
  9560. ESTAT_ADD(tx_mcast_packets);
  9561. ESTAT_ADD(tx_bcast_packets);
  9562. ESTAT_ADD(tx_carrier_sense_errors);
  9563. ESTAT_ADD(tx_discards);
  9564. ESTAT_ADD(tx_errors);
  9565. ESTAT_ADD(dma_writeq_full);
  9566. ESTAT_ADD(dma_write_prioq_full);
  9567. ESTAT_ADD(rxbds_empty);
  9568. ESTAT_ADD(rx_discards);
  9569. ESTAT_ADD(rx_errors);
  9570. ESTAT_ADD(rx_threshold_hit);
  9571. ESTAT_ADD(dma_readq_full);
  9572. ESTAT_ADD(dma_read_prioq_full);
  9573. ESTAT_ADD(tx_comp_queue_full);
  9574. ESTAT_ADD(ring_set_send_prod_index);
  9575. ESTAT_ADD(ring_status_update);
  9576. ESTAT_ADD(nic_irqs);
  9577. ESTAT_ADD(nic_avoided_irqs);
  9578. ESTAT_ADD(nic_tx_threshold_hit);
  9579. ESTAT_ADD(mbuf_lwm_thresh_hit);
  9580. }
  9581. static void tg3_get_nstats(struct tg3 *tp, struct rtnl_link_stats64 *stats)
  9582. {
  9583. struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev;
  9584. struct tg3_hw_stats *hw_stats = tp->hw_stats;
  9585. stats->rx_packets = old_stats->rx_packets +
  9586. get_stat64(&hw_stats->rx_ucast_packets) +
  9587. get_stat64(&hw_stats->rx_mcast_packets) +
  9588. get_stat64(&hw_stats->rx_bcast_packets);
  9589. stats->tx_packets = old_stats->tx_packets +
  9590. get_stat64(&hw_stats->tx_ucast_packets) +
  9591. get_stat64(&hw_stats->tx_mcast_packets) +
  9592. get_stat64(&hw_stats->tx_bcast_packets);
  9593. stats->rx_bytes = old_stats->rx_bytes +
  9594. get_stat64(&hw_stats->rx_octets);
  9595. stats->tx_bytes = old_stats->tx_bytes +
  9596. get_stat64(&hw_stats->tx_octets);
  9597. stats->rx_errors = old_stats->rx_errors +
  9598. get_stat64(&hw_stats->rx_errors);
  9599. stats->tx_errors = old_stats->tx_errors +
  9600. get_stat64(&hw_stats->tx_errors) +
  9601. get_stat64(&hw_stats->tx_mac_errors) +
  9602. get_stat64(&hw_stats->tx_carrier_sense_errors) +
  9603. get_stat64(&hw_stats->tx_discards);
  9604. stats->multicast = old_stats->multicast +
  9605. get_stat64(&hw_stats->rx_mcast_packets);
  9606. stats->collisions = old_stats->collisions +
  9607. get_stat64(&hw_stats->tx_collisions);
  9608. stats->rx_length_errors = old_stats->rx_length_errors +
  9609. get_stat64(&hw_stats->rx_frame_too_long_errors) +
  9610. get_stat64(&hw_stats->rx_undersize_packets);
  9611. stats->rx_over_errors = old_stats->rx_over_errors +
  9612. get_stat64(&hw_stats->rxbds_empty);
  9613. stats->rx_frame_errors = old_stats->rx_frame_errors +
  9614. get_stat64(&hw_stats->rx_align_errors);
  9615. stats->tx_aborted_errors = old_stats->tx_aborted_errors +
  9616. get_stat64(&hw_stats->tx_discards);
  9617. stats->tx_carrier_errors = old_stats->tx_carrier_errors +
  9618. get_stat64(&hw_stats->tx_carrier_sense_errors);
  9619. stats->rx_crc_errors = old_stats->rx_crc_errors +
  9620. tg3_calc_crc_errors(tp);
  9621. stats->rx_missed_errors = old_stats->rx_missed_errors +
  9622. get_stat64(&hw_stats->rx_discards);
  9623. stats->rx_dropped = tp->rx_dropped;
  9624. stats->tx_dropped = tp->tx_dropped;
  9625. }
  9626. static int tg3_get_regs_len(struct net_device *dev)
  9627. {
  9628. return TG3_REG_BLK_SIZE;
  9629. }
  9630. static void tg3_get_regs(struct net_device *dev,
  9631. struct ethtool_regs *regs, void *_p)
  9632. {
  9633. struct tg3 *tp = netdev_priv(dev);
  9634. regs->version = 0;
  9635. memset(_p, 0, TG3_REG_BLK_SIZE);
  9636. if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
  9637. return;
  9638. tg3_full_lock(tp, 0);
  9639. tg3_dump_legacy_regs(tp, (u32 *)_p);
  9640. tg3_full_unlock(tp);
  9641. }
  9642. static int tg3_get_eeprom_len(struct net_device *dev)
  9643. {
  9644. struct tg3 *tp = netdev_priv(dev);
  9645. return tp->nvram_size;
  9646. }
  9647. static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
  9648. {
  9649. struct tg3 *tp = netdev_priv(dev);
  9650. int ret;
  9651. u8 *pd;
  9652. u32 i, offset, len, b_offset, b_count;
  9653. __be32 val;
  9654. if (tg3_flag(tp, NO_NVRAM))
  9655. return -EINVAL;
  9656. offset = eeprom->offset;
  9657. len = eeprom->len;
  9658. eeprom->len = 0;
  9659. eeprom->magic = TG3_EEPROM_MAGIC;
  9660. if (offset & 3) {
  9661. /* adjustments to start on required 4 byte boundary */
  9662. b_offset = offset & 3;
  9663. b_count = 4 - b_offset;
  9664. if (b_count > len) {
  9665. /* i.e. offset=1 len=2 */
  9666. b_count = len;
  9667. }
  9668. ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
  9669. if (ret)
  9670. return ret;
  9671. memcpy(data, ((char *)&val) + b_offset, b_count);
  9672. len -= b_count;
  9673. offset += b_count;
  9674. eeprom->len += b_count;
  9675. }
  9676. /* read bytes up to the last 4 byte boundary */
  9677. pd = &data[eeprom->len];
  9678. for (i = 0; i < (len - (len & 3)); i += 4) {
  9679. ret = tg3_nvram_read_be32(tp, offset + i, &val);
  9680. if (ret) {
  9681. eeprom->len += i;
  9682. return ret;
  9683. }
  9684. memcpy(pd + i, &val, 4);
  9685. }
  9686. eeprom->len += i;
  9687. if (len & 3) {
  9688. /* read last bytes not ending on 4 byte boundary */
  9689. pd = &data[eeprom->len];
  9690. b_count = len & 3;
  9691. b_offset = offset + len - b_count;
  9692. ret = tg3_nvram_read_be32(tp, b_offset, &val);
  9693. if (ret)
  9694. return ret;
  9695. memcpy(pd, &val, b_count);
  9696. eeprom->len += b_count;
  9697. }
  9698. return 0;
  9699. }
  9700. static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
  9701. {
  9702. struct tg3 *tp = netdev_priv(dev);
  9703. int ret;
  9704. u32 offset, len, b_offset, odd_len;
  9705. u8 *buf;
  9706. __be32 start, end;
  9707. if (tg3_flag(tp, NO_NVRAM) ||
  9708. eeprom->magic != TG3_EEPROM_MAGIC)
  9709. return -EINVAL;
  9710. offset = eeprom->offset;
  9711. len = eeprom->len;
  9712. if ((b_offset = (offset & 3))) {
  9713. /* adjustments to start on required 4 byte boundary */
  9714. ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
  9715. if (ret)
  9716. return ret;
  9717. len += b_offset;
  9718. offset &= ~3;
  9719. if (len < 4)
  9720. len = 4;
  9721. }
  9722. odd_len = 0;
  9723. if (len & 3) {
  9724. /* adjustments to end on required 4 byte boundary */
  9725. odd_len = 1;
  9726. len = (len + 3) & ~3;
  9727. ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
  9728. if (ret)
  9729. return ret;
  9730. }
  9731. buf = data;
  9732. if (b_offset || odd_len) {
  9733. buf = kmalloc(len, GFP_KERNEL);
  9734. if (!buf)
  9735. return -ENOMEM;
  9736. if (b_offset)
  9737. memcpy(buf, &start, 4);
  9738. if (odd_len)
  9739. memcpy(buf+len-4, &end, 4);
  9740. memcpy(buf + b_offset, data, eeprom->len);
  9741. }
  9742. ret = tg3_nvram_write_block(tp, offset, len, buf);
  9743. if (buf != data)
  9744. kfree(buf);
  9745. return ret;
  9746. }
  9747. static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  9748. {
  9749. struct tg3 *tp = netdev_priv(dev);
  9750. if (tg3_flag(tp, USE_PHYLIB)) {
  9751. struct phy_device *phydev;
  9752. if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
  9753. return -EAGAIN;
  9754. phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
  9755. return phy_ethtool_gset(phydev, cmd);
  9756. }
  9757. cmd->supported = (SUPPORTED_Autoneg);
  9758. if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
  9759. cmd->supported |= (SUPPORTED_1000baseT_Half |
  9760. SUPPORTED_1000baseT_Full);
  9761. if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
  9762. cmd->supported |= (SUPPORTED_100baseT_Half |
  9763. SUPPORTED_100baseT_Full |
  9764. SUPPORTED_10baseT_Half |
  9765. SUPPORTED_10baseT_Full |
  9766. SUPPORTED_TP);
  9767. cmd->port = PORT_TP;
  9768. } else {
  9769. cmd->supported |= SUPPORTED_FIBRE;
  9770. cmd->port = PORT_FIBRE;
  9771. }
  9772. cmd->advertising = tp->link_config.advertising;
  9773. if (tg3_flag(tp, PAUSE_AUTONEG)) {
  9774. if (tp->link_config.flowctrl & FLOW_CTRL_RX) {
  9775. if (tp->link_config.flowctrl & FLOW_CTRL_TX) {
  9776. cmd->advertising |= ADVERTISED_Pause;
  9777. } else {
  9778. cmd->advertising |= ADVERTISED_Pause |
  9779. ADVERTISED_Asym_Pause;
  9780. }
  9781. } else if (tp->link_config.flowctrl & FLOW_CTRL_TX) {
  9782. cmd->advertising |= ADVERTISED_Asym_Pause;
  9783. }
  9784. }
  9785. if (netif_running(dev) && tp->link_up) {
  9786. ethtool_cmd_speed_set(cmd, tp->link_config.active_speed);
  9787. cmd->duplex = tp->link_config.active_duplex;
  9788. cmd->lp_advertising = tp->link_config.rmt_adv;
  9789. if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
  9790. if (tp->phy_flags & TG3_PHYFLG_MDIX_STATE)
  9791. cmd->eth_tp_mdix = ETH_TP_MDI_X;
  9792. else
  9793. cmd->eth_tp_mdix = ETH_TP_MDI;
  9794. }
  9795. } else {
  9796. ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN);
  9797. cmd->duplex = DUPLEX_UNKNOWN;
  9798. cmd->eth_tp_mdix = ETH_TP_MDI_INVALID;
  9799. }
  9800. cmd->phy_address = tp->phy_addr;
  9801. cmd->transceiver = XCVR_INTERNAL;
  9802. cmd->autoneg = tp->link_config.autoneg;
  9803. cmd->maxtxpkt = 0;
  9804. cmd->maxrxpkt = 0;
  9805. return 0;
  9806. }
  9807. static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  9808. {
  9809. struct tg3 *tp = netdev_priv(dev);
  9810. u32 speed = ethtool_cmd_speed(cmd);
  9811. if (tg3_flag(tp, USE_PHYLIB)) {
  9812. struct phy_device *phydev;
  9813. if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
  9814. return -EAGAIN;
  9815. phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
  9816. return phy_ethtool_sset(phydev, cmd);
  9817. }
  9818. if (cmd->autoneg != AUTONEG_ENABLE &&
  9819. cmd->autoneg != AUTONEG_DISABLE)
  9820. return -EINVAL;
  9821. if (cmd->autoneg == AUTONEG_DISABLE &&
  9822. cmd->duplex != DUPLEX_FULL &&
  9823. cmd->duplex != DUPLEX_HALF)
  9824. return -EINVAL;
  9825. if (cmd->autoneg == AUTONEG_ENABLE) {
  9826. u32 mask = ADVERTISED_Autoneg |
  9827. ADVERTISED_Pause |
  9828. ADVERTISED_Asym_Pause;
  9829. if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
  9830. mask |= ADVERTISED_1000baseT_Half |
  9831. ADVERTISED_1000baseT_Full;
  9832. if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
  9833. mask |= ADVERTISED_100baseT_Half |
  9834. ADVERTISED_100baseT_Full |
  9835. ADVERTISED_10baseT_Half |
  9836. ADVERTISED_10baseT_Full |
  9837. ADVERTISED_TP;
  9838. else
  9839. mask |= ADVERTISED_FIBRE;
  9840. if (cmd->advertising & ~mask)
  9841. return -EINVAL;
  9842. mask &= (ADVERTISED_1000baseT_Half |
  9843. ADVERTISED_1000baseT_Full |
  9844. ADVERTISED_100baseT_Half |
  9845. ADVERTISED_100baseT_Full |
  9846. ADVERTISED_10baseT_Half |
  9847. ADVERTISED_10baseT_Full);
  9848. cmd->advertising &= mask;
  9849. } else {
  9850. if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) {
  9851. if (speed != SPEED_1000)
  9852. return -EINVAL;
  9853. if (cmd->duplex != DUPLEX_FULL)
  9854. return -EINVAL;
  9855. } else {
  9856. if (speed != SPEED_100 &&
  9857. speed != SPEED_10)
  9858. return -EINVAL;
  9859. }
  9860. }
  9861. tg3_full_lock(tp, 0);
  9862. tp->link_config.autoneg = cmd->autoneg;
  9863. if (cmd->autoneg == AUTONEG_ENABLE) {
  9864. tp->link_config.advertising = (cmd->advertising |
  9865. ADVERTISED_Autoneg);
  9866. tp->link_config.speed = SPEED_UNKNOWN;
  9867. tp->link_config.duplex = DUPLEX_UNKNOWN;
  9868. } else {
  9869. tp->link_config.advertising = 0;
  9870. tp->link_config.speed = speed;
  9871. tp->link_config.duplex = cmd->duplex;
  9872. }
  9873. tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
  9874. tg3_warn_mgmt_link_flap(tp);
  9875. if (netif_running(dev))
  9876. tg3_setup_phy(tp, true);
  9877. tg3_full_unlock(tp);
  9878. return 0;
  9879. }
  9880. static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
  9881. {
  9882. struct tg3 *tp = netdev_priv(dev);
  9883. strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
  9884. strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
  9885. strlcpy(info->fw_version, tp->fw_ver, sizeof(info->fw_version));
  9886. strlcpy(info->bus_info, pci_name(tp->pdev), sizeof(info->bus_info));
  9887. }
  9888. static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
  9889. {
  9890. struct tg3 *tp = netdev_priv(dev);
  9891. if (tg3_flag(tp, WOL_CAP) && device_can_wakeup(&tp->pdev->dev))
  9892. wol->supported = WAKE_MAGIC;
  9893. else
  9894. wol->supported = 0;
  9895. wol->wolopts = 0;
  9896. if (tg3_flag(tp, WOL_ENABLE) && device_can_wakeup(&tp->pdev->dev))
  9897. wol->wolopts = WAKE_MAGIC;
  9898. memset(&wol->sopass, 0, sizeof(wol->sopass));
  9899. }
  9900. static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
  9901. {
  9902. struct tg3 *tp = netdev_priv(dev);
  9903. struct device *dp = &tp->pdev->dev;
  9904. if (wol->wolopts & ~WAKE_MAGIC)
  9905. return -EINVAL;
  9906. if ((wol->wolopts & WAKE_MAGIC) &&
  9907. !(tg3_flag(tp, WOL_CAP) && device_can_wakeup(dp)))
  9908. return -EINVAL;
  9909. device_set_wakeup_enable(dp, wol->wolopts & WAKE_MAGIC);
  9910. spin_lock_bh(&tp->lock);
  9911. if (device_may_wakeup(dp))
  9912. tg3_flag_set(tp, WOL_ENABLE);
  9913. else
  9914. tg3_flag_clear(tp, WOL_ENABLE);
  9915. spin_unlock_bh(&tp->lock);
  9916. return 0;
  9917. }
  9918. static u32 tg3_get_msglevel(struct net_device *dev)
  9919. {
  9920. struct tg3 *tp = netdev_priv(dev);
  9921. return tp->msg_enable;
  9922. }
  9923. static void tg3_set_msglevel(struct net_device *dev, u32 value)
  9924. {
  9925. struct tg3 *tp = netdev_priv(dev);
  9926. tp->msg_enable = value;
  9927. }
  9928. static int tg3_nway_reset(struct net_device *dev)
  9929. {
  9930. struct tg3 *tp = netdev_priv(dev);
  9931. int r;
  9932. if (!netif_running(dev))
  9933. return -EAGAIN;
  9934. if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
  9935. return -EINVAL;
  9936. tg3_warn_mgmt_link_flap(tp);
  9937. if (tg3_flag(tp, USE_PHYLIB)) {
  9938. if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
  9939. return -EAGAIN;
  9940. r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
  9941. } else {
  9942. u32 bmcr;
  9943. spin_lock_bh(&tp->lock);
  9944. r = -EINVAL;
  9945. tg3_readphy(tp, MII_BMCR, &bmcr);
  9946. if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
  9947. ((bmcr & BMCR_ANENABLE) ||
  9948. (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT))) {
  9949. tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
  9950. BMCR_ANENABLE);
  9951. r = 0;
  9952. }
  9953. spin_unlock_bh(&tp->lock);
  9954. }
  9955. return r;
  9956. }
  9957. static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
  9958. {
  9959. struct tg3 *tp = netdev_priv(dev);
  9960. ering->rx_max_pending = tp->rx_std_ring_mask;
  9961. if (tg3_flag(tp, JUMBO_RING_ENABLE))
  9962. ering->rx_jumbo_max_pending = tp->rx_jmb_ring_mask;
  9963. else
  9964. ering->rx_jumbo_max_pending = 0;
  9965. ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
  9966. ering->rx_pending = tp->rx_pending;
  9967. if (tg3_flag(tp, JUMBO_RING_ENABLE))
  9968. ering->rx_jumbo_pending = tp->rx_jumbo_pending;
  9969. else
  9970. ering->rx_jumbo_pending = 0;
  9971. ering->tx_pending = tp->napi[0].tx_pending;
  9972. }
  9973. static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
  9974. {
  9975. struct tg3 *tp = netdev_priv(dev);
  9976. int i, irq_sync = 0, err = 0;
  9977. if ((ering->rx_pending > tp->rx_std_ring_mask) ||
  9978. (ering->rx_jumbo_pending > tp->rx_jmb_ring_mask) ||
  9979. (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
  9980. (ering->tx_pending <= MAX_SKB_FRAGS) ||
  9981. (tg3_flag(tp, TSO_BUG) &&
  9982. (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
  9983. return -EINVAL;
  9984. if (netif_running(dev)) {
  9985. tg3_phy_stop(tp);
  9986. tg3_netif_stop(tp);
  9987. irq_sync = 1;
  9988. }
  9989. tg3_full_lock(tp, irq_sync);
  9990. tp->rx_pending = ering->rx_pending;
  9991. if (tg3_flag(tp, MAX_RXPEND_64) &&
  9992. tp->rx_pending > 63)
  9993. tp->rx_pending = 63;
  9994. tp->rx_jumbo_pending = ering->rx_jumbo_pending;
  9995. for (i = 0; i < tp->irq_max; i++)
  9996. tp->napi[i].tx_pending = ering->tx_pending;
  9997. if (netif_running(dev)) {
  9998. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  9999. err = tg3_restart_hw(tp, false);
  10000. if (!err)
  10001. tg3_netif_start(tp);
  10002. }
  10003. tg3_full_unlock(tp);
  10004. if (irq_sync && !err)
  10005. tg3_phy_start(tp);
  10006. return err;
  10007. }
  10008. static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
  10009. {
  10010. struct tg3 *tp = netdev_priv(dev);
  10011. epause->autoneg = !!tg3_flag(tp, PAUSE_AUTONEG);
  10012. if (tp->link_config.flowctrl & FLOW_CTRL_RX)
  10013. epause->rx_pause = 1;
  10014. else
  10015. epause->rx_pause = 0;
  10016. if (tp->link_config.flowctrl & FLOW_CTRL_TX)
  10017. epause->tx_pause = 1;
  10018. else
  10019. epause->tx_pause = 0;
  10020. }
  10021. static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
  10022. {
  10023. struct tg3 *tp = netdev_priv(dev);
  10024. int err = 0;
  10025. if (tp->link_config.autoneg == AUTONEG_ENABLE)
  10026. tg3_warn_mgmt_link_flap(tp);
  10027. if (tg3_flag(tp, USE_PHYLIB)) {
  10028. u32 newadv;
  10029. struct phy_device *phydev;
  10030. phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
  10031. if (!(phydev->supported & SUPPORTED_Pause) ||
  10032. (!(phydev->supported & SUPPORTED_Asym_Pause) &&
  10033. (epause->rx_pause != epause->tx_pause)))
  10034. return -EINVAL;
  10035. tp->link_config.flowctrl = 0;
  10036. if (epause->rx_pause) {
  10037. tp->link_config.flowctrl |= FLOW_CTRL_RX;
  10038. if (epause->tx_pause) {
  10039. tp->link_config.flowctrl |= FLOW_CTRL_TX;
  10040. newadv = ADVERTISED_Pause;
  10041. } else
  10042. newadv = ADVERTISED_Pause |
  10043. ADVERTISED_Asym_Pause;
  10044. } else if (epause->tx_pause) {
  10045. tp->link_config.flowctrl |= FLOW_CTRL_TX;
  10046. newadv = ADVERTISED_Asym_Pause;
  10047. } else
  10048. newadv = 0;
  10049. if (epause->autoneg)
  10050. tg3_flag_set(tp, PAUSE_AUTONEG);
  10051. else
  10052. tg3_flag_clear(tp, PAUSE_AUTONEG);
  10053. if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
  10054. u32 oldadv = phydev->advertising &
  10055. (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
  10056. if (oldadv != newadv) {
  10057. phydev->advertising &=
  10058. ~(ADVERTISED_Pause |
  10059. ADVERTISED_Asym_Pause);
  10060. phydev->advertising |= newadv;
  10061. if (phydev->autoneg) {
  10062. /*
  10063. * Always renegotiate the link to
  10064. * inform our link partner of our
  10065. * flow control settings, even if the
  10066. * flow control is forced. Let
  10067. * tg3_adjust_link() do the final
  10068. * flow control setup.
  10069. */
  10070. return phy_start_aneg(phydev);
  10071. }
  10072. }
  10073. if (!epause->autoneg)
  10074. tg3_setup_flow_control(tp, 0, 0);
  10075. } else {
  10076. tp->link_config.advertising &=
  10077. ~(ADVERTISED_Pause |
  10078. ADVERTISED_Asym_Pause);
  10079. tp->link_config.advertising |= newadv;
  10080. }
  10081. } else {
  10082. int irq_sync = 0;
  10083. if (netif_running(dev)) {
  10084. tg3_netif_stop(tp);
  10085. irq_sync = 1;
  10086. }
  10087. tg3_full_lock(tp, irq_sync);
  10088. if (epause->autoneg)
  10089. tg3_flag_set(tp, PAUSE_AUTONEG);
  10090. else
  10091. tg3_flag_clear(tp, PAUSE_AUTONEG);
  10092. if (epause->rx_pause)
  10093. tp->link_config.flowctrl |= FLOW_CTRL_RX;
  10094. else
  10095. tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
  10096. if (epause->tx_pause)
  10097. tp->link_config.flowctrl |= FLOW_CTRL_TX;
  10098. else
  10099. tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
  10100. if (netif_running(dev)) {
  10101. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  10102. err = tg3_restart_hw(tp, false);
  10103. if (!err)
  10104. tg3_netif_start(tp);
  10105. }
  10106. tg3_full_unlock(tp);
  10107. }
  10108. tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
  10109. return err;
  10110. }
  10111. static int tg3_get_sset_count(struct net_device *dev, int sset)
  10112. {
  10113. switch (sset) {
  10114. case ETH_SS_TEST:
  10115. return TG3_NUM_TEST;
  10116. case ETH_SS_STATS:
  10117. return TG3_NUM_STATS;
  10118. default:
  10119. return -EOPNOTSUPP;
  10120. }
  10121. }
  10122. static int tg3_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
  10123. u32 *rules __always_unused)
  10124. {
  10125. struct tg3 *tp = netdev_priv(dev);
  10126. if (!tg3_flag(tp, SUPPORT_MSIX))
  10127. return -EOPNOTSUPP;
  10128. switch (info->cmd) {
  10129. case ETHTOOL_GRXRINGS:
  10130. if (netif_running(tp->dev))
  10131. info->data = tp->rxq_cnt;
  10132. else {
  10133. info->data = num_online_cpus();
  10134. if (info->data > TG3_RSS_MAX_NUM_QS)
  10135. info->data = TG3_RSS_MAX_NUM_QS;
  10136. }
  10137. /* The first interrupt vector only
  10138. * handles link interrupts.
  10139. */
  10140. info->data -= 1;
  10141. return 0;
  10142. default:
  10143. return -EOPNOTSUPP;
  10144. }
  10145. }
  10146. static u32 tg3_get_rxfh_indir_size(struct net_device *dev)
  10147. {
  10148. u32 size = 0;
  10149. struct tg3 *tp = netdev_priv(dev);
  10150. if (tg3_flag(tp, SUPPORT_MSIX))
  10151. size = TG3_RSS_INDIR_TBL_SIZE;
  10152. return size;
  10153. }
  10154. static int tg3_get_rxfh_indir(struct net_device *dev, u32 *indir)
  10155. {
  10156. struct tg3 *tp = netdev_priv(dev);
  10157. int i;
  10158. for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
  10159. indir[i] = tp->rss_ind_tbl[i];
  10160. return 0;
  10161. }
  10162. static int tg3_set_rxfh_indir(struct net_device *dev, const u32 *indir)
  10163. {
  10164. struct tg3 *tp = netdev_priv(dev);
  10165. size_t i;
  10166. for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
  10167. tp->rss_ind_tbl[i] = indir[i];
  10168. if (!netif_running(dev) || !tg3_flag(tp, ENABLE_RSS))
  10169. return 0;
  10170. /* It is legal to write the indirection
  10171. * table while the device is running.
  10172. */
  10173. tg3_full_lock(tp, 0);
  10174. tg3_rss_write_indir_tbl(tp);
  10175. tg3_full_unlock(tp);
  10176. return 0;
  10177. }
  10178. static void tg3_get_channels(struct net_device *dev,
  10179. struct ethtool_channels *channel)
  10180. {
  10181. struct tg3 *tp = netdev_priv(dev);
  10182. u32 deflt_qs = netif_get_num_default_rss_queues();
  10183. channel->max_rx = tp->rxq_max;
  10184. channel->max_tx = tp->txq_max;
  10185. if (netif_running(dev)) {
  10186. channel->rx_count = tp->rxq_cnt;
  10187. channel->tx_count = tp->txq_cnt;
  10188. } else {
  10189. if (tp->rxq_req)
  10190. channel->rx_count = tp->rxq_req;
  10191. else
  10192. channel->rx_count = min(deflt_qs, tp->rxq_max);
  10193. if (tp->txq_req)
  10194. channel->tx_count = tp->txq_req;
  10195. else
  10196. channel->tx_count = min(deflt_qs, tp->txq_max);
  10197. }
  10198. }
  10199. static int tg3_set_channels(struct net_device *dev,
  10200. struct ethtool_channels *channel)
  10201. {
  10202. struct tg3 *tp = netdev_priv(dev);
  10203. if (!tg3_flag(tp, SUPPORT_MSIX))
  10204. return -EOPNOTSUPP;
  10205. if (channel->rx_count > tp->rxq_max ||
  10206. channel->tx_count > tp->txq_max)
  10207. return -EINVAL;
  10208. tp->rxq_req = channel->rx_count;
  10209. tp->txq_req = channel->tx_count;
  10210. if (!netif_running(dev))
  10211. return 0;
  10212. tg3_stop(tp);
  10213. tg3_carrier_off(tp);
  10214. tg3_start(tp, true, false, false);
  10215. return 0;
  10216. }
  10217. static void tg3_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
  10218. {
  10219. switch (stringset) {
  10220. case ETH_SS_STATS:
  10221. memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
  10222. break;
  10223. case ETH_SS_TEST:
  10224. memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
  10225. break;
  10226. default:
  10227. WARN_ON(1); /* we need a WARN() */
  10228. break;
  10229. }
  10230. }
  10231. static int tg3_set_phys_id(struct net_device *dev,
  10232. enum ethtool_phys_id_state state)
  10233. {
  10234. struct tg3 *tp = netdev_priv(dev);
  10235. if (!netif_running(tp->dev))
  10236. return -EAGAIN;
  10237. switch (state) {
  10238. case ETHTOOL_ID_ACTIVE:
  10239. return 1; /* cycle on/off once per second */
  10240. case ETHTOOL_ID_ON:
  10241. tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
  10242. LED_CTRL_1000MBPS_ON |
  10243. LED_CTRL_100MBPS_ON |
  10244. LED_CTRL_10MBPS_ON |
  10245. LED_CTRL_TRAFFIC_OVERRIDE |
  10246. LED_CTRL_TRAFFIC_BLINK |
  10247. LED_CTRL_TRAFFIC_LED);
  10248. break;
  10249. case ETHTOOL_ID_OFF:
  10250. tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
  10251. LED_CTRL_TRAFFIC_OVERRIDE);
  10252. break;
  10253. case ETHTOOL_ID_INACTIVE:
  10254. tw32(MAC_LED_CTRL, tp->led_ctrl);
  10255. break;
  10256. }
  10257. return 0;
  10258. }
  10259. static void tg3_get_ethtool_stats(struct net_device *dev,
  10260. struct ethtool_stats *estats, u64 *tmp_stats)
  10261. {
  10262. struct tg3 *tp = netdev_priv(dev);
  10263. if (tp->hw_stats)
  10264. tg3_get_estats(tp, (struct tg3_ethtool_stats *)tmp_stats);
  10265. else
  10266. memset(tmp_stats, 0, sizeof(struct tg3_ethtool_stats));
  10267. }
  10268. static __be32 *tg3_vpd_readblock(struct tg3 *tp, u32 *vpdlen)
  10269. {
  10270. int i;
  10271. __be32 *buf;
  10272. u32 offset = 0, len = 0;
  10273. u32 magic, val;
  10274. if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &magic))
  10275. return NULL;
  10276. if (magic == TG3_EEPROM_MAGIC) {
  10277. for (offset = TG3_NVM_DIR_START;
  10278. offset < TG3_NVM_DIR_END;
  10279. offset += TG3_NVM_DIRENT_SIZE) {
  10280. if (tg3_nvram_read(tp, offset, &val))
  10281. return NULL;
  10282. if ((val >> TG3_NVM_DIRTYPE_SHIFT) ==
  10283. TG3_NVM_DIRTYPE_EXTVPD)
  10284. break;
  10285. }
  10286. if (offset != TG3_NVM_DIR_END) {
  10287. len = (val & TG3_NVM_DIRTYPE_LENMSK) * 4;
  10288. if (tg3_nvram_read(tp, offset + 4, &offset))
  10289. return NULL;
  10290. offset = tg3_nvram_logical_addr(tp, offset);
  10291. }
  10292. }
  10293. if (!offset || !len) {
  10294. offset = TG3_NVM_VPD_OFF;
  10295. len = TG3_NVM_VPD_LEN;
  10296. }
  10297. buf = kmalloc(len, GFP_KERNEL);
  10298. if (buf == NULL)
  10299. return NULL;
  10300. if (magic == TG3_EEPROM_MAGIC) {
  10301. for (i = 0; i < len; i += 4) {
  10302. /* The data is in little-endian format in NVRAM.
  10303. * Use the big-endian read routines to preserve
  10304. * the byte order as it exists in NVRAM.
  10305. */
  10306. if (tg3_nvram_read_be32(tp, offset + i, &buf[i/4]))
  10307. goto error;
  10308. }
  10309. } else {
  10310. u8 *ptr;
  10311. ssize_t cnt;
  10312. unsigned int pos = 0;
  10313. ptr = (u8 *)&buf[0];
  10314. for (i = 0; pos < len && i < 3; i++, pos += cnt, ptr += cnt) {
  10315. cnt = pci_read_vpd(tp->pdev, pos,
  10316. len - pos, ptr);
  10317. if (cnt == -ETIMEDOUT || cnt == -EINTR)
  10318. cnt = 0;
  10319. else if (cnt < 0)
  10320. goto error;
  10321. }
  10322. if (pos != len)
  10323. goto error;
  10324. }
  10325. *vpdlen = len;
  10326. return buf;
  10327. error:
  10328. kfree(buf);
  10329. return NULL;
  10330. }
  10331. #define NVRAM_TEST_SIZE 0x100
  10332. #define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
  10333. #define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
  10334. #define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
  10335. #define NVRAM_SELFBOOT_FORMAT1_4_SIZE 0x20
  10336. #define NVRAM_SELFBOOT_FORMAT1_5_SIZE 0x24
  10337. #define NVRAM_SELFBOOT_FORMAT1_6_SIZE 0x50
  10338. #define NVRAM_SELFBOOT_HW_SIZE 0x20
  10339. #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
  10340. static int tg3_test_nvram(struct tg3 *tp)
  10341. {
  10342. u32 csum, magic, len;
  10343. __be32 *buf;
  10344. int i, j, k, err = 0, size;
  10345. if (tg3_flag(tp, NO_NVRAM))
  10346. return 0;
  10347. if (tg3_nvram_read(tp, 0, &magic) != 0)
  10348. return -EIO;
  10349. if (magic == TG3_EEPROM_MAGIC)
  10350. size = NVRAM_TEST_SIZE;
  10351. else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
  10352. if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
  10353. TG3_EEPROM_SB_FORMAT_1) {
  10354. switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
  10355. case TG3_EEPROM_SB_REVISION_0:
  10356. size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
  10357. break;
  10358. case TG3_EEPROM_SB_REVISION_2:
  10359. size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
  10360. break;
  10361. case TG3_EEPROM_SB_REVISION_3:
  10362. size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
  10363. break;
  10364. case TG3_EEPROM_SB_REVISION_4:
  10365. size = NVRAM_SELFBOOT_FORMAT1_4_SIZE;
  10366. break;
  10367. case TG3_EEPROM_SB_REVISION_5:
  10368. size = NVRAM_SELFBOOT_FORMAT1_5_SIZE;
  10369. break;
  10370. case TG3_EEPROM_SB_REVISION_6:
  10371. size = NVRAM_SELFBOOT_FORMAT1_6_SIZE;
  10372. break;
  10373. default:
  10374. return -EIO;
  10375. }
  10376. } else
  10377. return 0;
  10378. } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
  10379. size = NVRAM_SELFBOOT_HW_SIZE;
  10380. else
  10381. return -EIO;
  10382. buf = kmalloc(size, GFP_KERNEL);
  10383. if (buf == NULL)
  10384. return -ENOMEM;
  10385. err = -EIO;
  10386. for (i = 0, j = 0; i < size; i += 4, j++) {
  10387. err = tg3_nvram_read_be32(tp, i, &buf[j]);
  10388. if (err)
  10389. break;
  10390. }
  10391. if (i < size)
  10392. goto out;
  10393. /* Selfboot format */
  10394. magic = be32_to_cpu(buf[0]);
  10395. if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
  10396. TG3_EEPROM_MAGIC_FW) {
  10397. u8 *buf8 = (u8 *) buf, csum8 = 0;
  10398. if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
  10399. TG3_EEPROM_SB_REVISION_2) {
  10400. /* For rev 2, the csum doesn't include the MBA. */
  10401. for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
  10402. csum8 += buf8[i];
  10403. for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
  10404. csum8 += buf8[i];
  10405. } else {
  10406. for (i = 0; i < size; i++)
  10407. csum8 += buf8[i];
  10408. }
  10409. if (csum8 == 0) {
  10410. err = 0;
  10411. goto out;
  10412. }
  10413. err = -EIO;
  10414. goto out;
  10415. }
  10416. if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
  10417. TG3_EEPROM_MAGIC_HW) {
  10418. u8 data[NVRAM_SELFBOOT_DATA_SIZE];
  10419. u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
  10420. u8 *buf8 = (u8 *) buf;
  10421. /* Separate the parity bits and the data bytes. */
  10422. for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
  10423. if ((i == 0) || (i == 8)) {
  10424. int l;
  10425. u8 msk;
  10426. for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
  10427. parity[k++] = buf8[i] & msk;
  10428. i++;
  10429. } else if (i == 16) {
  10430. int l;
  10431. u8 msk;
  10432. for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
  10433. parity[k++] = buf8[i] & msk;
  10434. i++;
  10435. for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
  10436. parity[k++] = buf8[i] & msk;
  10437. i++;
  10438. }
  10439. data[j++] = buf8[i];
  10440. }
  10441. err = -EIO;
  10442. for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
  10443. u8 hw8 = hweight8(data[i]);
  10444. if ((hw8 & 0x1) && parity[i])
  10445. goto out;
  10446. else if (!(hw8 & 0x1) && !parity[i])
  10447. goto out;
  10448. }
  10449. err = 0;
  10450. goto out;
  10451. }
  10452. err = -EIO;
  10453. /* Bootstrap checksum at offset 0x10 */
  10454. csum = calc_crc((unsigned char *) buf, 0x10);
  10455. if (csum != le32_to_cpu(buf[0x10/4]))
  10456. goto out;
  10457. /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
  10458. csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
  10459. if (csum != le32_to_cpu(buf[0xfc/4]))
  10460. goto out;
  10461. kfree(buf);
  10462. buf = tg3_vpd_readblock(tp, &len);
  10463. if (!buf)
  10464. return -ENOMEM;
  10465. i = pci_vpd_find_tag((u8 *)buf, 0, len, PCI_VPD_LRDT_RO_DATA);
  10466. if (i > 0) {
  10467. j = pci_vpd_lrdt_size(&((u8 *)buf)[i]);
  10468. if (j < 0)
  10469. goto out;
  10470. if (i + PCI_VPD_LRDT_TAG_SIZE + j > len)
  10471. goto out;
  10472. i += PCI_VPD_LRDT_TAG_SIZE;
  10473. j = pci_vpd_find_info_keyword((u8 *)buf, i, j,
  10474. PCI_VPD_RO_KEYWORD_CHKSUM);
  10475. if (j > 0) {
  10476. u8 csum8 = 0;
  10477. j += PCI_VPD_INFO_FLD_HDR_SIZE;
  10478. for (i = 0; i <= j; i++)
  10479. csum8 += ((u8 *)buf)[i];
  10480. if (csum8)
  10481. goto out;
  10482. }
  10483. }
  10484. err = 0;
  10485. out:
  10486. kfree(buf);
  10487. return err;
  10488. }
  10489. #define TG3_SERDES_TIMEOUT_SEC 2
  10490. #define TG3_COPPER_TIMEOUT_SEC 6
  10491. static int tg3_test_link(struct tg3 *tp)
  10492. {
  10493. int i, max;
  10494. if (!netif_running(tp->dev))
  10495. return -ENODEV;
  10496. if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
  10497. max = TG3_SERDES_TIMEOUT_SEC;
  10498. else
  10499. max = TG3_COPPER_TIMEOUT_SEC;
  10500. for (i = 0; i < max; i++) {
  10501. if (tp->link_up)
  10502. return 0;
  10503. if (msleep_interruptible(1000))
  10504. break;
  10505. }
  10506. return -EIO;
  10507. }
  10508. /* Only test the commonly used registers */
  10509. static int tg3_test_registers(struct tg3 *tp)
  10510. {
  10511. int i, is_5705, is_5750;
  10512. u32 offset, read_mask, write_mask, val, save_val, read_val;
  10513. static struct {
  10514. u16 offset;
  10515. u16 flags;
  10516. #define TG3_FL_5705 0x1
  10517. #define TG3_FL_NOT_5705 0x2
  10518. #define TG3_FL_NOT_5788 0x4
  10519. #define TG3_FL_NOT_5750 0x8
  10520. u32 read_mask;
  10521. u32 write_mask;
  10522. } reg_tbl[] = {
  10523. /* MAC Control Registers */
  10524. { MAC_MODE, TG3_FL_NOT_5705,
  10525. 0x00000000, 0x00ef6f8c },
  10526. { MAC_MODE, TG3_FL_5705,
  10527. 0x00000000, 0x01ef6b8c },
  10528. { MAC_STATUS, TG3_FL_NOT_5705,
  10529. 0x03800107, 0x00000000 },
  10530. { MAC_STATUS, TG3_FL_5705,
  10531. 0x03800100, 0x00000000 },
  10532. { MAC_ADDR_0_HIGH, 0x0000,
  10533. 0x00000000, 0x0000ffff },
  10534. { MAC_ADDR_0_LOW, 0x0000,
  10535. 0x00000000, 0xffffffff },
  10536. { MAC_RX_MTU_SIZE, 0x0000,
  10537. 0x00000000, 0x0000ffff },
  10538. { MAC_TX_MODE, 0x0000,
  10539. 0x00000000, 0x00000070 },
  10540. { MAC_TX_LENGTHS, 0x0000,
  10541. 0x00000000, 0x00003fff },
  10542. { MAC_RX_MODE, TG3_FL_NOT_5705,
  10543. 0x00000000, 0x000007fc },
  10544. { MAC_RX_MODE, TG3_FL_5705,
  10545. 0x00000000, 0x000007dc },
  10546. { MAC_HASH_REG_0, 0x0000,
  10547. 0x00000000, 0xffffffff },
  10548. { MAC_HASH_REG_1, 0x0000,
  10549. 0x00000000, 0xffffffff },
  10550. { MAC_HASH_REG_2, 0x0000,
  10551. 0x00000000, 0xffffffff },
  10552. { MAC_HASH_REG_3, 0x0000,
  10553. 0x00000000, 0xffffffff },
  10554. /* Receive Data and Receive BD Initiator Control Registers. */
  10555. { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
  10556. 0x00000000, 0xffffffff },
  10557. { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
  10558. 0x00000000, 0xffffffff },
  10559. { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
  10560. 0x00000000, 0x00000003 },
  10561. { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
  10562. 0x00000000, 0xffffffff },
  10563. { RCVDBDI_STD_BD+0, 0x0000,
  10564. 0x00000000, 0xffffffff },
  10565. { RCVDBDI_STD_BD+4, 0x0000,
  10566. 0x00000000, 0xffffffff },
  10567. { RCVDBDI_STD_BD+8, 0x0000,
  10568. 0x00000000, 0xffff0002 },
  10569. { RCVDBDI_STD_BD+0xc, 0x0000,
  10570. 0x00000000, 0xffffffff },
  10571. /* Receive BD Initiator Control Registers. */
  10572. { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
  10573. 0x00000000, 0xffffffff },
  10574. { RCVBDI_STD_THRESH, TG3_FL_5705,
  10575. 0x00000000, 0x000003ff },
  10576. { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
  10577. 0x00000000, 0xffffffff },
  10578. /* Host Coalescing Control Registers. */
  10579. { HOSTCC_MODE, TG3_FL_NOT_5705,
  10580. 0x00000000, 0x00000004 },
  10581. { HOSTCC_MODE, TG3_FL_5705,
  10582. 0x00000000, 0x000000f6 },
  10583. { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
  10584. 0x00000000, 0xffffffff },
  10585. { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
  10586. 0x00000000, 0x000003ff },
  10587. { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
  10588. 0x00000000, 0xffffffff },
  10589. { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
  10590. 0x00000000, 0x000003ff },
  10591. { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
  10592. 0x00000000, 0xffffffff },
  10593. { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
  10594. 0x00000000, 0x000000ff },
  10595. { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
  10596. 0x00000000, 0xffffffff },
  10597. { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
  10598. 0x00000000, 0x000000ff },
  10599. { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
  10600. 0x00000000, 0xffffffff },
  10601. { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
  10602. 0x00000000, 0xffffffff },
  10603. { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
  10604. 0x00000000, 0xffffffff },
  10605. { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
  10606. 0x00000000, 0x000000ff },
  10607. { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
  10608. 0x00000000, 0xffffffff },
  10609. { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
  10610. 0x00000000, 0x000000ff },
  10611. { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
  10612. 0x00000000, 0xffffffff },
  10613. { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
  10614. 0x00000000, 0xffffffff },
  10615. { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
  10616. 0x00000000, 0xffffffff },
  10617. { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
  10618. 0x00000000, 0xffffffff },
  10619. { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
  10620. 0x00000000, 0xffffffff },
  10621. { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
  10622. 0xffffffff, 0x00000000 },
  10623. { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
  10624. 0xffffffff, 0x00000000 },
  10625. /* Buffer Manager Control Registers. */
  10626. { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
  10627. 0x00000000, 0x007fff80 },
  10628. { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
  10629. 0x00000000, 0x007fffff },
  10630. { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
  10631. 0x00000000, 0x0000003f },
  10632. { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
  10633. 0x00000000, 0x000001ff },
  10634. { BUFMGR_MB_HIGH_WATER, 0x0000,
  10635. 0x00000000, 0x000001ff },
  10636. { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
  10637. 0xffffffff, 0x00000000 },
  10638. { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
  10639. 0xffffffff, 0x00000000 },
  10640. /* Mailbox Registers */
  10641. { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
  10642. 0x00000000, 0x000001ff },
  10643. { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
  10644. 0x00000000, 0x000001ff },
  10645. { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
  10646. 0x00000000, 0x000007ff },
  10647. { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
  10648. 0x00000000, 0x000001ff },
  10649. { 0xffff, 0x0000, 0x00000000, 0x00000000 },
  10650. };
  10651. is_5705 = is_5750 = 0;
  10652. if (tg3_flag(tp, 5705_PLUS)) {
  10653. is_5705 = 1;
  10654. if (tg3_flag(tp, 5750_PLUS))
  10655. is_5750 = 1;
  10656. }
  10657. for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
  10658. if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
  10659. continue;
  10660. if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
  10661. continue;
  10662. if (tg3_flag(tp, IS_5788) &&
  10663. (reg_tbl[i].flags & TG3_FL_NOT_5788))
  10664. continue;
  10665. if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
  10666. continue;
  10667. offset = (u32) reg_tbl[i].offset;
  10668. read_mask = reg_tbl[i].read_mask;
  10669. write_mask = reg_tbl[i].write_mask;
  10670. /* Save the original register content */
  10671. save_val = tr32(offset);
  10672. /* Determine the read-only value. */
  10673. read_val = save_val & read_mask;
  10674. /* Write zero to the register, then make sure the read-only bits
  10675. * are not changed and the read/write bits are all zeros.
  10676. */
  10677. tw32(offset, 0);
  10678. val = tr32(offset);
  10679. /* Test the read-only and read/write bits. */
  10680. if (((val & read_mask) != read_val) || (val & write_mask))
  10681. goto out;
  10682. /* Write ones to all the bits defined by RdMask and WrMask, then
  10683. * make sure the read-only bits are not changed and the
  10684. * read/write bits are all ones.
  10685. */
  10686. tw32(offset, read_mask | write_mask);
  10687. val = tr32(offset);
  10688. /* Test the read-only bits. */
  10689. if ((val & read_mask) != read_val)
  10690. goto out;
  10691. /* Test the read/write bits. */
  10692. if ((val & write_mask) != write_mask)
  10693. goto out;
  10694. tw32(offset, save_val);
  10695. }
  10696. return 0;
  10697. out:
  10698. if (netif_msg_hw(tp))
  10699. netdev_err(tp->dev,
  10700. "Register test failed at offset %x\n", offset);
  10701. tw32(offset, save_val);
  10702. return -EIO;
  10703. }
  10704. static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
  10705. {
  10706. static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
  10707. int i;
  10708. u32 j;
  10709. for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
  10710. for (j = 0; j < len; j += 4) {
  10711. u32 val;
  10712. tg3_write_mem(tp, offset + j, test_pattern[i]);
  10713. tg3_read_mem(tp, offset + j, &val);
  10714. if (val != test_pattern[i])
  10715. return -EIO;
  10716. }
  10717. }
  10718. return 0;
  10719. }
  10720. static int tg3_test_memory(struct tg3 *tp)
  10721. {
  10722. static struct mem_entry {
  10723. u32 offset;
  10724. u32 len;
  10725. } mem_tbl_570x[] = {
  10726. { 0x00000000, 0x00b50},
  10727. { 0x00002000, 0x1c000},
  10728. { 0xffffffff, 0x00000}
  10729. }, mem_tbl_5705[] = {
  10730. { 0x00000100, 0x0000c},
  10731. { 0x00000200, 0x00008},
  10732. { 0x00004000, 0x00800},
  10733. { 0x00006000, 0x01000},
  10734. { 0x00008000, 0x02000},
  10735. { 0x00010000, 0x0e000},
  10736. { 0xffffffff, 0x00000}
  10737. }, mem_tbl_5755[] = {
  10738. { 0x00000200, 0x00008},
  10739. { 0x00004000, 0x00800},
  10740. { 0x00006000, 0x00800},
  10741. { 0x00008000, 0x02000},
  10742. { 0x00010000, 0x0c000},
  10743. { 0xffffffff, 0x00000}
  10744. }, mem_tbl_5906[] = {
  10745. { 0x00000200, 0x00008},
  10746. { 0x00004000, 0x00400},
  10747. { 0x00006000, 0x00400},
  10748. { 0x00008000, 0x01000},
  10749. { 0x00010000, 0x01000},
  10750. { 0xffffffff, 0x00000}
  10751. }, mem_tbl_5717[] = {
  10752. { 0x00000200, 0x00008},
  10753. { 0x00010000, 0x0a000},
  10754. { 0x00020000, 0x13c00},
  10755. { 0xffffffff, 0x00000}
  10756. }, mem_tbl_57765[] = {
  10757. { 0x00000200, 0x00008},
  10758. { 0x00004000, 0x00800},
  10759. { 0x00006000, 0x09800},
  10760. { 0x00010000, 0x0a000},
  10761. { 0xffffffff, 0x00000}
  10762. };
  10763. struct mem_entry *mem_tbl;
  10764. int err = 0;
  10765. int i;
  10766. if (tg3_flag(tp, 5717_PLUS))
  10767. mem_tbl = mem_tbl_5717;
  10768. else if (tg3_flag(tp, 57765_CLASS) ||
  10769. tg3_asic_rev(tp) == ASIC_REV_5762)
  10770. mem_tbl = mem_tbl_57765;
  10771. else if (tg3_flag(tp, 5755_PLUS))
  10772. mem_tbl = mem_tbl_5755;
  10773. else if (tg3_asic_rev(tp) == ASIC_REV_5906)
  10774. mem_tbl = mem_tbl_5906;
  10775. else if (tg3_flag(tp, 5705_PLUS))
  10776. mem_tbl = mem_tbl_5705;
  10777. else
  10778. mem_tbl = mem_tbl_570x;
  10779. for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
  10780. err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len);
  10781. if (err)
  10782. break;
  10783. }
  10784. return err;
  10785. }
  10786. #define TG3_TSO_MSS 500
  10787. #define TG3_TSO_IP_HDR_LEN 20
  10788. #define TG3_TSO_TCP_HDR_LEN 20
  10789. #define TG3_TSO_TCP_OPT_LEN 12
  10790. static const u8 tg3_tso_header[] = {
  10791. 0x08, 0x00,
  10792. 0x45, 0x00, 0x00, 0x00,
  10793. 0x00, 0x00, 0x40, 0x00,
  10794. 0x40, 0x06, 0x00, 0x00,
  10795. 0x0a, 0x00, 0x00, 0x01,
  10796. 0x0a, 0x00, 0x00, 0x02,
  10797. 0x0d, 0x00, 0xe0, 0x00,
  10798. 0x00, 0x00, 0x01, 0x00,
  10799. 0x00, 0x00, 0x02, 0x00,
  10800. 0x80, 0x10, 0x10, 0x00,
  10801. 0x14, 0x09, 0x00, 0x00,
  10802. 0x01, 0x01, 0x08, 0x0a,
  10803. 0x11, 0x11, 0x11, 0x11,
  10804. 0x11, 0x11, 0x11, 0x11,
  10805. };
  10806. static int tg3_run_loopback(struct tg3 *tp, u32 pktsz, bool tso_loopback)
  10807. {
  10808. u32 rx_start_idx, rx_idx, tx_idx, opaque_key;
  10809. u32 base_flags = 0, mss = 0, desc_idx, coal_now, data_off, val;
  10810. u32 budget;
  10811. struct sk_buff *skb;
  10812. u8 *tx_data, *rx_data;
  10813. dma_addr_t map;
  10814. int num_pkts, tx_len, rx_len, i, err;
  10815. struct tg3_rx_buffer_desc *desc;
  10816. struct tg3_napi *tnapi, *rnapi;
  10817. struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
  10818. tnapi = &tp->napi[0];
  10819. rnapi = &tp->napi[0];
  10820. if (tp->irq_cnt > 1) {
  10821. if (tg3_flag(tp, ENABLE_RSS))
  10822. rnapi = &tp->napi[1];
  10823. if (tg3_flag(tp, ENABLE_TSS))
  10824. tnapi = &tp->napi[1];
  10825. }
  10826. coal_now = tnapi->coal_now | rnapi->coal_now;
  10827. err = -EIO;
  10828. tx_len = pktsz;
  10829. skb = netdev_alloc_skb(tp->dev, tx_len);
  10830. if (!skb)
  10831. return -ENOMEM;
  10832. tx_data = skb_put(skb, tx_len);
  10833. memcpy(tx_data, tp->dev->dev_addr, 6);
  10834. memset(tx_data + 6, 0x0, 8);
  10835. tw32(MAC_RX_MTU_SIZE, tx_len + ETH_FCS_LEN);
  10836. if (tso_loopback) {
  10837. struct iphdr *iph = (struct iphdr *)&tx_data[ETH_HLEN];
  10838. u32 hdr_len = TG3_TSO_IP_HDR_LEN + TG3_TSO_TCP_HDR_LEN +
  10839. TG3_TSO_TCP_OPT_LEN;
  10840. memcpy(tx_data + ETH_ALEN * 2, tg3_tso_header,
  10841. sizeof(tg3_tso_header));
  10842. mss = TG3_TSO_MSS;
  10843. val = tx_len - ETH_ALEN * 2 - sizeof(tg3_tso_header);
  10844. num_pkts = DIV_ROUND_UP(val, TG3_TSO_MSS);
  10845. /* Set the total length field in the IP header */
  10846. iph->tot_len = htons((u16)(mss + hdr_len));
  10847. base_flags = (TXD_FLAG_CPU_PRE_DMA |
  10848. TXD_FLAG_CPU_POST_DMA);
  10849. if (tg3_flag(tp, HW_TSO_1) ||
  10850. tg3_flag(tp, HW_TSO_2) ||
  10851. tg3_flag(tp, HW_TSO_3)) {
  10852. struct tcphdr *th;
  10853. val = ETH_HLEN + TG3_TSO_IP_HDR_LEN;
  10854. th = (struct tcphdr *)&tx_data[val];
  10855. th->check = 0;
  10856. } else
  10857. base_flags |= TXD_FLAG_TCPUDP_CSUM;
  10858. if (tg3_flag(tp, HW_TSO_3)) {
  10859. mss |= (hdr_len & 0xc) << 12;
  10860. if (hdr_len & 0x10)
  10861. base_flags |= 0x00000010;
  10862. base_flags |= (hdr_len & 0x3e0) << 5;
  10863. } else if (tg3_flag(tp, HW_TSO_2))
  10864. mss |= hdr_len << 9;
  10865. else if (tg3_flag(tp, HW_TSO_1) ||
  10866. tg3_asic_rev(tp) == ASIC_REV_5705) {
  10867. mss |= (TG3_TSO_TCP_OPT_LEN << 9);
  10868. } else {
  10869. base_flags |= (TG3_TSO_TCP_OPT_LEN << 10);
  10870. }
  10871. data_off = ETH_ALEN * 2 + sizeof(tg3_tso_header);
  10872. } else {
  10873. num_pkts = 1;
  10874. data_off = ETH_HLEN;
  10875. if (tg3_flag(tp, USE_JUMBO_BDFLAG) &&
  10876. tx_len > VLAN_ETH_FRAME_LEN)
  10877. base_flags |= TXD_FLAG_JMB_PKT;
  10878. }
  10879. for (i = data_off; i < tx_len; i++)
  10880. tx_data[i] = (u8) (i & 0xff);
  10881. map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
  10882. if (pci_dma_mapping_error(tp->pdev, map)) {
  10883. dev_kfree_skb(skb);
  10884. return -EIO;
  10885. }
  10886. val = tnapi->tx_prod;
  10887. tnapi->tx_buffers[val].skb = skb;
  10888. dma_unmap_addr_set(&tnapi->tx_buffers[val], mapping, map);
  10889. tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
  10890. rnapi->coal_now);
  10891. udelay(10);
  10892. rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
  10893. budget = tg3_tx_avail(tnapi);
  10894. if (tg3_tx_frag_set(tnapi, &val, &budget, map, tx_len,
  10895. base_flags | TXD_FLAG_END, mss, 0)) {
  10896. tnapi->tx_buffers[val].skb = NULL;
  10897. dev_kfree_skb(skb);
  10898. return -EIO;
  10899. }
  10900. tnapi->tx_prod++;
  10901. /* Sync BD data before updating mailbox */
  10902. wmb();
  10903. tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
  10904. tr32_mailbox(tnapi->prodmbox);
  10905. udelay(10);
  10906. /* 350 usec to allow enough time on some 10/100 Mbps devices. */
  10907. for (i = 0; i < 35; i++) {
  10908. tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
  10909. coal_now);
  10910. udelay(10);
  10911. tx_idx = tnapi->hw_status->idx[0].tx_consumer;
  10912. rx_idx = rnapi->hw_status->idx[0].rx_producer;
  10913. if ((tx_idx == tnapi->tx_prod) &&
  10914. (rx_idx == (rx_start_idx + num_pkts)))
  10915. break;
  10916. }
  10917. tg3_tx_skb_unmap(tnapi, tnapi->tx_prod - 1, -1);
  10918. dev_kfree_skb(skb);
  10919. if (tx_idx != tnapi->tx_prod)
  10920. goto out;
  10921. if (rx_idx != rx_start_idx + num_pkts)
  10922. goto out;
  10923. val = data_off;
  10924. while (rx_idx != rx_start_idx) {
  10925. desc = &rnapi->rx_rcb[rx_start_idx++];
  10926. desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
  10927. opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
  10928. if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
  10929. (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
  10930. goto out;
  10931. rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT)
  10932. - ETH_FCS_LEN;
  10933. if (!tso_loopback) {
  10934. if (rx_len != tx_len)
  10935. goto out;
  10936. if (pktsz <= TG3_RX_STD_DMA_SZ - ETH_FCS_LEN) {
  10937. if (opaque_key != RXD_OPAQUE_RING_STD)
  10938. goto out;
  10939. } else {
  10940. if (opaque_key != RXD_OPAQUE_RING_JUMBO)
  10941. goto out;
  10942. }
  10943. } else if ((desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
  10944. (desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
  10945. >> RXD_TCPCSUM_SHIFT != 0xffff) {
  10946. goto out;
  10947. }
  10948. if (opaque_key == RXD_OPAQUE_RING_STD) {
  10949. rx_data = tpr->rx_std_buffers[desc_idx].data;
  10950. map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx],
  10951. mapping);
  10952. } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
  10953. rx_data = tpr->rx_jmb_buffers[desc_idx].data;
  10954. map = dma_unmap_addr(&tpr->rx_jmb_buffers[desc_idx],
  10955. mapping);
  10956. } else
  10957. goto out;
  10958. pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len,
  10959. PCI_DMA_FROMDEVICE);
  10960. rx_data += TG3_RX_OFFSET(tp);
  10961. for (i = data_off; i < rx_len; i++, val++) {
  10962. if (*(rx_data + i) != (u8) (val & 0xff))
  10963. goto out;
  10964. }
  10965. }
  10966. err = 0;
  10967. /* tg3_free_rings will unmap and free the rx_data */
  10968. out:
  10969. return err;
  10970. }
  10971. #define TG3_STD_LOOPBACK_FAILED 1
  10972. #define TG3_JMB_LOOPBACK_FAILED 2
  10973. #define TG3_TSO_LOOPBACK_FAILED 4
  10974. #define TG3_LOOPBACK_FAILED \
  10975. (TG3_STD_LOOPBACK_FAILED | \
  10976. TG3_JMB_LOOPBACK_FAILED | \
  10977. TG3_TSO_LOOPBACK_FAILED)
  10978. static int tg3_test_loopback(struct tg3 *tp, u64 *data, bool do_extlpbk)
  10979. {
  10980. int err = -EIO;
  10981. u32 eee_cap;
  10982. u32 jmb_pkt_sz = 9000;
  10983. if (tp->dma_limit)
  10984. jmb_pkt_sz = tp->dma_limit - ETH_HLEN;
  10985. eee_cap = tp->phy_flags & TG3_PHYFLG_EEE_CAP;
  10986. tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP;
  10987. if (!netif_running(tp->dev)) {
  10988. data[TG3_MAC_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
  10989. data[TG3_PHY_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
  10990. if (do_extlpbk)
  10991. data[TG3_EXT_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
  10992. goto done;
  10993. }
  10994. err = tg3_reset_hw(tp, true);
  10995. if (err) {
  10996. data[TG3_MAC_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
  10997. data[TG3_PHY_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
  10998. if (do_extlpbk)
  10999. data[TG3_EXT_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
  11000. goto done;
  11001. }
  11002. if (tg3_flag(tp, ENABLE_RSS)) {
  11003. int i;
  11004. /* Reroute all rx packets to the 1st queue */
  11005. for (i = MAC_RSS_INDIR_TBL_0;
  11006. i < MAC_RSS_INDIR_TBL_0 + TG3_RSS_INDIR_TBL_SIZE; i += 4)
  11007. tw32(i, 0x0);
  11008. }
  11009. /* HW errata - mac loopback fails in some cases on 5780.
  11010. * Normal traffic and PHY loopback are not affected by
  11011. * errata. Also, the MAC loopback test is deprecated for
  11012. * all newer ASIC revisions.
  11013. */
  11014. if (tg3_asic_rev(tp) != ASIC_REV_5780 &&
  11015. !tg3_flag(tp, CPMU_PRESENT)) {
  11016. tg3_mac_loopback(tp, true);
  11017. if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
  11018. data[TG3_MAC_LOOPB_TEST] |= TG3_STD_LOOPBACK_FAILED;
  11019. if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
  11020. tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
  11021. data[TG3_MAC_LOOPB_TEST] |= TG3_JMB_LOOPBACK_FAILED;
  11022. tg3_mac_loopback(tp, false);
  11023. }
  11024. if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
  11025. !tg3_flag(tp, USE_PHYLIB)) {
  11026. int i;
  11027. tg3_phy_lpbk_set(tp, 0, false);
  11028. /* Wait for link */
  11029. for (i = 0; i < 100; i++) {
  11030. if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
  11031. break;
  11032. mdelay(1);
  11033. }
  11034. if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
  11035. data[TG3_PHY_LOOPB_TEST] |= TG3_STD_LOOPBACK_FAILED;
  11036. if (tg3_flag(tp, TSO_CAPABLE) &&
  11037. tg3_run_loopback(tp, ETH_FRAME_LEN, true))
  11038. data[TG3_PHY_LOOPB_TEST] |= TG3_TSO_LOOPBACK_FAILED;
  11039. if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
  11040. tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
  11041. data[TG3_PHY_LOOPB_TEST] |= TG3_JMB_LOOPBACK_FAILED;
  11042. if (do_extlpbk) {
  11043. tg3_phy_lpbk_set(tp, 0, true);
  11044. /* All link indications report up, but the hardware
  11045. * isn't really ready for about 20 msec. Double it
  11046. * to be sure.
  11047. */
  11048. mdelay(40);
  11049. if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
  11050. data[TG3_EXT_LOOPB_TEST] |=
  11051. TG3_STD_LOOPBACK_FAILED;
  11052. if (tg3_flag(tp, TSO_CAPABLE) &&
  11053. tg3_run_loopback(tp, ETH_FRAME_LEN, true))
  11054. data[TG3_EXT_LOOPB_TEST] |=
  11055. TG3_TSO_LOOPBACK_FAILED;
  11056. if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
  11057. tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
  11058. data[TG3_EXT_LOOPB_TEST] |=
  11059. TG3_JMB_LOOPBACK_FAILED;
  11060. }
  11061. /* Re-enable gphy autopowerdown. */
  11062. if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
  11063. tg3_phy_toggle_apd(tp, true);
  11064. }
  11065. err = (data[TG3_MAC_LOOPB_TEST] | data[TG3_PHY_LOOPB_TEST] |
  11066. data[TG3_EXT_LOOPB_TEST]) ? -EIO : 0;
  11067. done:
  11068. tp->phy_flags |= eee_cap;
  11069. return err;
  11070. }
  11071. static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
  11072. u64 *data)
  11073. {
  11074. struct tg3 *tp = netdev_priv(dev);
  11075. bool doextlpbk = etest->flags & ETH_TEST_FL_EXTERNAL_LB;
  11076. if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
  11077. if (tg3_power_up(tp)) {
  11078. etest->flags |= ETH_TEST_FL_FAILED;
  11079. memset(data, 1, sizeof(u64) * TG3_NUM_TEST);
  11080. return;
  11081. }
  11082. tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
  11083. }
  11084. memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
  11085. if (tg3_test_nvram(tp) != 0) {
  11086. etest->flags |= ETH_TEST_FL_FAILED;
  11087. data[TG3_NVRAM_TEST] = 1;
  11088. }
  11089. if (!doextlpbk && tg3_test_link(tp)) {
  11090. etest->flags |= ETH_TEST_FL_FAILED;
  11091. data[TG3_LINK_TEST] = 1;
  11092. }
  11093. if (etest->flags & ETH_TEST_FL_OFFLINE) {
  11094. int err, err2 = 0, irq_sync = 0;
  11095. if (netif_running(dev)) {
  11096. tg3_phy_stop(tp);
  11097. tg3_netif_stop(tp);
  11098. irq_sync = 1;
  11099. }
  11100. tg3_full_lock(tp, irq_sync);
  11101. tg3_halt(tp, RESET_KIND_SUSPEND, 1);
  11102. err = tg3_nvram_lock(tp);
  11103. tg3_halt_cpu(tp, RX_CPU_BASE);
  11104. if (!tg3_flag(tp, 5705_PLUS))
  11105. tg3_halt_cpu(tp, TX_CPU_BASE);
  11106. if (!err)
  11107. tg3_nvram_unlock(tp);
  11108. if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
  11109. tg3_phy_reset(tp);
  11110. if (tg3_test_registers(tp) != 0) {
  11111. etest->flags |= ETH_TEST_FL_FAILED;
  11112. data[TG3_REGISTER_TEST] = 1;
  11113. }
  11114. if (tg3_test_memory(tp) != 0) {
  11115. etest->flags |= ETH_TEST_FL_FAILED;
  11116. data[TG3_MEMORY_TEST] = 1;
  11117. }
  11118. if (doextlpbk)
  11119. etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE;
  11120. if (tg3_test_loopback(tp, data, doextlpbk))
  11121. etest->flags |= ETH_TEST_FL_FAILED;
  11122. tg3_full_unlock(tp);
  11123. if (tg3_test_interrupt(tp) != 0) {
  11124. etest->flags |= ETH_TEST_FL_FAILED;
  11125. data[TG3_INTERRUPT_TEST] = 1;
  11126. }
  11127. tg3_full_lock(tp, 0);
  11128. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  11129. if (netif_running(dev)) {
  11130. tg3_flag_set(tp, INIT_COMPLETE);
  11131. err2 = tg3_restart_hw(tp, true);
  11132. if (!err2)
  11133. tg3_netif_start(tp);
  11134. }
  11135. tg3_full_unlock(tp);
  11136. if (irq_sync && !err2)
  11137. tg3_phy_start(tp);
  11138. }
  11139. if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
  11140. tg3_power_down_prepare(tp);
  11141. }
  11142. static int tg3_hwtstamp_ioctl(struct net_device *dev,
  11143. struct ifreq *ifr, int cmd)
  11144. {
  11145. struct tg3 *tp = netdev_priv(dev);
  11146. struct hwtstamp_config stmpconf;
  11147. if (!tg3_flag(tp, PTP_CAPABLE))
  11148. return -EINVAL;
  11149. if (copy_from_user(&stmpconf, ifr->ifr_data, sizeof(stmpconf)))
  11150. return -EFAULT;
  11151. if (stmpconf.flags)
  11152. return -EINVAL;
  11153. switch (stmpconf.tx_type) {
  11154. case HWTSTAMP_TX_ON:
  11155. tg3_flag_set(tp, TX_TSTAMP_EN);
  11156. break;
  11157. case HWTSTAMP_TX_OFF:
  11158. tg3_flag_clear(tp, TX_TSTAMP_EN);
  11159. break;
  11160. default:
  11161. return -ERANGE;
  11162. }
  11163. switch (stmpconf.rx_filter) {
  11164. case HWTSTAMP_FILTER_NONE:
  11165. tp->rxptpctl = 0;
  11166. break;
  11167. case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
  11168. tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN |
  11169. TG3_RX_PTP_CTL_ALL_V1_EVENTS;
  11170. break;
  11171. case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
  11172. tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN |
  11173. TG3_RX_PTP_CTL_SYNC_EVNT;
  11174. break;
  11175. case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
  11176. tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN |
  11177. TG3_RX_PTP_CTL_DELAY_REQ;
  11178. break;
  11179. case HWTSTAMP_FILTER_PTP_V2_EVENT:
  11180. tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN |
  11181. TG3_RX_PTP_CTL_ALL_V2_EVENTS;
  11182. break;
  11183. case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
  11184. tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN |
  11185. TG3_RX_PTP_CTL_ALL_V2_EVENTS;
  11186. break;
  11187. case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
  11188. tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN |
  11189. TG3_RX_PTP_CTL_ALL_V2_EVENTS;
  11190. break;
  11191. case HWTSTAMP_FILTER_PTP_V2_SYNC:
  11192. tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN |
  11193. TG3_RX_PTP_CTL_SYNC_EVNT;
  11194. break;
  11195. case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
  11196. tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN |
  11197. TG3_RX_PTP_CTL_SYNC_EVNT;
  11198. break;
  11199. case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
  11200. tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN |
  11201. TG3_RX_PTP_CTL_SYNC_EVNT;
  11202. break;
  11203. case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
  11204. tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN |
  11205. TG3_RX_PTP_CTL_DELAY_REQ;
  11206. break;
  11207. case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
  11208. tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN |
  11209. TG3_RX_PTP_CTL_DELAY_REQ;
  11210. break;
  11211. case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
  11212. tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN |
  11213. TG3_RX_PTP_CTL_DELAY_REQ;
  11214. break;
  11215. default:
  11216. return -ERANGE;
  11217. }
  11218. if (netif_running(dev) && tp->rxptpctl)
  11219. tw32(TG3_RX_PTP_CTL,
  11220. tp->rxptpctl | TG3_RX_PTP_CTL_HWTS_INTERLOCK);
  11221. return copy_to_user(ifr->ifr_data, &stmpconf, sizeof(stmpconf)) ?
  11222. -EFAULT : 0;
  11223. }
  11224. static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
  11225. {
  11226. struct mii_ioctl_data *data = if_mii(ifr);
  11227. struct tg3 *tp = netdev_priv(dev);
  11228. int err;
  11229. if (tg3_flag(tp, USE_PHYLIB)) {
  11230. struct phy_device *phydev;
  11231. if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
  11232. return -EAGAIN;
  11233. phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
  11234. return phy_mii_ioctl(phydev, ifr, cmd);
  11235. }
  11236. switch (cmd) {
  11237. case SIOCGMIIPHY:
  11238. data->phy_id = tp->phy_addr;
  11239. /* fallthru */
  11240. case SIOCGMIIREG: {
  11241. u32 mii_regval;
  11242. if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
  11243. break; /* We have no PHY */
  11244. if (!netif_running(dev))
  11245. return -EAGAIN;
  11246. spin_lock_bh(&tp->lock);
  11247. err = __tg3_readphy(tp, data->phy_id & 0x1f,
  11248. data->reg_num & 0x1f, &mii_regval);
  11249. spin_unlock_bh(&tp->lock);
  11250. data->val_out = mii_regval;
  11251. return err;
  11252. }
  11253. case SIOCSMIIREG:
  11254. if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
  11255. break; /* We have no PHY */
  11256. if (!netif_running(dev))
  11257. return -EAGAIN;
  11258. spin_lock_bh(&tp->lock);
  11259. err = __tg3_writephy(tp, data->phy_id & 0x1f,
  11260. data->reg_num & 0x1f, data->val_in);
  11261. spin_unlock_bh(&tp->lock);
  11262. return err;
  11263. case SIOCSHWTSTAMP:
  11264. return tg3_hwtstamp_ioctl(dev, ifr, cmd);
  11265. default:
  11266. /* do nothing */
  11267. break;
  11268. }
  11269. return -EOPNOTSUPP;
  11270. }
  11271. static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
  11272. {
  11273. struct tg3 *tp = netdev_priv(dev);
  11274. memcpy(ec, &tp->coal, sizeof(*ec));
  11275. return 0;
  11276. }
  11277. static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
  11278. {
  11279. struct tg3 *tp = netdev_priv(dev);
  11280. u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
  11281. u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
  11282. if (!tg3_flag(tp, 5705_PLUS)) {
  11283. max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
  11284. max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
  11285. max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
  11286. min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
  11287. }
  11288. if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
  11289. (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
  11290. (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
  11291. (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
  11292. (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
  11293. (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
  11294. (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
  11295. (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
  11296. (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
  11297. (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
  11298. return -EINVAL;
  11299. /* No rx interrupts will be generated if both are zero */
  11300. if ((ec->rx_coalesce_usecs == 0) &&
  11301. (ec->rx_max_coalesced_frames == 0))
  11302. return -EINVAL;
  11303. /* No tx interrupts will be generated if both are zero */
  11304. if ((ec->tx_coalesce_usecs == 0) &&
  11305. (ec->tx_max_coalesced_frames == 0))
  11306. return -EINVAL;
  11307. /* Only copy relevant parameters, ignore all others. */
  11308. tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
  11309. tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
  11310. tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
  11311. tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
  11312. tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
  11313. tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
  11314. tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
  11315. tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
  11316. tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
  11317. if (netif_running(dev)) {
  11318. tg3_full_lock(tp, 0);
  11319. __tg3_set_coalesce(tp, &tp->coal);
  11320. tg3_full_unlock(tp);
  11321. }
  11322. return 0;
  11323. }
  11324. static int tg3_set_eee(struct net_device *dev, struct ethtool_eee *edata)
  11325. {
  11326. struct tg3 *tp = netdev_priv(dev);
  11327. if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) {
  11328. netdev_warn(tp->dev, "Board does not support EEE!\n");
  11329. return -EOPNOTSUPP;
  11330. }
  11331. if (edata->advertised != tp->eee.advertised) {
  11332. netdev_warn(tp->dev,
  11333. "Direct manipulation of EEE advertisement is not supported\n");
  11334. return -EINVAL;
  11335. }
  11336. if (edata->tx_lpi_timer > TG3_CPMU_DBTMR1_LNKIDLE_MAX) {
  11337. netdev_warn(tp->dev,
  11338. "Maximal Tx Lpi timer supported is %#x(u)\n",
  11339. TG3_CPMU_DBTMR1_LNKIDLE_MAX);
  11340. return -EINVAL;
  11341. }
  11342. tp->eee = *edata;
  11343. tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
  11344. tg3_warn_mgmt_link_flap(tp);
  11345. if (netif_running(tp->dev)) {
  11346. tg3_full_lock(tp, 0);
  11347. tg3_setup_eee(tp);
  11348. tg3_phy_reset(tp);
  11349. tg3_full_unlock(tp);
  11350. }
  11351. return 0;
  11352. }
  11353. static int tg3_get_eee(struct net_device *dev, struct ethtool_eee *edata)
  11354. {
  11355. struct tg3 *tp = netdev_priv(dev);
  11356. if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) {
  11357. netdev_warn(tp->dev,
  11358. "Board does not support EEE!\n");
  11359. return -EOPNOTSUPP;
  11360. }
  11361. *edata = tp->eee;
  11362. return 0;
  11363. }
  11364. static const struct ethtool_ops tg3_ethtool_ops = {
  11365. .get_settings = tg3_get_settings,
  11366. .set_settings = tg3_set_settings,
  11367. .get_drvinfo = tg3_get_drvinfo,
  11368. .get_regs_len = tg3_get_regs_len,
  11369. .get_regs = tg3_get_regs,
  11370. .get_wol = tg3_get_wol,
  11371. .set_wol = tg3_set_wol,
  11372. .get_msglevel = tg3_get_msglevel,
  11373. .set_msglevel = tg3_set_msglevel,
  11374. .nway_reset = tg3_nway_reset,
  11375. .get_link = ethtool_op_get_link,
  11376. .get_eeprom_len = tg3_get_eeprom_len,
  11377. .get_eeprom = tg3_get_eeprom,
  11378. .set_eeprom = tg3_set_eeprom,
  11379. .get_ringparam = tg3_get_ringparam,
  11380. .set_ringparam = tg3_set_ringparam,
  11381. .get_pauseparam = tg3_get_pauseparam,
  11382. .set_pauseparam = tg3_set_pauseparam,
  11383. .self_test = tg3_self_test,
  11384. .get_strings = tg3_get_strings,
  11385. .set_phys_id = tg3_set_phys_id,
  11386. .get_ethtool_stats = tg3_get_ethtool_stats,
  11387. .get_coalesce = tg3_get_coalesce,
  11388. .set_coalesce = tg3_set_coalesce,
  11389. .get_sset_count = tg3_get_sset_count,
  11390. .get_rxnfc = tg3_get_rxnfc,
  11391. .get_rxfh_indir_size = tg3_get_rxfh_indir_size,
  11392. .get_rxfh_indir = tg3_get_rxfh_indir,
  11393. .set_rxfh_indir = tg3_set_rxfh_indir,
  11394. .get_channels = tg3_get_channels,
  11395. .set_channels = tg3_set_channels,
  11396. .get_ts_info = tg3_get_ts_info,
  11397. .get_eee = tg3_get_eee,
  11398. .set_eee = tg3_set_eee,
  11399. };
  11400. static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *dev,
  11401. struct rtnl_link_stats64 *stats)
  11402. {
  11403. struct tg3 *tp = netdev_priv(dev);
  11404. spin_lock_bh(&tp->lock);
  11405. if (!tp->hw_stats) {
  11406. spin_unlock_bh(&tp->lock);
  11407. return &tp->net_stats_prev;
  11408. }
  11409. tg3_get_nstats(tp, stats);
  11410. spin_unlock_bh(&tp->lock);
  11411. return stats;
  11412. }
  11413. static void tg3_set_rx_mode(struct net_device *dev)
  11414. {
  11415. struct tg3 *tp = netdev_priv(dev);
  11416. if (!netif_running(dev))
  11417. return;
  11418. tg3_full_lock(tp, 0);
  11419. __tg3_set_rx_mode(dev);
  11420. tg3_full_unlock(tp);
  11421. }
  11422. static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
  11423. int new_mtu)
  11424. {
  11425. dev->mtu = new_mtu;
  11426. if (new_mtu > ETH_DATA_LEN) {
  11427. if (tg3_flag(tp, 5780_CLASS)) {
  11428. netdev_update_features(dev);
  11429. tg3_flag_clear(tp, TSO_CAPABLE);
  11430. } else {
  11431. tg3_flag_set(tp, JUMBO_RING_ENABLE);
  11432. }
  11433. } else {
  11434. if (tg3_flag(tp, 5780_CLASS)) {
  11435. tg3_flag_set(tp, TSO_CAPABLE);
  11436. netdev_update_features(dev);
  11437. }
  11438. tg3_flag_clear(tp, JUMBO_RING_ENABLE);
  11439. }
  11440. }
  11441. static int tg3_change_mtu(struct net_device *dev, int new_mtu)
  11442. {
  11443. struct tg3 *tp = netdev_priv(dev);
  11444. int err;
  11445. bool reset_phy = false;
  11446. if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
  11447. return -EINVAL;
  11448. if (!netif_running(dev)) {
  11449. /* We'll just catch it later when the
  11450. * device is up'd.
  11451. */
  11452. tg3_set_mtu(dev, tp, new_mtu);
  11453. return 0;
  11454. }
  11455. tg3_phy_stop(tp);
  11456. tg3_netif_stop(tp);
  11457. tg3_full_lock(tp, 1);
  11458. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  11459. tg3_set_mtu(dev, tp, new_mtu);
  11460. /* Reset PHY, otherwise the read DMA engine will be in a mode that
  11461. * breaks all requests to 256 bytes.
  11462. */
  11463. if (tg3_asic_rev(tp) == ASIC_REV_57766)
  11464. reset_phy = true;
  11465. err = tg3_restart_hw(tp, reset_phy);
  11466. if (!err)
  11467. tg3_netif_start(tp);
  11468. tg3_full_unlock(tp);
  11469. if (!err)
  11470. tg3_phy_start(tp);
  11471. return err;
  11472. }
  11473. static const struct net_device_ops tg3_netdev_ops = {
  11474. .ndo_open = tg3_open,
  11475. .ndo_stop = tg3_close,
  11476. .ndo_start_xmit = tg3_start_xmit,
  11477. .ndo_get_stats64 = tg3_get_stats64,
  11478. .ndo_validate_addr = eth_validate_addr,
  11479. .ndo_set_rx_mode = tg3_set_rx_mode,
  11480. .ndo_set_mac_address = tg3_set_mac_addr,
  11481. .ndo_do_ioctl = tg3_ioctl,
  11482. .ndo_tx_timeout = tg3_tx_timeout,
  11483. .ndo_change_mtu = tg3_change_mtu,
  11484. .ndo_fix_features = tg3_fix_features,
  11485. .ndo_set_features = tg3_set_features,
  11486. #ifdef CONFIG_NET_POLL_CONTROLLER
  11487. .ndo_poll_controller = tg3_poll_controller,
  11488. #endif
  11489. };
  11490. static void tg3_get_eeprom_size(struct tg3 *tp)
  11491. {
  11492. u32 cursize, val, magic;
  11493. tp->nvram_size = EEPROM_CHIP_SIZE;
  11494. if (tg3_nvram_read(tp, 0, &magic) != 0)
  11495. return;
  11496. if ((magic != TG3_EEPROM_MAGIC) &&
  11497. ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
  11498. ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
  11499. return;
  11500. /*
  11501. * Size the chip by reading offsets at increasing powers of two.
  11502. * When we encounter our validation signature, we know the addressing
  11503. * has wrapped around, and thus have our chip size.
  11504. */
  11505. cursize = 0x10;
  11506. while (cursize < tp->nvram_size) {
  11507. if (tg3_nvram_read(tp, cursize, &val) != 0)
  11508. return;
  11509. if (val == magic)
  11510. break;
  11511. cursize <<= 1;
  11512. }
  11513. tp->nvram_size = cursize;
  11514. }
  11515. static void tg3_get_nvram_size(struct tg3 *tp)
  11516. {
  11517. u32 val;
  11518. if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &val) != 0)
  11519. return;
  11520. /* Selfboot format */
  11521. if (val != TG3_EEPROM_MAGIC) {
  11522. tg3_get_eeprom_size(tp);
  11523. return;
  11524. }
  11525. if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
  11526. if (val != 0) {
  11527. /* This is confusing. We want to operate on the
  11528. * 16-bit value at offset 0xf2. The tg3_nvram_read()
  11529. * call will read from NVRAM and byteswap the data
  11530. * according to the byteswapping settings for all
  11531. * other register accesses. This ensures the data we
  11532. * want will always reside in the lower 16-bits.
  11533. * However, the data in NVRAM is in LE format, which
  11534. * means the data from the NVRAM read will always be
  11535. * opposite the endianness of the CPU. The 16-bit
  11536. * byteswap then brings the data to CPU endianness.
  11537. */
  11538. tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
  11539. return;
  11540. }
  11541. }
  11542. tp->nvram_size = TG3_NVRAM_SIZE_512KB;
  11543. }
  11544. static void tg3_get_nvram_info(struct tg3 *tp)
  11545. {
  11546. u32 nvcfg1;
  11547. nvcfg1 = tr32(NVRAM_CFG1);
  11548. if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
  11549. tg3_flag_set(tp, FLASH);
  11550. } else {
  11551. nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
  11552. tw32(NVRAM_CFG1, nvcfg1);
  11553. }
  11554. if (tg3_asic_rev(tp) == ASIC_REV_5750 ||
  11555. tg3_flag(tp, 5780_CLASS)) {
  11556. switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
  11557. case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
  11558. tp->nvram_jedecnum = JEDEC_ATMEL;
  11559. tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
  11560. tg3_flag_set(tp, NVRAM_BUFFERED);
  11561. break;
  11562. case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
  11563. tp->nvram_jedecnum = JEDEC_ATMEL;
  11564. tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
  11565. break;
  11566. case FLASH_VENDOR_ATMEL_EEPROM:
  11567. tp->nvram_jedecnum = JEDEC_ATMEL;
  11568. tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
  11569. tg3_flag_set(tp, NVRAM_BUFFERED);
  11570. break;
  11571. case FLASH_VENDOR_ST:
  11572. tp->nvram_jedecnum = JEDEC_ST;
  11573. tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
  11574. tg3_flag_set(tp, NVRAM_BUFFERED);
  11575. break;
  11576. case FLASH_VENDOR_SAIFUN:
  11577. tp->nvram_jedecnum = JEDEC_SAIFUN;
  11578. tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
  11579. break;
  11580. case FLASH_VENDOR_SST_SMALL:
  11581. case FLASH_VENDOR_SST_LARGE:
  11582. tp->nvram_jedecnum = JEDEC_SST;
  11583. tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
  11584. break;
  11585. }
  11586. } else {
  11587. tp->nvram_jedecnum = JEDEC_ATMEL;
  11588. tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
  11589. tg3_flag_set(tp, NVRAM_BUFFERED);
  11590. }
  11591. }
  11592. static void tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
  11593. {
  11594. switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
  11595. case FLASH_5752PAGE_SIZE_256:
  11596. tp->nvram_pagesize = 256;
  11597. break;
  11598. case FLASH_5752PAGE_SIZE_512:
  11599. tp->nvram_pagesize = 512;
  11600. break;
  11601. case FLASH_5752PAGE_SIZE_1K:
  11602. tp->nvram_pagesize = 1024;
  11603. break;
  11604. case FLASH_5752PAGE_SIZE_2K:
  11605. tp->nvram_pagesize = 2048;
  11606. break;
  11607. case FLASH_5752PAGE_SIZE_4K:
  11608. tp->nvram_pagesize = 4096;
  11609. break;
  11610. case FLASH_5752PAGE_SIZE_264:
  11611. tp->nvram_pagesize = 264;
  11612. break;
  11613. case FLASH_5752PAGE_SIZE_528:
  11614. tp->nvram_pagesize = 528;
  11615. break;
  11616. }
  11617. }
  11618. static void tg3_get_5752_nvram_info(struct tg3 *tp)
  11619. {
  11620. u32 nvcfg1;
  11621. nvcfg1 = tr32(NVRAM_CFG1);
  11622. /* NVRAM protection for TPM */
  11623. if (nvcfg1 & (1 << 27))
  11624. tg3_flag_set(tp, PROTECTED_NVRAM);
  11625. switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
  11626. case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
  11627. case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
  11628. tp->nvram_jedecnum = JEDEC_ATMEL;
  11629. tg3_flag_set(tp, NVRAM_BUFFERED);
  11630. break;
  11631. case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
  11632. tp->nvram_jedecnum = JEDEC_ATMEL;
  11633. tg3_flag_set(tp, NVRAM_BUFFERED);
  11634. tg3_flag_set(tp, FLASH);
  11635. break;
  11636. case FLASH_5752VENDOR_ST_M45PE10:
  11637. case FLASH_5752VENDOR_ST_M45PE20:
  11638. case FLASH_5752VENDOR_ST_M45PE40:
  11639. tp->nvram_jedecnum = JEDEC_ST;
  11640. tg3_flag_set(tp, NVRAM_BUFFERED);
  11641. tg3_flag_set(tp, FLASH);
  11642. break;
  11643. }
  11644. if (tg3_flag(tp, FLASH)) {
  11645. tg3_nvram_get_pagesize(tp, nvcfg1);
  11646. } else {
  11647. /* For eeprom, set pagesize to maximum eeprom size */
  11648. tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
  11649. nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
  11650. tw32(NVRAM_CFG1, nvcfg1);
  11651. }
  11652. }
  11653. static void tg3_get_5755_nvram_info(struct tg3 *tp)
  11654. {
  11655. u32 nvcfg1, protect = 0;
  11656. nvcfg1 = tr32(NVRAM_CFG1);
  11657. /* NVRAM protection for TPM */
  11658. if (nvcfg1 & (1 << 27)) {
  11659. tg3_flag_set(tp, PROTECTED_NVRAM);
  11660. protect = 1;
  11661. }
  11662. nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
  11663. switch (nvcfg1) {
  11664. case FLASH_5755VENDOR_ATMEL_FLASH_1:
  11665. case FLASH_5755VENDOR_ATMEL_FLASH_2:
  11666. case FLASH_5755VENDOR_ATMEL_FLASH_3:
  11667. case FLASH_5755VENDOR_ATMEL_FLASH_5:
  11668. tp->nvram_jedecnum = JEDEC_ATMEL;
  11669. tg3_flag_set(tp, NVRAM_BUFFERED);
  11670. tg3_flag_set(tp, FLASH);
  11671. tp->nvram_pagesize = 264;
  11672. if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
  11673. nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
  11674. tp->nvram_size = (protect ? 0x3e200 :
  11675. TG3_NVRAM_SIZE_512KB);
  11676. else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
  11677. tp->nvram_size = (protect ? 0x1f200 :
  11678. TG3_NVRAM_SIZE_256KB);
  11679. else
  11680. tp->nvram_size = (protect ? 0x1f200 :
  11681. TG3_NVRAM_SIZE_128KB);
  11682. break;
  11683. case FLASH_5752VENDOR_ST_M45PE10:
  11684. case FLASH_5752VENDOR_ST_M45PE20:
  11685. case FLASH_5752VENDOR_ST_M45PE40:
  11686. tp->nvram_jedecnum = JEDEC_ST;
  11687. tg3_flag_set(tp, NVRAM_BUFFERED);
  11688. tg3_flag_set(tp, FLASH);
  11689. tp->nvram_pagesize = 256;
  11690. if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
  11691. tp->nvram_size = (protect ?
  11692. TG3_NVRAM_SIZE_64KB :
  11693. TG3_NVRAM_SIZE_128KB);
  11694. else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
  11695. tp->nvram_size = (protect ?
  11696. TG3_NVRAM_SIZE_64KB :
  11697. TG3_NVRAM_SIZE_256KB);
  11698. else
  11699. tp->nvram_size = (protect ?
  11700. TG3_NVRAM_SIZE_128KB :
  11701. TG3_NVRAM_SIZE_512KB);
  11702. break;
  11703. }
  11704. }
  11705. static void tg3_get_5787_nvram_info(struct tg3 *tp)
  11706. {
  11707. u32 nvcfg1;
  11708. nvcfg1 = tr32(NVRAM_CFG1);
  11709. switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
  11710. case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
  11711. case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
  11712. case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
  11713. case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
  11714. tp->nvram_jedecnum = JEDEC_ATMEL;
  11715. tg3_flag_set(tp, NVRAM_BUFFERED);
  11716. tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
  11717. nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
  11718. tw32(NVRAM_CFG1, nvcfg1);
  11719. break;
  11720. case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
  11721. case FLASH_5755VENDOR_ATMEL_FLASH_1:
  11722. case FLASH_5755VENDOR_ATMEL_FLASH_2:
  11723. case FLASH_5755VENDOR_ATMEL_FLASH_3:
  11724. tp->nvram_jedecnum = JEDEC_ATMEL;
  11725. tg3_flag_set(tp, NVRAM_BUFFERED);
  11726. tg3_flag_set(tp, FLASH);
  11727. tp->nvram_pagesize = 264;
  11728. break;
  11729. case FLASH_5752VENDOR_ST_M45PE10:
  11730. case FLASH_5752VENDOR_ST_M45PE20:
  11731. case FLASH_5752VENDOR_ST_M45PE40:
  11732. tp->nvram_jedecnum = JEDEC_ST;
  11733. tg3_flag_set(tp, NVRAM_BUFFERED);
  11734. tg3_flag_set(tp, FLASH);
  11735. tp->nvram_pagesize = 256;
  11736. break;
  11737. }
  11738. }
  11739. static void tg3_get_5761_nvram_info(struct tg3 *tp)
  11740. {
  11741. u32 nvcfg1, protect = 0;
  11742. nvcfg1 = tr32(NVRAM_CFG1);
  11743. /* NVRAM protection for TPM */
  11744. if (nvcfg1 & (1 << 27)) {
  11745. tg3_flag_set(tp, PROTECTED_NVRAM);
  11746. protect = 1;
  11747. }
  11748. nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
  11749. switch (nvcfg1) {
  11750. case FLASH_5761VENDOR_ATMEL_ADB021D:
  11751. case FLASH_5761VENDOR_ATMEL_ADB041D:
  11752. case FLASH_5761VENDOR_ATMEL_ADB081D:
  11753. case FLASH_5761VENDOR_ATMEL_ADB161D:
  11754. case FLASH_5761VENDOR_ATMEL_MDB021D:
  11755. case FLASH_5761VENDOR_ATMEL_MDB041D:
  11756. case FLASH_5761VENDOR_ATMEL_MDB081D:
  11757. case FLASH_5761VENDOR_ATMEL_MDB161D:
  11758. tp->nvram_jedecnum = JEDEC_ATMEL;
  11759. tg3_flag_set(tp, NVRAM_BUFFERED);
  11760. tg3_flag_set(tp, FLASH);
  11761. tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
  11762. tp->nvram_pagesize = 256;
  11763. break;
  11764. case FLASH_5761VENDOR_ST_A_M45PE20:
  11765. case FLASH_5761VENDOR_ST_A_M45PE40:
  11766. case FLASH_5761VENDOR_ST_A_M45PE80:
  11767. case FLASH_5761VENDOR_ST_A_M45PE16:
  11768. case FLASH_5761VENDOR_ST_M_M45PE20:
  11769. case FLASH_5761VENDOR_ST_M_M45PE40:
  11770. case FLASH_5761VENDOR_ST_M_M45PE80:
  11771. case FLASH_5761VENDOR_ST_M_M45PE16:
  11772. tp->nvram_jedecnum = JEDEC_ST;
  11773. tg3_flag_set(tp, NVRAM_BUFFERED);
  11774. tg3_flag_set(tp, FLASH);
  11775. tp->nvram_pagesize = 256;
  11776. break;
  11777. }
  11778. if (protect) {
  11779. tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
  11780. } else {
  11781. switch (nvcfg1) {
  11782. case FLASH_5761VENDOR_ATMEL_ADB161D:
  11783. case FLASH_5761VENDOR_ATMEL_MDB161D:
  11784. case FLASH_5761VENDOR_ST_A_M45PE16:
  11785. case FLASH_5761VENDOR_ST_M_M45PE16:
  11786. tp->nvram_size = TG3_NVRAM_SIZE_2MB;
  11787. break;
  11788. case FLASH_5761VENDOR_ATMEL_ADB081D:
  11789. case FLASH_5761VENDOR_ATMEL_MDB081D:
  11790. case FLASH_5761VENDOR_ST_A_M45PE80:
  11791. case FLASH_5761VENDOR_ST_M_M45PE80:
  11792. tp->nvram_size = TG3_NVRAM_SIZE_1MB;
  11793. break;
  11794. case FLASH_5761VENDOR_ATMEL_ADB041D:
  11795. case FLASH_5761VENDOR_ATMEL_MDB041D:
  11796. case FLASH_5761VENDOR_ST_A_M45PE40:
  11797. case FLASH_5761VENDOR_ST_M_M45PE40:
  11798. tp->nvram_size = TG3_NVRAM_SIZE_512KB;
  11799. break;
  11800. case FLASH_5761VENDOR_ATMEL_ADB021D:
  11801. case FLASH_5761VENDOR_ATMEL_MDB021D:
  11802. case FLASH_5761VENDOR_ST_A_M45PE20:
  11803. case FLASH_5761VENDOR_ST_M_M45PE20:
  11804. tp->nvram_size = TG3_NVRAM_SIZE_256KB;
  11805. break;
  11806. }
  11807. }
  11808. }
  11809. static void tg3_get_5906_nvram_info(struct tg3 *tp)
  11810. {
  11811. tp->nvram_jedecnum = JEDEC_ATMEL;
  11812. tg3_flag_set(tp, NVRAM_BUFFERED);
  11813. tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
  11814. }
  11815. static void tg3_get_57780_nvram_info(struct tg3 *tp)
  11816. {
  11817. u32 nvcfg1;
  11818. nvcfg1 = tr32(NVRAM_CFG1);
  11819. switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
  11820. case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
  11821. case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
  11822. tp->nvram_jedecnum = JEDEC_ATMEL;
  11823. tg3_flag_set(tp, NVRAM_BUFFERED);
  11824. tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
  11825. nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
  11826. tw32(NVRAM_CFG1, nvcfg1);
  11827. return;
  11828. case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
  11829. case FLASH_57780VENDOR_ATMEL_AT45DB011D:
  11830. case FLASH_57780VENDOR_ATMEL_AT45DB011B:
  11831. case FLASH_57780VENDOR_ATMEL_AT45DB021D:
  11832. case FLASH_57780VENDOR_ATMEL_AT45DB021B:
  11833. case FLASH_57780VENDOR_ATMEL_AT45DB041D:
  11834. case FLASH_57780VENDOR_ATMEL_AT45DB041B:
  11835. tp->nvram_jedecnum = JEDEC_ATMEL;
  11836. tg3_flag_set(tp, NVRAM_BUFFERED);
  11837. tg3_flag_set(tp, FLASH);
  11838. switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
  11839. case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
  11840. case FLASH_57780VENDOR_ATMEL_AT45DB011D:
  11841. case FLASH_57780VENDOR_ATMEL_AT45DB011B:
  11842. tp->nvram_size = TG3_NVRAM_SIZE_128KB;
  11843. break;
  11844. case FLASH_57780VENDOR_ATMEL_AT45DB021D:
  11845. case FLASH_57780VENDOR_ATMEL_AT45DB021B:
  11846. tp->nvram_size = TG3_NVRAM_SIZE_256KB;
  11847. break;
  11848. case FLASH_57780VENDOR_ATMEL_AT45DB041D:
  11849. case FLASH_57780VENDOR_ATMEL_AT45DB041B:
  11850. tp->nvram_size = TG3_NVRAM_SIZE_512KB;
  11851. break;
  11852. }
  11853. break;
  11854. case FLASH_5752VENDOR_ST_M45PE10:
  11855. case FLASH_5752VENDOR_ST_M45PE20:
  11856. case FLASH_5752VENDOR_ST_M45PE40:
  11857. tp->nvram_jedecnum = JEDEC_ST;
  11858. tg3_flag_set(tp, NVRAM_BUFFERED);
  11859. tg3_flag_set(tp, FLASH);
  11860. switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
  11861. case FLASH_5752VENDOR_ST_M45PE10:
  11862. tp->nvram_size = TG3_NVRAM_SIZE_128KB;
  11863. break;
  11864. case FLASH_5752VENDOR_ST_M45PE20:
  11865. tp->nvram_size = TG3_NVRAM_SIZE_256KB;
  11866. break;
  11867. case FLASH_5752VENDOR_ST_M45PE40:
  11868. tp->nvram_size = TG3_NVRAM_SIZE_512KB;
  11869. break;
  11870. }
  11871. break;
  11872. default:
  11873. tg3_flag_set(tp, NO_NVRAM);
  11874. return;
  11875. }
  11876. tg3_nvram_get_pagesize(tp, nvcfg1);
  11877. if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
  11878. tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
  11879. }
  11880. static void tg3_get_5717_nvram_info(struct tg3 *tp)
  11881. {
  11882. u32 nvcfg1;
  11883. nvcfg1 = tr32(NVRAM_CFG1);
  11884. switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
  11885. case FLASH_5717VENDOR_ATMEL_EEPROM:
  11886. case FLASH_5717VENDOR_MICRO_EEPROM:
  11887. tp->nvram_jedecnum = JEDEC_ATMEL;
  11888. tg3_flag_set(tp, NVRAM_BUFFERED);
  11889. tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
  11890. nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
  11891. tw32(NVRAM_CFG1, nvcfg1);
  11892. return;
  11893. case FLASH_5717VENDOR_ATMEL_MDB011D:
  11894. case FLASH_5717VENDOR_ATMEL_ADB011B:
  11895. case FLASH_5717VENDOR_ATMEL_ADB011D:
  11896. case FLASH_5717VENDOR_ATMEL_MDB021D:
  11897. case FLASH_5717VENDOR_ATMEL_ADB021B:
  11898. case FLASH_5717VENDOR_ATMEL_ADB021D:
  11899. case FLASH_5717VENDOR_ATMEL_45USPT:
  11900. tp->nvram_jedecnum = JEDEC_ATMEL;
  11901. tg3_flag_set(tp, NVRAM_BUFFERED);
  11902. tg3_flag_set(tp, FLASH);
  11903. switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
  11904. case FLASH_5717VENDOR_ATMEL_MDB021D:
  11905. /* Detect size with tg3_nvram_get_size() */
  11906. break;
  11907. case FLASH_5717VENDOR_ATMEL_ADB021B:
  11908. case FLASH_5717VENDOR_ATMEL_ADB021D:
  11909. tp->nvram_size = TG3_NVRAM_SIZE_256KB;
  11910. break;
  11911. default:
  11912. tp->nvram_size = TG3_NVRAM_SIZE_128KB;
  11913. break;
  11914. }
  11915. break;
  11916. case FLASH_5717VENDOR_ST_M_M25PE10:
  11917. case FLASH_5717VENDOR_ST_A_M25PE10:
  11918. case FLASH_5717VENDOR_ST_M_M45PE10:
  11919. case FLASH_5717VENDOR_ST_A_M45PE10:
  11920. case FLASH_5717VENDOR_ST_M_M25PE20:
  11921. case FLASH_5717VENDOR_ST_A_M25PE20:
  11922. case FLASH_5717VENDOR_ST_M_M45PE20:
  11923. case FLASH_5717VENDOR_ST_A_M45PE20:
  11924. case FLASH_5717VENDOR_ST_25USPT:
  11925. case FLASH_5717VENDOR_ST_45USPT:
  11926. tp->nvram_jedecnum = JEDEC_ST;
  11927. tg3_flag_set(tp, NVRAM_BUFFERED);
  11928. tg3_flag_set(tp, FLASH);
  11929. switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
  11930. case FLASH_5717VENDOR_ST_M_M25PE20:
  11931. case FLASH_5717VENDOR_ST_M_M45PE20:
  11932. /* Detect size with tg3_nvram_get_size() */
  11933. break;
  11934. case FLASH_5717VENDOR_ST_A_M25PE20:
  11935. case FLASH_5717VENDOR_ST_A_M45PE20:
  11936. tp->nvram_size = TG3_NVRAM_SIZE_256KB;
  11937. break;
  11938. default:
  11939. tp->nvram_size = TG3_NVRAM_SIZE_128KB;
  11940. break;
  11941. }
  11942. break;
  11943. default:
  11944. tg3_flag_set(tp, NO_NVRAM);
  11945. return;
  11946. }
  11947. tg3_nvram_get_pagesize(tp, nvcfg1);
  11948. if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
  11949. tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
  11950. }
  11951. static void tg3_get_5720_nvram_info(struct tg3 *tp)
  11952. {
  11953. u32 nvcfg1, nvmpinstrp;
  11954. nvcfg1 = tr32(NVRAM_CFG1);
  11955. nvmpinstrp = nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK;
  11956. if (tg3_asic_rev(tp) == ASIC_REV_5762) {
  11957. if (!(nvcfg1 & NVRAM_CFG1_5762VENDOR_MASK)) {
  11958. tg3_flag_set(tp, NO_NVRAM);
  11959. return;
  11960. }
  11961. switch (nvmpinstrp) {
  11962. case FLASH_5762_EEPROM_HD:
  11963. nvmpinstrp = FLASH_5720_EEPROM_HD;
  11964. break;
  11965. case FLASH_5762_EEPROM_LD:
  11966. nvmpinstrp = FLASH_5720_EEPROM_LD;
  11967. break;
  11968. case FLASH_5720VENDOR_M_ST_M45PE20:
  11969. /* This pinstrap supports multiple sizes, so force it
  11970. * to read the actual size from location 0xf0.
  11971. */
  11972. nvmpinstrp = FLASH_5720VENDOR_ST_45USPT;
  11973. break;
  11974. }
  11975. }
  11976. switch (nvmpinstrp) {
  11977. case FLASH_5720_EEPROM_HD:
  11978. case FLASH_5720_EEPROM_LD:
  11979. tp->nvram_jedecnum = JEDEC_ATMEL;
  11980. tg3_flag_set(tp, NVRAM_BUFFERED);
  11981. nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
  11982. tw32(NVRAM_CFG1, nvcfg1);
  11983. if (nvmpinstrp == FLASH_5720_EEPROM_HD)
  11984. tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
  11985. else
  11986. tp->nvram_pagesize = ATMEL_AT24C02_CHIP_SIZE;
  11987. return;
  11988. case FLASH_5720VENDOR_M_ATMEL_DB011D:
  11989. case FLASH_5720VENDOR_A_ATMEL_DB011B:
  11990. case FLASH_5720VENDOR_A_ATMEL_DB011D:
  11991. case FLASH_5720VENDOR_M_ATMEL_DB021D:
  11992. case FLASH_5720VENDOR_A_ATMEL_DB021B:
  11993. case FLASH_5720VENDOR_A_ATMEL_DB021D:
  11994. case FLASH_5720VENDOR_M_ATMEL_DB041D:
  11995. case FLASH_5720VENDOR_A_ATMEL_DB041B:
  11996. case FLASH_5720VENDOR_A_ATMEL_DB041D:
  11997. case FLASH_5720VENDOR_M_ATMEL_DB081D:
  11998. case FLASH_5720VENDOR_A_ATMEL_DB081D:
  11999. case FLASH_5720VENDOR_ATMEL_45USPT:
  12000. tp->nvram_jedecnum = JEDEC_ATMEL;
  12001. tg3_flag_set(tp, NVRAM_BUFFERED);
  12002. tg3_flag_set(tp, FLASH);
  12003. switch (nvmpinstrp) {
  12004. case FLASH_5720VENDOR_M_ATMEL_DB021D:
  12005. case FLASH_5720VENDOR_A_ATMEL_DB021B:
  12006. case FLASH_5720VENDOR_A_ATMEL_DB021D:
  12007. tp->nvram_size = TG3_NVRAM_SIZE_256KB;
  12008. break;
  12009. case FLASH_5720VENDOR_M_ATMEL_DB041D:
  12010. case FLASH_5720VENDOR_A_ATMEL_DB041B:
  12011. case FLASH_5720VENDOR_A_ATMEL_DB041D:
  12012. tp->nvram_size = TG3_NVRAM_SIZE_512KB;
  12013. break;
  12014. case FLASH_5720VENDOR_M_ATMEL_DB081D:
  12015. case FLASH_5720VENDOR_A_ATMEL_DB081D:
  12016. tp->nvram_size = TG3_NVRAM_SIZE_1MB;
  12017. break;
  12018. default:
  12019. if (tg3_asic_rev(tp) != ASIC_REV_5762)
  12020. tp->nvram_size = TG3_NVRAM_SIZE_128KB;
  12021. break;
  12022. }
  12023. break;
  12024. case FLASH_5720VENDOR_M_ST_M25PE10:
  12025. case FLASH_5720VENDOR_M_ST_M45PE10:
  12026. case FLASH_5720VENDOR_A_ST_M25PE10:
  12027. case FLASH_5720VENDOR_A_ST_M45PE10:
  12028. case FLASH_5720VENDOR_M_ST_M25PE20:
  12029. case FLASH_5720VENDOR_M_ST_M45PE20:
  12030. case FLASH_5720VENDOR_A_ST_M25PE20:
  12031. case FLASH_5720VENDOR_A_ST_M45PE20:
  12032. case FLASH_5720VENDOR_M_ST_M25PE40:
  12033. case FLASH_5720VENDOR_M_ST_M45PE40:
  12034. case FLASH_5720VENDOR_A_ST_M25PE40:
  12035. case FLASH_5720VENDOR_A_ST_M45PE40:
  12036. case FLASH_5720VENDOR_M_ST_M25PE80:
  12037. case FLASH_5720VENDOR_M_ST_M45PE80:
  12038. case FLASH_5720VENDOR_A_ST_M25PE80:
  12039. case FLASH_5720VENDOR_A_ST_M45PE80:
  12040. case FLASH_5720VENDOR_ST_25USPT:
  12041. case FLASH_5720VENDOR_ST_45USPT:
  12042. tp->nvram_jedecnum = JEDEC_ST;
  12043. tg3_flag_set(tp, NVRAM_BUFFERED);
  12044. tg3_flag_set(tp, FLASH);
  12045. switch (nvmpinstrp) {
  12046. case FLASH_5720VENDOR_M_ST_M25PE20:
  12047. case FLASH_5720VENDOR_M_ST_M45PE20:
  12048. case FLASH_5720VENDOR_A_ST_M25PE20:
  12049. case FLASH_5720VENDOR_A_ST_M45PE20:
  12050. tp->nvram_size = TG3_NVRAM_SIZE_256KB;
  12051. break;
  12052. case FLASH_5720VENDOR_M_ST_M25PE40:
  12053. case FLASH_5720VENDOR_M_ST_M45PE40:
  12054. case FLASH_5720VENDOR_A_ST_M25PE40:
  12055. case FLASH_5720VENDOR_A_ST_M45PE40:
  12056. tp->nvram_size = TG3_NVRAM_SIZE_512KB;
  12057. break;
  12058. case FLASH_5720VENDOR_M_ST_M25PE80:
  12059. case FLASH_5720VENDOR_M_ST_M45PE80:
  12060. case FLASH_5720VENDOR_A_ST_M25PE80:
  12061. case FLASH_5720VENDOR_A_ST_M45PE80:
  12062. tp->nvram_size = TG3_NVRAM_SIZE_1MB;
  12063. break;
  12064. default:
  12065. if (tg3_asic_rev(tp) != ASIC_REV_5762)
  12066. tp->nvram_size = TG3_NVRAM_SIZE_128KB;
  12067. break;
  12068. }
  12069. break;
  12070. default:
  12071. tg3_flag_set(tp, NO_NVRAM);
  12072. return;
  12073. }
  12074. tg3_nvram_get_pagesize(tp, nvcfg1);
  12075. if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
  12076. tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
  12077. if (tg3_asic_rev(tp) == ASIC_REV_5762) {
  12078. u32 val;
  12079. if (tg3_nvram_read(tp, 0, &val))
  12080. return;
  12081. if (val != TG3_EEPROM_MAGIC &&
  12082. (val & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW)
  12083. tg3_flag_set(tp, NO_NVRAM);
  12084. }
  12085. }
  12086. /* Chips other than 5700/5701 use the NVRAM for fetching info. */
  12087. static void tg3_nvram_init(struct tg3 *tp)
  12088. {
  12089. if (tg3_flag(tp, IS_SSB_CORE)) {
  12090. /* No NVRAM and EEPROM on the SSB Broadcom GigE core. */
  12091. tg3_flag_clear(tp, NVRAM);
  12092. tg3_flag_clear(tp, NVRAM_BUFFERED);
  12093. tg3_flag_set(tp, NO_NVRAM);
  12094. return;
  12095. }
  12096. tw32_f(GRC_EEPROM_ADDR,
  12097. (EEPROM_ADDR_FSM_RESET |
  12098. (EEPROM_DEFAULT_CLOCK_PERIOD <<
  12099. EEPROM_ADDR_CLKPERD_SHIFT)));
  12100. msleep(1);
  12101. /* Enable seeprom accesses. */
  12102. tw32_f(GRC_LOCAL_CTRL,
  12103. tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
  12104. udelay(100);
  12105. if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
  12106. tg3_asic_rev(tp) != ASIC_REV_5701) {
  12107. tg3_flag_set(tp, NVRAM);
  12108. if (tg3_nvram_lock(tp)) {
  12109. netdev_warn(tp->dev,
  12110. "Cannot get nvram lock, %s failed\n",
  12111. __func__);
  12112. return;
  12113. }
  12114. tg3_enable_nvram_access(tp);
  12115. tp->nvram_size = 0;
  12116. if (tg3_asic_rev(tp) == ASIC_REV_5752)
  12117. tg3_get_5752_nvram_info(tp);
  12118. else if (tg3_asic_rev(tp) == ASIC_REV_5755)
  12119. tg3_get_5755_nvram_info(tp);
  12120. else if (tg3_asic_rev(tp) == ASIC_REV_5787 ||
  12121. tg3_asic_rev(tp) == ASIC_REV_5784 ||
  12122. tg3_asic_rev(tp) == ASIC_REV_5785)
  12123. tg3_get_5787_nvram_info(tp);
  12124. else if (tg3_asic_rev(tp) == ASIC_REV_5761)
  12125. tg3_get_5761_nvram_info(tp);
  12126. else if (tg3_asic_rev(tp) == ASIC_REV_5906)
  12127. tg3_get_5906_nvram_info(tp);
  12128. else if (tg3_asic_rev(tp) == ASIC_REV_57780 ||
  12129. tg3_flag(tp, 57765_CLASS))
  12130. tg3_get_57780_nvram_info(tp);
  12131. else if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
  12132. tg3_asic_rev(tp) == ASIC_REV_5719)
  12133. tg3_get_5717_nvram_info(tp);
  12134. else if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
  12135. tg3_asic_rev(tp) == ASIC_REV_5762)
  12136. tg3_get_5720_nvram_info(tp);
  12137. else
  12138. tg3_get_nvram_info(tp);
  12139. if (tp->nvram_size == 0)
  12140. tg3_get_nvram_size(tp);
  12141. tg3_disable_nvram_access(tp);
  12142. tg3_nvram_unlock(tp);
  12143. } else {
  12144. tg3_flag_clear(tp, NVRAM);
  12145. tg3_flag_clear(tp, NVRAM_BUFFERED);
  12146. tg3_get_eeprom_size(tp);
  12147. }
  12148. }
  12149. struct subsys_tbl_ent {
  12150. u16 subsys_vendor, subsys_devid;
  12151. u32 phy_id;
  12152. };
  12153. static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
  12154. /* Broadcom boards. */
  12155. { TG3PCI_SUBVENDOR_ID_BROADCOM,
  12156. TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 },
  12157. { TG3PCI_SUBVENDOR_ID_BROADCOM,
  12158. TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 },
  12159. { TG3PCI_SUBVENDOR_ID_BROADCOM,
  12160. TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 },
  12161. { TG3PCI_SUBVENDOR_ID_BROADCOM,
  12162. TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 },
  12163. { TG3PCI_SUBVENDOR_ID_BROADCOM,
  12164. TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 },
  12165. { TG3PCI_SUBVENDOR_ID_BROADCOM,
  12166. TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 },
  12167. { TG3PCI_SUBVENDOR_ID_BROADCOM,
  12168. TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 },
  12169. { TG3PCI_SUBVENDOR_ID_BROADCOM,
  12170. TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 },
  12171. { TG3PCI_SUBVENDOR_ID_BROADCOM,
  12172. TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 },
  12173. { TG3PCI_SUBVENDOR_ID_BROADCOM,
  12174. TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 },
  12175. { TG3PCI_SUBVENDOR_ID_BROADCOM,
  12176. TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 },
  12177. /* 3com boards. */
  12178. { TG3PCI_SUBVENDOR_ID_3COM,
  12179. TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 },
  12180. { TG3PCI_SUBVENDOR_ID_3COM,
  12181. TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 },
  12182. { TG3PCI_SUBVENDOR_ID_3COM,
  12183. TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 },
  12184. { TG3PCI_SUBVENDOR_ID_3COM,
  12185. TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 },
  12186. { TG3PCI_SUBVENDOR_ID_3COM,
  12187. TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 },
  12188. /* DELL boards. */
  12189. { TG3PCI_SUBVENDOR_ID_DELL,
  12190. TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 },
  12191. { TG3PCI_SUBVENDOR_ID_DELL,
  12192. TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 },
  12193. { TG3PCI_SUBVENDOR_ID_DELL,
  12194. TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 },
  12195. { TG3PCI_SUBVENDOR_ID_DELL,
  12196. TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 },
  12197. /* Compaq boards. */
  12198. { TG3PCI_SUBVENDOR_ID_COMPAQ,
  12199. TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 },
  12200. { TG3PCI_SUBVENDOR_ID_COMPAQ,
  12201. TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 },
  12202. { TG3PCI_SUBVENDOR_ID_COMPAQ,
  12203. TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 },
  12204. { TG3PCI_SUBVENDOR_ID_COMPAQ,
  12205. TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 },
  12206. { TG3PCI_SUBVENDOR_ID_COMPAQ,
  12207. TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 },
  12208. /* IBM boards. */
  12209. { TG3PCI_SUBVENDOR_ID_IBM,
  12210. TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 }
  12211. };
  12212. static struct subsys_tbl_ent *tg3_lookup_by_subsys(struct tg3 *tp)
  12213. {
  12214. int i;
  12215. for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
  12216. if ((subsys_id_to_phy_id[i].subsys_vendor ==
  12217. tp->pdev->subsystem_vendor) &&
  12218. (subsys_id_to_phy_id[i].subsys_devid ==
  12219. tp->pdev->subsystem_device))
  12220. return &subsys_id_to_phy_id[i];
  12221. }
  12222. return NULL;
  12223. }
  12224. static void tg3_get_eeprom_hw_cfg(struct tg3 *tp)
  12225. {
  12226. u32 val;
  12227. tp->phy_id = TG3_PHY_ID_INVALID;
  12228. tp->led_ctrl = LED_CTRL_MODE_PHY_1;
  12229. /* Assume an onboard device and WOL capable by default. */
  12230. tg3_flag_set(tp, EEPROM_WRITE_PROT);
  12231. tg3_flag_set(tp, WOL_CAP);
  12232. if (tg3_asic_rev(tp) == ASIC_REV_5906) {
  12233. if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
  12234. tg3_flag_clear(tp, EEPROM_WRITE_PROT);
  12235. tg3_flag_set(tp, IS_NIC);
  12236. }
  12237. val = tr32(VCPU_CFGSHDW);
  12238. if (val & VCPU_CFGSHDW_ASPM_DBNC)
  12239. tg3_flag_set(tp, ASPM_WORKAROUND);
  12240. if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
  12241. (val & VCPU_CFGSHDW_WOL_MAGPKT)) {
  12242. tg3_flag_set(tp, WOL_ENABLE);
  12243. device_set_wakeup_enable(&tp->pdev->dev, true);
  12244. }
  12245. goto done;
  12246. }
  12247. tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
  12248. if (val == NIC_SRAM_DATA_SIG_MAGIC) {
  12249. u32 nic_cfg, led_cfg;
  12250. u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
  12251. int eeprom_phy_serdes = 0;
  12252. tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
  12253. tp->nic_sram_data_cfg = nic_cfg;
  12254. tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
  12255. ver >>= NIC_SRAM_DATA_VER_SHIFT;
  12256. if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
  12257. tg3_asic_rev(tp) != ASIC_REV_5701 &&
  12258. tg3_asic_rev(tp) != ASIC_REV_5703 &&
  12259. (ver > 0) && (ver < 0x100))
  12260. tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
  12261. if (tg3_asic_rev(tp) == ASIC_REV_5785)
  12262. tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
  12263. if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
  12264. NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
  12265. eeprom_phy_serdes = 1;
  12266. tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
  12267. if (nic_phy_id != 0) {
  12268. u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
  12269. u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
  12270. eeprom_phy_id = (id1 >> 16) << 10;
  12271. eeprom_phy_id |= (id2 & 0xfc00) << 16;
  12272. eeprom_phy_id |= (id2 & 0x03ff) << 0;
  12273. } else
  12274. eeprom_phy_id = 0;
  12275. tp->phy_id = eeprom_phy_id;
  12276. if (eeprom_phy_serdes) {
  12277. if (!tg3_flag(tp, 5705_PLUS))
  12278. tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
  12279. else
  12280. tp->phy_flags |= TG3_PHYFLG_MII_SERDES;
  12281. }
  12282. if (tg3_flag(tp, 5750_PLUS))
  12283. led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
  12284. SHASTA_EXT_LED_MODE_MASK);
  12285. else
  12286. led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
  12287. switch (led_cfg) {
  12288. default:
  12289. case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
  12290. tp->led_ctrl = LED_CTRL_MODE_PHY_1;
  12291. break;
  12292. case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
  12293. tp->led_ctrl = LED_CTRL_MODE_PHY_2;
  12294. break;
  12295. case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
  12296. tp->led_ctrl = LED_CTRL_MODE_MAC;
  12297. /* Default to PHY_1_MODE if 0 (MAC_MODE) is
  12298. * read on some older 5700/5701 bootcode.
  12299. */
  12300. if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
  12301. tg3_asic_rev(tp) == ASIC_REV_5701)
  12302. tp->led_ctrl = LED_CTRL_MODE_PHY_1;
  12303. break;
  12304. case SHASTA_EXT_LED_SHARED:
  12305. tp->led_ctrl = LED_CTRL_MODE_SHARED;
  12306. if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0 &&
  12307. tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A1)
  12308. tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
  12309. LED_CTRL_MODE_PHY_2);
  12310. break;
  12311. case SHASTA_EXT_LED_MAC:
  12312. tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
  12313. break;
  12314. case SHASTA_EXT_LED_COMBO:
  12315. tp->led_ctrl = LED_CTRL_MODE_COMBO;
  12316. if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0)
  12317. tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
  12318. LED_CTRL_MODE_PHY_2);
  12319. break;
  12320. }
  12321. if ((tg3_asic_rev(tp) == ASIC_REV_5700 ||
  12322. tg3_asic_rev(tp) == ASIC_REV_5701) &&
  12323. tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
  12324. tp->led_ctrl = LED_CTRL_MODE_PHY_2;
  12325. if (tg3_chip_rev(tp) == CHIPREV_5784_AX)
  12326. tp->led_ctrl = LED_CTRL_MODE_PHY_1;
  12327. if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
  12328. tg3_flag_set(tp, EEPROM_WRITE_PROT);
  12329. if ((tp->pdev->subsystem_vendor ==
  12330. PCI_VENDOR_ID_ARIMA) &&
  12331. (tp->pdev->subsystem_device == 0x205a ||
  12332. tp->pdev->subsystem_device == 0x2063))
  12333. tg3_flag_clear(tp, EEPROM_WRITE_PROT);
  12334. } else {
  12335. tg3_flag_clear(tp, EEPROM_WRITE_PROT);
  12336. tg3_flag_set(tp, IS_NIC);
  12337. }
  12338. if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
  12339. tg3_flag_set(tp, ENABLE_ASF);
  12340. if (tg3_flag(tp, 5750_PLUS))
  12341. tg3_flag_set(tp, ASF_NEW_HANDSHAKE);
  12342. }
  12343. if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
  12344. tg3_flag(tp, 5750_PLUS))
  12345. tg3_flag_set(tp, ENABLE_APE);
  12346. if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES &&
  12347. !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
  12348. tg3_flag_clear(tp, WOL_CAP);
  12349. if (tg3_flag(tp, WOL_CAP) &&
  12350. (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE)) {
  12351. tg3_flag_set(tp, WOL_ENABLE);
  12352. device_set_wakeup_enable(&tp->pdev->dev, true);
  12353. }
  12354. if (cfg2 & (1 << 17))
  12355. tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING;
  12356. /* serdes signal pre-emphasis in register 0x590 set by */
  12357. /* bootcode if bit 18 is set */
  12358. if (cfg2 & (1 << 18))
  12359. tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS;
  12360. if ((tg3_flag(tp, 57765_PLUS) ||
  12361. (tg3_asic_rev(tp) == ASIC_REV_5784 &&
  12362. tg3_chip_rev(tp) != CHIPREV_5784_AX)) &&
  12363. (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
  12364. tp->phy_flags |= TG3_PHYFLG_ENABLE_APD;
  12365. if (tg3_flag(tp, PCI_EXPRESS)) {
  12366. u32 cfg3;
  12367. tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
  12368. if (tg3_asic_rev(tp) != ASIC_REV_5785 &&
  12369. !tg3_flag(tp, 57765_PLUS) &&
  12370. (cfg3 & NIC_SRAM_ASPM_DEBOUNCE))
  12371. tg3_flag_set(tp, ASPM_WORKAROUND);
  12372. if (cfg3 & NIC_SRAM_LNK_FLAP_AVOID)
  12373. tp->phy_flags |= TG3_PHYFLG_KEEP_LINK_ON_PWRDN;
  12374. if (cfg3 & NIC_SRAM_1G_ON_VAUX_OK)
  12375. tp->phy_flags |= TG3_PHYFLG_1G_ON_VAUX_OK;
  12376. }
  12377. if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE)
  12378. tg3_flag_set(tp, RGMII_INBAND_DISABLE);
  12379. if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
  12380. tg3_flag_set(tp, RGMII_EXT_IBND_RX_EN);
  12381. if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
  12382. tg3_flag_set(tp, RGMII_EXT_IBND_TX_EN);
  12383. }
  12384. done:
  12385. if (tg3_flag(tp, WOL_CAP))
  12386. device_set_wakeup_enable(&tp->pdev->dev,
  12387. tg3_flag(tp, WOL_ENABLE));
  12388. else
  12389. device_set_wakeup_capable(&tp->pdev->dev, false);
  12390. }
  12391. static int tg3_ape_otp_read(struct tg3 *tp, u32 offset, u32 *val)
  12392. {
  12393. int i, err;
  12394. u32 val2, off = offset * 8;
  12395. err = tg3_nvram_lock(tp);
  12396. if (err)
  12397. return err;
  12398. tg3_ape_write32(tp, TG3_APE_OTP_ADDR, off | APE_OTP_ADDR_CPU_ENABLE);
  12399. tg3_ape_write32(tp, TG3_APE_OTP_CTRL, APE_OTP_CTRL_PROG_EN |
  12400. APE_OTP_CTRL_CMD_RD | APE_OTP_CTRL_START);
  12401. tg3_ape_read32(tp, TG3_APE_OTP_CTRL);
  12402. udelay(10);
  12403. for (i = 0; i < 100; i++) {
  12404. val2 = tg3_ape_read32(tp, TG3_APE_OTP_STATUS);
  12405. if (val2 & APE_OTP_STATUS_CMD_DONE) {
  12406. *val = tg3_ape_read32(tp, TG3_APE_OTP_RD_DATA);
  12407. break;
  12408. }
  12409. udelay(10);
  12410. }
  12411. tg3_ape_write32(tp, TG3_APE_OTP_CTRL, 0);
  12412. tg3_nvram_unlock(tp);
  12413. if (val2 & APE_OTP_STATUS_CMD_DONE)
  12414. return 0;
  12415. return -EBUSY;
  12416. }
  12417. static int tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
  12418. {
  12419. int i;
  12420. u32 val;
  12421. tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
  12422. tw32(OTP_CTRL, cmd);
  12423. /* Wait for up to 1 ms for command to execute. */
  12424. for (i = 0; i < 100; i++) {
  12425. val = tr32(OTP_STATUS);
  12426. if (val & OTP_STATUS_CMD_DONE)
  12427. break;
  12428. udelay(10);
  12429. }
  12430. return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
  12431. }
  12432. /* Read the gphy configuration from the OTP region of the chip. The gphy
  12433. * configuration is a 32-bit value that straddles the alignment boundary.
  12434. * We do two 32-bit reads and then shift and merge the results.
  12435. */
  12436. static u32 tg3_read_otp_phycfg(struct tg3 *tp)
  12437. {
  12438. u32 bhalf_otp, thalf_otp;
  12439. tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
  12440. if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
  12441. return 0;
  12442. tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
  12443. if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
  12444. return 0;
  12445. thalf_otp = tr32(OTP_READ_DATA);
  12446. tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
  12447. if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
  12448. return 0;
  12449. bhalf_otp = tr32(OTP_READ_DATA);
  12450. return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
  12451. }
  12452. static void tg3_phy_init_link_config(struct tg3 *tp)
  12453. {
  12454. u32 adv = ADVERTISED_Autoneg;
  12455. if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
  12456. adv |= ADVERTISED_1000baseT_Half |
  12457. ADVERTISED_1000baseT_Full;
  12458. if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
  12459. adv |= ADVERTISED_100baseT_Half |
  12460. ADVERTISED_100baseT_Full |
  12461. ADVERTISED_10baseT_Half |
  12462. ADVERTISED_10baseT_Full |
  12463. ADVERTISED_TP;
  12464. else
  12465. adv |= ADVERTISED_FIBRE;
  12466. tp->link_config.advertising = adv;
  12467. tp->link_config.speed = SPEED_UNKNOWN;
  12468. tp->link_config.duplex = DUPLEX_UNKNOWN;
  12469. tp->link_config.autoneg = AUTONEG_ENABLE;
  12470. tp->link_config.active_speed = SPEED_UNKNOWN;
  12471. tp->link_config.active_duplex = DUPLEX_UNKNOWN;
  12472. tp->old_link = -1;
  12473. }
  12474. static int tg3_phy_probe(struct tg3 *tp)
  12475. {
  12476. u32 hw_phy_id_1, hw_phy_id_2;
  12477. u32 hw_phy_id, hw_phy_id_masked;
  12478. int err;
  12479. /* flow control autonegotiation is default behavior */
  12480. tg3_flag_set(tp, PAUSE_AUTONEG);
  12481. tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
  12482. if (tg3_flag(tp, ENABLE_APE)) {
  12483. switch (tp->pci_fn) {
  12484. case 0:
  12485. tp->phy_ape_lock = TG3_APE_LOCK_PHY0;
  12486. break;
  12487. case 1:
  12488. tp->phy_ape_lock = TG3_APE_LOCK_PHY1;
  12489. break;
  12490. case 2:
  12491. tp->phy_ape_lock = TG3_APE_LOCK_PHY2;
  12492. break;
  12493. case 3:
  12494. tp->phy_ape_lock = TG3_APE_LOCK_PHY3;
  12495. break;
  12496. }
  12497. }
  12498. if (!tg3_flag(tp, ENABLE_ASF) &&
  12499. !(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
  12500. !(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
  12501. tp->phy_flags &= ~(TG3_PHYFLG_1G_ON_VAUX_OK |
  12502. TG3_PHYFLG_KEEP_LINK_ON_PWRDN);
  12503. if (tg3_flag(tp, USE_PHYLIB))
  12504. return tg3_phy_init(tp);
  12505. /* Reading the PHY ID register can conflict with ASF
  12506. * firmware access to the PHY hardware.
  12507. */
  12508. err = 0;
  12509. if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)) {
  12510. hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID;
  12511. } else {
  12512. /* Now read the physical PHY_ID from the chip and verify
  12513. * that it is sane. If it doesn't look good, we fall back
  12514. * to either the hard-coded table based PHY_ID and failing
  12515. * that the value found in the eeprom area.
  12516. */
  12517. err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
  12518. err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
  12519. hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
  12520. hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
  12521. hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
  12522. hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK;
  12523. }
  12524. if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) {
  12525. tp->phy_id = hw_phy_id;
  12526. if (hw_phy_id_masked == TG3_PHY_ID_BCM8002)
  12527. tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
  12528. else
  12529. tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES;
  12530. } else {
  12531. if (tp->phy_id != TG3_PHY_ID_INVALID) {
  12532. /* Do nothing, phy ID already set up in
  12533. * tg3_get_eeprom_hw_cfg().
  12534. */
  12535. } else {
  12536. struct subsys_tbl_ent *p;
  12537. /* No eeprom signature? Try the hardcoded
  12538. * subsys device table.
  12539. */
  12540. p = tg3_lookup_by_subsys(tp);
  12541. if (p) {
  12542. tp->phy_id = p->phy_id;
  12543. } else if (!tg3_flag(tp, IS_SSB_CORE)) {
  12544. /* For now we saw the IDs 0xbc050cd0,
  12545. * 0xbc050f80 and 0xbc050c30 on devices
  12546. * connected to an BCM4785 and there are
  12547. * probably more. Just assume that the phy is
  12548. * supported when it is connected to a SSB core
  12549. * for now.
  12550. */
  12551. return -ENODEV;
  12552. }
  12553. if (!tp->phy_id ||
  12554. tp->phy_id == TG3_PHY_ID_BCM8002)
  12555. tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
  12556. }
  12557. }
  12558. if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
  12559. (tg3_asic_rev(tp) == ASIC_REV_5719 ||
  12560. tg3_asic_rev(tp) == ASIC_REV_5720 ||
  12561. tg3_asic_rev(tp) == ASIC_REV_57766 ||
  12562. tg3_asic_rev(tp) == ASIC_REV_5762 ||
  12563. (tg3_asic_rev(tp) == ASIC_REV_5717 &&
  12564. tg3_chip_rev_id(tp) != CHIPREV_ID_5717_A0) ||
  12565. (tg3_asic_rev(tp) == ASIC_REV_57765 &&
  12566. tg3_chip_rev_id(tp) != CHIPREV_ID_57765_A0))) {
  12567. tp->phy_flags |= TG3_PHYFLG_EEE_CAP;
  12568. tp->eee.supported = SUPPORTED_100baseT_Full |
  12569. SUPPORTED_1000baseT_Full;
  12570. tp->eee.advertised = ADVERTISED_100baseT_Full |
  12571. ADVERTISED_1000baseT_Full;
  12572. tp->eee.eee_enabled = 1;
  12573. tp->eee.tx_lpi_enabled = 1;
  12574. tp->eee.tx_lpi_timer = TG3_CPMU_DBTMR1_LNKIDLE_2047US;
  12575. }
  12576. tg3_phy_init_link_config(tp);
  12577. if (!(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) &&
  12578. !(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
  12579. !tg3_flag(tp, ENABLE_APE) &&
  12580. !tg3_flag(tp, ENABLE_ASF)) {
  12581. u32 bmsr, dummy;
  12582. tg3_readphy(tp, MII_BMSR, &bmsr);
  12583. if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
  12584. (bmsr & BMSR_LSTATUS))
  12585. goto skip_phy_reset;
  12586. err = tg3_phy_reset(tp);
  12587. if (err)
  12588. return err;
  12589. tg3_phy_set_wirespeed(tp);
  12590. if (!tg3_phy_copper_an_config_ok(tp, &dummy)) {
  12591. tg3_phy_autoneg_cfg(tp, tp->link_config.advertising,
  12592. tp->link_config.flowctrl);
  12593. tg3_writephy(tp, MII_BMCR,
  12594. BMCR_ANENABLE | BMCR_ANRESTART);
  12595. }
  12596. }
  12597. skip_phy_reset:
  12598. if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
  12599. err = tg3_init_5401phy_dsp(tp);
  12600. if (err)
  12601. return err;
  12602. err = tg3_init_5401phy_dsp(tp);
  12603. }
  12604. return err;
  12605. }
  12606. static void tg3_read_vpd(struct tg3 *tp)
  12607. {
  12608. u8 *vpd_data;
  12609. unsigned int block_end, rosize, len;
  12610. u32 vpdlen;
  12611. int j, i = 0;
  12612. vpd_data = (u8 *)tg3_vpd_readblock(tp, &vpdlen);
  12613. if (!vpd_data)
  12614. goto out_no_vpd;
  12615. i = pci_vpd_find_tag(vpd_data, 0, vpdlen, PCI_VPD_LRDT_RO_DATA);
  12616. if (i < 0)
  12617. goto out_not_found;
  12618. rosize = pci_vpd_lrdt_size(&vpd_data[i]);
  12619. block_end = i + PCI_VPD_LRDT_TAG_SIZE + rosize;
  12620. i += PCI_VPD_LRDT_TAG_SIZE;
  12621. if (block_end > vpdlen)
  12622. goto out_not_found;
  12623. j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
  12624. PCI_VPD_RO_KEYWORD_MFR_ID);
  12625. if (j > 0) {
  12626. len = pci_vpd_info_field_size(&vpd_data[j]);
  12627. j += PCI_VPD_INFO_FLD_HDR_SIZE;
  12628. if (j + len > block_end || len != 4 ||
  12629. memcmp(&vpd_data[j], "1028", 4))
  12630. goto partno;
  12631. j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
  12632. PCI_VPD_RO_KEYWORD_VENDOR0);
  12633. if (j < 0)
  12634. goto partno;
  12635. len = pci_vpd_info_field_size(&vpd_data[j]);
  12636. j += PCI_VPD_INFO_FLD_HDR_SIZE;
  12637. if (j + len > block_end)
  12638. goto partno;
  12639. if (len >= sizeof(tp->fw_ver))
  12640. len = sizeof(tp->fw_ver) - 1;
  12641. memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
  12642. snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
  12643. &vpd_data[j]);
  12644. }
  12645. partno:
  12646. i = pci_vpd_find_info_keyword(vpd_data, i, rosize,
  12647. PCI_VPD_RO_KEYWORD_PARTNO);
  12648. if (i < 0)
  12649. goto out_not_found;
  12650. len = pci_vpd_info_field_size(&vpd_data[i]);
  12651. i += PCI_VPD_INFO_FLD_HDR_SIZE;
  12652. if (len > TG3_BPN_SIZE ||
  12653. (len + i) > vpdlen)
  12654. goto out_not_found;
  12655. memcpy(tp->board_part_number, &vpd_data[i], len);
  12656. out_not_found:
  12657. kfree(vpd_data);
  12658. if (tp->board_part_number[0])
  12659. return;
  12660. out_no_vpd:
  12661. if (tg3_asic_rev(tp) == ASIC_REV_5717) {
  12662. if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
  12663. tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C)
  12664. strcpy(tp->board_part_number, "BCM5717");
  12665. else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718)
  12666. strcpy(tp->board_part_number, "BCM5718");
  12667. else
  12668. goto nomatch;
  12669. } else if (tg3_asic_rev(tp) == ASIC_REV_57780) {
  12670. if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
  12671. strcpy(tp->board_part_number, "BCM57780");
  12672. else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
  12673. strcpy(tp->board_part_number, "BCM57760");
  12674. else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
  12675. strcpy(tp->board_part_number, "BCM57790");
  12676. else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
  12677. strcpy(tp->board_part_number, "BCM57788");
  12678. else
  12679. goto nomatch;
  12680. } else if (tg3_asic_rev(tp) == ASIC_REV_57765) {
  12681. if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761)
  12682. strcpy(tp->board_part_number, "BCM57761");
  12683. else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765)
  12684. strcpy(tp->board_part_number, "BCM57765");
  12685. else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781)
  12686. strcpy(tp->board_part_number, "BCM57781");
  12687. else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785)
  12688. strcpy(tp->board_part_number, "BCM57785");
  12689. else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791)
  12690. strcpy(tp->board_part_number, "BCM57791");
  12691. else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
  12692. strcpy(tp->board_part_number, "BCM57795");
  12693. else
  12694. goto nomatch;
  12695. } else if (tg3_asic_rev(tp) == ASIC_REV_57766) {
  12696. if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762)
  12697. strcpy(tp->board_part_number, "BCM57762");
  12698. else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766)
  12699. strcpy(tp->board_part_number, "BCM57766");
  12700. else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782)
  12701. strcpy(tp->board_part_number, "BCM57782");
  12702. else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786)
  12703. strcpy(tp->board_part_number, "BCM57786");
  12704. else
  12705. goto nomatch;
  12706. } else if (tg3_asic_rev(tp) == ASIC_REV_5906) {
  12707. strcpy(tp->board_part_number, "BCM95906");
  12708. } else {
  12709. nomatch:
  12710. strcpy(tp->board_part_number, "none");
  12711. }
  12712. }
  12713. static int tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
  12714. {
  12715. u32 val;
  12716. if (tg3_nvram_read(tp, offset, &val) ||
  12717. (val & 0xfc000000) != 0x0c000000 ||
  12718. tg3_nvram_read(tp, offset + 4, &val) ||
  12719. val != 0)
  12720. return 0;
  12721. return 1;
  12722. }
  12723. static void tg3_read_bc_ver(struct tg3 *tp)
  12724. {
  12725. u32 val, offset, start, ver_offset;
  12726. int i, dst_off;
  12727. bool newver = false;
  12728. if (tg3_nvram_read(tp, 0xc, &offset) ||
  12729. tg3_nvram_read(tp, 0x4, &start))
  12730. return;
  12731. offset = tg3_nvram_logical_addr(tp, offset);
  12732. if (tg3_nvram_read(tp, offset, &val))
  12733. return;
  12734. if ((val & 0xfc000000) == 0x0c000000) {
  12735. if (tg3_nvram_read(tp, offset + 4, &val))
  12736. return;
  12737. if (val == 0)
  12738. newver = true;
  12739. }
  12740. dst_off = strlen(tp->fw_ver);
  12741. if (newver) {
  12742. if (TG3_VER_SIZE - dst_off < 16 ||
  12743. tg3_nvram_read(tp, offset + 8, &ver_offset))
  12744. return;
  12745. offset = offset + ver_offset - start;
  12746. for (i = 0; i < 16; i += 4) {
  12747. __be32 v;
  12748. if (tg3_nvram_read_be32(tp, offset + i, &v))
  12749. return;
  12750. memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v));
  12751. }
  12752. } else {
  12753. u32 major, minor;
  12754. if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
  12755. return;
  12756. major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
  12757. TG3_NVM_BCVER_MAJSFT;
  12758. minor = ver_offset & TG3_NVM_BCVER_MINMSK;
  12759. snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off,
  12760. "v%d.%02d", major, minor);
  12761. }
  12762. }
  12763. static void tg3_read_hwsb_ver(struct tg3 *tp)
  12764. {
  12765. u32 val, major, minor;
  12766. /* Use native endian representation */
  12767. if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
  12768. return;
  12769. major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
  12770. TG3_NVM_HWSB_CFG1_MAJSFT;
  12771. minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
  12772. TG3_NVM_HWSB_CFG1_MINSFT;
  12773. snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
  12774. }
  12775. static void tg3_read_sb_ver(struct tg3 *tp, u32 val)
  12776. {
  12777. u32 offset, major, minor, build;
  12778. strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1);
  12779. if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
  12780. return;
  12781. switch (val & TG3_EEPROM_SB_REVISION_MASK) {
  12782. case TG3_EEPROM_SB_REVISION_0:
  12783. offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
  12784. break;
  12785. case TG3_EEPROM_SB_REVISION_2:
  12786. offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
  12787. break;
  12788. case TG3_EEPROM_SB_REVISION_3:
  12789. offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
  12790. break;
  12791. case TG3_EEPROM_SB_REVISION_4:
  12792. offset = TG3_EEPROM_SB_F1R4_EDH_OFF;
  12793. break;
  12794. case TG3_EEPROM_SB_REVISION_5:
  12795. offset = TG3_EEPROM_SB_F1R5_EDH_OFF;
  12796. break;
  12797. case TG3_EEPROM_SB_REVISION_6:
  12798. offset = TG3_EEPROM_SB_F1R6_EDH_OFF;
  12799. break;
  12800. default:
  12801. return;
  12802. }
  12803. if (tg3_nvram_read(tp, offset, &val))
  12804. return;
  12805. build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
  12806. TG3_EEPROM_SB_EDH_BLD_SHFT;
  12807. major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
  12808. TG3_EEPROM_SB_EDH_MAJ_SHFT;
  12809. minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
  12810. if (minor > 99 || build > 26)
  12811. return;
  12812. offset = strlen(tp->fw_ver);
  12813. snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset,
  12814. " v%d.%02d", major, minor);
  12815. if (build > 0) {
  12816. offset = strlen(tp->fw_ver);
  12817. if (offset < TG3_VER_SIZE - 1)
  12818. tp->fw_ver[offset] = 'a' + build - 1;
  12819. }
  12820. }
  12821. static void tg3_read_mgmtfw_ver(struct tg3 *tp)
  12822. {
  12823. u32 val, offset, start;
  12824. int i, vlen;
  12825. for (offset = TG3_NVM_DIR_START;
  12826. offset < TG3_NVM_DIR_END;
  12827. offset += TG3_NVM_DIRENT_SIZE) {
  12828. if (tg3_nvram_read(tp, offset, &val))
  12829. return;
  12830. if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
  12831. break;
  12832. }
  12833. if (offset == TG3_NVM_DIR_END)
  12834. return;
  12835. if (!tg3_flag(tp, 5705_PLUS))
  12836. start = 0x08000000;
  12837. else if (tg3_nvram_read(tp, offset - 4, &start))
  12838. return;
  12839. if (tg3_nvram_read(tp, offset + 4, &offset) ||
  12840. !tg3_fw_img_is_valid(tp, offset) ||
  12841. tg3_nvram_read(tp, offset + 8, &val))
  12842. return;
  12843. offset += val - start;
  12844. vlen = strlen(tp->fw_ver);
  12845. tp->fw_ver[vlen++] = ',';
  12846. tp->fw_ver[vlen++] = ' ';
  12847. for (i = 0; i < 4; i++) {
  12848. __be32 v;
  12849. if (tg3_nvram_read_be32(tp, offset, &v))
  12850. return;
  12851. offset += sizeof(v);
  12852. if (vlen > TG3_VER_SIZE - sizeof(v)) {
  12853. memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
  12854. break;
  12855. }
  12856. memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
  12857. vlen += sizeof(v);
  12858. }
  12859. }
  12860. static void tg3_probe_ncsi(struct tg3 *tp)
  12861. {
  12862. u32 apedata;
  12863. apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
  12864. if (apedata != APE_SEG_SIG_MAGIC)
  12865. return;
  12866. apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
  12867. if (!(apedata & APE_FW_STATUS_READY))
  12868. return;
  12869. if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI)
  12870. tg3_flag_set(tp, APE_HAS_NCSI);
  12871. }
  12872. static void tg3_read_dash_ver(struct tg3 *tp)
  12873. {
  12874. int vlen;
  12875. u32 apedata;
  12876. char *fwtype;
  12877. apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
  12878. if (tg3_flag(tp, APE_HAS_NCSI))
  12879. fwtype = "NCSI";
  12880. else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725)
  12881. fwtype = "SMASH";
  12882. else
  12883. fwtype = "DASH";
  12884. vlen = strlen(tp->fw_ver);
  12885. snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d",
  12886. fwtype,
  12887. (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
  12888. (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
  12889. (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
  12890. (apedata & APE_FW_VERSION_BLDMSK));
  12891. }
  12892. static void tg3_read_otp_ver(struct tg3 *tp)
  12893. {
  12894. u32 val, val2;
  12895. if (tg3_asic_rev(tp) != ASIC_REV_5762)
  12896. return;
  12897. if (!tg3_ape_otp_read(tp, OTP_ADDRESS_MAGIC0, &val) &&
  12898. !tg3_ape_otp_read(tp, OTP_ADDRESS_MAGIC0 + 4, &val2) &&
  12899. TG3_OTP_MAGIC0_VALID(val)) {
  12900. u64 val64 = (u64) val << 32 | val2;
  12901. u32 ver = 0;
  12902. int i, vlen;
  12903. for (i = 0; i < 7; i++) {
  12904. if ((val64 & 0xff) == 0)
  12905. break;
  12906. ver = val64 & 0xff;
  12907. val64 >>= 8;
  12908. }
  12909. vlen = strlen(tp->fw_ver);
  12910. snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " .%02d", ver);
  12911. }
  12912. }
  12913. static void tg3_read_fw_ver(struct tg3 *tp)
  12914. {
  12915. u32 val;
  12916. bool vpd_vers = false;
  12917. if (tp->fw_ver[0] != 0)
  12918. vpd_vers = true;
  12919. if (tg3_flag(tp, NO_NVRAM)) {
  12920. strcat(tp->fw_ver, "sb");
  12921. tg3_read_otp_ver(tp);
  12922. return;
  12923. }
  12924. if (tg3_nvram_read(tp, 0, &val))
  12925. return;
  12926. if (val == TG3_EEPROM_MAGIC)
  12927. tg3_read_bc_ver(tp);
  12928. else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
  12929. tg3_read_sb_ver(tp, val);
  12930. else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
  12931. tg3_read_hwsb_ver(tp);
  12932. if (tg3_flag(tp, ENABLE_ASF)) {
  12933. if (tg3_flag(tp, ENABLE_APE)) {
  12934. tg3_probe_ncsi(tp);
  12935. if (!vpd_vers)
  12936. tg3_read_dash_ver(tp);
  12937. } else if (!vpd_vers) {
  12938. tg3_read_mgmtfw_ver(tp);
  12939. }
  12940. }
  12941. tp->fw_ver[TG3_VER_SIZE - 1] = 0;
  12942. }
  12943. static inline u32 tg3_rx_ret_ring_size(struct tg3 *tp)
  12944. {
  12945. if (tg3_flag(tp, LRG_PROD_RING_CAP))
  12946. return TG3_RX_RET_MAX_SIZE_5717;
  12947. else if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))
  12948. return TG3_RX_RET_MAX_SIZE_5700;
  12949. else
  12950. return TG3_RX_RET_MAX_SIZE_5705;
  12951. }
  12952. static DEFINE_PCI_DEVICE_TABLE(tg3_write_reorder_chipsets) = {
  12953. { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C) },
  12954. { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE) },
  12955. { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8385_0) },
  12956. { },
  12957. };
  12958. static struct pci_dev *tg3_find_peer(struct tg3 *tp)
  12959. {
  12960. struct pci_dev *peer;
  12961. unsigned int func, devnr = tp->pdev->devfn & ~7;
  12962. for (func = 0; func < 8; func++) {
  12963. peer = pci_get_slot(tp->pdev->bus, devnr | func);
  12964. if (peer && peer != tp->pdev)
  12965. break;
  12966. pci_dev_put(peer);
  12967. }
  12968. /* 5704 can be configured in single-port mode, set peer to
  12969. * tp->pdev in that case.
  12970. */
  12971. if (!peer) {
  12972. peer = tp->pdev;
  12973. return peer;
  12974. }
  12975. /*
  12976. * We don't need to keep the refcount elevated; there's no way
  12977. * to remove one half of this device without removing the other
  12978. */
  12979. pci_dev_put(peer);
  12980. return peer;
  12981. }
  12982. static void tg3_detect_asic_rev(struct tg3 *tp, u32 misc_ctrl_reg)
  12983. {
  12984. tp->pci_chip_rev_id = misc_ctrl_reg >> MISC_HOST_CTRL_CHIPREV_SHIFT;
  12985. if (tg3_asic_rev(tp) == ASIC_REV_USE_PROD_ID_REG) {
  12986. u32 reg;
  12987. /* All devices that use the alternate
  12988. * ASIC REV location have a CPMU.
  12989. */
  12990. tg3_flag_set(tp, CPMU_PRESENT);
  12991. if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
  12992. tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C ||
  12993. tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
  12994. tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||
  12995. tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720 ||
  12996. tp->pdev->device == TG3PCI_DEVICE_TIGON3_5762 ||
  12997. tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725 ||
  12998. tp->pdev->device == TG3PCI_DEVICE_TIGON3_5727)
  12999. reg = TG3PCI_GEN2_PRODID_ASICREV;
  13000. else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
  13001. tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
  13002. tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
  13003. tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
  13004. tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
  13005. tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
  13006. tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762 ||
  13007. tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766 ||
  13008. tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782 ||
  13009. tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786)
  13010. reg = TG3PCI_GEN15_PRODID_ASICREV;
  13011. else
  13012. reg = TG3PCI_PRODID_ASICREV;
  13013. pci_read_config_dword(tp->pdev, reg, &tp->pci_chip_rev_id);
  13014. }
  13015. /* Wrong chip ID in 5752 A0. This code can be removed later
  13016. * as A0 is not in production.
  13017. */
  13018. if (tg3_chip_rev_id(tp) == CHIPREV_ID_5752_A0_HW)
  13019. tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
  13020. if (tg3_chip_rev_id(tp) == CHIPREV_ID_5717_C0)
  13021. tp->pci_chip_rev_id = CHIPREV_ID_5720_A0;
  13022. if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
  13023. tg3_asic_rev(tp) == ASIC_REV_5719 ||
  13024. tg3_asic_rev(tp) == ASIC_REV_5720)
  13025. tg3_flag_set(tp, 5717_PLUS);
  13026. if (tg3_asic_rev(tp) == ASIC_REV_57765 ||
  13027. tg3_asic_rev(tp) == ASIC_REV_57766)
  13028. tg3_flag_set(tp, 57765_CLASS);
  13029. if (tg3_flag(tp, 57765_CLASS) || tg3_flag(tp, 5717_PLUS) ||
  13030. tg3_asic_rev(tp) == ASIC_REV_5762)
  13031. tg3_flag_set(tp, 57765_PLUS);
  13032. /* Intentionally exclude ASIC_REV_5906 */
  13033. if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
  13034. tg3_asic_rev(tp) == ASIC_REV_5787 ||
  13035. tg3_asic_rev(tp) == ASIC_REV_5784 ||
  13036. tg3_asic_rev(tp) == ASIC_REV_5761 ||
  13037. tg3_asic_rev(tp) == ASIC_REV_5785 ||
  13038. tg3_asic_rev(tp) == ASIC_REV_57780 ||
  13039. tg3_flag(tp, 57765_PLUS))
  13040. tg3_flag_set(tp, 5755_PLUS);
  13041. if (tg3_asic_rev(tp) == ASIC_REV_5780 ||
  13042. tg3_asic_rev(tp) == ASIC_REV_5714)
  13043. tg3_flag_set(tp, 5780_CLASS);
  13044. if (tg3_asic_rev(tp) == ASIC_REV_5750 ||
  13045. tg3_asic_rev(tp) == ASIC_REV_5752 ||
  13046. tg3_asic_rev(tp) == ASIC_REV_5906 ||
  13047. tg3_flag(tp, 5755_PLUS) ||
  13048. tg3_flag(tp, 5780_CLASS))
  13049. tg3_flag_set(tp, 5750_PLUS);
  13050. if (tg3_asic_rev(tp) == ASIC_REV_5705 ||
  13051. tg3_flag(tp, 5750_PLUS))
  13052. tg3_flag_set(tp, 5705_PLUS);
  13053. }
  13054. static bool tg3_10_100_only_device(struct tg3 *tp,
  13055. const struct pci_device_id *ent)
  13056. {
  13057. u32 grc_misc_cfg = tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK;
  13058. if ((tg3_asic_rev(tp) == ASIC_REV_5703 &&
  13059. (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
  13060. (tp->phy_flags & TG3_PHYFLG_IS_FET))
  13061. return true;
  13062. if (ent->driver_data & TG3_DRV_DATA_FLAG_10_100_ONLY) {
  13063. if (tg3_asic_rev(tp) == ASIC_REV_5705) {
  13064. if (ent->driver_data & TG3_DRV_DATA_FLAG_5705_10_100)
  13065. return true;
  13066. } else {
  13067. return true;
  13068. }
  13069. }
  13070. return false;
  13071. }
  13072. static int tg3_get_invariants(struct tg3 *tp, const struct pci_device_id *ent)
  13073. {
  13074. u32 misc_ctrl_reg;
  13075. u32 pci_state_reg, grc_misc_cfg;
  13076. u32 val;
  13077. u16 pci_cmd;
  13078. int err;
  13079. /* Force memory write invalidate off. If we leave it on,
  13080. * then on 5700_BX chips we have to enable a workaround.
  13081. * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
  13082. * to match the cacheline size. The Broadcom driver have this
  13083. * workaround but turns MWI off all the times so never uses
  13084. * it. This seems to suggest that the workaround is insufficient.
  13085. */
  13086. pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
  13087. pci_cmd &= ~PCI_COMMAND_INVALIDATE;
  13088. pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
  13089. /* Important! -- Make sure register accesses are byteswapped
  13090. * correctly. Also, for those chips that require it, make
  13091. * sure that indirect register accesses are enabled before
  13092. * the first operation.
  13093. */
  13094. pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
  13095. &misc_ctrl_reg);
  13096. tp->misc_host_ctrl |= (misc_ctrl_reg &
  13097. MISC_HOST_CTRL_CHIPREV);
  13098. pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
  13099. tp->misc_host_ctrl);
  13100. tg3_detect_asic_rev(tp, misc_ctrl_reg);
  13101. /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
  13102. * we need to disable memory and use config. cycles
  13103. * only to access all registers. The 5702/03 chips
  13104. * can mistakenly decode the special cycles from the
  13105. * ICH chipsets as memory write cycles, causing corruption
  13106. * of register and memory space. Only certain ICH bridges
  13107. * will drive special cycles with non-zero data during the
  13108. * address phase which can fall within the 5703's address
  13109. * range. This is not an ICH bug as the PCI spec allows
  13110. * non-zero address during special cycles. However, only
  13111. * these ICH bridges are known to drive non-zero addresses
  13112. * during special cycles.
  13113. *
  13114. * Since special cycles do not cross PCI bridges, we only
  13115. * enable this workaround if the 5703 is on the secondary
  13116. * bus of these ICH bridges.
  13117. */
  13118. if ((tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A1) ||
  13119. (tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A2)) {
  13120. static struct tg3_dev_id {
  13121. u32 vendor;
  13122. u32 device;
  13123. u32 rev;
  13124. } ich_chipsets[] = {
  13125. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
  13126. PCI_ANY_ID },
  13127. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
  13128. PCI_ANY_ID },
  13129. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
  13130. 0xa },
  13131. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
  13132. PCI_ANY_ID },
  13133. { },
  13134. };
  13135. struct tg3_dev_id *pci_id = &ich_chipsets[0];
  13136. struct pci_dev *bridge = NULL;
  13137. while (pci_id->vendor != 0) {
  13138. bridge = pci_get_device(pci_id->vendor, pci_id->device,
  13139. bridge);
  13140. if (!bridge) {
  13141. pci_id++;
  13142. continue;
  13143. }
  13144. if (pci_id->rev != PCI_ANY_ID) {
  13145. if (bridge->revision > pci_id->rev)
  13146. continue;
  13147. }
  13148. if (bridge->subordinate &&
  13149. (bridge->subordinate->number ==
  13150. tp->pdev->bus->number)) {
  13151. tg3_flag_set(tp, ICH_WORKAROUND);
  13152. pci_dev_put(bridge);
  13153. break;
  13154. }
  13155. }
  13156. }
  13157. if (tg3_asic_rev(tp) == ASIC_REV_5701) {
  13158. static struct tg3_dev_id {
  13159. u32 vendor;
  13160. u32 device;
  13161. } bridge_chipsets[] = {
  13162. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
  13163. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
  13164. { },
  13165. };
  13166. struct tg3_dev_id *pci_id = &bridge_chipsets[0];
  13167. struct pci_dev *bridge = NULL;
  13168. while (pci_id->vendor != 0) {
  13169. bridge = pci_get_device(pci_id->vendor,
  13170. pci_id->device,
  13171. bridge);
  13172. if (!bridge) {
  13173. pci_id++;
  13174. continue;
  13175. }
  13176. if (bridge->subordinate &&
  13177. (bridge->subordinate->number <=
  13178. tp->pdev->bus->number) &&
  13179. (bridge->subordinate->busn_res.end >=
  13180. tp->pdev->bus->number)) {
  13181. tg3_flag_set(tp, 5701_DMA_BUG);
  13182. pci_dev_put(bridge);
  13183. break;
  13184. }
  13185. }
  13186. }
  13187. /* The EPB bridge inside 5714, 5715, and 5780 cannot support
  13188. * DMA addresses > 40-bit. This bridge may have other additional
  13189. * 57xx devices behind it in some 4-port NIC designs for example.
  13190. * Any tg3 device found behind the bridge will also need the 40-bit
  13191. * DMA workaround.
  13192. */
  13193. if (tg3_flag(tp, 5780_CLASS)) {
  13194. tg3_flag_set(tp, 40BIT_DMA_BUG);
  13195. tp->msi_cap = tp->pdev->msi_cap;
  13196. } else {
  13197. struct pci_dev *bridge = NULL;
  13198. do {
  13199. bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
  13200. PCI_DEVICE_ID_SERVERWORKS_EPB,
  13201. bridge);
  13202. if (bridge && bridge->subordinate &&
  13203. (bridge->subordinate->number <=
  13204. tp->pdev->bus->number) &&
  13205. (bridge->subordinate->busn_res.end >=
  13206. tp->pdev->bus->number)) {
  13207. tg3_flag_set(tp, 40BIT_DMA_BUG);
  13208. pci_dev_put(bridge);
  13209. break;
  13210. }
  13211. } while (bridge);
  13212. }
  13213. if (tg3_asic_rev(tp) == ASIC_REV_5704 ||
  13214. tg3_asic_rev(tp) == ASIC_REV_5714)
  13215. tp->pdev_peer = tg3_find_peer(tp);
  13216. /* Determine TSO capabilities */
  13217. if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0)
  13218. ; /* Do nothing. HW bug. */
  13219. else if (tg3_flag(tp, 57765_PLUS))
  13220. tg3_flag_set(tp, HW_TSO_3);
  13221. else if (tg3_flag(tp, 5755_PLUS) ||
  13222. tg3_asic_rev(tp) == ASIC_REV_5906)
  13223. tg3_flag_set(tp, HW_TSO_2);
  13224. else if (tg3_flag(tp, 5750_PLUS)) {
  13225. tg3_flag_set(tp, HW_TSO_1);
  13226. tg3_flag_set(tp, TSO_BUG);
  13227. if (tg3_asic_rev(tp) == ASIC_REV_5750 &&
  13228. tg3_chip_rev_id(tp) >= CHIPREV_ID_5750_C2)
  13229. tg3_flag_clear(tp, TSO_BUG);
  13230. } else if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
  13231. tg3_asic_rev(tp) != ASIC_REV_5701 &&
  13232. tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) {
  13233. tg3_flag_set(tp, FW_TSO);
  13234. tg3_flag_set(tp, TSO_BUG);
  13235. if (tg3_asic_rev(tp) == ASIC_REV_5705)
  13236. tp->fw_needed = FIRMWARE_TG3TSO5;
  13237. else
  13238. tp->fw_needed = FIRMWARE_TG3TSO;
  13239. }
  13240. /* Selectively allow TSO based on operating conditions */
  13241. if (tg3_flag(tp, HW_TSO_1) ||
  13242. tg3_flag(tp, HW_TSO_2) ||
  13243. tg3_flag(tp, HW_TSO_3) ||
  13244. tg3_flag(tp, FW_TSO)) {
  13245. /* For firmware TSO, assume ASF is disabled.
  13246. * We'll disable TSO later if we discover ASF
  13247. * is enabled in tg3_get_eeprom_hw_cfg().
  13248. */
  13249. tg3_flag_set(tp, TSO_CAPABLE);
  13250. } else {
  13251. tg3_flag_clear(tp, TSO_CAPABLE);
  13252. tg3_flag_clear(tp, TSO_BUG);
  13253. tp->fw_needed = NULL;
  13254. }
  13255. if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0)
  13256. tp->fw_needed = FIRMWARE_TG3;
  13257. if (tg3_asic_rev(tp) == ASIC_REV_57766)
  13258. tp->fw_needed = FIRMWARE_TG357766;
  13259. tp->irq_max = 1;
  13260. if (tg3_flag(tp, 5750_PLUS)) {
  13261. tg3_flag_set(tp, SUPPORT_MSI);
  13262. if (tg3_chip_rev(tp) == CHIPREV_5750_AX ||
  13263. tg3_chip_rev(tp) == CHIPREV_5750_BX ||
  13264. (tg3_asic_rev(tp) == ASIC_REV_5714 &&
  13265. tg3_chip_rev_id(tp) <= CHIPREV_ID_5714_A2 &&
  13266. tp->pdev_peer == tp->pdev))
  13267. tg3_flag_clear(tp, SUPPORT_MSI);
  13268. if (tg3_flag(tp, 5755_PLUS) ||
  13269. tg3_asic_rev(tp) == ASIC_REV_5906) {
  13270. tg3_flag_set(tp, 1SHOT_MSI);
  13271. }
  13272. if (tg3_flag(tp, 57765_PLUS)) {
  13273. tg3_flag_set(tp, SUPPORT_MSIX);
  13274. tp->irq_max = TG3_IRQ_MAX_VECS;
  13275. }
  13276. }
  13277. tp->txq_max = 1;
  13278. tp->rxq_max = 1;
  13279. if (tp->irq_max > 1) {
  13280. tp->rxq_max = TG3_RSS_MAX_NUM_QS;
  13281. tg3_rss_init_dflt_indir_tbl(tp, TG3_RSS_MAX_NUM_QS);
  13282. if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
  13283. tg3_asic_rev(tp) == ASIC_REV_5720)
  13284. tp->txq_max = tp->irq_max - 1;
  13285. }
  13286. if (tg3_flag(tp, 5755_PLUS) ||
  13287. tg3_asic_rev(tp) == ASIC_REV_5906)
  13288. tg3_flag_set(tp, SHORT_DMA_BUG);
  13289. if (tg3_asic_rev(tp) == ASIC_REV_5719)
  13290. tp->dma_limit = TG3_TX_BD_DMA_MAX_4K;
  13291. if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
  13292. tg3_asic_rev(tp) == ASIC_REV_5719 ||
  13293. tg3_asic_rev(tp) == ASIC_REV_5720 ||
  13294. tg3_asic_rev(tp) == ASIC_REV_5762)
  13295. tg3_flag_set(tp, LRG_PROD_RING_CAP);
  13296. if (tg3_flag(tp, 57765_PLUS) &&
  13297. tg3_chip_rev_id(tp) != CHIPREV_ID_5719_A0)
  13298. tg3_flag_set(tp, USE_JUMBO_BDFLAG);
  13299. if (!tg3_flag(tp, 5705_PLUS) ||
  13300. tg3_flag(tp, 5780_CLASS) ||
  13301. tg3_flag(tp, USE_JUMBO_BDFLAG))
  13302. tg3_flag_set(tp, JUMBO_CAPABLE);
  13303. pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
  13304. &pci_state_reg);
  13305. if (pci_is_pcie(tp->pdev)) {
  13306. u16 lnkctl;
  13307. tg3_flag_set(tp, PCI_EXPRESS);
  13308. pcie_capability_read_word(tp->pdev, PCI_EXP_LNKCTL, &lnkctl);
  13309. if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
  13310. if (tg3_asic_rev(tp) == ASIC_REV_5906) {
  13311. tg3_flag_clear(tp, HW_TSO_2);
  13312. tg3_flag_clear(tp, TSO_CAPABLE);
  13313. }
  13314. if (tg3_asic_rev(tp) == ASIC_REV_5784 ||
  13315. tg3_asic_rev(tp) == ASIC_REV_5761 ||
  13316. tg3_chip_rev_id(tp) == CHIPREV_ID_57780_A0 ||
  13317. tg3_chip_rev_id(tp) == CHIPREV_ID_57780_A1)
  13318. tg3_flag_set(tp, CLKREQ_BUG);
  13319. } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5717_A0) {
  13320. tg3_flag_set(tp, L1PLLPD_EN);
  13321. }
  13322. } else if (tg3_asic_rev(tp) == ASIC_REV_5785) {
  13323. /* BCM5785 devices are effectively PCIe devices, and should
  13324. * follow PCIe codepaths, but do not have a PCIe capabilities
  13325. * section.
  13326. */
  13327. tg3_flag_set(tp, PCI_EXPRESS);
  13328. } else if (!tg3_flag(tp, 5705_PLUS) ||
  13329. tg3_flag(tp, 5780_CLASS)) {
  13330. tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
  13331. if (!tp->pcix_cap) {
  13332. dev_err(&tp->pdev->dev,
  13333. "Cannot find PCI-X capability, aborting\n");
  13334. return -EIO;
  13335. }
  13336. if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
  13337. tg3_flag_set(tp, PCIX_MODE);
  13338. }
  13339. /* If we have an AMD 762 or VIA K8T800 chipset, write
  13340. * reordering to the mailbox registers done by the host
  13341. * controller can cause major troubles. We read back from
  13342. * every mailbox register write to force the writes to be
  13343. * posted to the chip in order.
  13344. */
  13345. if (pci_dev_present(tg3_write_reorder_chipsets) &&
  13346. !tg3_flag(tp, PCI_EXPRESS))
  13347. tg3_flag_set(tp, MBOX_WRITE_REORDER);
  13348. pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
  13349. &tp->pci_cacheline_sz);
  13350. pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
  13351. &tp->pci_lat_timer);
  13352. if (tg3_asic_rev(tp) == ASIC_REV_5703 &&
  13353. tp->pci_lat_timer < 64) {
  13354. tp->pci_lat_timer = 64;
  13355. pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
  13356. tp->pci_lat_timer);
  13357. }
  13358. /* Important! -- It is critical that the PCI-X hw workaround
  13359. * situation is decided before the first MMIO register access.
  13360. */
  13361. if (tg3_chip_rev(tp) == CHIPREV_5700_BX) {
  13362. /* 5700 BX chips need to have their TX producer index
  13363. * mailboxes written twice to workaround a bug.
  13364. */
  13365. tg3_flag_set(tp, TXD_MBOX_HWBUG);
  13366. /* If we are in PCI-X mode, enable register write workaround.
  13367. *
  13368. * The workaround is to use indirect register accesses
  13369. * for all chip writes not to mailbox registers.
  13370. */
  13371. if (tg3_flag(tp, PCIX_MODE)) {
  13372. u32 pm_reg;
  13373. tg3_flag_set(tp, PCIX_TARGET_HWBUG);
  13374. /* The chip can have it's power management PCI config
  13375. * space registers clobbered due to this bug.
  13376. * So explicitly force the chip into D0 here.
  13377. */
  13378. pci_read_config_dword(tp->pdev,
  13379. tp->pm_cap + PCI_PM_CTRL,
  13380. &pm_reg);
  13381. pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
  13382. pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
  13383. pci_write_config_dword(tp->pdev,
  13384. tp->pm_cap + PCI_PM_CTRL,
  13385. pm_reg);
  13386. /* Also, force SERR#/PERR# in PCI command. */
  13387. pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
  13388. pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
  13389. pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
  13390. }
  13391. }
  13392. if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
  13393. tg3_flag_set(tp, PCI_HIGH_SPEED);
  13394. if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
  13395. tg3_flag_set(tp, PCI_32BIT);
  13396. /* Chip-specific fixup from Broadcom driver */
  13397. if ((tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0) &&
  13398. (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
  13399. pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
  13400. pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
  13401. }
  13402. /* Default fast path register access methods */
  13403. tp->read32 = tg3_read32;
  13404. tp->write32 = tg3_write32;
  13405. tp->read32_mbox = tg3_read32;
  13406. tp->write32_mbox = tg3_write32;
  13407. tp->write32_tx_mbox = tg3_write32;
  13408. tp->write32_rx_mbox = tg3_write32;
  13409. /* Various workaround register access methods */
  13410. if (tg3_flag(tp, PCIX_TARGET_HWBUG))
  13411. tp->write32 = tg3_write_indirect_reg32;
  13412. else if (tg3_asic_rev(tp) == ASIC_REV_5701 ||
  13413. (tg3_flag(tp, PCI_EXPRESS) &&
  13414. tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A0)) {
  13415. /*
  13416. * Back to back register writes can cause problems on these
  13417. * chips, the workaround is to read back all reg writes
  13418. * except those to mailbox regs.
  13419. *
  13420. * See tg3_write_indirect_reg32().
  13421. */
  13422. tp->write32 = tg3_write_flush_reg32;
  13423. }
  13424. if (tg3_flag(tp, TXD_MBOX_HWBUG) || tg3_flag(tp, MBOX_WRITE_REORDER)) {
  13425. tp->write32_tx_mbox = tg3_write32_tx_mbox;
  13426. if (tg3_flag(tp, MBOX_WRITE_REORDER))
  13427. tp->write32_rx_mbox = tg3_write_flush_reg32;
  13428. }
  13429. if (tg3_flag(tp, ICH_WORKAROUND)) {
  13430. tp->read32 = tg3_read_indirect_reg32;
  13431. tp->write32 = tg3_write_indirect_reg32;
  13432. tp->read32_mbox = tg3_read_indirect_mbox;
  13433. tp->write32_mbox = tg3_write_indirect_mbox;
  13434. tp->write32_tx_mbox = tg3_write_indirect_mbox;
  13435. tp->write32_rx_mbox = tg3_write_indirect_mbox;
  13436. iounmap(tp->regs);
  13437. tp->regs = NULL;
  13438. pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
  13439. pci_cmd &= ~PCI_COMMAND_MEMORY;
  13440. pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
  13441. }
  13442. if (tg3_asic_rev(tp) == ASIC_REV_5906) {
  13443. tp->read32_mbox = tg3_read32_mbox_5906;
  13444. tp->write32_mbox = tg3_write32_mbox_5906;
  13445. tp->write32_tx_mbox = tg3_write32_mbox_5906;
  13446. tp->write32_rx_mbox = tg3_write32_mbox_5906;
  13447. }
  13448. if (tp->write32 == tg3_write_indirect_reg32 ||
  13449. (tg3_flag(tp, PCIX_MODE) &&
  13450. (tg3_asic_rev(tp) == ASIC_REV_5700 ||
  13451. tg3_asic_rev(tp) == ASIC_REV_5701)))
  13452. tg3_flag_set(tp, SRAM_USE_CONFIG);
  13453. /* The memory arbiter has to be enabled in order for SRAM accesses
  13454. * to succeed. Normally on powerup the tg3 chip firmware will make
  13455. * sure it is enabled, but other entities such as system netboot
  13456. * code might disable it.
  13457. */
  13458. val = tr32(MEMARB_MODE);
  13459. tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
  13460. tp->pci_fn = PCI_FUNC(tp->pdev->devfn) & 3;
  13461. if (tg3_asic_rev(tp) == ASIC_REV_5704 ||
  13462. tg3_flag(tp, 5780_CLASS)) {
  13463. if (tg3_flag(tp, PCIX_MODE)) {
  13464. pci_read_config_dword(tp->pdev,
  13465. tp->pcix_cap + PCI_X_STATUS,
  13466. &val);
  13467. tp->pci_fn = val & 0x7;
  13468. }
  13469. } else if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
  13470. tg3_asic_rev(tp) == ASIC_REV_5719 ||
  13471. tg3_asic_rev(tp) == ASIC_REV_5720) {
  13472. tg3_read_mem(tp, NIC_SRAM_CPMU_STATUS, &val);
  13473. if ((val & NIC_SRAM_CPMUSTAT_SIG_MSK) != NIC_SRAM_CPMUSTAT_SIG)
  13474. val = tr32(TG3_CPMU_STATUS);
  13475. if (tg3_asic_rev(tp) == ASIC_REV_5717)
  13476. tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5717) ? 1 : 0;
  13477. else
  13478. tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5719) >>
  13479. TG3_CPMU_STATUS_FSHFT_5719;
  13480. }
  13481. if (tg3_flag(tp, FLUSH_POSTED_WRITES)) {
  13482. tp->write32_tx_mbox = tg3_write_flush_reg32;
  13483. tp->write32_rx_mbox = tg3_write_flush_reg32;
  13484. }
  13485. /* Get eeprom hw config before calling tg3_set_power_state().
  13486. * In particular, the TG3_FLAG_IS_NIC flag must be
  13487. * determined before calling tg3_set_power_state() so that
  13488. * we know whether or not to switch out of Vaux power.
  13489. * When the flag is set, it means that GPIO1 is used for eeprom
  13490. * write protect and also implies that it is a LOM where GPIOs
  13491. * are not used to switch power.
  13492. */
  13493. tg3_get_eeprom_hw_cfg(tp);
  13494. if (tg3_flag(tp, FW_TSO) && tg3_flag(tp, ENABLE_ASF)) {
  13495. tg3_flag_clear(tp, TSO_CAPABLE);
  13496. tg3_flag_clear(tp, TSO_BUG);
  13497. tp->fw_needed = NULL;
  13498. }
  13499. if (tg3_flag(tp, ENABLE_APE)) {
  13500. /* Allow reads and writes to the
  13501. * APE register and memory space.
  13502. */
  13503. pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
  13504. PCISTATE_ALLOW_APE_SHMEM_WR |
  13505. PCISTATE_ALLOW_APE_PSPACE_WR;
  13506. pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
  13507. pci_state_reg);
  13508. tg3_ape_lock_init(tp);
  13509. }
  13510. /* Set up tp->grc_local_ctrl before calling
  13511. * tg3_pwrsrc_switch_to_vmain(). GPIO1 driven high
  13512. * will bring 5700's external PHY out of reset.
  13513. * It is also used as eeprom write protect on LOMs.
  13514. */
  13515. tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
  13516. if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
  13517. tg3_flag(tp, EEPROM_WRITE_PROT))
  13518. tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
  13519. GRC_LCLCTRL_GPIO_OUTPUT1);
  13520. /* Unused GPIO3 must be driven as output on 5752 because there
  13521. * are no pull-up resistors on unused GPIO pins.
  13522. */
  13523. else if (tg3_asic_rev(tp) == ASIC_REV_5752)
  13524. tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
  13525. if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
  13526. tg3_asic_rev(tp) == ASIC_REV_57780 ||
  13527. tg3_flag(tp, 57765_CLASS))
  13528. tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
  13529. if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
  13530. tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
  13531. /* Turn off the debug UART. */
  13532. tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
  13533. if (tg3_flag(tp, IS_NIC))
  13534. /* Keep VMain power. */
  13535. tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
  13536. GRC_LCLCTRL_GPIO_OUTPUT0;
  13537. }
  13538. if (tg3_asic_rev(tp) == ASIC_REV_5762)
  13539. tp->grc_local_ctrl |=
  13540. tr32(GRC_LOCAL_CTRL) & GRC_LCLCTRL_GPIO_UART_SEL;
  13541. /* Switch out of Vaux if it is a NIC */
  13542. tg3_pwrsrc_switch_to_vmain(tp);
  13543. /* Derive initial jumbo mode from MTU assigned in
  13544. * ether_setup() via the alloc_etherdev() call
  13545. */
  13546. if (tp->dev->mtu > ETH_DATA_LEN && !tg3_flag(tp, 5780_CLASS))
  13547. tg3_flag_set(tp, JUMBO_RING_ENABLE);
  13548. /* Determine WakeOnLan speed to use. */
  13549. if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
  13550. tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
  13551. tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0 ||
  13552. tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B2) {
  13553. tg3_flag_clear(tp, WOL_SPEED_100MB);
  13554. } else {
  13555. tg3_flag_set(tp, WOL_SPEED_100MB);
  13556. }
  13557. if (tg3_asic_rev(tp) == ASIC_REV_5906)
  13558. tp->phy_flags |= TG3_PHYFLG_IS_FET;
  13559. /* A few boards don't want Ethernet@WireSpeed phy feature */
  13560. if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
  13561. (tg3_asic_rev(tp) == ASIC_REV_5705 &&
  13562. (tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) &&
  13563. (tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A1)) ||
  13564. (tp->phy_flags & TG3_PHYFLG_IS_FET) ||
  13565. (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
  13566. tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED;
  13567. if (tg3_chip_rev(tp) == CHIPREV_5703_AX ||
  13568. tg3_chip_rev(tp) == CHIPREV_5704_AX)
  13569. tp->phy_flags |= TG3_PHYFLG_ADC_BUG;
  13570. if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0)
  13571. tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG;
  13572. if (tg3_flag(tp, 5705_PLUS) &&
  13573. !(tp->phy_flags & TG3_PHYFLG_IS_FET) &&
  13574. tg3_asic_rev(tp) != ASIC_REV_5785 &&
  13575. tg3_asic_rev(tp) != ASIC_REV_57780 &&
  13576. !tg3_flag(tp, 57765_PLUS)) {
  13577. if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
  13578. tg3_asic_rev(tp) == ASIC_REV_5787 ||
  13579. tg3_asic_rev(tp) == ASIC_REV_5784 ||
  13580. tg3_asic_rev(tp) == ASIC_REV_5761) {
  13581. if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
  13582. tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
  13583. tp->phy_flags |= TG3_PHYFLG_JITTER_BUG;
  13584. if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
  13585. tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM;
  13586. } else
  13587. tp->phy_flags |= TG3_PHYFLG_BER_BUG;
  13588. }
  13589. if (tg3_asic_rev(tp) == ASIC_REV_5784 &&
  13590. tg3_chip_rev(tp) != CHIPREV_5784_AX) {
  13591. tp->phy_otp = tg3_read_otp_phycfg(tp);
  13592. if (tp->phy_otp == 0)
  13593. tp->phy_otp = TG3_OTP_DEFAULT;
  13594. }
  13595. if (tg3_flag(tp, CPMU_PRESENT))
  13596. tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
  13597. else
  13598. tp->mi_mode = MAC_MI_MODE_BASE;
  13599. tp->coalesce_mode = 0;
  13600. if (tg3_chip_rev(tp) != CHIPREV_5700_AX &&
  13601. tg3_chip_rev(tp) != CHIPREV_5700_BX)
  13602. tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
  13603. /* Set these bits to enable statistics workaround. */
  13604. if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
  13605. tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
  13606. tg3_chip_rev_id(tp) == CHIPREV_ID_5720_A0) {
  13607. tp->coalesce_mode |= HOSTCC_MODE_ATTN;
  13608. tp->grc_mode |= GRC_MODE_IRQ_ON_FLOW_ATTN;
  13609. }
  13610. if (tg3_asic_rev(tp) == ASIC_REV_5785 ||
  13611. tg3_asic_rev(tp) == ASIC_REV_57780)
  13612. tg3_flag_set(tp, USE_PHYLIB);
  13613. err = tg3_mdio_init(tp);
  13614. if (err)
  13615. return err;
  13616. /* Initialize data/descriptor byte/word swapping. */
  13617. val = tr32(GRC_MODE);
  13618. if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
  13619. tg3_asic_rev(tp) == ASIC_REV_5762)
  13620. val &= (GRC_MODE_BYTE_SWAP_B2HRX_DATA |
  13621. GRC_MODE_WORD_SWAP_B2HRX_DATA |
  13622. GRC_MODE_B2HRX_ENABLE |
  13623. GRC_MODE_HTX2B_ENABLE |
  13624. GRC_MODE_HOST_STACKUP);
  13625. else
  13626. val &= GRC_MODE_HOST_STACKUP;
  13627. tw32(GRC_MODE, val | tp->grc_mode);
  13628. tg3_switch_clocks(tp);
  13629. /* Clear this out for sanity. */
  13630. tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
  13631. pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
  13632. &pci_state_reg);
  13633. if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
  13634. !tg3_flag(tp, PCIX_TARGET_HWBUG)) {
  13635. if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
  13636. tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0 ||
  13637. tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B2 ||
  13638. tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B5) {
  13639. void __iomem *sram_base;
  13640. /* Write some dummy words into the SRAM status block
  13641. * area, see if it reads back correctly. If the return
  13642. * value is bad, force enable the PCIX workaround.
  13643. */
  13644. sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
  13645. writel(0x00000000, sram_base);
  13646. writel(0x00000000, sram_base + 4);
  13647. writel(0xffffffff, sram_base + 4);
  13648. if (readl(sram_base) != 0x00000000)
  13649. tg3_flag_set(tp, PCIX_TARGET_HWBUG);
  13650. }
  13651. }
  13652. udelay(50);
  13653. tg3_nvram_init(tp);
  13654. /* If the device has an NVRAM, no need to load patch firmware */
  13655. if (tg3_asic_rev(tp) == ASIC_REV_57766 &&
  13656. !tg3_flag(tp, NO_NVRAM))
  13657. tp->fw_needed = NULL;
  13658. grc_misc_cfg = tr32(GRC_MISC_CFG);
  13659. grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
  13660. if (tg3_asic_rev(tp) == ASIC_REV_5705 &&
  13661. (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
  13662. grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
  13663. tg3_flag_set(tp, IS_5788);
  13664. if (!tg3_flag(tp, IS_5788) &&
  13665. tg3_asic_rev(tp) != ASIC_REV_5700)
  13666. tg3_flag_set(tp, TAGGED_STATUS);
  13667. if (tg3_flag(tp, TAGGED_STATUS)) {
  13668. tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
  13669. HOSTCC_MODE_CLRTICK_TXBD);
  13670. tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
  13671. pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
  13672. tp->misc_host_ctrl);
  13673. }
  13674. /* Preserve the APE MAC_MODE bits */
  13675. if (tg3_flag(tp, ENABLE_APE))
  13676. tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
  13677. else
  13678. tp->mac_mode = 0;
  13679. if (tg3_10_100_only_device(tp, ent))
  13680. tp->phy_flags |= TG3_PHYFLG_10_100_ONLY;
  13681. err = tg3_phy_probe(tp);
  13682. if (err) {
  13683. dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err);
  13684. /* ... but do not return immediately ... */
  13685. tg3_mdio_fini(tp);
  13686. }
  13687. tg3_read_vpd(tp);
  13688. tg3_read_fw_ver(tp);
  13689. if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
  13690. tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
  13691. } else {
  13692. if (tg3_asic_rev(tp) == ASIC_REV_5700)
  13693. tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
  13694. else
  13695. tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
  13696. }
  13697. /* 5700 {AX,BX} chips have a broken status block link
  13698. * change bit implementation, so we must use the
  13699. * status register in those cases.
  13700. */
  13701. if (tg3_asic_rev(tp) == ASIC_REV_5700)
  13702. tg3_flag_set(tp, USE_LINKCHG_REG);
  13703. else
  13704. tg3_flag_clear(tp, USE_LINKCHG_REG);
  13705. /* The led_ctrl is set during tg3_phy_probe, here we might
  13706. * have to force the link status polling mechanism based
  13707. * upon subsystem IDs.
  13708. */
  13709. if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
  13710. tg3_asic_rev(tp) == ASIC_REV_5701 &&
  13711. !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
  13712. tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
  13713. tg3_flag_set(tp, USE_LINKCHG_REG);
  13714. }
  13715. /* For all SERDES we poll the MAC status register. */
  13716. if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
  13717. tg3_flag_set(tp, POLL_SERDES);
  13718. else
  13719. tg3_flag_clear(tp, POLL_SERDES);
  13720. tp->rx_offset = NET_SKB_PAD + NET_IP_ALIGN;
  13721. tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD;
  13722. if (tg3_asic_rev(tp) == ASIC_REV_5701 &&
  13723. tg3_flag(tp, PCIX_MODE)) {
  13724. tp->rx_offset = NET_SKB_PAD;
  13725. #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
  13726. tp->rx_copy_thresh = ~(u16)0;
  13727. #endif
  13728. }
  13729. tp->rx_std_ring_mask = TG3_RX_STD_RING_SIZE(tp) - 1;
  13730. tp->rx_jmb_ring_mask = TG3_RX_JMB_RING_SIZE(tp) - 1;
  13731. tp->rx_ret_ring_mask = tg3_rx_ret_ring_size(tp) - 1;
  13732. tp->rx_std_max_post = tp->rx_std_ring_mask + 1;
  13733. /* Increment the rx prod index on the rx std ring by at most
  13734. * 8 for these chips to workaround hw errata.
  13735. */
  13736. if (tg3_asic_rev(tp) == ASIC_REV_5750 ||
  13737. tg3_asic_rev(tp) == ASIC_REV_5752 ||
  13738. tg3_asic_rev(tp) == ASIC_REV_5755)
  13739. tp->rx_std_max_post = 8;
  13740. if (tg3_flag(tp, ASPM_WORKAROUND))
  13741. tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
  13742. PCIE_PWR_MGMT_L1_THRESH_MSK;
  13743. return err;
  13744. }
  13745. #ifdef CONFIG_SPARC
  13746. static int tg3_get_macaddr_sparc(struct tg3 *tp)
  13747. {
  13748. struct net_device *dev = tp->dev;
  13749. struct pci_dev *pdev = tp->pdev;
  13750. struct device_node *dp = pci_device_to_OF_node(pdev);
  13751. const unsigned char *addr;
  13752. int len;
  13753. addr = of_get_property(dp, "local-mac-address", &len);
  13754. if (addr && len == 6) {
  13755. memcpy(dev->dev_addr, addr, 6);
  13756. return 0;
  13757. }
  13758. return -ENODEV;
  13759. }
  13760. static int tg3_get_default_macaddr_sparc(struct tg3 *tp)
  13761. {
  13762. struct net_device *dev = tp->dev;
  13763. memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
  13764. return 0;
  13765. }
  13766. #endif
  13767. static int tg3_get_device_address(struct tg3 *tp)
  13768. {
  13769. struct net_device *dev = tp->dev;
  13770. u32 hi, lo, mac_offset;
  13771. int addr_ok = 0;
  13772. int err;
  13773. #ifdef CONFIG_SPARC
  13774. if (!tg3_get_macaddr_sparc(tp))
  13775. return 0;
  13776. #endif
  13777. if (tg3_flag(tp, IS_SSB_CORE)) {
  13778. err = ssb_gige_get_macaddr(tp->pdev, &dev->dev_addr[0]);
  13779. if (!err && is_valid_ether_addr(&dev->dev_addr[0]))
  13780. return 0;
  13781. }
  13782. mac_offset = 0x7c;
  13783. if (tg3_asic_rev(tp) == ASIC_REV_5704 ||
  13784. tg3_flag(tp, 5780_CLASS)) {
  13785. if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
  13786. mac_offset = 0xcc;
  13787. if (tg3_nvram_lock(tp))
  13788. tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
  13789. else
  13790. tg3_nvram_unlock(tp);
  13791. } else if (tg3_flag(tp, 5717_PLUS)) {
  13792. if (tp->pci_fn & 1)
  13793. mac_offset = 0xcc;
  13794. if (tp->pci_fn > 1)
  13795. mac_offset += 0x18c;
  13796. } else if (tg3_asic_rev(tp) == ASIC_REV_5906)
  13797. mac_offset = 0x10;
  13798. /* First try to get it from MAC address mailbox. */
  13799. tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
  13800. if ((hi >> 16) == 0x484b) {
  13801. dev->dev_addr[0] = (hi >> 8) & 0xff;
  13802. dev->dev_addr[1] = (hi >> 0) & 0xff;
  13803. tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
  13804. dev->dev_addr[2] = (lo >> 24) & 0xff;
  13805. dev->dev_addr[3] = (lo >> 16) & 0xff;
  13806. dev->dev_addr[4] = (lo >> 8) & 0xff;
  13807. dev->dev_addr[5] = (lo >> 0) & 0xff;
  13808. /* Some old bootcode may report a 0 MAC address in SRAM */
  13809. addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
  13810. }
  13811. if (!addr_ok) {
  13812. /* Next, try NVRAM. */
  13813. if (!tg3_flag(tp, NO_NVRAM) &&
  13814. !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
  13815. !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
  13816. memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
  13817. memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
  13818. }
  13819. /* Finally just fetch it out of the MAC control regs. */
  13820. else {
  13821. hi = tr32(MAC_ADDR_0_HIGH);
  13822. lo = tr32(MAC_ADDR_0_LOW);
  13823. dev->dev_addr[5] = lo & 0xff;
  13824. dev->dev_addr[4] = (lo >> 8) & 0xff;
  13825. dev->dev_addr[3] = (lo >> 16) & 0xff;
  13826. dev->dev_addr[2] = (lo >> 24) & 0xff;
  13827. dev->dev_addr[1] = hi & 0xff;
  13828. dev->dev_addr[0] = (hi >> 8) & 0xff;
  13829. }
  13830. }
  13831. if (!is_valid_ether_addr(&dev->dev_addr[0])) {
  13832. #ifdef CONFIG_SPARC
  13833. if (!tg3_get_default_macaddr_sparc(tp))
  13834. return 0;
  13835. #endif
  13836. return -EINVAL;
  13837. }
  13838. return 0;
  13839. }
  13840. #define BOUNDARY_SINGLE_CACHELINE 1
  13841. #define BOUNDARY_MULTI_CACHELINE 2
  13842. static u32 tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
  13843. {
  13844. int cacheline_size;
  13845. u8 byte;
  13846. int goal;
  13847. pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
  13848. if (byte == 0)
  13849. cacheline_size = 1024;
  13850. else
  13851. cacheline_size = (int) byte * 4;
  13852. /* On 5703 and later chips, the boundary bits have no
  13853. * effect.
  13854. */
  13855. if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
  13856. tg3_asic_rev(tp) != ASIC_REV_5701 &&
  13857. !tg3_flag(tp, PCI_EXPRESS))
  13858. goto out;
  13859. #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
  13860. goal = BOUNDARY_MULTI_CACHELINE;
  13861. #else
  13862. #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
  13863. goal = BOUNDARY_SINGLE_CACHELINE;
  13864. #else
  13865. goal = 0;
  13866. #endif
  13867. #endif
  13868. if (tg3_flag(tp, 57765_PLUS)) {
  13869. val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
  13870. goto out;
  13871. }
  13872. if (!goal)
  13873. goto out;
  13874. /* PCI controllers on most RISC systems tend to disconnect
  13875. * when a device tries to burst across a cache-line boundary.
  13876. * Therefore, letting tg3 do so just wastes PCI bandwidth.
  13877. *
  13878. * Unfortunately, for PCI-E there are only limited
  13879. * write-side controls for this, and thus for reads
  13880. * we will still get the disconnects. We'll also waste
  13881. * these PCI cycles for both read and write for chips
  13882. * other than 5700 and 5701 which do not implement the
  13883. * boundary bits.
  13884. */
  13885. if (tg3_flag(tp, PCIX_MODE) && !tg3_flag(tp, PCI_EXPRESS)) {
  13886. switch (cacheline_size) {
  13887. case 16:
  13888. case 32:
  13889. case 64:
  13890. case 128:
  13891. if (goal == BOUNDARY_SINGLE_CACHELINE) {
  13892. val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
  13893. DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
  13894. } else {
  13895. val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
  13896. DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
  13897. }
  13898. break;
  13899. case 256:
  13900. val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
  13901. DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
  13902. break;
  13903. default:
  13904. val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
  13905. DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
  13906. break;
  13907. }
  13908. } else if (tg3_flag(tp, PCI_EXPRESS)) {
  13909. switch (cacheline_size) {
  13910. case 16:
  13911. case 32:
  13912. case 64:
  13913. if (goal == BOUNDARY_SINGLE_CACHELINE) {
  13914. val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
  13915. val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
  13916. break;
  13917. }
  13918. /* fallthrough */
  13919. case 128:
  13920. default:
  13921. val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
  13922. val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
  13923. break;
  13924. }
  13925. } else {
  13926. switch (cacheline_size) {
  13927. case 16:
  13928. if (goal == BOUNDARY_SINGLE_CACHELINE) {
  13929. val |= (DMA_RWCTRL_READ_BNDRY_16 |
  13930. DMA_RWCTRL_WRITE_BNDRY_16);
  13931. break;
  13932. }
  13933. /* fallthrough */
  13934. case 32:
  13935. if (goal == BOUNDARY_SINGLE_CACHELINE) {
  13936. val |= (DMA_RWCTRL_READ_BNDRY_32 |
  13937. DMA_RWCTRL_WRITE_BNDRY_32);
  13938. break;
  13939. }
  13940. /* fallthrough */
  13941. case 64:
  13942. if (goal == BOUNDARY_SINGLE_CACHELINE) {
  13943. val |= (DMA_RWCTRL_READ_BNDRY_64 |
  13944. DMA_RWCTRL_WRITE_BNDRY_64);
  13945. break;
  13946. }
  13947. /* fallthrough */
  13948. case 128:
  13949. if (goal == BOUNDARY_SINGLE_CACHELINE) {
  13950. val |= (DMA_RWCTRL_READ_BNDRY_128 |
  13951. DMA_RWCTRL_WRITE_BNDRY_128);
  13952. break;
  13953. }
  13954. /* fallthrough */
  13955. case 256:
  13956. val |= (DMA_RWCTRL_READ_BNDRY_256 |
  13957. DMA_RWCTRL_WRITE_BNDRY_256);
  13958. break;
  13959. case 512:
  13960. val |= (DMA_RWCTRL_READ_BNDRY_512 |
  13961. DMA_RWCTRL_WRITE_BNDRY_512);
  13962. break;
  13963. case 1024:
  13964. default:
  13965. val |= (DMA_RWCTRL_READ_BNDRY_1024 |
  13966. DMA_RWCTRL_WRITE_BNDRY_1024);
  13967. break;
  13968. }
  13969. }
  13970. out:
  13971. return val;
  13972. }
  13973. static int tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma,
  13974. int size, bool to_device)
  13975. {
  13976. struct tg3_internal_buffer_desc test_desc;
  13977. u32 sram_dma_descs;
  13978. int i, ret;
  13979. sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
  13980. tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
  13981. tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
  13982. tw32(RDMAC_STATUS, 0);
  13983. tw32(WDMAC_STATUS, 0);
  13984. tw32(BUFMGR_MODE, 0);
  13985. tw32(FTQ_RESET, 0);
  13986. test_desc.addr_hi = ((u64) buf_dma) >> 32;
  13987. test_desc.addr_lo = buf_dma & 0xffffffff;
  13988. test_desc.nic_mbuf = 0x00002100;
  13989. test_desc.len = size;
  13990. /*
  13991. * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
  13992. * the *second* time the tg3 driver was getting loaded after an
  13993. * initial scan.
  13994. *
  13995. * Broadcom tells me:
  13996. * ...the DMA engine is connected to the GRC block and a DMA
  13997. * reset may affect the GRC block in some unpredictable way...
  13998. * The behavior of resets to individual blocks has not been tested.
  13999. *
  14000. * Broadcom noted the GRC reset will also reset all sub-components.
  14001. */
  14002. if (to_device) {
  14003. test_desc.cqid_sqid = (13 << 8) | 2;
  14004. tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
  14005. udelay(40);
  14006. } else {
  14007. test_desc.cqid_sqid = (16 << 8) | 7;
  14008. tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
  14009. udelay(40);
  14010. }
  14011. test_desc.flags = 0x00000005;
  14012. for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
  14013. u32 val;
  14014. val = *(((u32 *)&test_desc) + i);
  14015. pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
  14016. sram_dma_descs + (i * sizeof(u32)));
  14017. pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
  14018. }
  14019. pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
  14020. if (to_device)
  14021. tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
  14022. else
  14023. tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
  14024. ret = -ENODEV;
  14025. for (i = 0; i < 40; i++) {
  14026. u32 val;
  14027. if (to_device)
  14028. val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
  14029. else
  14030. val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
  14031. if ((val & 0xffff) == sram_dma_descs) {
  14032. ret = 0;
  14033. break;
  14034. }
  14035. udelay(100);
  14036. }
  14037. return ret;
  14038. }
  14039. #define TEST_BUFFER_SIZE 0x2000
  14040. static DEFINE_PCI_DEVICE_TABLE(tg3_dma_wait_state_chipsets) = {
  14041. { PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
  14042. { },
  14043. };
  14044. static int tg3_test_dma(struct tg3 *tp)
  14045. {
  14046. dma_addr_t buf_dma;
  14047. u32 *buf, saved_dma_rwctrl;
  14048. int ret = 0;
  14049. buf = dma_alloc_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE,
  14050. &buf_dma, GFP_KERNEL);
  14051. if (!buf) {
  14052. ret = -ENOMEM;
  14053. goto out_nofree;
  14054. }
  14055. tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
  14056. (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
  14057. tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
  14058. if (tg3_flag(tp, 57765_PLUS))
  14059. goto out;
  14060. if (tg3_flag(tp, PCI_EXPRESS)) {
  14061. /* DMA read watermark not used on PCIE */
  14062. tp->dma_rwctrl |= 0x00180000;
  14063. } else if (!tg3_flag(tp, PCIX_MODE)) {
  14064. if (tg3_asic_rev(tp) == ASIC_REV_5705 ||
  14065. tg3_asic_rev(tp) == ASIC_REV_5750)
  14066. tp->dma_rwctrl |= 0x003f0000;
  14067. else
  14068. tp->dma_rwctrl |= 0x003f000f;
  14069. } else {
  14070. if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
  14071. tg3_asic_rev(tp) == ASIC_REV_5704) {
  14072. u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
  14073. u32 read_water = 0x7;
  14074. /* If the 5704 is behind the EPB bridge, we can
  14075. * do the less restrictive ONE_DMA workaround for
  14076. * better performance.
  14077. */
  14078. if (tg3_flag(tp, 40BIT_DMA_BUG) &&
  14079. tg3_asic_rev(tp) == ASIC_REV_5704)
  14080. tp->dma_rwctrl |= 0x8000;
  14081. else if (ccval == 0x6 || ccval == 0x7)
  14082. tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
  14083. if (tg3_asic_rev(tp) == ASIC_REV_5703)
  14084. read_water = 4;
  14085. /* Set bit 23 to enable PCIX hw bug fix */
  14086. tp->dma_rwctrl |=
  14087. (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
  14088. (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
  14089. (1 << 23);
  14090. } else if (tg3_asic_rev(tp) == ASIC_REV_5780) {
  14091. /* 5780 always in PCIX mode */
  14092. tp->dma_rwctrl |= 0x00144000;
  14093. } else if (tg3_asic_rev(tp) == ASIC_REV_5714) {
  14094. /* 5714 always in PCIX mode */
  14095. tp->dma_rwctrl |= 0x00148000;
  14096. } else {
  14097. tp->dma_rwctrl |= 0x001b000f;
  14098. }
  14099. }
  14100. if (tg3_flag(tp, ONE_DMA_AT_ONCE))
  14101. tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
  14102. if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
  14103. tg3_asic_rev(tp) == ASIC_REV_5704)
  14104. tp->dma_rwctrl &= 0xfffffff0;
  14105. if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
  14106. tg3_asic_rev(tp) == ASIC_REV_5701) {
  14107. /* Remove this if it causes problems for some boards. */
  14108. tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
  14109. /* On 5700/5701 chips, we need to set this bit.
  14110. * Otherwise the chip will issue cacheline transactions
  14111. * to streamable DMA memory with not all the byte
  14112. * enables turned on. This is an error on several
  14113. * RISC PCI controllers, in particular sparc64.
  14114. *
  14115. * On 5703/5704 chips, this bit has been reassigned
  14116. * a different meaning. In particular, it is used
  14117. * on those chips to enable a PCI-X workaround.
  14118. */
  14119. tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
  14120. }
  14121. tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
  14122. #if 0
  14123. /* Unneeded, already done by tg3_get_invariants. */
  14124. tg3_switch_clocks(tp);
  14125. #endif
  14126. if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
  14127. tg3_asic_rev(tp) != ASIC_REV_5701)
  14128. goto out;
  14129. /* It is best to perform DMA test with maximum write burst size
  14130. * to expose the 5700/5701 write DMA bug.
  14131. */
  14132. saved_dma_rwctrl = tp->dma_rwctrl;
  14133. tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
  14134. tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
  14135. while (1) {
  14136. u32 *p = buf, i;
  14137. for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
  14138. p[i] = i;
  14139. /* Send the buffer to the chip. */
  14140. ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, true);
  14141. if (ret) {
  14142. dev_err(&tp->pdev->dev,
  14143. "%s: Buffer write failed. err = %d\n",
  14144. __func__, ret);
  14145. break;
  14146. }
  14147. #if 0
  14148. /* validate data reached card RAM correctly. */
  14149. for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
  14150. u32 val;
  14151. tg3_read_mem(tp, 0x2100 + (i*4), &val);
  14152. if (le32_to_cpu(val) != p[i]) {
  14153. dev_err(&tp->pdev->dev,
  14154. "%s: Buffer corrupted on device! "
  14155. "(%d != %d)\n", __func__, val, i);
  14156. /* ret = -ENODEV here? */
  14157. }
  14158. p[i] = 0;
  14159. }
  14160. #endif
  14161. /* Now read it back. */
  14162. ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, false);
  14163. if (ret) {
  14164. dev_err(&tp->pdev->dev, "%s: Buffer read failed. "
  14165. "err = %d\n", __func__, ret);
  14166. break;
  14167. }
  14168. /* Verify it. */
  14169. for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
  14170. if (p[i] == i)
  14171. continue;
  14172. if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
  14173. DMA_RWCTRL_WRITE_BNDRY_16) {
  14174. tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
  14175. tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
  14176. tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
  14177. break;
  14178. } else {
  14179. dev_err(&tp->pdev->dev,
  14180. "%s: Buffer corrupted on read back! "
  14181. "(%d != %d)\n", __func__, p[i], i);
  14182. ret = -ENODEV;
  14183. goto out;
  14184. }
  14185. }
  14186. if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
  14187. /* Success. */
  14188. ret = 0;
  14189. break;
  14190. }
  14191. }
  14192. if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
  14193. DMA_RWCTRL_WRITE_BNDRY_16) {
  14194. /* DMA test passed without adjusting DMA boundary,
  14195. * now look for chipsets that are known to expose the
  14196. * DMA bug without failing the test.
  14197. */
  14198. if (pci_dev_present(tg3_dma_wait_state_chipsets)) {
  14199. tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
  14200. tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
  14201. } else {
  14202. /* Safe to use the calculated DMA boundary. */
  14203. tp->dma_rwctrl = saved_dma_rwctrl;
  14204. }
  14205. tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
  14206. }
  14207. out:
  14208. dma_free_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, buf, buf_dma);
  14209. out_nofree:
  14210. return ret;
  14211. }
  14212. static void tg3_init_bufmgr_config(struct tg3 *tp)
  14213. {
  14214. if (tg3_flag(tp, 57765_PLUS)) {
  14215. tp->bufmgr_config.mbuf_read_dma_low_water =
  14216. DEFAULT_MB_RDMA_LOW_WATER_5705;
  14217. tp->bufmgr_config.mbuf_mac_rx_low_water =
  14218. DEFAULT_MB_MACRX_LOW_WATER_57765;
  14219. tp->bufmgr_config.mbuf_high_water =
  14220. DEFAULT_MB_HIGH_WATER_57765;
  14221. tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
  14222. DEFAULT_MB_RDMA_LOW_WATER_5705;
  14223. tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
  14224. DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
  14225. tp->bufmgr_config.mbuf_high_water_jumbo =
  14226. DEFAULT_MB_HIGH_WATER_JUMBO_57765;
  14227. } else if (tg3_flag(tp, 5705_PLUS)) {
  14228. tp->bufmgr_config.mbuf_read_dma_low_water =
  14229. DEFAULT_MB_RDMA_LOW_WATER_5705;
  14230. tp->bufmgr_config.mbuf_mac_rx_low_water =
  14231. DEFAULT_MB_MACRX_LOW_WATER_5705;
  14232. tp->bufmgr_config.mbuf_high_water =
  14233. DEFAULT_MB_HIGH_WATER_5705;
  14234. if (tg3_asic_rev(tp) == ASIC_REV_5906) {
  14235. tp->bufmgr_config.mbuf_mac_rx_low_water =
  14236. DEFAULT_MB_MACRX_LOW_WATER_5906;
  14237. tp->bufmgr_config.mbuf_high_water =
  14238. DEFAULT_MB_HIGH_WATER_5906;
  14239. }
  14240. tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
  14241. DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
  14242. tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
  14243. DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
  14244. tp->bufmgr_config.mbuf_high_water_jumbo =
  14245. DEFAULT_MB_HIGH_WATER_JUMBO_5780;
  14246. } else {
  14247. tp->bufmgr_config.mbuf_read_dma_low_water =
  14248. DEFAULT_MB_RDMA_LOW_WATER;
  14249. tp->bufmgr_config.mbuf_mac_rx_low_water =
  14250. DEFAULT_MB_MACRX_LOW_WATER;
  14251. tp->bufmgr_config.mbuf_high_water =
  14252. DEFAULT_MB_HIGH_WATER;
  14253. tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
  14254. DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
  14255. tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
  14256. DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
  14257. tp->bufmgr_config.mbuf_high_water_jumbo =
  14258. DEFAULT_MB_HIGH_WATER_JUMBO;
  14259. }
  14260. tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
  14261. tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
  14262. }
  14263. static char *tg3_phy_string(struct tg3 *tp)
  14264. {
  14265. switch (tp->phy_id & TG3_PHY_ID_MASK) {
  14266. case TG3_PHY_ID_BCM5400: return "5400";
  14267. case TG3_PHY_ID_BCM5401: return "5401";
  14268. case TG3_PHY_ID_BCM5411: return "5411";
  14269. case TG3_PHY_ID_BCM5701: return "5701";
  14270. case TG3_PHY_ID_BCM5703: return "5703";
  14271. case TG3_PHY_ID_BCM5704: return "5704";
  14272. case TG3_PHY_ID_BCM5705: return "5705";
  14273. case TG3_PHY_ID_BCM5750: return "5750";
  14274. case TG3_PHY_ID_BCM5752: return "5752";
  14275. case TG3_PHY_ID_BCM5714: return "5714";
  14276. case TG3_PHY_ID_BCM5780: return "5780";
  14277. case TG3_PHY_ID_BCM5755: return "5755";
  14278. case TG3_PHY_ID_BCM5787: return "5787";
  14279. case TG3_PHY_ID_BCM5784: return "5784";
  14280. case TG3_PHY_ID_BCM5756: return "5722/5756";
  14281. case TG3_PHY_ID_BCM5906: return "5906";
  14282. case TG3_PHY_ID_BCM5761: return "5761";
  14283. case TG3_PHY_ID_BCM5718C: return "5718C";
  14284. case TG3_PHY_ID_BCM5718S: return "5718S";
  14285. case TG3_PHY_ID_BCM57765: return "57765";
  14286. case TG3_PHY_ID_BCM5719C: return "5719C";
  14287. case TG3_PHY_ID_BCM5720C: return "5720C";
  14288. case TG3_PHY_ID_BCM5762: return "5762C";
  14289. case TG3_PHY_ID_BCM8002: return "8002/serdes";
  14290. case 0: return "serdes";
  14291. default: return "unknown";
  14292. }
  14293. }
  14294. static char *tg3_bus_string(struct tg3 *tp, char *str)
  14295. {
  14296. if (tg3_flag(tp, PCI_EXPRESS)) {
  14297. strcpy(str, "PCI Express");
  14298. return str;
  14299. } else if (tg3_flag(tp, PCIX_MODE)) {
  14300. u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
  14301. strcpy(str, "PCIX:");
  14302. if ((clock_ctrl == 7) ||
  14303. ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
  14304. GRC_MISC_CFG_BOARD_ID_5704CIOBE))
  14305. strcat(str, "133MHz");
  14306. else if (clock_ctrl == 0)
  14307. strcat(str, "33MHz");
  14308. else if (clock_ctrl == 2)
  14309. strcat(str, "50MHz");
  14310. else if (clock_ctrl == 4)
  14311. strcat(str, "66MHz");
  14312. else if (clock_ctrl == 6)
  14313. strcat(str, "100MHz");
  14314. } else {
  14315. strcpy(str, "PCI:");
  14316. if (tg3_flag(tp, PCI_HIGH_SPEED))
  14317. strcat(str, "66MHz");
  14318. else
  14319. strcat(str, "33MHz");
  14320. }
  14321. if (tg3_flag(tp, PCI_32BIT))
  14322. strcat(str, ":32-bit");
  14323. else
  14324. strcat(str, ":64-bit");
  14325. return str;
  14326. }
  14327. static void tg3_init_coal(struct tg3 *tp)
  14328. {
  14329. struct ethtool_coalesce *ec = &tp->coal;
  14330. memset(ec, 0, sizeof(*ec));
  14331. ec->cmd = ETHTOOL_GCOALESCE;
  14332. ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
  14333. ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
  14334. ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
  14335. ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
  14336. ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
  14337. ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
  14338. ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
  14339. ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
  14340. ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
  14341. if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
  14342. HOSTCC_MODE_CLRTICK_TXBD)) {
  14343. ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
  14344. ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
  14345. ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
  14346. ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
  14347. }
  14348. if (tg3_flag(tp, 5705_PLUS)) {
  14349. ec->rx_coalesce_usecs_irq = 0;
  14350. ec->tx_coalesce_usecs_irq = 0;
  14351. ec->stats_block_coalesce_usecs = 0;
  14352. }
  14353. }
  14354. static int tg3_init_one(struct pci_dev *pdev,
  14355. const struct pci_device_id *ent)
  14356. {
  14357. struct net_device *dev;
  14358. struct tg3 *tp;
  14359. int i, err;
  14360. u32 sndmbx, rcvmbx, intmbx;
  14361. char str[40];
  14362. u64 dma_mask, persist_dma_mask;
  14363. netdev_features_t features = 0;
  14364. printk_once(KERN_INFO "%s\n", version);
  14365. err = pci_enable_device(pdev);
  14366. if (err) {
  14367. dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
  14368. return err;
  14369. }
  14370. err = pci_request_regions(pdev, DRV_MODULE_NAME);
  14371. if (err) {
  14372. dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
  14373. goto err_out_disable_pdev;
  14374. }
  14375. pci_set_master(pdev);
  14376. dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
  14377. if (!dev) {
  14378. err = -ENOMEM;
  14379. goto err_out_free_res;
  14380. }
  14381. SET_NETDEV_DEV(dev, &pdev->dev);
  14382. tp = netdev_priv(dev);
  14383. tp->pdev = pdev;
  14384. tp->dev = dev;
  14385. tp->pm_cap = pdev->pm_cap;
  14386. tp->rx_mode = TG3_DEF_RX_MODE;
  14387. tp->tx_mode = TG3_DEF_TX_MODE;
  14388. tp->irq_sync = 1;
  14389. if (tg3_debug > 0)
  14390. tp->msg_enable = tg3_debug;
  14391. else
  14392. tp->msg_enable = TG3_DEF_MSG_ENABLE;
  14393. if (pdev_is_ssb_gige_core(pdev)) {
  14394. tg3_flag_set(tp, IS_SSB_CORE);
  14395. if (ssb_gige_must_flush_posted_writes(pdev))
  14396. tg3_flag_set(tp, FLUSH_POSTED_WRITES);
  14397. if (ssb_gige_one_dma_at_once(pdev))
  14398. tg3_flag_set(tp, ONE_DMA_AT_ONCE);
  14399. if (ssb_gige_have_roboswitch(pdev))
  14400. tg3_flag_set(tp, ROBOSWITCH);
  14401. if (ssb_gige_is_rgmii(pdev))
  14402. tg3_flag_set(tp, RGMII_MODE);
  14403. }
  14404. /* The word/byte swap controls here control register access byte
  14405. * swapping. DMA data byte swapping is controlled in the GRC_MODE
  14406. * setting below.
  14407. */
  14408. tp->misc_host_ctrl =
  14409. MISC_HOST_CTRL_MASK_PCI_INT |
  14410. MISC_HOST_CTRL_WORD_SWAP |
  14411. MISC_HOST_CTRL_INDIR_ACCESS |
  14412. MISC_HOST_CTRL_PCISTATE_RW;
  14413. /* The NONFRM (non-frame) byte/word swap controls take effect
  14414. * on descriptor entries, anything which isn't packet data.
  14415. *
  14416. * The StrongARM chips on the board (one for tx, one for rx)
  14417. * are running in big-endian mode.
  14418. */
  14419. tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
  14420. GRC_MODE_WSWAP_NONFRM_DATA);
  14421. #ifdef __BIG_ENDIAN
  14422. tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
  14423. #endif
  14424. spin_lock_init(&tp->lock);
  14425. spin_lock_init(&tp->indirect_lock);
  14426. INIT_WORK(&tp->reset_task, tg3_reset_task);
  14427. tp->regs = pci_ioremap_bar(pdev, BAR_0);
  14428. if (!tp->regs) {
  14429. dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
  14430. err = -ENOMEM;
  14431. goto err_out_free_dev;
  14432. }
  14433. if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
  14434. tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761E ||
  14435. tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S ||
  14436. tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761SE ||
  14437. tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
  14438. tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C ||
  14439. tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
  14440. tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||
  14441. tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720 ||
  14442. tp->pdev->device == TG3PCI_DEVICE_TIGON3_5762 ||
  14443. tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725 ||
  14444. tp->pdev->device == TG3PCI_DEVICE_TIGON3_5727) {
  14445. tg3_flag_set(tp, ENABLE_APE);
  14446. tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
  14447. if (!tp->aperegs) {
  14448. dev_err(&pdev->dev,
  14449. "Cannot map APE registers, aborting\n");
  14450. err = -ENOMEM;
  14451. goto err_out_iounmap;
  14452. }
  14453. }
  14454. tp->rx_pending = TG3_DEF_RX_RING_PENDING;
  14455. tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
  14456. dev->ethtool_ops = &tg3_ethtool_ops;
  14457. dev->watchdog_timeo = TG3_TX_TIMEOUT;
  14458. dev->netdev_ops = &tg3_netdev_ops;
  14459. dev->irq = pdev->irq;
  14460. err = tg3_get_invariants(tp, ent);
  14461. if (err) {
  14462. dev_err(&pdev->dev,
  14463. "Problem fetching invariants of chip, aborting\n");
  14464. goto err_out_apeunmap;
  14465. }
  14466. /* The EPB bridge inside 5714, 5715, and 5780 and any
  14467. * device behind the EPB cannot support DMA addresses > 40-bit.
  14468. * On 64-bit systems with IOMMU, use 40-bit dma_mask.
  14469. * On 64-bit systems without IOMMU, use 64-bit dma_mask and
  14470. * do DMA address check in tg3_start_xmit().
  14471. */
  14472. if (tg3_flag(tp, IS_5788))
  14473. persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
  14474. else if (tg3_flag(tp, 40BIT_DMA_BUG)) {
  14475. persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
  14476. #ifdef CONFIG_HIGHMEM
  14477. dma_mask = DMA_BIT_MASK(64);
  14478. #endif
  14479. } else
  14480. persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
  14481. /* Configure DMA attributes. */
  14482. if (dma_mask > DMA_BIT_MASK(32)) {
  14483. err = pci_set_dma_mask(pdev, dma_mask);
  14484. if (!err) {
  14485. features |= NETIF_F_HIGHDMA;
  14486. err = pci_set_consistent_dma_mask(pdev,
  14487. persist_dma_mask);
  14488. if (err < 0) {
  14489. dev_err(&pdev->dev, "Unable to obtain 64 bit "
  14490. "DMA for consistent allocations\n");
  14491. goto err_out_apeunmap;
  14492. }
  14493. }
  14494. }
  14495. if (err || dma_mask == DMA_BIT_MASK(32)) {
  14496. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  14497. if (err) {
  14498. dev_err(&pdev->dev,
  14499. "No usable DMA configuration, aborting\n");
  14500. goto err_out_apeunmap;
  14501. }
  14502. }
  14503. tg3_init_bufmgr_config(tp);
  14504. features |= NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
  14505. /* 5700 B0 chips do not support checksumming correctly due
  14506. * to hardware bugs.
  14507. */
  14508. if (tg3_chip_rev_id(tp) != CHIPREV_ID_5700_B0) {
  14509. features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_RXCSUM;
  14510. if (tg3_flag(tp, 5755_PLUS))
  14511. features |= NETIF_F_IPV6_CSUM;
  14512. }
  14513. /* TSO is on by default on chips that support hardware TSO.
  14514. * Firmware TSO on older chips gives lower performance, so it
  14515. * is off by default, but can be enabled using ethtool.
  14516. */
  14517. if ((tg3_flag(tp, HW_TSO_1) ||
  14518. tg3_flag(tp, HW_TSO_2) ||
  14519. tg3_flag(tp, HW_TSO_3)) &&
  14520. (features & NETIF_F_IP_CSUM))
  14521. features |= NETIF_F_TSO;
  14522. if (tg3_flag(tp, HW_TSO_2) || tg3_flag(tp, HW_TSO_3)) {
  14523. if (features & NETIF_F_IPV6_CSUM)
  14524. features |= NETIF_F_TSO6;
  14525. if (tg3_flag(tp, HW_TSO_3) ||
  14526. tg3_asic_rev(tp) == ASIC_REV_5761 ||
  14527. (tg3_asic_rev(tp) == ASIC_REV_5784 &&
  14528. tg3_chip_rev(tp) != CHIPREV_5784_AX) ||
  14529. tg3_asic_rev(tp) == ASIC_REV_5785 ||
  14530. tg3_asic_rev(tp) == ASIC_REV_57780)
  14531. features |= NETIF_F_TSO_ECN;
  14532. }
  14533. dev->features |= features;
  14534. dev->vlan_features |= features;
  14535. /*
  14536. * Add loopback capability only for a subset of devices that support
  14537. * MAC-LOOPBACK. Eventually this need to be enhanced to allow INT-PHY
  14538. * loopback for the remaining devices.
  14539. */
  14540. if (tg3_asic_rev(tp) != ASIC_REV_5780 &&
  14541. !tg3_flag(tp, CPMU_PRESENT))
  14542. /* Add the loopback capability */
  14543. features |= NETIF_F_LOOPBACK;
  14544. dev->hw_features |= features;
  14545. if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A1 &&
  14546. !tg3_flag(tp, TSO_CAPABLE) &&
  14547. !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
  14548. tg3_flag_set(tp, MAX_RXPEND_64);
  14549. tp->rx_pending = 63;
  14550. }
  14551. err = tg3_get_device_address(tp);
  14552. if (err) {
  14553. dev_err(&pdev->dev,
  14554. "Could not obtain valid ethernet address, aborting\n");
  14555. goto err_out_apeunmap;
  14556. }
  14557. /*
  14558. * Reset chip in case UNDI or EFI driver did not shutdown
  14559. * DMA self test will enable WDMAC and we'll see (spurious)
  14560. * pending DMA on the PCI bus at that point.
  14561. */
  14562. if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
  14563. (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
  14564. tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
  14565. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  14566. }
  14567. err = tg3_test_dma(tp);
  14568. if (err) {
  14569. dev_err(&pdev->dev, "DMA engine test failed, aborting\n");
  14570. goto err_out_apeunmap;
  14571. }
  14572. intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
  14573. rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
  14574. sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
  14575. for (i = 0; i < tp->irq_max; i++) {
  14576. struct tg3_napi *tnapi = &tp->napi[i];
  14577. tnapi->tp = tp;
  14578. tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
  14579. tnapi->int_mbox = intmbx;
  14580. if (i <= 4)
  14581. intmbx += 0x8;
  14582. else
  14583. intmbx += 0x4;
  14584. tnapi->consmbox = rcvmbx;
  14585. tnapi->prodmbox = sndmbx;
  14586. if (i)
  14587. tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
  14588. else
  14589. tnapi->coal_now = HOSTCC_MODE_NOW;
  14590. if (!tg3_flag(tp, SUPPORT_MSIX))
  14591. break;
  14592. /*
  14593. * If we support MSIX, we'll be using RSS. If we're using
  14594. * RSS, the first vector only handles link interrupts and the
  14595. * remaining vectors handle rx and tx interrupts. Reuse the
  14596. * mailbox values for the next iteration. The values we setup
  14597. * above are still useful for the single vectored mode.
  14598. */
  14599. if (!i)
  14600. continue;
  14601. rcvmbx += 0x8;
  14602. if (sndmbx & 0x4)
  14603. sndmbx -= 0x4;
  14604. else
  14605. sndmbx += 0xc;
  14606. }
  14607. tg3_init_coal(tp);
  14608. pci_set_drvdata(pdev, dev);
  14609. if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
  14610. tg3_asic_rev(tp) == ASIC_REV_5720 ||
  14611. tg3_asic_rev(tp) == ASIC_REV_5762)
  14612. tg3_flag_set(tp, PTP_CAPABLE);
  14613. tg3_timer_init(tp);
  14614. tg3_carrier_off(tp);
  14615. err = register_netdev(dev);
  14616. if (err) {
  14617. dev_err(&pdev->dev, "Cannot register net device, aborting\n");
  14618. goto err_out_apeunmap;
  14619. }
  14620. netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
  14621. tp->board_part_number,
  14622. tg3_chip_rev_id(tp),
  14623. tg3_bus_string(tp, str),
  14624. dev->dev_addr);
  14625. if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
  14626. struct phy_device *phydev;
  14627. phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
  14628. netdev_info(dev,
  14629. "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
  14630. phydev->drv->name, dev_name(&phydev->dev));
  14631. } else {
  14632. char *ethtype;
  14633. if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
  14634. ethtype = "10/100Base-TX";
  14635. else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
  14636. ethtype = "1000Base-SX";
  14637. else
  14638. ethtype = "10/100/1000Base-T";
  14639. netdev_info(dev, "attached PHY is %s (%s Ethernet) "
  14640. "(WireSpeed[%d], EEE[%d])\n",
  14641. tg3_phy_string(tp), ethtype,
  14642. (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0,
  14643. (tp->phy_flags & TG3_PHYFLG_EEE_CAP) != 0);
  14644. }
  14645. netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
  14646. (dev->features & NETIF_F_RXCSUM) != 0,
  14647. tg3_flag(tp, USE_LINKCHG_REG) != 0,
  14648. (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0,
  14649. tg3_flag(tp, ENABLE_ASF) != 0,
  14650. tg3_flag(tp, TSO_CAPABLE) != 0);
  14651. netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n",
  14652. tp->dma_rwctrl,
  14653. pdev->dma_mask == DMA_BIT_MASK(32) ? 32 :
  14654. ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64);
  14655. pci_save_state(pdev);
  14656. return 0;
  14657. err_out_apeunmap:
  14658. if (tp->aperegs) {
  14659. iounmap(tp->aperegs);
  14660. tp->aperegs = NULL;
  14661. }
  14662. err_out_iounmap:
  14663. if (tp->regs) {
  14664. iounmap(tp->regs);
  14665. tp->regs = NULL;
  14666. }
  14667. err_out_free_dev:
  14668. free_netdev(dev);
  14669. err_out_free_res:
  14670. pci_release_regions(pdev);
  14671. err_out_disable_pdev:
  14672. if (pci_is_enabled(pdev))
  14673. pci_disable_device(pdev);
  14674. pci_set_drvdata(pdev, NULL);
  14675. return err;
  14676. }
  14677. static void tg3_remove_one(struct pci_dev *pdev)
  14678. {
  14679. struct net_device *dev = pci_get_drvdata(pdev);
  14680. if (dev) {
  14681. struct tg3 *tp = netdev_priv(dev);
  14682. release_firmware(tp->fw);
  14683. tg3_reset_task_cancel(tp);
  14684. if (tg3_flag(tp, USE_PHYLIB)) {
  14685. tg3_phy_fini(tp);
  14686. tg3_mdio_fini(tp);
  14687. }
  14688. unregister_netdev(dev);
  14689. if (tp->aperegs) {
  14690. iounmap(tp->aperegs);
  14691. tp->aperegs = NULL;
  14692. }
  14693. if (tp->regs) {
  14694. iounmap(tp->regs);
  14695. tp->regs = NULL;
  14696. }
  14697. free_netdev(dev);
  14698. pci_release_regions(pdev);
  14699. pci_disable_device(pdev);
  14700. pci_set_drvdata(pdev, NULL);
  14701. }
  14702. }
  14703. #ifdef CONFIG_PM_SLEEP
  14704. static int tg3_suspend(struct device *device)
  14705. {
  14706. struct pci_dev *pdev = to_pci_dev(device);
  14707. struct net_device *dev = pci_get_drvdata(pdev);
  14708. struct tg3 *tp = netdev_priv(dev);
  14709. int err;
  14710. if (!netif_running(dev))
  14711. return 0;
  14712. tg3_reset_task_cancel(tp);
  14713. tg3_phy_stop(tp);
  14714. tg3_netif_stop(tp);
  14715. tg3_timer_stop(tp);
  14716. tg3_full_lock(tp, 1);
  14717. tg3_disable_ints(tp);
  14718. tg3_full_unlock(tp);
  14719. netif_device_detach(dev);
  14720. tg3_full_lock(tp, 0);
  14721. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  14722. tg3_flag_clear(tp, INIT_COMPLETE);
  14723. tg3_full_unlock(tp);
  14724. err = tg3_power_down_prepare(tp);
  14725. if (err) {
  14726. int err2;
  14727. tg3_full_lock(tp, 0);
  14728. tg3_flag_set(tp, INIT_COMPLETE);
  14729. err2 = tg3_restart_hw(tp, true);
  14730. if (err2)
  14731. goto out;
  14732. tg3_timer_start(tp);
  14733. netif_device_attach(dev);
  14734. tg3_netif_start(tp);
  14735. out:
  14736. tg3_full_unlock(tp);
  14737. if (!err2)
  14738. tg3_phy_start(tp);
  14739. }
  14740. return err;
  14741. }
  14742. static int tg3_resume(struct device *device)
  14743. {
  14744. struct pci_dev *pdev = to_pci_dev(device);
  14745. struct net_device *dev = pci_get_drvdata(pdev);
  14746. struct tg3 *tp = netdev_priv(dev);
  14747. int err;
  14748. if (!netif_running(dev))
  14749. return 0;
  14750. netif_device_attach(dev);
  14751. tg3_full_lock(tp, 0);
  14752. tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
  14753. tg3_flag_set(tp, INIT_COMPLETE);
  14754. err = tg3_restart_hw(tp,
  14755. !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN));
  14756. if (err)
  14757. goto out;
  14758. tg3_timer_start(tp);
  14759. tg3_netif_start(tp);
  14760. out:
  14761. tg3_full_unlock(tp);
  14762. if (!err)
  14763. tg3_phy_start(tp);
  14764. return err;
  14765. }
  14766. #endif /* CONFIG_PM_SLEEP */
  14767. static SIMPLE_DEV_PM_OPS(tg3_pm_ops, tg3_suspend, tg3_resume);
  14768. static void tg3_shutdown(struct pci_dev *pdev)
  14769. {
  14770. struct net_device *dev = pci_get_drvdata(pdev);
  14771. struct tg3 *tp = netdev_priv(dev);
  14772. rtnl_lock();
  14773. netif_device_detach(dev);
  14774. if (netif_running(dev))
  14775. dev_close(dev);
  14776. if (system_state == SYSTEM_POWER_OFF)
  14777. tg3_power_down(tp);
  14778. rtnl_unlock();
  14779. }
  14780. /**
  14781. * tg3_io_error_detected - called when PCI error is detected
  14782. * @pdev: Pointer to PCI device
  14783. * @state: The current pci connection state
  14784. *
  14785. * This function is called after a PCI bus error affecting
  14786. * this device has been detected.
  14787. */
  14788. static pci_ers_result_t tg3_io_error_detected(struct pci_dev *pdev,
  14789. pci_channel_state_t state)
  14790. {
  14791. struct net_device *netdev = pci_get_drvdata(pdev);
  14792. struct tg3 *tp = netdev_priv(netdev);
  14793. pci_ers_result_t err = PCI_ERS_RESULT_NEED_RESET;
  14794. netdev_info(netdev, "PCI I/O error detected\n");
  14795. rtnl_lock();
  14796. /* We probably don't have netdev yet */
  14797. if (!netdev || !netif_running(netdev))
  14798. goto done;
  14799. tg3_phy_stop(tp);
  14800. tg3_netif_stop(tp);
  14801. tg3_timer_stop(tp);
  14802. /* Want to make sure that the reset task doesn't run */
  14803. tg3_reset_task_cancel(tp);
  14804. netif_device_detach(netdev);
  14805. /* Clean up software state, even if MMIO is blocked */
  14806. tg3_full_lock(tp, 0);
  14807. tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
  14808. tg3_full_unlock(tp);
  14809. done:
  14810. if (state == pci_channel_io_perm_failure) {
  14811. if (netdev) {
  14812. tg3_napi_enable(tp);
  14813. dev_close(netdev);
  14814. }
  14815. err = PCI_ERS_RESULT_DISCONNECT;
  14816. } else {
  14817. pci_disable_device(pdev);
  14818. }
  14819. rtnl_unlock();
  14820. return err;
  14821. }
  14822. /**
  14823. * tg3_io_slot_reset - called after the pci bus has been reset.
  14824. * @pdev: Pointer to PCI device
  14825. *
  14826. * Restart the card from scratch, as if from a cold-boot.
  14827. * At this point, the card has exprienced a hard reset,
  14828. * followed by fixups by BIOS, and has its config space
  14829. * set up identically to what it was at cold boot.
  14830. */
  14831. static pci_ers_result_t tg3_io_slot_reset(struct pci_dev *pdev)
  14832. {
  14833. struct net_device *netdev = pci_get_drvdata(pdev);
  14834. struct tg3 *tp = netdev_priv(netdev);
  14835. pci_ers_result_t rc = PCI_ERS_RESULT_DISCONNECT;
  14836. int err;
  14837. rtnl_lock();
  14838. if (pci_enable_device(pdev)) {
  14839. dev_err(&pdev->dev,
  14840. "Cannot re-enable PCI device after reset.\n");
  14841. goto done;
  14842. }
  14843. pci_set_master(pdev);
  14844. pci_restore_state(pdev);
  14845. pci_save_state(pdev);
  14846. if (!netdev || !netif_running(netdev)) {
  14847. rc = PCI_ERS_RESULT_RECOVERED;
  14848. goto done;
  14849. }
  14850. err = tg3_power_up(tp);
  14851. if (err)
  14852. goto done;
  14853. rc = PCI_ERS_RESULT_RECOVERED;
  14854. done:
  14855. if (rc != PCI_ERS_RESULT_RECOVERED && netdev && netif_running(netdev)) {
  14856. tg3_napi_enable(tp);
  14857. dev_close(netdev);
  14858. }
  14859. rtnl_unlock();
  14860. return rc;
  14861. }
  14862. /**
  14863. * tg3_io_resume - called when traffic can start flowing again.
  14864. * @pdev: Pointer to PCI device
  14865. *
  14866. * This callback is called when the error recovery driver tells
  14867. * us that its OK to resume normal operation.
  14868. */
  14869. static void tg3_io_resume(struct pci_dev *pdev)
  14870. {
  14871. struct net_device *netdev = pci_get_drvdata(pdev);
  14872. struct tg3 *tp = netdev_priv(netdev);
  14873. int err;
  14874. rtnl_lock();
  14875. if (!netif_running(netdev))
  14876. goto done;
  14877. tg3_full_lock(tp, 0);
  14878. tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
  14879. tg3_flag_set(tp, INIT_COMPLETE);
  14880. err = tg3_restart_hw(tp, true);
  14881. if (err) {
  14882. tg3_full_unlock(tp);
  14883. netdev_err(netdev, "Cannot restart hardware after reset.\n");
  14884. goto done;
  14885. }
  14886. netif_device_attach(netdev);
  14887. tg3_timer_start(tp);
  14888. tg3_netif_start(tp);
  14889. tg3_full_unlock(tp);
  14890. tg3_phy_start(tp);
  14891. done:
  14892. rtnl_unlock();
  14893. }
  14894. static const struct pci_error_handlers tg3_err_handler = {
  14895. .error_detected = tg3_io_error_detected,
  14896. .slot_reset = tg3_io_slot_reset,
  14897. .resume = tg3_io_resume
  14898. };
  14899. static struct pci_driver tg3_driver = {
  14900. .name = DRV_MODULE_NAME,
  14901. .id_table = tg3_pci_tbl,
  14902. .probe = tg3_init_one,
  14903. .remove = tg3_remove_one,
  14904. .err_handler = &tg3_err_handler,
  14905. .driver.pm = &tg3_pm_ops,
  14906. .shutdown = tg3_shutdown,
  14907. };
  14908. module_pci_driver(tg3_driver);