cnic.c 147 KB

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  1. /* cnic.c: Broadcom CNIC core network driver.
  2. *
  3. * Copyright (c) 2006-2013 Broadcom Corporation
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License as published by
  7. * the Free Software Foundation.
  8. *
  9. * Original skeleton written by: John(Zongxi) Chen (zongxi@broadcom.com)
  10. * Modified and maintained by: Michael Chan <mchan@broadcom.com>
  11. */
  12. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  13. #include <linux/module.h>
  14. #include <linux/kernel.h>
  15. #include <linux/errno.h>
  16. #include <linux/list.h>
  17. #include <linux/slab.h>
  18. #include <linux/pci.h>
  19. #include <linux/init.h>
  20. #include <linux/netdevice.h>
  21. #include <linux/uio_driver.h>
  22. #include <linux/in.h>
  23. #include <linux/dma-mapping.h>
  24. #include <linux/delay.h>
  25. #include <linux/ethtool.h>
  26. #include <linux/if_vlan.h>
  27. #include <linux/prefetch.h>
  28. #include <linux/random.h>
  29. #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  30. #define BCM_VLAN 1
  31. #endif
  32. #include <net/ip.h>
  33. #include <net/tcp.h>
  34. #include <net/route.h>
  35. #include <net/ipv6.h>
  36. #include <net/ip6_route.h>
  37. #include <net/ip6_checksum.h>
  38. #include <scsi/iscsi_if.h>
  39. #define BCM_CNIC 1
  40. #include "cnic_if.h"
  41. #include "bnx2.h"
  42. #include "bnx2x/bnx2x.h"
  43. #include "bnx2x/bnx2x_reg.h"
  44. #include "bnx2x/bnx2x_fw_defs.h"
  45. #include "bnx2x/bnx2x_hsi.h"
  46. #include "../../../scsi/bnx2i/57xx_iscsi_constants.h"
  47. #include "../../../scsi/bnx2i/57xx_iscsi_hsi.h"
  48. #include "../../../scsi/bnx2fc/bnx2fc_constants.h"
  49. #include "cnic.h"
  50. #include "cnic_defs.h"
  51. #define CNIC_MODULE_NAME "cnic"
  52. static char version[] =
  53. "Broadcom NetXtreme II CNIC Driver " CNIC_MODULE_NAME " v" CNIC_MODULE_VERSION " (" CNIC_MODULE_RELDATE ")\n";
  54. MODULE_AUTHOR("Michael Chan <mchan@broadcom.com> and John(Zongxi) "
  55. "Chen (zongxi@broadcom.com");
  56. MODULE_DESCRIPTION("Broadcom NetXtreme II CNIC Driver");
  57. MODULE_LICENSE("GPL");
  58. MODULE_VERSION(CNIC_MODULE_VERSION);
  59. /* cnic_dev_list modifications are protected by both rtnl and cnic_dev_lock */
  60. static LIST_HEAD(cnic_dev_list);
  61. static LIST_HEAD(cnic_udev_list);
  62. static DEFINE_RWLOCK(cnic_dev_lock);
  63. static DEFINE_MUTEX(cnic_lock);
  64. static struct cnic_ulp_ops __rcu *cnic_ulp_tbl[MAX_CNIC_ULP_TYPE];
  65. /* helper function, assuming cnic_lock is held */
  66. static inline struct cnic_ulp_ops *cnic_ulp_tbl_prot(int type)
  67. {
  68. return rcu_dereference_protected(cnic_ulp_tbl[type],
  69. lockdep_is_held(&cnic_lock));
  70. }
  71. static int cnic_service_bnx2(void *, void *);
  72. static int cnic_service_bnx2x(void *, void *);
  73. static int cnic_ctl(void *, struct cnic_ctl_info *);
  74. static struct cnic_ops cnic_bnx2_ops = {
  75. .cnic_owner = THIS_MODULE,
  76. .cnic_handler = cnic_service_bnx2,
  77. .cnic_ctl = cnic_ctl,
  78. };
  79. static struct cnic_ops cnic_bnx2x_ops = {
  80. .cnic_owner = THIS_MODULE,
  81. .cnic_handler = cnic_service_bnx2x,
  82. .cnic_ctl = cnic_ctl,
  83. };
  84. static struct workqueue_struct *cnic_wq;
  85. static void cnic_shutdown_rings(struct cnic_dev *);
  86. static void cnic_init_rings(struct cnic_dev *);
  87. static int cnic_cm_set_pg(struct cnic_sock *);
  88. static int cnic_uio_open(struct uio_info *uinfo, struct inode *inode)
  89. {
  90. struct cnic_uio_dev *udev = uinfo->priv;
  91. struct cnic_dev *dev;
  92. if (!capable(CAP_NET_ADMIN))
  93. return -EPERM;
  94. if (udev->uio_dev != -1)
  95. return -EBUSY;
  96. rtnl_lock();
  97. dev = udev->dev;
  98. if (!dev || !test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
  99. rtnl_unlock();
  100. return -ENODEV;
  101. }
  102. udev->uio_dev = iminor(inode);
  103. cnic_shutdown_rings(dev);
  104. cnic_init_rings(dev);
  105. rtnl_unlock();
  106. return 0;
  107. }
  108. static int cnic_uio_close(struct uio_info *uinfo, struct inode *inode)
  109. {
  110. struct cnic_uio_dev *udev = uinfo->priv;
  111. udev->uio_dev = -1;
  112. return 0;
  113. }
  114. static inline void cnic_hold(struct cnic_dev *dev)
  115. {
  116. atomic_inc(&dev->ref_count);
  117. }
  118. static inline void cnic_put(struct cnic_dev *dev)
  119. {
  120. atomic_dec(&dev->ref_count);
  121. }
  122. static inline void csk_hold(struct cnic_sock *csk)
  123. {
  124. atomic_inc(&csk->ref_count);
  125. }
  126. static inline void csk_put(struct cnic_sock *csk)
  127. {
  128. atomic_dec(&csk->ref_count);
  129. }
  130. static struct cnic_dev *cnic_from_netdev(struct net_device *netdev)
  131. {
  132. struct cnic_dev *cdev;
  133. read_lock(&cnic_dev_lock);
  134. list_for_each_entry(cdev, &cnic_dev_list, list) {
  135. if (netdev == cdev->netdev) {
  136. cnic_hold(cdev);
  137. read_unlock(&cnic_dev_lock);
  138. return cdev;
  139. }
  140. }
  141. read_unlock(&cnic_dev_lock);
  142. return NULL;
  143. }
  144. static inline void ulp_get(struct cnic_ulp_ops *ulp_ops)
  145. {
  146. atomic_inc(&ulp_ops->ref_count);
  147. }
  148. static inline void ulp_put(struct cnic_ulp_ops *ulp_ops)
  149. {
  150. atomic_dec(&ulp_ops->ref_count);
  151. }
  152. static void cnic_ctx_wr(struct cnic_dev *dev, u32 cid_addr, u32 off, u32 val)
  153. {
  154. struct cnic_local *cp = dev->cnic_priv;
  155. struct cnic_eth_dev *ethdev = cp->ethdev;
  156. struct drv_ctl_info info;
  157. struct drv_ctl_io *io = &info.data.io;
  158. info.cmd = DRV_CTL_CTX_WR_CMD;
  159. io->cid_addr = cid_addr;
  160. io->offset = off;
  161. io->data = val;
  162. ethdev->drv_ctl(dev->netdev, &info);
  163. }
  164. static void cnic_ctx_tbl_wr(struct cnic_dev *dev, u32 off, dma_addr_t addr)
  165. {
  166. struct cnic_local *cp = dev->cnic_priv;
  167. struct cnic_eth_dev *ethdev = cp->ethdev;
  168. struct drv_ctl_info info;
  169. struct drv_ctl_io *io = &info.data.io;
  170. info.cmd = DRV_CTL_CTXTBL_WR_CMD;
  171. io->offset = off;
  172. io->dma_addr = addr;
  173. ethdev->drv_ctl(dev->netdev, &info);
  174. }
  175. static void cnic_ring_ctl(struct cnic_dev *dev, u32 cid, u32 cl_id, int start)
  176. {
  177. struct cnic_local *cp = dev->cnic_priv;
  178. struct cnic_eth_dev *ethdev = cp->ethdev;
  179. struct drv_ctl_info info;
  180. struct drv_ctl_l2_ring *ring = &info.data.ring;
  181. if (start)
  182. info.cmd = DRV_CTL_START_L2_CMD;
  183. else
  184. info.cmd = DRV_CTL_STOP_L2_CMD;
  185. ring->cid = cid;
  186. ring->client_id = cl_id;
  187. ethdev->drv_ctl(dev->netdev, &info);
  188. }
  189. static void cnic_reg_wr_ind(struct cnic_dev *dev, u32 off, u32 val)
  190. {
  191. struct cnic_local *cp = dev->cnic_priv;
  192. struct cnic_eth_dev *ethdev = cp->ethdev;
  193. struct drv_ctl_info info;
  194. struct drv_ctl_io *io = &info.data.io;
  195. info.cmd = DRV_CTL_IO_WR_CMD;
  196. io->offset = off;
  197. io->data = val;
  198. ethdev->drv_ctl(dev->netdev, &info);
  199. }
  200. static u32 cnic_reg_rd_ind(struct cnic_dev *dev, u32 off)
  201. {
  202. struct cnic_local *cp = dev->cnic_priv;
  203. struct cnic_eth_dev *ethdev = cp->ethdev;
  204. struct drv_ctl_info info;
  205. struct drv_ctl_io *io = &info.data.io;
  206. info.cmd = DRV_CTL_IO_RD_CMD;
  207. io->offset = off;
  208. ethdev->drv_ctl(dev->netdev, &info);
  209. return io->data;
  210. }
  211. static void cnic_ulp_ctl(struct cnic_dev *dev, int ulp_type, bool reg)
  212. {
  213. struct cnic_local *cp = dev->cnic_priv;
  214. struct cnic_eth_dev *ethdev = cp->ethdev;
  215. struct drv_ctl_info info;
  216. struct fcoe_capabilities *fcoe_cap =
  217. &info.data.register_data.fcoe_features;
  218. if (reg) {
  219. info.cmd = DRV_CTL_ULP_REGISTER_CMD;
  220. if (ulp_type == CNIC_ULP_FCOE && dev->fcoe_cap)
  221. memcpy(fcoe_cap, dev->fcoe_cap, sizeof(*fcoe_cap));
  222. } else {
  223. info.cmd = DRV_CTL_ULP_UNREGISTER_CMD;
  224. }
  225. info.data.ulp_type = ulp_type;
  226. ethdev->drv_ctl(dev->netdev, &info);
  227. }
  228. static int cnic_in_use(struct cnic_sock *csk)
  229. {
  230. return test_bit(SK_F_INUSE, &csk->flags);
  231. }
  232. static void cnic_spq_completion(struct cnic_dev *dev, int cmd, u32 count)
  233. {
  234. struct cnic_local *cp = dev->cnic_priv;
  235. struct cnic_eth_dev *ethdev = cp->ethdev;
  236. struct drv_ctl_info info;
  237. info.cmd = cmd;
  238. info.data.credit.credit_count = count;
  239. ethdev->drv_ctl(dev->netdev, &info);
  240. }
  241. static int cnic_get_l5_cid(struct cnic_local *cp, u32 cid, u32 *l5_cid)
  242. {
  243. u32 i;
  244. if (!cp->ctx_tbl)
  245. return -EINVAL;
  246. for (i = 0; i < cp->max_cid_space; i++) {
  247. if (cp->ctx_tbl[i].cid == cid) {
  248. *l5_cid = i;
  249. return 0;
  250. }
  251. }
  252. return -EINVAL;
  253. }
  254. static int cnic_send_nlmsg(struct cnic_local *cp, u32 type,
  255. struct cnic_sock *csk)
  256. {
  257. struct iscsi_path path_req;
  258. char *buf = NULL;
  259. u16 len = 0;
  260. u32 msg_type = ISCSI_KEVENT_IF_DOWN;
  261. struct cnic_ulp_ops *ulp_ops;
  262. struct cnic_uio_dev *udev = cp->udev;
  263. int rc = 0, retry = 0;
  264. if (!udev || udev->uio_dev == -1)
  265. return -ENODEV;
  266. if (csk) {
  267. len = sizeof(path_req);
  268. buf = (char *) &path_req;
  269. memset(&path_req, 0, len);
  270. msg_type = ISCSI_KEVENT_PATH_REQ;
  271. path_req.handle = (u64) csk->l5_cid;
  272. if (test_bit(SK_F_IPV6, &csk->flags)) {
  273. memcpy(&path_req.dst.v6_addr, &csk->dst_ip[0],
  274. sizeof(struct in6_addr));
  275. path_req.ip_addr_len = 16;
  276. } else {
  277. memcpy(&path_req.dst.v4_addr, &csk->dst_ip[0],
  278. sizeof(struct in_addr));
  279. path_req.ip_addr_len = 4;
  280. }
  281. path_req.vlan_id = csk->vlan_id;
  282. path_req.pmtu = csk->mtu;
  283. }
  284. while (retry < 3) {
  285. rc = 0;
  286. rcu_read_lock();
  287. ulp_ops = rcu_dereference(cnic_ulp_tbl[CNIC_ULP_ISCSI]);
  288. if (ulp_ops)
  289. rc = ulp_ops->iscsi_nl_send_msg(
  290. cp->ulp_handle[CNIC_ULP_ISCSI],
  291. msg_type, buf, len);
  292. rcu_read_unlock();
  293. if (rc == 0 || msg_type != ISCSI_KEVENT_PATH_REQ)
  294. break;
  295. msleep(100);
  296. retry++;
  297. }
  298. return rc;
  299. }
  300. static void cnic_cm_upcall(struct cnic_local *, struct cnic_sock *, u8);
  301. static int cnic_iscsi_nl_msg_recv(struct cnic_dev *dev, u32 msg_type,
  302. char *buf, u16 len)
  303. {
  304. int rc = -EINVAL;
  305. switch (msg_type) {
  306. case ISCSI_UEVENT_PATH_UPDATE: {
  307. struct cnic_local *cp;
  308. u32 l5_cid;
  309. struct cnic_sock *csk;
  310. struct iscsi_path *path_resp;
  311. if (len < sizeof(*path_resp))
  312. break;
  313. path_resp = (struct iscsi_path *) buf;
  314. cp = dev->cnic_priv;
  315. l5_cid = (u32) path_resp->handle;
  316. if (l5_cid >= MAX_CM_SK_TBL_SZ)
  317. break;
  318. rcu_read_lock();
  319. if (!rcu_dereference(cp->ulp_ops[CNIC_ULP_L4])) {
  320. rc = -ENODEV;
  321. rcu_read_unlock();
  322. break;
  323. }
  324. csk = &cp->csk_tbl[l5_cid];
  325. csk_hold(csk);
  326. if (cnic_in_use(csk) &&
  327. test_bit(SK_F_CONNECT_START, &csk->flags)) {
  328. csk->vlan_id = path_resp->vlan_id;
  329. memcpy(csk->ha, path_resp->mac_addr, 6);
  330. if (test_bit(SK_F_IPV6, &csk->flags))
  331. memcpy(&csk->src_ip[0], &path_resp->src.v6_addr,
  332. sizeof(struct in6_addr));
  333. else
  334. memcpy(&csk->src_ip[0], &path_resp->src.v4_addr,
  335. sizeof(struct in_addr));
  336. if (is_valid_ether_addr(csk->ha)) {
  337. cnic_cm_set_pg(csk);
  338. } else if (!test_bit(SK_F_OFFLD_SCHED, &csk->flags) &&
  339. !test_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  340. cnic_cm_upcall(cp, csk,
  341. L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
  342. clear_bit(SK_F_CONNECT_START, &csk->flags);
  343. }
  344. }
  345. csk_put(csk);
  346. rcu_read_unlock();
  347. rc = 0;
  348. }
  349. }
  350. return rc;
  351. }
  352. static int cnic_offld_prep(struct cnic_sock *csk)
  353. {
  354. if (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  355. return 0;
  356. if (!test_bit(SK_F_CONNECT_START, &csk->flags)) {
  357. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  358. return 0;
  359. }
  360. return 1;
  361. }
  362. static int cnic_close_prep(struct cnic_sock *csk)
  363. {
  364. clear_bit(SK_F_CONNECT_START, &csk->flags);
  365. smp_mb__after_clear_bit();
  366. if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  367. while (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  368. msleep(1);
  369. return 1;
  370. }
  371. return 0;
  372. }
  373. static int cnic_abort_prep(struct cnic_sock *csk)
  374. {
  375. clear_bit(SK_F_CONNECT_START, &csk->flags);
  376. smp_mb__after_clear_bit();
  377. while (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  378. msleep(1);
  379. if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  380. csk->state = L4_KCQE_OPCODE_VALUE_RESET_COMP;
  381. return 1;
  382. }
  383. return 0;
  384. }
  385. int cnic_register_driver(int ulp_type, struct cnic_ulp_ops *ulp_ops)
  386. {
  387. struct cnic_dev *dev;
  388. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  389. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  390. return -EINVAL;
  391. }
  392. mutex_lock(&cnic_lock);
  393. if (cnic_ulp_tbl_prot(ulp_type)) {
  394. pr_err("%s: Type %d has already been registered\n",
  395. __func__, ulp_type);
  396. mutex_unlock(&cnic_lock);
  397. return -EBUSY;
  398. }
  399. read_lock(&cnic_dev_lock);
  400. list_for_each_entry(dev, &cnic_dev_list, list) {
  401. struct cnic_local *cp = dev->cnic_priv;
  402. clear_bit(ULP_F_INIT, &cp->ulp_flags[ulp_type]);
  403. }
  404. read_unlock(&cnic_dev_lock);
  405. atomic_set(&ulp_ops->ref_count, 0);
  406. rcu_assign_pointer(cnic_ulp_tbl[ulp_type], ulp_ops);
  407. mutex_unlock(&cnic_lock);
  408. /* Prevent race conditions with netdev_event */
  409. rtnl_lock();
  410. list_for_each_entry(dev, &cnic_dev_list, list) {
  411. struct cnic_local *cp = dev->cnic_priv;
  412. if (!test_and_set_bit(ULP_F_INIT, &cp->ulp_flags[ulp_type]))
  413. ulp_ops->cnic_init(dev);
  414. }
  415. rtnl_unlock();
  416. return 0;
  417. }
  418. int cnic_unregister_driver(int ulp_type)
  419. {
  420. struct cnic_dev *dev;
  421. struct cnic_ulp_ops *ulp_ops;
  422. int i = 0;
  423. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  424. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  425. return -EINVAL;
  426. }
  427. mutex_lock(&cnic_lock);
  428. ulp_ops = cnic_ulp_tbl_prot(ulp_type);
  429. if (!ulp_ops) {
  430. pr_err("%s: Type %d has not been registered\n",
  431. __func__, ulp_type);
  432. goto out_unlock;
  433. }
  434. read_lock(&cnic_dev_lock);
  435. list_for_each_entry(dev, &cnic_dev_list, list) {
  436. struct cnic_local *cp = dev->cnic_priv;
  437. if (rcu_dereference(cp->ulp_ops[ulp_type])) {
  438. pr_err("%s: Type %d still has devices registered\n",
  439. __func__, ulp_type);
  440. read_unlock(&cnic_dev_lock);
  441. goto out_unlock;
  442. }
  443. }
  444. read_unlock(&cnic_dev_lock);
  445. RCU_INIT_POINTER(cnic_ulp_tbl[ulp_type], NULL);
  446. mutex_unlock(&cnic_lock);
  447. synchronize_rcu();
  448. while ((atomic_read(&ulp_ops->ref_count) != 0) && (i < 20)) {
  449. msleep(100);
  450. i++;
  451. }
  452. if (atomic_read(&ulp_ops->ref_count) != 0)
  453. pr_warn("%s: Failed waiting for ref count to go to zero\n",
  454. __func__);
  455. return 0;
  456. out_unlock:
  457. mutex_unlock(&cnic_lock);
  458. return -EINVAL;
  459. }
  460. static int cnic_start_hw(struct cnic_dev *);
  461. static void cnic_stop_hw(struct cnic_dev *);
  462. static int cnic_register_device(struct cnic_dev *dev, int ulp_type,
  463. void *ulp_ctx)
  464. {
  465. struct cnic_local *cp = dev->cnic_priv;
  466. struct cnic_ulp_ops *ulp_ops;
  467. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  468. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  469. return -EINVAL;
  470. }
  471. mutex_lock(&cnic_lock);
  472. if (cnic_ulp_tbl_prot(ulp_type) == NULL) {
  473. pr_err("%s: Driver with type %d has not been registered\n",
  474. __func__, ulp_type);
  475. mutex_unlock(&cnic_lock);
  476. return -EAGAIN;
  477. }
  478. if (rcu_dereference(cp->ulp_ops[ulp_type])) {
  479. pr_err("%s: Type %d has already been registered to this device\n",
  480. __func__, ulp_type);
  481. mutex_unlock(&cnic_lock);
  482. return -EBUSY;
  483. }
  484. clear_bit(ULP_F_START, &cp->ulp_flags[ulp_type]);
  485. cp->ulp_handle[ulp_type] = ulp_ctx;
  486. ulp_ops = cnic_ulp_tbl_prot(ulp_type);
  487. rcu_assign_pointer(cp->ulp_ops[ulp_type], ulp_ops);
  488. cnic_hold(dev);
  489. if (test_bit(CNIC_F_CNIC_UP, &dev->flags))
  490. if (!test_and_set_bit(ULP_F_START, &cp->ulp_flags[ulp_type]))
  491. ulp_ops->cnic_start(cp->ulp_handle[ulp_type]);
  492. mutex_unlock(&cnic_lock);
  493. cnic_ulp_ctl(dev, ulp_type, true);
  494. return 0;
  495. }
  496. EXPORT_SYMBOL(cnic_register_driver);
  497. static int cnic_unregister_device(struct cnic_dev *dev, int ulp_type)
  498. {
  499. struct cnic_local *cp = dev->cnic_priv;
  500. int i = 0;
  501. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  502. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  503. return -EINVAL;
  504. }
  505. mutex_lock(&cnic_lock);
  506. if (rcu_dereference(cp->ulp_ops[ulp_type])) {
  507. RCU_INIT_POINTER(cp->ulp_ops[ulp_type], NULL);
  508. cnic_put(dev);
  509. } else {
  510. pr_err("%s: device not registered to this ulp type %d\n",
  511. __func__, ulp_type);
  512. mutex_unlock(&cnic_lock);
  513. return -EINVAL;
  514. }
  515. mutex_unlock(&cnic_lock);
  516. if (ulp_type == CNIC_ULP_ISCSI)
  517. cnic_send_nlmsg(cp, ISCSI_KEVENT_IF_DOWN, NULL);
  518. else if (ulp_type == CNIC_ULP_FCOE)
  519. dev->fcoe_cap = NULL;
  520. synchronize_rcu();
  521. while (test_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[ulp_type]) &&
  522. i < 20) {
  523. msleep(100);
  524. i++;
  525. }
  526. if (test_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[ulp_type]))
  527. netdev_warn(dev->netdev, "Failed waiting for ULP up call to complete\n");
  528. cnic_ulp_ctl(dev, ulp_type, false);
  529. return 0;
  530. }
  531. EXPORT_SYMBOL(cnic_unregister_driver);
  532. static int cnic_init_id_tbl(struct cnic_id_tbl *id_tbl, u32 size, u32 start_id,
  533. u32 next)
  534. {
  535. id_tbl->start = start_id;
  536. id_tbl->max = size;
  537. id_tbl->next = next;
  538. spin_lock_init(&id_tbl->lock);
  539. id_tbl->table = kzalloc(DIV_ROUND_UP(size, 32) * 4, GFP_KERNEL);
  540. if (!id_tbl->table)
  541. return -ENOMEM;
  542. return 0;
  543. }
  544. static void cnic_free_id_tbl(struct cnic_id_tbl *id_tbl)
  545. {
  546. kfree(id_tbl->table);
  547. id_tbl->table = NULL;
  548. }
  549. static int cnic_alloc_id(struct cnic_id_tbl *id_tbl, u32 id)
  550. {
  551. int ret = -1;
  552. id -= id_tbl->start;
  553. if (id >= id_tbl->max)
  554. return ret;
  555. spin_lock(&id_tbl->lock);
  556. if (!test_bit(id, id_tbl->table)) {
  557. set_bit(id, id_tbl->table);
  558. ret = 0;
  559. }
  560. spin_unlock(&id_tbl->lock);
  561. return ret;
  562. }
  563. /* Returns -1 if not successful */
  564. static u32 cnic_alloc_new_id(struct cnic_id_tbl *id_tbl)
  565. {
  566. u32 id;
  567. spin_lock(&id_tbl->lock);
  568. id = find_next_zero_bit(id_tbl->table, id_tbl->max, id_tbl->next);
  569. if (id >= id_tbl->max) {
  570. id = -1;
  571. if (id_tbl->next != 0) {
  572. id = find_first_zero_bit(id_tbl->table, id_tbl->next);
  573. if (id >= id_tbl->next)
  574. id = -1;
  575. }
  576. }
  577. if (id < id_tbl->max) {
  578. set_bit(id, id_tbl->table);
  579. id_tbl->next = (id + 1) & (id_tbl->max - 1);
  580. id += id_tbl->start;
  581. }
  582. spin_unlock(&id_tbl->lock);
  583. return id;
  584. }
  585. static void cnic_free_id(struct cnic_id_tbl *id_tbl, u32 id)
  586. {
  587. if (id == -1)
  588. return;
  589. id -= id_tbl->start;
  590. if (id >= id_tbl->max)
  591. return;
  592. clear_bit(id, id_tbl->table);
  593. }
  594. static void cnic_free_dma(struct cnic_dev *dev, struct cnic_dma *dma)
  595. {
  596. int i;
  597. if (!dma->pg_arr)
  598. return;
  599. for (i = 0; i < dma->num_pages; i++) {
  600. if (dma->pg_arr[i]) {
  601. dma_free_coherent(&dev->pcidev->dev, BNX2_PAGE_SIZE,
  602. dma->pg_arr[i], dma->pg_map_arr[i]);
  603. dma->pg_arr[i] = NULL;
  604. }
  605. }
  606. if (dma->pgtbl) {
  607. dma_free_coherent(&dev->pcidev->dev, dma->pgtbl_size,
  608. dma->pgtbl, dma->pgtbl_map);
  609. dma->pgtbl = NULL;
  610. }
  611. kfree(dma->pg_arr);
  612. dma->pg_arr = NULL;
  613. dma->num_pages = 0;
  614. }
  615. static void cnic_setup_page_tbl(struct cnic_dev *dev, struct cnic_dma *dma)
  616. {
  617. int i;
  618. __le32 *page_table = (__le32 *) dma->pgtbl;
  619. for (i = 0; i < dma->num_pages; i++) {
  620. /* Each entry needs to be in big endian format. */
  621. *page_table = cpu_to_le32((u64) dma->pg_map_arr[i] >> 32);
  622. page_table++;
  623. *page_table = cpu_to_le32(dma->pg_map_arr[i] & 0xffffffff);
  624. page_table++;
  625. }
  626. }
  627. static void cnic_setup_page_tbl_le(struct cnic_dev *dev, struct cnic_dma *dma)
  628. {
  629. int i;
  630. __le32 *page_table = (__le32 *) dma->pgtbl;
  631. for (i = 0; i < dma->num_pages; i++) {
  632. /* Each entry needs to be in little endian format. */
  633. *page_table = cpu_to_le32(dma->pg_map_arr[i] & 0xffffffff);
  634. page_table++;
  635. *page_table = cpu_to_le32((u64) dma->pg_map_arr[i] >> 32);
  636. page_table++;
  637. }
  638. }
  639. static int cnic_alloc_dma(struct cnic_dev *dev, struct cnic_dma *dma,
  640. int pages, int use_pg_tbl)
  641. {
  642. int i, size;
  643. struct cnic_local *cp = dev->cnic_priv;
  644. size = pages * (sizeof(void *) + sizeof(dma_addr_t));
  645. dma->pg_arr = kzalloc(size, GFP_ATOMIC);
  646. if (dma->pg_arr == NULL)
  647. return -ENOMEM;
  648. dma->pg_map_arr = (dma_addr_t *) (dma->pg_arr + pages);
  649. dma->num_pages = pages;
  650. for (i = 0; i < pages; i++) {
  651. dma->pg_arr[i] = dma_alloc_coherent(&dev->pcidev->dev,
  652. BNX2_PAGE_SIZE,
  653. &dma->pg_map_arr[i],
  654. GFP_ATOMIC);
  655. if (dma->pg_arr[i] == NULL)
  656. goto error;
  657. }
  658. if (!use_pg_tbl)
  659. return 0;
  660. dma->pgtbl_size = ((pages * 8) + BNX2_PAGE_SIZE - 1) &
  661. ~(BNX2_PAGE_SIZE - 1);
  662. dma->pgtbl = dma_alloc_coherent(&dev->pcidev->dev, dma->pgtbl_size,
  663. &dma->pgtbl_map, GFP_ATOMIC);
  664. if (dma->pgtbl == NULL)
  665. goto error;
  666. cp->setup_pgtbl(dev, dma);
  667. return 0;
  668. error:
  669. cnic_free_dma(dev, dma);
  670. return -ENOMEM;
  671. }
  672. static void cnic_free_context(struct cnic_dev *dev)
  673. {
  674. struct cnic_local *cp = dev->cnic_priv;
  675. int i;
  676. for (i = 0; i < cp->ctx_blks; i++) {
  677. if (cp->ctx_arr[i].ctx) {
  678. dma_free_coherent(&dev->pcidev->dev, cp->ctx_blk_size,
  679. cp->ctx_arr[i].ctx,
  680. cp->ctx_arr[i].mapping);
  681. cp->ctx_arr[i].ctx = NULL;
  682. }
  683. }
  684. }
  685. static void __cnic_free_uio_rings(struct cnic_uio_dev *udev)
  686. {
  687. if (udev->l2_buf) {
  688. dma_free_coherent(&udev->pdev->dev, udev->l2_buf_size,
  689. udev->l2_buf, udev->l2_buf_map);
  690. udev->l2_buf = NULL;
  691. }
  692. if (udev->l2_ring) {
  693. dma_free_coherent(&udev->pdev->dev, udev->l2_ring_size,
  694. udev->l2_ring, udev->l2_ring_map);
  695. udev->l2_ring = NULL;
  696. }
  697. }
  698. static void __cnic_free_uio(struct cnic_uio_dev *udev)
  699. {
  700. uio_unregister_device(&udev->cnic_uinfo);
  701. __cnic_free_uio_rings(udev);
  702. pci_dev_put(udev->pdev);
  703. kfree(udev);
  704. }
  705. static void cnic_free_uio(struct cnic_uio_dev *udev)
  706. {
  707. if (!udev)
  708. return;
  709. write_lock(&cnic_dev_lock);
  710. list_del_init(&udev->list);
  711. write_unlock(&cnic_dev_lock);
  712. __cnic_free_uio(udev);
  713. }
  714. static void cnic_free_resc(struct cnic_dev *dev)
  715. {
  716. struct cnic_local *cp = dev->cnic_priv;
  717. struct cnic_uio_dev *udev = cp->udev;
  718. if (udev) {
  719. udev->dev = NULL;
  720. cp->udev = NULL;
  721. if (udev->uio_dev == -1)
  722. __cnic_free_uio_rings(udev);
  723. }
  724. cnic_free_context(dev);
  725. kfree(cp->ctx_arr);
  726. cp->ctx_arr = NULL;
  727. cp->ctx_blks = 0;
  728. cnic_free_dma(dev, &cp->gbl_buf_info);
  729. cnic_free_dma(dev, &cp->kwq_info);
  730. cnic_free_dma(dev, &cp->kwq_16_data_info);
  731. cnic_free_dma(dev, &cp->kcq2.dma);
  732. cnic_free_dma(dev, &cp->kcq1.dma);
  733. kfree(cp->iscsi_tbl);
  734. cp->iscsi_tbl = NULL;
  735. kfree(cp->ctx_tbl);
  736. cp->ctx_tbl = NULL;
  737. cnic_free_id_tbl(&cp->fcoe_cid_tbl);
  738. cnic_free_id_tbl(&cp->cid_tbl);
  739. }
  740. static int cnic_alloc_context(struct cnic_dev *dev)
  741. {
  742. struct cnic_local *cp = dev->cnic_priv;
  743. if (BNX2_CHIP(cp) == BNX2_CHIP_5709) {
  744. int i, k, arr_size;
  745. cp->ctx_blk_size = BNX2_PAGE_SIZE;
  746. cp->cids_per_blk = BNX2_PAGE_SIZE / 128;
  747. arr_size = BNX2_MAX_CID / cp->cids_per_blk *
  748. sizeof(struct cnic_ctx);
  749. cp->ctx_arr = kzalloc(arr_size, GFP_KERNEL);
  750. if (cp->ctx_arr == NULL)
  751. return -ENOMEM;
  752. k = 0;
  753. for (i = 0; i < 2; i++) {
  754. u32 j, reg, off, lo, hi;
  755. if (i == 0)
  756. off = BNX2_PG_CTX_MAP;
  757. else
  758. off = BNX2_ISCSI_CTX_MAP;
  759. reg = cnic_reg_rd_ind(dev, off);
  760. lo = reg >> 16;
  761. hi = reg & 0xffff;
  762. for (j = lo; j < hi; j += cp->cids_per_blk, k++)
  763. cp->ctx_arr[k].cid = j;
  764. }
  765. cp->ctx_blks = k;
  766. if (cp->ctx_blks >= (BNX2_MAX_CID / cp->cids_per_blk)) {
  767. cp->ctx_blks = 0;
  768. return -ENOMEM;
  769. }
  770. for (i = 0; i < cp->ctx_blks; i++) {
  771. cp->ctx_arr[i].ctx =
  772. dma_alloc_coherent(&dev->pcidev->dev,
  773. BNX2_PAGE_SIZE,
  774. &cp->ctx_arr[i].mapping,
  775. GFP_KERNEL);
  776. if (cp->ctx_arr[i].ctx == NULL)
  777. return -ENOMEM;
  778. }
  779. }
  780. return 0;
  781. }
  782. static u16 cnic_bnx2_next_idx(u16 idx)
  783. {
  784. return idx + 1;
  785. }
  786. static u16 cnic_bnx2_hw_idx(u16 idx)
  787. {
  788. return idx;
  789. }
  790. static u16 cnic_bnx2x_next_idx(u16 idx)
  791. {
  792. idx++;
  793. if ((idx & MAX_KCQE_CNT) == MAX_KCQE_CNT)
  794. idx++;
  795. return idx;
  796. }
  797. static u16 cnic_bnx2x_hw_idx(u16 idx)
  798. {
  799. if ((idx & MAX_KCQE_CNT) == MAX_KCQE_CNT)
  800. idx++;
  801. return idx;
  802. }
  803. static int cnic_alloc_kcq(struct cnic_dev *dev, struct kcq_info *info,
  804. bool use_pg_tbl)
  805. {
  806. int err, i, use_page_tbl = 0;
  807. struct kcqe **kcq;
  808. if (use_pg_tbl)
  809. use_page_tbl = 1;
  810. err = cnic_alloc_dma(dev, &info->dma, KCQ_PAGE_CNT, use_page_tbl);
  811. if (err)
  812. return err;
  813. kcq = (struct kcqe **) info->dma.pg_arr;
  814. info->kcq = kcq;
  815. info->next_idx = cnic_bnx2_next_idx;
  816. info->hw_idx = cnic_bnx2_hw_idx;
  817. if (use_pg_tbl)
  818. return 0;
  819. info->next_idx = cnic_bnx2x_next_idx;
  820. info->hw_idx = cnic_bnx2x_hw_idx;
  821. for (i = 0; i < KCQ_PAGE_CNT; i++) {
  822. struct bnx2x_bd_chain_next *next =
  823. (struct bnx2x_bd_chain_next *) &kcq[i][MAX_KCQE_CNT];
  824. int j = i + 1;
  825. if (j >= KCQ_PAGE_CNT)
  826. j = 0;
  827. next->addr_hi = (u64) info->dma.pg_map_arr[j] >> 32;
  828. next->addr_lo = info->dma.pg_map_arr[j] & 0xffffffff;
  829. }
  830. return 0;
  831. }
  832. static int __cnic_alloc_uio_rings(struct cnic_uio_dev *udev, int pages)
  833. {
  834. struct cnic_local *cp = udev->dev->cnic_priv;
  835. if (udev->l2_ring)
  836. return 0;
  837. udev->l2_ring_size = pages * BNX2_PAGE_SIZE;
  838. udev->l2_ring = dma_alloc_coherent(&udev->pdev->dev, udev->l2_ring_size,
  839. &udev->l2_ring_map,
  840. GFP_KERNEL | __GFP_COMP);
  841. if (!udev->l2_ring)
  842. return -ENOMEM;
  843. udev->l2_buf_size = (cp->l2_rx_ring_size + 1) * cp->l2_single_buf_size;
  844. udev->l2_buf_size = PAGE_ALIGN(udev->l2_buf_size);
  845. udev->l2_buf = dma_alloc_coherent(&udev->pdev->dev, udev->l2_buf_size,
  846. &udev->l2_buf_map,
  847. GFP_KERNEL | __GFP_COMP);
  848. if (!udev->l2_buf) {
  849. __cnic_free_uio_rings(udev);
  850. return -ENOMEM;
  851. }
  852. return 0;
  853. }
  854. static int cnic_alloc_uio_rings(struct cnic_dev *dev, int pages)
  855. {
  856. struct cnic_local *cp = dev->cnic_priv;
  857. struct cnic_uio_dev *udev;
  858. read_lock(&cnic_dev_lock);
  859. list_for_each_entry(udev, &cnic_udev_list, list) {
  860. if (udev->pdev == dev->pcidev) {
  861. udev->dev = dev;
  862. if (__cnic_alloc_uio_rings(udev, pages)) {
  863. udev->dev = NULL;
  864. read_unlock(&cnic_dev_lock);
  865. return -ENOMEM;
  866. }
  867. cp->udev = udev;
  868. read_unlock(&cnic_dev_lock);
  869. return 0;
  870. }
  871. }
  872. read_unlock(&cnic_dev_lock);
  873. udev = kzalloc(sizeof(struct cnic_uio_dev), GFP_ATOMIC);
  874. if (!udev)
  875. return -ENOMEM;
  876. udev->uio_dev = -1;
  877. udev->dev = dev;
  878. udev->pdev = dev->pcidev;
  879. if (__cnic_alloc_uio_rings(udev, pages))
  880. goto err_udev;
  881. write_lock(&cnic_dev_lock);
  882. list_add(&udev->list, &cnic_udev_list);
  883. write_unlock(&cnic_dev_lock);
  884. pci_dev_get(udev->pdev);
  885. cp->udev = udev;
  886. return 0;
  887. err_udev:
  888. kfree(udev);
  889. return -ENOMEM;
  890. }
  891. static int cnic_init_uio(struct cnic_dev *dev)
  892. {
  893. struct cnic_local *cp = dev->cnic_priv;
  894. struct cnic_uio_dev *udev = cp->udev;
  895. struct uio_info *uinfo;
  896. int ret = 0;
  897. if (!udev)
  898. return -ENOMEM;
  899. uinfo = &udev->cnic_uinfo;
  900. uinfo->mem[0].addr = pci_resource_start(dev->pcidev, 0);
  901. uinfo->mem[0].internal_addr = dev->regview;
  902. uinfo->mem[0].memtype = UIO_MEM_PHYS;
  903. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
  904. uinfo->mem[0].size = MB_GET_CID_ADDR(TX_TSS_CID +
  905. TX_MAX_TSS_RINGS + 1);
  906. uinfo->mem[1].addr = (unsigned long) cp->status_blk.gen &
  907. PAGE_MASK;
  908. if (cp->ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX)
  909. uinfo->mem[1].size = BNX2_SBLK_MSIX_ALIGN_SIZE * 9;
  910. else
  911. uinfo->mem[1].size = BNX2_SBLK_MSIX_ALIGN_SIZE;
  912. uinfo->name = "bnx2_cnic";
  913. } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
  914. uinfo->mem[0].size = pci_resource_len(dev->pcidev, 0);
  915. uinfo->mem[1].addr = (unsigned long) cp->bnx2x_def_status_blk &
  916. PAGE_MASK;
  917. uinfo->mem[1].size = sizeof(*cp->bnx2x_def_status_blk);
  918. uinfo->name = "bnx2x_cnic";
  919. }
  920. uinfo->mem[1].memtype = UIO_MEM_LOGICAL;
  921. uinfo->mem[2].addr = (unsigned long) udev->l2_ring;
  922. uinfo->mem[2].size = udev->l2_ring_size;
  923. uinfo->mem[2].memtype = UIO_MEM_LOGICAL;
  924. uinfo->mem[3].addr = (unsigned long) udev->l2_buf;
  925. uinfo->mem[3].size = udev->l2_buf_size;
  926. uinfo->mem[3].memtype = UIO_MEM_LOGICAL;
  927. uinfo->version = CNIC_MODULE_VERSION;
  928. uinfo->irq = UIO_IRQ_CUSTOM;
  929. uinfo->open = cnic_uio_open;
  930. uinfo->release = cnic_uio_close;
  931. if (udev->uio_dev == -1) {
  932. if (!uinfo->priv) {
  933. uinfo->priv = udev;
  934. ret = uio_register_device(&udev->pdev->dev, uinfo);
  935. }
  936. } else {
  937. cnic_init_rings(dev);
  938. }
  939. return ret;
  940. }
  941. static int cnic_alloc_bnx2_resc(struct cnic_dev *dev)
  942. {
  943. struct cnic_local *cp = dev->cnic_priv;
  944. int ret;
  945. ret = cnic_alloc_dma(dev, &cp->kwq_info, KWQ_PAGE_CNT, 1);
  946. if (ret)
  947. goto error;
  948. cp->kwq = (struct kwqe **) cp->kwq_info.pg_arr;
  949. ret = cnic_alloc_kcq(dev, &cp->kcq1, true);
  950. if (ret)
  951. goto error;
  952. ret = cnic_alloc_context(dev);
  953. if (ret)
  954. goto error;
  955. ret = cnic_alloc_uio_rings(dev, 2);
  956. if (ret)
  957. goto error;
  958. ret = cnic_init_uio(dev);
  959. if (ret)
  960. goto error;
  961. return 0;
  962. error:
  963. cnic_free_resc(dev);
  964. return ret;
  965. }
  966. static int cnic_alloc_bnx2x_context(struct cnic_dev *dev)
  967. {
  968. struct cnic_local *cp = dev->cnic_priv;
  969. int ctx_blk_size = cp->ethdev->ctx_blk_size;
  970. int total_mem, blks, i;
  971. total_mem = BNX2X_CONTEXT_MEM_SIZE * cp->max_cid_space;
  972. blks = total_mem / ctx_blk_size;
  973. if (total_mem % ctx_blk_size)
  974. blks++;
  975. if (blks > cp->ethdev->ctx_tbl_len)
  976. return -ENOMEM;
  977. cp->ctx_arr = kcalloc(blks, sizeof(struct cnic_ctx), GFP_KERNEL);
  978. if (cp->ctx_arr == NULL)
  979. return -ENOMEM;
  980. cp->ctx_blks = blks;
  981. cp->ctx_blk_size = ctx_blk_size;
  982. if (!BNX2X_CHIP_IS_57710(cp->chip_id))
  983. cp->ctx_align = 0;
  984. else
  985. cp->ctx_align = ctx_blk_size;
  986. cp->cids_per_blk = ctx_blk_size / BNX2X_CONTEXT_MEM_SIZE;
  987. for (i = 0; i < blks; i++) {
  988. cp->ctx_arr[i].ctx =
  989. dma_alloc_coherent(&dev->pcidev->dev, cp->ctx_blk_size,
  990. &cp->ctx_arr[i].mapping,
  991. GFP_KERNEL);
  992. if (cp->ctx_arr[i].ctx == NULL)
  993. return -ENOMEM;
  994. if (cp->ctx_align && cp->ctx_blk_size == ctx_blk_size) {
  995. if (cp->ctx_arr[i].mapping & (cp->ctx_align - 1)) {
  996. cnic_free_context(dev);
  997. cp->ctx_blk_size += cp->ctx_align;
  998. i = -1;
  999. continue;
  1000. }
  1001. }
  1002. }
  1003. return 0;
  1004. }
  1005. static int cnic_alloc_bnx2x_resc(struct cnic_dev *dev)
  1006. {
  1007. struct cnic_local *cp = dev->cnic_priv;
  1008. struct cnic_eth_dev *ethdev = cp->ethdev;
  1009. u32 start_cid = ethdev->starting_cid;
  1010. int i, j, n, ret, pages;
  1011. struct cnic_dma *kwq_16_dma = &cp->kwq_16_data_info;
  1012. cp->max_cid_space = MAX_ISCSI_TBL_SZ;
  1013. cp->iscsi_start_cid = start_cid;
  1014. cp->fcoe_start_cid = start_cid + MAX_ISCSI_TBL_SZ;
  1015. if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id)) {
  1016. cp->max_cid_space += dev->max_fcoe_conn;
  1017. cp->fcoe_init_cid = ethdev->fcoe_init_cid;
  1018. if (!cp->fcoe_init_cid)
  1019. cp->fcoe_init_cid = 0x10;
  1020. }
  1021. cp->iscsi_tbl = kzalloc(sizeof(struct cnic_iscsi) * MAX_ISCSI_TBL_SZ,
  1022. GFP_KERNEL);
  1023. if (!cp->iscsi_tbl)
  1024. goto error;
  1025. cp->ctx_tbl = kzalloc(sizeof(struct cnic_context) *
  1026. cp->max_cid_space, GFP_KERNEL);
  1027. if (!cp->ctx_tbl)
  1028. goto error;
  1029. for (i = 0; i < MAX_ISCSI_TBL_SZ; i++) {
  1030. cp->ctx_tbl[i].proto.iscsi = &cp->iscsi_tbl[i];
  1031. cp->ctx_tbl[i].ulp_proto_id = CNIC_ULP_ISCSI;
  1032. }
  1033. for (i = MAX_ISCSI_TBL_SZ; i < cp->max_cid_space; i++)
  1034. cp->ctx_tbl[i].ulp_proto_id = CNIC_ULP_FCOE;
  1035. pages = PAGE_ALIGN(cp->max_cid_space * CNIC_KWQ16_DATA_SIZE) /
  1036. PAGE_SIZE;
  1037. ret = cnic_alloc_dma(dev, kwq_16_dma, pages, 0);
  1038. if (ret)
  1039. return -ENOMEM;
  1040. n = PAGE_SIZE / CNIC_KWQ16_DATA_SIZE;
  1041. for (i = 0, j = 0; i < cp->max_cid_space; i++) {
  1042. long off = CNIC_KWQ16_DATA_SIZE * (i % n);
  1043. cp->ctx_tbl[i].kwqe_data = kwq_16_dma->pg_arr[j] + off;
  1044. cp->ctx_tbl[i].kwqe_data_mapping = kwq_16_dma->pg_map_arr[j] +
  1045. off;
  1046. if ((i % n) == (n - 1))
  1047. j++;
  1048. }
  1049. ret = cnic_alloc_kcq(dev, &cp->kcq1, false);
  1050. if (ret)
  1051. goto error;
  1052. if (CNIC_SUPPORTS_FCOE(cp)) {
  1053. ret = cnic_alloc_kcq(dev, &cp->kcq2, true);
  1054. if (ret)
  1055. goto error;
  1056. }
  1057. pages = PAGE_ALIGN(BNX2X_ISCSI_GLB_BUF_SIZE) / PAGE_SIZE;
  1058. ret = cnic_alloc_dma(dev, &cp->gbl_buf_info, pages, 0);
  1059. if (ret)
  1060. goto error;
  1061. ret = cnic_alloc_bnx2x_context(dev);
  1062. if (ret)
  1063. goto error;
  1064. if (cp->ethdev->drv_state & CNIC_DRV_STATE_NO_ISCSI)
  1065. return 0;
  1066. cp->bnx2x_def_status_blk = cp->ethdev->irq_arr[1].status_blk;
  1067. cp->l2_rx_ring_size = 15;
  1068. ret = cnic_alloc_uio_rings(dev, 4);
  1069. if (ret)
  1070. goto error;
  1071. ret = cnic_init_uio(dev);
  1072. if (ret)
  1073. goto error;
  1074. return 0;
  1075. error:
  1076. cnic_free_resc(dev);
  1077. return -ENOMEM;
  1078. }
  1079. static inline u32 cnic_kwq_avail(struct cnic_local *cp)
  1080. {
  1081. return cp->max_kwq_idx -
  1082. ((cp->kwq_prod_idx - cp->kwq_con_idx) & cp->max_kwq_idx);
  1083. }
  1084. static int cnic_submit_bnx2_kwqes(struct cnic_dev *dev, struct kwqe *wqes[],
  1085. u32 num_wqes)
  1086. {
  1087. struct cnic_local *cp = dev->cnic_priv;
  1088. struct kwqe *prod_qe;
  1089. u16 prod, sw_prod, i;
  1090. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  1091. return -EAGAIN; /* bnx2 is down */
  1092. spin_lock_bh(&cp->cnic_ulp_lock);
  1093. if (num_wqes > cnic_kwq_avail(cp) &&
  1094. !test_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags)) {
  1095. spin_unlock_bh(&cp->cnic_ulp_lock);
  1096. return -EAGAIN;
  1097. }
  1098. clear_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags);
  1099. prod = cp->kwq_prod_idx;
  1100. sw_prod = prod & MAX_KWQ_IDX;
  1101. for (i = 0; i < num_wqes; i++) {
  1102. prod_qe = &cp->kwq[KWQ_PG(sw_prod)][KWQ_IDX(sw_prod)];
  1103. memcpy(prod_qe, wqes[i], sizeof(struct kwqe));
  1104. prod++;
  1105. sw_prod = prod & MAX_KWQ_IDX;
  1106. }
  1107. cp->kwq_prod_idx = prod;
  1108. CNIC_WR16(dev, cp->kwq_io_addr, cp->kwq_prod_idx);
  1109. spin_unlock_bh(&cp->cnic_ulp_lock);
  1110. return 0;
  1111. }
  1112. static void *cnic_get_kwqe_16_data(struct cnic_local *cp, u32 l5_cid,
  1113. union l5cm_specific_data *l5_data)
  1114. {
  1115. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1116. dma_addr_t map;
  1117. map = ctx->kwqe_data_mapping;
  1118. l5_data->phy_address.lo = (u64) map & 0xffffffff;
  1119. l5_data->phy_address.hi = (u64) map >> 32;
  1120. return ctx->kwqe_data;
  1121. }
  1122. static int cnic_submit_kwqe_16(struct cnic_dev *dev, u32 cmd, u32 cid,
  1123. u32 type, union l5cm_specific_data *l5_data)
  1124. {
  1125. struct cnic_local *cp = dev->cnic_priv;
  1126. struct l5cm_spe kwqe;
  1127. struct kwqe_16 *kwq[1];
  1128. u16 type_16;
  1129. int ret;
  1130. kwqe.hdr.conn_and_cmd_data =
  1131. cpu_to_le32(((cmd << SPE_HDR_CMD_ID_SHIFT) |
  1132. BNX2X_HW_CID(cp, cid)));
  1133. type_16 = (type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
  1134. type_16 |= (cp->pfid << SPE_HDR_FUNCTION_ID_SHIFT) &
  1135. SPE_HDR_FUNCTION_ID;
  1136. kwqe.hdr.type = cpu_to_le16(type_16);
  1137. kwqe.hdr.reserved1 = 0;
  1138. kwqe.data.phy_address.lo = cpu_to_le32(l5_data->phy_address.lo);
  1139. kwqe.data.phy_address.hi = cpu_to_le32(l5_data->phy_address.hi);
  1140. kwq[0] = (struct kwqe_16 *) &kwqe;
  1141. spin_lock_bh(&cp->cnic_ulp_lock);
  1142. ret = cp->ethdev->drv_submit_kwqes_16(dev->netdev, kwq, 1);
  1143. spin_unlock_bh(&cp->cnic_ulp_lock);
  1144. if (ret == 1)
  1145. return 0;
  1146. return ret;
  1147. }
  1148. static void cnic_reply_bnx2x_kcqes(struct cnic_dev *dev, int ulp_type,
  1149. struct kcqe *cqes[], u32 num_cqes)
  1150. {
  1151. struct cnic_local *cp = dev->cnic_priv;
  1152. struct cnic_ulp_ops *ulp_ops;
  1153. rcu_read_lock();
  1154. ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
  1155. if (likely(ulp_ops)) {
  1156. ulp_ops->indicate_kcqes(cp->ulp_handle[ulp_type],
  1157. cqes, num_cqes);
  1158. }
  1159. rcu_read_unlock();
  1160. }
  1161. static void cnic_bnx2x_set_tcp_options(struct cnic_dev *dev, int time_stamps,
  1162. int en_tcp_dack)
  1163. {
  1164. struct cnic_local *cp = dev->cnic_priv;
  1165. struct bnx2x *bp = netdev_priv(dev->netdev);
  1166. u8 xstorm_flags = XSTORM_L5CM_TCP_FLAGS_WND_SCL_EN;
  1167. u16 tstorm_flags = 0;
  1168. if (time_stamps) {
  1169. xstorm_flags |= XSTORM_L5CM_TCP_FLAGS_TS_ENABLED;
  1170. tstorm_flags |= TSTORM_L5CM_TCP_FLAGS_TS_ENABLED;
  1171. }
  1172. if (en_tcp_dack)
  1173. tstorm_flags |= TSTORM_L5CM_TCP_FLAGS_DELAYED_ACK_EN;
  1174. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1175. XSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(cp->pfid), xstorm_flags);
  1176. CNIC_WR16(dev, BAR_TSTRORM_INTMEM +
  1177. TSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(cp->pfid), tstorm_flags);
  1178. }
  1179. static int cnic_bnx2x_iscsi_init1(struct cnic_dev *dev, struct kwqe *kwqe)
  1180. {
  1181. struct cnic_local *cp = dev->cnic_priv;
  1182. struct bnx2x *bp = netdev_priv(dev->netdev);
  1183. struct iscsi_kwqe_init1 *req1 = (struct iscsi_kwqe_init1 *) kwqe;
  1184. int hq_bds, pages;
  1185. u32 pfid = cp->pfid;
  1186. cp->num_iscsi_tasks = req1->num_tasks_per_conn;
  1187. cp->num_ccells = req1->num_ccells_per_conn;
  1188. cp->task_array_size = BNX2X_ISCSI_TASK_CONTEXT_SIZE *
  1189. cp->num_iscsi_tasks;
  1190. cp->r2tq_size = cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS *
  1191. BNX2X_ISCSI_R2TQE_SIZE;
  1192. cp->hq_size = cp->num_ccells * BNX2X_ISCSI_HQ_BD_SIZE;
  1193. pages = PAGE_ALIGN(cp->hq_size) / PAGE_SIZE;
  1194. hq_bds = pages * (PAGE_SIZE / BNX2X_ISCSI_HQ_BD_SIZE);
  1195. cp->num_cqs = req1->num_cqs;
  1196. if (!dev->max_iscsi_conn)
  1197. return 0;
  1198. /* init Tstorm RAM */
  1199. CNIC_WR16(dev, BAR_TSTRORM_INTMEM + TSTORM_ISCSI_RQ_SIZE_OFFSET(pfid),
  1200. req1->rq_num_wqes);
  1201. CNIC_WR16(dev, BAR_TSTRORM_INTMEM + TSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1202. PAGE_SIZE);
  1203. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1204. TSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
  1205. CNIC_WR16(dev, BAR_TSTRORM_INTMEM +
  1206. TSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1207. req1->num_tasks_per_conn);
  1208. /* init Ustorm RAM */
  1209. CNIC_WR16(dev, BAR_USTRORM_INTMEM +
  1210. USTORM_ISCSI_RQ_BUFFER_SIZE_OFFSET(pfid),
  1211. req1->rq_buffer_size);
  1212. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1213. PAGE_SIZE);
  1214. CNIC_WR8(dev, BAR_USTRORM_INTMEM +
  1215. USTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
  1216. CNIC_WR16(dev, BAR_USTRORM_INTMEM +
  1217. USTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1218. req1->num_tasks_per_conn);
  1219. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_RQ_SIZE_OFFSET(pfid),
  1220. req1->rq_num_wqes);
  1221. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_CQ_SIZE_OFFSET(pfid),
  1222. req1->cq_num_wqes);
  1223. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_R2TQ_SIZE_OFFSET(pfid),
  1224. cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS);
  1225. /* init Xstorm RAM */
  1226. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1227. PAGE_SIZE);
  1228. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1229. XSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
  1230. CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
  1231. XSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1232. req1->num_tasks_per_conn);
  1233. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_HQ_SIZE_OFFSET(pfid),
  1234. hq_bds);
  1235. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_SQ_SIZE_OFFSET(pfid),
  1236. req1->num_tasks_per_conn);
  1237. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_R2TQ_SIZE_OFFSET(pfid),
  1238. cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS);
  1239. /* init Cstorm RAM */
  1240. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1241. PAGE_SIZE);
  1242. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  1243. CSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
  1244. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  1245. CSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1246. req1->num_tasks_per_conn);
  1247. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_CQ_SIZE_OFFSET(pfid),
  1248. req1->cq_num_wqes);
  1249. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_HQ_SIZE_OFFSET(pfid),
  1250. hq_bds);
  1251. cnic_bnx2x_set_tcp_options(dev,
  1252. req1->flags & ISCSI_KWQE_INIT1_TIME_STAMPS_ENABLE,
  1253. req1->flags & ISCSI_KWQE_INIT1_DELAYED_ACK_ENABLE);
  1254. return 0;
  1255. }
  1256. static int cnic_bnx2x_iscsi_init2(struct cnic_dev *dev, struct kwqe *kwqe)
  1257. {
  1258. struct iscsi_kwqe_init2 *req2 = (struct iscsi_kwqe_init2 *) kwqe;
  1259. struct cnic_local *cp = dev->cnic_priv;
  1260. struct bnx2x *bp = netdev_priv(dev->netdev);
  1261. u32 pfid = cp->pfid;
  1262. struct iscsi_kcqe kcqe;
  1263. struct kcqe *cqes[1];
  1264. memset(&kcqe, 0, sizeof(kcqe));
  1265. if (!dev->max_iscsi_conn) {
  1266. kcqe.completion_status =
  1267. ISCSI_KCQE_COMPLETION_STATUS_ISCSI_NOT_SUPPORTED;
  1268. goto done;
  1269. }
  1270. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  1271. TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid), req2->error_bit_map[0]);
  1272. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  1273. TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid) + 4,
  1274. req2->error_bit_map[1]);
  1275. CNIC_WR16(dev, BAR_USTRORM_INTMEM +
  1276. USTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfid), req2->max_cq_sqn);
  1277. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  1278. USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid), req2->error_bit_map[0]);
  1279. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  1280. USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid) + 4,
  1281. req2->error_bit_map[1]);
  1282. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  1283. CSTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfid), req2->max_cq_sqn);
  1284. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
  1285. done:
  1286. kcqe.op_code = ISCSI_KCQE_OPCODE_INIT;
  1287. cqes[0] = (struct kcqe *) &kcqe;
  1288. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
  1289. return 0;
  1290. }
  1291. static void cnic_free_bnx2x_conn_resc(struct cnic_dev *dev, u32 l5_cid)
  1292. {
  1293. struct cnic_local *cp = dev->cnic_priv;
  1294. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1295. if (ctx->ulp_proto_id == CNIC_ULP_ISCSI) {
  1296. struct cnic_iscsi *iscsi = ctx->proto.iscsi;
  1297. cnic_free_dma(dev, &iscsi->hq_info);
  1298. cnic_free_dma(dev, &iscsi->r2tq_info);
  1299. cnic_free_dma(dev, &iscsi->task_array_info);
  1300. cnic_free_id(&cp->cid_tbl, ctx->cid);
  1301. } else {
  1302. cnic_free_id(&cp->fcoe_cid_tbl, ctx->cid);
  1303. }
  1304. ctx->cid = 0;
  1305. }
  1306. static int cnic_alloc_bnx2x_conn_resc(struct cnic_dev *dev, u32 l5_cid)
  1307. {
  1308. u32 cid;
  1309. int ret, pages;
  1310. struct cnic_local *cp = dev->cnic_priv;
  1311. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1312. struct cnic_iscsi *iscsi = ctx->proto.iscsi;
  1313. if (ctx->ulp_proto_id == CNIC_ULP_FCOE) {
  1314. cid = cnic_alloc_new_id(&cp->fcoe_cid_tbl);
  1315. if (cid == -1) {
  1316. ret = -ENOMEM;
  1317. goto error;
  1318. }
  1319. ctx->cid = cid;
  1320. return 0;
  1321. }
  1322. cid = cnic_alloc_new_id(&cp->cid_tbl);
  1323. if (cid == -1) {
  1324. ret = -ENOMEM;
  1325. goto error;
  1326. }
  1327. ctx->cid = cid;
  1328. pages = PAGE_ALIGN(cp->task_array_size) / PAGE_SIZE;
  1329. ret = cnic_alloc_dma(dev, &iscsi->task_array_info, pages, 1);
  1330. if (ret)
  1331. goto error;
  1332. pages = PAGE_ALIGN(cp->r2tq_size) / PAGE_SIZE;
  1333. ret = cnic_alloc_dma(dev, &iscsi->r2tq_info, pages, 1);
  1334. if (ret)
  1335. goto error;
  1336. pages = PAGE_ALIGN(cp->hq_size) / PAGE_SIZE;
  1337. ret = cnic_alloc_dma(dev, &iscsi->hq_info, pages, 1);
  1338. if (ret)
  1339. goto error;
  1340. return 0;
  1341. error:
  1342. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1343. return ret;
  1344. }
  1345. static void *cnic_get_bnx2x_ctx(struct cnic_dev *dev, u32 cid, int init,
  1346. struct regpair *ctx_addr)
  1347. {
  1348. struct cnic_local *cp = dev->cnic_priv;
  1349. struct cnic_eth_dev *ethdev = cp->ethdev;
  1350. int blk = (cid - ethdev->starting_cid) / cp->cids_per_blk;
  1351. int off = (cid - ethdev->starting_cid) % cp->cids_per_blk;
  1352. unsigned long align_off = 0;
  1353. dma_addr_t ctx_map;
  1354. void *ctx;
  1355. if (cp->ctx_align) {
  1356. unsigned long mask = cp->ctx_align - 1;
  1357. if (cp->ctx_arr[blk].mapping & mask)
  1358. align_off = cp->ctx_align -
  1359. (cp->ctx_arr[blk].mapping & mask);
  1360. }
  1361. ctx_map = cp->ctx_arr[blk].mapping + align_off +
  1362. (off * BNX2X_CONTEXT_MEM_SIZE);
  1363. ctx = cp->ctx_arr[blk].ctx + align_off +
  1364. (off * BNX2X_CONTEXT_MEM_SIZE);
  1365. if (init)
  1366. memset(ctx, 0, BNX2X_CONTEXT_MEM_SIZE);
  1367. ctx_addr->lo = ctx_map & 0xffffffff;
  1368. ctx_addr->hi = (u64) ctx_map >> 32;
  1369. return ctx;
  1370. }
  1371. static int cnic_setup_bnx2x_ctx(struct cnic_dev *dev, struct kwqe *wqes[],
  1372. u32 num)
  1373. {
  1374. struct cnic_local *cp = dev->cnic_priv;
  1375. struct iscsi_kwqe_conn_offload1 *req1 =
  1376. (struct iscsi_kwqe_conn_offload1 *) wqes[0];
  1377. struct iscsi_kwqe_conn_offload2 *req2 =
  1378. (struct iscsi_kwqe_conn_offload2 *) wqes[1];
  1379. struct iscsi_kwqe_conn_offload3 *req3;
  1380. struct cnic_context *ctx = &cp->ctx_tbl[req1->iscsi_conn_id];
  1381. struct cnic_iscsi *iscsi = ctx->proto.iscsi;
  1382. u32 cid = ctx->cid;
  1383. u32 hw_cid = BNX2X_HW_CID(cp, cid);
  1384. struct iscsi_context *ictx;
  1385. struct regpair context_addr;
  1386. int i, j, n = 2, n_max;
  1387. u8 port = CNIC_PORT(cp);
  1388. ctx->ctx_flags = 0;
  1389. if (!req2->num_additional_wqes)
  1390. return -EINVAL;
  1391. n_max = req2->num_additional_wqes + 2;
  1392. ictx = cnic_get_bnx2x_ctx(dev, cid, 1, &context_addr);
  1393. if (ictx == NULL)
  1394. return -ENOMEM;
  1395. req3 = (struct iscsi_kwqe_conn_offload3 *) wqes[n++];
  1396. ictx->xstorm_ag_context.hq_prod = 1;
  1397. ictx->xstorm_st_context.iscsi.first_burst_length =
  1398. ISCSI_DEF_FIRST_BURST_LEN;
  1399. ictx->xstorm_st_context.iscsi.max_send_pdu_length =
  1400. ISCSI_DEF_MAX_RECV_SEG_LEN;
  1401. ictx->xstorm_st_context.iscsi.sq_pbl_base.lo =
  1402. req1->sq_page_table_addr_lo;
  1403. ictx->xstorm_st_context.iscsi.sq_pbl_base.hi =
  1404. req1->sq_page_table_addr_hi;
  1405. ictx->xstorm_st_context.iscsi.sq_curr_pbe.lo = req2->sq_first_pte.hi;
  1406. ictx->xstorm_st_context.iscsi.sq_curr_pbe.hi = req2->sq_first_pte.lo;
  1407. ictx->xstorm_st_context.iscsi.hq_pbl_base.lo =
  1408. iscsi->hq_info.pgtbl_map & 0xffffffff;
  1409. ictx->xstorm_st_context.iscsi.hq_pbl_base.hi =
  1410. (u64) iscsi->hq_info.pgtbl_map >> 32;
  1411. ictx->xstorm_st_context.iscsi.hq_curr_pbe_base.lo =
  1412. iscsi->hq_info.pgtbl[0];
  1413. ictx->xstorm_st_context.iscsi.hq_curr_pbe_base.hi =
  1414. iscsi->hq_info.pgtbl[1];
  1415. ictx->xstorm_st_context.iscsi.r2tq_pbl_base.lo =
  1416. iscsi->r2tq_info.pgtbl_map & 0xffffffff;
  1417. ictx->xstorm_st_context.iscsi.r2tq_pbl_base.hi =
  1418. (u64) iscsi->r2tq_info.pgtbl_map >> 32;
  1419. ictx->xstorm_st_context.iscsi.r2tq_curr_pbe_base.lo =
  1420. iscsi->r2tq_info.pgtbl[0];
  1421. ictx->xstorm_st_context.iscsi.r2tq_curr_pbe_base.hi =
  1422. iscsi->r2tq_info.pgtbl[1];
  1423. ictx->xstorm_st_context.iscsi.task_pbl_base.lo =
  1424. iscsi->task_array_info.pgtbl_map & 0xffffffff;
  1425. ictx->xstorm_st_context.iscsi.task_pbl_base.hi =
  1426. (u64) iscsi->task_array_info.pgtbl_map >> 32;
  1427. ictx->xstorm_st_context.iscsi.task_pbl_cache_idx =
  1428. BNX2X_ISCSI_PBL_NOT_CACHED;
  1429. ictx->xstorm_st_context.iscsi.flags.flags |=
  1430. XSTORM_ISCSI_CONTEXT_FLAGS_B_IMMEDIATE_DATA;
  1431. ictx->xstorm_st_context.iscsi.flags.flags |=
  1432. XSTORM_ISCSI_CONTEXT_FLAGS_B_INITIAL_R2T;
  1433. ictx->xstorm_st_context.common.ethernet.reserved_vlan_type =
  1434. ETH_P_8021Q;
  1435. if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id) &&
  1436. cp->port_mode == CHIP_2_PORT_MODE) {
  1437. port = 0;
  1438. }
  1439. ictx->xstorm_st_context.common.flags =
  1440. 1 << XSTORM_COMMON_CONTEXT_SECTION_PHYSQ_INITIALIZED_SHIFT;
  1441. ictx->xstorm_st_context.common.flags =
  1442. port << XSTORM_COMMON_CONTEXT_SECTION_PBF_PORT_SHIFT;
  1443. ictx->tstorm_st_context.iscsi.hdr_bytes_2_fetch = ISCSI_HEADER_SIZE;
  1444. /* TSTORM requires the base address of RQ DB & not PTE */
  1445. ictx->tstorm_st_context.iscsi.rq_db_phy_addr.lo =
  1446. req2->rq_page_table_addr_lo & PAGE_MASK;
  1447. ictx->tstorm_st_context.iscsi.rq_db_phy_addr.hi =
  1448. req2->rq_page_table_addr_hi;
  1449. ictx->tstorm_st_context.iscsi.iscsi_conn_id = req1->iscsi_conn_id;
  1450. ictx->tstorm_st_context.tcp.cwnd = 0x5A8;
  1451. ictx->tstorm_st_context.tcp.flags2 |=
  1452. TSTORM_TCP_ST_CONTEXT_SECTION_DA_EN;
  1453. ictx->tstorm_st_context.tcp.ooo_support_mode =
  1454. TCP_TSTORM_OOO_DROP_AND_PROC_ACK;
  1455. ictx->timers_context.flags |= TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG;
  1456. ictx->ustorm_st_context.ring.rq.pbl_base.lo =
  1457. req2->rq_page_table_addr_lo;
  1458. ictx->ustorm_st_context.ring.rq.pbl_base.hi =
  1459. req2->rq_page_table_addr_hi;
  1460. ictx->ustorm_st_context.ring.rq.curr_pbe.lo = req3->qp_first_pte[0].hi;
  1461. ictx->ustorm_st_context.ring.rq.curr_pbe.hi = req3->qp_first_pte[0].lo;
  1462. ictx->ustorm_st_context.ring.r2tq.pbl_base.lo =
  1463. iscsi->r2tq_info.pgtbl_map & 0xffffffff;
  1464. ictx->ustorm_st_context.ring.r2tq.pbl_base.hi =
  1465. (u64) iscsi->r2tq_info.pgtbl_map >> 32;
  1466. ictx->ustorm_st_context.ring.r2tq.curr_pbe.lo =
  1467. iscsi->r2tq_info.pgtbl[0];
  1468. ictx->ustorm_st_context.ring.r2tq.curr_pbe.hi =
  1469. iscsi->r2tq_info.pgtbl[1];
  1470. ictx->ustorm_st_context.ring.cq_pbl_base.lo =
  1471. req1->cq_page_table_addr_lo;
  1472. ictx->ustorm_st_context.ring.cq_pbl_base.hi =
  1473. req1->cq_page_table_addr_hi;
  1474. ictx->ustorm_st_context.ring.cq[0].cq_sn = ISCSI_INITIAL_SN;
  1475. ictx->ustorm_st_context.ring.cq[0].curr_pbe.lo = req2->cq_first_pte.hi;
  1476. ictx->ustorm_st_context.ring.cq[0].curr_pbe.hi = req2->cq_first_pte.lo;
  1477. ictx->ustorm_st_context.task_pbe_cache_index =
  1478. BNX2X_ISCSI_PBL_NOT_CACHED;
  1479. ictx->ustorm_st_context.task_pdu_cache_index =
  1480. BNX2X_ISCSI_PDU_HEADER_NOT_CACHED;
  1481. for (i = 1, j = 1; i < cp->num_cqs; i++, j++) {
  1482. if (j == 3) {
  1483. if (n >= n_max)
  1484. break;
  1485. req3 = (struct iscsi_kwqe_conn_offload3 *) wqes[n++];
  1486. j = 0;
  1487. }
  1488. ictx->ustorm_st_context.ring.cq[i].cq_sn = ISCSI_INITIAL_SN;
  1489. ictx->ustorm_st_context.ring.cq[i].curr_pbe.lo =
  1490. req3->qp_first_pte[j].hi;
  1491. ictx->ustorm_st_context.ring.cq[i].curr_pbe.hi =
  1492. req3->qp_first_pte[j].lo;
  1493. }
  1494. ictx->ustorm_st_context.task_pbl_base.lo =
  1495. iscsi->task_array_info.pgtbl_map & 0xffffffff;
  1496. ictx->ustorm_st_context.task_pbl_base.hi =
  1497. (u64) iscsi->task_array_info.pgtbl_map >> 32;
  1498. ictx->ustorm_st_context.tce_phy_addr.lo =
  1499. iscsi->task_array_info.pgtbl[0];
  1500. ictx->ustorm_st_context.tce_phy_addr.hi =
  1501. iscsi->task_array_info.pgtbl[1];
  1502. ictx->ustorm_st_context.iscsi_conn_id = req1->iscsi_conn_id;
  1503. ictx->ustorm_st_context.num_cqs = cp->num_cqs;
  1504. ictx->ustorm_st_context.negotiated_rx |= ISCSI_DEF_MAX_RECV_SEG_LEN;
  1505. ictx->ustorm_st_context.negotiated_rx_and_flags |=
  1506. ISCSI_DEF_MAX_BURST_LEN;
  1507. ictx->ustorm_st_context.negotiated_rx |=
  1508. ISCSI_DEFAULT_MAX_OUTSTANDING_R2T <<
  1509. USTORM_ISCSI_ST_CONTEXT_MAX_OUTSTANDING_R2TS_SHIFT;
  1510. ictx->cstorm_st_context.hq_pbl_base.lo =
  1511. iscsi->hq_info.pgtbl_map & 0xffffffff;
  1512. ictx->cstorm_st_context.hq_pbl_base.hi =
  1513. (u64) iscsi->hq_info.pgtbl_map >> 32;
  1514. ictx->cstorm_st_context.hq_curr_pbe.lo = iscsi->hq_info.pgtbl[0];
  1515. ictx->cstorm_st_context.hq_curr_pbe.hi = iscsi->hq_info.pgtbl[1];
  1516. ictx->cstorm_st_context.task_pbl_base.lo =
  1517. iscsi->task_array_info.pgtbl_map & 0xffffffff;
  1518. ictx->cstorm_st_context.task_pbl_base.hi =
  1519. (u64) iscsi->task_array_info.pgtbl_map >> 32;
  1520. /* CSTORM and USTORM initialization is different, CSTORM requires
  1521. * CQ DB base & not PTE addr */
  1522. ictx->cstorm_st_context.cq_db_base.lo =
  1523. req1->cq_page_table_addr_lo & PAGE_MASK;
  1524. ictx->cstorm_st_context.cq_db_base.hi = req1->cq_page_table_addr_hi;
  1525. ictx->cstorm_st_context.iscsi_conn_id = req1->iscsi_conn_id;
  1526. ictx->cstorm_st_context.cq_proc_en_bit_map = (1 << cp->num_cqs) - 1;
  1527. for (i = 0; i < cp->num_cqs; i++) {
  1528. ictx->cstorm_st_context.cq_c_prod_sqn_arr.sqn[i] =
  1529. ISCSI_INITIAL_SN;
  1530. ictx->cstorm_st_context.cq_c_sqn_2_notify_arr.sqn[i] =
  1531. ISCSI_INITIAL_SN;
  1532. }
  1533. ictx->xstorm_ag_context.cdu_reserved =
  1534. CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_XCM_AG,
  1535. ISCSI_CONNECTION_TYPE);
  1536. ictx->ustorm_ag_context.cdu_usage =
  1537. CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_UCM_AG,
  1538. ISCSI_CONNECTION_TYPE);
  1539. return 0;
  1540. }
  1541. static int cnic_bnx2x_iscsi_ofld1(struct cnic_dev *dev, struct kwqe *wqes[],
  1542. u32 num, int *work)
  1543. {
  1544. struct iscsi_kwqe_conn_offload1 *req1;
  1545. struct iscsi_kwqe_conn_offload2 *req2;
  1546. struct cnic_local *cp = dev->cnic_priv;
  1547. struct cnic_context *ctx;
  1548. struct iscsi_kcqe kcqe;
  1549. struct kcqe *cqes[1];
  1550. u32 l5_cid;
  1551. int ret = 0;
  1552. if (num < 2) {
  1553. *work = num;
  1554. return -EINVAL;
  1555. }
  1556. req1 = (struct iscsi_kwqe_conn_offload1 *) wqes[0];
  1557. req2 = (struct iscsi_kwqe_conn_offload2 *) wqes[1];
  1558. if ((num - 2) < req2->num_additional_wqes) {
  1559. *work = num;
  1560. return -EINVAL;
  1561. }
  1562. *work = 2 + req2->num_additional_wqes;
  1563. l5_cid = req1->iscsi_conn_id;
  1564. if (l5_cid >= MAX_ISCSI_TBL_SZ)
  1565. return -EINVAL;
  1566. memset(&kcqe, 0, sizeof(kcqe));
  1567. kcqe.op_code = ISCSI_KCQE_OPCODE_OFFLOAD_CONN;
  1568. kcqe.iscsi_conn_id = l5_cid;
  1569. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE;
  1570. ctx = &cp->ctx_tbl[l5_cid];
  1571. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags)) {
  1572. kcqe.completion_status =
  1573. ISCSI_KCQE_COMPLETION_STATUS_CID_BUSY;
  1574. goto done;
  1575. }
  1576. if (atomic_inc_return(&cp->iscsi_conn) > dev->max_iscsi_conn) {
  1577. atomic_dec(&cp->iscsi_conn);
  1578. goto done;
  1579. }
  1580. ret = cnic_alloc_bnx2x_conn_resc(dev, l5_cid);
  1581. if (ret) {
  1582. atomic_dec(&cp->iscsi_conn);
  1583. ret = 0;
  1584. goto done;
  1585. }
  1586. ret = cnic_setup_bnx2x_ctx(dev, wqes, num);
  1587. if (ret < 0) {
  1588. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1589. atomic_dec(&cp->iscsi_conn);
  1590. goto done;
  1591. }
  1592. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
  1593. kcqe.iscsi_conn_context_id = BNX2X_HW_CID(cp, cp->ctx_tbl[l5_cid].cid);
  1594. done:
  1595. cqes[0] = (struct kcqe *) &kcqe;
  1596. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
  1597. return 0;
  1598. }
  1599. static int cnic_bnx2x_iscsi_update(struct cnic_dev *dev, struct kwqe *kwqe)
  1600. {
  1601. struct cnic_local *cp = dev->cnic_priv;
  1602. struct iscsi_kwqe_conn_update *req =
  1603. (struct iscsi_kwqe_conn_update *) kwqe;
  1604. void *data;
  1605. union l5cm_specific_data l5_data;
  1606. u32 l5_cid, cid = BNX2X_SW_CID(req->context_id);
  1607. int ret;
  1608. if (cnic_get_l5_cid(cp, cid, &l5_cid) != 0)
  1609. return -EINVAL;
  1610. data = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1611. if (!data)
  1612. return -ENOMEM;
  1613. memcpy(data, kwqe, sizeof(struct kwqe));
  1614. ret = cnic_submit_kwqe_16(dev, ISCSI_RAMROD_CMD_ID_UPDATE_CONN,
  1615. req->context_id, ISCSI_CONNECTION_TYPE, &l5_data);
  1616. return ret;
  1617. }
  1618. static int cnic_bnx2x_destroy_ramrod(struct cnic_dev *dev, u32 l5_cid)
  1619. {
  1620. struct cnic_local *cp = dev->cnic_priv;
  1621. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1622. union l5cm_specific_data l5_data;
  1623. int ret;
  1624. u32 hw_cid;
  1625. init_waitqueue_head(&ctx->waitq);
  1626. ctx->wait_cond = 0;
  1627. memset(&l5_data, 0, sizeof(l5_data));
  1628. hw_cid = BNX2X_HW_CID(cp, ctx->cid);
  1629. ret = cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_COMMON_CFC_DEL,
  1630. hw_cid, NONE_CONNECTION_TYPE, &l5_data);
  1631. if (ret == 0) {
  1632. wait_event_timeout(ctx->waitq, ctx->wait_cond, CNIC_RAMROD_TMO);
  1633. if (unlikely(test_bit(CTX_FL_CID_ERROR, &ctx->ctx_flags)))
  1634. return -EBUSY;
  1635. }
  1636. return 0;
  1637. }
  1638. static int cnic_bnx2x_iscsi_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
  1639. {
  1640. struct cnic_local *cp = dev->cnic_priv;
  1641. struct iscsi_kwqe_conn_destroy *req =
  1642. (struct iscsi_kwqe_conn_destroy *) kwqe;
  1643. u32 l5_cid = req->reserved0;
  1644. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1645. int ret = 0;
  1646. struct iscsi_kcqe kcqe;
  1647. struct kcqe *cqes[1];
  1648. if (!test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  1649. goto skip_cfc_delete;
  1650. if (!time_after(jiffies, ctx->timestamp + (2 * HZ))) {
  1651. unsigned long delta = ctx->timestamp + (2 * HZ) - jiffies;
  1652. if (delta > (2 * HZ))
  1653. delta = 0;
  1654. set_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags);
  1655. queue_delayed_work(cnic_wq, &cp->delete_task, delta);
  1656. goto destroy_reply;
  1657. }
  1658. ret = cnic_bnx2x_destroy_ramrod(dev, l5_cid);
  1659. skip_cfc_delete:
  1660. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1661. if (!ret) {
  1662. atomic_dec(&cp->iscsi_conn);
  1663. clear_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  1664. }
  1665. destroy_reply:
  1666. memset(&kcqe, 0, sizeof(kcqe));
  1667. kcqe.op_code = ISCSI_KCQE_OPCODE_DESTROY_CONN;
  1668. kcqe.iscsi_conn_id = l5_cid;
  1669. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
  1670. kcqe.iscsi_conn_context_id = req->context_id;
  1671. cqes[0] = (struct kcqe *) &kcqe;
  1672. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
  1673. return 0;
  1674. }
  1675. static void cnic_init_storm_conn_bufs(struct cnic_dev *dev,
  1676. struct l4_kwq_connect_req1 *kwqe1,
  1677. struct l4_kwq_connect_req3 *kwqe3,
  1678. struct l5cm_active_conn_buffer *conn_buf)
  1679. {
  1680. struct l5cm_conn_addr_params *conn_addr = &conn_buf->conn_addr_buf;
  1681. struct l5cm_xstorm_conn_buffer *xstorm_buf =
  1682. &conn_buf->xstorm_conn_buffer;
  1683. struct l5cm_tstorm_conn_buffer *tstorm_buf =
  1684. &conn_buf->tstorm_conn_buffer;
  1685. struct regpair context_addr;
  1686. u32 cid = BNX2X_SW_CID(kwqe1->cid);
  1687. struct in6_addr src_ip, dst_ip;
  1688. int i;
  1689. u32 *addrp;
  1690. addrp = (u32 *) &conn_addr->local_ip_addr;
  1691. for (i = 0; i < 4; i++, addrp++)
  1692. src_ip.in6_u.u6_addr32[i] = cpu_to_be32(*addrp);
  1693. addrp = (u32 *) &conn_addr->remote_ip_addr;
  1694. for (i = 0; i < 4; i++, addrp++)
  1695. dst_ip.in6_u.u6_addr32[i] = cpu_to_be32(*addrp);
  1696. cnic_get_bnx2x_ctx(dev, cid, 0, &context_addr);
  1697. xstorm_buf->context_addr.hi = context_addr.hi;
  1698. xstorm_buf->context_addr.lo = context_addr.lo;
  1699. xstorm_buf->mss = 0xffff;
  1700. xstorm_buf->rcv_buf = kwqe3->rcv_buf;
  1701. if (kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE)
  1702. xstorm_buf->params |= L5CM_XSTORM_CONN_BUFFER_NAGLE_ENABLE;
  1703. xstorm_buf->pseudo_header_checksum =
  1704. swab16(~csum_ipv6_magic(&src_ip, &dst_ip, 0, IPPROTO_TCP, 0));
  1705. if (kwqe3->ka_timeout) {
  1706. tstorm_buf->ka_enable = 1;
  1707. tstorm_buf->ka_timeout = kwqe3->ka_timeout;
  1708. tstorm_buf->ka_interval = kwqe3->ka_interval;
  1709. tstorm_buf->ka_max_probe_count = kwqe3->ka_max_probe_count;
  1710. }
  1711. tstorm_buf->max_rt_time = 0xffffffff;
  1712. }
  1713. static void cnic_init_bnx2x_mac(struct cnic_dev *dev)
  1714. {
  1715. struct cnic_local *cp = dev->cnic_priv;
  1716. struct bnx2x *bp = netdev_priv(dev->netdev);
  1717. u32 pfid = cp->pfid;
  1718. u8 *mac = dev->mac_addr;
  1719. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1720. XSTORM_ISCSI_LOCAL_MAC_ADDR0_OFFSET(pfid), mac[0]);
  1721. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1722. XSTORM_ISCSI_LOCAL_MAC_ADDR1_OFFSET(pfid), mac[1]);
  1723. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1724. XSTORM_ISCSI_LOCAL_MAC_ADDR2_OFFSET(pfid), mac[2]);
  1725. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1726. XSTORM_ISCSI_LOCAL_MAC_ADDR3_OFFSET(pfid), mac[3]);
  1727. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1728. XSTORM_ISCSI_LOCAL_MAC_ADDR4_OFFSET(pfid), mac[4]);
  1729. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1730. XSTORM_ISCSI_LOCAL_MAC_ADDR5_OFFSET(pfid), mac[5]);
  1731. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1732. TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfid), mac[5]);
  1733. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1734. TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 1,
  1735. mac[4]);
  1736. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1737. TSTORM_ISCSI_TCP_VARS_MID_LOCAL_MAC_ADDR_OFFSET(pfid), mac[3]);
  1738. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1739. TSTORM_ISCSI_TCP_VARS_MID_LOCAL_MAC_ADDR_OFFSET(pfid) + 1,
  1740. mac[2]);
  1741. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1742. TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid), mac[1]);
  1743. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1744. TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 1,
  1745. mac[0]);
  1746. }
  1747. static int cnic_bnx2x_connect(struct cnic_dev *dev, struct kwqe *wqes[],
  1748. u32 num, int *work)
  1749. {
  1750. struct cnic_local *cp = dev->cnic_priv;
  1751. struct bnx2x *bp = netdev_priv(dev->netdev);
  1752. struct l4_kwq_connect_req1 *kwqe1 =
  1753. (struct l4_kwq_connect_req1 *) wqes[0];
  1754. struct l4_kwq_connect_req3 *kwqe3;
  1755. struct l5cm_active_conn_buffer *conn_buf;
  1756. struct l5cm_conn_addr_params *conn_addr;
  1757. union l5cm_specific_data l5_data;
  1758. u32 l5_cid = kwqe1->pg_cid;
  1759. struct cnic_sock *csk = &cp->csk_tbl[l5_cid];
  1760. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1761. int ret;
  1762. if (num < 2) {
  1763. *work = num;
  1764. return -EINVAL;
  1765. }
  1766. if (kwqe1->conn_flags & L4_KWQ_CONNECT_REQ1_IP_V6)
  1767. *work = 3;
  1768. else
  1769. *work = 2;
  1770. if (num < *work) {
  1771. *work = num;
  1772. return -EINVAL;
  1773. }
  1774. if (sizeof(*conn_buf) > CNIC_KWQ16_DATA_SIZE) {
  1775. netdev_err(dev->netdev, "conn_buf size too big\n");
  1776. return -ENOMEM;
  1777. }
  1778. conn_buf = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1779. if (!conn_buf)
  1780. return -ENOMEM;
  1781. memset(conn_buf, 0, sizeof(*conn_buf));
  1782. conn_addr = &conn_buf->conn_addr_buf;
  1783. conn_addr->remote_addr_0 = csk->ha[0];
  1784. conn_addr->remote_addr_1 = csk->ha[1];
  1785. conn_addr->remote_addr_2 = csk->ha[2];
  1786. conn_addr->remote_addr_3 = csk->ha[3];
  1787. conn_addr->remote_addr_4 = csk->ha[4];
  1788. conn_addr->remote_addr_5 = csk->ha[5];
  1789. if (kwqe1->conn_flags & L4_KWQ_CONNECT_REQ1_IP_V6) {
  1790. struct l4_kwq_connect_req2 *kwqe2 =
  1791. (struct l4_kwq_connect_req2 *) wqes[1];
  1792. conn_addr->local_ip_addr.ip_addr_hi_hi = kwqe2->src_ip_v6_4;
  1793. conn_addr->local_ip_addr.ip_addr_hi_lo = kwqe2->src_ip_v6_3;
  1794. conn_addr->local_ip_addr.ip_addr_lo_hi = kwqe2->src_ip_v6_2;
  1795. conn_addr->remote_ip_addr.ip_addr_hi_hi = kwqe2->dst_ip_v6_4;
  1796. conn_addr->remote_ip_addr.ip_addr_hi_lo = kwqe2->dst_ip_v6_3;
  1797. conn_addr->remote_ip_addr.ip_addr_lo_hi = kwqe2->dst_ip_v6_2;
  1798. conn_addr->params |= L5CM_CONN_ADDR_PARAMS_IP_VERSION;
  1799. }
  1800. kwqe3 = (struct l4_kwq_connect_req3 *) wqes[*work - 1];
  1801. conn_addr->local_ip_addr.ip_addr_lo_lo = kwqe1->src_ip;
  1802. conn_addr->remote_ip_addr.ip_addr_lo_lo = kwqe1->dst_ip;
  1803. conn_addr->local_tcp_port = kwqe1->src_port;
  1804. conn_addr->remote_tcp_port = kwqe1->dst_port;
  1805. conn_addr->pmtu = kwqe3->pmtu;
  1806. cnic_init_storm_conn_bufs(dev, kwqe1, kwqe3, conn_buf);
  1807. CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
  1808. XSTORM_ISCSI_LOCAL_VLAN_OFFSET(cp->pfid), csk->vlan_id);
  1809. ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_TCP_CONNECT,
  1810. kwqe1->cid, ISCSI_CONNECTION_TYPE, &l5_data);
  1811. if (!ret)
  1812. set_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  1813. return ret;
  1814. }
  1815. static int cnic_bnx2x_close(struct cnic_dev *dev, struct kwqe *kwqe)
  1816. {
  1817. struct l4_kwq_close_req *req = (struct l4_kwq_close_req *) kwqe;
  1818. union l5cm_specific_data l5_data;
  1819. int ret;
  1820. memset(&l5_data, 0, sizeof(l5_data));
  1821. ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_CLOSE,
  1822. req->cid, ISCSI_CONNECTION_TYPE, &l5_data);
  1823. return ret;
  1824. }
  1825. static int cnic_bnx2x_reset(struct cnic_dev *dev, struct kwqe *kwqe)
  1826. {
  1827. struct l4_kwq_reset_req *req = (struct l4_kwq_reset_req *) kwqe;
  1828. union l5cm_specific_data l5_data;
  1829. int ret;
  1830. memset(&l5_data, 0, sizeof(l5_data));
  1831. ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_ABORT,
  1832. req->cid, ISCSI_CONNECTION_TYPE, &l5_data);
  1833. return ret;
  1834. }
  1835. static int cnic_bnx2x_offload_pg(struct cnic_dev *dev, struct kwqe *kwqe)
  1836. {
  1837. struct l4_kwq_offload_pg *req = (struct l4_kwq_offload_pg *) kwqe;
  1838. struct l4_kcq kcqe;
  1839. struct kcqe *cqes[1];
  1840. memset(&kcqe, 0, sizeof(kcqe));
  1841. kcqe.pg_host_opaque = req->host_opaque;
  1842. kcqe.pg_cid = req->host_opaque;
  1843. kcqe.op_code = L4_KCQE_OPCODE_VALUE_OFFLOAD_PG;
  1844. cqes[0] = (struct kcqe *) &kcqe;
  1845. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_L4, cqes, 1);
  1846. return 0;
  1847. }
  1848. static int cnic_bnx2x_update_pg(struct cnic_dev *dev, struct kwqe *kwqe)
  1849. {
  1850. struct l4_kwq_update_pg *req = (struct l4_kwq_update_pg *) kwqe;
  1851. struct l4_kcq kcqe;
  1852. struct kcqe *cqes[1];
  1853. memset(&kcqe, 0, sizeof(kcqe));
  1854. kcqe.pg_host_opaque = req->pg_host_opaque;
  1855. kcqe.pg_cid = req->pg_cid;
  1856. kcqe.op_code = L4_KCQE_OPCODE_VALUE_UPDATE_PG;
  1857. cqes[0] = (struct kcqe *) &kcqe;
  1858. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_L4, cqes, 1);
  1859. return 0;
  1860. }
  1861. static int cnic_bnx2x_fcoe_stat(struct cnic_dev *dev, struct kwqe *kwqe)
  1862. {
  1863. struct fcoe_kwqe_stat *req;
  1864. struct fcoe_stat_ramrod_params *fcoe_stat;
  1865. union l5cm_specific_data l5_data;
  1866. struct cnic_local *cp = dev->cnic_priv;
  1867. int ret;
  1868. u32 cid;
  1869. req = (struct fcoe_kwqe_stat *) kwqe;
  1870. cid = BNX2X_HW_CID(cp, cp->fcoe_init_cid);
  1871. fcoe_stat = cnic_get_kwqe_16_data(cp, BNX2X_FCOE_L5_CID_BASE, &l5_data);
  1872. if (!fcoe_stat)
  1873. return -ENOMEM;
  1874. memset(fcoe_stat, 0, sizeof(*fcoe_stat));
  1875. memcpy(&fcoe_stat->stat_kwqe, req, sizeof(*req));
  1876. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_STAT_FUNC, cid,
  1877. FCOE_CONNECTION_TYPE, &l5_data);
  1878. return ret;
  1879. }
  1880. static int cnic_bnx2x_fcoe_init1(struct cnic_dev *dev, struct kwqe *wqes[],
  1881. u32 num, int *work)
  1882. {
  1883. int ret;
  1884. struct cnic_local *cp = dev->cnic_priv;
  1885. u32 cid;
  1886. struct fcoe_init_ramrod_params *fcoe_init;
  1887. struct fcoe_kwqe_init1 *req1;
  1888. struct fcoe_kwqe_init2 *req2;
  1889. struct fcoe_kwqe_init3 *req3;
  1890. union l5cm_specific_data l5_data;
  1891. if (num < 3) {
  1892. *work = num;
  1893. return -EINVAL;
  1894. }
  1895. req1 = (struct fcoe_kwqe_init1 *) wqes[0];
  1896. req2 = (struct fcoe_kwqe_init2 *) wqes[1];
  1897. req3 = (struct fcoe_kwqe_init3 *) wqes[2];
  1898. if (req2->hdr.op_code != FCOE_KWQE_OPCODE_INIT2) {
  1899. *work = 1;
  1900. return -EINVAL;
  1901. }
  1902. if (req3->hdr.op_code != FCOE_KWQE_OPCODE_INIT3) {
  1903. *work = 2;
  1904. return -EINVAL;
  1905. }
  1906. if (sizeof(*fcoe_init) > CNIC_KWQ16_DATA_SIZE) {
  1907. netdev_err(dev->netdev, "fcoe_init size too big\n");
  1908. return -ENOMEM;
  1909. }
  1910. fcoe_init = cnic_get_kwqe_16_data(cp, BNX2X_FCOE_L5_CID_BASE, &l5_data);
  1911. if (!fcoe_init)
  1912. return -ENOMEM;
  1913. memset(fcoe_init, 0, sizeof(*fcoe_init));
  1914. memcpy(&fcoe_init->init_kwqe1, req1, sizeof(*req1));
  1915. memcpy(&fcoe_init->init_kwqe2, req2, sizeof(*req2));
  1916. memcpy(&fcoe_init->init_kwqe3, req3, sizeof(*req3));
  1917. fcoe_init->eq_pbl_base.lo = cp->kcq2.dma.pgtbl_map & 0xffffffff;
  1918. fcoe_init->eq_pbl_base.hi = (u64) cp->kcq2.dma.pgtbl_map >> 32;
  1919. fcoe_init->eq_pbl_size = cp->kcq2.dma.num_pages;
  1920. fcoe_init->sb_num = cp->status_blk_num;
  1921. fcoe_init->eq_prod = MAX_KCQ_IDX;
  1922. fcoe_init->sb_id = HC_INDEX_FCOE_EQ_CONS;
  1923. cp->kcq2.sw_prod_idx = 0;
  1924. cid = BNX2X_HW_CID(cp, cp->fcoe_init_cid);
  1925. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_INIT_FUNC, cid,
  1926. FCOE_CONNECTION_TYPE, &l5_data);
  1927. *work = 3;
  1928. return ret;
  1929. }
  1930. static int cnic_bnx2x_fcoe_ofld1(struct cnic_dev *dev, struct kwqe *wqes[],
  1931. u32 num, int *work)
  1932. {
  1933. int ret = 0;
  1934. u32 cid = -1, l5_cid;
  1935. struct cnic_local *cp = dev->cnic_priv;
  1936. struct fcoe_kwqe_conn_offload1 *req1;
  1937. struct fcoe_kwqe_conn_offload2 *req2;
  1938. struct fcoe_kwqe_conn_offload3 *req3;
  1939. struct fcoe_kwqe_conn_offload4 *req4;
  1940. struct fcoe_conn_offload_ramrod_params *fcoe_offload;
  1941. struct cnic_context *ctx;
  1942. struct fcoe_context *fctx;
  1943. struct regpair ctx_addr;
  1944. union l5cm_specific_data l5_data;
  1945. struct fcoe_kcqe kcqe;
  1946. struct kcqe *cqes[1];
  1947. if (num < 4) {
  1948. *work = num;
  1949. return -EINVAL;
  1950. }
  1951. req1 = (struct fcoe_kwqe_conn_offload1 *) wqes[0];
  1952. req2 = (struct fcoe_kwqe_conn_offload2 *) wqes[1];
  1953. req3 = (struct fcoe_kwqe_conn_offload3 *) wqes[2];
  1954. req4 = (struct fcoe_kwqe_conn_offload4 *) wqes[3];
  1955. *work = 4;
  1956. l5_cid = req1->fcoe_conn_id;
  1957. if (l5_cid >= dev->max_fcoe_conn)
  1958. goto err_reply;
  1959. l5_cid += BNX2X_FCOE_L5_CID_BASE;
  1960. ctx = &cp->ctx_tbl[l5_cid];
  1961. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  1962. goto err_reply;
  1963. ret = cnic_alloc_bnx2x_conn_resc(dev, l5_cid);
  1964. if (ret) {
  1965. ret = 0;
  1966. goto err_reply;
  1967. }
  1968. cid = ctx->cid;
  1969. fctx = cnic_get_bnx2x_ctx(dev, cid, 1, &ctx_addr);
  1970. if (fctx) {
  1971. u32 hw_cid = BNX2X_HW_CID(cp, cid);
  1972. u32 val;
  1973. val = CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_XCM_AG,
  1974. FCOE_CONNECTION_TYPE);
  1975. fctx->xstorm_ag_context.cdu_reserved = val;
  1976. val = CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_UCM_AG,
  1977. FCOE_CONNECTION_TYPE);
  1978. fctx->ustorm_ag_context.cdu_usage = val;
  1979. }
  1980. if (sizeof(*fcoe_offload) > CNIC_KWQ16_DATA_SIZE) {
  1981. netdev_err(dev->netdev, "fcoe_offload size too big\n");
  1982. goto err_reply;
  1983. }
  1984. fcoe_offload = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1985. if (!fcoe_offload)
  1986. goto err_reply;
  1987. memset(fcoe_offload, 0, sizeof(*fcoe_offload));
  1988. memcpy(&fcoe_offload->offload_kwqe1, req1, sizeof(*req1));
  1989. memcpy(&fcoe_offload->offload_kwqe2, req2, sizeof(*req2));
  1990. memcpy(&fcoe_offload->offload_kwqe3, req3, sizeof(*req3));
  1991. memcpy(&fcoe_offload->offload_kwqe4, req4, sizeof(*req4));
  1992. cid = BNX2X_HW_CID(cp, cid);
  1993. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_OFFLOAD_CONN, cid,
  1994. FCOE_CONNECTION_TYPE, &l5_data);
  1995. if (!ret)
  1996. set_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  1997. return ret;
  1998. err_reply:
  1999. if (cid != -1)
  2000. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  2001. memset(&kcqe, 0, sizeof(kcqe));
  2002. kcqe.op_code = FCOE_KCQE_OPCODE_OFFLOAD_CONN;
  2003. kcqe.fcoe_conn_id = req1->fcoe_conn_id;
  2004. kcqe.completion_status = FCOE_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE;
  2005. cqes[0] = (struct kcqe *) &kcqe;
  2006. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_FCOE, cqes, 1);
  2007. return ret;
  2008. }
  2009. static int cnic_bnx2x_fcoe_enable(struct cnic_dev *dev, struct kwqe *kwqe)
  2010. {
  2011. struct fcoe_kwqe_conn_enable_disable *req;
  2012. struct fcoe_conn_enable_disable_ramrod_params *fcoe_enable;
  2013. union l5cm_specific_data l5_data;
  2014. int ret;
  2015. u32 cid, l5_cid;
  2016. struct cnic_local *cp = dev->cnic_priv;
  2017. req = (struct fcoe_kwqe_conn_enable_disable *) kwqe;
  2018. cid = req->context_id;
  2019. l5_cid = req->conn_id + BNX2X_FCOE_L5_CID_BASE;
  2020. if (sizeof(*fcoe_enable) > CNIC_KWQ16_DATA_SIZE) {
  2021. netdev_err(dev->netdev, "fcoe_enable size too big\n");
  2022. return -ENOMEM;
  2023. }
  2024. fcoe_enable = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  2025. if (!fcoe_enable)
  2026. return -ENOMEM;
  2027. memset(fcoe_enable, 0, sizeof(*fcoe_enable));
  2028. memcpy(&fcoe_enable->enable_disable_kwqe, req, sizeof(*req));
  2029. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_ENABLE_CONN, cid,
  2030. FCOE_CONNECTION_TYPE, &l5_data);
  2031. return ret;
  2032. }
  2033. static int cnic_bnx2x_fcoe_disable(struct cnic_dev *dev, struct kwqe *kwqe)
  2034. {
  2035. struct fcoe_kwqe_conn_enable_disable *req;
  2036. struct fcoe_conn_enable_disable_ramrod_params *fcoe_disable;
  2037. union l5cm_specific_data l5_data;
  2038. int ret;
  2039. u32 cid, l5_cid;
  2040. struct cnic_local *cp = dev->cnic_priv;
  2041. req = (struct fcoe_kwqe_conn_enable_disable *) kwqe;
  2042. cid = req->context_id;
  2043. l5_cid = req->conn_id;
  2044. if (l5_cid >= dev->max_fcoe_conn)
  2045. return -EINVAL;
  2046. l5_cid += BNX2X_FCOE_L5_CID_BASE;
  2047. if (sizeof(*fcoe_disable) > CNIC_KWQ16_DATA_SIZE) {
  2048. netdev_err(dev->netdev, "fcoe_disable size too big\n");
  2049. return -ENOMEM;
  2050. }
  2051. fcoe_disable = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  2052. if (!fcoe_disable)
  2053. return -ENOMEM;
  2054. memset(fcoe_disable, 0, sizeof(*fcoe_disable));
  2055. memcpy(&fcoe_disable->enable_disable_kwqe, req, sizeof(*req));
  2056. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_DISABLE_CONN, cid,
  2057. FCOE_CONNECTION_TYPE, &l5_data);
  2058. return ret;
  2059. }
  2060. static int cnic_bnx2x_fcoe_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
  2061. {
  2062. struct fcoe_kwqe_conn_destroy *req;
  2063. union l5cm_specific_data l5_data;
  2064. int ret;
  2065. u32 cid, l5_cid;
  2066. struct cnic_local *cp = dev->cnic_priv;
  2067. struct cnic_context *ctx;
  2068. struct fcoe_kcqe kcqe;
  2069. struct kcqe *cqes[1];
  2070. req = (struct fcoe_kwqe_conn_destroy *) kwqe;
  2071. cid = req->context_id;
  2072. l5_cid = req->conn_id;
  2073. if (l5_cid >= dev->max_fcoe_conn)
  2074. return -EINVAL;
  2075. l5_cid += BNX2X_FCOE_L5_CID_BASE;
  2076. ctx = &cp->ctx_tbl[l5_cid];
  2077. init_waitqueue_head(&ctx->waitq);
  2078. ctx->wait_cond = 0;
  2079. memset(&kcqe, 0, sizeof(kcqe));
  2080. kcqe.completion_status = FCOE_KCQE_COMPLETION_STATUS_ERROR;
  2081. memset(&l5_data, 0, sizeof(l5_data));
  2082. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_TERMINATE_CONN, cid,
  2083. FCOE_CONNECTION_TYPE, &l5_data);
  2084. if (ret == 0) {
  2085. wait_event_timeout(ctx->waitq, ctx->wait_cond, CNIC_RAMROD_TMO);
  2086. if (ctx->wait_cond)
  2087. kcqe.completion_status = 0;
  2088. }
  2089. set_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags);
  2090. queue_delayed_work(cnic_wq, &cp->delete_task, msecs_to_jiffies(2000));
  2091. kcqe.op_code = FCOE_KCQE_OPCODE_DESTROY_CONN;
  2092. kcqe.fcoe_conn_id = req->conn_id;
  2093. kcqe.fcoe_conn_context_id = cid;
  2094. cqes[0] = (struct kcqe *) &kcqe;
  2095. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_FCOE, cqes, 1);
  2096. return ret;
  2097. }
  2098. static void cnic_bnx2x_delete_wait(struct cnic_dev *dev, u32 start_cid)
  2099. {
  2100. struct cnic_local *cp = dev->cnic_priv;
  2101. u32 i;
  2102. for (i = start_cid; i < cp->max_cid_space; i++) {
  2103. struct cnic_context *ctx = &cp->ctx_tbl[i];
  2104. int j;
  2105. while (test_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
  2106. msleep(10);
  2107. for (j = 0; j < 5; j++) {
  2108. if (!test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  2109. break;
  2110. msleep(20);
  2111. }
  2112. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  2113. netdev_warn(dev->netdev, "CID %x not deleted\n",
  2114. ctx->cid);
  2115. }
  2116. }
  2117. static int cnic_bnx2x_fcoe_fw_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
  2118. {
  2119. struct fcoe_kwqe_destroy *req;
  2120. union l5cm_specific_data l5_data;
  2121. struct cnic_local *cp = dev->cnic_priv;
  2122. int ret;
  2123. u32 cid;
  2124. cnic_bnx2x_delete_wait(dev, MAX_ISCSI_TBL_SZ);
  2125. req = (struct fcoe_kwqe_destroy *) kwqe;
  2126. cid = BNX2X_HW_CID(cp, cp->fcoe_init_cid);
  2127. memset(&l5_data, 0, sizeof(l5_data));
  2128. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_DESTROY_FUNC, cid,
  2129. FCOE_CONNECTION_TYPE, &l5_data);
  2130. return ret;
  2131. }
  2132. static void cnic_bnx2x_kwqe_err(struct cnic_dev *dev, struct kwqe *kwqe)
  2133. {
  2134. struct cnic_local *cp = dev->cnic_priv;
  2135. struct kcqe kcqe;
  2136. struct kcqe *cqes[1];
  2137. u32 cid;
  2138. u32 opcode = KWQE_OPCODE(kwqe->kwqe_op_flag);
  2139. u32 layer_code = kwqe->kwqe_op_flag & KWQE_LAYER_MASK;
  2140. u32 kcqe_op;
  2141. int ulp_type;
  2142. cid = kwqe->kwqe_info0;
  2143. memset(&kcqe, 0, sizeof(kcqe));
  2144. if (layer_code == KWQE_FLAGS_LAYER_MASK_L5_FCOE) {
  2145. u32 l5_cid = 0;
  2146. ulp_type = CNIC_ULP_FCOE;
  2147. if (opcode == FCOE_KWQE_OPCODE_DISABLE_CONN) {
  2148. struct fcoe_kwqe_conn_enable_disable *req;
  2149. req = (struct fcoe_kwqe_conn_enable_disable *) kwqe;
  2150. kcqe_op = FCOE_KCQE_OPCODE_DISABLE_CONN;
  2151. cid = req->context_id;
  2152. l5_cid = req->conn_id;
  2153. } else if (opcode == FCOE_KWQE_OPCODE_DESTROY) {
  2154. kcqe_op = FCOE_KCQE_OPCODE_DESTROY_FUNC;
  2155. } else {
  2156. return;
  2157. }
  2158. kcqe.kcqe_op_flag = kcqe_op << KCQE_FLAGS_OPCODE_SHIFT;
  2159. kcqe.kcqe_op_flag |= KCQE_FLAGS_LAYER_MASK_L5_FCOE;
  2160. kcqe.kcqe_info1 = FCOE_KCQE_COMPLETION_STATUS_PARITY_ERROR;
  2161. kcqe.kcqe_info2 = cid;
  2162. kcqe.kcqe_info0 = l5_cid;
  2163. } else if (layer_code == KWQE_FLAGS_LAYER_MASK_L5_ISCSI) {
  2164. ulp_type = CNIC_ULP_ISCSI;
  2165. if (opcode == ISCSI_KWQE_OPCODE_UPDATE_CONN)
  2166. cid = kwqe->kwqe_info1;
  2167. kcqe.kcqe_op_flag = (opcode + 0x10) << KCQE_FLAGS_OPCODE_SHIFT;
  2168. kcqe.kcqe_op_flag |= KCQE_FLAGS_LAYER_MASK_L5_ISCSI;
  2169. kcqe.kcqe_info1 = ISCSI_KCQE_COMPLETION_STATUS_PARITY_ERR;
  2170. kcqe.kcqe_info2 = cid;
  2171. cnic_get_l5_cid(cp, BNX2X_SW_CID(cid), &kcqe.kcqe_info0);
  2172. } else if (layer_code == KWQE_FLAGS_LAYER_MASK_L4) {
  2173. struct l4_kcq *l4kcqe = (struct l4_kcq *) &kcqe;
  2174. ulp_type = CNIC_ULP_L4;
  2175. if (opcode == L4_KWQE_OPCODE_VALUE_CONNECT1)
  2176. kcqe_op = L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE;
  2177. else if (opcode == L4_KWQE_OPCODE_VALUE_RESET)
  2178. kcqe_op = L4_KCQE_OPCODE_VALUE_RESET_COMP;
  2179. else if (opcode == L4_KWQE_OPCODE_VALUE_CLOSE)
  2180. kcqe_op = L4_KCQE_OPCODE_VALUE_CLOSE_COMP;
  2181. else
  2182. return;
  2183. kcqe.kcqe_op_flag = (kcqe_op << KCQE_FLAGS_OPCODE_SHIFT) |
  2184. KCQE_FLAGS_LAYER_MASK_L4;
  2185. l4kcqe->status = L4_KCQE_COMPLETION_STATUS_PARITY_ERROR;
  2186. l4kcqe->cid = cid;
  2187. cnic_get_l5_cid(cp, BNX2X_SW_CID(cid), &l4kcqe->conn_id);
  2188. } else {
  2189. return;
  2190. }
  2191. cqes[0] = &kcqe;
  2192. cnic_reply_bnx2x_kcqes(dev, ulp_type, cqes, 1);
  2193. }
  2194. static int cnic_submit_bnx2x_iscsi_kwqes(struct cnic_dev *dev,
  2195. struct kwqe *wqes[], u32 num_wqes)
  2196. {
  2197. int i, work, ret;
  2198. u32 opcode;
  2199. struct kwqe *kwqe;
  2200. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  2201. return -EAGAIN; /* bnx2 is down */
  2202. for (i = 0; i < num_wqes; ) {
  2203. kwqe = wqes[i];
  2204. opcode = KWQE_OPCODE(kwqe->kwqe_op_flag);
  2205. work = 1;
  2206. switch (opcode) {
  2207. case ISCSI_KWQE_OPCODE_INIT1:
  2208. ret = cnic_bnx2x_iscsi_init1(dev, kwqe);
  2209. break;
  2210. case ISCSI_KWQE_OPCODE_INIT2:
  2211. ret = cnic_bnx2x_iscsi_init2(dev, kwqe);
  2212. break;
  2213. case ISCSI_KWQE_OPCODE_OFFLOAD_CONN1:
  2214. ret = cnic_bnx2x_iscsi_ofld1(dev, &wqes[i],
  2215. num_wqes - i, &work);
  2216. break;
  2217. case ISCSI_KWQE_OPCODE_UPDATE_CONN:
  2218. ret = cnic_bnx2x_iscsi_update(dev, kwqe);
  2219. break;
  2220. case ISCSI_KWQE_OPCODE_DESTROY_CONN:
  2221. ret = cnic_bnx2x_iscsi_destroy(dev, kwqe);
  2222. break;
  2223. case L4_KWQE_OPCODE_VALUE_CONNECT1:
  2224. ret = cnic_bnx2x_connect(dev, &wqes[i], num_wqes - i,
  2225. &work);
  2226. break;
  2227. case L4_KWQE_OPCODE_VALUE_CLOSE:
  2228. ret = cnic_bnx2x_close(dev, kwqe);
  2229. break;
  2230. case L4_KWQE_OPCODE_VALUE_RESET:
  2231. ret = cnic_bnx2x_reset(dev, kwqe);
  2232. break;
  2233. case L4_KWQE_OPCODE_VALUE_OFFLOAD_PG:
  2234. ret = cnic_bnx2x_offload_pg(dev, kwqe);
  2235. break;
  2236. case L4_KWQE_OPCODE_VALUE_UPDATE_PG:
  2237. ret = cnic_bnx2x_update_pg(dev, kwqe);
  2238. break;
  2239. case L4_KWQE_OPCODE_VALUE_UPLOAD_PG:
  2240. ret = 0;
  2241. break;
  2242. default:
  2243. ret = 0;
  2244. netdev_err(dev->netdev, "Unknown type of KWQE(0x%x)\n",
  2245. opcode);
  2246. break;
  2247. }
  2248. if (ret < 0) {
  2249. netdev_err(dev->netdev, "KWQE(0x%x) failed\n",
  2250. opcode);
  2251. /* Possibly bnx2x parity error, send completion
  2252. * to ulp drivers with error code to speed up
  2253. * cleanup and reset recovery.
  2254. */
  2255. if (ret == -EIO || ret == -EAGAIN)
  2256. cnic_bnx2x_kwqe_err(dev, kwqe);
  2257. }
  2258. i += work;
  2259. }
  2260. return 0;
  2261. }
  2262. static int cnic_submit_bnx2x_fcoe_kwqes(struct cnic_dev *dev,
  2263. struct kwqe *wqes[], u32 num_wqes)
  2264. {
  2265. struct cnic_local *cp = dev->cnic_priv;
  2266. int i, work, ret;
  2267. u32 opcode;
  2268. struct kwqe *kwqe;
  2269. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  2270. return -EAGAIN; /* bnx2 is down */
  2271. if (!BNX2X_CHIP_IS_E2_PLUS(cp->chip_id))
  2272. return -EINVAL;
  2273. for (i = 0; i < num_wqes; ) {
  2274. kwqe = wqes[i];
  2275. opcode = KWQE_OPCODE(kwqe->kwqe_op_flag);
  2276. work = 1;
  2277. switch (opcode) {
  2278. case FCOE_KWQE_OPCODE_INIT1:
  2279. ret = cnic_bnx2x_fcoe_init1(dev, &wqes[i],
  2280. num_wqes - i, &work);
  2281. break;
  2282. case FCOE_KWQE_OPCODE_OFFLOAD_CONN1:
  2283. ret = cnic_bnx2x_fcoe_ofld1(dev, &wqes[i],
  2284. num_wqes - i, &work);
  2285. break;
  2286. case FCOE_KWQE_OPCODE_ENABLE_CONN:
  2287. ret = cnic_bnx2x_fcoe_enable(dev, kwqe);
  2288. break;
  2289. case FCOE_KWQE_OPCODE_DISABLE_CONN:
  2290. ret = cnic_bnx2x_fcoe_disable(dev, kwqe);
  2291. break;
  2292. case FCOE_KWQE_OPCODE_DESTROY_CONN:
  2293. ret = cnic_bnx2x_fcoe_destroy(dev, kwqe);
  2294. break;
  2295. case FCOE_KWQE_OPCODE_DESTROY:
  2296. ret = cnic_bnx2x_fcoe_fw_destroy(dev, kwqe);
  2297. break;
  2298. case FCOE_KWQE_OPCODE_STAT:
  2299. ret = cnic_bnx2x_fcoe_stat(dev, kwqe);
  2300. break;
  2301. default:
  2302. ret = 0;
  2303. netdev_err(dev->netdev, "Unknown type of KWQE(0x%x)\n",
  2304. opcode);
  2305. break;
  2306. }
  2307. if (ret < 0) {
  2308. netdev_err(dev->netdev, "KWQE(0x%x) failed\n",
  2309. opcode);
  2310. /* Possibly bnx2x parity error, send completion
  2311. * to ulp drivers with error code to speed up
  2312. * cleanup and reset recovery.
  2313. */
  2314. if (ret == -EIO || ret == -EAGAIN)
  2315. cnic_bnx2x_kwqe_err(dev, kwqe);
  2316. }
  2317. i += work;
  2318. }
  2319. return 0;
  2320. }
  2321. static int cnic_submit_bnx2x_kwqes(struct cnic_dev *dev, struct kwqe *wqes[],
  2322. u32 num_wqes)
  2323. {
  2324. int ret = -EINVAL;
  2325. u32 layer_code;
  2326. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  2327. return -EAGAIN; /* bnx2x is down */
  2328. if (!num_wqes)
  2329. return 0;
  2330. layer_code = wqes[0]->kwqe_op_flag & KWQE_LAYER_MASK;
  2331. switch (layer_code) {
  2332. case KWQE_FLAGS_LAYER_MASK_L5_ISCSI:
  2333. case KWQE_FLAGS_LAYER_MASK_L4:
  2334. case KWQE_FLAGS_LAYER_MASK_L2:
  2335. ret = cnic_submit_bnx2x_iscsi_kwqes(dev, wqes, num_wqes);
  2336. break;
  2337. case KWQE_FLAGS_LAYER_MASK_L5_FCOE:
  2338. ret = cnic_submit_bnx2x_fcoe_kwqes(dev, wqes, num_wqes);
  2339. break;
  2340. }
  2341. return ret;
  2342. }
  2343. static inline u32 cnic_get_kcqe_layer_mask(u32 opflag)
  2344. {
  2345. if (unlikely(KCQE_OPCODE(opflag) == FCOE_RAMROD_CMD_ID_TERMINATE_CONN))
  2346. return KCQE_FLAGS_LAYER_MASK_L4;
  2347. return opflag & KCQE_FLAGS_LAYER_MASK;
  2348. }
  2349. static void service_kcqes(struct cnic_dev *dev, int num_cqes)
  2350. {
  2351. struct cnic_local *cp = dev->cnic_priv;
  2352. int i, j, comp = 0;
  2353. i = 0;
  2354. j = 1;
  2355. while (num_cqes) {
  2356. struct cnic_ulp_ops *ulp_ops;
  2357. int ulp_type;
  2358. u32 kcqe_op_flag = cp->completed_kcq[i]->kcqe_op_flag;
  2359. u32 kcqe_layer = cnic_get_kcqe_layer_mask(kcqe_op_flag);
  2360. if (unlikely(kcqe_op_flag & KCQE_RAMROD_COMPLETION))
  2361. comp++;
  2362. while (j < num_cqes) {
  2363. u32 next_op = cp->completed_kcq[i + j]->kcqe_op_flag;
  2364. if (cnic_get_kcqe_layer_mask(next_op) != kcqe_layer)
  2365. break;
  2366. if (unlikely(next_op & KCQE_RAMROD_COMPLETION))
  2367. comp++;
  2368. j++;
  2369. }
  2370. if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_RDMA)
  2371. ulp_type = CNIC_ULP_RDMA;
  2372. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_ISCSI)
  2373. ulp_type = CNIC_ULP_ISCSI;
  2374. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_FCOE)
  2375. ulp_type = CNIC_ULP_FCOE;
  2376. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L4)
  2377. ulp_type = CNIC_ULP_L4;
  2378. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L2)
  2379. goto end;
  2380. else {
  2381. netdev_err(dev->netdev, "Unknown type of KCQE(0x%x)\n",
  2382. kcqe_op_flag);
  2383. goto end;
  2384. }
  2385. rcu_read_lock();
  2386. ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
  2387. if (likely(ulp_ops)) {
  2388. ulp_ops->indicate_kcqes(cp->ulp_handle[ulp_type],
  2389. cp->completed_kcq + i, j);
  2390. }
  2391. rcu_read_unlock();
  2392. end:
  2393. num_cqes -= j;
  2394. i += j;
  2395. j = 1;
  2396. }
  2397. if (unlikely(comp))
  2398. cnic_spq_completion(dev, DRV_CTL_RET_L5_SPQ_CREDIT_CMD, comp);
  2399. }
  2400. static int cnic_get_kcqes(struct cnic_dev *dev, struct kcq_info *info)
  2401. {
  2402. struct cnic_local *cp = dev->cnic_priv;
  2403. u16 i, ri, hw_prod, last;
  2404. struct kcqe *kcqe;
  2405. int kcqe_cnt = 0, last_cnt = 0;
  2406. i = ri = last = info->sw_prod_idx;
  2407. ri &= MAX_KCQ_IDX;
  2408. hw_prod = *info->hw_prod_idx_ptr;
  2409. hw_prod = info->hw_idx(hw_prod);
  2410. while ((i != hw_prod) && (kcqe_cnt < MAX_COMPLETED_KCQE)) {
  2411. kcqe = &info->kcq[KCQ_PG(ri)][KCQ_IDX(ri)];
  2412. cp->completed_kcq[kcqe_cnt++] = kcqe;
  2413. i = info->next_idx(i);
  2414. ri = i & MAX_KCQ_IDX;
  2415. if (likely(!(kcqe->kcqe_op_flag & KCQE_FLAGS_NEXT))) {
  2416. last_cnt = kcqe_cnt;
  2417. last = i;
  2418. }
  2419. }
  2420. info->sw_prod_idx = last;
  2421. return last_cnt;
  2422. }
  2423. static int cnic_l2_completion(struct cnic_local *cp)
  2424. {
  2425. u16 hw_cons, sw_cons;
  2426. struct cnic_uio_dev *udev = cp->udev;
  2427. union eth_rx_cqe *cqe, *cqe_ring = (union eth_rx_cqe *)
  2428. (udev->l2_ring + (2 * BNX2_PAGE_SIZE));
  2429. u32 cmd;
  2430. int comp = 0;
  2431. if (!test_bit(CNIC_F_BNX2X_CLASS, &cp->dev->flags))
  2432. return 0;
  2433. hw_cons = *cp->rx_cons_ptr;
  2434. if ((hw_cons & BNX2X_MAX_RCQ_DESC_CNT) == BNX2X_MAX_RCQ_DESC_CNT)
  2435. hw_cons++;
  2436. sw_cons = cp->rx_cons;
  2437. while (sw_cons != hw_cons) {
  2438. u8 cqe_fp_flags;
  2439. cqe = &cqe_ring[sw_cons & BNX2X_MAX_RCQ_DESC_CNT];
  2440. cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
  2441. if (cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE) {
  2442. cmd = le32_to_cpu(cqe->ramrod_cqe.conn_and_cmd_data);
  2443. cmd >>= COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT;
  2444. if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP ||
  2445. cmd == RAMROD_CMD_ID_ETH_HALT)
  2446. comp++;
  2447. }
  2448. sw_cons = BNX2X_NEXT_RCQE(sw_cons);
  2449. }
  2450. return comp;
  2451. }
  2452. static void cnic_chk_pkt_rings(struct cnic_local *cp)
  2453. {
  2454. u16 rx_cons, tx_cons;
  2455. int comp = 0;
  2456. if (!test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
  2457. return;
  2458. rx_cons = *cp->rx_cons_ptr;
  2459. tx_cons = *cp->tx_cons_ptr;
  2460. if (cp->tx_cons != tx_cons || cp->rx_cons != rx_cons) {
  2461. if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
  2462. comp = cnic_l2_completion(cp);
  2463. cp->tx_cons = tx_cons;
  2464. cp->rx_cons = rx_cons;
  2465. if (cp->udev)
  2466. uio_event_notify(&cp->udev->cnic_uinfo);
  2467. }
  2468. if (comp)
  2469. clear_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
  2470. }
  2471. static u32 cnic_service_bnx2_queues(struct cnic_dev *dev)
  2472. {
  2473. struct cnic_local *cp = dev->cnic_priv;
  2474. u32 status_idx = (u16) *cp->kcq1.status_idx_ptr;
  2475. int kcqe_cnt;
  2476. /* status block index must be read before reading other fields */
  2477. rmb();
  2478. cp->kwq_con_idx = *cp->kwq_con_idx_ptr;
  2479. while ((kcqe_cnt = cnic_get_kcqes(dev, &cp->kcq1))) {
  2480. service_kcqes(dev, kcqe_cnt);
  2481. /* Tell compiler that status_blk fields can change. */
  2482. barrier();
  2483. status_idx = (u16) *cp->kcq1.status_idx_ptr;
  2484. /* status block index must be read first */
  2485. rmb();
  2486. cp->kwq_con_idx = *cp->kwq_con_idx_ptr;
  2487. }
  2488. CNIC_WR16(dev, cp->kcq1.io_addr, cp->kcq1.sw_prod_idx);
  2489. cnic_chk_pkt_rings(cp);
  2490. return status_idx;
  2491. }
  2492. static int cnic_service_bnx2(void *data, void *status_blk)
  2493. {
  2494. struct cnic_dev *dev = data;
  2495. if (unlikely(!test_bit(CNIC_F_CNIC_UP, &dev->flags))) {
  2496. struct status_block *sblk = status_blk;
  2497. return sblk->status_idx;
  2498. }
  2499. return cnic_service_bnx2_queues(dev);
  2500. }
  2501. static void cnic_service_bnx2_msix(unsigned long data)
  2502. {
  2503. struct cnic_dev *dev = (struct cnic_dev *) data;
  2504. struct cnic_local *cp = dev->cnic_priv;
  2505. cp->last_status_idx = cnic_service_bnx2_queues(dev);
  2506. CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
  2507. BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | cp->last_status_idx);
  2508. }
  2509. static void cnic_doirq(struct cnic_dev *dev)
  2510. {
  2511. struct cnic_local *cp = dev->cnic_priv;
  2512. if (likely(test_bit(CNIC_F_CNIC_UP, &dev->flags))) {
  2513. u16 prod = cp->kcq1.sw_prod_idx & MAX_KCQ_IDX;
  2514. prefetch(cp->status_blk.gen);
  2515. prefetch(&cp->kcq1.kcq[KCQ_PG(prod)][KCQ_IDX(prod)]);
  2516. tasklet_schedule(&cp->cnic_irq_task);
  2517. }
  2518. }
  2519. static irqreturn_t cnic_irq(int irq, void *dev_instance)
  2520. {
  2521. struct cnic_dev *dev = dev_instance;
  2522. struct cnic_local *cp = dev->cnic_priv;
  2523. if (cp->ack_int)
  2524. cp->ack_int(dev);
  2525. cnic_doirq(dev);
  2526. return IRQ_HANDLED;
  2527. }
  2528. static inline void cnic_ack_bnx2x_int(struct cnic_dev *dev, u8 id, u8 storm,
  2529. u16 index, u8 op, u8 update)
  2530. {
  2531. struct cnic_local *cp = dev->cnic_priv;
  2532. u32 hc_addr = (HC_REG_COMMAND_REG + CNIC_PORT(cp) * 32 +
  2533. COMMAND_REG_INT_ACK);
  2534. struct igu_ack_register igu_ack;
  2535. igu_ack.status_block_index = index;
  2536. igu_ack.sb_id_and_flags =
  2537. ((id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) |
  2538. (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) |
  2539. (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
  2540. (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
  2541. CNIC_WR(dev, hc_addr, (*(u32 *)&igu_ack));
  2542. }
  2543. static void cnic_ack_igu_sb(struct cnic_dev *dev, u8 igu_sb_id, u8 segment,
  2544. u16 index, u8 op, u8 update)
  2545. {
  2546. struct igu_regular cmd_data;
  2547. u32 igu_addr = BAR_IGU_INTMEM + (IGU_CMD_INT_ACK_BASE + igu_sb_id) * 8;
  2548. cmd_data.sb_id_and_flags =
  2549. (index << IGU_REGULAR_SB_INDEX_SHIFT) |
  2550. (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) |
  2551. (update << IGU_REGULAR_BUPDATE_SHIFT) |
  2552. (op << IGU_REGULAR_ENABLE_INT_SHIFT);
  2553. CNIC_WR(dev, igu_addr, cmd_data.sb_id_and_flags);
  2554. }
  2555. static void cnic_ack_bnx2x_msix(struct cnic_dev *dev)
  2556. {
  2557. struct cnic_local *cp = dev->cnic_priv;
  2558. cnic_ack_bnx2x_int(dev, cp->bnx2x_igu_sb_id, CSTORM_ID, 0,
  2559. IGU_INT_DISABLE, 0);
  2560. }
  2561. static void cnic_ack_bnx2x_e2_msix(struct cnic_dev *dev)
  2562. {
  2563. struct cnic_local *cp = dev->cnic_priv;
  2564. cnic_ack_igu_sb(dev, cp->bnx2x_igu_sb_id, IGU_SEG_ACCESS_DEF, 0,
  2565. IGU_INT_DISABLE, 0);
  2566. }
  2567. static void cnic_arm_bnx2x_msix(struct cnic_dev *dev, u32 idx)
  2568. {
  2569. struct cnic_local *cp = dev->cnic_priv;
  2570. cnic_ack_bnx2x_int(dev, cp->bnx2x_igu_sb_id, CSTORM_ID, idx,
  2571. IGU_INT_ENABLE, 1);
  2572. }
  2573. static void cnic_arm_bnx2x_e2_msix(struct cnic_dev *dev, u32 idx)
  2574. {
  2575. struct cnic_local *cp = dev->cnic_priv;
  2576. cnic_ack_igu_sb(dev, cp->bnx2x_igu_sb_id, IGU_SEG_ACCESS_DEF, idx,
  2577. IGU_INT_ENABLE, 1);
  2578. }
  2579. static u32 cnic_service_bnx2x_kcq(struct cnic_dev *dev, struct kcq_info *info)
  2580. {
  2581. u32 last_status = *info->status_idx_ptr;
  2582. int kcqe_cnt;
  2583. /* status block index must be read before reading the KCQ */
  2584. rmb();
  2585. while ((kcqe_cnt = cnic_get_kcqes(dev, info))) {
  2586. service_kcqes(dev, kcqe_cnt);
  2587. /* Tell compiler that sblk fields can change. */
  2588. barrier();
  2589. last_status = *info->status_idx_ptr;
  2590. /* status block index must be read before reading the KCQ */
  2591. rmb();
  2592. }
  2593. return last_status;
  2594. }
  2595. static void cnic_service_bnx2x_bh(unsigned long data)
  2596. {
  2597. struct cnic_dev *dev = (struct cnic_dev *) data;
  2598. struct cnic_local *cp = dev->cnic_priv;
  2599. u32 status_idx, new_status_idx;
  2600. if (unlikely(!test_bit(CNIC_F_CNIC_UP, &dev->flags)))
  2601. return;
  2602. while (1) {
  2603. status_idx = cnic_service_bnx2x_kcq(dev, &cp->kcq1);
  2604. CNIC_WR16(dev, cp->kcq1.io_addr,
  2605. cp->kcq1.sw_prod_idx + MAX_KCQ_IDX);
  2606. if (cp->ethdev->drv_state & CNIC_DRV_STATE_NO_FCOE) {
  2607. cp->arm_int(dev, status_idx);
  2608. break;
  2609. }
  2610. new_status_idx = cnic_service_bnx2x_kcq(dev, &cp->kcq2);
  2611. if (new_status_idx != status_idx)
  2612. continue;
  2613. CNIC_WR16(dev, cp->kcq2.io_addr, cp->kcq2.sw_prod_idx +
  2614. MAX_KCQ_IDX);
  2615. cnic_ack_igu_sb(dev, cp->bnx2x_igu_sb_id, IGU_SEG_ACCESS_DEF,
  2616. status_idx, IGU_INT_ENABLE, 1);
  2617. break;
  2618. }
  2619. }
  2620. static int cnic_service_bnx2x(void *data, void *status_blk)
  2621. {
  2622. struct cnic_dev *dev = data;
  2623. struct cnic_local *cp = dev->cnic_priv;
  2624. if (!(cp->ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
  2625. cnic_doirq(dev);
  2626. cnic_chk_pkt_rings(cp);
  2627. return 0;
  2628. }
  2629. static void cnic_ulp_stop_one(struct cnic_local *cp, int if_type)
  2630. {
  2631. struct cnic_ulp_ops *ulp_ops;
  2632. if (if_type == CNIC_ULP_ISCSI)
  2633. cnic_send_nlmsg(cp, ISCSI_KEVENT_IF_DOWN, NULL);
  2634. mutex_lock(&cnic_lock);
  2635. ulp_ops = rcu_dereference_protected(cp->ulp_ops[if_type],
  2636. lockdep_is_held(&cnic_lock));
  2637. if (!ulp_ops) {
  2638. mutex_unlock(&cnic_lock);
  2639. return;
  2640. }
  2641. set_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2642. mutex_unlock(&cnic_lock);
  2643. if (test_and_clear_bit(ULP_F_START, &cp->ulp_flags[if_type]))
  2644. ulp_ops->cnic_stop(cp->ulp_handle[if_type]);
  2645. clear_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2646. }
  2647. static void cnic_ulp_stop(struct cnic_dev *dev)
  2648. {
  2649. struct cnic_local *cp = dev->cnic_priv;
  2650. int if_type;
  2651. for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++)
  2652. cnic_ulp_stop_one(cp, if_type);
  2653. }
  2654. static void cnic_ulp_start(struct cnic_dev *dev)
  2655. {
  2656. struct cnic_local *cp = dev->cnic_priv;
  2657. int if_type;
  2658. for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
  2659. struct cnic_ulp_ops *ulp_ops;
  2660. mutex_lock(&cnic_lock);
  2661. ulp_ops = rcu_dereference_protected(cp->ulp_ops[if_type],
  2662. lockdep_is_held(&cnic_lock));
  2663. if (!ulp_ops || !ulp_ops->cnic_start) {
  2664. mutex_unlock(&cnic_lock);
  2665. continue;
  2666. }
  2667. set_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2668. mutex_unlock(&cnic_lock);
  2669. if (!test_and_set_bit(ULP_F_START, &cp->ulp_flags[if_type]))
  2670. ulp_ops->cnic_start(cp->ulp_handle[if_type]);
  2671. clear_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2672. }
  2673. }
  2674. static int cnic_copy_ulp_stats(struct cnic_dev *dev, int ulp_type)
  2675. {
  2676. struct cnic_local *cp = dev->cnic_priv;
  2677. struct cnic_ulp_ops *ulp_ops;
  2678. int rc;
  2679. mutex_lock(&cnic_lock);
  2680. ulp_ops = cnic_ulp_tbl_prot(ulp_type);
  2681. if (ulp_ops && ulp_ops->cnic_get_stats)
  2682. rc = ulp_ops->cnic_get_stats(cp->ulp_handle[ulp_type]);
  2683. else
  2684. rc = -ENODEV;
  2685. mutex_unlock(&cnic_lock);
  2686. return rc;
  2687. }
  2688. static int cnic_ctl(void *data, struct cnic_ctl_info *info)
  2689. {
  2690. struct cnic_dev *dev = data;
  2691. int ulp_type = CNIC_ULP_ISCSI;
  2692. switch (info->cmd) {
  2693. case CNIC_CTL_STOP_CMD:
  2694. cnic_hold(dev);
  2695. cnic_ulp_stop(dev);
  2696. cnic_stop_hw(dev);
  2697. cnic_put(dev);
  2698. break;
  2699. case CNIC_CTL_START_CMD:
  2700. cnic_hold(dev);
  2701. if (!cnic_start_hw(dev))
  2702. cnic_ulp_start(dev);
  2703. cnic_put(dev);
  2704. break;
  2705. case CNIC_CTL_STOP_ISCSI_CMD: {
  2706. struct cnic_local *cp = dev->cnic_priv;
  2707. set_bit(CNIC_LCL_FL_STOP_ISCSI, &cp->cnic_local_flags);
  2708. queue_delayed_work(cnic_wq, &cp->delete_task, 0);
  2709. break;
  2710. }
  2711. case CNIC_CTL_COMPLETION_CMD: {
  2712. struct cnic_ctl_completion *comp = &info->data.comp;
  2713. u32 cid = BNX2X_SW_CID(comp->cid);
  2714. u32 l5_cid;
  2715. struct cnic_local *cp = dev->cnic_priv;
  2716. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  2717. break;
  2718. if (cnic_get_l5_cid(cp, cid, &l5_cid) == 0) {
  2719. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  2720. if (unlikely(comp->error)) {
  2721. set_bit(CTX_FL_CID_ERROR, &ctx->ctx_flags);
  2722. netdev_err(dev->netdev,
  2723. "CID %x CFC delete comp error %x\n",
  2724. cid, comp->error);
  2725. }
  2726. ctx->wait_cond = 1;
  2727. wake_up(&ctx->waitq);
  2728. }
  2729. break;
  2730. }
  2731. case CNIC_CTL_FCOE_STATS_GET_CMD:
  2732. ulp_type = CNIC_ULP_FCOE;
  2733. /* fall through */
  2734. case CNIC_CTL_ISCSI_STATS_GET_CMD:
  2735. cnic_hold(dev);
  2736. cnic_copy_ulp_stats(dev, ulp_type);
  2737. cnic_put(dev);
  2738. break;
  2739. default:
  2740. return -EINVAL;
  2741. }
  2742. return 0;
  2743. }
  2744. static void cnic_ulp_init(struct cnic_dev *dev)
  2745. {
  2746. int i;
  2747. struct cnic_local *cp = dev->cnic_priv;
  2748. for (i = 0; i < MAX_CNIC_ULP_TYPE_EXT; i++) {
  2749. struct cnic_ulp_ops *ulp_ops;
  2750. mutex_lock(&cnic_lock);
  2751. ulp_ops = cnic_ulp_tbl_prot(i);
  2752. if (!ulp_ops || !ulp_ops->cnic_init) {
  2753. mutex_unlock(&cnic_lock);
  2754. continue;
  2755. }
  2756. ulp_get(ulp_ops);
  2757. mutex_unlock(&cnic_lock);
  2758. if (!test_and_set_bit(ULP_F_INIT, &cp->ulp_flags[i]))
  2759. ulp_ops->cnic_init(dev);
  2760. ulp_put(ulp_ops);
  2761. }
  2762. }
  2763. static void cnic_ulp_exit(struct cnic_dev *dev)
  2764. {
  2765. int i;
  2766. struct cnic_local *cp = dev->cnic_priv;
  2767. for (i = 0; i < MAX_CNIC_ULP_TYPE_EXT; i++) {
  2768. struct cnic_ulp_ops *ulp_ops;
  2769. mutex_lock(&cnic_lock);
  2770. ulp_ops = cnic_ulp_tbl_prot(i);
  2771. if (!ulp_ops || !ulp_ops->cnic_exit) {
  2772. mutex_unlock(&cnic_lock);
  2773. continue;
  2774. }
  2775. ulp_get(ulp_ops);
  2776. mutex_unlock(&cnic_lock);
  2777. if (test_and_clear_bit(ULP_F_INIT, &cp->ulp_flags[i]))
  2778. ulp_ops->cnic_exit(dev);
  2779. ulp_put(ulp_ops);
  2780. }
  2781. }
  2782. static int cnic_cm_offload_pg(struct cnic_sock *csk)
  2783. {
  2784. struct cnic_dev *dev = csk->dev;
  2785. struct l4_kwq_offload_pg *l4kwqe;
  2786. struct kwqe *wqes[1];
  2787. l4kwqe = (struct l4_kwq_offload_pg *) &csk->kwqe1;
  2788. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2789. wqes[0] = (struct kwqe *) l4kwqe;
  2790. l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_OFFLOAD_PG;
  2791. l4kwqe->flags =
  2792. L4_LAYER_CODE << L4_KWQ_OFFLOAD_PG_LAYER_CODE_SHIFT;
  2793. l4kwqe->l2hdr_nbytes = ETH_HLEN;
  2794. l4kwqe->da0 = csk->ha[0];
  2795. l4kwqe->da1 = csk->ha[1];
  2796. l4kwqe->da2 = csk->ha[2];
  2797. l4kwqe->da3 = csk->ha[3];
  2798. l4kwqe->da4 = csk->ha[4];
  2799. l4kwqe->da5 = csk->ha[5];
  2800. l4kwqe->sa0 = dev->mac_addr[0];
  2801. l4kwqe->sa1 = dev->mac_addr[1];
  2802. l4kwqe->sa2 = dev->mac_addr[2];
  2803. l4kwqe->sa3 = dev->mac_addr[3];
  2804. l4kwqe->sa4 = dev->mac_addr[4];
  2805. l4kwqe->sa5 = dev->mac_addr[5];
  2806. l4kwqe->etype = ETH_P_IP;
  2807. l4kwqe->ipid_start = DEF_IPID_START;
  2808. l4kwqe->host_opaque = csk->l5_cid;
  2809. if (csk->vlan_id) {
  2810. l4kwqe->pg_flags |= L4_KWQ_OFFLOAD_PG_VLAN_TAGGING;
  2811. l4kwqe->vlan_tag = csk->vlan_id;
  2812. l4kwqe->l2hdr_nbytes += 4;
  2813. }
  2814. return dev->submit_kwqes(dev, wqes, 1);
  2815. }
  2816. static int cnic_cm_update_pg(struct cnic_sock *csk)
  2817. {
  2818. struct cnic_dev *dev = csk->dev;
  2819. struct l4_kwq_update_pg *l4kwqe;
  2820. struct kwqe *wqes[1];
  2821. l4kwqe = (struct l4_kwq_update_pg *) &csk->kwqe1;
  2822. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2823. wqes[0] = (struct kwqe *) l4kwqe;
  2824. l4kwqe->opcode = L4_KWQE_OPCODE_VALUE_UPDATE_PG;
  2825. l4kwqe->flags =
  2826. L4_LAYER_CODE << L4_KWQ_UPDATE_PG_LAYER_CODE_SHIFT;
  2827. l4kwqe->pg_cid = csk->pg_cid;
  2828. l4kwqe->da0 = csk->ha[0];
  2829. l4kwqe->da1 = csk->ha[1];
  2830. l4kwqe->da2 = csk->ha[2];
  2831. l4kwqe->da3 = csk->ha[3];
  2832. l4kwqe->da4 = csk->ha[4];
  2833. l4kwqe->da5 = csk->ha[5];
  2834. l4kwqe->pg_host_opaque = csk->l5_cid;
  2835. l4kwqe->pg_valids = L4_KWQ_UPDATE_PG_VALIDS_DA;
  2836. return dev->submit_kwqes(dev, wqes, 1);
  2837. }
  2838. static int cnic_cm_upload_pg(struct cnic_sock *csk)
  2839. {
  2840. struct cnic_dev *dev = csk->dev;
  2841. struct l4_kwq_upload *l4kwqe;
  2842. struct kwqe *wqes[1];
  2843. l4kwqe = (struct l4_kwq_upload *) &csk->kwqe1;
  2844. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2845. wqes[0] = (struct kwqe *) l4kwqe;
  2846. l4kwqe->opcode = L4_KWQE_OPCODE_VALUE_UPLOAD_PG;
  2847. l4kwqe->flags =
  2848. L4_LAYER_CODE << L4_KWQ_UPLOAD_LAYER_CODE_SHIFT;
  2849. l4kwqe->cid = csk->pg_cid;
  2850. return dev->submit_kwqes(dev, wqes, 1);
  2851. }
  2852. static int cnic_cm_conn_req(struct cnic_sock *csk)
  2853. {
  2854. struct cnic_dev *dev = csk->dev;
  2855. struct l4_kwq_connect_req1 *l4kwqe1;
  2856. struct l4_kwq_connect_req2 *l4kwqe2;
  2857. struct l4_kwq_connect_req3 *l4kwqe3;
  2858. struct kwqe *wqes[3];
  2859. u8 tcp_flags = 0;
  2860. int num_wqes = 2;
  2861. l4kwqe1 = (struct l4_kwq_connect_req1 *) &csk->kwqe1;
  2862. l4kwqe2 = (struct l4_kwq_connect_req2 *) &csk->kwqe2;
  2863. l4kwqe3 = (struct l4_kwq_connect_req3 *) &csk->kwqe3;
  2864. memset(l4kwqe1, 0, sizeof(*l4kwqe1));
  2865. memset(l4kwqe2, 0, sizeof(*l4kwqe2));
  2866. memset(l4kwqe3, 0, sizeof(*l4kwqe3));
  2867. l4kwqe3->op_code = L4_KWQE_OPCODE_VALUE_CONNECT3;
  2868. l4kwqe3->flags =
  2869. L4_LAYER_CODE << L4_KWQ_CONNECT_REQ3_LAYER_CODE_SHIFT;
  2870. l4kwqe3->ka_timeout = csk->ka_timeout;
  2871. l4kwqe3->ka_interval = csk->ka_interval;
  2872. l4kwqe3->ka_max_probe_count = csk->ka_max_probe_count;
  2873. l4kwqe3->tos = csk->tos;
  2874. l4kwqe3->ttl = csk->ttl;
  2875. l4kwqe3->snd_seq_scale = csk->snd_seq_scale;
  2876. l4kwqe3->pmtu = csk->mtu;
  2877. l4kwqe3->rcv_buf = csk->rcv_buf;
  2878. l4kwqe3->snd_buf = csk->snd_buf;
  2879. l4kwqe3->seed = csk->seed;
  2880. wqes[0] = (struct kwqe *) l4kwqe1;
  2881. if (test_bit(SK_F_IPV6, &csk->flags)) {
  2882. wqes[1] = (struct kwqe *) l4kwqe2;
  2883. wqes[2] = (struct kwqe *) l4kwqe3;
  2884. num_wqes = 3;
  2885. l4kwqe1->conn_flags = L4_KWQ_CONNECT_REQ1_IP_V6;
  2886. l4kwqe2->op_code = L4_KWQE_OPCODE_VALUE_CONNECT2;
  2887. l4kwqe2->flags =
  2888. L4_KWQ_CONNECT_REQ2_LINKED_WITH_NEXT |
  2889. L4_LAYER_CODE << L4_KWQ_CONNECT_REQ2_LAYER_CODE_SHIFT;
  2890. l4kwqe2->src_ip_v6_2 = be32_to_cpu(csk->src_ip[1]);
  2891. l4kwqe2->src_ip_v6_3 = be32_to_cpu(csk->src_ip[2]);
  2892. l4kwqe2->src_ip_v6_4 = be32_to_cpu(csk->src_ip[3]);
  2893. l4kwqe2->dst_ip_v6_2 = be32_to_cpu(csk->dst_ip[1]);
  2894. l4kwqe2->dst_ip_v6_3 = be32_to_cpu(csk->dst_ip[2]);
  2895. l4kwqe2->dst_ip_v6_4 = be32_to_cpu(csk->dst_ip[3]);
  2896. l4kwqe3->mss = l4kwqe3->pmtu - sizeof(struct ipv6hdr) -
  2897. sizeof(struct tcphdr);
  2898. } else {
  2899. wqes[1] = (struct kwqe *) l4kwqe3;
  2900. l4kwqe3->mss = l4kwqe3->pmtu - sizeof(struct iphdr) -
  2901. sizeof(struct tcphdr);
  2902. }
  2903. l4kwqe1->op_code = L4_KWQE_OPCODE_VALUE_CONNECT1;
  2904. l4kwqe1->flags =
  2905. (L4_LAYER_CODE << L4_KWQ_CONNECT_REQ1_LAYER_CODE_SHIFT) |
  2906. L4_KWQ_CONNECT_REQ3_LINKED_WITH_NEXT;
  2907. l4kwqe1->cid = csk->cid;
  2908. l4kwqe1->pg_cid = csk->pg_cid;
  2909. l4kwqe1->src_ip = be32_to_cpu(csk->src_ip[0]);
  2910. l4kwqe1->dst_ip = be32_to_cpu(csk->dst_ip[0]);
  2911. l4kwqe1->src_port = be16_to_cpu(csk->src_port);
  2912. l4kwqe1->dst_port = be16_to_cpu(csk->dst_port);
  2913. if (csk->tcp_flags & SK_TCP_NO_DELAY_ACK)
  2914. tcp_flags |= L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK;
  2915. if (csk->tcp_flags & SK_TCP_KEEP_ALIVE)
  2916. tcp_flags |= L4_KWQ_CONNECT_REQ1_KEEP_ALIVE;
  2917. if (csk->tcp_flags & SK_TCP_NAGLE)
  2918. tcp_flags |= L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE;
  2919. if (csk->tcp_flags & SK_TCP_TIMESTAMP)
  2920. tcp_flags |= L4_KWQ_CONNECT_REQ1_TIME_STAMP;
  2921. if (csk->tcp_flags & SK_TCP_SACK)
  2922. tcp_flags |= L4_KWQ_CONNECT_REQ1_SACK;
  2923. if (csk->tcp_flags & SK_TCP_SEG_SCALING)
  2924. tcp_flags |= L4_KWQ_CONNECT_REQ1_SEG_SCALING;
  2925. l4kwqe1->tcp_flags = tcp_flags;
  2926. return dev->submit_kwqes(dev, wqes, num_wqes);
  2927. }
  2928. static int cnic_cm_close_req(struct cnic_sock *csk)
  2929. {
  2930. struct cnic_dev *dev = csk->dev;
  2931. struct l4_kwq_close_req *l4kwqe;
  2932. struct kwqe *wqes[1];
  2933. l4kwqe = (struct l4_kwq_close_req *) &csk->kwqe2;
  2934. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2935. wqes[0] = (struct kwqe *) l4kwqe;
  2936. l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_CLOSE;
  2937. l4kwqe->flags = L4_LAYER_CODE << L4_KWQ_CLOSE_REQ_LAYER_CODE_SHIFT;
  2938. l4kwqe->cid = csk->cid;
  2939. return dev->submit_kwqes(dev, wqes, 1);
  2940. }
  2941. static int cnic_cm_abort_req(struct cnic_sock *csk)
  2942. {
  2943. struct cnic_dev *dev = csk->dev;
  2944. struct l4_kwq_reset_req *l4kwqe;
  2945. struct kwqe *wqes[1];
  2946. l4kwqe = (struct l4_kwq_reset_req *) &csk->kwqe2;
  2947. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2948. wqes[0] = (struct kwqe *) l4kwqe;
  2949. l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_RESET;
  2950. l4kwqe->flags = L4_LAYER_CODE << L4_KWQ_RESET_REQ_LAYER_CODE_SHIFT;
  2951. l4kwqe->cid = csk->cid;
  2952. return dev->submit_kwqes(dev, wqes, 1);
  2953. }
  2954. static int cnic_cm_create(struct cnic_dev *dev, int ulp_type, u32 cid,
  2955. u32 l5_cid, struct cnic_sock **csk, void *context)
  2956. {
  2957. struct cnic_local *cp = dev->cnic_priv;
  2958. struct cnic_sock *csk1;
  2959. if (l5_cid >= MAX_CM_SK_TBL_SZ)
  2960. return -EINVAL;
  2961. if (cp->ctx_tbl) {
  2962. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  2963. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  2964. return -EAGAIN;
  2965. }
  2966. csk1 = &cp->csk_tbl[l5_cid];
  2967. if (atomic_read(&csk1->ref_count))
  2968. return -EAGAIN;
  2969. if (test_and_set_bit(SK_F_INUSE, &csk1->flags))
  2970. return -EBUSY;
  2971. csk1->dev = dev;
  2972. csk1->cid = cid;
  2973. csk1->l5_cid = l5_cid;
  2974. csk1->ulp_type = ulp_type;
  2975. csk1->context = context;
  2976. csk1->ka_timeout = DEF_KA_TIMEOUT;
  2977. csk1->ka_interval = DEF_KA_INTERVAL;
  2978. csk1->ka_max_probe_count = DEF_KA_MAX_PROBE_COUNT;
  2979. csk1->tos = DEF_TOS;
  2980. csk1->ttl = DEF_TTL;
  2981. csk1->snd_seq_scale = DEF_SND_SEQ_SCALE;
  2982. csk1->rcv_buf = DEF_RCV_BUF;
  2983. csk1->snd_buf = DEF_SND_BUF;
  2984. csk1->seed = DEF_SEED;
  2985. csk1->tcp_flags = 0;
  2986. *csk = csk1;
  2987. return 0;
  2988. }
  2989. static void cnic_cm_cleanup(struct cnic_sock *csk)
  2990. {
  2991. if (csk->src_port) {
  2992. struct cnic_dev *dev = csk->dev;
  2993. struct cnic_local *cp = dev->cnic_priv;
  2994. cnic_free_id(&cp->csk_port_tbl, be16_to_cpu(csk->src_port));
  2995. csk->src_port = 0;
  2996. }
  2997. }
  2998. static void cnic_close_conn(struct cnic_sock *csk)
  2999. {
  3000. if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags)) {
  3001. cnic_cm_upload_pg(csk);
  3002. clear_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags);
  3003. }
  3004. cnic_cm_cleanup(csk);
  3005. }
  3006. static int cnic_cm_destroy(struct cnic_sock *csk)
  3007. {
  3008. if (!cnic_in_use(csk))
  3009. return -EINVAL;
  3010. csk_hold(csk);
  3011. clear_bit(SK_F_INUSE, &csk->flags);
  3012. smp_mb__after_clear_bit();
  3013. while (atomic_read(&csk->ref_count) != 1)
  3014. msleep(1);
  3015. cnic_cm_cleanup(csk);
  3016. csk->flags = 0;
  3017. csk_put(csk);
  3018. return 0;
  3019. }
  3020. static inline u16 cnic_get_vlan(struct net_device *dev,
  3021. struct net_device **vlan_dev)
  3022. {
  3023. if (dev->priv_flags & IFF_802_1Q_VLAN) {
  3024. *vlan_dev = vlan_dev_real_dev(dev);
  3025. return vlan_dev_vlan_id(dev);
  3026. }
  3027. *vlan_dev = dev;
  3028. return 0;
  3029. }
  3030. static int cnic_get_v4_route(struct sockaddr_in *dst_addr,
  3031. struct dst_entry **dst)
  3032. {
  3033. #if defined(CONFIG_INET)
  3034. struct rtable *rt;
  3035. rt = ip_route_output(&init_net, dst_addr->sin_addr.s_addr, 0, 0, 0);
  3036. if (!IS_ERR(rt)) {
  3037. *dst = &rt->dst;
  3038. return 0;
  3039. }
  3040. return PTR_ERR(rt);
  3041. #else
  3042. return -ENETUNREACH;
  3043. #endif
  3044. }
  3045. static int cnic_get_v6_route(struct sockaddr_in6 *dst_addr,
  3046. struct dst_entry **dst)
  3047. {
  3048. #if defined(CONFIG_IPV6) || (defined(CONFIG_IPV6_MODULE) && defined(MODULE))
  3049. struct flowi6 fl6;
  3050. memset(&fl6, 0, sizeof(fl6));
  3051. fl6.daddr = dst_addr->sin6_addr;
  3052. if (ipv6_addr_type(&fl6.daddr) & IPV6_ADDR_LINKLOCAL)
  3053. fl6.flowi6_oif = dst_addr->sin6_scope_id;
  3054. *dst = ip6_route_output(&init_net, NULL, &fl6);
  3055. if ((*dst)->error) {
  3056. dst_release(*dst);
  3057. *dst = NULL;
  3058. return -ENETUNREACH;
  3059. } else
  3060. return 0;
  3061. #endif
  3062. return -ENETUNREACH;
  3063. }
  3064. static struct cnic_dev *cnic_cm_select_dev(struct sockaddr_in *dst_addr,
  3065. int ulp_type)
  3066. {
  3067. struct cnic_dev *dev = NULL;
  3068. struct dst_entry *dst;
  3069. struct net_device *netdev = NULL;
  3070. int err = -ENETUNREACH;
  3071. if (dst_addr->sin_family == AF_INET)
  3072. err = cnic_get_v4_route(dst_addr, &dst);
  3073. else if (dst_addr->sin_family == AF_INET6) {
  3074. struct sockaddr_in6 *dst_addr6 =
  3075. (struct sockaddr_in6 *) dst_addr;
  3076. err = cnic_get_v6_route(dst_addr6, &dst);
  3077. } else
  3078. return NULL;
  3079. if (err)
  3080. return NULL;
  3081. if (!dst->dev)
  3082. goto done;
  3083. cnic_get_vlan(dst->dev, &netdev);
  3084. dev = cnic_from_netdev(netdev);
  3085. done:
  3086. dst_release(dst);
  3087. if (dev)
  3088. cnic_put(dev);
  3089. return dev;
  3090. }
  3091. static int cnic_resolve_addr(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
  3092. {
  3093. struct cnic_dev *dev = csk->dev;
  3094. struct cnic_local *cp = dev->cnic_priv;
  3095. return cnic_send_nlmsg(cp, ISCSI_KEVENT_PATH_REQ, csk);
  3096. }
  3097. static int cnic_get_route(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
  3098. {
  3099. struct cnic_dev *dev = csk->dev;
  3100. struct cnic_local *cp = dev->cnic_priv;
  3101. int is_v6, rc = 0;
  3102. struct dst_entry *dst = NULL;
  3103. struct net_device *realdev;
  3104. __be16 local_port;
  3105. u32 port_id;
  3106. if (saddr->local.v6.sin6_family == AF_INET6 &&
  3107. saddr->remote.v6.sin6_family == AF_INET6)
  3108. is_v6 = 1;
  3109. else if (saddr->local.v4.sin_family == AF_INET &&
  3110. saddr->remote.v4.sin_family == AF_INET)
  3111. is_v6 = 0;
  3112. else
  3113. return -EINVAL;
  3114. clear_bit(SK_F_IPV6, &csk->flags);
  3115. if (is_v6) {
  3116. set_bit(SK_F_IPV6, &csk->flags);
  3117. cnic_get_v6_route(&saddr->remote.v6, &dst);
  3118. memcpy(&csk->dst_ip[0], &saddr->remote.v6.sin6_addr,
  3119. sizeof(struct in6_addr));
  3120. csk->dst_port = saddr->remote.v6.sin6_port;
  3121. local_port = saddr->local.v6.sin6_port;
  3122. } else {
  3123. cnic_get_v4_route(&saddr->remote.v4, &dst);
  3124. csk->dst_ip[0] = saddr->remote.v4.sin_addr.s_addr;
  3125. csk->dst_port = saddr->remote.v4.sin_port;
  3126. local_port = saddr->local.v4.sin_port;
  3127. }
  3128. csk->vlan_id = 0;
  3129. csk->mtu = dev->netdev->mtu;
  3130. if (dst && dst->dev) {
  3131. u16 vlan = cnic_get_vlan(dst->dev, &realdev);
  3132. if (realdev == dev->netdev) {
  3133. csk->vlan_id = vlan;
  3134. csk->mtu = dst_mtu(dst);
  3135. }
  3136. }
  3137. port_id = be16_to_cpu(local_port);
  3138. if (port_id >= CNIC_LOCAL_PORT_MIN &&
  3139. port_id < CNIC_LOCAL_PORT_MAX) {
  3140. if (cnic_alloc_id(&cp->csk_port_tbl, port_id))
  3141. port_id = 0;
  3142. } else
  3143. port_id = 0;
  3144. if (!port_id) {
  3145. port_id = cnic_alloc_new_id(&cp->csk_port_tbl);
  3146. if (port_id == -1) {
  3147. rc = -ENOMEM;
  3148. goto err_out;
  3149. }
  3150. local_port = cpu_to_be16(port_id);
  3151. }
  3152. csk->src_port = local_port;
  3153. err_out:
  3154. dst_release(dst);
  3155. return rc;
  3156. }
  3157. static void cnic_init_csk_state(struct cnic_sock *csk)
  3158. {
  3159. csk->state = 0;
  3160. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  3161. clear_bit(SK_F_CLOSING, &csk->flags);
  3162. }
  3163. static int cnic_cm_connect(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
  3164. {
  3165. struct cnic_local *cp = csk->dev->cnic_priv;
  3166. int err = 0;
  3167. if (cp->ethdev->drv_state & CNIC_DRV_STATE_NO_ISCSI)
  3168. return -EOPNOTSUPP;
  3169. if (!cnic_in_use(csk))
  3170. return -EINVAL;
  3171. if (test_and_set_bit(SK_F_CONNECT_START, &csk->flags))
  3172. return -EINVAL;
  3173. cnic_init_csk_state(csk);
  3174. err = cnic_get_route(csk, saddr);
  3175. if (err)
  3176. goto err_out;
  3177. err = cnic_resolve_addr(csk, saddr);
  3178. if (!err)
  3179. return 0;
  3180. err_out:
  3181. clear_bit(SK_F_CONNECT_START, &csk->flags);
  3182. return err;
  3183. }
  3184. static int cnic_cm_abort(struct cnic_sock *csk)
  3185. {
  3186. struct cnic_local *cp = csk->dev->cnic_priv;
  3187. u32 opcode = L4_KCQE_OPCODE_VALUE_RESET_COMP;
  3188. if (!cnic_in_use(csk))
  3189. return -EINVAL;
  3190. if (cnic_abort_prep(csk))
  3191. return cnic_cm_abort_req(csk);
  3192. /* Getting here means that we haven't started connect, or
  3193. * connect was not successful, or it has been reset by the target.
  3194. */
  3195. cp->close_conn(csk, opcode);
  3196. if (csk->state != opcode) {
  3197. /* Wait for remote reset sequence to complete */
  3198. while (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
  3199. msleep(1);
  3200. return -EALREADY;
  3201. }
  3202. return 0;
  3203. }
  3204. static int cnic_cm_close(struct cnic_sock *csk)
  3205. {
  3206. if (!cnic_in_use(csk))
  3207. return -EINVAL;
  3208. if (cnic_close_prep(csk)) {
  3209. csk->state = L4_KCQE_OPCODE_VALUE_CLOSE_COMP;
  3210. return cnic_cm_close_req(csk);
  3211. } else {
  3212. /* Wait for remote reset sequence to complete */
  3213. while (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
  3214. msleep(1);
  3215. return -EALREADY;
  3216. }
  3217. return 0;
  3218. }
  3219. static void cnic_cm_upcall(struct cnic_local *cp, struct cnic_sock *csk,
  3220. u8 opcode)
  3221. {
  3222. struct cnic_ulp_ops *ulp_ops;
  3223. int ulp_type = csk->ulp_type;
  3224. rcu_read_lock();
  3225. ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
  3226. if (ulp_ops) {
  3227. if (opcode == L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE)
  3228. ulp_ops->cm_connect_complete(csk);
  3229. else if (opcode == L4_KCQE_OPCODE_VALUE_CLOSE_COMP)
  3230. ulp_ops->cm_close_complete(csk);
  3231. else if (opcode == L4_KCQE_OPCODE_VALUE_RESET_RECEIVED)
  3232. ulp_ops->cm_remote_abort(csk);
  3233. else if (opcode == L4_KCQE_OPCODE_VALUE_RESET_COMP)
  3234. ulp_ops->cm_abort_complete(csk);
  3235. else if (opcode == L4_KCQE_OPCODE_VALUE_CLOSE_RECEIVED)
  3236. ulp_ops->cm_remote_close(csk);
  3237. }
  3238. rcu_read_unlock();
  3239. }
  3240. static int cnic_cm_set_pg(struct cnic_sock *csk)
  3241. {
  3242. if (cnic_offld_prep(csk)) {
  3243. if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
  3244. cnic_cm_update_pg(csk);
  3245. else
  3246. cnic_cm_offload_pg(csk);
  3247. }
  3248. return 0;
  3249. }
  3250. static void cnic_cm_process_offld_pg(struct cnic_dev *dev, struct l4_kcq *kcqe)
  3251. {
  3252. struct cnic_local *cp = dev->cnic_priv;
  3253. u32 l5_cid = kcqe->pg_host_opaque;
  3254. u8 opcode = kcqe->op_code;
  3255. struct cnic_sock *csk = &cp->csk_tbl[l5_cid];
  3256. csk_hold(csk);
  3257. if (!cnic_in_use(csk))
  3258. goto done;
  3259. if (opcode == L4_KCQE_OPCODE_VALUE_UPDATE_PG) {
  3260. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  3261. goto done;
  3262. }
  3263. /* Possible PG kcqe status: SUCCESS, OFFLOADED_PG, or CTX_ALLOC_FAIL */
  3264. if (kcqe->status == L4_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAIL) {
  3265. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  3266. cnic_cm_upcall(cp, csk,
  3267. L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
  3268. goto done;
  3269. }
  3270. csk->pg_cid = kcqe->pg_cid;
  3271. set_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags);
  3272. cnic_cm_conn_req(csk);
  3273. done:
  3274. csk_put(csk);
  3275. }
  3276. static void cnic_process_fcoe_term_conn(struct cnic_dev *dev, struct kcqe *kcqe)
  3277. {
  3278. struct cnic_local *cp = dev->cnic_priv;
  3279. struct fcoe_kcqe *fc_kcqe = (struct fcoe_kcqe *) kcqe;
  3280. u32 l5_cid = fc_kcqe->fcoe_conn_id + BNX2X_FCOE_L5_CID_BASE;
  3281. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  3282. ctx->timestamp = jiffies;
  3283. ctx->wait_cond = 1;
  3284. wake_up(&ctx->waitq);
  3285. }
  3286. static void cnic_cm_process_kcqe(struct cnic_dev *dev, struct kcqe *kcqe)
  3287. {
  3288. struct cnic_local *cp = dev->cnic_priv;
  3289. struct l4_kcq *l4kcqe = (struct l4_kcq *) kcqe;
  3290. u8 opcode = l4kcqe->op_code;
  3291. u32 l5_cid;
  3292. struct cnic_sock *csk;
  3293. if (opcode == FCOE_RAMROD_CMD_ID_TERMINATE_CONN) {
  3294. cnic_process_fcoe_term_conn(dev, kcqe);
  3295. return;
  3296. }
  3297. if (opcode == L4_KCQE_OPCODE_VALUE_OFFLOAD_PG ||
  3298. opcode == L4_KCQE_OPCODE_VALUE_UPDATE_PG) {
  3299. cnic_cm_process_offld_pg(dev, l4kcqe);
  3300. return;
  3301. }
  3302. l5_cid = l4kcqe->conn_id;
  3303. if (opcode & 0x80)
  3304. l5_cid = l4kcqe->cid;
  3305. if (l5_cid >= MAX_CM_SK_TBL_SZ)
  3306. return;
  3307. csk = &cp->csk_tbl[l5_cid];
  3308. csk_hold(csk);
  3309. if (!cnic_in_use(csk)) {
  3310. csk_put(csk);
  3311. return;
  3312. }
  3313. switch (opcode) {
  3314. case L5CM_RAMROD_CMD_ID_TCP_CONNECT:
  3315. if (l4kcqe->status != 0) {
  3316. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  3317. cnic_cm_upcall(cp, csk,
  3318. L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
  3319. }
  3320. break;
  3321. case L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE:
  3322. if (l4kcqe->status == 0)
  3323. set_bit(SK_F_OFFLD_COMPLETE, &csk->flags);
  3324. else if (l4kcqe->status ==
  3325. L4_KCQE_COMPLETION_STATUS_PARITY_ERROR)
  3326. set_bit(SK_F_HW_ERR, &csk->flags);
  3327. smp_mb__before_clear_bit();
  3328. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  3329. cnic_cm_upcall(cp, csk, opcode);
  3330. break;
  3331. case L5CM_RAMROD_CMD_ID_CLOSE: {
  3332. struct iscsi_kcqe *l5kcqe = (struct iscsi_kcqe *) kcqe;
  3333. if (l4kcqe->status != 0 || l5kcqe->completion_status != 0) {
  3334. netdev_warn(dev->netdev, "RAMROD CLOSE compl with status 0x%x completion status 0x%x\n",
  3335. l4kcqe->status, l5kcqe->completion_status);
  3336. opcode = L4_KCQE_OPCODE_VALUE_CLOSE_COMP;
  3337. /* Fall through */
  3338. } else {
  3339. break;
  3340. }
  3341. }
  3342. case L4_KCQE_OPCODE_VALUE_RESET_RECEIVED:
  3343. case L4_KCQE_OPCODE_VALUE_CLOSE_COMP:
  3344. case L4_KCQE_OPCODE_VALUE_RESET_COMP:
  3345. case L5CM_RAMROD_CMD_ID_SEARCHER_DELETE:
  3346. case L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD:
  3347. if (l4kcqe->status == L4_KCQE_COMPLETION_STATUS_PARITY_ERROR)
  3348. set_bit(SK_F_HW_ERR, &csk->flags);
  3349. cp->close_conn(csk, opcode);
  3350. break;
  3351. case L4_KCQE_OPCODE_VALUE_CLOSE_RECEIVED:
  3352. /* after we already sent CLOSE_REQ */
  3353. if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags) &&
  3354. !test_bit(SK_F_OFFLD_COMPLETE, &csk->flags) &&
  3355. csk->state == L4_KCQE_OPCODE_VALUE_CLOSE_COMP)
  3356. cp->close_conn(csk, L4_KCQE_OPCODE_VALUE_RESET_COMP);
  3357. else
  3358. cnic_cm_upcall(cp, csk, opcode);
  3359. break;
  3360. }
  3361. csk_put(csk);
  3362. }
  3363. static void cnic_cm_indicate_kcqe(void *data, struct kcqe *kcqe[], u32 num)
  3364. {
  3365. struct cnic_dev *dev = data;
  3366. int i;
  3367. for (i = 0; i < num; i++)
  3368. cnic_cm_process_kcqe(dev, kcqe[i]);
  3369. }
  3370. static struct cnic_ulp_ops cm_ulp_ops = {
  3371. .indicate_kcqes = cnic_cm_indicate_kcqe,
  3372. };
  3373. static void cnic_cm_free_mem(struct cnic_dev *dev)
  3374. {
  3375. struct cnic_local *cp = dev->cnic_priv;
  3376. kfree(cp->csk_tbl);
  3377. cp->csk_tbl = NULL;
  3378. cnic_free_id_tbl(&cp->csk_port_tbl);
  3379. }
  3380. static int cnic_cm_alloc_mem(struct cnic_dev *dev)
  3381. {
  3382. struct cnic_local *cp = dev->cnic_priv;
  3383. u32 port_id;
  3384. cp->csk_tbl = kzalloc(sizeof(struct cnic_sock) * MAX_CM_SK_TBL_SZ,
  3385. GFP_KERNEL);
  3386. if (!cp->csk_tbl)
  3387. return -ENOMEM;
  3388. port_id = prandom_u32();
  3389. port_id %= CNIC_LOCAL_PORT_RANGE;
  3390. if (cnic_init_id_tbl(&cp->csk_port_tbl, CNIC_LOCAL_PORT_RANGE,
  3391. CNIC_LOCAL_PORT_MIN, port_id)) {
  3392. cnic_cm_free_mem(dev);
  3393. return -ENOMEM;
  3394. }
  3395. return 0;
  3396. }
  3397. static int cnic_ready_to_close(struct cnic_sock *csk, u32 opcode)
  3398. {
  3399. if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  3400. /* Unsolicited RESET_COMP or RESET_RECEIVED */
  3401. opcode = L4_KCQE_OPCODE_VALUE_RESET_RECEIVED;
  3402. csk->state = opcode;
  3403. }
  3404. /* 1. If event opcode matches the expected event in csk->state
  3405. * 2. If the expected event is CLOSE_COMP or RESET_COMP, we accept any
  3406. * event
  3407. * 3. If the expected event is 0, meaning the connection was never
  3408. * never established, we accept the opcode from cm_abort.
  3409. */
  3410. if (opcode == csk->state || csk->state == 0 ||
  3411. csk->state == L4_KCQE_OPCODE_VALUE_CLOSE_COMP ||
  3412. csk->state == L4_KCQE_OPCODE_VALUE_RESET_COMP) {
  3413. if (!test_and_set_bit(SK_F_CLOSING, &csk->flags)) {
  3414. if (csk->state == 0)
  3415. csk->state = opcode;
  3416. return 1;
  3417. }
  3418. }
  3419. return 0;
  3420. }
  3421. static void cnic_close_bnx2_conn(struct cnic_sock *csk, u32 opcode)
  3422. {
  3423. struct cnic_dev *dev = csk->dev;
  3424. struct cnic_local *cp = dev->cnic_priv;
  3425. if (opcode == L4_KCQE_OPCODE_VALUE_RESET_RECEIVED) {
  3426. cnic_cm_upcall(cp, csk, opcode);
  3427. return;
  3428. }
  3429. clear_bit(SK_F_CONNECT_START, &csk->flags);
  3430. cnic_close_conn(csk);
  3431. csk->state = opcode;
  3432. cnic_cm_upcall(cp, csk, opcode);
  3433. }
  3434. static void cnic_cm_stop_bnx2_hw(struct cnic_dev *dev)
  3435. {
  3436. }
  3437. static int cnic_cm_init_bnx2_hw(struct cnic_dev *dev)
  3438. {
  3439. u32 seed;
  3440. seed = prandom_u32();
  3441. cnic_ctx_wr(dev, 45, 0, seed);
  3442. return 0;
  3443. }
  3444. static void cnic_close_bnx2x_conn(struct cnic_sock *csk, u32 opcode)
  3445. {
  3446. struct cnic_dev *dev = csk->dev;
  3447. struct cnic_local *cp = dev->cnic_priv;
  3448. struct cnic_context *ctx = &cp->ctx_tbl[csk->l5_cid];
  3449. union l5cm_specific_data l5_data;
  3450. u32 cmd = 0;
  3451. int close_complete = 0;
  3452. switch (opcode) {
  3453. case L4_KCQE_OPCODE_VALUE_RESET_RECEIVED:
  3454. case L4_KCQE_OPCODE_VALUE_CLOSE_COMP:
  3455. case L4_KCQE_OPCODE_VALUE_RESET_COMP:
  3456. if (cnic_ready_to_close(csk, opcode)) {
  3457. if (test_bit(SK_F_HW_ERR, &csk->flags))
  3458. close_complete = 1;
  3459. else if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
  3460. cmd = L5CM_RAMROD_CMD_ID_SEARCHER_DELETE;
  3461. else
  3462. close_complete = 1;
  3463. }
  3464. break;
  3465. case L5CM_RAMROD_CMD_ID_SEARCHER_DELETE:
  3466. cmd = L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD;
  3467. break;
  3468. case L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD:
  3469. close_complete = 1;
  3470. break;
  3471. }
  3472. if (cmd) {
  3473. memset(&l5_data, 0, sizeof(l5_data));
  3474. cnic_submit_kwqe_16(dev, cmd, csk->cid, ISCSI_CONNECTION_TYPE,
  3475. &l5_data);
  3476. } else if (close_complete) {
  3477. ctx->timestamp = jiffies;
  3478. cnic_close_conn(csk);
  3479. cnic_cm_upcall(cp, csk, csk->state);
  3480. }
  3481. }
  3482. static void cnic_cm_stop_bnx2x_hw(struct cnic_dev *dev)
  3483. {
  3484. struct cnic_local *cp = dev->cnic_priv;
  3485. if (!cp->ctx_tbl)
  3486. return;
  3487. if (!netif_running(dev->netdev))
  3488. return;
  3489. cnic_bnx2x_delete_wait(dev, 0);
  3490. cancel_delayed_work(&cp->delete_task);
  3491. flush_workqueue(cnic_wq);
  3492. if (atomic_read(&cp->iscsi_conn) != 0)
  3493. netdev_warn(dev->netdev, "%d iSCSI connections not destroyed\n",
  3494. atomic_read(&cp->iscsi_conn));
  3495. }
  3496. static int cnic_cm_init_bnx2x_hw(struct cnic_dev *dev)
  3497. {
  3498. struct cnic_local *cp = dev->cnic_priv;
  3499. struct bnx2x *bp = netdev_priv(dev->netdev);
  3500. u32 pfid = cp->pfid;
  3501. u32 port = CNIC_PORT(cp);
  3502. cnic_init_bnx2x_mac(dev);
  3503. cnic_bnx2x_set_tcp_options(dev, 0, 1);
  3504. CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
  3505. XSTORM_ISCSI_LOCAL_VLAN_OFFSET(pfid), 0);
  3506. CNIC_WR(dev, BAR_XSTRORM_INTMEM +
  3507. XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_ENABLED_OFFSET(port), 1);
  3508. CNIC_WR(dev, BAR_XSTRORM_INTMEM +
  3509. XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_MAX_COUNT_OFFSET(port),
  3510. DEF_MAX_DA_COUNT);
  3511. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  3512. XSTORM_ISCSI_TCP_VARS_TTL_OFFSET(pfid), DEF_TTL);
  3513. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  3514. XSTORM_ISCSI_TCP_VARS_TOS_OFFSET(pfid), DEF_TOS);
  3515. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  3516. XSTORM_ISCSI_TCP_VARS_ADV_WND_SCL_OFFSET(pfid), 2);
  3517. CNIC_WR(dev, BAR_XSTRORM_INTMEM +
  3518. XSTORM_TCP_TX_SWS_TIMER_VAL_OFFSET(pfid), DEF_SWS_TIMER);
  3519. CNIC_WR(dev, BAR_TSTRORM_INTMEM + TSTORM_TCP_MAX_CWND_OFFSET(pfid),
  3520. DEF_MAX_CWND);
  3521. return 0;
  3522. }
  3523. static void cnic_delete_task(struct work_struct *work)
  3524. {
  3525. struct cnic_local *cp;
  3526. struct cnic_dev *dev;
  3527. u32 i;
  3528. int need_resched = 0;
  3529. cp = container_of(work, struct cnic_local, delete_task.work);
  3530. dev = cp->dev;
  3531. if (test_and_clear_bit(CNIC_LCL_FL_STOP_ISCSI, &cp->cnic_local_flags)) {
  3532. struct drv_ctl_info info;
  3533. cnic_ulp_stop_one(cp, CNIC_ULP_ISCSI);
  3534. info.cmd = DRV_CTL_ISCSI_STOPPED_CMD;
  3535. cp->ethdev->drv_ctl(dev->netdev, &info);
  3536. }
  3537. for (i = 0; i < cp->max_cid_space; i++) {
  3538. struct cnic_context *ctx = &cp->ctx_tbl[i];
  3539. int err;
  3540. if (!test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags) ||
  3541. !test_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
  3542. continue;
  3543. if (!time_after(jiffies, ctx->timestamp + (2 * HZ))) {
  3544. need_resched = 1;
  3545. continue;
  3546. }
  3547. if (!test_and_clear_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
  3548. continue;
  3549. err = cnic_bnx2x_destroy_ramrod(dev, i);
  3550. cnic_free_bnx2x_conn_resc(dev, i);
  3551. if (!err) {
  3552. if (ctx->ulp_proto_id == CNIC_ULP_ISCSI)
  3553. atomic_dec(&cp->iscsi_conn);
  3554. clear_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  3555. }
  3556. }
  3557. if (need_resched)
  3558. queue_delayed_work(cnic_wq, &cp->delete_task,
  3559. msecs_to_jiffies(10));
  3560. }
  3561. static int cnic_cm_open(struct cnic_dev *dev)
  3562. {
  3563. struct cnic_local *cp = dev->cnic_priv;
  3564. int err;
  3565. err = cnic_cm_alloc_mem(dev);
  3566. if (err)
  3567. return err;
  3568. err = cp->start_cm(dev);
  3569. if (err)
  3570. goto err_out;
  3571. INIT_DELAYED_WORK(&cp->delete_task, cnic_delete_task);
  3572. dev->cm_create = cnic_cm_create;
  3573. dev->cm_destroy = cnic_cm_destroy;
  3574. dev->cm_connect = cnic_cm_connect;
  3575. dev->cm_abort = cnic_cm_abort;
  3576. dev->cm_close = cnic_cm_close;
  3577. dev->cm_select_dev = cnic_cm_select_dev;
  3578. cp->ulp_handle[CNIC_ULP_L4] = dev;
  3579. rcu_assign_pointer(cp->ulp_ops[CNIC_ULP_L4], &cm_ulp_ops);
  3580. return 0;
  3581. err_out:
  3582. cnic_cm_free_mem(dev);
  3583. return err;
  3584. }
  3585. static int cnic_cm_shutdown(struct cnic_dev *dev)
  3586. {
  3587. struct cnic_local *cp = dev->cnic_priv;
  3588. int i;
  3589. if (!cp->csk_tbl)
  3590. return 0;
  3591. for (i = 0; i < MAX_CM_SK_TBL_SZ; i++) {
  3592. struct cnic_sock *csk = &cp->csk_tbl[i];
  3593. clear_bit(SK_F_INUSE, &csk->flags);
  3594. cnic_cm_cleanup(csk);
  3595. }
  3596. cnic_cm_free_mem(dev);
  3597. return 0;
  3598. }
  3599. static void cnic_init_context(struct cnic_dev *dev, u32 cid)
  3600. {
  3601. u32 cid_addr;
  3602. int i;
  3603. cid_addr = GET_CID_ADDR(cid);
  3604. for (i = 0; i < CTX_SIZE; i += 4)
  3605. cnic_ctx_wr(dev, cid_addr, i, 0);
  3606. }
  3607. static int cnic_setup_5709_context(struct cnic_dev *dev, int valid)
  3608. {
  3609. struct cnic_local *cp = dev->cnic_priv;
  3610. int ret = 0, i;
  3611. u32 valid_bit = valid ? BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID : 0;
  3612. if (BNX2_CHIP(cp) != BNX2_CHIP_5709)
  3613. return 0;
  3614. for (i = 0; i < cp->ctx_blks; i++) {
  3615. int j;
  3616. u32 idx = cp->ctx_arr[i].cid / cp->cids_per_blk;
  3617. u32 val;
  3618. memset(cp->ctx_arr[i].ctx, 0, BNX2_PAGE_SIZE);
  3619. CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_DATA0,
  3620. (cp->ctx_arr[i].mapping & 0xffffffff) | valid_bit);
  3621. CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_DATA1,
  3622. (u64) cp->ctx_arr[i].mapping >> 32);
  3623. CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_CTRL, idx |
  3624. BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
  3625. for (j = 0; j < 10; j++) {
  3626. val = CNIC_RD(dev, BNX2_CTX_HOST_PAGE_TBL_CTRL);
  3627. if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
  3628. break;
  3629. udelay(5);
  3630. }
  3631. if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
  3632. ret = -EBUSY;
  3633. break;
  3634. }
  3635. }
  3636. return ret;
  3637. }
  3638. static void cnic_free_irq(struct cnic_dev *dev)
  3639. {
  3640. struct cnic_local *cp = dev->cnic_priv;
  3641. struct cnic_eth_dev *ethdev = cp->ethdev;
  3642. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3643. cp->disable_int_sync(dev);
  3644. tasklet_kill(&cp->cnic_irq_task);
  3645. free_irq(ethdev->irq_arr[0].vector, dev);
  3646. }
  3647. }
  3648. static int cnic_request_irq(struct cnic_dev *dev)
  3649. {
  3650. struct cnic_local *cp = dev->cnic_priv;
  3651. struct cnic_eth_dev *ethdev = cp->ethdev;
  3652. int err;
  3653. err = request_irq(ethdev->irq_arr[0].vector, cnic_irq, 0, "cnic", dev);
  3654. if (err)
  3655. tasklet_disable(&cp->cnic_irq_task);
  3656. return err;
  3657. }
  3658. static int cnic_init_bnx2_irq(struct cnic_dev *dev)
  3659. {
  3660. struct cnic_local *cp = dev->cnic_priv;
  3661. struct cnic_eth_dev *ethdev = cp->ethdev;
  3662. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3663. int err, i = 0;
  3664. int sblk_num = cp->status_blk_num;
  3665. u32 base = ((sblk_num - 1) * BNX2_HC_SB_CONFIG_SIZE) +
  3666. BNX2_HC_SB_CONFIG_1;
  3667. CNIC_WR(dev, base, BNX2_HC_SB_CONFIG_1_ONE_SHOT);
  3668. CNIC_WR(dev, base + BNX2_HC_COMP_PROD_TRIP_OFF, (2 << 16) | 8);
  3669. CNIC_WR(dev, base + BNX2_HC_COM_TICKS_OFF, (64 << 16) | 220);
  3670. CNIC_WR(dev, base + BNX2_HC_CMD_TICKS_OFF, (64 << 16) | 220);
  3671. cp->last_status_idx = cp->status_blk.bnx2->status_idx;
  3672. tasklet_init(&cp->cnic_irq_task, cnic_service_bnx2_msix,
  3673. (unsigned long) dev);
  3674. err = cnic_request_irq(dev);
  3675. if (err)
  3676. return err;
  3677. while (cp->status_blk.bnx2->status_completion_producer_index &&
  3678. i < 10) {
  3679. CNIC_WR(dev, BNX2_HC_COALESCE_NOW,
  3680. 1 << (11 + sblk_num));
  3681. udelay(10);
  3682. i++;
  3683. barrier();
  3684. }
  3685. if (cp->status_blk.bnx2->status_completion_producer_index) {
  3686. cnic_free_irq(dev);
  3687. goto failed;
  3688. }
  3689. } else {
  3690. struct status_block *sblk = cp->status_blk.gen;
  3691. u32 hc_cmd = CNIC_RD(dev, BNX2_HC_COMMAND);
  3692. int i = 0;
  3693. while (sblk->status_completion_producer_index && i < 10) {
  3694. CNIC_WR(dev, BNX2_HC_COMMAND,
  3695. hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
  3696. udelay(10);
  3697. i++;
  3698. barrier();
  3699. }
  3700. if (sblk->status_completion_producer_index)
  3701. goto failed;
  3702. }
  3703. return 0;
  3704. failed:
  3705. netdev_err(dev->netdev, "KCQ index not resetting to 0\n");
  3706. return -EBUSY;
  3707. }
  3708. static void cnic_enable_bnx2_int(struct cnic_dev *dev)
  3709. {
  3710. struct cnic_local *cp = dev->cnic_priv;
  3711. struct cnic_eth_dev *ethdev = cp->ethdev;
  3712. if (!(ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
  3713. return;
  3714. CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
  3715. BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | cp->last_status_idx);
  3716. }
  3717. static void cnic_disable_bnx2_int_sync(struct cnic_dev *dev)
  3718. {
  3719. struct cnic_local *cp = dev->cnic_priv;
  3720. struct cnic_eth_dev *ethdev = cp->ethdev;
  3721. if (!(ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
  3722. return;
  3723. CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
  3724. BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
  3725. CNIC_RD(dev, BNX2_PCICFG_INT_ACK_CMD);
  3726. synchronize_irq(ethdev->irq_arr[0].vector);
  3727. }
  3728. static void cnic_init_bnx2_tx_ring(struct cnic_dev *dev)
  3729. {
  3730. struct cnic_local *cp = dev->cnic_priv;
  3731. struct cnic_eth_dev *ethdev = cp->ethdev;
  3732. struct cnic_uio_dev *udev = cp->udev;
  3733. u32 cid_addr, tx_cid, sb_id;
  3734. u32 val, offset0, offset1, offset2, offset3;
  3735. int i;
  3736. struct bnx2_tx_bd *txbd;
  3737. dma_addr_t buf_map, ring_map = udev->l2_ring_map;
  3738. struct status_block *s_blk = cp->status_blk.gen;
  3739. sb_id = cp->status_blk_num;
  3740. tx_cid = 20;
  3741. cp->tx_cons_ptr = &s_blk->status_tx_quick_consumer_index2;
  3742. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3743. struct status_block_msix *sblk = cp->status_blk.bnx2;
  3744. tx_cid = TX_TSS_CID + sb_id - 1;
  3745. CNIC_WR(dev, BNX2_TSCH_TSS_CFG, (sb_id << 24) |
  3746. (TX_TSS_CID << 7));
  3747. cp->tx_cons_ptr = &sblk->status_tx_quick_consumer_index;
  3748. }
  3749. cp->tx_cons = *cp->tx_cons_ptr;
  3750. cid_addr = GET_CID_ADDR(tx_cid);
  3751. if (BNX2_CHIP(cp) == BNX2_CHIP_5709) {
  3752. u32 cid_addr2 = GET_CID_ADDR(tx_cid + 4) + 0x40;
  3753. for (i = 0; i < PHY_CTX_SIZE; i += 4)
  3754. cnic_ctx_wr(dev, cid_addr2, i, 0);
  3755. offset0 = BNX2_L2CTX_TYPE_XI;
  3756. offset1 = BNX2_L2CTX_CMD_TYPE_XI;
  3757. offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
  3758. offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
  3759. } else {
  3760. cnic_init_context(dev, tx_cid);
  3761. cnic_init_context(dev, tx_cid + 1);
  3762. offset0 = BNX2_L2CTX_TYPE;
  3763. offset1 = BNX2_L2CTX_CMD_TYPE;
  3764. offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
  3765. offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
  3766. }
  3767. val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
  3768. cnic_ctx_wr(dev, cid_addr, offset0, val);
  3769. val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
  3770. cnic_ctx_wr(dev, cid_addr, offset1, val);
  3771. txbd = udev->l2_ring;
  3772. buf_map = udev->l2_buf_map;
  3773. for (i = 0; i < BNX2_MAX_TX_DESC_CNT; i++, txbd++) {
  3774. txbd->tx_bd_haddr_hi = (u64) buf_map >> 32;
  3775. txbd->tx_bd_haddr_lo = (u64) buf_map & 0xffffffff;
  3776. }
  3777. val = (u64) ring_map >> 32;
  3778. cnic_ctx_wr(dev, cid_addr, offset2, val);
  3779. txbd->tx_bd_haddr_hi = val;
  3780. val = (u64) ring_map & 0xffffffff;
  3781. cnic_ctx_wr(dev, cid_addr, offset3, val);
  3782. txbd->tx_bd_haddr_lo = val;
  3783. }
  3784. static void cnic_init_bnx2_rx_ring(struct cnic_dev *dev)
  3785. {
  3786. struct cnic_local *cp = dev->cnic_priv;
  3787. struct cnic_eth_dev *ethdev = cp->ethdev;
  3788. struct cnic_uio_dev *udev = cp->udev;
  3789. u32 cid_addr, sb_id, val, coal_reg, coal_val;
  3790. int i;
  3791. struct bnx2_rx_bd *rxbd;
  3792. struct status_block *s_blk = cp->status_blk.gen;
  3793. dma_addr_t ring_map = udev->l2_ring_map;
  3794. sb_id = cp->status_blk_num;
  3795. cnic_init_context(dev, 2);
  3796. cp->rx_cons_ptr = &s_blk->status_rx_quick_consumer_index2;
  3797. coal_reg = BNX2_HC_COMMAND;
  3798. coal_val = CNIC_RD(dev, coal_reg);
  3799. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3800. struct status_block_msix *sblk = cp->status_blk.bnx2;
  3801. cp->rx_cons_ptr = &sblk->status_rx_quick_consumer_index;
  3802. coal_reg = BNX2_HC_COALESCE_NOW;
  3803. coal_val = 1 << (11 + sb_id);
  3804. }
  3805. i = 0;
  3806. while (!(*cp->rx_cons_ptr != 0) && i < 10) {
  3807. CNIC_WR(dev, coal_reg, coal_val);
  3808. udelay(10);
  3809. i++;
  3810. barrier();
  3811. }
  3812. cp->rx_cons = *cp->rx_cons_ptr;
  3813. cid_addr = GET_CID_ADDR(2);
  3814. val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE |
  3815. BNX2_L2CTX_CTX_TYPE_SIZE_L2 | (0x02 << 8);
  3816. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_CTX_TYPE, val);
  3817. if (sb_id == 0)
  3818. val = 2 << BNX2_L2CTX_L2_STATUSB_NUM_SHIFT;
  3819. else
  3820. val = BNX2_L2CTX_L2_STATUSB_NUM(sb_id);
  3821. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_HOST_BDIDX, val);
  3822. rxbd = udev->l2_ring + BNX2_PAGE_SIZE;
  3823. for (i = 0; i < BNX2_MAX_RX_DESC_CNT; i++, rxbd++) {
  3824. dma_addr_t buf_map;
  3825. int n = (i % cp->l2_rx_ring_size) + 1;
  3826. buf_map = udev->l2_buf_map + (n * cp->l2_single_buf_size);
  3827. rxbd->rx_bd_len = cp->l2_single_buf_size;
  3828. rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
  3829. rxbd->rx_bd_haddr_hi = (u64) buf_map >> 32;
  3830. rxbd->rx_bd_haddr_lo = (u64) buf_map & 0xffffffff;
  3831. }
  3832. val = (u64) (ring_map + BNX2_PAGE_SIZE) >> 32;
  3833. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
  3834. rxbd->rx_bd_haddr_hi = val;
  3835. val = (u64) (ring_map + BNX2_PAGE_SIZE) & 0xffffffff;
  3836. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
  3837. rxbd->rx_bd_haddr_lo = val;
  3838. val = cnic_reg_rd_ind(dev, BNX2_RXP_SCRATCH_RXP_FLOOD);
  3839. cnic_reg_wr_ind(dev, BNX2_RXP_SCRATCH_RXP_FLOOD, val | (1 << 2));
  3840. }
  3841. static void cnic_shutdown_bnx2_rx_ring(struct cnic_dev *dev)
  3842. {
  3843. struct kwqe *wqes[1], l2kwqe;
  3844. memset(&l2kwqe, 0, sizeof(l2kwqe));
  3845. wqes[0] = &l2kwqe;
  3846. l2kwqe.kwqe_op_flag = (L2_LAYER_CODE << KWQE_LAYER_SHIFT) |
  3847. (L2_KWQE_OPCODE_VALUE_FLUSH <<
  3848. KWQE_OPCODE_SHIFT) | 2;
  3849. dev->submit_kwqes(dev, wqes, 1);
  3850. }
  3851. static void cnic_set_bnx2_mac(struct cnic_dev *dev)
  3852. {
  3853. struct cnic_local *cp = dev->cnic_priv;
  3854. u32 val;
  3855. val = cp->func << 2;
  3856. cp->shmem_base = cnic_reg_rd_ind(dev, BNX2_SHM_HDR_ADDR_0 + val);
  3857. val = cnic_reg_rd_ind(dev, cp->shmem_base +
  3858. BNX2_PORT_HW_CFG_ISCSI_MAC_UPPER);
  3859. dev->mac_addr[0] = (u8) (val >> 8);
  3860. dev->mac_addr[1] = (u8) val;
  3861. CNIC_WR(dev, BNX2_EMAC_MAC_MATCH4, val);
  3862. val = cnic_reg_rd_ind(dev, cp->shmem_base +
  3863. BNX2_PORT_HW_CFG_ISCSI_MAC_LOWER);
  3864. dev->mac_addr[2] = (u8) (val >> 24);
  3865. dev->mac_addr[3] = (u8) (val >> 16);
  3866. dev->mac_addr[4] = (u8) (val >> 8);
  3867. dev->mac_addr[5] = (u8) val;
  3868. CNIC_WR(dev, BNX2_EMAC_MAC_MATCH5, val);
  3869. val = 4 | BNX2_RPM_SORT_USER2_BC_EN;
  3870. if (BNX2_CHIP(cp) != BNX2_CHIP_5709)
  3871. val |= BNX2_RPM_SORT_USER2_PROM_VLAN;
  3872. CNIC_WR(dev, BNX2_RPM_SORT_USER2, 0x0);
  3873. CNIC_WR(dev, BNX2_RPM_SORT_USER2, val);
  3874. CNIC_WR(dev, BNX2_RPM_SORT_USER2, val | BNX2_RPM_SORT_USER2_ENA);
  3875. }
  3876. static int cnic_start_bnx2_hw(struct cnic_dev *dev)
  3877. {
  3878. struct cnic_local *cp = dev->cnic_priv;
  3879. struct cnic_eth_dev *ethdev = cp->ethdev;
  3880. struct status_block *sblk = cp->status_blk.gen;
  3881. u32 val, kcq_cid_addr, kwq_cid_addr;
  3882. int err;
  3883. cnic_set_bnx2_mac(dev);
  3884. val = CNIC_RD(dev, BNX2_MQ_CONFIG);
  3885. val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
  3886. if (BNX2_PAGE_BITS > 12)
  3887. val |= (12 - 8) << 4;
  3888. else
  3889. val |= (BNX2_PAGE_BITS - 8) << 4;
  3890. CNIC_WR(dev, BNX2_MQ_CONFIG, val);
  3891. CNIC_WR(dev, BNX2_HC_COMP_PROD_TRIP, (2 << 16) | 8);
  3892. CNIC_WR(dev, BNX2_HC_COM_TICKS, (64 << 16) | 220);
  3893. CNIC_WR(dev, BNX2_HC_CMD_TICKS, (64 << 16) | 220);
  3894. err = cnic_setup_5709_context(dev, 1);
  3895. if (err)
  3896. return err;
  3897. cnic_init_context(dev, KWQ_CID);
  3898. cnic_init_context(dev, KCQ_CID);
  3899. kwq_cid_addr = GET_CID_ADDR(KWQ_CID);
  3900. cp->kwq_io_addr = MB_GET_CID_ADDR(KWQ_CID) + L5_KRNLQ_HOST_QIDX;
  3901. cp->max_kwq_idx = MAX_KWQ_IDX;
  3902. cp->kwq_prod_idx = 0;
  3903. cp->kwq_con_idx = 0;
  3904. set_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags);
  3905. if (BNX2_CHIP(cp) == BNX2_CHIP_5706 || BNX2_CHIP(cp) == BNX2_CHIP_5708)
  3906. cp->kwq_con_idx_ptr = &sblk->status_rx_quick_consumer_index15;
  3907. else
  3908. cp->kwq_con_idx_ptr = &sblk->status_cmd_consumer_index;
  3909. /* Initialize the kernel work queue context. */
  3910. val = KRNLQ_TYPE_TYPE_KRNLQ | KRNLQ_SIZE_TYPE_SIZE |
  3911. (BNX2_PAGE_BITS - 8) | KRNLQ_FLAGS_QE_SELF_SEQ;
  3912. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_TYPE, val);
  3913. val = (BNX2_PAGE_SIZE / sizeof(struct kwqe) - 1) << 16;
  3914. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_QE_SELF_SEQ_MAX, val);
  3915. val = ((BNX2_PAGE_SIZE / sizeof(struct kwqe)) << 16) | KWQ_PAGE_CNT;
  3916. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_NPAGES, val);
  3917. val = (u32) ((u64) cp->kwq_info.pgtbl_map >> 32);
  3918. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_HADDR_HI, val);
  3919. val = (u32) cp->kwq_info.pgtbl_map;
  3920. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_HADDR_LO, val);
  3921. kcq_cid_addr = GET_CID_ADDR(KCQ_CID);
  3922. cp->kcq1.io_addr = MB_GET_CID_ADDR(KCQ_CID) + L5_KRNLQ_HOST_QIDX;
  3923. cp->kcq1.sw_prod_idx = 0;
  3924. cp->kcq1.hw_prod_idx_ptr =
  3925. &sblk->status_completion_producer_index;
  3926. cp->kcq1.status_idx_ptr = &sblk->status_idx;
  3927. /* Initialize the kernel complete queue context. */
  3928. val = KRNLQ_TYPE_TYPE_KRNLQ | KRNLQ_SIZE_TYPE_SIZE |
  3929. (BNX2_PAGE_BITS - 8) | KRNLQ_FLAGS_QE_SELF_SEQ;
  3930. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_TYPE, val);
  3931. val = (BNX2_PAGE_SIZE / sizeof(struct kcqe) - 1) << 16;
  3932. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_QE_SELF_SEQ_MAX, val);
  3933. val = ((BNX2_PAGE_SIZE / sizeof(struct kcqe)) << 16) | KCQ_PAGE_CNT;
  3934. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_NPAGES, val);
  3935. val = (u32) ((u64) cp->kcq1.dma.pgtbl_map >> 32);
  3936. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_HADDR_HI, val);
  3937. val = (u32) cp->kcq1.dma.pgtbl_map;
  3938. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_HADDR_LO, val);
  3939. cp->int_num = 0;
  3940. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3941. struct status_block_msix *msblk = cp->status_blk.bnx2;
  3942. u32 sb_id = cp->status_blk_num;
  3943. u32 sb = BNX2_L2CTX_L5_STATUSB_NUM(sb_id);
  3944. cp->kcq1.hw_prod_idx_ptr =
  3945. &msblk->status_completion_producer_index;
  3946. cp->kcq1.status_idx_ptr = &msblk->status_idx;
  3947. cp->kwq_con_idx_ptr = &msblk->status_cmd_consumer_index;
  3948. cp->int_num = sb_id << BNX2_PCICFG_INT_ACK_CMD_INT_NUM_SHIFT;
  3949. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_HOST_QIDX, sb);
  3950. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_HOST_QIDX, sb);
  3951. }
  3952. /* Enable Commnad Scheduler notification when we write to the
  3953. * host producer index of the kernel contexts. */
  3954. CNIC_WR(dev, BNX2_MQ_KNL_CMD_MASK1, 2);
  3955. /* Enable Command Scheduler notification when we write to either
  3956. * the Send Queue or Receive Queue producer indexes of the kernel
  3957. * bypass contexts. */
  3958. CNIC_WR(dev, BNX2_MQ_KNL_BYP_CMD_MASK1, 7);
  3959. CNIC_WR(dev, BNX2_MQ_KNL_BYP_WRITE_MASK1, 7);
  3960. /* Notify COM when the driver post an application buffer. */
  3961. CNIC_WR(dev, BNX2_MQ_KNL_RX_V2P_MASK2, 0x2000);
  3962. /* Set the CP and COM doorbells. These two processors polls the
  3963. * doorbell for a non zero value before running. This must be done
  3964. * after setting up the kernel queue contexts. */
  3965. cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 1);
  3966. cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 1);
  3967. cnic_init_bnx2_tx_ring(dev);
  3968. cnic_init_bnx2_rx_ring(dev);
  3969. err = cnic_init_bnx2_irq(dev);
  3970. if (err) {
  3971. netdev_err(dev->netdev, "cnic_init_irq failed\n");
  3972. cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 0);
  3973. cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 0);
  3974. return err;
  3975. }
  3976. ethdev->drv_state |= CNIC_DRV_STATE_HANDLES_IRQ;
  3977. return 0;
  3978. }
  3979. static void cnic_setup_bnx2x_context(struct cnic_dev *dev)
  3980. {
  3981. struct cnic_local *cp = dev->cnic_priv;
  3982. struct cnic_eth_dev *ethdev = cp->ethdev;
  3983. u32 start_offset = ethdev->ctx_tbl_offset;
  3984. int i;
  3985. for (i = 0; i < cp->ctx_blks; i++) {
  3986. struct cnic_ctx *ctx = &cp->ctx_arr[i];
  3987. dma_addr_t map = ctx->mapping;
  3988. if (cp->ctx_align) {
  3989. unsigned long mask = cp->ctx_align - 1;
  3990. map = (map + mask) & ~mask;
  3991. }
  3992. cnic_ctx_tbl_wr(dev, start_offset + i, map);
  3993. }
  3994. }
  3995. static int cnic_init_bnx2x_irq(struct cnic_dev *dev)
  3996. {
  3997. struct cnic_local *cp = dev->cnic_priv;
  3998. struct cnic_eth_dev *ethdev = cp->ethdev;
  3999. int err = 0;
  4000. tasklet_init(&cp->cnic_irq_task, cnic_service_bnx2x_bh,
  4001. (unsigned long) dev);
  4002. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX)
  4003. err = cnic_request_irq(dev);
  4004. return err;
  4005. }
  4006. static inline void cnic_storm_memset_hc_disable(struct cnic_dev *dev,
  4007. u16 sb_id, u8 sb_index,
  4008. u8 disable)
  4009. {
  4010. struct bnx2x *bp = netdev_priv(dev->netdev);
  4011. u32 addr = BAR_CSTRORM_INTMEM +
  4012. CSTORM_STATUS_BLOCK_DATA_OFFSET(sb_id) +
  4013. offsetof(struct hc_status_block_data_e1x, index_data) +
  4014. sizeof(struct hc_index_data)*sb_index +
  4015. offsetof(struct hc_index_data, flags);
  4016. u16 flags = CNIC_RD16(dev, addr);
  4017. /* clear and set */
  4018. flags &= ~HC_INDEX_DATA_HC_ENABLED;
  4019. flags |= (((~disable) << HC_INDEX_DATA_HC_ENABLED_SHIFT) &
  4020. HC_INDEX_DATA_HC_ENABLED);
  4021. CNIC_WR16(dev, addr, flags);
  4022. }
  4023. static void cnic_enable_bnx2x_int(struct cnic_dev *dev)
  4024. {
  4025. struct cnic_local *cp = dev->cnic_priv;
  4026. struct bnx2x *bp = netdev_priv(dev->netdev);
  4027. u8 sb_id = cp->status_blk_num;
  4028. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  4029. CSTORM_STATUS_BLOCK_DATA_OFFSET(sb_id) +
  4030. offsetof(struct hc_status_block_data_e1x, index_data) +
  4031. sizeof(struct hc_index_data)*HC_INDEX_ISCSI_EQ_CONS +
  4032. offsetof(struct hc_index_data, timeout), 64 / 4);
  4033. cnic_storm_memset_hc_disable(dev, sb_id, HC_INDEX_ISCSI_EQ_CONS, 0);
  4034. }
  4035. static void cnic_disable_bnx2x_int_sync(struct cnic_dev *dev)
  4036. {
  4037. }
  4038. static void cnic_init_bnx2x_tx_ring(struct cnic_dev *dev,
  4039. struct client_init_ramrod_data *data)
  4040. {
  4041. struct cnic_local *cp = dev->cnic_priv;
  4042. struct cnic_uio_dev *udev = cp->udev;
  4043. union eth_tx_bd_types *txbd = (union eth_tx_bd_types *) udev->l2_ring;
  4044. dma_addr_t buf_map, ring_map = udev->l2_ring_map;
  4045. struct host_sp_status_block *sb = cp->bnx2x_def_status_blk;
  4046. int i;
  4047. u32 cli = cp->ethdev->iscsi_l2_client_id;
  4048. u32 val;
  4049. memset(txbd, 0, BNX2_PAGE_SIZE);
  4050. buf_map = udev->l2_buf_map;
  4051. for (i = 0; i < BNX2_MAX_TX_DESC_CNT; i += 3, txbd += 3) {
  4052. struct eth_tx_start_bd *start_bd = &txbd->start_bd;
  4053. struct eth_tx_parse_bd_e1x *pbd_e1x =
  4054. &((txbd + 1)->parse_bd_e1x);
  4055. struct eth_tx_parse_bd_e2 *pbd_e2 = &((txbd + 1)->parse_bd_e2);
  4056. struct eth_tx_bd *reg_bd = &((txbd + 2)->reg_bd);
  4057. start_bd->addr_hi = cpu_to_le32((u64) buf_map >> 32);
  4058. start_bd->addr_lo = cpu_to_le32(buf_map & 0xffffffff);
  4059. reg_bd->addr_hi = start_bd->addr_hi;
  4060. reg_bd->addr_lo = start_bd->addr_lo + 0x10;
  4061. start_bd->nbytes = cpu_to_le16(0x10);
  4062. start_bd->nbd = cpu_to_le16(3);
  4063. start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
  4064. start_bd->general_data &= ~ETH_TX_START_BD_PARSE_NBDS;
  4065. start_bd->general_data |= (1 << ETH_TX_START_BD_HDR_NBDS_SHIFT);
  4066. if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id))
  4067. pbd_e2->parsing_data = (UNICAST_ADDRESS <<
  4068. ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE_SHIFT);
  4069. else
  4070. pbd_e1x->global_data = (UNICAST_ADDRESS <<
  4071. ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE_SHIFT);
  4072. }
  4073. val = (u64) ring_map >> 32;
  4074. txbd->next_bd.addr_hi = cpu_to_le32(val);
  4075. data->tx.tx_bd_page_base.hi = cpu_to_le32(val);
  4076. val = (u64) ring_map & 0xffffffff;
  4077. txbd->next_bd.addr_lo = cpu_to_le32(val);
  4078. data->tx.tx_bd_page_base.lo = cpu_to_le32(val);
  4079. /* Other ramrod params */
  4080. data->tx.tx_sb_index_number = HC_SP_INDEX_ETH_ISCSI_CQ_CONS;
  4081. data->tx.tx_status_block_id = BNX2X_DEF_SB_ID;
  4082. /* reset xstorm per client statistics */
  4083. if (cli < MAX_STAT_COUNTER_ID) {
  4084. data->general.statistics_zero_flg = 1;
  4085. data->general.statistics_en_flg = 1;
  4086. data->general.statistics_counter_id = cli;
  4087. }
  4088. cp->tx_cons_ptr =
  4089. &sb->sp_sb.index_values[HC_SP_INDEX_ETH_ISCSI_CQ_CONS];
  4090. }
  4091. static void cnic_init_bnx2x_rx_ring(struct cnic_dev *dev,
  4092. struct client_init_ramrod_data *data)
  4093. {
  4094. struct cnic_local *cp = dev->cnic_priv;
  4095. struct cnic_uio_dev *udev = cp->udev;
  4096. struct eth_rx_bd *rxbd = (struct eth_rx_bd *) (udev->l2_ring +
  4097. BNX2_PAGE_SIZE);
  4098. struct eth_rx_cqe_next_page *rxcqe = (struct eth_rx_cqe_next_page *)
  4099. (udev->l2_ring + (2 * BNX2_PAGE_SIZE));
  4100. struct host_sp_status_block *sb = cp->bnx2x_def_status_blk;
  4101. int i;
  4102. u32 cli = cp->ethdev->iscsi_l2_client_id;
  4103. int cl_qzone_id = BNX2X_CL_QZONE_ID(cp, cli);
  4104. u32 val;
  4105. dma_addr_t ring_map = udev->l2_ring_map;
  4106. /* General data */
  4107. data->general.client_id = cli;
  4108. data->general.activate_flg = 1;
  4109. data->general.sp_client_id = cli;
  4110. data->general.mtu = cpu_to_le16(cp->l2_single_buf_size - 14);
  4111. data->general.func_id = cp->pfid;
  4112. for (i = 0; i < BNX2X_MAX_RX_DESC_CNT; i++, rxbd++) {
  4113. dma_addr_t buf_map;
  4114. int n = (i % cp->l2_rx_ring_size) + 1;
  4115. buf_map = udev->l2_buf_map + (n * cp->l2_single_buf_size);
  4116. rxbd->addr_hi = cpu_to_le32((u64) buf_map >> 32);
  4117. rxbd->addr_lo = cpu_to_le32(buf_map & 0xffffffff);
  4118. }
  4119. val = (u64) (ring_map + BNX2_PAGE_SIZE) >> 32;
  4120. rxbd->addr_hi = cpu_to_le32(val);
  4121. data->rx.bd_page_base.hi = cpu_to_le32(val);
  4122. val = (u64) (ring_map + BNX2_PAGE_SIZE) & 0xffffffff;
  4123. rxbd->addr_lo = cpu_to_le32(val);
  4124. data->rx.bd_page_base.lo = cpu_to_le32(val);
  4125. rxcqe += BNX2X_MAX_RCQ_DESC_CNT;
  4126. val = (u64) (ring_map + (2 * BNX2_PAGE_SIZE)) >> 32;
  4127. rxcqe->addr_hi = cpu_to_le32(val);
  4128. data->rx.cqe_page_base.hi = cpu_to_le32(val);
  4129. val = (u64) (ring_map + (2 * BNX2_PAGE_SIZE)) & 0xffffffff;
  4130. rxcqe->addr_lo = cpu_to_le32(val);
  4131. data->rx.cqe_page_base.lo = cpu_to_le32(val);
  4132. /* Other ramrod params */
  4133. data->rx.client_qzone_id = cl_qzone_id;
  4134. data->rx.rx_sb_index_number = HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS;
  4135. data->rx.status_block_id = BNX2X_DEF_SB_ID;
  4136. data->rx.cache_line_alignment_log_size = L1_CACHE_SHIFT;
  4137. data->rx.max_bytes_on_bd = cpu_to_le16(cp->l2_single_buf_size);
  4138. data->rx.outer_vlan_removal_enable_flg = 1;
  4139. data->rx.silent_vlan_removal_flg = 1;
  4140. data->rx.silent_vlan_value = 0;
  4141. data->rx.silent_vlan_mask = 0xffff;
  4142. cp->rx_cons_ptr =
  4143. &sb->sp_sb.index_values[HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS];
  4144. cp->rx_cons = *cp->rx_cons_ptr;
  4145. }
  4146. static void cnic_init_bnx2x_kcq(struct cnic_dev *dev)
  4147. {
  4148. struct cnic_local *cp = dev->cnic_priv;
  4149. struct bnx2x *bp = netdev_priv(dev->netdev);
  4150. u32 pfid = cp->pfid;
  4151. cp->kcq1.io_addr = BAR_CSTRORM_INTMEM +
  4152. CSTORM_ISCSI_EQ_PROD_OFFSET(pfid, 0);
  4153. cp->kcq1.sw_prod_idx = 0;
  4154. if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id)) {
  4155. struct host_hc_status_block_e2 *sb = cp->status_blk.gen;
  4156. cp->kcq1.hw_prod_idx_ptr =
  4157. &sb->sb.index_values[HC_INDEX_ISCSI_EQ_CONS];
  4158. cp->kcq1.status_idx_ptr =
  4159. &sb->sb.running_index[SM_RX_ID];
  4160. } else {
  4161. struct host_hc_status_block_e1x *sb = cp->status_blk.gen;
  4162. cp->kcq1.hw_prod_idx_ptr =
  4163. &sb->sb.index_values[HC_INDEX_ISCSI_EQ_CONS];
  4164. cp->kcq1.status_idx_ptr =
  4165. &sb->sb.running_index[SM_RX_ID];
  4166. }
  4167. if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id)) {
  4168. struct host_hc_status_block_e2 *sb = cp->status_blk.gen;
  4169. cp->kcq2.io_addr = BAR_USTRORM_INTMEM +
  4170. USTORM_FCOE_EQ_PROD_OFFSET(pfid);
  4171. cp->kcq2.sw_prod_idx = 0;
  4172. cp->kcq2.hw_prod_idx_ptr =
  4173. &sb->sb.index_values[HC_INDEX_FCOE_EQ_CONS];
  4174. cp->kcq2.status_idx_ptr =
  4175. &sb->sb.running_index[SM_RX_ID];
  4176. }
  4177. }
  4178. static int cnic_start_bnx2x_hw(struct cnic_dev *dev)
  4179. {
  4180. struct cnic_local *cp = dev->cnic_priv;
  4181. struct bnx2x *bp = netdev_priv(dev->netdev);
  4182. struct cnic_eth_dev *ethdev = cp->ethdev;
  4183. int func, ret;
  4184. u32 pfid;
  4185. dev->stats_addr = ethdev->addr_drv_info_to_mcp;
  4186. cp->port_mode = bp->common.chip_port_mode;
  4187. cp->pfid = bp->pfid;
  4188. cp->func = bp->pf_num;
  4189. func = CNIC_FUNC(cp);
  4190. pfid = cp->pfid;
  4191. ret = cnic_init_id_tbl(&cp->cid_tbl, MAX_ISCSI_TBL_SZ,
  4192. cp->iscsi_start_cid, 0);
  4193. if (ret)
  4194. return -ENOMEM;
  4195. if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id)) {
  4196. ret = cnic_init_id_tbl(&cp->fcoe_cid_tbl, dev->max_fcoe_conn,
  4197. cp->fcoe_start_cid, 0);
  4198. if (ret)
  4199. return -ENOMEM;
  4200. }
  4201. cp->bnx2x_igu_sb_id = ethdev->irq_arr[0].status_blk_num2;
  4202. cnic_init_bnx2x_kcq(dev);
  4203. /* Only 1 EQ */
  4204. CNIC_WR16(dev, cp->kcq1.io_addr, MAX_KCQ_IDX);
  4205. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4206. CSTORM_ISCSI_EQ_CONS_OFFSET(pfid, 0), 0);
  4207. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4208. CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfid, 0),
  4209. cp->kcq1.dma.pg_map_arr[1] & 0xffffffff);
  4210. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4211. CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfid, 0) + 4,
  4212. (u64) cp->kcq1.dma.pg_map_arr[1] >> 32);
  4213. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4214. CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfid, 0),
  4215. cp->kcq1.dma.pg_map_arr[0] & 0xffffffff);
  4216. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4217. CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfid, 0) + 4,
  4218. (u64) cp->kcq1.dma.pg_map_arr[0] >> 32);
  4219. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  4220. CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_VALID_OFFSET(pfid, 0), 1);
  4221. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  4222. CSTORM_ISCSI_EQ_SB_NUM_OFFSET(pfid, 0), cp->status_blk_num);
  4223. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  4224. CSTORM_ISCSI_EQ_SB_INDEX_OFFSET(pfid, 0),
  4225. HC_INDEX_ISCSI_EQ_CONS);
  4226. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  4227. USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfid),
  4228. cp->gbl_buf_info.pg_map_arr[0] & 0xffffffff);
  4229. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  4230. USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfid) + 4,
  4231. (u64) cp->gbl_buf_info.pg_map_arr[0] >> 32);
  4232. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  4233. TSTORM_ISCSI_TCP_LOCAL_ADV_WND_OFFSET(pfid), DEF_RCV_BUF);
  4234. cnic_setup_bnx2x_context(dev);
  4235. ret = cnic_init_bnx2x_irq(dev);
  4236. if (ret)
  4237. return ret;
  4238. ethdev->drv_state |= CNIC_DRV_STATE_HANDLES_IRQ;
  4239. return 0;
  4240. }
  4241. static void cnic_init_rings(struct cnic_dev *dev)
  4242. {
  4243. struct cnic_local *cp = dev->cnic_priv;
  4244. struct bnx2x *bp = netdev_priv(dev->netdev);
  4245. struct cnic_uio_dev *udev = cp->udev;
  4246. if (test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
  4247. return;
  4248. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
  4249. cnic_init_bnx2_tx_ring(dev);
  4250. cnic_init_bnx2_rx_ring(dev);
  4251. set_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
  4252. } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
  4253. u32 cli = cp->ethdev->iscsi_l2_client_id;
  4254. u32 cid = cp->ethdev->iscsi_l2_cid;
  4255. u32 cl_qzone_id;
  4256. struct client_init_ramrod_data *data;
  4257. union l5cm_specific_data l5_data;
  4258. struct ustorm_eth_rx_producers rx_prods = {0};
  4259. u32 off, i, *cid_ptr;
  4260. rx_prods.bd_prod = 0;
  4261. rx_prods.cqe_prod = BNX2X_MAX_RCQ_DESC_CNT;
  4262. barrier();
  4263. cl_qzone_id = BNX2X_CL_QZONE_ID(cp, cli);
  4264. off = BAR_USTRORM_INTMEM +
  4265. (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id) ?
  4266. USTORM_RX_PRODS_E2_OFFSET(cl_qzone_id) :
  4267. USTORM_RX_PRODS_E1X_OFFSET(CNIC_PORT(cp), cli));
  4268. for (i = 0; i < sizeof(struct ustorm_eth_rx_producers) / 4; i++)
  4269. CNIC_WR(dev, off + i * 4, ((u32 *) &rx_prods)[i]);
  4270. set_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
  4271. data = udev->l2_buf;
  4272. cid_ptr = udev->l2_buf + 12;
  4273. memset(data, 0, sizeof(*data));
  4274. cnic_init_bnx2x_tx_ring(dev, data);
  4275. cnic_init_bnx2x_rx_ring(dev, data);
  4276. l5_data.phy_address.lo = udev->l2_buf_map & 0xffffffff;
  4277. l5_data.phy_address.hi = (u64) udev->l2_buf_map >> 32;
  4278. set_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
  4279. cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_CLIENT_SETUP,
  4280. cid, ETH_CONNECTION_TYPE, &l5_data);
  4281. i = 0;
  4282. while (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags) &&
  4283. ++i < 10)
  4284. msleep(1);
  4285. if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
  4286. netdev_err(dev->netdev,
  4287. "iSCSI CLIENT_SETUP did not complete\n");
  4288. cnic_spq_completion(dev, DRV_CTL_RET_L2_SPQ_CREDIT_CMD, 1);
  4289. cnic_ring_ctl(dev, cid, cli, 1);
  4290. *cid_ptr = cid;
  4291. }
  4292. }
  4293. static void cnic_shutdown_rings(struct cnic_dev *dev)
  4294. {
  4295. struct cnic_local *cp = dev->cnic_priv;
  4296. struct cnic_uio_dev *udev = cp->udev;
  4297. void *rx_ring;
  4298. if (!test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
  4299. return;
  4300. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
  4301. cnic_shutdown_bnx2_rx_ring(dev);
  4302. } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
  4303. u32 cli = cp->ethdev->iscsi_l2_client_id;
  4304. u32 cid = cp->ethdev->iscsi_l2_cid;
  4305. union l5cm_specific_data l5_data;
  4306. int i;
  4307. cnic_ring_ctl(dev, cid, cli, 0);
  4308. set_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
  4309. l5_data.phy_address.lo = cli;
  4310. l5_data.phy_address.hi = 0;
  4311. cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_HALT,
  4312. cid, ETH_CONNECTION_TYPE, &l5_data);
  4313. i = 0;
  4314. while (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags) &&
  4315. ++i < 10)
  4316. msleep(1);
  4317. if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
  4318. netdev_err(dev->netdev,
  4319. "iSCSI CLIENT_HALT did not complete\n");
  4320. cnic_spq_completion(dev, DRV_CTL_RET_L2_SPQ_CREDIT_CMD, 1);
  4321. memset(&l5_data, 0, sizeof(l5_data));
  4322. cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_COMMON_CFC_DEL,
  4323. cid, NONE_CONNECTION_TYPE, &l5_data);
  4324. msleep(10);
  4325. }
  4326. clear_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
  4327. rx_ring = udev->l2_ring + BNX2_PAGE_SIZE;
  4328. memset(rx_ring, 0, BNX2_PAGE_SIZE);
  4329. }
  4330. static int cnic_register_netdev(struct cnic_dev *dev)
  4331. {
  4332. struct cnic_local *cp = dev->cnic_priv;
  4333. struct cnic_eth_dev *ethdev = cp->ethdev;
  4334. int err;
  4335. if (!ethdev)
  4336. return -ENODEV;
  4337. if (ethdev->drv_state & CNIC_DRV_STATE_REGD)
  4338. return 0;
  4339. err = ethdev->drv_register_cnic(dev->netdev, cp->cnic_ops, dev);
  4340. if (err)
  4341. netdev_err(dev->netdev, "register_cnic failed\n");
  4342. /* Read iSCSI config again. On some bnx2x device, iSCSI config
  4343. * can change after firmware is downloaded.
  4344. */
  4345. dev->max_iscsi_conn = ethdev->max_iscsi_conn;
  4346. if (ethdev->drv_state & CNIC_DRV_STATE_NO_ISCSI)
  4347. dev->max_iscsi_conn = 0;
  4348. return err;
  4349. }
  4350. static void cnic_unregister_netdev(struct cnic_dev *dev)
  4351. {
  4352. struct cnic_local *cp = dev->cnic_priv;
  4353. struct cnic_eth_dev *ethdev = cp->ethdev;
  4354. if (!ethdev)
  4355. return;
  4356. ethdev->drv_unregister_cnic(dev->netdev);
  4357. }
  4358. static int cnic_start_hw(struct cnic_dev *dev)
  4359. {
  4360. struct cnic_local *cp = dev->cnic_priv;
  4361. struct cnic_eth_dev *ethdev = cp->ethdev;
  4362. int err;
  4363. if (test_bit(CNIC_F_CNIC_UP, &dev->flags))
  4364. return -EALREADY;
  4365. dev->regview = ethdev->io_base;
  4366. pci_dev_get(dev->pcidev);
  4367. cp->func = PCI_FUNC(dev->pcidev->devfn);
  4368. cp->status_blk.gen = ethdev->irq_arr[0].status_blk;
  4369. cp->status_blk_num = ethdev->irq_arr[0].status_blk_num;
  4370. err = cp->alloc_resc(dev);
  4371. if (err) {
  4372. netdev_err(dev->netdev, "allocate resource failure\n");
  4373. goto err1;
  4374. }
  4375. err = cp->start_hw(dev);
  4376. if (err)
  4377. goto err1;
  4378. err = cnic_cm_open(dev);
  4379. if (err)
  4380. goto err1;
  4381. set_bit(CNIC_F_CNIC_UP, &dev->flags);
  4382. cp->enable_int(dev);
  4383. return 0;
  4384. err1:
  4385. cp->free_resc(dev);
  4386. pci_dev_put(dev->pcidev);
  4387. return err;
  4388. }
  4389. static void cnic_stop_bnx2_hw(struct cnic_dev *dev)
  4390. {
  4391. cnic_disable_bnx2_int_sync(dev);
  4392. cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 0);
  4393. cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 0);
  4394. cnic_init_context(dev, KWQ_CID);
  4395. cnic_init_context(dev, KCQ_CID);
  4396. cnic_setup_5709_context(dev, 0);
  4397. cnic_free_irq(dev);
  4398. cnic_free_resc(dev);
  4399. }
  4400. static void cnic_stop_bnx2x_hw(struct cnic_dev *dev)
  4401. {
  4402. struct cnic_local *cp = dev->cnic_priv;
  4403. struct bnx2x *bp = netdev_priv(dev->netdev);
  4404. u32 hc_index = HC_INDEX_ISCSI_EQ_CONS;
  4405. u32 sb_id = cp->status_blk_num;
  4406. u32 idx_off, syn_off;
  4407. cnic_free_irq(dev);
  4408. if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id)) {
  4409. idx_off = offsetof(struct hc_status_block_e2, index_values) +
  4410. (hc_index * sizeof(u16));
  4411. syn_off = CSTORM_HC_SYNC_LINE_INDEX_E2_OFFSET(hc_index, sb_id);
  4412. } else {
  4413. idx_off = offsetof(struct hc_status_block_e1x, index_values) +
  4414. (hc_index * sizeof(u16));
  4415. syn_off = CSTORM_HC_SYNC_LINE_INDEX_E1X_OFFSET(hc_index, sb_id);
  4416. }
  4417. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + syn_off, 0);
  4418. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_STATUS_BLOCK_OFFSET(sb_id) +
  4419. idx_off, 0);
  4420. *cp->kcq1.hw_prod_idx_ptr = 0;
  4421. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4422. CSTORM_ISCSI_EQ_CONS_OFFSET(cp->pfid, 0), 0);
  4423. CNIC_WR16(dev, cp->kcq1.io_addr, 0);
  4424. cnic_free_resc(dev);
  4425. }
  4426. static void cnic_stop_hw(struct cnic_dev *dev)
  4427. {
  4428. if (test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
  4429. struct cnic_local *cp = dev->cnic_priv;
  4430. int i = 0;
  4431. /* Need to wait for the ring shutdown event to complete
  4432. * before clearing the CNIC_UP flag.
  4433. */
  4434. while (cp->udev && cp->udev->uio_dev != -1 && i < 15) {
  4435. msleep(100);
  4436. i++;
  4437. }
  4438. cnic_shutdown_rings(dev);
  4439. cp->stop_cm(dev);
  4440. cp->ethdev->drv_state &= ~CNIC_DRV_STATE_HANDLES_IRQ;
  4441. clear_bit(CNIC_F_CNIC_UP, &dev->flags);
  4442. RCU_INIT_POINTER(cp->ulp_ops[CNIC_ULP_L4], NULL);
  4443. synchronize_rcu();
  4444. cnic_cm_shutdown(dev);
  4445. cp->stop_hw(dev);
  4446. pci_dev_put(dev->pcidev);
  4447. }
  4448. }
  4449. static void cnic_free_dev(struct cnic_dev *dev)
  4450. {
  4451. int i = 0;
  4452. while ((atomic_read(&dev->ref_count) != 0) && i < 10) {
  4453. msleep(100);
  4454. i++;
  4455. }
  4456. if (atomic_read(&dev->ref_count) != 0)
  4457. netdev_err(dev->netdev, "Failed waiting for ref count to go to zero\n");
  4458. netdev_info(dev->netdev, "Removed CNIC device\n");
  4459. dev_put(dev->netdev);
  4460. kfree(dev);
  4461. }
  4462. static struct cnic_dev *cnic_alloc_dev(struct net_device *dev,
  4463. struct pci_dev *pdev)
  4464. {
  4465. struct cnic_dev *cdev;
  4466. struct cnic_local *cp;
  4467. int alloc_size;
  4468. alloc_size = sizeof(struct cnic_dev) + sizeof(struct cnic_local);
  4469. cdev = kzalloc(alloc_size, GFP_KERNEL);
  4470. if (cdev == NULL)
  4471. return NULL;
  4472. cdev->netdev = dev;
  4473. cdev->cnic_priv = (char *)cdev + sizeof(struct cnic_dev);
  4474. cdev->register_device = cnic_register_device;
  4475. cdev->unregister_device = cnic_unregister_device;
  4476. cdev->iscsi_nl_msg_recv = cnic_iscsi_nl_msg_recv;
  4477. cp = cdev->cnic_priv;
  4478. cp->dev = cdev;
  4479. cp->l2_single_buf_size = 0x400;
  4480. cp->l2_rx_ring_size = 3;
  4481. spin_lock_init(&cp->cnic_ulp_lock);
  4482. netdev_info(dev, "Added CNIC device\n");
  4483. return cdev;
  4484. }
  4485. static struct cnic_dev *init_bnx2_cnic(struct net_device *dev)
  4486. {
  4487. struct pci_dev *pdev;
  4488. struct cnic_dev *cdev;
  4489. struct cnic_local *cp;
  4490. struct bnx2 *bp = netdev_priv(dev);
  4491. struct cnic_eth_dev *ethdev = NULL;
  4492. if (bp->cnic_probe)
  4493. ethdev = (bp->cnic_probe)(dev);
  4494. if (!ethdev)
  4495. return NULL;
  4496. pdev = ethdev->pdev;
  4497. if (!pdev)
  4498. return NULL;
  4499. dev_hold(dev);
  4500. pci_dev_get(pdev);
  4501. if ((pdev->device == PCI_DEVICE_ID_NX2_5709 ||
  4502. pdev->device == PCI_DEVICE_ID_NX2_5709S) &&
  4503. (pdev->revision < 0x10)) {
  4504. pci_dev_put(pdev);
  4505. goto cnic_err;
  4506. }
  4507. pci_dev_put(pdev);
  4508. cdev = cnic_alloc_dev(dev, pdev);
  4509. if (cdev == NULL)
  4510. goto cnic_err;
  4511. set_bit(CNIC_F_BNX2_CLASS, &cdev->flags);
  4512. cdev->submit_kwqes = cnic_submit_bnx2_kwqes;
  4513. cp = cdev->cnic_priv;
  4514. cp->ethdev = ethdev;
  4515. cdev->pcidev = pdev;
  4516. cp->chip_id = ethdev->chip_id;
  4517. cdev->max_iscsi_conn = ethdev->max_iscsi_conn;
  4518. cp->cnic_ops = &cnic_bnx2_ops;
  4519. cp->start_hw = cnic_start_bnx2_hw;
  4520. cp->stop_hw = cnic_stop_bnx2_hw;
  4521. cp->setup_pgtbl = cnic_setup_page_tbl;
  4522. cp->alloc_resc = cnic_alloc_bnx2_resc;
  4523. cp->free_resc = cnic_free_resc;
  4524. cp->start_cm = cnic_cm_init_bnx2_hw;
  4525. cp->stop_cm = cnic_cm_stop_bnx2_hw;
  4526. cp->enable_int = cnic_enable_bnx2_int;
  4527. cp->disable_int_sync = cnic_disable_bnx2_int_sync;
  4528. cp->close_conn = cnic_close_bnx2_conn;
  4529. return cdev;
  4530. cnic_err:
  4531. dev_put(dev);
  4532. return NULL;
  4533. }
  4534. static struct cnic_dev *init_bnx2x_cnic(struct net_device *dev)
  4535. {
  4536. struct pci_dev *pdev;
  4537. struct cnic_dev *cdev;
  4538. struct cnic_local *cp;
  4539. struct bnx2x *bp = netdev_priv(dev);
  4540. struct cnic_eth_dev *ethdev = NULL;
  4541. if (bp->cnic_probe)
  4542. ethdev = bp->cnic_probe(dev);
  4543. if (!ethdev)
  4544. return NULL;
  4545. pdev = ethdev->pdev;
  4546. if (!pdev)
  4547. return NULL;
  4548. dev_hold(dev);
  4549. cdev = cnic_alloc_dev(dev, pdev);
  4550. if (cdev == NULL) {
  4551. dev_put(dev);
  4552. return NULL;
  4553. }
  4554. set_bit(CNIC_F_BNX2X_CLASS, &cdev->flags);
  4555. cdev->submit_kwqes = cnic_submit_bnx2x_kwqes;
  4556. cp = cdev->cnic_priv;
  4557. cp->ethdev = ethdev;
  4558. cdev->pcidev = pdev;
  4559. cp->chip_id = ethdev->chip_id;
  4560. cdev->stats_addr = ethdev->addr_drv_info_to_mcp;
  4561. if (!(ethdev->drv_state & CNIC_DRV_STATE_NO_ISCSI))
  4562. cdev->max_iscsi_conn = ethdev->max_iscsi_conn;
  4563. if (CNIC_SUPPORTS_FCOE(cp)) {
  4564. cdev->max_fcoe_conn = ethdev->max_fcoe_conn;
  4565. cdev->max_fcoe_exchanges = ethdev->max_fcoe_exchanges;
  4566. }
  4567. if (cdev->max_fcoe_conn > BNX2X_FCOE_NUM_CONNECTIONS)
  4568. cdev->max_fcoe_conn = BNX2X_FCOE_NUM_CONNECTIONS;
  4569. memcpy(cdev->mac_addr, ethdev->iscsi_mac, 6);
  4570. cp->cnic_ops = &cnic_bnx2x_ops;
  4571. cp->start_hw = cnic_start_bnx2x_hw;
  4572. cp->stop_hw = cnic_stop_bnx2x_hw;
  4573. cp->setup_pgtbl = cnic_setup_page_tbl_le;
  4574. cp->alloc_resc = cnic_alloc_bnx2x_resc;
  4575. cp->free_resc = cnic_free_resc;
  4576. cp->start_cm = cnic_cm_init_bnx2x_hw;
  4577. cp->stop_cm = cnic_cm_stop_bnx2x_hw;
  4578. cp->enable_int = cnic_enable_bnx2x_int;
  4579. cp->disable_int_sync = cnic_disable_bnx2x_int_sync;
  4580. if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id)) {
  4581. cp->ack_int = cnic_ack_bnx2x_e2_msix;
  4582. cp->arm_int = cnic_arm_bnx2x_e2_msix;
  4583. } else {
  4584. cp->ack_int = cnic_ack_bnx2x_msix;
  4585. cp->arm_int = cnic_arm_bnx2x_msix;
  4586. }
  4587. cp->close_conn = cnic_close_bnx2x_conn;
  4588. return cdev;
  4589. }
  4590. static struct cnic_dev *is_cnic_dev(struct net_device *dev)
  4591. {
  4592. struct ethtool_drvinfo drvinfo;
  4593. struct cnic_dev *cdev = NULL;
  4594. if (dev->ethtool_ops && dev->ethtool_ops->get_drvinfo) {
  4595. memset(&drvinfo, 0, sizeof(drvinfo));
  4596. dev->ethtool_ops->get_drvinfo(dev, &drvinfo);
  4597. if (!strcmp(drvinfo.driver, "bnx2"))
  4598. cdev = init_bnx2_cnic(dev);
  4599. if (!strcmp(drvinfo.driver, "bnx2x"))
  4600. cdev = init_bnx2x_cnic(dev);
  4601. if (cdev) {
  4602. write_lock(&cnic_dev_lock);
  4603. list_add(&cdev->list, &cnic_dev_list);
  4604. write_unlock(&cnic_dev_lock);
  4605. }
  4606. }
  4607. return cdev;
  4608. }
  4609. static void cnic_rcv_netevent(struct cnic_local *cp, unsigned long event,
  4610. u16 vlan_id)
  4611. {
  4612. int if_type;
  4613. rcu_read_lock();
  4614. for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
  4615. struct cnic_ulp_ops *ulp_ops;
  4616. void *ctx;
  4617. ulp_ops = rcu_dereference(cp->ulp_ops[if_type]);
  4618. if (!ulp_ops || !ulp_ops->indicate_netevent)
  4619. continue;
  4620. ctx = cp->ulp_handle[if_type];
  4621. ulp_ops->indicate_netevent(ctx, event, vlan_id);
  4622. }
  4623. rcu_read_unlock();
  4624. }
  4625. /* netdev event handler */
  4626. static int cnic_netdev_event(struct notifier_block *this, unsigned long event,
  4627. void *ptr)
  4628. {
  4629. struct net_device *netdev = netdev_notifier_info_to_dev(ptr);
  4630. struct cnic_dev *dev;
  4631. int new_dev = 0;
  4632. dev = cnic_from_netdev(netdev);
  4633. if (!dev && event == NETDEV_REGISTER) {
  4634. /* Check for the hot-plug device */
  4635. dev = is_cnic_dev(netdev);
  4636. if (dev) {
  4637. new_dev = 1;
  4638. cnic_hold(dev);
  4639. }
  4640. }
  4641. if (dev) {
  4642. struct cnic_local *cp = dev->cnic_priv;
  4643. if (new_dev)
  4644. cnic_ulp_init(dev);
  4645. else if (event == NETDEV_UNREGISTER)
  4646. cnic_ulp_exit(dev);
  4647. if (event == NETDEV_UP) {
  4648. if (cnic_register_netdev(dev) != 0) {
  4649. cnic_put(dev);
  4650. goto done;
  4651. }
  4652. if (!cnic_start_hw(dev))
  4653. cnic_ulp_start(dev);
  4654. }
  4655. cnic_rcv_netevent(cp, event, 0);
  4656. if (event == NETDEV_GOING_DOWN) {
  4657. cnic_ulp_stop(dev);
  4658. cnic_stop_hw(dev);
  4659. cnic_unregister_netdev(dev);
  4660. } else if (event == NETDEV_UNREGISTER) {
  4661. write_lock(&cnic_dev_lock);
  4662. list_del_init(&dev->list);
  4663. write_unlock(&cnic_dev_lock);
  4664. cnic_put(dev);
  4665. cnic_free_dev(dev);
  4666. goto done;
  4667. }
  4668. cnic_put(dev);
  4669. } else {
  4670. struct net_device *realdev;
  4671. u16 vid;
  4672. vid = cnic_get_vlan(netdev, &realdev);
  4673. if (realdev) {
  4674. dev = cnic_from_netdev(realdev);
  4675. if (dev) {
  4676. vid |= VLAN_TAG_PRESENT;
  4677. cnic_rcv_netevent(dev->cnic_priv, event, vid);
  4678. cnic_put(dev);
  4679. }
  4680. }
  4681. }
  4682. done:
  4683. return NOTIFY_DONE;
  4684. }
  4685. static struct notifier_block cnic_netdev_notifier = {
  4686. .notifier_call = cnic_netdev_event
  4687. };
  4688. static void cnic_release(void)
  4689. {
  4690. struct cnic_uio_dev *udev;
  4691. while (!list_empty(&cnic_udev_list)) {
  4692. udev = list_entry(cnic_udev_list.next, struct cnic_uio_dev,
  4693. list);
  4694. cnic_free_uio(udev);
  4695. }
  4696. }
  4697. static int __init cnic_init(void)
  4698. {
  4699. int rc = 0;
  4700. pr_info("%s", version);
  4701. rc = register_netdevice_notifier(&cnic_netdev_notifier);
  4702. if (rc) {
  4703. cnic_release();
  4704. return rc;
  4705. }
  4706. cnic_wq = create_singlethread_workqueue("cnic_wq");
  4707. if (!cnic_wq) {
  4708. cnic_release();
  4709. unregister_netdevice_notifier(&cnic_netdev_notifier);
  4710. return -ENOMEM;
  4711. }
  4712. return 0;
  4713. }
  4714. static void __exit cnic_exit(void)
  4715. {
  4716. unregister_netdevice_notifier(&cnic_netdev_notifier);
  4717. cnic_release();
  4718. destroy_workqueue(cnic_wq);
  4719. }
  4720. module_init(cnic_init);
  4721. module_exit(cnic_exit);