bgmac.c 42 KB

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  1. /*
  2. * Driver for (BCM4706)? GBit MAC core on BCMA bus.
  3. *
  4. * Copyright (C) 2012 Rafał Miłecki <zajec5@gmail.com>
  5. *
  6. * Licensed under the GNU/GPL. See COPYING for details.
  7. */
  8. #include "bgmac.h"
  9. #include <linux/kernel.h>
  10. #include <linux/module.h>
  11. #include <linux/delay.h>
  12. #include <linux/etherdevice.h>
  13. #include <linux/mii.h>
  14. #include <linux/phy.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/dma-mapping.h>
  17. #include <bcm47xx_nvram.h>
  18. static const struct bcma_device_id bgmac_bcma_tbl[] = {
  19. BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_4706_MAC_GBIT, BCMA_ANY_REV, BCMA_ANY_CLASS),
  20. BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_MAC_GBIT, BCMA_ANY_REV, BCMA_ANY_CLASS),
  21. BCMA_CORETABLE_END
  22. };
  23. MODULE_DEVICE_TABLE(bcma, bgmac_bcma_tbl);
  24. static bool bgmac_wait_value(struct bcma_device *core, u16 reg, u32 mask,
  25. u32 value, int timeout)
  26. {
  27. u32 val;
  28. int i;
  29. for (i = 0; i < timeout / 10; i++) {
  30. val = bcma_read32(core, reg);
  31. if ((val & mask) == value)
  32. return true;
  33. udelay(10);
  34. }
  35. pr_err("Timeout waiting for reg 0x%X\n", reg);
  36. return false;
  37. }
  38. /**************************************************
  39. * DMA
  40. **************************************************/
  41. static void bgmac_dma_tx_reset(struct bgmac *bgmac, struct bgmac_dma_ring *ring)
  42. {
  43. u32 val;
  44. int i;
  45. if (!ring->mmio_base)
  46. return;
  47. /* Suspend DMA TX ring first.
  48. * bgmac_wait_value doesn't support waiting for any of few values, so
  49. * implement whole loop here.
  50. */
  51. bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL,
  52. BGMAC_DMA_TX_SUSPEND);
  53. for (i = 0; i < 10000 / 10; i++) {
  54. val = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS);
  55. val &= BGMAC_DMA_TX_STAT;
  56. if (val == BGMAC_DMA_TX_STAT_DISABLED ||
  57. val == BGMAC_DMA_TX_STAT_IDLEWAIT ||
  58. val == BGMAC_DMA_TX_STAT_STOPPED) {
  59. i = 0;
  60. break;
  61. }
  62. udelay(10);
  63. }
  64. if (i)
  65. bgmac_err(bgmac, "Timeout suspending DMA TX ring 0x%X (BGMAC_DMA_TX_STAT: 0x%08X)\n",
  66. ring->mmio_base, val);
  67. /* Remove SUSPEND bit */
  68. bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, 0);
  69. if (!bgmac_wait_value(bgmac->core,
  70. ring->mmio_base + BGMAC_DMA_TX_STATUS,
  71. BGMAC_DMA_TX_STAT, BGMAC_DMA_TX_STAT_DISABLED,
  72. 10000)) {
  73. bgmac_warn(bgmac, "DMA TX ring 0x%X wasn't disabled on time, waiting additional 300us\n",
  74. ring->mmio_base);
  75. udelay(300);
  76. val = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS);
  77. if ((val & BGMAC_DMA_TX_STAT) != BGMAC_DMA_TX_STAT_DISABLED)
  78. bgmac_err(bgmac, "Reset of DMA TX ring 0x%X failed\n",
  79. ring->mmio_base);
  80. }
  81. }
  82. static void bgmac_dma_tx_enable(struct bgmac *bgmac,
  83. struct bgmac_dma_ring *ring)
  84. {
  85. u32 ctl;
  86. ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL);
  87. ctl |= BGMAC_DMA_TX_ENABLE;
  88. ctl |= BGMAC_DMA_TX_PARITY_DISABLE;
  89. bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, ctl);
  90. }
  91. static netdev_tx_t bgmac_dma_tx_add(struct bgmac *bgmac,
  92. struct bgmac_dma_ring *ring,
  93. struct sk_buff *skb)
  94. {
  95. struct device *dma_dev = bgmac->core->dma_dev;
  96. struct net_device *net_dev = bgmac->net_dev;
  97. struct bgmac_dma_desc *dma_desc;
  98. struct bgmac_slot_info *slot;
  99. u32 ctl0, ctl1;
  100. int free_slots;
  101. if (skb->len > BGMAC_DESC_CTL1_LEN) {
  102. bgmac_err(bgmac, "Too long skb (%d)\n", skb->len);
  103. goto err_stop_drop;
  104. }
  105. if (ring->start <= ring->end)
  106. free_slots = ring->start - ring->end + BGMAC_TX_RING_SLOTS;
  107. else
  108. free_slots = ring->start - ring->end;
  109. if (free_slots == 1) {
  110. bgmac_err(bgmac, "TX ring is full, queue should be stopped!\n");
  111. netif_stop_queue(net_dev);
  112. return NETDEV_TX_BUSY;
  113. }
  114. slot = &ring->slots[ring->end];
  115. slot->skb = skb;
  116. slot->dma_addr = dma_map_single(dma_dev, skb->data, skb->len,
  117. DMA_TO_DEVICE);
  118. if (dma_mapping_error(dma_dev, slot->dma_addr)) {
  119. bgmac_err(bgmac, "Mapping error of skb on ring 0x%X\n",
  120. ring->mmio_base);
  121. goto err_stop_drop;
  122. }
  123. ctl0 = BGMAC_DESC_CTL0_IOC | BGMAC_DESC_CTL0_SOF | BGMAC_DESC_CTL0_EOF;
  124. if (ring->end == ring->num_slots - 1)
  125. ctl0 |= BGMAC_DESC_CTL0_EOT;
  126. ctl1 = skb->len & BGMAC_DESC_CTL1_LEN;
  127. dma_desc = ring->cpu_base;
  128. dma_desc += ring->end;
  129. dma_desc->addr_low = cpu_to_le32(lower_32_bits(slot->dma_addr));
  130. dma_desc->addr_high = cpu_to_le32(upper_32_bits(slot->dma_addr));
  131. dma_desc->ctl0 = cpu_to_le32(ctl0);
  132. dma_desc->ctl1 = cpu_to_le32(ctl1);
  133. wmb();
  134. /* Increase ring->end to point empty slot. We tell hardware the first
  135. * slot it should *not* read.
  136. */
  137. if (++ring->end >= BGMAC_TX_RING_SLOTS)
  138. ring->end = 0;
  139. bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_INDEX,
  140. ring->end * sizeof(struct bgmac_dma_desc));
  141. /* Always keep one slot free to allow detecting bugged calls. */
  142. if (--free_slots == 1)
  143. netif_stop_queue(net_dev);
  144. return NETDEV_TX_OK;
  145. err_stop_drop:
  146. netif_stop_queue(net_dev);
  147. dev_kfree_skb(skb);
  148. return NETDEV_TX_OK;
  149. }
  150. /* Free transmitted packets */
  151. static void bgmac_dma_tx_free(struct bgmac *bgmac, struct bgmac_dma_ring *ring)
  152. {
  153. struct device *dma_dev = bgmac->core->dma_dev;
  154. int empty_slot;
  155. bool freed = false;
  156. /* The last slot that hardware didn't consume yet */
  157. empty_slot = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS);
  158. empty_slot &= BGMAC_DMA_TX_STATDPTR;
  159. empty_slot /= sizeof(struct bgmac_dma_desc);
  160. while (ring->start != empty_slot) {
  161. struct bgmac_slot_info *slot = &ring->slots[ring->start];
  162. if (slot->skb) {
  163. /* Unmap no longer used buffer */
  164. dma_unmap_single(dma_dev, slot->dma_addr,
  165. slot->skb->len, DMA_TO_DEVICE);
  166. slot->dma_addr = 0;
  167. /* Free memory! :) */
  168. dev_kfree_skb(slot->skb);
  169. slot->skb = NULL;
  170. } else {
  171. bgmac_err(bgmac, "Hardware reported transmission for empty TX ring slot %d! End of ring: %d\n",
  172. ring->start, ring->end);
  173. }
  174. if (++ring->start >= BGMAC_TX_RING_SLOTS)
  175. ring->start = 0;
  176. freed = true;
  177. }
  178. if (freed && netif_queue_stopped(bgmac->net_dev))
  179. netif_wake_queue(bgmac->net_dev);
  180. }
  181. static void bgmac_dma_rx_reset(struct bgmac *bgmac, struct bgmac_dma_ring *ring)
  182. {
  183. if (!ring->mmio_base)
  184. return;
  185. bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL, 0);
  186. if (!bgmac_wait_value(bgmac->core,
  187. ring->mmio_base + BGMAC_DMA_RX_STATUS,
  188. BGMAC_DMA_RX_STAT, BGMAC_DMA_RX_STAT_DISABLED,
  189. 10000))
  190. bgmac_err(bgmac, "Reset of ring 0x%X RX failed\n",
  191. ring->mmio_base);
  192. }
  193. static void bgmac_dma_rx_enable(struct bgmac *bgmac,
  194. struct bgmac_dma_ring *ring)
  195. {
  196. u32 ctl;
  197. ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL);
  198. ctl &= BGMAC_DMA_RX_ADDREXT_MASK;
  199. ctl |= BGMAC_DMA_RX_ENABLE;
  200. ctl |= BGMAC_DMA_RX_PARITY_DISABLE;
  201. ctl |= BGMAC_DMA_RX_OVERFLOW_CONT;
  202. ctl |= BGMAC_RX_FRAME_OFFSET << BGMAC_DMA_RX_FRAME_OFFSET_SHIFT;
  203. bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL, ctl);
  204. }
  205. static int bgmac_dma_rx_skb_for_slot(struct bgmac *bgmac,
  206. struct bgmac_slot_info *slot)
  207. {
  208. struct device *dma_dev = bgmac->core->dma_dev;
  209. struct bgmac_rx_header *rx;
  210. /* Alloc skb */
  211. slot->skb = netdev_alloc_skb(bgmac->net_dev, BGMAC_RX_BUF_SIZE);
  212. if (!slot->skb)
  213. return -ENOMEM;
  214. /* Poison - if everything goes fine, hardware will overwrite it */
  215. rx = (struct bgmac_rx_header *)slot->skb->data;
  216. rx->len = cpu_to_le16(0xdead);
  217. rx->flags = cpu_to_le16(0xbeef);
  218. /* Map skb for the DMA */
  219. slot->dma_addr = dma_map_single(dma_dev, slot->skb->data,
  220. BGMAC_RX_BUF_SIZE, DMA_FROM_DEVICE);
  221. if (dma_mapping_error(dma_dev, slot->dma_addr)) {
  222. bgmac_err(bgmac, "DMA mapping error\n");
  223. return -ENOMEM;
  224. }
  225. if (slot->dma_addr & 0xC0000000)
  226. bgmac_warn(bgmac, "DMA address using 0xC0000000 bit(s), it may need translation trick\n");
  227. return 0;
  228. }
  229. static int bgmac_dma_rx_read(struct bgmac *bgmac, struct bgmac_dma_ring *ring,
  230. int weight)
  231. {
  232. u32 end_slot;
  233. int handled = 0;
  234. end_slot = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_STATUS);
  235. end_slot &= BGMAC_DMA_RX_STATDPTR;
  236. end_slot /= sizeof(struct bgmac_dma_desc);
  237. ring->end = end_slot;
  238. while (ring->start != ring->end) {
  239. struct device *dma_dev = bgmac->core->dma_dev;
  240. struct bgmac_slot_info *slot = &ring->slots[ring->start];
  241. struct sk_buff *skb = slot->skb;
  242. struct sk_buff *new_skb;
  243. struct bgmac_rx_header *rx;
  244. u16 len, flags;
  245. /* Unmap buffer to make it accessible to the CPU */
  246. dma_sync_single_for_cpu(dma_dev, slot->dma_addr,
  247. BGMAC_RX_BUF_SIZE, DMA_FROM_DEVICE);
  248. /* Get info from the header */
  249. rx = (struct bgmac_rx_header *)skb->data;
  250. len = le16_to_cpu(rx->len);
  251. flags = le16_to_cpu(rx->flags);
  252. /* Check for poison and drop or pass the packet */
  253. if (len == 0xdead && flags == 0xbeef) {
  254. bgmac_err(bgmac, "Found poisoned packet at slot %d, DMA issue!\n",
  255. ring->start);
  256. } else {
  257. /* Omit CRC. */
  258. len -= ETH_FCS_LEN;
  259. new_skb = netdev_alloc_skb_ip_align(bgmac->net_dev, len);
  260. if (new_skb) {
  261. skb_put(new_skb, len);
  262. skb_copy_from_linear_data_offset(skb, BGMAC_RX_FRAME_OFFSET,
  263. new_skb->data,
  264. len);
  265. skb_checksum_none_assert(skb);
  266. new_skb->protocol =
  267. eth_type_trans(new_skb, bgmac->net_dev);
  268. netif_receive_skb(new_skb);
  269. handled++;
  270. } else {
  271. bgmac->net_dev->stats.rx_dropped++;
  272. bgmac_err(bgmac, "Allocation of skb for copying packet failed!\n");
  273. }
  274. /* Poison the old skb */
  275. rx->len = cpu_to_le16(0xdead);
  276. rx->flags = cpu_to_le16(0xbeef);
  277. }
  278. /* Make it back accessible to the hardware */
  279. dma_sync_single_for_device(dma_dev, slot->dma_addr,
  280. BGMAC_RX_BUF_SIZE, DMA_FROM_DEVICE);
  281. if (++ring->start >= BGMAC_RX_RING_SLOTS)
  282. ring->start = 0;
  283. if (handled >= weight) /* Should never be greater */
  284. break;
  285. }
  286. return handled;
  287. }
  288. /* Does ring support unaligned addressing? */
  289. static bool bgmac_dma_unaligned(struct bgmac *bgmac,
  290. struct bgmac_dma_ring *ring,
  291. enum bgmac_dma_ring_type ring_type)
  292. {
  293. switch (ring_type) {
  294. case BGMAC_DMA_RING_TX:
  295. bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO,
  296. 0xff0);
  297. if (bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO))
  298. return true;
  299. break;
  300. case BGMAC_DMA_RING_RX:
  301. bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO,
  302. 0xff0);
  303. if (bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO))
  304. return true;
  305. break;
  306. }
  307. return false;
  308. }
  309. static void bgmac_dma_ring_free(struct bgmac *bgmac,
  310. struct bgmac_dma_ring *ring)
  311. {
  312. struct device *dma_dev = bgmac->core->dma_dev;
  313. struct bgmac_slot_info *slot;
  314. int size;
  315. int i;
  316. for (i = 0; i < ring->num_slots; i++) {
  317. slot = &ring->slots[i];
  318. if (slot->skb) {
  319. if (slot->dma_addr)
  320. dma_unmap_single(dma_dev, slot->dma_addr,
  321. slot->skb->len, DMA_TO_DEVICE);
  322. dev_kfree_skb(slot->skb);
  323. }
  324. }
  325. if (ring->cpu_base) {
  326. /* Free ring of descriptors */
  327. size = ring->num_slots * sizeof(struct bgmac_dma_desc);
  328. dma_free_coherent(dma_dev, size, ring->cpu_base,
  329. ring->dma_base);
  330. }
  331. }
  332. static void bgmac_dma_free(struct bgmac *bgmac)
  333. {
  334. int i;
  335. for (i = 0; i < BGMAC_MAX_TX_RINGS; i++)
  336. bgmac_dma_ring_free(bgmac, &bgmac->tx_ring[i]);
  337. for (i = 0; i < BGMAC_MAX_RX_RINGS; i++)
  338. bgmac_dma_ring_free(bgmac, &bgmac->rx_ring[i]);
  339. }
  340. static int bgmac_dma_alloc(struct bgmac *bgmac)
  341. {
  342. struct device *dma_dev = bgmac->core->dma_dev;
  343. struct bgmac_dma_ring *ring;
  344. static const u16 ring_base[] = { BGMAC_DMA_BASE0, BGMAC_DMA_BASE1,
  345. BGMAC_DMA_BASE2, BGMAC_DMA_BASE3, };
  346. int size; /* ring size: different for Tx and Rx */
  347. int err;
  348. int i;
  349. BUILD_BUG_ON(BGMAC_MAX_TX_RINGS > ARRAY_SIZE(ring_base));
  350. BUILD_BUG_ON(BGMAC_MAX_RX_RINGS > ARRAY_SIZE(ring_base));
  351. if (!(bcma_aread32(bgmac->core, BCMA_IOST) & BCMA_IOST_DMA64)) {
  352. bgmac_err(bgmac, "Core does not report 64-bit DMA\n");
  353. return -ENOTSUPP;
  354. }
  355. for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) {
  356. ring = &bgmac->tx_ring[i];
  357. ring->num_slots = BGMAC_TX_RING_SLOTS;
  358. ring->mmio_base = ring_base[i];
  359. if (bgmac_dma_unaligned(bgmac, ring, BGMAC_DMA_RING_TX))
  360. bgmac_warn(bgmac, "TX on ring 0x%X supports unaligned addressing but this feature is not implemented\n",
  361. ring->mmio_base);
  362. /* Alloc ring of descriptors */
  363. size = ring->num_slots * sizeof(struct bgmac_dma_desc);
  364. ring->cpu_base = dma_zalloc_coherent(dma_dev, size,
  365. &ring->dma_base,
  366. GFP_KERNEL);
  367. if (!ring->cpu_base) {
  368. bgmac_err(bgmac, "Allocation of TX ring 0x%X failed\n",
  369. ring->mmio_base);
  370. goto err_dma_free;
  371. }
  372. if (ring->dma_base & 0xC0000000)
  373. bgmac_warn(bgmac, "DMA address using 0xC0000000 bit(s), it may need translation trick\n");
  374. /* No need to alloc TX slots yet */
  375. }
  376. for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) {
  377. int j;
  378. ring = &bgmac->rx_ring[i];
  379. ring->num_slots = BGMAC_RX_RING_SLOTS;
  380. ring->mmio_base = ring_base[i];
  381. if (bgmac_dma_unaligned(bgmac, ring, BGMAC_DMA_RING_RX))
  382. bgmac_warn(bgmac, "RX on ring 0x%X supports unaligned addressing but this feature is not implemented\n",
  383. ring->mmio_base);
  384. /* Alloc ring of descriptors */
  385. size = ring->num_slots * sizeof(struct bgmac_dma_desc);
  386. ring->cpu_base = dma_zalloc_coherent(dma_dev, size,
  387. &ring->dma_base,
  388. GFP_KERNEL);
  389. if (!ring->cpu_base) {
  390. bgmac_err(bgmac, "Allocation of RX ring 0x%X failed\n",
  391. ring->mmio_base);
  392. err = -ENOMEM;
  393. goto err_dma_free;
  394. }
  395. if (ring->dma_base & 0xC0000000)
  396. bgmac_warn(bgmac, "DMA address using 0xC0000000 bit(s), it may need translation trick\n");
  397. /* Alloc RX slots */
  398. for (j = 0; j < ring->num_slots; j++) {
  399. err = bgmac_dma_rx_skb_for_slot(bgmac, &ring->slots[j]);
  400. if (err) {
  401. bgmac_err(bgmac, "Can't allocate skb for slot in RX ring\n");
  402. goto err_dma_free;
  403. }
  404. }
  405. }
  406. return 0;
  407. err_dma_free:
  408. bgmac_dma_free(bgmac);
  409. return -ENOMEM;
  410. }
  411. static void bgmac_dma_init(struct bgmac *bgmac)
  412. {
  413. struct bgmac_dma_ring *ring;
  414. struct bgmac_dma_desc *dma_desc;
  415. u32 ctl0, ctl1;
  416. int i;
  417. for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) {
  418. ring = &bgmac->tx_ring[i];
  419. /* We don't implement unaligned addressing, so enable first */
  420. bgmac_dma_tx_enable(bgmac, ring);
  421. bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO,
  422. lower_32_bits(ring->dma_base));
  423. bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGHI,
  424. upper_32_bits(ring->dma_base));
  425. ring->start = 0;
  426. ring->end = 0; /* Points the slot that should *not* be read */
  427. }
  428. for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) {
  429. int j;
  430. ring = &bgmac->rx_ring[i];
  431. /* We don't implement unaligned addressing, so enable first */
  432. bgmac_dma_rx_enable(bgmac, ring);
  433. bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO,
  434. lower_32_bits(ring->dma_base));
  435. bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGHI,
  436. upper_32_bits(ring->dma_base));
  437. for (j = 0, dma_desc = ring->cpu_base; j < ring->num_slots;
  438. j++, dma_desc++) {
  439. ctl0 = ctl1 = 0;
  440. if (j == ring->num_slots - 1)
  441. ctl0 |= BGMAC_DESC_CTL0_EOT;
  442. ctl1 |= BGMAC_RX_BUF_SIZE & BGMAC_DESC_CTL1_LEN;
  443. /* Is there any BGMAC device that requires extension? */
  444. /* ctl1 |= (addrext << B43_DMA64_DCTL1_ADDREXT_SHIFT) &
  445. * B43_DMA64_DCTL1_ADDREXT_MASK;
  446. */
  447. dma_desc->addr_low = cpu_to_le32(lower_32_bits(ring->slots[j].dma_addr));
  448. dma_desc->addr_high = cpu_to_le32(upper_32_bits(ring->slots[j].dma_addr));
  449. dma_desc->ctl0 = cpu_to_le32(ctl0);
  450. dma_desc->ctl1 = cpu_to_le32(ctl1);
  451. }
  452. bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_INDEX,
  453. ring->num_slots * sizeof(struct bgmac_dma_desc));
  454. ring->start = 0;
  455. ring->end = 0;
  456. }
  457. }
  458. /**************************************************
  459. * PHY ops
  460. **************************************************/
  461. static u16 bgmac_phy_read(struct bgmac *bgmac, u8 phyaddr, u8 reg)
  462. {
  463. struct bcma_device *core;
  464. u16 phy_access_addr;
  465. u16 phy_ctl_addr;
  466. u32 tmp;
  467. BUILD_BUG_ON(BGMAC_PA_DATA_MASK != BCMA_GMAC_CMN_PA_DATA_MASK);
  468. BUILD_BUG_ON(BGMAC_PA_ADDR_MASK != BCMA_GMAC_CMN_PA_ADDR_MASK);
  469. BUILD_BUG_ON(BGMAC_PA_ADDR_SHIFT != BCMA_GMAC_CMN_PA_ADDR_SHIFT);
  470. BUILD_BUG_ON(BGMAC_PA_REG_MASK != BCMA_GMAC_CMN_PA_REG_MASK);
  471. BUILD_BUG_ON(BGMAC_PA_REG_SHIFT != BCMA_GMAC_CMN_PA_REG_SHIFT);
  472. BUILD_BUG_ON(BGMAC_PA_WRITE != BCMA_GMAC_CMN_PA_WRITE);
  473. BUILD_BUG_ON(BGMAC_PA_START != BCMA_GMAC_CMN_PA_START);
  474. BUILD_BUG_ON(BGMAC_PC_EPA_MASK != BCMA_GMAC_CMN_PC_EPA_MASK);
  475. BUILD_BUG_ON(BGMAC_PC_MCT_MASK != BCMA_GMAC_CMN_PC_MCT_MASK);
  476. BUILD_BUG_ON(BGMAC_PC_MCT_SHIFT != BCMA_GMAC_CMN_PC_MCT_SHIFT);
  477. BUILD_BUG_ON(BGMAC_PC_MTE != BCMA_GMAC_CMN_PC_MTE);
  478. if (bgmac->core->id.id == BCMA_CORE_4706_MAC_GBIT) {
  479. core = bgmac->core->bus->drv_gmac_cmn.core;
  480. phy_access_addr = BCMA_GMAC_CMN_PHY_ACCESS;
  481. phy_ctl_addr = BCMA_GMAC_CMN_PHY_CTL;
  482. } else {
  483. core = bgmac->core;
  484. phy_access_addr = BGMAC_PHY_ACCESS;
  485. phy_ctl_addr = BGMAC_PHY_CNTL;
  486. }
  487. tmp = bcma_read32(core, phy_ctl_addr);
  488. tmp &= ~BGMAC_PC_EPA_MASK;
  489. tmp |= phyaddr;
  490. bcma_write32(core, phy_ctl_addr, tmp);
  491. tmp = BGMAC_PA_START;
  492. tmp |= phyaddr << BGMAC_PA_ADDR_SHIFT;
  493. tmp |= reg << BGMAC_PA_REG_SHIFT;
  494. bcma_write32(core, phy_access_addr, tmp);
  495. if (!bgmac_wait_value(core, phy_access_addr, BGMAC_PA_START, 0, 1000)) {
  496. bgmac_err(bgmac, "Reading PHY %d register 0x%X failed\n",
  497. phyaddr, reg);
  498. return 0xffff;
  499. }
  500. return bcma_read32(core, phy_access_addr) & BGMAC_PA_DATA_MASK;
  501. }
  502. /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphywr */
  503. static int bgmac_phy_write(struct bgmac *bgmac, u8 phyaddr, u8 reg, u16 value)
  504. {
  505. struct bcma_device *core;
  506. u16 phy_access_addr;
  507. u16 phy_ctl_addr;
  508. u32 tmp;
  509. if (bgmac->core->id.id == BCMA_CORE_4706_MAC_GBIT) {
  510. core = bgmac->core->bus->drv_gmac_cmn.core;
  511. phy_access_addr = BCMA_GMAC_CMN_PHY_ACCESS;
  512. phy_ctl_addr = BCMA_GMAC_CMN_PHY_CTL;
  513. } else {
  514. core = bgmac->core;
  515. phy_access_addr = BGMAC_PHY_ACCESS;
  516. phy_ctl_addr = BGMAC_PHY_CNTL;
  517. }
  518. tmp = bcma_read32(core, phy_ctl_addr);
  519. tmp &= ~BGMAC_PC_EPA_MASK;
  520. tmp |= phyaddr;
  521. bcma_write32(core, phy_ctl_addr, tmp);
  522. bgmac_write(bgmac, BGMAC_INT_STATUS, BGMAC_IS_MDIO);
  523. if (bgmac_read(bgmac, BGMAC_INT_STATUS) & BGMAC_IS_MDIO)
  524. bgmac_warn(bgmac, "Error setting MDIO int\n");
  525. tmp = BGMAC_PA_START;
  526. tmp |= BGMAC_PA_WRITE;
  527. tmp |= phyaddr << BGMAC_PA_ADDR_SHIFT;
  528. tmp |= reg << BGMAC_PA_REG_SHIFT;
  529. tmp |= value;
  530. bcma_write32(core, phy_access_addr, tmp);
  531. if (!bgmac_wait_value(core, phy_access_addr, BGMAC_PA_START, 0, 1000)) {
  532. bgmac_err(bgmac, "Writing to PHY %d register 0x%X failed\n",
  533. phyaddr, reg);
  534. return -ETIMEDOUT;
  535. }
  536. return 0;
  537. }
  538. /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphyforce */
  539. static void bgmac_phy_force(struct bgmac *bgmac)
  540. {
  541. u16 ctl;
  542. u16 mask = ~(BGMAC_PHY_CTL_SPEED | BGMAC_PHY_CTL_SPEED_MSB |
  543. BGMAC_PHY_CTL_ANENAB | BGMAC_PHY_CTL_DUPLEX);
  544. if (bgmac->phyaddr == BGMAC_PHY_NOREGS)
  545. return;
  546. if (bgmac->autoneg)
  547. return;
  548. ctl = bgmac_phy_read(bgmac, bgmac->phyaddr, BGMAC_PHY_CTL);
  549. ctl &= mask;
  550. if (bgmac->full_duplex)
  551. ctl |= BGMAC_PHY_CTL_DUPLEX;
  552. if (bgmac->speed == BGMAC_SPEED_100)
  553. ctl |= BGMAC_PHY_CTL_SPEED_100;
  554. else if (bgmac->speed == BGMAC_SPEED_1000)
  555. ctl |= BGMAC_PHY_CTL_SPEED_1000;
  556. bgmac_phy_write(bgmac, bgmac->phyaddr, BGMAC_PHY_CTL, ctl);
  557. }
  558. /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphyadvertise */
  559. static void bgmac_phy_advertise(struct bgmac *bgmac)
  560. {
  561. u16 adv;
  562. if (bgmac->phyaddr == BGMAC_PHY_NOREGS)
  563. return;
  564. if (!bgmac->autoneg)
  565. return;
  566. /* Adv selected 10/100 speeds */
  567. adv = bgmac_phy_read(bgmac, bgmac->phyaddr, BGMAC_PHY_ADV);
  568. adv &= ~(BGMAC_PHY_ADV_10HALF | BGMAC_PHY_ADV_10FULL |
  569. BGMAC_PHY_ADV_100HALF | BGMAC_PHY_ADV_100FULL);
  570. if (!bgmac->full_duplex && bgmac->speed & BGMAC_SPEED_10)
  571. adv |= BGMAC_PHY_ADV_10HALF;
  572. if (!bgmac->full_duplex && bgmac->speed & BGMAC_SPEED_100)
  573. adv |= BGMAC_PHY_ADV_100HALF;
  574. if (bgmac->full_duplex && bgmac->speed & BGMAC_SPEED_10)
  575. adv |= BGMAC_PHY_ADV_10FULL;
  576. if (bgmac->full_duplex && bgmac->speed & BGMAC_SPEED_100)
  577. adv |= BGMAC_PHY_ADV_100FULL;
  578. bgmac_phy_write(bgmac, bgmac->phyaddr, BGMAC_PHY_ADV, adv);
  579. /* Adv selected 1000 speeds */
  580. adv = bgmac_phy_read(bgmac, bgmac->phyaddr, BGMAC_PHY_ADV2);
  581. adv &= ~(BGMAC_PHY_ADV2_1000HALF | BGMAC_PHY_ADV2_1000FULL);
  582. if (!bgmac->full_duplex && bgmac->speed & BGMAC_SPEED_1000)
  583. adv |= BGMAC_PHY_ADV2_1000HALF;
  584. if (bgmac->full_duplex && bgmac->speed & BGMAC_SPEED_1000)
  585. adv |= BGMAC_PHY_ADV2_1000FULL;
  586. bgmac_phy_write(bgmac, bgmac->phyaddr, BGMAC_PHY_ADV2, adv);
  587. /* Restart */
  588. bgmac_phy_write(bgmac, bgmac->phyaddr, BGMAC_PHY_CTL,
  589. bgmac_phy_read(bgmac, bgmac->phyaddr, BGMAC_PHY_CTL) |
  590. BGMAC_PHY_CTL_RESTART);
  591. }
  592. /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphyinit */
  593. static void bgmac_phy_init(struct bgmac *bgmac)
  594. {
  595. struct bcma_chipinfo *ci = &bgmac->core->bus->chipinfo;
  596. struct bcma_drv_cc *cc = &bgmac->core->bus->drv_cc;
  597. u8 i;
  598. if (ci->id == BCMA_CHIP_ID_BCM5356) {
  599. for (i = 0; i < 5; i++) {
  600. bgmac_phy_write(bgmac, i, 0x1f, 0x008b);
  601. bgmac_phy_write(bgmac, i, 0x15, 0x0100);
  602. bgmac_phy_write(bgmac, i, 0x1f, 0x000f);
  603. bgmac_phy_write(bgmac, i, 0x12, 0x2aaa);
  604. bgmac_phy_write(bgmac, i, 0x1f, 0x000b);
  605. }
  606. }
  607. if ((ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg != 10) ||
  608. (ci->id == BCMA_CHIP_ID_BCM4749 && ci->pkg != 10) ||
  609. (ci->id == BCMA_CHIP_ID_BCM53572 && ci->pkg != 9)) {
  610. bcma_chipco_chipctl_maskset(cc, 2, ~0xc0000000, 0);
  611. bcma_chipco_chipctl_maskset(cc, 4, ~0x80000000, 0);
  612. for (i = 0; i < 5; i++) {
  613. bgmac_phy_write(bgmac, i, 0x1f, 0x000f);
  614. bgmac_phy_write(bgmac, i, 0x16, 0x5284);
  615. bgmac_phy_write(bgmac, i, 0x1f, 0x000b);
  616. bgmac_phy_write(bgmac, i, 0x17, 0x0010);
  617. bgmac_phy_write(bgmac, i, 0x1f, 0x000f);
  618. bgmac_phy_write(bgmac, i, 0x16, 0x5296);
  619. bgmac_phy_write(bgmac, i, 0x17, 0x1073);
  620. bgmac_phy_write(bgmac, i, 0x17, 0x9073);
  621. bgmac_phy_write(bgmac, i, 0x16, 0x52b6);
  622. bgmac_phy_write(bgmac, i, 0x17, 0x9273);
  623. bgmac_phy_write(bgmac, i, 0x1f, 0x000b);
  624. }
  625. }
  626. }
  627. /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphyreset */
  628. static void bgmac_phy_reset(struct bgmac *bgmac)
  629. {
  630. if (bgmac->phyaddr == BGMAC_PHY_NOREGS)
  631. return;
  632. bgmac_phy_write(bgmac, bgmac->phyaddr, BGMAC_PHY_CTL,
  633. BGMAC_PHY_CTL_RESET);
  634. udelay(100);
  635. if (bgmac_phy_read(bgmac, bgmac->phyaddr, BGMAC_PHY_CTL) &
  636. BGMAC_PHY_CTL_RESET)
  637. bgmac_err(bgmac, "PHY reset failed\n");
  638. bgmac_phy_init(bgmac);
  639. }
  640. /**************************************************
  641. * Chip ops
  642. **************************************************/
  643. /* TODO: can we just drop @force? Can we don't reset MAC at all if there is
  644. * nothing to change? Try if after stabilizng driver.
  645. */
  646. static void bgmac_cmdcfg_maskset(struct bgmac *bgmac, u32 mask, u32 set,
  647. bool force)
  648. {
  649. u32 cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG);
  650. u32 new_val = (cmdcfg & mask) | set;
  651. bgmac_set(bgmac, BGMAC_CMDCFG, BGMAC_CMDCFG_SR);
  652. udelay(2);
  653. if (new_val != cmdcfg || force)
  654. bgmac_write(bgmac, BGMAC_CMDCFG, new_val);
  655. bgmac_mask(bgmac, BGMAC_CMDCFG, ~BGMAC_CMDCFG_SR);
  656. udelay(2);
  657. }
  658. static void bgmac_write_mac_address(struct bgmac *bgmac, u8 *addr)
  659. {
  660. u32 tmp;
  661. tmp = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
  662. bgmac_write(bgmac, BGMAC_MACADDR_HIGH, tmp);
  663. tmp = (addr[4] << 8) | addr[5];
  664. bgmac_write(bgmac, BGMAC_MACADDR_LOW, tmp);
  665. }
  666. static void bgmac_set_rx_mode(struct net_device *net_dev)
  667. {
  668. struct bgmac *bgmac = netdev_priv(net_dev);
  669. if (net_dev->flags & IFF_PROMISC)
  670. bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_PROM, true);
  671. else
  672. bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_PROM, 0, true);
  673. }
  674. #if 0 /* We don't use that regs yet */
  675. static void bgmac_chip_stats_update(struct bgmac *bgmac)
  676. {
  677. int i;
  678. if (bgmac->core->id.id != BCMA_CORE_4706_MAC_GBIT) {
  679. for (i = 0; i < BGMAC_NUM_MIB_TX_REGS; i++)
  680. bgmac->mib_tx_regs[i] =
  681. bgmac_read(bgmac,
  682. BGMAC_TX_GOOD_OCTETS + (i * 4));
  683. for (i = 0; i < BGMAC_NUM_MIB_RX_REGS; i++)
  684. bgmac->mib_rx_regs[i] =
  685. bgmac_read(bgmac,
  686. BGMAC_RX_GOOD_OCTETS + (i * 4));
  687. }
  688. /* TODO: what else? how to handle BCM4706? Specs are needed */
  689. }
  690. #endif
  691. static void bgmac_clear_mib(struct bgmac *bgmac)
  692. {
  693. int i;
  694. if (bgmac->core->id.id == BCMA_CORE_4706_MAC_GBIT)
  695. return;
  696. bgmac_set(bgmac, BGMAC_DEV_CTL, BGMAC_DC_MROR);
  697. for (i = 0; i < BGMAC_NUM_MIB_TX_REGS; i++)
  698. bgmac_read(bgmac, BGMAC_TX_GOOD_OCTETS + (i * 4));
  699. for (i = 0; i < BGMAC_NUM_MIB_RX_REGS; i++)
  700. bgmac_read(bgmac, BGMAC_RX_GOOD_OCTETS + (i * 4));
  701. }
  702. /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_speed */
  703. static void bgmac_speed(struct bgmac *bgmac, int speed)
  704. {
  705. u32 mask = ~(BGMAC_CMDCFG_ES_MASK | BGMAC_CMDCFG_HD);
  706. u32 set = 0;
  707. if (speed & BGMAC_SPEED_10)
  708. set |= BGMAC_CMDCFG_ES_10;
  709. if (speed & BGMAC_SPEED_100)
  710. set |= BGMAC_CMDCFG_ES_100;
  711. if (speed & BGMAC_SPEED_1000)
  712. set |= BGMAC_CMDCFG_ES_1000;
  713. if (!bgmac->full_duplex)
  714. set |= BGMAC_CMDCFG_HD;
  715. bgmac_cmdcfg_maskset(bgmac, mask, set, true);
  716. }
  717. static void bgmac_miiconfig(struct bgmac *bgmac)
  718. {
  719. u8 imode = (bgmac_read(bgmac, BGMAC_DEV_STATUS) & BGMAC_DS_MM_MASK) >>
  720. BGMAC_DS_MM_SHIFT;
  721. if (imode == 0 || imode == 1) {
  722. if (bgmac->autoneg)
  723. bgmac_speed(bgmac, BGMAC_SPEED_100);
  724. else
  725. bgmac_speed(bgmac, bgmac->speed);
  726. }
  727. }
  728. /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipreset */
  729. static void bgmac_chip_reset(struct bgmac *bgmac)
  730. {
  731. struct bcma_device *core = bgmac->core;
  732. struct bcma_bus *bus = core->bus;
  733. struct bcma_chipinfo *ci = &bus->chipinfo;
  734. u32 flags = 0;
  735. u32 iost;
  736. int i;
  737. if (bcma_core_is_enabled(core)) {
  738. if (!bgmac->stats_grabbed) {
  739. /* bgmac_chip_stats_update(bgmac); */
  740. bgmac->stats_grabbed = true;
  741. }
  742. for (i = 0; i < BGMAC_MAX_TX_RINGS; i++)
  743. bgmac_dma_tx_reset(bgmac, &bgmac->tx_ring[i]);
  744. bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_ML, false);
  745. udelay(1);
  746. for (i = 0; i < BGMAC_MAX_RX_RINGS; i++)
  747. bgmac_dma_rx_reset(bgmac, &bgmac->rx_ring[i]);
  748. /* TODO: Clear software multicast filter list */
  749. }
  750. iost = bcma_aread32(core, BCMA_IOST);
  751. if ((ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg == 10) ||
  752. (ci->id == BCMA_CHIP_ID_BCM4749 && ci->pkg == 10) ||
  753. (ci->id == BCMA_CHIP_ID_BCM53572 && ci->pkg == 9))
  754. iost &= ~BGMAC_BCMA_IOST_ATTACHED;
  755. if (iost & BGMAC_BCMA_IOST_ATTACHED) {
  756. flags = BGMAC_BCMA_IOCTL_SW_CLKEN;
  757. if (!bgmac->has_robosw)
  758. flags |= BGMAC_BCMA_IOCTL_SW_RESET;
  759. }
  760. bcma_core_enable(core, flags);
  761. if (core->id.rev > 2) {
  762. bgmac_set(bgmac, BCMA_CLKCTLST, 1 << 8);
  763. bgmac_wait_value(bgmac->core, BCMA_CLKCTLST, 1 << 24, 1 << 24,
  764. 1000);
  765. }
  766. if (ci->id == BCMA_CHIP_ID_BCM5357 || ci->id == BCMA_CHIP_ID_BCM4749 ||
  767. ci->id == BCMA_CHIP_ID_BCM53572) {
  768. struct bcma_drv_cc *cc = &bgmac->core->bus->drv_cc;
  769. u8 et_swtype = 0;
  770. u8 sw_type = BGMAC_CHIPCTL_1_SW_TYPE_EPHY |
  771. BGMAC_CHIPCTL_1_IF_TYPE_RMII;
  772. char buf[2];
  773. if (bcm47xx_nvram_getenv("et_swtype", buf, 1) > 0) {
  774. if (kstrtou8(buf, 0, &et_swtype))
  775. bgmac_err(bgmac, "Failed to parse et_swtype (%s)\n",
  776. buf);
  777. et_swtype &= 0x0f;
  778. et_swtype <<= 4;
  779. sw_type = et_swtype;
  780. } else if (ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg == 9) {
  781. sw_type = BGMAC_CHIPCTL_1_SW_TYPE_EPHYRMII;
  782. } else if ((ci->id != BCMA_CHIP_ID_BCM53572 && ci->pkg == 10) ||
  783. (ci->id == BCMA_CHIP_ID_BCM53572 && ci->pkg == 9)) {
  784. sw_type = BGMAC_CHIPCTL_1_IF_TYPE_RGMII |
  785. BGMAC_CHIPCTL_1_SW_TYPE_RGMII;
  786. }
  787. bcma_chipco_chipctl_maskset(cc, 1,
  788. ~(BGMAC_CHIPCTL_1_IF_TYPE_MASK |
  789. BGMAC_CHIPCTL_1_SW_TYPE_MASK),
  790. sw_type);
  791. }
  792. if (iost & BGMAC_BCMA_IOST_ATTACHED && !bgmac->has_robosw)
  793. bcma_awrite32(core, BCMA_IOCTL,
  794. bcma_aread32(core, BCMA_IOCTL) &
  795. ~BGMAC_BCMA_IOCTL_SW_RESET);
  796. /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_reset
  797. * Specs don't say about using BGMAC_CMDCFG_SR, but in this routine
  798. * BGMAC_CMDCFG is read _after_ putting chip in a reset. So it has to
  799. * be keps until taking MAC out of the reset.
  800. */
  801. bgmac_cmdcfg_maskset(bgmac,
  802. ~(BGMAC_CMDCFG_TE |
  803. BGMAC_CMDCFG_RE |
  804. BGMAC_CMDCFG_RPI |
  805. BGMAC_CMDCFG_TAI |
  806. BGMAC_CMDCFG_HD |
  807. BGMAC_CMDCFG_ML |
  808. BGMAC_CMDCFG_CFE |
  809. BGMAC_CMDCFG_RL |
  810. BGMAC_CMDCFG_RED |
  811. BGMAC_CMDCFG_PE |
  812. BGMAC_CMDCFG_TPI |
  813. BGMAC_CMDCFG_PAD_EN |
  814. BGMAC_CMDCFG_PF),
  815. BGMAC_CMDCFG_PROM |
  816. BGMAC_CMDCFG_NLC |
  817. BGMAC_CMDCFG_CFE |
  818. BGMAC_CMDCFG_SR,
  819. false);
  820. bgmac_clear_mib(bgmac);
  821. if (core->id.id == BCMA_CORE_4706_MAC_GBIT)
  822. bcma_maskset32(bgmac->cmn, BCMA_GMAC_CMN_PHY_CTL, ~0,
  823. BCMA_GMAC_CMN_PC_MTE);
  824. else
  825. bgmac_set(bgmac, BGMAC_PHY_CNTL, BGMAC_PC_MTE);
  826. bgmac_miiconfig(bgmac);
  827. bgmac_phy_init(bgmac);
  828. bgmac->int_status = 0;
  829. }
  830. static void bgmac_chip_intrs_on(struct bgmac *bgmac)
  831. {
  832. bgmac_write(bgmac, BGMAC_INT_MASK, bgmac->int_mask);
  833. }
  834. static void bgmac_chip_intrs_off(struct bgmac *bgmac)
  835. {
  836. bgmac_write(bgmac, BGMAC_INT_MASK, 0);
  837. bgmac_read(bgmac, BGMAC_INT_MASK);
  838. }
  839. /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_enable */
  840. static void bgmac_enable(struct bgmac *bgmac)
  841. {
  842. struct bcma_chipinfo *ci = &bgmac->core->bus->chipinfo;
  843. u32 cmdcfg;
  844. u32 mode;
  845. u32 rxq_ctl;
  846. u32 fl_ctl;
  847. u16 bp_clk;
  848. u8 mdp;
  849. cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG);
  850. bgmac_cmdcfg_maskset(bgmac, ~(BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE),
  851. BGMAC_CMDCFG_SR, true);
  852. udelay(2);
  853. cmdcfg |= BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE;
  854. bgmac_write(bgmac, BGMAC_CMDCFG, cmdcfg);
  855. mode = (bgmac_read(bgmac, BGMAC_DEV_STATUS) & BGMAC_DS_MM_MASK) >>
  856. BGMAC_DS_MM_SHIFT;
  857. if (ci->id != BCMA_CHIP_ID_BCM47162 || mode != 0)
  858. bgmac_set(bgmac, BCMA_CLKCTLST, BCMA_CLKCTLST_FORCEHT);
  859. if (ci->id == BCMA_CHIP_ID_BCM47162 && mode == 2)
  860. bcma_chipco_chipctl_maskset(&bgmac->core->bus->drv_cc, 1, ~0,
  861. BGMAC_CHIPCTL_1_RXC_DLL_BYPASS);
  862. switch (ci->id) {
  863. case BCMA_CHIP_ID_BCM5357:
  864. case BCMA_CHIP_ID_BCM4749:
  865. case BCMA_CHIP_ID_BCM53572:
  866. case BCMA_CHIP_ID_BCM4716:
  867. case BCMA_CHIP_ID_BCM47162:
  868. fl_ctl = 0x03cb04cb;
  869. if (ci->id == BCMA_CHIP_ID_BCM5357 ||
  870. ci->id == BCMA_CHIP_ID_BCM4749 ||
  871. ci->id == BCMA_CHIP_ID_BCM53572)
  872. fl_ctl = 0x2300e1;
  873. bgmac_write(bgmac, BGMAC_FLOW_CTL_THRESH, fl_ctl);
  874. bgmac_write(bgmac, BGMAC_PAUSE_CTL, 0x27fff);
  875. break;
  876. }
  877. rxq_ctl = bgmac_read(bgmac, BGMAC_RXQ_CTL);
  878. rxq_ctl &= ~BGMAC_RXQ_CTL_MDP_MASK;
  879. bp_clk = bcma_pmu_get_bus_clock(&bgmac->core->bus->drv_cc) / 1000000;
  880. mdp = (bp_clk * 128 / 1000) - 3;
  881. rxq_ctl |= (mdp << BGMAC_RXQ_CTL_MDP_SHIFT);
  882. bgmac_write(bgmac, BGMAC_RXQ_CTL, rxq_ctl);
  883. }
  884. /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipinit */
  885. static void bgmac_chip_init(struct bgmac *bgmac, bool full_init)
  886. {
  887. struct bgmac_dma_ring *ring;
  888. int i;
  889. /* 1 interrupt per received frame */
  890. bgmac_write(bgmac, BGMAC_INT_RECV_LAZY, 1 << BGMAC_IRL_FC_SHIFT);
  891. /* Enable 802.3x tx flow control (honor received PAUSE frames) */
  892. bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_RPI, 0, true);
  893. bgmac_set_rx_mode(bgmac->net_dev);
  894. bgmac_write_mac_address(bgmac, bgmac->net_dev->dev_addr);
  895. if (bgmac->loopback)
  896. bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_ML, false);
  897. else
  898. bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_ML, 0, false);
  899. bgmac_write(bgmac, BGMAC_RXMAX_LENGTH, 32 + ETHER_MAX_LEN);
  900. if (!bgmac->autoneg) {
  901. bgmac_speed(bgmac, bgmac->speed);
  902. bgmac_phy_force(bgmac);
  903. } else if (bgmac->speed) { /* if there is anything to adv */
  904. bgmac_phy_advertise(bgmac);
  905. }
  906. if (full_init) {
  907. bgmac_dma_init(bgmac);
  908. if (1) /* FIXME: is there any case we don't want IRQs? */
  909. bgmac_chip_intrs_on(bgmac);
  910. } else {
  911. for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) {
  912. ring = &bgmac->rx_ring[i];
  913. bgmac_dma_rx_enable(bgmac, ring);
  914. }
  915. }
  916. bgmac_enable(bgmac);
  917. }
  918. static irqreturn_t bgmac_interrupt(int irq, void *dev_id)
  919. {
  920. struct bgmac *bgmac = netdev_priv(dev_id);
  921. u32 int_status = bgmac_read(bgmac, BGMAC_INT_STATUS);
  922. int_status &= bgmac->int_mask;
  923. if (!int_status)
  924. return IRQ_NONE;
  925. /* Ack */
  926. bgmac_write(bgmac, BGMAC_INT_STATUS, int_status);
  927. /* Disable new interrupts until handling existing ones */
  928. bgmac_chip_intrs_off(bgmac);
  929. bgmac->int_status = int_status;
  930. napi_schedule(&bgmac->napi);
  931. return IRQ_HANDLED;
  932. }
  933. static int bgmac_poll(struct napi_struct *napi, int weight)
  934. {
  935. struct bgmac *bgmac = container_of(napi, struct bgmac, napi);
  936. struct bgmac_dma_ring *ring;
  937. int handled = 0;
  938. if (bgmac->int_status & BGMAC_IS_TX0) {
  939. ring = &bgmac->tx_ring[0];
  940. bgmac_dma_tx_free(bgmac, ring);
  941. bgmac->int_status &= ~BGMAC_IS_TX0;
  942. }
  943. if (bgmac->int_status & BGMAC_IS_RX) {
  944. ring = &bgmac->rx_ring[0];
  945. handled += bgmac_dma_rx_read(bgmac, ring, weight);
  946. bgmac->int_status &= ~BGMAC_IS_RX;
  947. }
  948. if (bgmac->int_status) {
  949. bgmac_err(bgmac, "Unknown IRQs: 0x%08X\n", bgmac->int_status);
  950. bgmac->int_status = 0;
  951. }
  952. if (handled < weight)
  953. napi_complete(napi);
  954. bgmac_chip_intrs_on(bgmac);
  955. return handled;
  956. }
  957. /**************************************************
  958. * net_device_ops
  959. **************************************************/
  960. static int bgmac_open(struct net_device *net_dev)
  961. {
  962. struct bgmac *bgmac = netdev_priv(net_dev);
  963. int err = 0;
  964. bgmac_chip_reset(bgmac);
  965. /* Specs say about reclaiming rings here, but we do that in DMA init */
  966. bgmac_chip_init(bgmac, true);
  967. err = request_irq(bgmac->core->irq, bgmac_interrupt, IRQF_SHARED,
  968. KBUILD_MODNAME, net_dev);
  969. if (err < 0) {
  970. bgmac_err(bgmac, "IRQ request error: %d!\n", err);
  971. goto err_out;
  972. }
  973. napi_enable(&bgmac->napi);
  974. netif_carrier_on(net_dev);
  975. err_out:
  976. return err;
  977. }
  978. static int bgmac_stop(struct net_device *net_dev)
  979. {
  980. struct bgmac *bgmac = netdev_priv(net_dev);
  981. netif_carrier_off(net_dev);
  982. napi_disable(&bgmac->napi);
  983. bgmac_chip_intrs_off(bgmac);
  984. free_irq(bgmac->core->irq, net_dev);
  985. bgmac_chip_reset(bgmac);
  986. return 0;
  987. }
  988. static netdev_tx_t bgmac_start_xmit(struct sk_buff *skb,
  989. struct net_device *net_dev)
  990. {
  991. struct bgmac *bgmac = netdev_priv(net_dev);
  992. struct bgmac_dma_ring *ring;
  993. /* No QOS support yet */
  994. ring = &bgmac->tx_ring[0];
  995. return bgmac_dma_tx_add(bgmac, ring, skb);
  996. }
  997. static int bgmac_set_mac_address(struct net_device *net_dev, void *addr)
  998. {
  999. struct bgmac *bgmac = netdev_priv(net_dev);
  1000. int ret;
  1001. ret = eth_prepare_mac_addr_change(net_dev, addr);
  1002. if (ret < 0)
  1003. return ret;
  1004. bgmac_write_mac_address(bgmac, (u8 *)addr);
  1005. eth_commit_mac_addr_change(net_dev, addr);
  1006. return 0;
  1007. }
  1008. static int bgmac_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd)
  1009. {
  1010. struct bgmac *bgmac = netdev_priv(net_dev);
  1011. struct mii_ioctl_data *data = if_mii(ifr);
  1012. switch (cmd) {
  1013. case SIOCGMIIPHY:
  1014. data->phy_id = bgmac->phyaddr;
  1015. /* fallthru */
  1016. case SIOCGMIIREG:
  1017. if (!netif_running(net_dev))
  1018. return -EAGAIN;
  1019. data->val_out = bgmac_phy_read(bgmac, data->phy_id,
  1020. data->reg_num & 0x1f);
  1021. return 0;
  1022. case SIOCSMIIREG:
  1023. if (!netif_running(net_dev))
  1024. return -EAGAIN;
  1025. bgmac_phy_write(bgmac, data->phy_id, data->reg_num & 0x1f,
  1026. data->val_in);
  1027. return 0;
  1028. default:
  1029. return -EOPNOTSUPP;
  1030. }
  1031. }
  1032. static const struct net_device_ops bgmac_netdev_ops = {
  1033. .ndo_open = bgmac_open,
  1034. .ndo_stop = bgmac_stop,
  1035. .ndo_start_xmit = bgmac_start_xmit,
  1036. .ndo_set_rx_mode = bgmac_set_rx_mode,
  1037. .ndo_set_mac_address = bgmac_set_mac_address,
  1038. .ndo_validate_addr = eth_validate_addr,
  1039. .ndo_do_ioctl = bgmac_ioctl,
  1040. };
  1041. /**************************************************
  1042. * ethtool_ops
  1043. **************************************************/
  1044. static int bgmac_get_settings(struct net_device *net_dev,
  1045. struct ethtool_cmd *cmd)
  1046. {
  1047. struct bgmac *bgmac = netdev_priv(net_dev);
  1048. cmd->supported = SUPPORTED_10baseT_Half |
  1049. SUPPORTED_10baseT_Full |
  1050. SUPPORTED_100baseT_Half |
  1051. SUPPORTED_100baseT_Full |
  1052. SUPPORTED_1000baseT_Half |
  1053. SUPPORTED_1000baseT_Full |
  1054. SUPPORTED_Autoneg;
  1055. if (bgmac->autoneg) {
  1056. WARN_ON(cmd->advertising);
  1057. if (bgmac->full_duplex) {
  1058. if (bgmac->speed & BGMAC_SPEED_10)
  1059. cmd->advertising |= ADVERTISED_10baseT_Full;
  1060. if (bgmac->speed & BGMAC_SPEED_100)
  1061. cmd->advertising |= ADVERTISED_100baseT_Full;
  1062. if (bgmac->speed & BGMAC_SPEED_1000)
  1063. cmd->advertising |= ADVERTISED_1000baseT_Full;
  1064. } else {
  1065. if (bgmac->speed & BGMAC_SPEED_10)
  1066. cmd->advertising |= ADVERTISED_10baseT_Half;
  1067. if (bgmac->speed & BGMAC_SPEED_100)
  1068. cmd->advertising |= ADVERTISED_100baseT_Half;
  1069. if (bgmac->speed & BGMAC_SPEED_1000)
  1070. cmd->advertising |= ADVERTISED_1000baseT_Half;
  1071. }
  1072. } else {
  1073. switch (bgmac->speed) {
  1074. case BGMAC_SPEED_10:
  1075. ethtool_cmd_speed_set(cmd, SPEED_10);
  1076. break;
  1077. case BGMAC_SPEED_100:
  1078. ethtool_cmd_speed_set(cmd, SPEED_100);
  1079. break;
  1080. case BGMAC_SPEED_1000:
  1081. ethtool_cmd_speed_set(cmd, SPEED_1000);
  1082. break;
  1083. }
  1084. }
  1085. cmd->duplex = bgmac->full_duplex ? DUPLEX_FULL : DUPLEX_HALF;
  1086. cmd->autoneg = bgmac->autoneg;
  1087. return 0;
  1088. }
  1089. #if 0
  1090. static int bgmac_set_settings(struct net_device *net_dev,
  1091. struct ethtool_cmd *cmd)
  1092. {
  1093. struct bgmac *bgmac = netdev_priv(net_dev);
  1094. return -1;
  1095. }
  1096. #endif
  1097. static void bgmac_get_drvinfo(struct net_device *net_dev,
  1098. struct ethtool_drvinfo *info)
  1099. {
  1100. strlcpy(info->driver, KBUILD_MODNAME, sizeof(info->driver));
  1101. strlcpy(info->bus_info, "BCMA", sizeof(info->bus_info));
  1102. }
  1103. static const struct ethtool_ops bgmac_ethtool_ops = {
  1104. .get_settings = bgmac_get_settings,
  1105. .get_drvinfo = bgmac_get_drvinfo,
  1106. };
  1107. /**************************************************
  1108. * MII
  1109. **************************************************/
  1110. static int bgmac_mii_read(struct mii_bus *bus, int mii_id, int regnum)
  1111. {
  1112. return bgmac_phy_read(bus->priv, mii_id, regnum);
  1113. }
  1114. static int bgmac_mii_write(struct mii_bus *bus, int mii_id, int regnum,
  1115. u16 value)
  1116. {
  1117. return bgmac_phy_write(bus->priv, mii_id, regnum, value);
  1118. }
  1119. static int bgmac_mii_register(struct bgmac *bgmac)
  1120. {
  1121. struct mii_bus *mii_bus;
  1122. int i, err = 0;
  1123. mii_bus = mdiobus_alloc();
  1124. if (!mii_bus)
  1125. return -ENOMEM;
  1126. mii_bus->name = "bgmac mii bus";
  1127. sprintf(mii_bus->id, "%s-%d-%d", "bgmac", bgmac->core->bus->num,
  1128. bgmac->core->core_unit);
  1129. mii_bus->priv = bgmac;
  1130. mii_bus->read = bgmac_mii_read;
  1131. mii_bus->write = bgmac_mii_write;
  1132. mii_bus->parent = &bgmac->core->dev;
  1133. mii_bus->phy_mask = ~(1 << bgmac->phyaddr);
  1134. mii_bus->irq = kmalloc_array(PHY_MAX_ADDR, sizeof(int), GFP_KERNEL);
  1135. if (!mii_bus->irq) {
  1136. err = -ENOMEM;
  1137. goto err_free_bus;
  1138. }
  1139. for (i = 0; i < PHY_MAX_ADDR; i++)
  1140. mii_bus->irq[i] = PHY_POLL;
  1141. err = mdiobus_register(mii_bus);
  1142. if (err) {
  1143. bgmac_err(bgmac, "Registration of mii bus failed\n");
  1144. goto err_free_irq;
  1145. }
  1146. bgmac->mii_bus = mii_bus;
  1147. return err;
  1148. err_free_irq:
  1149. kfree(mii_bus->irq);
  1150. err_free_bus:
  1151. mdiobus_free(mii_bus);
  1152. return err;
  1153. }
  1154. static void bgmac_mii_unregister(struct bgmac *bgmac)
  1155. {
  1156. struct mii_bus *mii_bus = bgmac->mii_bus;
  1157. mdiobus_unregister(mii_bus);
  1158. kfree(mii_bus->irq);
  1159. mdiobus_free(mii_bus);
  1160. }
  1161. /**************************************************
  1162. * BCMA bus ops
  1163. **************************************************/
  1164. /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipattach */
  1165. static int bgmac_probe(struct bcma_device *core)
  1166. {
  1167. struct net_device *net_dev;
  1168. struct bgmac *bgmac;
  1169. struct ssb_sprom *sprom = &core->bus->sprom;
  1170. u8 *mac = core->core_unit ? sprom->et1mac : sprom->et0mac;
  1171. int err;
  1172. /* We don't support 2nd, 3rd, ... units, SPROM has to be adjusted */
  1173. if (core->core_unit > 1) {
  1174. pr_err("Unsupported core_unit %d\n", core->core_unit);
  1175. return -ENOTSUPP;
  1176. }
  1177. if (!is_valid_ether_addr(mac)) {
  1178. dev_err(&core->dev, "Invalid MAC addr: %pM\n", mac);
  1179. eth_random_addr(mac);
  1180. dev_warn(&core->dev, "Using random MAC: %pM\n", mac);
  1181. }
  1182. /* Allocation and references */
  1183. net_dev = alloc_etherdev(sizeof(*bgmac));
  1184. if (!net_dev)
  1185. return -ENOMEM;
  1186. net_dev->netdev_ops = &bgmac_netdev_ops;
  1187. net_dev->irq = core->irq;
  1188. SET_ETHTOOL_OPS(net_dev, &bgmac_ethtool_ops);
  1189. bgmac = netdev_priv(net_dev);
  1190. bgmac->net_dev = net_dev;
  1191. bgmac->core = core;
  1192. bcma_set_drvdata(core, bgmac);
  1193. /* Defaults */
  1194. bgmac->autoneg = true;
  1195. bgmac->full_duplex = true;
  1196. bgmac->speed = BGMAC_SPEED_10 | BGMAC_SPEED_100 | BGMAC_SPEED_1000;
  1197. memcpy(bgmac->net_dev->dev_addr, mac, ETH_ALEN);
  1198. /* On BCM4706 we need common core to access PHY */
  1199. if (core->id.id == BCMA_CORE_4706_MAC_GBIT &&
  1200. !core->bus->drv_gmac_cmn.core) {
  1201. bgmac_err(bgmac, "GMAC CMN core not found (required for BCM4706)\n");
  1202. err = -ENODEV;
  1203. goto err_netdev_free;
  1204. }
  1205. bgmac->cmn = core->bus->drv_gmac_cmn.core;
  1206. bgmac->phyaddr = core->core_unit ? sprom->et1phyaddr :
  1207. sprom->et0phyaddr;
  1208. bgmac->phyaddr &= BGMAC_PHY_MASK;
  1209. if (bgmac->phyaddr == BGMAC_PHY_MASK) {
  1210. bgmac_err(bgmac, "No PHY found\n");
  1211. err = -ENODEV;
  1212. goto err_netdev_free;
  1213. }
  1214. bgmac_info(bgmac, "Found PHY addr: %d%s\n", bgmac->phyaddr,
  1215. bgmac->phyaddr == BGMAC_PHY_NOREGS ? " (NOREGS)" : "");
  1216. if (core->bus->hosttype == BCMA_HOSTTYPE_PCI) {
  1217. bgmac_err(bgmac, "PCI setup not implemented\n");
  1218. err = -ENOTSUPP;
  1219. goto err_netdev_free;
  1220. }
  1221. bgmac_chip_reset(bgmac);
  1222. err = bgmac_dma_alloc(bgmac);
  1223. if (err) {
  1224. bgmac_err(bgmac, "Unable to alloc memory for DMA\n");
  1225. goto err_netdev_free;
  1226. }
  1227. bgmac->int_mask = BGMAC_IS_ERRMASK | BGMAC_IS_RX | BGMAC_IS_TX_MASK;
  1228. if (bcm47xx_nvram_getenv("et0_no_txint", NULL, 0) == 0)
  1229. bgmac->int_mask &= ~BGMAC_IS_TX_MASK;
  1230. /* TODO: reset the external phy. Specs are needed */
  1231. bgmac_phy_reset(bgmac);
  1232. bgmac->has_robosw = !!(core->bus->sprom.boardflags_lo &
  1233. BGMAC_BFL_ENETROBO);
  1234. if (bgmac->has_robosw)
  1235. bgmac_warn(bgmac, "Support for Roboswitch not implemented\n");
  1236. if (core->bus->sprom.boardflags_lo & BGMAC_BFL_ENETADM)
  1237. bgmac_warn(bgmac, "Support for ADMtek ethernet switch not implemented\n");
  1238. err = bgmac_mii_register(bgmac);
  1239. if (err) {
  1240. bgmac_err(bgmac, "Cannot register MDIO\n");
  1241. err = -ENOTSUPP;
  1242. goto err_dma_free;
  1243. }
  1244. err = register_netdev(bgmac->net_dev);
  1245. if (err) {
  1246. bgmac_err(bgmac, "Cannot register net device\n");
  1247. err = -ENOTSUPP;
  1248. goto err_mii_unregister;
  1249. }
  1250. netif_carrier_off(net_dev);
  1251. netif_napi_add(net_dev, &bgmac->napi, bgmac_poll, BGMAC_WEIGHT);
  1252. return 0;
  1253. err_mii_unregister:
  1254. bgmac_mii_unregister(bgmac);
  1255. err_dma_free:
  1256. bgmac_dma_free(bgmac);
  1257. err_netdev_free:
  1258. bcma_set_drvdata(core, NULL);
  1259. free_netdev(net_dev);
  1260. return err;
  1261. }
  1262. static void bgmac_remove(struct bcma_device *core)
  1263. {
  1264. struct bgmac *bgmac = bcma_get_drvdata(core);
  1265. netif_napi_del(&bgmac->napi);
  1266. unregister_netdev(bgmac->net_dev);
  1267. bgmac_mii_unregister(bgmac);
  1268. bgmac_dma_free(bgmac);
  1269. bcma_set_drvdata(core, NULL);
  1270. free_netdev(bgmac->net_dev);
  1271. }
  1272. static struct bcma_driver bgmac_bcma_driver = {
  1273. .name = KBUILD_MODNAME,
  1274. .id_table = bgmac_bcma_tbl,
  1275. .probe = bgmac_probe,
  1276. .remove = bgmac_remove,
  1277. };
  1278. static int __init bgmac_init(void)
  1279. {
  1280. int err;
  1281. err = bcma_driver_register(&bgmac_bcma_driver);
  1282. if (err)
  1283. return err;
  1284. pr_info("Broadcom 47xx GBit MAC driver loaded\n");
  1285. return 0;
  1286. }
  1287. static void __exit bgmac_exit(void)
  1288. {
  1289. bcma_driver_unregister(&bgmac_bcma_driver);
  1290. }
  1291. module_init(bgmac_init)
  1292. module_exit(bgmac_exit)
  1293. MODULE_AUTHOR("Rafał Miłecki");
  1294. MODULE_LICENSE("GPL");