cputable.c 40 KB

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  1. /*
  2. * Copyright (C) 2001 Ben. Herrenschmidt (benh@kernel.crashing.org)
  3. *
  4. * Modifications for ppc64:
  5. * Copyright (C) 2003 Dave Engebretsen <engebret@us.ibm.com>
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License
  9. * as published by the Free Software Foundation; either version
  10. * 2 of the License, or (at your option) any later version.
  11. */
  12. #include <linux/string.h>
  13. #include <linux/sched.h>
  14. #include <linux/threads.h>
  15. #include <linux/init.h>
  16. #include <linux/module.h>
  17. #include <asm/oprofile_impl.h>
  18. #include <asm/cputable.h>
  19. #include <asm/prom.h> /* for PTRRELOC on ARCH=ppc */
  20. struct cpu_spec* cur_cpu_spec = NULL;
  21. EXPORT_SYMBOL(cur_cpu_spec);
  22. /* NOTE:
  23. * Unlike ppc32, ppc64 will only call this once for the boot CPU, it's
  24. * the responsibility of the appropriate CPU save/restore functions to
  25. * eventually copy these settings over. Those save/restore aren't yet
  26. * part of the cputable though. That has to be fixed for both ppc32
  27. * and ppc64
  28. */
  29. #ifdef CONFIG_PPC32
  30. extern void __setup_cpu_440ep(unsigned long offset, struct cpu_spec* spec);
  31. extern void __setup_cpu_440epx(unsigned long offset, struct cpu_spec* spec);
  32. extern void __setup_cpu_440grx(unsigned long offset, struct cpu_spec* spec);
  33. extern void __setup_cpu_603(unsigned long offset, struct cpu_spec* spec);
  34. extern void __setup_cpu_604(unsigned long offset, struct cpu_spec* spec);
  35. extern void __setup_cpu_750(unsigned long offset, struct cpu_spec* spec);
  36. extern void __setup_cpu_750cx(unsigned long offset, struct cpu_spec* spec);
  37. extern void __setup_cpu_750fx(unsigned long offset, struct cpu_spec* spec);
  38. extern void __setup_cpu_7400(unsigned long offset, struct cpu_spec* spec);
  39. extern void __setup_cpu_7410(unsigned long offset, struct cpu_spec* spec);
  40. extern void __setup_cpu_745x(unsigned long offset, struct cpu_spec* spec);
  41. #endif /* CONFIG_PPC32 */
  42. #ifdef CONFIG_PPC64
  43. extern void __setup_cpu_ppc970(unsigned long offset, struct cpu_spec* spec);
  44. extern void __setup_cpu_ppc970MP(unsigned long offset, struct cpu_spec* spec);
  45. extern void __setup_cpu_pa6t(unsigned long offset, struct cpu_spec* spec);
  46. extern void __restore_cpu_pa6t(void);
  47. extern void __restore_cpu_ppc970(void);
  48. #endif /* CONFIG_PPC64 */
  49. /* This table only contains "desktop" CPUs, it need to be filled with embedded
  50. * ones as well...
  51. */
  52. #define COMMON_USER (PPC_FEATURE_32 | PPC_FEATURE_HAS_FPU | \
  53. PPC_FEATURE_HAS_MMU)
  54. #define COMMON_USER_PPC64 (COMMON_USER | PPC_FEATURE_64)
  55. #define COMMON_USER_POWER4 (COMMON_USER_PPC64 | PPC_FEATURE_POWER4)
  56. #define COMMON_USER_POWER5 (COMMON_USER_PPC64 | PPC_FEATURE_POWER5 |\
  57. PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP)
  58. #define COMMON_USER_POWER5_PLUS (COMMON_USER_PPC64 | PPC_FEATURE_POWER5_PLUS|\
  59. PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP)
  60. #define COMMON_USER_POWER6 (COMMON_USER_PPC64 | PPC_FEATURE_ARCH_2_05 |\
  61. PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP | \
  62. PPC_FEATURE_TRUE_LE)
  63. #define COMMON_USER_PA6T (COMMON_USER_PPC64 | PPC_FEATURE_PA6T |\
  64. PPC_FEATURE_TRUE_LE | \
  65. PPC_FEATURE_HAS_ALTIVEC_COMP)
  66. #define COMMON_USER_BOOKE (PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | \
  67. PPC_FEATURE_BOOKE)
  68. static struct cpu_spec __initdata cpu_specs[] = {
  69. #ifdef CONFIG_PPC64
  70. { /* Power3 */
  71. .pvr_mask = 0xffff0000,
  72. .pvr_value = 0x00400000,
  73. .cpu_name = "POWER3 (630)",
  74. .cpu_features = CPU_FTRS_POWER3,
  75. .cpu_user_features = COMMON_USER_PPC64|PPC_FEATURE_PPC_LE,
  76. .icache_bsize = 128,
  77. .dcache_bsize = 128,
  78. .num_pmcs = 8,
  79. .pmc_type = PPC_PMC_IBM,
  80. .oprofile_cpu_type = "ppc64/power3",
  81. .oprofile_type = PPC_OPROFILE_RS64,
  82. .platform = "power3",
  83. },
  84. { /* Power3+ */
  85. .pvr_mask = 0xffff0000,
  86. .pvr_value = 0x00410000,
  87. .cpu_name = "POWER3 (630+)",
  88. .cpu_features = CPU_FTRS_POWER3,
  89. .cpu_user_features = COMMON_USER_PPC64|PPC_FEATURE_PPC_LE,
  90. .icache_bsize = 128,
  91. .dcache_bsize = 128,
  92. .num_pmcs = 8,
  93. .pmc_type = PPC_PMC_IBM,
  94. .oprofile_cpu_type = "ppc64/power3",
  95. .oprofile_type = PPC_OPROFILE_RS64,
  96. .platform = "power3",
  97. },
  98. { /* Northstar */
  99. .pvr_mask = 0xffff0000,
  100. .pvr_value = 0x00330000,
  101. .cpu_name = "RS64-II (northstar)",
  102. .cpu_features = CPU_FTRS_RS64,
  103. .cpu_user_features = COMMON_USER_PPC64,
  104. .icache_bsize = 128,
  105. .dcache_bsize = 128,
  106. .num_pmcs = 8,
  107. .pmc_type = PPC_PMC_IBM,
  108. .oprofile_cpu_type = "ppc64/rs64",
  109. .oprofile_type = PPC_OPROFILE_RS64,
  110. .platform = "rs64",
  111. },
  112. { /* Pulsar */
  113. .pvr_mask = 0xffff0000,
  114. .pvr_value = 0x00340000,
  115. .cpu_name = "RS64-III (pulsar)",
  116. .cpu_features = CPU_FTRS_RS64,
  117. .cpu_user_features = COMMON_USER_PPC64,
  118. .icache_bsize = 128,
  119. .dcache_bsize = 128,
  120. .num_pmcs = 8,
  121. .pmc_type = PPC_PMC_IBM,
  122. .oprofile_cpu_type = "ppc64/rs64",
  123. .oprofile_type = PPC_OPROFILE_RS64,
  124. .platform = "rs64",
  125. },
  126. { /* I-star */
  127. .pvr_mask = 0xffff0000,
  128. .pvr_value = 0x00360000,
  129. .cpu_name = "RS64-III (icestar)",
  130. .cpu_features = CPU_FTRS_RS64,
  131. .cpu_user_features = COMMON_USER_PPC64,
  132. .icache_bsize = 128,
  133. .dcache_bsize = 128,
  134. .num_pmcs = 8,
  135. .pmc_type = PPC_PMC_IBM,
  136. .oprofile_cpu_type = "ppc64/rs64",
  137. .oprofile_type = PPC_OPROFILE_RS64,
  138. .platform = "rs64",
  139. },
  140. { /* S-star */
  141. .pvr_mask = 0xffff0000,
  142. .pvr_value = 0x00370000,
  143. .cpu_name = "RS64-IV (sstar)",
  144. .cpu_features = CPU_FTRS_RS64,
  145. .cpu_user_features = COMMON_USER_PPC64,
  146. .icache_bsize = 128,
  147. .dcache_bsize = 128,
  148. .num_pmcs = 8,
  149. .pmc_type = PPC_PMC_IBM,
  150. .oprofile_cpu_type = "ppc64/rs64",
  151. .oprofile_type = PPC_OPROFILE_RS64,
  152. .platform = "rs64",
  153. },
  154. { /* Power4 */
  155. .pvr_mask = 0xffff0000,
  156. .pvr_value = 0x00350000,
  157. .cpu_name = "POWER4 (gp)",
  158. .cpu_features = CPU_FTRS_POWER4,
  159. .cpu_user_features = COMMON_USER_POWER4,
  160. .icache_bsize = 128,
  161. .dcache_bsize = 128,
  162. .num_pmcs = 8,
  163. .pmc_type = PPC_PMC_IBM,
  164. .oprofile_cpu_type = "ppc64/power4",
  165. .oprofile_type = PPC_OPROFILE_POWER4,
  166. .platform = "power4",
  167. },
  168. { /* Power4+ */
  169. .pvr_mask = 0xffff0000,
  170. .pvr_value = 0x00380000,
  171. .cpu_name = "POWER4+ (gq)",
  172. .cpu_features = CPU_FTRS_POWER4,
  173. .cpu_user_features = COMMON_USER_POWER4,
  174. .icache_bsize = 128,
  175. .dcache_bsize = 128,
  176. .num_pmcs = 8,
  177. .pmc_type = PPC_PMC_IBM,
  178. .oprofile_cpu_type = "ppc64/power4",
  179. .oprofile_type = PPC_OPROFILE_POWER4,
  180. .platform = "power4",
  181. },
  182. { /* PPC970 */
  183. .pvr_mask = 0xffff0000,
  184. .pvr_value = 0x00390000,
  185. .cpu_name = "PPC970",
  186. .cpu_features = CPU_FTRS_PPC970,
  187. .cpu_user_features = COMMON_USER_POWER4 |
  188. PPC_FEATURE_HAS_ALTIVEC_COMP,
  189. .icache_bsize = 128,
  190. .dcache_bsize = 128,
  191. .num_pmcs = 8,
  192. .pmc_type = PPC_PMC_IBM,
  193. .cpu_setup = __setup_cpu_ppc970,
  194. .cpu_restore = __restore_cpu_ppc970,
  195. .oprofile_cpu_type = "ppc64/970",
  196. .oprofile_type = PPC_OPROFILE_POWER4,
  197. .platform = "ppc970",
  198. },
  199. { /* PPC970FX */
  200. .pvr_mask = 0xffff0000,
  201. .pvr_value = 0x003c0000,
  202. .cpu_name = "PPC970FX",
  203. .cpu_features = CPU_FTRS_PPC970,
  204. .cpu_user_features = COMMON_USER_POWER4 |
  205. PPC_FEATURE_HAS_ALTIVEC_COMP,
  206. .icache_bsize = 128,
  207. .dcache_bsize = 128,
  208. .num_pmcs = 8,
  209. .pmc_type = PPC_PMC_IBM,
  210. .cpu_setup = __setup_cpu_ppc970,
  211. .cpu_restore = __restore_cpu_ppc970,
  212. .oprofile_cpu_type = "ppc64/970",
  213. .oprofile_type = PPC_OPROFILE_POWER4,
  214. .platform = "ppc970",
  215. },
  216. { /* PPC970MP DD1.0 - no DEEPNAP, use regular 970 init */
  217. .pvr_mask = 0xffffffff,
  218. .pvr_value = 0x00440100,
  219. .cpu_name = "PPC970MP",
  220. .cpu_features = CPU_FTRS_PPC970,
  221. .cpu_user_features = COMMON_USER_POWER4 |
  222. PPC_FEATURE_HAS_ALTIVEC_COMP,
  223. .icache_bsize = 128,
  224. .dcache_bsize = 128,
  225. .num_pmcs = 8,
  226. .pmc_type = PPC_PMC_IBM,
  227. .cpu_setup = __setup_cpu_ppc970,
  228. .cpu_restore = __restore_cpu_ppc970,
  229. .oprofile_cpu_type = "ppc64/970MP",
  230. .oprofile_type = PPC_OPROFILE_POWER4,
  231. .platform = "ppc970",
  232. },
  233. { /* PPC970MP */
  234. .pvr_mask = 0xffff0000,
  235. .pvr_value = 0x00440000,
  236. .cpu_name = "PPC970MP",
  237. .cpu_features = CPU_FTRS_PPC970,
  238. .cpu_user_features = COMMON_USER_POWER4 |
  239. PPC_FEATURE_HAS_ALTIVEC_COMP,
  240. .icache_bsize = 128,
  241. .dcache_bsize = 128,
  242. .num_pmcs = 8,
  243. .pmc_type = PPC_PMC_IBM,
  244. .cpu_setup = __setup_cpu_ppc970MP,
  245. .cpu_restore = __restore_cpu_ppc970,
  246. .oprofile_cpu_type = "ppc64/970MP",
  247. .oprofile_type = PPC_OPROFILE_POWER4,
  248. .platform = "ppc970",
  249. },
  250. { /* PPC970GX */
  251. .pvr_mask = 0xffff0000,
  252. .pvr_value = 0x00450000,
  253. .cpu_name = "PPC970GX",
  254. .cpu_features = CPU_FTRS_PPC970,
  255. .cpu_user_features = COMMON_USER_POWER4 |
  256. PPC_FEATURE_HAS_ALTIVEC_COMP,
  257. .icache_bsize = 128,
  258. .dcache_bsize = 128,
  259. .num_pmcs = 8,
  260. .pmc_type = PPC_PMC_IBM,
  261. .cpu_setup = __setup_cpu_ppc970,
  262. .oprofile_cpu_type = "ppc64/970",
  263. .oprofile_type = PPC_OPROFILE_POWER4,
  264. .platform = "ppc970",
  265. },
  266. { /* Power5 GR */
  267. .pvr_mask = 0xffff0000,
  268. .pvr_value = 0x003a0000,
  269. .cpu_name = "POWER5 (gr)",
  270. .cpu_features = CPU_FTRS_POWER5,
  271. .cpu_user_features = COMMON_USER_POWER5,
  272. .icache_bsize = 128,
  273. .dcache_bsize = 128,
  274. .num_pmcs = 6,
  275. .pmc_type = PPC_PMC_IBM,
  276. .oprofile_cpu_type = "ppc64/power5",
  277. .oprofile_type = PPC_OPROFILE_POWER4,
  278. /* SIHV / SIPR bits are implemented on POWER4+ (GQ)
  279. * and above but only works on POWER5 and above
  280. */
  281. .oprofile_mmcra_sihv = MMCRA_SIHV,
  282. .oprofile_mmcra_sipr = MMCRA_SIPR,
  283. .platform = "power5",
  284. },
  285. { /* Power5++ */
  286. .pvr_mask = 0xffffff00,
  287. .pvr_value = 0x003b0300,
  288. .cpu_name = "POWER5+ (gs)",
  289. .cpu_features = CPU_FTRS_POWER5,
  290. .cpu_user_features = COMMON_USER_POWER5_PLUS,
  291. .icache_bsize = 128,
  292. .dcache_bsize = 128,
  293. .num_pmcs = 6,
  294. .oprofile_cpu_type = "ppc64/power5++",
  295. .oprofile_type = PPC_OPROFILE_POWER4,
  296. .oprofile_mmcra_sihv = MMCRA_SIHV,
  297. .oprofile_mmcra_sipr = MMCRA_SIPR,
  298. .platform = "power5+",
  299. },
  300. { /* Power5 GS */
  301. .pvr_mask = 0xffff0000,
  302. .pvr_value = 0x003b0000,
  303. .cpu_name = "POWER5+ (gs)",
  304. .cpu_features = CPU_FTRS_POWER5,
  305. .cpu_user_features = COMMON_USER_POWER5_PLUS,
  306. .icache_bsize = 128,
  307. .dcache_bsize = 128,
  308. .num_pmcs = 6,
  309. .pmc_type = PPC_PMC_IBM,
  310. .oprofile_cpu_type = "ppc64/power5+",
  311. .oprofile_type = PPC_OPROFILE_POWER4,
  312. .oprofile_mmcra_sihv = MMCRA_SIHV,
  313. .oprofile_mmcra_sipr = MMCRA_SIPR,
  314. .platform = "power5+",
  315. },
  316. { /* POWER6 in P5+ mode; 2.04-compliant processor */
  317. .pvr_mask = 0xffffffff,
  318. .pvr_value = 0x0f000001,
  319. .cpu_name = "POWER5+",
  320. .cpu_features = CPU_FTRS_POWER5,
  321. .cpu_user_features = COMMON_USER_POWER5_PLUS,
  322. .icache_bsize = 128,
  323. .dcache_bsize = 128,
  324. .platform = "power5+",
  325. },
  326. { /* Power6 */
  327. .pvr_mask = 0xffff0000,
  328. .pvr_value = 0x003e0000,
  329. .cpu_name = "POWER6 (raw)",
  330. .cpu_features = CPU_FTRS_POWER6,
  331. .cpu_user_features = COMMON_USER_POWER6 |
  332. PPC_FEATURE_POWER6_EXT,
  333. .icache_bsize = 128,
  334. .dcache_bsize = 128,
  335. .num_pmcs = 6,
  336. .pmc_type = PPC_PMC_IBM,
  337. .oprofile_cpu_type = "ppc64/power6",
  338. .oprofile_type = PPC_OPROFILE_POWER4,
  339. .oprofile_mmcra_sihv = POWER6_MMCRA_SIHV,
  340. .oprofile_mmcra_sipr = POWER6_MMCRA_SIPR,
  341. .oprofile_mmcra_clear = POWER6_MMCRA_THRM |
  342. POWER6_MMCRA_OTHER,
  343. .platform = "power6x",
  344. },
  345. { /* 2.05-compliant processor, i.e. Power6 "architected" mode */
  346. .pvr_mask = 0xffffffff,
  347. .pvr_value = 0x0f000002,
  348. .cpu_name = "POWER6 (architected)",
  349. .cpu_features = CPU_FTRS_POWER6,
  350. .cpu_user_features = COMMON_USER_POWER6,
  351. .icache_bsize = 128,
  352. .dcache_bsize = 128,
  353. .platform = "power6",
  354. },
  355. { /* Cell Broadband Engine */
  356. .pvr_mask = 0xffff0000,
  357. .pvr_value = 0x00700000,
  358. .cpu_name = "Cell Broadband Engine",
  359. .cpu_features = CPU_FTRS_CELL,
  360. .cpu_user_features = COMMON_USER_PPC64 |
  361. PPC_FEATURE_CELL | PPC_FEATURE_HAS_ALTIVEC_COMP |
  362. PPC_FEATURE_SMT,
  363. .icache_bsize = 128,
  364. .dcache_bsize = 128,
  365. .num_pmcs = 4,
  366. .pmc_type = PPC_PMC_IBM,
  367. .oprofile_cpu_type = "ppc64/cell-be",
  368. .oprofile_type = PPC_OPROFILE_CELL,
  369. .platform = "ppc-cell-be",
  370. },
  371. { /* PA Semi PA6T */
  372. .pvr_mask = 0x7fff0000,
  373. .pvr_value = 0x00900000,
  374. .cpu_name = "PA6T",
  375. .cpu_features = CPU_FTRS_PA6T,
  376. .cpu_user_features = COMMON_USER_PA6T,
  377. .icache_bsize = 64,
  378. .dcache_bsize = 64,
  379. .num_pmcs = 6,
  380. .pmc_type = PPC_PMC_PA6T,
  381. .cpu_setup = __setup_cpu_pa6t,
  382. .cpu_restore = __restore_cpu_pa6t,
  383. .oprofile_cpu_type = "ppc64/pa6t",
  384. .oprofile_type = PPC_OPROFILE_PA6T,
  385. .platform = "pa6t",
  386. },
  387. { /* default match */
  388. .pvr_mask = 0x00000000,
  389. .pvr_value = 0x00000000,
  390. .cpu_name = "POWER4 (compatible)",
  391. .cpu_features = CPU_FTRS_COMPATIBLE,
  392. .cpu_user_features = COMMON_USER_PPC64,
  393. .icache_bsize = 128,
  394. .dcache_bsize = 128,
  395. .num_pmcs = 6,
  396. .pmc_type = PPC_PMC_IBM,
  397. .platform = "power4",
  398. }
  399. #endif /* CONFIG_PPC64 */
  400. #ifdef CONFIG_PPC32
  401. #if CLASSIC_PPC
  402. { /* 601 */
  403. .pvr_mask = 0xffff0000,
  404. .pvr_value = 0x00010000,
  405. .cpu_name = "601",
  406. .cpu_features = CPU_FTRS_PPC601,
  407. .cpu_user_features = COMMON_USER | PPC_FEATURE_601_INSTR |
  408. PPC_FEATURE_UNIFIED_CACHE | PPC_FEATURE_NO_TB,
  409. .icache_bsize = 32,
  410. .dcache_bsize = 32,
  411. .platform = "ppc601",
  412. },
  413. { /* 603 */
  414. .pvr_mask = 0xffff0000,
  415. .pvr_value = 0x00030000,
  416. .cpu_name = "603",
  417. .cpu_features = CPU_FTRS_603,
  418. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  419. .icache_bsize = 32,
  420. .dcache_bsize = 32,
  421. .cpu_setup = __setup_cpu_603,
  422. .platform = "ppc603",
  423. },
  424. { /* 603e */
  425. .pvr_mask = 0xffff0000,
  426. .pvr_value = 0x00060000,
  427. .cpu_name = "603e",
  428. .cpu_features = CPU_FTRS_603,
  429. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  430. .icache_bsize = 32,
  431. .dcache_bsize = 32,
  432. .cpu_setup = __setup_cpu_603,
  433. .platform = "ppc603",
  434. },
  435. { /* 603ev */
  436. .pvr_mask = 0xffff0000,
  437. .pvr_value = 0x00070000,
  438. .cpu_name = "603ev",
  439. .cpu_features = CPU_FTRS_603,
  440. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  441. .icache_bsize = 32,
  442. .dcache_bsize = 32,
  443. .cpu_setup = __setup_cpu_603,
  444. .platform = "ppc603",
  445. },
  446. { /* 604 */
  447. .pvr_mask = 0xffff0000,
  448. .pvr_value = 0x00040000,
  449. .cpu_name = "604",
  450. .cpu_features = CPU_FTRS_604,
  451. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  452. .icache_bsize = 32,
  453. .dcache_bsize = 32,
  454. .num_pmcs = 2,
  455. .cpu_setup = __setup_cpu_604,
  456. .platform = "ppc604",
  457. },
  458. { /* 604e */
  459. .pvr_mask = 0xfffff000,
  460. .pvr_value = 0x00090000,
  461. .cpu_name = "604e",
  462. .cpu_features = CPU_FTRS_604,
  463. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  464. .icache_bsize = 32,
  465. .dcache_bsize = 32,
  466. .num_pmcs = 4,
  467. .cpu_setup = __setup_cpu_604,
  468. .platform = "ppc604",
  469. },
  470. { /* 604r */
  471. .pvr_mask = 0xffff0000,
  472. .pvr_value = 0x00090000,
  473. .cpu_name = "604r",
  474. .cpu_features = CPU_FTRS_604,
  475. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  476. .icache_bsize = 32,
  477. .dcache_bsize = 32,
  478. .num_pmcs = 4,
  479. .cpu_setup = __setup_cpu_604,
  480. .platform = "ppc604",
  481. },
  482. { /* 604ev */
  483. .pvr_mask = 0xffff0000,
  484. .pvr_value = 0x000a0000,
  485. .cpu_name = "604ev",
  486. .cpu_features = CPU_FTRS_604,
  487. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  488. .icache_bsize = 32,
  489. .dcache_bsize = 32,
  490. .num_pmcs = 4,
  491. .cpu_setup = __setup_cpu_604,
  492. .platform = "ppc604",
  493. },
  494. { /* 740/750 (0x4202, don't support TAU ?) */
  495. .pvr_mask = 0xffffffff,
  496. .pvr_value = 0x00084202,
  497. .cpu_name = "740/750",
  498. .cpu_features = CPU_FTRS_740_NOTAU,
  499. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  500. .icache_bsize = 32,
  501. .dcache_bsize = 32,
  502. .num_pmcs = 4,
  503. .cpu_setup = __setup_cpu_750,
  504. .platform = "ppc750",
  505. },
  506. { /* 750CX (80100 and 8010x?) */
  507. .pvr_mask = 0xfffffff0,
  508. .pvr_value = 0x00080100,
  509. .cpu_name = "750CX",
  510. .cpu_features = CPU_FTRS_750,
  511. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  512. .icache_bsize = 32,
  513. .dcache_bsize = 32,
  514. .num_pmcs = 4,
  515. .cpu_setup = __setup_cpu_750cx,
  516. .platform = "ppc750",
  517. },
  518. { /* 750CX (82201 and 82202) */
  519. .pvr_mask = 0xfffffff0,
  520. .pvr_value = 0x00082200,
  521. .cpu_name = "750CX",
  522. .cpu_features = CPU_FTRS_750,
  523. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  524. .icache_bsize = 32,
  525. .dcache_bsize = 32,
  526. .num_pmcs = 4,
  527. .cpu_setup = __setup_cpu_750cx,
  528. .platform = "ppc750",
  529. },
  530. { /* 750CXe (82214) */
  531. .pvr_mask = 0xfffffff0,
  532. .pvr_value = 0x00082210,
  533. .cpu_name = "750CXe",
  534. .cpu_features = CPU_FTRS_750,
  535. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  536. .icache_bsize = 32,
  537. .dcache_bsize = 32,
  538. .num_pmcs = 4,
  539. .cpu_setup = __setup_cpu_750cx,
  540. .platform = "ppc750",
  541. },
  542. { /* 750CXe "Gekko" (83214) */
  543. .pvr_mask = 0xffffffff,
  544. .pvr_value = 0x00083214,
  545. .cpu_name = "750CXe",
  546. .cpu_features = CPU_FTRS_750,
  547. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  548. .icache_bsize = 32,
  549. .dcache_bsize = 32,
  550. .num_pmcs = 4,
  551. .cpu_setup = __setup_cpu_750cx,
  552. .platform = "ppc750",
  553. },
  554. { /* 750CL */
  555. .pvr_mask = 0xfffff0f0,
  556. .pvr_value = 0x00087010,
  557. .cpu_name = "750CL",
  558. .cpu_features = CPU_FTRS_750CL,
  559. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  560. .icache_bsize = 32,
  561. .dcache_bsize = 32,
  562. .num_pmcs = 4,
  563. .cpu_setup = __setup_cpu_750,
  564. .platform = "ppc750",
  565. },
  566. { /* 745/755 */
  567. .pvr_mask = 0xfffff000,
  568. .pvr_value = 0x00083000,
  569. .cpu_name = "745/755",
  570. .cpu_features = CPU_FTRS_750,
  571. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  572. .icache_bsize = 32,
  573. .dcache_bsize = 32,
  574. .num_pmcs = 4,
  575. .cpu_setup = __setup_cpu_750,
  576. .platform = "ppc750",
  577. },
  578. { /* 750FX rev 1.x */
  579. .pvr_mask = 0xffffff00,
  580. .pvr_value = 0x70000100,
  581. .cpu_name = "750FX",
  582. .cpu_features = CPU_FTRS_750FX1,
  583. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  584. .icache_bsize = 32,
  585. .dcache_bsize = 32,
  586. .num_pmcs = 4,
  587. .cpu_setup = __setup_cpu_750,
  588. .platform = "ppc750",
  589. },
  590. { /* 750FX rev 2.0 must disable HID0[DPM] */
  591. .pvr_mask = 0xffffffff,
  592. .pvr_value = 0x70000200,
  593. .cpu_name = "750FX",
  594. .cpu_features = CPU_FTRS_750FX2,
  595. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  596. .icache_bsize = 32,
  597. .dcache_bsize = 32,
  598. .num_pmcs = 4,
  599. .cpu_setup = __setup_cpu_750,
  600. .platform = "ppc750",
  601. },
  602. { /* 750FX (All revs except 2.0) */
  603. .pvr_mask = 0xffff0000,
  604. .pvr_value = 0x70000000,
  605. .cpu_name = "750FX",
  606. .cpu_features = CPU_FTRS_750FX,
  607. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  608. .icache_bsize = 32,
  609. .dcache_bsize = 32,
  610. .num_pmcs = 4,
  611. .cpu_setup = __setup_cpu_750fx,
  612. .platform = "ppc750",
  613. },
  614. { /* 750GX */
  615. .pvr_mask = 0xffff0000,
  616. .pvr_value = 0x70020000,
  617. .cpu_name = "750GX",
  618. .cpu_features = CPU_FTRS_750GX,
  619. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  620. .icache_bsize = 32,
  621. .dcache_bsize = 32,
  622. .num_pmcs = 4,
  623. .cpu_setup = __setup_cpu_750fx,
  624. .platform = "ppc750",
  625. },
  626. { /* 740/750 (L2CR bit need fixup for 740) */
  627. .pvr_mask = 0xffff0000,
  628. .pvr_value = 0x00080000,
  629. .cpu_name = "740/750",
  630. .cpu_features = CPU_FTRS_740,
  631. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  632. .icache_bsize = 32,
  633. .dcache_bsize = 32,
  634. .num_pmcs = 4,
  635. .cpu_setup = __setup_cpu_750,
  636. .platform = "ppc750",
  637. },
  638. { /* 7400 rev 1.1 ? (no TAU) */
  639. .pvr_mask = 0xffffffff,
  640. .pvr_value = 0x000c1101,
  641. .cpu_name = "7400 (1.1)",
  642. .cpu_features = CPU_FTRS_7400_NOTAU,
  643. .cpu_user_features = COMMON_USER |
  644. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  645. .icache_bsize = 32,
  646. .dcache_bsize = 32,
  647. .num_pmcs = 4,
  648. .cpu_setup = __setup_cpu_7400,
  649. .platform = "ppc7400",
  650. },
  651. { /* 7400 */
  652. .pvr_mask = 0xffff0000,
  653. .pvr_value = 0x000c0000,
  654. .cpu_name = "7400",
  655. .cpu_features = CPU_FTRS_7400,
  656. .cpu_user_features = COMMON_USER |
  657. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  658. .icache_bsize = 32,
  659. .dcache_bsize = 32,
  660. .num_pmcs = 4,
  661. .cpu_setup = __setup_cpu_7400,
  662. .platform = "ppc7400",
  663. },
  664. { /* 7410 */
  665. .pvr_mask = 0xffff0000,
  666. .pvr_value = 0x800c0000,
  667. .cpu_name = "7410",
  668. .cpu_features = CPU_FTRS_7400,
  669. .cpu_user_features = COMMON_USER |
  670. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  671. .icache_bsize = 32,
  672. .dcache_bsize = 32,
  673. .num_pmcs = 4,
  674. .cpu_setup = __setup_cpu_7410,
  675. .platform = "ppc7400",
  676. },
  677. { /* 7450 2.0 - no doze/nap */
  678. .pvr_mask = 0xffffffff,
  679. .pvr_value = 0x80000200,
  680. .cpu_name = "7450",
  681. .cpu_features = CPU_FTRS_7450_20,
  682. .cpu_user_features = COMMON_USER |
  683. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  684. .icache_bsize = 32,
  685. .dcache_bsize = 32,
  686. .num_pmcs = 6,
  687. .cpu_setup = __setup_cpu_745x,
  688. .oprofile_cpu_type = "ppc/7450",
  689. .oprofile_type = PPC_OPROFILE_G4,
  690. .platform = "ppc7450",
  691. },
  692. { /* 7450 2.1 */
  693. .pvr_mask = 0xffffffff,
  694. .pvr_value = 0x80000201,
  695. .cpu_name = "7450",
  696. .cpu_features = CPU_FTRS_7450_21,
  697. .cpu_user_features = COMMON_USER |
  698. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  699. .icache_bsize = 32,
  700. .dcache_bsize = 32,
  701. .num_pmcs = 6,
  702. .cpu_setup = __setup_cpu_745x,
  703. .oprofile_cpu_type = "ppc/7450",
  704. .oprofile_type = PPC_OPROFILE_G4,
  705. .platform = "ppc7450",
  706. },
  707. { /* 7450 2.3 and newer */
  708. .pvr_mask = 0xffff0000,
  709. .pvr_value = 0x80000000,
  710. .cpu_name = "7450",
  711. .cpu_features = CPU_FTRS_7450_23,
  712. .cpu_user_features = COMMON_USER |
  713. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  714. .icache_bsize = 32,
  715. .dcache_bsize = 32,
  716. .num_pmcs = 6,
  717. .cpu_setup = __setup_cpu_745x,
  718. .oprofile_cpu_type = "ppc/7450",
  719. .oprofile_type = PPC_OPROFILE_G4,
  720. .platform = "ppc7450",
  721. },
  722. { /* 7455 rev 1.x */
  723. .pvr_mask = 0xffffff00,
  724. .pvr_value = 0x80010100,
  725. .cpu_name = "7455",
  726. .cpu_features = CPU_FTRS_7455_1,
  727. .cpu_user_features = COMMON_USER |
  728. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  729. .icache_bsize = 32,
  730. .dcache_bsize = 32,
  731. .num_pmcs = 6,
  732. .cpu_setup = __setup_cpu_745x,
  733. .oprofile_cpu_type = "ppc/7450",
  734. .oprofile_type = PPC_OPROFILE_G4,
  735. .platform = "ppc7450",
  736. },
  737. { /* 7455 rev 2.0 */
  738. .pvr_mask = 0xffffffff,
  739. .pvr_value = 0x80010200,
  740. .cpu_name = "7455",
  741. .cpu_features = CPU_FTRS_7455_20,
  742. .cpu_user_features = COMMON_USER |
  743. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  744. .icache_bsize = 32,
  745. .dcache_bsize = 32,
  746. .num_pmcs = 6,
  747. .cpu_setup = __setup_cpu_745x,
  748. .oprofile_cpu_type = "ppc/7450",
  749. .oprofile_type = PPC_OPROFILE_G4,
  750. .platform = "ppc7450",
  751. },
  752. { /* 7455 others */
  753. .pvr_mask = 0xffff0000,
  754. .pvr_value = 0x80010000,
  755. .cpu_name = "7455",
  756. .cpu_features = CPU_FTRS_7455,
  757. .cpu_user_features = COMMON_USER |
  758. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  759. .icache_bsize = 32,
  760. .dcache_bsize = 32,
  761. .num_pmcs = 6,
  762. .cpu_setup = __setup_cpu_745x,
  763. .oprofile_cpu_type = "ppc/7450",
  764. .oprofile_type = PPC_OPROFILE_G4,
  765. .platform = "ppc7450",
  766. },
  767. { /* 7447/7457 Rev 1.0 */
  768. .pvr_mask = 0xffffffff,
  769. .pvr_value = 0x80020100,
  770. .cpu_name = "7447/7457",
  771. .cpu_features = CPU_FTRS_7447_10,
  772. .cpu_user_features = COMMON_USER |
  773. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  774. .icache_bsize = 32,
  775. .dcache_bsize = 32,
  776. .num_pmcs = 6,
  777. .cpu_setup = __setup_cpu_745x,
  778. .oprofile_cpu_type = "ppc/7450",
  779. .oprofile_type = PPC_OPROFILE_G4,
  780. .platform = "ppc7450",
  781. },
  782. { /* 7447/7457 Rev 1.1 */
  783. .pvr_mask = 0xffffffff,
  784. .pvr_value = 0x80020101,
  785. .cpu_name = "7447/7457",
  786. .cpu_features = CPU_FTRS_7447_10,
  787. .cpu_user_features = COMMON_USER |
  788. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  789. .icache_bsize = 32,
  790. .dcache_bsize = 32,
  791. .num_pmcs = 6,
  792. .cpu_setup = __setup_cpu_745x,
  793. .oprofile_cpu_type = "ppc/7450",
  794. .oprofile_type = PPC_OPROFILE_G4,
  795. .platform = "ppc7450",
  796. },
  797. { /* 7447/7457 Rev 1.2 and later */
  798. .pvr_mask = 0xffff0000,
  799. .pvr_value = 0x80020000,
  800. .cpu_name = "7447/7457",
  801. .cpu_features = CPU_FTRS_7447,
  802. .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  803. .icache_bsize = 32,
  804. .dcache_bsize = 32,
  805. .num_pmcs = 6,
  806. .cpu_setup = __setup_cpu_745x,
  807. .oprofile_cpu_type = "ppc/7450",
  808. .oprofile_type = PPC_OPROFILE_G4,
  809. .platform = "ppc7450",
  810. },
  811. { /* 7447A */
  812. .pvr_mask = 0xffff0000,
  813. .pvr_value = 0x80030000,
  814. .cpu_name = "7447A",
  815. .cpu_features = CPU_FTRS_7447A,
  816. .cpu_user_features = COMMON_USER |
  817. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  818. .icache_bsize = 32,
  819. .dcache_bsize = 32,
  820. .num_pmcs = 6,
  821. .cpu_setup = __setup_cpu_745x,
  822. .oprofile_cpu_type = "ppc/7450",
  823. .oprofile_type = PPC_OPROFILE_G4,
  824. .platform = "ppc7450",
  825. },
  826. { /* 7448 */
  827. .pvr_mask = 0xffff0000,
  828. .pvr_value = 0x80040000,
  829. .cpu_name = "7448",
  830. .cpu_features = CPU_FTRS_7448,
  831. .cpu_user_features = COMMON_USER |
  832. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  833. .icache_bsize = 32,
  834. .dcache_bsize = 32,
  835. .num_pmcs = 6,
  836. .cpu_setup = __setup_cpu_745x,
  837. .oprofile_cpu_type = "ppc/7450",
  838. .oprofile_type = PPC_OPROFILE_G4,
  839. .platform = "ppc7450",
  840. },
  841. { /* 82xx (8240, 8245, 8260 are all 603e cores) */
  842. .pvr_mask = 0x7fff0000,
  843. .pvr_value = 0x00810000,
  844. .cpu_name = "82xx",
  845. .cpu_features = CPU_FTRS_82XX,
  846. .cpu_user_features = COMMON_USER,
  847. .icache_bsize = 32,
  848. .dcache_bsize = 32,
  849. .cpu_setup = __setup_cpu_603,
  850. .platform = "ppc603",
  851. },
  852. { /* All G2_LE (603e core, plus some) have the same pvr */
  853. .pvr_mask = 0x7fff0000,
  854. .pvr_value = 0x00820000,
  855. .cpu_name = "G2_LE",
  856. .cpu_features = CPU_FTRS_G2_LE,
  857. .cpu_user_features = COMMON_USER,
  858. .icache_bsize = 32,
  859. .dcache_bsize = 32,
  860. .cpu_setup = __setup_cpu_603,
  861. .platform = "ppc603",
  862. },
  863. { /* e300c1 (a 603e core, plus some) on 83xx */
  864. .pvr_mask = 0x7fff0000,
  865. .pvr_value = 0x00830000,
  866. .cpu_name = "e300c1",
  867. .cpu_features = CPU_FTRS_E300,
  868. .cpu_user_features = COMMON_USER,
  869. .icache_bsize = 32,
  870. .dcache_bsize = 32,
  871. .cpu_setup = __setup_cpu_603,
  872. .platform = "ppc603",
  873. },
  874. { /* e300c2 (an e300c1 core, plus some, minus FPU) on 83xx */
  875. .pvr_mask = 0x7fff0000,
  876. .pvr_value = 0x00840000,
  877. .cpu_name = "e300c2",
  878. .cpu_features = CPU_FTRS_E300C2,
  879. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  880. .icache_bsize = 32,
  881. .dcache_bsize = 32,
  882. .cpu_setup = __setup_cpu_603,
  883. .platform = "ppc603",
  884. },
  885. { /* e300c3 (e300c1, plus one IU, half cache size) on 83xx */
  886. .pvr_mask = 0x7fff0000,
  887. .pvr_value = 0x00850000,
  888. .cpu_name = "e300c3",
  889. .cpu_features = CPU_FTRS_E300,
  890. .cpu_user_features = COMMON_USER,
  891. .icache_bsize = 32,
  892. .dcache_bsize = 32,
  893. .cpu_setup = __setup_cpu_603,
  894. .platform = "ppc603",
  895. },
  896. { /* e300c4 (e300c1, plus one IU) */
  897. .pvr_mask = 0x7fff0000,
  898. .pvr_value = 0x00860000,
  899. .cpu_name = "e300c4",
  900. .cpu_features = CPU_FTRS_E300,
  901. .cpu_user_features = COMMON_USER,
  902. .icache_bsize = 32,
  903. .dcache_bsize = 32,
  904. .cpu_setup = __setup_cpu_603,
  905. .platform = "ppc603",
  906. },
  907. { /* default match, we assume split I/D cache & TB (non-601)... */
  908. .pvr_mask = 0x00000000,
  909. .pvr_value = 0x00000000,
  910. .cpu_name = "(generic PPC)",
  911. .cpu_features = CPU_FTRS_CLASSIC32,
  912. .cpu_user_features = COMMON_USER,
  913. .icache_bsize = 32,
  914. .dcache_bsize = 32,
  915. .platform = "ppc603",
  916. },
  917. #endif /* CLASSIC_PPC */
  918. #ifdef CONFIG_8xx
  919. { /* 8xx */
  920. .pvr_mask = 0xffff0000,
  921. .pvr_value = 0x00500000,
  922. .cpu_name = "8xx",
  923. /* CPU_FTR_MAYBE_CAN_DOZE is possible,
  924. * if the 8xx code is there.... */
  925. .cpu_features = CPU_FTRS_8XX,
  926. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  927. .icache_bsize = 16,
  928. .dcache_bsize = 16,
  929. .platform = "ppc823",
  930. },
  931. #endif /* CONFIG_8xx */
  932. #ifdef CONFIG_40x
  933. { /* 403GC */
  934. .pvr_mask = 0xffffff00,
  935. .pvr_value = 0x00200200,
  936. .cpu_name = "403GC",
  937. .cpu_features = CPU_FTRS_40X,
  938. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  939. .icache_bsize = 16,
  940. .dcache_bsize = 16,
  941. .platform = "ppc403",
  942. },
  943. { /* 403GCX */
  944. .pvr_mask = 0xffffff00,
  945. .pvr_value = 0x00201400,
  946. .cpu_name = "403GCX",
  947. .cpu_features = CPU_FTRS_40X,
  948. .cpu_user_features = PPC_FEATURE_32 |
  949. PPC_FEATURE_HAS_MMU | PPC_FEATURE_NO_TB,
  950. .icache_bsize = 16,
  951. .dcache_bsize = 16,
  952. .platform = "ppc403",
  953. },
  954. { /* 403G ?? */
  955. .pvr_mask = 0xffff0000,
  956. .pvr_value = 0x00200000,
  957. .cpu_name = "403G ??",
  958. .cpu_features = CPU_FTRS_40X,
  959. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  960. .icache_bsize = 16,
  961. .dcache_bsize = 16,
  962. .platform = "ppc403",
  963. },
  964. { /* 405GP */
  965. .pvr_mask = 0xffff0000,
  966. .pvr_value = 0x40110000,
  967. .cpu_name = "405GP",
  968. .cpu_features = CPU_FTRS_40X,
  969. .cpu_user_features = PPC_FEATURE_32 |
  970. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  971. .icache_bsize = 32,
  972. .dcache_bsize = 32,
  973. .platform = "ppc405",
  974. },
  975. { /* STB 03xxx */
  976. .pvr_mask = 0xffff0000,
  977. .pvr_value = 0x40130000,
  978. .cpu_name = "STB03xxx",
  979. .cpu_features = CPU_FTRS_40X,
  980. .cpu_user_features = PPC_FEATURE_32 |
  981. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  982. .icache_bsize = 32,
  983. .dcache_bsize = 32,
  984. .platform = "ppc405",
  985. },
  986. { /* STB 04xxx */
  987. .pvr_mask = 0xffff0000,
  988. .pvr_value = 0x41810000,
  989. .cpu_name = "STB04xxx",
  990. .cpu_features = CPU_FTRS_40X,
  991. .cpu_user_features = PPC_FEATURE_32 |
  992. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  993. .icache_bsize = 32,
  994. .dcache_bsize = 32,
  995. .platform = "ppc405",
  996. },
  997. { /* NP405L */
  998. .pvr_mask = 0xffff0000,
  999. .pvr_value = 0x41610000,
  1000. .cpu_name = "NP405L",
  1001. .cpu_features = CPU_FTRS_40X,
  1002. .cpu_user_features = PPC_FEATURE_32 |
  1003. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1004. .icache_bsize = 32,
  1005. .dcache_bsize = 32,
  1006. .platform = "ppc405",
  1007. },
  1008. { /* NP4GS3 */
  1009. .pvr_mask = 0xffff0000,
  1010. .pvr_value = 0x40B10000,
  1011. .cpu_name = "NP4GS3",
  1012. .cpu_features = CPU_FTRS_40X,
  1013. .cpu_user_features = PPC_FEATURE_32 |
  1014. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1015. .icache_bsize = 32,
  1016. .dcache_bsize = 32,
  1017. .platform = "ppc405",
  1018. },
  1019. { /* NP405H */
  1020. .pvr_mask = 0xffff0000,
  1021. .pvr_value = 0x41410000,
  1022. .cpu_name = "NP405H",
  1023. .cpu_features = CPU_FTRS_40X,
  1024. .cpu_user_features = PPC_FEATURE_32 |
  1025. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1026. .icache_bsize = 32,
  1027. .dcache_bsize = 32,
  1028. .platform = "ppc405",
  1029. },
  1030. { /* 405GPr */
  1031. .pvr_mask = 0xffff0000,
  1032. .pvr_value = 0x50910000,
  1033. .cpu_name = "405GPr",
  1034. .cpu_features = CPU_FTRS_40X,
  1035. .cpu_user_features = PPC_FEATURE_32 |
  1036. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1037. .icache_bsize = 32,
  1038. .dcache_bsize = 32,
  1039. .platform = "ppc405",
  1040. },
  1041. { /* STBx25xx */
  1042. .pvr_mask = 0xffff0000,
  1043. .pvr_value = 0x51510000,
  1044. .cpu_name = "STBx25xx",
  1045. .cpu_features = CPU_FTRS_40X,
  1046. .cpu_user_features = PPC_FEATURE_32 |
  1047. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1048. .icache_bsize = 32,
  1049. .dcache_bsize = 32,
  1050. .platform = "ppc405",
  1051. },
  1052. { /* 405LP */
  1053. .pvr_mask = 0xffff0000,
  1054. .pvr_value = 0x41F10000,
  1055. .cpu_name = "405LP",
  1056. .cpu_features = CPU_FTRS_40X,
  1057. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  1058. .icache_bsize = 32,
  1059. .dcache_bsize = 32,
  1060. .platform = "ppc405",
  1061. },
  1062. { /* Xilinx Virtex-II Pro */
  1063. .pvr_mask = 0xfffff000,
  1064. .pvr_value = 0x20010000,
  1065. .cpu_name = "Virtex-II Pro",
  1066. .cpu_features = CPU_FTRS_40X,
  1067. .cpu_user_features = PPC_FEATURE_32 |
  1068. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1069. .icache_bsize = 32,
  1070. .dcache_bsize = 32,
  1071. .platform = "ppc405",
  1072. },
  1073. { /* Xilinx Virtex-4 FX */
  1074. .pvr_mask = 0xfffff000,
  1075. .pvr_value = 0x20011000,
  1076. .cpu_name = "Virtex-4 FX",
  1077. .cpu_features = CPU_FTRS_40X,
  1078. .cpu_user_features = PPC_FEATURE_32 |
  1079. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1080. .icache_bsize = 32,
  1081. .dcache_bsize = 32,
  1082. .platform = "ppc405",
  1083. },
  1084. { /* 405EP */
  1085. .pvr_mask = 0xffff0000,
  1086. .pvr_value = 0x51210000,
  1087. .cpu_name = "405EP",
  1088. .cpu_features = CPU_FTRS_40X,
  1089. .cpu_user_features = PPC_FEATURE_32 |
  1090. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1091. .icache_bsize = 32,
  1092. .dcache_bsize = 32,
  1093. .platform = "ppc405",
  1094. },
  1095. { /* 405EX */
  1096. .pvr_mask = 0xffff0000,
  1097. .pvr_value = 0x12910000,
  1098. .cpu_name = "405EX",
  1099. .cpu_features = CPU_FTRS_40X,
  1100. .cpu_user_features = PPC_FEATURE_32 |
  1101. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1102. .icache_bsize = 32,
  1103. .dcache_bsize = 32,
  1104. .platform = "ppc405",
  1105. },
  1106. #endif /* CONFIG_40x */
  1107. #ifdef CONFIG_44x
  1108. {
  1109. .pvr_mask = 0xf0000fff,
  1110. .pvr_value = 0x40000850,
  1111. .cpu_name = "440GR Rev. A",
  1112. .cpu_features = CPU_FTRS_44X,
  1113. .cpu_user_features = COMMON_USER_BOOKE,
  1114. .icache_bsize = 32,
  1115. .dcache_bsize = 32,
  1116. .platform = "ppc440",
  1117. },
  1118. { /* Use logical PVR for 440EP (logical pvr = pvr | 0x8) */
  1119. .pvr_mask = 0xf0000fff,
  1120. .pvr_value = 0x40000858,
  1121. .cpu_name = "440EP Rev. A",
  1122. .cpu_features = CPU_FTRS_44X,
  1123. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1124. .icache_bsize = 32,
  1125. .dcache_bsize = 32,
  1126. .cpu_setup = __setup_cpu_440ep,
  1127. .platform = "ppc440",
  1128. },
  1129. {
  1130. .pvr_mask = 0xf0000fff,
  1131. .pvr_value = 0x400008d3,
  1132. .cpu_name = "440GR Rev. B",
  1133. .cpu_features = CPU_FTRS_44X,
  1134. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1135. .icache_bsize = 32,
  1136. .dcache_bsize = 32,
  1137. .platform = "ppc440",
  1138. },
  1139. { /* Use logical PVR for 440EP (logical pvr = pvr | 0x8) */
  1140. .pvr_mask = 0xf0000fff,
  1141. .pvr_value = 0x400008db,
  1142. .cpu_name = "440EP Rev. B",
  1143. .cpu_features = CPU_FTRS_44X,
  1144. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1145. .icache_bsize = 32,
  1146. .dcache_bsize = 32,
  1147. .cpu_setup = __setup_cpu_440ep,
  1148. .platform = "ppc440",
  1149. },
  1150. { /* 440GRX */
  1151. .pvr_mask = 0xf0000ffb,
  1152. .pvr_value = 0x200008D0,
  1153. .cpu_name = "440GRX",
  1154. .cpu_features = CPU_FTRS_44X,
  1155. .cpu_user_features = COMMON_USER_BOOKE,
  1156. .icache_bsize = 32,
  1157. .dcache_bsize = 32,
  1158. .cpu_setup = __setup_cpu_440grx,
  1159. .platform = "ppc440",
  1160. },
  1161. { /* Use logical PVR for 440EPx (logical pvr = pvr | 0x8) */
  1162. .pvr_mask = 0xf0000ffb,
  1163. .pvr_value = 0x200008D8,
  1164. .cpu_name = "440EPX",
  1165. .cpu_features = CPU_FTRS_44X,
  1166. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1167. .icache_bsize = 32,
  1168. .dcache_bsize = 32,
  1169. .cpu_setup = __setup_cpu_440epx,
  1170. .platform = "ppc440",
  1171. },
  1172. { /* 440GP Rev. B */
  1173. .pvr_mask = 0xf0000fff,
  1174. .pvr_value = 0x40000440,
  1175. .cpu_name = "440GP Rev. B",
  1176. .cpu_features = CPU_FTRS_44X,
  1177. .cpu_user_features = COMMON_USER_BOOKE,
  1178. .icache_bsize = 32,
  1179. .dcache_bsize = 32,
  1180. .platform = "ppc440gp",
  1181. },
  1182. { /* 440GP Rev. C */
  1183. .pvr_mask = 0xf0000fff,
  1184. .pvr_value = 0x40000481,
  1185. .cpu_name = "440GP Rev. C",
  1186. .cpu_features = CPU_FTRS_44X,
  1187. .cpu_user_features = COMMON_USER_BOOKE,
  1188. .icache_bsize = 32,
  1189. .dcache_bsize = 32,
  1190. .platform = "ppc440gp",
  1191. },
  1192. { /* 440GX Rev. A */
  1193. .pvr_mask = 0xf0000fff,
  1194. .pvr_value = 0x50000850,
  1195. .cpu_name = "440GX Rev. A",
  1196. .cpu_features = CPU_FTRS_44X,
  1197. .cpu_user_features = COMMON_USER_BOOKE,
  1198. .icache_bsize = 32,
  1199. .dcache_bsize = 32,
  1200. .platform = "ppc440",
  1201. },
  1202. { /* 440GX Rev. B */
  1203. .pvr_mask = 0xf0000fff,
  1204. .pvr_value = 0x50000851,
  1205. .cpu_name = "440GX Rev. B",
  1206. .cpu_features = CPU_FTRS_44X,
  1207. .cpu_user_features = COMMON_USER_BOOKE,
  1208. .icache_bsize = 32,
  1209. .dcache_bsize = 32,
  1210. .platform = "ppc440",
  1211. },
  1212. { /* 440GX Rev. C */
  1213. .pvr_mask = 0xf0000fff,
  1214. .pvr_value = 0x50000892,
  1215. .cpu_name = "440GX Rev. C",
  1216. .cpu_features = CPU_FTRS_44X,
  1217. .cpu_user_features = COMMON_USER_BOOKE,
  1218. .icache_bsize = 32,
  1219. .dcache_bsize = 32,
  1220. .platform = "ppc440",
  1221. },
  1222. { /* 440GX Rev. F */
  1223. .pvr_mask = 0xf0000fff,
  1224. .pvr_value = 0x50000894,
  1225. .cpu_name = "440GX Rev. F",
  1226. .cpu_features = CPU_FTRS_44X,
  1227. .cpu_user_features = COMMON_USER_BOOKE,
  1228. .icache_bsize = 32,
  1229. .dcache_bsize = 32,
  1230. .platform = "ppc440",
  1231. },
  1232. { /* 440SP Rev. A */
  1233. .pvr_mask = 0xfff00fff,
  1234. .pvr_value = 0x53200891,
  1235. .cpu_name = "440SP Rev. A",
  1236. .cpu_features = CPU_FTRS_44X,
  1237. .cpu_user_features = COMMON_USER_BOOKE,
  1238. .icache_bsize = 32,
  1239. .dcache_bsize = 32,
  1240. .platform = "ppc440",
  1241. },
  1242. { /* 440SPe Rev. A */
  1243. .pvr_mask = 0xfff00fff,
  1244. .pvr_value = 0x53400890,
  1245. .cpu_name = "440SPe Rev. A",
  1246. .cpu_features = CPU_FTRS_44X,
  1247. .cpu_user_features = COMMON_USER_BOOKE,
  1248. .icache_bsize = 32,
  1249. .dcache_bsize = 32,
  1250. .platform = "ppc440",
  1251. },
  1252. { /* 440SPe Rev. B */
  1253. .pvr_mask = 0xfff00fff,
  1254. .pvr_value = 0x53400891,
  1255. .cpu_name = "440SPe Rev. B",
  1256. .cpu_features = CPU_FTRS_44X,
  1257. .cpu_user_features = COMMON_USER_BOOKE,
  1258. .icache_bsize = 32,
  1259. .dcache_bsize = 32,
  1260. .platform = "ppc440",
  1261. },
  1262. #endif /* CONFIG_44x */
  1263. #ifdef CONFIG_FSL_BOOKE
  1264. { /* e200z5 */
  1265. .pvr_mask = 0xfff00000,
  1266. .pvr_value = 0x81000000,
  1267. .cpu_name = "e200z5",
  1268. /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
  1269. .cpu_features = CPU_FTRS_E200,
  1270. .cpu_user_features = COMMON_USER_BOOKE |
  1271. PPC_FEATURE_HAS_EFP_SINGLE |
  1272. PPC_FEATURE_UNIFIED_CACHE,
  1273. .dcache_bsize = 32,
  1274. .platform = "ppc5554",
  1275. },
  1276. { /* e200z6 */
  1277. .pvr_mask = 0xfff00000,
  1278. .pvr_value = 0x81100000,
  1279. .cpu_name = "e200z6",
  1280. /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
  1281. .cpu_features = CPU_FTRS_E200,
  1282. .cpu_user_features = COMMON_USER_BOOKE |
  1283. PPC_FEATURE_HAS_SPE_COMP |
  1284. PPC_FEATURE_HAS_EFP_SINGLE_COMP |
  1285. PPC_FEATURE_UNIFIED_CACHE,
  1286. .dcache_bsize = 32,
  1287. .platform = "ppc5554",
  1288. },
  1289. { /* e500 */
  1290. .pvr_mask = 0xffff0000,
  1291. .pvr_value = 0x80200000,
  1292. .cpu_name = "e500",
  1293. /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
  1294. .cpu_features = CPU_FTRS_E500,
  1295. .cpu_user_features = COMMON_USER_BOOKE |
  1296. PPC_FEATURE_HAS_SPE_COMP |
  1297. PPC_FEATURE_HAS_EFP_SINGLE_COMP,
  1298. .icache_bsize = 32,
  1299. .dcache_bsize = 32,
  1300. .num_pmcs = 4,
  1301. .oprofile_cpu_type = "ppc/e500",
  1302. .oprofile_type = PPC_OPROFILE_BOOKE,
  1303. .platform = "ppc8540",
  1304. },
  1305. { /* e500v2 */
  1306. .pvr_mask = 0xffff0000,
  1307. .pvr_value = 0x80210000,
  1308. .cpu_name = "e500v2",
  1309. /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
  1310. .cpu_features = CPU_FTRS_E500_2,
  1311. .cpu_user_features = COMMON_USER_BOOKE |
  1312. PPC_FEATURE_HAS_SPE_COMP |
  1313. PPC_FEATURE_HAS_EFP_SINGLE_COMP |
  1314. PPC_FEATURE_HAS_EFP_DOUBLE_COMP,
  1315. .icache_bsize = 32,
  1316. .dcache_bsize = 32,
  1317. .num_pmcs = 4,
  1318. .oprofile_cpu_type = "ppc/e500",
  1319. .oprofile_type = PPC_OPROFILE_BOOKE,
  1320. .platform = "ppc8548",
  1321. },
  1322. #endif
  1323. #if !CLASSIC_PPC
  1324. { /* default match */
  1325. .pvr_mask = 0x00000000,
  1326. .pvr_value = 0x00000000,
  1327. .cpu_name = "(generic PPC)",
  1328. .cpu_features = CPU_FTRS_GENERIC_32,
  1329. .cpu_user_features = PPC_FEATURE_32,
  1330. .icache_bsize = 32,
  1331. .dcache_bsize = 32,
  1332. .platform = "powerpc",
  1333. }
  1334. #endif /* !CLASSIC_PPC */
  1335. #endif /* CONFIG_PPC32 */
  1336. };
  1337. static struct cpu_spec the_cpu_spec;
  1338. struct cpu_spec * __init identify_cpu(unsigned long offset, unsigned int pvr)
  1339. {
  1340. struct cpu_spec *s = cpu_specs;
  1341. struct cpu_spec *t = &the_cpu_spec;
  1342. int i;
  1343. s = PTRRELOC(s);
  1344. t = PTRRELOC(t);
  1345. for (i = 0; i < ARRAY_SIZE(cpu_specs); i++,s++)
  1346. if ((pvr & s->pvr_mask) == s->pvr_value) {
  1347. /*
  1348. * If we are overriding a previous value derived
  1349. * from the real PVR with a new value obtained
  1350. * using a logical PVR value, don't modify the
  1351. * performance monitor fields.
  1352. */
  1353. if (t->num_pmcs && !s->num_pmcs) {
  1354. t->cpu_name = s->cpu_name;
  1355. t->cpu_features = s->cpu_features;
  1356. t->cpu_user_features = s->cpu_user_features;
  1357. t->icache_bsize = s->icache_bsize;
  1358. t->dcache_bsize = s->dcache_bsize;
  1359. t->cpu_setup = s->cpu_setup;
  1360. t->cpu_restore = s->cpu_restore;
  1361. t->platform = s->platform;
  1362. } else
  1363. *t = *s;
  1364. *PTRRELOC(&cur_cpu_spec) = &the_cpu_spec;
  1365. #if defined(CONFIG_PPC64) || defined(CONFIG_BOOKE)
  1366. /* ppc64 and booke expect identify_cpu to also call
  1367. * setup_cpu for that processor. I will consolidate
  1368. * that at a later time, for now, just use #ifdef.
  1369. * we also don't need to PTRRELOC the function pointer
  1370. * on ppc64 and booke as we are running at 0 in real
  1371. * mode on ppc64 and reloc_offset is always 0 on booke.
  1372. */
  1373. if (s->cpu_setup) {
  1374. s->cpu_setup(offset, s);
  1375. }
  1376. #endif /* CONFIG_PPC64 || CONFIG_BOOKE */
  1377. return s;
  1378. }
  1379. BUG();
  1380. return NULL;
  1381. }
  1382. void do_feature_fixups(unsigned long value, void *fixup_start, void *fixup_end)
  1383. {
  1384. struct fixup_entry {
  1385. unsigned long mask;
  1386. unsigned long value;
  1387. long start_off;
  1388. long end_off;
  1389. } *fcur, *fend;
  1390. fcur = fixup_start;
  1391. fend = fixup_end;
  1392. for (; fcur < fend; fcur++) {
  1393. unsigned int *pstart, *pend, *p;
  1394. if ((value & fcur->mask) == fcur->value)
  1395. continue;
  1396. /* These PTRRELOCs will disappear once the new scheme for
  1397. * modules and vdso is implemented
  1398. */
  1399. pstart = ((unsigned int *)fcur) + (fcur->start_off / 4);
  1400. pend = ((unsigned int *)fcur) + (fcur->end_off / 4);
  1401. for (p = pstart; p < pend; p++) {
  1402. *p = 0x60000000u;
  1403. asm volatile ("dcbst 0, %0" : : "r" (p));
  1404. }
  1405. asm volatile ("sync" : : : "memory");
  1406. for (p = pstart; p < pend; p++)
  1407. asm volatile ("icbi 0,%0" : : "r" (p));
  1408. asm volatile ("sync; isync" : : : "memory");
  1409. }
  1410. }