iwl-core.c 85 KB

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  1. /******************************************************************************
  2. *
  3. * GPL LICENSE SUMMARY
  4. *
  5. * Copyright(c) 2008 - 2009 Intel Corporation. All rights reserved.
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of version 2 of the GNU General Public License as
  9. * published by the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope that it will be useful, but
  12. * WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  14. * General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
  19. * USA
  20. *
  21. * The full GNU General Public License is included in this distribution
  22. * in the file called LICENSE.GPL.
  23. *
  24. * Contact Information:
  25. * Intel Linux Wireless <ilw@linux.intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *****************************************************************************/
  28. #include <linux/kernel.h>
  29. #include <linux/module.h>
  30. #include <linux/etherdevice.h>
  31. #include <net/mac80211.h>
  32. #include "iwl-eeprom.h"
  33. #include "iwl-dev.h" /* FIXME: remove */
  34. #include "iwl-debug.h"
  35. #include "iwl-core.h"
  36. #include "iwl-io.h"
  37. #include "iwl-power.h"
  38. #include "iwl-sta.h"
  39. #include "iwl-helpers.h"
  40. MODULE_DESCRIPTION("iwl core");
  41. MODULE_VERSION(IWLWIFI_VERSION);
  42. MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
  43. MODULE_LICENSE("GPL");
  44. #define IWL_DECLARE_RATE_INFO(r, s, ip, in, rp, rn, pp, np) \
  45. [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
  46. IWL_RATE_SISO_##s##M_PLCP, \
  47. IWL_RATE_MIMO2_##s##M_PLCP,\
  48. IWL_RATE_MIMO3_##s##M_PLCP,\
  49. IWL_RATE_##r##M_IEEE, \
  50. IWL_RATE_##ip##M_INDEX, \
  51. IWL_RATE_##in##M_INDEX, \
  52. IWL_RATE_##rp##M_INDEX, \
  53. IWL_RATE_##rn##M_INDEX, \
  54. IWL_RATE_##pp##M_INDEX, \
  55. IWL_RATE_##np##M_INDEX }
  56. u32 iwl_debug_level;
  57. EXPORT_SYMBOL(iwl_debug_level);
  58. static irqreturn_t iwl_isr(int irq, void *data);
  59. /*
  60. * Parameter order:
  61. * rate, ht rate, prev rate, next rate, prev tgg rate, next tgg rate
  62. *
  63. * If there isn't a valid next or previous rate then INV is used which
  64. * maps to IWL_RATE_INVALID
  65. *
  66. */
  67. const struct iwl_rate_info iwl_rates[IWL_RATE_COUNT] = {
  68. IWL_DECLARE_RATE_INFO(1, INV, INV, 2, INV, 2, INV, 2), /* 1mbps */
  69. IWL_DECLARE_RATE_INFO(2, INV, 1, 5, 1, 5, 1, 5), /* 2mbps */
  70. IWL_DECLARE_RATE_INFO(5, INV, 2, 6, 2, 11, 2, 11), /*5.5mbps */
  71. IWL_DECLARE_RATE_INFO(11, INV, 9, 12, 9, 12, 5, 18), /* 11mbps */
  72. IWL_DECLARE_RATE_INFO(6, 6, 5, 9, 5, 11, 5, 11), /* 6mbps */
  73. IWL_DECLARE_RATE_INFO(9, 6, 6, 11, 6, 11, 5, 11), /* 9mbps */
  74. IWL_DECLARE_RATE_INFO(12, 12, 11, 18, 11, 18, 11, 18), /* 12mbps */
  75. IWL_DECLARE_RATE_INFO(18, 18, 12, 24, 12, 24, 11, 24), /* 18mbps */
  76. IWL_DECLARE_RATE_INFO(24, 24, 18, 36, 18, 36, 18, 36), /* 24mbps */
  77. IWL_DECLARE_RATE_INFO(36, 36, 24, 48, 24, 48, 24, 48), /* 36mbps */
  78. IWL_DECLARE_RATE_INFO(48, 48, 36, 54, 36, 54, 36, 54), /* 48mbps */
  79. IWL_DECLARE_RATE_INFO(54, 54, 48, INV, 48, INV, 48, INV),/* 54mbps */
  80. IWL_DECLARE_RATE_INFO(60, 60, 48, INV, 48, INV, 48, INV),/* 60mbps */
  81. /* FIXME:RS: ^^ should be INV (legacy) */
  82. };
  83. EXPORT_SYMBOL(iwl_rates);
  84. /**
  85. * translate ucode response to mac80211 tx status control values
  86. */
  87. void iwl_hwrate_to_tx_control(struct iwl_priv *priv, u32 rate_n_flags,
  88. struct ieee80211_tx_info *info)
  89. {
  90. int rate_index;
  91. struct ieee80211_tx_rate *r = &info->control.rates[0];
  92. info->antenna_sel_tx =
  93. ((rate_n_flags & RATE_MCS_ANT_ABC_MSK) >> RATE_MCS_ANT_POS);
  94. if (rate_n_flags & RATE_MCS_HT_MSK)
  95. r->flags |= IEEE80211_TX_RC_MCS;
  96. if (rate_n_flags & RATE_MCS_GF_MSK)
  97. r->flags |= IEEE80211_TX_RC_GREEN_FIELD;
  98. if (rate_n_flags & RATE_MCS_FAT_MSK)
  99. r->flags |= IEEE80211_TX_RC_40_MHZ_WIDTH;
  100. if (rate_n_flags & RATE_MCS_DUP_MSK)
  101. r->flags |= IEEE80211_TX_RC_DUP_DATA;
  102. if (rate_n_flags & RATE_MCS_SGI_MSK)
  103. r->flags |= IEEE80211_TX_RC_SHORT_GI;
  104. rate_index = iwl_hwrate_to_plcp_idx(rate_n_flags);
  105. if (info->band == IEEE80211_BAND_5GHZ)
  106. rate_index -= IWL_FIRST_OFDM_RATE;
  107. r->idx = rate_index;
  108. }
  109. EXPORT_SYMBOL(iwl_hwrate_to_tx_control);
  110. int iwl_hwrate_to_plcp_idx(u32 rate_n_flags)
  111. {
  112. int idx = 0;
  113. /* HT rate format */
  114. if (rate_n_flags & RATE_MCS_HT_MSK) {
  115. idx = (rate_n_flags & 0xff);
  116. if (idx >= IWL_RATE_MIMO3_6M_PLCP)
  117. idx = idx - IWL_RATE_MIMO3_6M_PLCP;
  118. else if (idx >= IWL_RATE_MIMO2_6M_PLCP)
  119. idx = idx - IWL_RATE_MIMO2_6M_PLCP;
  120. idx += IWL_FIRST_OFDM_RATE;
  121. /* skip 9M not supported in ht*/
  122. if (idx >= IWL_RATE_9M_INDEX)
  123. idx += 1;
  124. if ((idx >= IWL_FIRST_OFDM_RATE) && (idx <= IWL_LAST_OFDM_RATE))
  125. return idx;
  126. /* legacy rate format, search for match in table */
  127. } else {
  128. for (idx = 0; idx < ARRAY_SIZE(iwl_rates); idx++)
  129. if (iwl_rates[idx].plcp == (rate_n_flags & 0xFF))
  130. return idx;
  131. }
  132. return -1;
  133. }
  134. EXPORT_SYMBOL(iwl_hwrate_to_plcp_idx);
  135. u8 iwl_toggle_tx_ant(struct iwl_priv *priv, u8 ant)
  136. {
  137. int i;
  138. u8 ind = ant;
  139. for (i = 0; i < RATE_ANT_NUM - 1; i++) {
  140. ind = (ind + 1) < RATE_ANT_NUM ? ind + 1 : 0;
  141. if (priv->hw_params.valid_tx_ant & BIT(ind))
  142. return ind;
  143. }
  144. return ant;
  145. }
  146. const u8 iwl_bcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
  147. EXPORT_SYMBOL(iwl_bcast_addr);
  148. /* This function both allocates and initializes hw and priv. */
  149. struct ieee80211_hw *iwl_alloc_all(struct iwl_cfg *cfg,
  150. struct ieee80211_ops *hw_ops)
  151. {
  152. struct iwl_priv *priv;
  153. /* mac80211 allocates memory for this device instance, including
  154. * space for this driver's private structure */
  155. struct ieee80211_hw *hw =
  156. ieee80211_alloc_hw(sizeof(struct iwl_priv), hw_ops);
  157. if (hw == NULL) {
  158. printk(KERN_ERR "%s: Can not allocate network device\n",
  159. cfg->name);
  160. goto out;
  161. }
  162. priv = hw->priv;
  163. priv->hw = hw;
  164. out:
  165. return hw;
  166. }
  167. EXPORT_SYMBOL(iwl_alloc_all);
  168. void iwl_hw_detect(struct iwl_priv *priv)
  169. {
  170. priv->hw_rev = _iwl_read32(priv, CSR_HW_REV);
  171. priv->hw_wa_rev = _iwl_read32(priv, CSR_HW_REV_WA_REG);
  172. pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &priv->rev_id);
  173. }
  174. EXPORT_SYMBOL(iwl_hw_detect);
  175. int iwl_hw_nic_init(struct iwl_priv *priv)
  176. {
  177. unsigned long flags;
  178. struct iwl_rx_queue *rxq = &priv->rxq;
  179. int ret;
  180. /* nic_init */
  181. spin_lock_irqsave(&priv->lock, flags);
  182. priv->cfg->ops->lib->apm_ops.init(priv);
  183. iwl_write32(priv, CSR_INT_COALESCING, 512 / 32);
  184. spin_unlock_irqrestore(&priv->lock, flags);
  185. ret = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
  186. priv->cfg->ops->lib->apm_ops.config(priv);
  187. /* Allocate the RX queue, or reset if it is already allocated */
  188. if (!rxq->bd) {
  189. ret = iwl_rx_queue_alloc(priv);
  190. if (ret) {
  191. IWL_ERR(priv, "Unable to initialize Rx queue\n");
  192. return -ENOMEM;
  193. }
  194. } else
  195. iwl_rx_queue_reset(priv, rxq);
  196. iwl_rx_replenish(priv);
  197. iwl_rx_init(priv, rxq);
  198. spin_lock_irqsave(&priv->lock, flags);
  199. rxq->need_update = 1;
  200. iwl_rx_queue_update_write_ptr(priv, rxq);
  201. spin_unlock_irqrestore(&priv->lock, flags);
  202. /* Allocate and init all Tx and Command queues */
  203. ret = iwl_txq_ctx_reset(priv);
  204. if (ret)
  205. return ret;
  206. set_bit(STATUS_INIT, &priv->status);
  207. return 0;
  208. }
  209. EXPORT_SYMBOL(iwl_hw_nic_init);
  210. /*
  211. * QoS support
  212. */
  213. void iwl_activate_qos(struct iwl_priv *priv, u8 force)
  214. {
  215. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  216. return;
  217. priv->qos_data.def_qos_parm.qos_flags = 0;
  218. if (priv->qos_data.qos_cap.q_AP.queue_request &&
  219. !priv->qos_data.qos_cap.q_AP.txop_request)
  220. priv->qos_data.def_qos_parm.qos_flags |=
  221. QOS_PARAM_FLG_TXOP_TYPE_MSK;
  222. if (priv->qos_data.qos_active)
  223. priv->qos_data.def_qos_parm.qos_flags |=
  224. QOS_PARAM_FLG_UPDATE_EDCA_MSK;
  225. if (priv->current_ht_config.is_ht)
  226. priv->qos_data.def_qos_parm.qos_flags |= QOS_PARAM_FLG_TGN_MSK;
  227. if (force || iwl_is_associated(priv)) {
  228. IWL_DEBUG_QOS(priv, "send QoS cmd with Qos active=%d FLAGS=0x%X\n",
  229. priv->qos_data.qos_active,
  230. priv->qos_data.def_qos_parm.qos_flags);
  231. iwl_send_cmd_pdu_async(priv, REPLY_QOS_PARAM,
  232. sizeof(struct iwl_qosparam_cmd),
  233. &priv->qos_data.def_qos_parm, NULL);
  234. }
  235. }
  236. EXPORT_SYMBOL(iwl_activate_qos);
  237. /*
  238. * AC CWmin CW max AIFSN TXOP Limit TXOP Limit
  239. * (802.11b) (802.11a/g)
  240. * AC_BK 15 1023 7 0 0
  241. * AC_BE 15 1023 3 0 0
  242. * AC_VI 7 15 2 6.016ms 3.008ms
  243. * AC_VO 3 7 2 3.264ms 1.504ms
  244. */
  245. void iwl_reset_qos(struct iwl_priv *priv)
  246. {
  247. u16 cw_min = 15;
  248. u16 cw_max = 1023;
  249. u8 aifs = 2;
  250. bool is_legacy = false;
  251. unsigned long flags;
  252. int i;
  253. spin_lock_irqsave(&priv->lock, flags);
  254. /* QoS always active in AP and ADHOC mode
  255. * In STA mode wait for association
  256. */
  257. if (priv->iw_mode == NL80211_IFTYPE_ADHOC ||
  258. priv->iw_mode == NL80211_IFTYPE_AP)
  259. priv->qos_data.qos_active = 1;
  260. else
  261. priv->qos_data.qos_active = 0;
  262. /* check for legacy mode */
  263. if ((priv->iw_mode == NL80211_IFTYPE_ADHOC &&
  264. (priv->active_rate & IWL_OFDM_RATES_MASK) == 0) ||
  265. (priv->iw_mode == NL80211_IFTYPE_STATION &&
  266. (priv->staging_rxon.flags & RXON_FLG_SHORT_SLOT_MSK) == 0)) {
  267. cw_min = 31;
  268. is_legacy = 1;
  269. }
  270. if (priv->qos_data.qos_active)
  271. aifs = 3;
  272. /* AC_BE */
  273. priv->qos_data.def_qos_parm.ac[0].cw_min = cpu_to_le16(cw_min);
  274. priv->qos_data.def_qos_parm.ac[0].cw_max = cpu_to_le16(cw_max);
  275. priv->qos_data.def_qos_parm.ac[0].aifsn = aifs;
  276. priv->qos_data.def_qos_parm.ac[0].edca_txop = 0;
  277. priv->qos_data.def_qos_parm.ac[0].reserved1 = 0;
  278. if (priv->qos_data.qos_active) {
  279. /* AC_BK */
  280. i = 1;
  281. priv->qos_data.def_qos_parm.ac[i].cw_min = cpu_to_le16(cw_min);
  282. priv->qos_data.def_qos_parm.ac[i].cw_max = cpu_to_le16(cw_max);
  283. priv->qos_data.def_qos_parm.ac[i].aifsn = 7;
  284. priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
  285. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  286. /* AC_VI */
  287. i = 2;
  288. priv->qos_data.def_qos_parm.ac[i].cw_min =
  289. cpu_to_le16((cw_min + 1) / 2 - 1);
  290. priv->qos_data.def_qos_parm.ac[i].cw_max =
  291. cpu_to_le16(cw_min);
  292. priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
  293. if (is_legacy)
  294. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  295. cpu_to_le16(6016);
  296. else
  297. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  298. cpu_to_le16(3008);
  299. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  300. /* AC_VO */
  301. i = 3;
  302. priv->qos_data.def_qos_parm.ac[i].cw_min =
  303. cpu_to_le16((cw_min + 1) / 4 - 1);
  304. priv->qos_data.def_qos_parm.ac[i].cw_max =
  305. cpu_to_le16((cw_min + 1) / 2 - 1);
  306. priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
  307. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  308. if (is_legacy)
  309. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  310. cpu_to_le16(3264);
  311. else
  312. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  313. cpu_to_le16(1504);
  314. } else {
  315. for (i = 1; i < 4; i++) {
  316. priv->qos_data.def_qos_parm.ac[i].cw_min =
  317. cpu_to_le16(cw_min);
  318. priv->qos_data.def_qos_parm.ac[i].cw_max =
  319. cpu_to_le16(cw_max);
  320. priv->qos_data.def_qos_parm.ac[i].aifsn = aifs;
  321. priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
  322. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  323. }
  324. }
  325. IWL_DEBUG_QOS(priv, "set QoS to default \n");
  326. spin_unlock_irqrestore(&priv->lock, flags);
  327. }
  328. EXPORT_SYMBOL(iwl_reset_qos);
  329. #define MAX_BIT_RATE_40_MHZ 150 /* Mbps */
  330. #define MAX_BIT_RATE_20_MHZ 72 /* Mbps */
  331. static void iwlcore_init_ht_hw_capab(const struct iwl_priv *priv,
  332. struct ieee80211_sta_ht_cap *ht_info,
  333. enum ieee80211_band band)
  334. {
  335. u16 max_bit_rate = 0;
  336. u8 rx_chains_num = priv->hw_params.rx_chains_num;
  337. u8 tx_chains_num = priv->hw_params.tx_chains_num;
  338. ht_info->cap = 0;
  339. memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
  340. ht_info->ht_supported = true;
  341. ht_info->cap |= IEEE80211_HT_CAP_GRN_FLD;
  342. ht_info->cap |= IEEE80211_HT_CAP_SGI_20;
  343. ht_info->cap |= (IEEE80211_HT_CAP_SM_PS &
  344. (WLAN_HT_CAP_SM_PS_DISABLED << 2));
  345. max_bit_rate = MAX_BIT_RATE_20_MHZ;
  346. if (priv->hw_params.fat_channel & BIT(band)) {
  347. ht_info->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
  348. ht_info->cap |= IEEE80211_HT_CAP_SGI_40;
  349. ht_info->mcs.rx_mask[4] = 0x01;
  350. max_bit_rate = MAX_BIT_RATE_40_MHZ;
  351. }
  352. if (priv->cfg->mod_params->amsdu_size_8K)
  353. ht_info->cap |= IEEE80211_HT_CAP_MAX_AMSDU;
  354. ht_info->ampdu_factor = CFG_HT_RX_AMPDU_FACTOR_DEF;
  355. ht_info->ampdu_density = CFG_HT_MPDU_DENSITY_DEF;
  356. ht_info->mcs.rx_mask[0] = 0xFF;
  357. if (rx_chains_num >= 2)
  358. ht_info->mcs.rx_mask[1] = 0xFF;
  359. if (rx_chains_num >= 3)
  360. ht_info->mcs.rx_mask[2] = 0xFF;
  361. /* Highest supported Rx data rate */
  362. max_bit_rate *= rx_chains_num;
  363. WARN_ON(max_bit_rate & ~IEEE80211_HT_MCS_RX_HIGHEST_MASK);
  364. ht_info->mcs.rx_highest = cpu_to_le16(max_bit_rate);
  365. /* Tx MCS capabilities */
  366. ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
  367. if (tx_chains_num != rx_chains_num) {
  368. ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
  369. ht_info->mcs.tx_params |= ((tx_chains_num - 1) <<
  370. IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
  371. }
  372. }
  373. static void iwlcore_init_hw_rates(struct iwl_priv *priv,
  374. struct ieee80211_rate *rates)
  375. {
  376. int i;
  377. for (i = 0; i < IWL_RATE_COUNT; i++) {
  378. rates[i].bitrate = iwl_rates[i].ieee * 5;
  379. rates[i].hw_value = i; /* Rate scaling will work on indexes */
  380. rates[i].hw_value_short = i;
  381. rates[i].flags = 0;
  382. if ((i > IWL_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) {
  383. /*
  384. * If CCK != 1M then set short preamble rate flag.
  385. */
  386. rates[i].flags |=
  387. (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
  388. 0 : IEEE80211_RATE_SHORT_PREAMBLE;
  389. }
  390. }
  391. }
  392. /**
  393. * iwlcore_init_geos - Initialize mac80211's geo/channel info based from eeprom
  394. */
  395. int iwlcore_init_geos(struct iwl_priv *priv)
  396. {
  397. struct iwl_channel_info *ch;
  398. struct ieee80211_supported_band *sband;
  399. struct ieee80211_channel *channels;
  400. struct ieee80211_channel *geo_ch;
  401. struct ieee80211_rate *rates;
  402. int i = 0;
  403. if (priv->bands[IEEE80211_BAND_2GHZ].n_bitrates ||
  404. priv->bands[IEEE80211_BAND_5GHZ].n_bitrates) {
  405. IWL_DEBUG_INFO(priv, "Geography modes already initialized.\n");
  406. set_bit(STATUS_GEO_CONFIGURED, &priv->status);
  407. return 0;
  408. }
  409. channels = kzalloc(sizeof(struct ieee80211_channel) *
  410. priv->channel_count, GFP_KERNEL);
  411. if (!channels)
  412. return -ENOMEM;
  413. rates = kzalloc((sizeof(struct ieee80211_rate) * (IWL_RATE_COUNT + 1)),
  414. GFP_KERNEL);
  415. if (!rates) {
  416. kfree(channels);
  417. return -ENOMEM;
  418. }
  419. /* 5.2GHz channels start after the 2.4GHz channels */
  420. sband = &priv->bands[IEEE80211_BAND_5GHZ];
  421. sband->channels = &channels[ARRAY_SIZE(iwl_eeprom_band_1)];
  422. /* just OFDM */
  423. sband->bitrates = &rates[IWL_FIRST_OFDM_RATE];
  424. sband->n_bitrates = IWL_RATE_COUNT - IWL_FIRST_OFDM_RATE;
  425. if (priv->cfg->sku & IWL_SKU_N)
  426. iwlcore_init_ht_hw_capab(priv, &sband->ht_cap,
  427. IEEE80211_BAND_5GHZ);
  428. sband = &priv->bands[IEEE80211_BAND_2GHZ];
  429. sband->channels = channels;
  430. /* OFDM & CCK */
  431. sband->bitrates = rates;
  432. sband->n_bitrates = IWL_RATE_COUNT;
  433. if (priv->cfg->sku & IWL_SKU_N)
  434. iwlcore_init_ht_hw_capab(priv, &sband->ht_cap,
  435. IEEE80211_BAND_2GHZ);
  436. priv->ieee_channels = channels;
  437. priv->ieee_rates = rates;
  438. for (i = 0; i < priv->channel_count; i++) {
  439. ch = &priv->channel_info[i];
  440. /* FIXME: might be removed if scan is OK */
  441. if (!is_channel_valid(ch))
  442. continue;
  443. if (is_channel_a_band(ch))
  444. sband = &priv->bands[IEEE80211_BAND_5GHZ];
  445. else
  446. sband = &priv->bands[IEEE80211_BAND_2GHZ];
  447. geo_ch = &sband->channels[sband->n_channels++];
  448. geo_ch->center_freq =
  449. ieee80211_channel_to_frequency(ch->channel);
  450. geo_ch->max_power = ch->max_power_avg;
  451. geo_ch->max_antenna_gain = 0xff;
  452. geo_ch->hw_value = ch->channel;
  453. if (is_channel_valid(ch)) {
  454. if (!(ch->flags & EEPROM_CHANNEL_IBSS))
  455. geo_ch->flags |= IEEE80211_CHAN_NO_IBSS;
  456. if (!(ch->flags & EEPROM_CHANNEL_ACTIVE))
  457. geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
  458. if (ch->flags & EEPROM_CHANNEL_RADAR)
  459. geo_ch->flags |= IEEE80211_CHAN_RADAR;
  460. geo_ch->flags |= ch->fat_extension_channel;
  461. if (ch->max_power_avg > priv->tx_power_channel_lmt)
  462. priv->tx_power_channel_lmt = ch->max_power_avg;
  463. } else {
  464. geo_ch->flags |= IEEE80211_CHAN_DISABLED;
  465. }
  466. /* Save flags for reg domain usage */
  467. geo_ch->orig_flags = geo_ch->flags;
  468. IWL_DEBUG_INFO(priv, "Channel %d Freq=%d[%sGHz] %s flag=0x%X\n",
  469. ch->channel, geo_ch->center_freq,
  470. is_channel_a_band(ch) ? "5.2" : "2.4",
  471. geo_ch->flags & IEEE80211_CHAN_DISABLED ?
  472. "restricted" : "valid",
  473. geo_ch->flags);
  474. }
  475. if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) &&
  476. priv->cfg->sku & IWL_SKU_A) {
  477. IWL_INFO(priv, "Incorrectly detected BG card as ABG. "
  478. "Please send your PCI ID 0x%04X:0x%04X to maintainer.\n",
  479. priv->pci_dev->device,
  480. priv->pci_dev->subsystem_device);
  481. priv->cfg->sku &= ~IWL_SKU_A;
  482. }
  483. IWL_INFO(priv, "Tunable channels: %d 802.11bg, %d 802.11a channels\n",
  484. priv->bands[IEEE80211_BAND_2GHZ].n_channels,
  485. priv->bands[IEEE80211_BAND_5GHZ].n_channels);
  486. set_bit(STATUS_GEO_CONFIGURED, &priv->status);
  487. return 0;
  488. }
  489. EXPORT_SYMBOL(iwlcore_init_geos);
  490. /*
  491. * iwlcore_free_geos - undo allocations in iwlcore_init_geos
  492. */
  493. void iwlcore_free_geos(struct iwl_priv *priv)
  494. {
  495. kfree(priv->ieee_channels);
  496. kfree(priv->ieee_rates);
  497. clear_bit(STATUS_GEO_CONFIGURED, &priv->status);
  498. }
  499. EXPORT_SYMBOL(iwlcore_free_geos);
  500. static bool is_single_rx_stream(struct iwl_priv *priv)
  501. {
  502. return !priv->current_ht_config.is_ht ||
  503. ((priv->current_ht_config.mcs.rx_mask[1] == 0) &&
  504. (priv->current_ht_config.mcs.rx_mask[2] == 0));
  505. }
  506. static u8 iwl_is_channel_extension(struct iwl_priv *priv,
  507. enum ieee80211_band band,
  508. u16 channel, u8 extension_chan_offset)
  509. {
  510. const struct iwl_channel_info *ch_info;
  511. ch_info = iwl_get_channel_info(priv, band, channel);
  512. if (!is_channel_valid(ch_info))
  513. return 0;
  514. if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_ABOVE)
  515. return !(ch_info->fat_extension_channel &
  516. IEEE80211_CHAN_NO_HT40PLUS);
  517. else if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_BELOW)
  518. return !(ch_info->fat_extension_channel &
  519. IEEE80211_CHAN_NO_HT40MINUS);
  520. return 0;
  521. }
  522. u8 iwl_is_fat_tx_allowed(struct iwl_priv *priv,
  523. struct ieee80211_sta_ht_cap *sta_ht_inf)
  524. {
  525. struct iwl_ht_info *iwl_ht_conf = &priv->current_ht_config;
  526. if ((!iwl_ht_conf->is_ht) ||
  527. (iwl_ht_conf->supported_chan_width != IWL_CHANNEL_WIDTH_40MHZ))
  528. return 0;
  529. /* We do not check for IEEE80211_HT_CAP_SUP_WIDTH_20_40
  530. * the bit will not set if it is pure 40MHz case
  531. */
  532. if (sta_ht_inf) {
  533. if (!sta_ht_inf->ht_supported)
  534. return 0;
  535. }
  536. return iwl_is_channel_extension(priv, priv->band,
  537. le16_to_cpu(priv->staging_rxon.channel),
  538. iwl_ht_conf->extension_chan_offset);
  539. }
  540. EXPORT_SYMBOL(iwl_is_fat_tx_allowed);
  541. static u16 iwl_adjust_beacon_interval(u16 beacon_val, u16 max_beacon_val)
  542. {
  543. u16 new_val = 0;
  544. u16 beacon_factor = 0;
  545. beacon_factor = (beacon_val + max_beacon_val) / max_beacon_val;
  546. new_val = beacon_val / beacon_factor;
  547. if (!new_val)
  548. new_val = max_beacon_val;
  549. return new_val;
  550. }
  551. void iwl_setup_rxon_timing(struct iwl_priv *priv)
  552. {
  553. u64 tsf;
  554. s32 interval_tm, rem;
  555. unsigned long flags;
  556. struct ieee80211_conf *conf = NULL;
  557. u16 beacon_int;
  558. conf = ieee80211_get_hw_conf(priv->hw);
  559. spin_lock_irqsave(&priv->lock, flags);
  560. priv->rxon_timing.timestamp = cpu_to_le64(priv->timestamp);
  561. priv->rxon_timing.listen_interval = cpu_to_le16(conf->listen_interval);
  562. if (priv->iw_mode == NL80211_IFTYPE_STATION) {
  563. beacon_int = priv->beacon_int;
  564. priv->rxon_timing.atim_window = 0;
  565. } else {
  566. beacon_int = priv->vif->bss_conf.beacon_int;
  567. /* TODO: we need to get atim_window from upper stack
  568. * for now we set to 0 */
  569. priv->rxon_timing.atim_window = 0;
  570. }
  571. beacon_int = iwl_adjust_beacon_interval(beacon_int,
  572. priv->hw_params.max_beacon_itrvl * 1024);
  573. priv->rxon_timing.beacon_interval = cpu_to_le16(beacon_int);
  574. tsf = priv->timestamp; /* tsf is modifed by do_div: copy it */
  575. interval_tm = beacon_int * 1024;
  576. rem = do_div(tsf, interval_tm);
  577. priv->rxon_timing.beacon_init_val = cpu_to_le32(interval_tm - rem);
  578. spin_unlock_irqrestore(&priv->lock, flags);
  579. IWL_DEBUG_ASSOC(priv,
  580. "beacon interval %d beacon timer %d beacon tim %d\n",
  581. le16_to_cpu(priv->rxon_timing.beacon_interval),
  582. le32_to_cpu(priv->rxon_timing.beacon_init_val),
  583. le16_to_cpu(priv->rxon_timing.atim_window));
  584. }
  585. EXPORT_SYMBOL(iwl_setup_rxon_timing);
  586. void iwl_set_rxon_hwcrypto(struct iwl_priv *priv, int hw_decrypt)
  587. {
  588. struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
  589. if (hw_decrypt)
  590. rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK;
  591. else
  592. rxon->filter_flags |= RXON_FILTER_DIS_DECRYPT_MSK;
  593. }
  594. EXPORT_SYMBOL(iwl_set_rxon_hwcrypto);
  595. /**
  596. * iwl_check_rxon_cmd - validate RXON structure is valid
  597. *
  598. * NOTE: This is really only useful during development and can eventually
  599. * be #ifdef'd out once the driver is stable and folks aren't actively
  600. * making changes
  601. */
  602. int iwl_check_rxon_cmd(struct iwl_priv *priv)
  603. {
  604. int error = 0;
  605. int counter = 1;
  606. struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
  607. if (rxon->flags & RXON_FLG_BAND_24G_MSK) {
  608. error |= le32_to_cpu(rxon->flags &
  609. (RXON_FLG_TGJ_NARROW_BAND_MSK |
  610. RXON_FLG_RADAR_DETECT_MSK));
  611. if (error)
  612. IWL_WARN(priv, "check 24G fields %d | %d\n",
  613. counter++, error);
  614. } else {
  615. error |= (rxon->flags & RXON_FLG_SHORT_SLOT_MSK) ?
  616. 0 : le32_to_cpu(RXON_FLG_SHORT_SLOT_MSK);
  617. if (error)
  618. IWL_WARN(priv, "check 52 fields %d | %d\n",
  619. counter++, error);
  620. error |= le32_to_cpu(rxon->flags & RXON_FLG_CCK_MSK);
  621. if (error)
  622. IWL_WARN(priv, "check 52 CCK %d | %d\n",
  623. counter++, error);
  624. }
  625. error |= (rxon->node_addr[0] | rxon->bssid_addr[0]) & 0x1;
  626. if (error)
  627. IWL_WARN(priv, "check mac addr %d | %d\n", counter++, error);
  628. /* make sure basic rates 6Mbps and 1Mbps are supported */
  629. error |= (((rxon->ofdm_basic_rates & IWL_RATE_6M_MASK) == 0) &&
  630. ((rxon->cck_basic_rates & IWL_RATE_1M_MASK) == 0));
  631. if (error)
  632. IWL_WARN(priv, "check basic rate %d | %d\n", counter++, error);
  633. error |= (le16_to_cpu(rxon->assoc_id) > 2007);
  634. if (error)
  635. IWL_WARN(priv, "check assoc id %d | %d\n", counter++, error);
  636. error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK))
  637. == (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK));
  638. if (error)
  639. IWL_WARN(priv, "check CCK and short slot %d | %d\n",
  640. counter++, error);
  641. error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK))
  642. == (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK));
  643. if (error)
  644. IWL_WARN(priv, "check CCK & auto detect %d | %d\n",
  645. counter++, error);
  646. error |= ((rxon->flags & (RXON_FLG_AUTO_DETECT_MSK |
  647. RXON_FLG_TGG_PROTECT_MSK)) == RXON_FLG_TGG_PROTECT_MSK);
  648. if (error)
  649. IWL_WARN(priv, "check TGG and auto detect %d | %d\n",
  650. counter++, error);
  651. if (error)
  652. IWL_WARN(priv, "Tuning to channel %d\n",
  653. le16_to_cpu(rxon->channel));
  654. if (error) {
  655. IWL_ERR(priv, "Not a valid iwl_rxon_assoc_cmd field values\n");
  656. return -1;
  657. }
  658. return 0;
  659. }
  660. EXPORT_SYMBOL(iwl_check_rxon_cmd);
  661. /**
  662. * iwl_full_rxon_required - check if full RXON (vs RXON_ASSOC) cmd is needed
  663. * @priv: staging_rxon is compared to active_rxon
  664. *
  665. * If the RXON structure is changing enough to require a new tune,
  666. * or is clearing the RXON_FILTER_ASSOC_MSK, then return 1 to indicate that
  667. * a new tune (full RXON command, rather than RXON_ASSOC cmd) is required.
  668. */
  669. int iwl_full_rxon_required(struct iwl_priv *priv)
  670. {
  671. /* These items are only settable from the full RXON command */
  672. if (!(iwl_is_associated(priv)) ||
  673. compare_ether_addr(priv->staging_rxon.bssid_addr,
  674. priv->active_rxon.bssid_addr) ||
  675. compare_ether_addr(priv->staging_rxon.node_addr,
  676. priv->active_rxon.node_addr) ||
  677. compare_ether_addr(priv->staging_rxon.wlap_bssid_addr,
  678. priv->active_rxon.wlap_bssid_addr) ||
  679. (priv->staging_rxon.dev_type != priv->active_rxon.dev_type) ||
  680. (priv->staging_rxon.channel != priv->active_rxon.channel) ||
  681. (priv->staging_rxon.air_propagation !=
  682. priv->active_rxon.air_propagation) ||
  683. (priv->staging_rxon.ofdm_ht_single_stream_basic_rates !=
  684. priv->active_rxon.ofdm_ht_single_stream_basic_rates) ||
  685. (priv->staging_rxon.ofdm_ht_dual_stream_basic_rates !=
  686. priv->active_rxon.ofdm_ht_dual_stream_basic_rates) ||
  687. (priv->staging_rxon.ofdm_ht_triple_stream_basic_rates !=
  688. priv->active_rxon.ofdm_ht_triple_stream_basic_rates) ||
  689. (priv->staging_rxon.assoc_id != priv->active_rxon.assoc_id))
  690. return 1;
  691. /* flags, filter_flags, ofdm_basic_rates, and cck_basic_rates can
  692. * be updated with the RXON_ASSOC command -- however only some
  693. * flag transitions are allowed using RXON_ASSOC */
  694. /* Check if we are not switching bands */
  695. if ((priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) !=
  696. (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK))
  697. return 1;
  698. /* Check if we are switching association toggle */
  699. if ((priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) !=
  700. (priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK))
  701. return 1;
  702. return 0;
  703. }
  704. EXPORT_SYMBOL(iwl_full_rxon_required);
  705. u8 iwl_rate_get_lowest_plcp(struct iwl_priv *priv)
  706. {
  707. int i;
  708. int rate_mask;
  709. /* Set rate mask*/
  710. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK)
  711. rate_mask = priv->active_rate_basic & IWL_CCK_RATES_MASK;
  712. else
  713. rate_mask = priv->active_rate_basic & IWL_OFDM_RATES_MASK;
  714. /* Find lowest valid rate */
  715. for (i = IWL_RATE_1M_INDEX; i != IWL_RATE_INVALID;
  716. i = iwl_rates[i].next_ieee) {
  717. if (rate_mask & (1 << i))
  718. return iwl_rates[i].plcp;
  719. }
  720. /* No valid rate was found. Assign the lowest one */
  721. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK)
  722. return IWL_RATE_1M_PLCP;
  723. else
  724. return IWL_RATE_6M_PLCP;
  725. }
  726. EXPORT_SYMBOL(iwl_rate_get_lowest_plcp);
  727. void iwl_set_rxon_ht(struct iwl_priv *priv, struct iwl_ht_info *ht_info)
  728. {
  729. struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
  730. if (!ht_info->is_ht) {
  731. rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MSK |
  732. RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK |
  733. RXON_FLG_FAT_PROT_MSK |
  734. RXON_FLG_HT_PROT_MSK);
  735. return;
  736. }
  737. /* FIXME: if the definition of ht_protection changed, the "translation"
  738. * will be needed for rxon->flags
  739. */
  740. rxon->flags |= cpu_to_le32(ht_info->ht_protection << RXON_FLG_HT_OPERATING_MODE_POS);
  741. /* Set up channel bandwidth:
  742. * 20 MHz only, 20/40 mixed or pure 40 if fat ok */
  743. /* clear the HT channel mode before set the mode */
  744. rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MSK |
  745. RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
  746. if (iwl_is_fat_tx_allowed(priv, NULL)) {
  747. /* pure 40 fat */
  748. if (ht_info->ht_protection == IEEE80211_HT_OP_MODE_PROTECTION_20MHZ) {
  749. rxon->flags |= RXON_FLG_CHANNEL_MODE_PURE_40;
  750. /* Note: control channel is opposite of extension channel */
  751. switch (ht_info->extension_chan_offset) {
  752. case IEEE80211_HT_PARAM_CHA_SEC_ABOVE:
  753. rxon->flags &= ~RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
  754. break;
  755. case IEEE80211_HT_PARAM_CHA_SEC_BELOW:
  756. rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
  757. break;
  758. }
  759. } else {
  760. /* Note: control channel is opposite of extension channel */
  761. switch (ht_info->extension_chan_offset) {
  762. case IEEE80211_HT_PARAM_CHA_SEC_ABOVE:
  763. rxon->flags &= ~(RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
  764. rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED;
  765. break;
  766. case IEEE80211_HT_PARAM_CHA_SEC_BELOW:
  767. rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
  768. rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED;
  769. break;
  770. case IEEE80211_HT_PARAM_CHA_SEC_NONE:
  771. default:
  772. /* channel location only valid if in Mixed mode */
  773. IWL_ERR(priv, "invalid extension channel offset\n");
  774. break;
  775. }
  776. }
  777. } else {
  778. rxon->flags |= RXON_FLG_CHANNEL_MODE_LEGACY;
  779. }
  780. if (priv->cfg->ops->hcmd->set_rxon_chain)
  781. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  782. IWL_DEBUG_ASSOC(priv, "supported HT rate 0x%X 0x%X 0x%X "
  783. "rxon flags 0x%X operation mode :0x%X "
  784. "extension channel offset 0x%x\n",
  785. ht_info->mcs.rx_mask[0],
  786. ht_info->mcs.rx_mask[1],
  787. ht_info->mcs.rx_mask[2],
  788. le32_to_cpu(rxon->flags), ht_info->ht_protection,
  789. ht_info->extension_chan_offset);
  790. return;
  791. }
  792. EXPORT_SYMBOL(iwl_set_rxon_ht);
  793. #define IWL_NUM_RX_CHAINS_MULTIPLE 3
  794. #define IWL_NUM_RX_CHAINS_SINGLE 2
  795. #define IWL_NUM_IDLE_CHAINS_DUAL 2
  796. #define IWL_NUM_IDLE_CHAINS_SINGLE 1
  797. /* Determine how many receiver/antenna chains to use.
  798. * More provides better reception via diversity. Fewer saves power.
  799. * MIMO (dual stream) requires at least 2, but works better with 3.
  800. * This does not determine *which* chains to use, just how many.
  801. */
  802. static int iwl_get_active_rx_chain_count(struct iwl_priv *priv)
  803. {
  804. bool is_single = is_single_rx_stream(priv);
  805. bool is_cam = !test_bit(STATUS_POWER_PMI, &priv->status);
  806. /* # of Rx chains to use when expecting MIMO. */
  807. if (is_single || (!is_cam && (priv->current_ht_config.sm_ps ==
  808. WLAN_HT_CAP_SM_PS_STATIC)))
  809. return IWL_NUM_RX_CHAINS_SINGLE;
  810. else
  811. return IWL_NUM_RX_CHAINS_MULTIPLE;
  812. }
  813. static int iwl_get_idle_rx_chain_count(struct iwl_priv *priv, int active_cnt)
  814. {
  815. int idle_cnt;
  816. bool is_cam = !test_bit(STATUS_POWER_PMI, &priv->status);
  817. /* # Rx chains when idling and maybe trying to save power */
  818. switch (priv->current_ht_config.sm_ps) {
  819. case WLAN_HT_CAP_SM_PS_STATIC:
  820. case WLAN_HT_CAP_SM_PS_DYNAMIC:
  821. idle_cnt = (is_cam) ? IWL_NUM_IDLE_CHAINS_DUAL :
  822. IWL_NUM_IDLE_CHAINS_SINGLE;
  823. break;
  824. case WLAN_HT_CAP_SM_PS_DISABLED:
  825. idle_cnt = (is_cam) ? active_cnt : IWL_NUM_IDLE_CHAINS_SINGLE;
  826. break;
  827. case WLAN_HT_CAP_SM_PS_INVALID:
  828. default:
  829. IWL_ERR(priv, "invalid mimo ps mode %d\n",
  830. priv->current_ht_config.sm_ps);
  831. WARN_ON(1);
  832. idle_cnt = -1;
  833. break;
  834. }
  835. return idle_cnt;
  836. }
  837. /* up to 4 chains */
  838. static u8 iwl_count_chain_bitmap(u32 chain_bitmap)
  839. {
  840. u8 res;
  841. res = (chain_bitmap & BIT(0)) >> 0;
  842. res += (chain_bitmap & BIT(1)) >> 1;
  843. res += (chain_bitmap & BIT(2)) >> 2;
  844. res += (chain_bitmap & BIT(4)) >> 4;
  845. return res;
  846. }
  847. /**
  848. * iwl_is_monitor_mode - Determine if interface in monitor mode
  849. *
  850. * priv->iw_mode is set in add_interface, but add_interface is
  851. * never called for monitor mode. The only way mac80211 informs us about
  852. * monitor mode is through configuring filters (call to configure_filter).
  853. */
  854. bool iwl_is_monitor_mode(struct iwl_priv *priv)
  855. {
  856. return !!(priv->staging_rxon.filter_flags & RXON_FILTER_PROMISC_MSK);
  857. }
  858. EXPORT_SYMBOL(iwl_is_monitor_mode);
  859. /**
  860. * iwl_set_rxon_chain - Set up Rx chain usage in "staging" RXON image
  861. *
  862. * Selects how many and which Rx receivers/antennas/chains to use.
  863. * This should not be used for scan command ... it puts data in wrong place.
  864. */
  865. void iwl_set_rxon_chain(struct iwl_priv *priv)
  866. {
  867. bool is_single = is_single_rx_stream(priv);
  868. bool is_cam = !test_bit(STATUS_POWER_PMI, &priv->status);
  869. u8 idle_rx_cnt, active_rx_cnt, valid_rx_cnt;
  870. u32 active_chains;
  871. u16 rx_chain;
  872. /* Tell uCode which antennas are actually connected.
  873. * Before first association, we assume all antennas are connected.
  874. * Just after first association, iwl_chain_noise_calibration()
  875. * checks which antennas actually *are* connected. */
  876. if (priv->chain_noise_data.active_chains)
  877. active_chains = priv->chain_noise_data.active_chains;
  878. else
  879. active_chains = priv->hw_params.valid_rx_ant;
  880. rx_chain = active_chains << RXON_RX_CHAIN_VALID_POS;
  881. /* How many receivers should we use? */
  882. active_rx_cnt = iwl_get_active_rx_chain_count(priv);
  883. idle_rx_cnt = iwl_get_idle_rx_chain_count(priv, active_rx_cnt);
  884. /* correct rx chain count according hw settings
  885. * and chain noise calibration
  886. */
  887. valid_rx_cnt = iwl_count_chain_bitmap(active_chains);
  888. if (valid_rx_cnt < active_rx_cnt)
  889. active_rx_cnt = valid_rx_cnt;
  890. if (valid_rx_cnt < idle_rx_cnt)
  891. idle_rx_cnt = valid_rx_cnt;
  892. rx_chain |= active_rx_cnt << RXON_RX_CHAIN_MIMO_CNT_POS;
  893. rx_chain |= idle_rx_cnt << RXON_RX_CHAIN_CNT_POS;
  894. /* copied from 'iwl_bg_request_scan()' */
  895. /* Force use of chains B and C (0x6) for Rx for 4965
  896. * Avoid A (0x1) because of its off-channel reception on A-band.
  897. * MIMO is not used here, but value is required */
  898. if (iwl_is_monitor_mode(priv) &&
  899. !(priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) &&
  900. ((priv->hw_rev & CSR_HW_REV_TYPE_MSK) == CSR_HW_REV_TYPE_4965)) {
  901. rx_chain = ANT_ABC << RXON_RX_CHAIN_VALID_POS;
  902. rx_chain |= ANT_BC << RXON_RX_CHAIN_FORCE_SEL_POS;
  903. rx_chain |= ANT_ABC << RXON_RX_CHAIN_FORCE_MIMO_SEL_POS;
  904. rx_chain |= 0x1 << RXON_RX_CHAIN_DRIVER_FORCE_POS;
  905. }
  906. priv->staging_rxon.rx_chain = cpu_to_le16(rx_chain);
  907. if (!is_single && (active_rx_cnt >= IWL_NUM_RX_CHAINS_SINGLE) && is_cam)
  908. priv->staging_rxon.rx_chain |= RXON_RX_CHAIN_MIMO_FORCE_MSK;
  909. else
  910. priv->staging_rxon.rx_chain &= ~RXON_RX_CHAIN_MIMO_FORCE_MSK;
  911. IWL_DEBUG_ASSOC(priv, "rx_chain=0x%X active=%d idle=%d\n",
  912. priv->staging_rxon.rx_chain,
  913. active_rx_cnt, idle_rx_cnt);
  914. WARN_ON(active_rx_cnt == 0 || idle_rx_cnt == 0 ||
  915. active_rx_cnt < idle_rx_cnt);
  916. }
  917. EXPORT_SYMBOL(iwl_set_rxon_chain);
  918. /**
  919. * iwl_set_rxon_channel - Set the phymode and channel values in staging RXON
  920. * @phymode: MODE_IEEE80211A sets to 5.2GHz; all else set to 2.4GHz
  921. * @channel: Any channel valid for the requested phymode
  922. * In addition to setting the staging RXON, priv->phymode is also set.
  923. *
  924. * NOTE: Does not commit to the hardware; it sets appropriate bit fields
  925. * in the staging RXON flag structure based on the phymode
  926. */
  927. int iwl_set_rxon_channel(struct iwl_priv *priv, struct ieee80211_channel *ch)
  928. {
  929. enum ieee80211_band band = ch->band;
  930. u16 channel = ieee80211_frequency_to_channel(ch->center_freq);
  931. if (!iwl_get_channel_info(priv, band, channel)) {
  932. IWL_DEBUG_INFO(priv, "Could not set channel to %d [%d]\n",
  933. channel, band);
  934. return -EINVAL;
  935. }
  936. if ((le16_to_cpu(priv->staging_rxon.channel) == channel) &&
  937. (priv->band == band))
  938. return 0;
  939. priv->staging_rxon.channel = cpu_to_le16(channel);
  940. if (band == IEEE80211_BAND_5GHZ)
  941. priv->staging_rxon.flags &= ~RXON_FLG_BAND_24G_MSK;
  942. else
  943. priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
  944. priv->band = band;
  945. IWL_DEBUG_INFO(priv, "Staging channel set to %d [%d]\n", channel, band);
  946. return 0;
  947. }
  948. EXPORT_SYMBOL(iwl_set_rxon_channel);
  949. void iwl_set_flags_for_band(struct iwl_priv *priv,
  950. enum ieee80211_band band)
  951. {
  952. if (band == IEEE80211_BAND_5GHZ) {
  953. priv->staging_rxon.flags &=
  954. ~(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK
  955. | RXON_FLG_CCK_MSK);
  956. priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  957. } else {
  958. /* Copied from iwl_post_associate() */
  959. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
  960. priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  961. else
  962. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  963. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  964. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  965. priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
  966. priv->staging_rxon.flags |= RXON_FLG_AUTO_DETECT_MSK;
  967. priv->staging_rxon.flags &= ~RXON_FLG_CCK_MSK;
  968. }
  969. }
  970. EXPORT_SYMBOL(iwl_set_flags_for_band);
  971. /*
  972. * initialize rxon structure with default values from eeprom
  973. */
  974. void iwl_connection_init_rx_config(struct iwl_priv *priv, int mode)
  975. {
  976. const struct iwl_channel_info *ch_info;
  977. memset(&priv->staging_rxon, 0, sizeof(priv->staging_rxon));
  978. switch (mode) {
  979. case NL80211_IFTYPE_AP:
  980. priv->staging_rxon.dev_type = RXON_DEV_TYPE_AP;
  981. break;
  982. case NL80211_IFTYPE_STATION:
  983. priv->staging_rxon.dev_type = RXON_DEV_TYPE_ESS;
  984. priv->staging_rxon.filter_flags = RXON_FILTER_ACCEPT_GRP_MSK;
  985. break;
  986. case NL80211_IFTYPE_ADHOC:
  987. priv->staging_rxon.dev_type = RXON_DEV_TYPE_IBSS;
  988. priv->staging_rxon.flags = RXON_FLG_SHORT_PREAMBLE_MSK;
  989. priv->staging_rxon.filter_flags = RXON_FILTER_BCON_AWARE_MSK |
  990. RXON_FILTER_ACCEPT_GRP_MSK;
  991. break;
  992. default:
  993. IWL_ERR(priv, "Unsupported interface type %d\n", mode);
  994. break;
  995. }
  996. #if 0
  997. /* TODO: Figure out when short_preamble would be set and cache from
  998. * that */
  999. if (!hw_to_local(priv->hw)->short_preamble)
  1000. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  1001. else
  1002. priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  1003. #endif
  1004. ch_info = iwl_get_channel_info(priv, priv->band,
  1005. le16_to_cpu(priv->active_rxon.channel));
  1006. if (!ch_info)
  1007. ch_info = &priv->channel_info[0];
  1008. /*
  1009. * in some case A channels are all non IBSS
  1010. * in this case force B/G channel
  1011. */
  1012. if ((priv->iw_mode == NL80211_IFTYPE_ADHOC) &&
  1013. !(is_channel_ibss(ch_info)))
  1014. ch_info = &priv->channel_info[0];
  1015. priv->staging_rxon.channel = cpu_to_le16(ch_info->channel);
  1016. priv->band = ch_info->band;
  1017. iwl_set_flags_for_band(priv, priv->band);
  1018. priv->staging_rxon.ofdm_basic_rates =
  1019. (IWL_OFDM_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
  1020. priv->staging_rxon.cck_basic_rates =
  1021. (IWL_CCK_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
  1022. /* clear both MIX and PURE40 mode flag */
  1023. priv->staging_rxon.flags &= ~(RXON_FLG_CHANNEL_MODE_MIXED |
  1024. RXON_FLG_CHANNEL_MODE_PURE_40);
  1025. memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
  1026. memcpy(priv->staging_rxon.wlap_bssid_addr, priv->mac_addr, ETH_ALEN);
  1027. priv->staging_rxon.ofdm_ht_single_stream_basic_rates = 0xff;
  1028. priv->staging_rxon.ofdm_ht_dual_stream_basic_rates = 0xff;
  1029. priv->staging_rxon.ofdm_ht_triple_stream_basic_rates = 0xff;
  1030. }
  1031. EXPORT_SYMBOL(iwl_connection_init_rx_config);
  1032. static void iwl_set_rate(struct iwl_priv *priv)
  1033. {
  1034. const struct ieee80211_supported_band *hw = NULL;
  1035. struct ieee80211_rate *rate;
  1036. int i;
  1037. hw = iwl_get_hw_mode(priv, priv->band);
  1038. if (!hw) {
  1039. IWL_ERR(priv, "Failed to set rate: unable to get hw mode\n");
  1040. return;
  1041. }
  1042. priv->active_rate = 0;
  1043. priv->active_rate_basic = 0;
  1044. for (i = 0; i < hw->n_bitrates; i++) {
  1045. rate = &(hw->bitrates[i]);
  1046. if (rate->hw_value < IWL_RATE_COUNT)
  1047. priv->active_rate |= (1 << rate->hw_value);
  1048. }
  1049. IWL_DEBUG_RATE(priv, "Set active_rate = %0x, active_rate_basic = %0x\n",
  1050. priv->active_rate, priv->active_rate_basic);
  1051. /*
  1052. * If a basic rate is configured, then use it (adding IWL_RATE_1M_MASK)
  1053. * otherwise set it to the default of all CCK rates and 6, 12, 24 for
  1054. * OFDM
  1055. */
  1056. if (priv->active_rate_basic & IWL_CCK_BASIC_RATES_MASK)
  1057. priv->staging_rxon.cck_basic_rates =
  1058. ((priv->active_rate_basic &
  1059. IWL_CCK_RATES_MASK) >> IWL_FIRST_CCK_RATE) & 0xF;
  1060. else
  1061. priv->staging_rxon.cck_basic_rates =
  1062. (IWL_CCK_BASIC_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
  1063. if (priv->active_rate_basic & IWL_OFDM_BASIC_RATES_MASK)
  1064. priv->staging_rxon.ofdm_basic_rates =
  1065. ((priv->active_rate_basic &
  1066. (IWL_OFDM_BASIC_RATES_MASK | IWL_RATE_6M_MASK)) >>
  1067. IWL_FIRST_OFDM_RATE) & 0xFF;
  1068. else
  1069. priv->staging_rxon.ofdm_basic_rates =
  1070. (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
  1071. }
  1072. void iwl_rx_csa(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
  1073. {
  1074. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  1075. struct iwl_rxon_cmd *rxon = (void *)&priv->active_rxon;
  1076. struct iwl_csa_notification *csa = &(pkt->u.csa_notif);
  1077. IWL_DEBUG_11H(priv, "CSA notif: channel %d, status %d\n",
  1078. le16_to_cpu(csa->channel), le32_to_cpu(csa->status));
  1079. rxon->channel = csa->channel;
  1080. priv->staging_rxon.channel = csa->channel;
  1081. }
  1082. EXPORT_SYMBOL(iwl_rx_csa);
  1083. #ifdef CONFIG_IWLWIFI_DEBUG
  1084. static void iwl_print_rx_config_cmd(struct iwl_priv *priv)
  1085. {
  1086. struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
  1087. IWL_DEBUG_RADIO(priv, "RX CONFIG:\n");
  1088. iwl_print_hex_dump(IWL_DL_RADIO, (u8 *) rxon, sizeof(*rxon));
  1089. IWL_DEBUG_RADIO(priv, "u16 channel: 0x%x\n", le16_to_cpu(rxon->channel));
  1090. IWL_DEBUG_RADIO(priv, "u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags));
  1091. IWL_DEBUG_RADIO(priv, "u32 filter_flags: 0x%08x\n",
  1092. le32_to_cpu(rxon->filter_flags));
  1093. IWL_DEBUG_RADIO(priv, "u8 dev_type: 0x%x\n", rxon->dev_type);
  1094. IWL_DEBUG_RADIO(priv, "u8 ofdm_basic_rates: 0x%02x\n",
  1095. rxon->ofdm_basic_rates);
  1096. IWL_DEBUG_RADIO(priv, "u8 cck_basic_rates: 0x%02x\n", rxon->cck_basic_rates);
  1097. IWL_DEBUG_RADIO(priv, "u8[6] node_addr: %pM\n", rxon->node_addr);
  1098. IWL_DEBUG_RADIO(priv, "u8[6] bssid_addr: %pM\n", rxon->bssid_addr);
  1099. IWL_DEBUG_RADIO(priv, "u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id));
  1100. }
  1101. #endif
  1102. static const char *desc_lookup_text[] = {
  1103. "OK",
  1104. "FAIL",
  1105. "BAD_PARAM",
  1106. "BAD_CHECKSUM",
  1107. "NMI_INTERRUPT_WDG",
  1108. "SYSASSERT",
  1109. "FATAL_ERROR",
  1110. "BAD_COMMAND",
  1111. "HW_ERROR_TUNE_LOCK",
  1112. "HW_ERROR_TEMPERATURE",
  1113. "ILLEGAL_CHAN_FREQ",
  1114. "VCC_NOT_STABLE",
  1115. "FH_ERROR",
  1116. "NMI_INTERRUPT_HOST",
  1117. "NMI_INTERRUPT_ACTION_PT",
  1118. "NMI_INTERRUPT_UNKNOWN",
  1119. "UCODE_VERSION_MISMATCH",
  1120. "HW_ERROR_ABS_LOCK",
  1121. "HW_ERROR_CAL_LOCK_FAIL",
  1122. "NMI_INTERRUPT_INST_ACTION_PT",
  1123. "NMI_INTERRUPT_DATA_ACTION_PT",
  1124. "NMI_TRM_HW_ER",
  1125. "NMI_INTERRUPT_TRM",
  1126. "NMI_INTERRUPT_BREAK_POINT"
  1127. "DEBUG_0",
  1128. "DEBUG_1",
  1129. "DEBUG_2",
  1130. "DEBUG_3",
  1131. "UNKNOWN"
  1132. };
  1133. static const char *desc_lookup(int i)
  1134. {
  1135. int max = ARRAY_SIZE(desc_lookup_text) - 1;
  1136. if (i < 0 || i > max)
  1137. i = max;
  1138. return desc_lookup_text[i];
  1139. }
  1140. #define ERROR_START_OFFSET (1 * sizeof(u32))
  1141. #define ERROR_ELEM_SIZE (7 * sizeof(u32))
  1142. static void iwl_dump_nic_error_log(struct iwl_priv *priv)
  1143. {
  1144. u32 data2, line;
  1145. u32 desc, time, count, base, data1;
  1146. u32 blink1, blink2, ilink1, ilink2;
  1147. switch (priv->ucode_type) {
  1148. case UCODE_RT:
  1149. base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
  1150. break;
  1151. case UCODE_INIT:
  1152. base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
  1153. break;
  1154. default:
  1155. IWL_ERR(priv, "uCode image not available\n");
  1156. return;
  1157. }
  1158. if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
  1159. IWL_ERR(priv, "Not valid error log pointer 0x%08X\n", base);
  1160. return;
  1161. }
  1162. count = iwl_read_targ_mem(priv, base);
  1163. if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
  1164. IWL_ERR(priv, "Start IWL Error Log Dump:\n");
  1165. IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
  1166. priv->status, count);
  1167. }
  1168. desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
  1169. blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
  1170. blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
  1171. ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
  1172. ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
  1173. data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
  1174. data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
  1175. line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
  1176. time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
  1177. IWL_ERR(priv, "Desc Time "
  1178. "data1 data2 line\n");
  1179. IWL_ERR(priv, "%-28s (#%02d) %010u 0x%08X 0x%08X %u\n",
  1180. desc_lookup(desc), desc, time, data1, data2, line);
  1181. IWL_ERR(priv, "blink1 blink2 ilink1 ilink2\n");
  1182. IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X\n", blink1, blink2,
  1183. ilink1, ilink2);
  1184. }
  1185. #define EVENT_START_OFFSET (4 * sizeof(u32))
  1186. /**
  1187. * iwl_print_event_log - Dump error event log to syslog
  1188. *
  1189. */
  1190. static void iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
  1191. u32 num_events, u32 mode)
  1192. {
  1193. u32 i;
  1194. u32 base; /* SRAM byte address of event log header */
  1195. u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
  1196. u32 ptr; /* SRAM byte address of log data */
  1197. u32 ev, time, data; /* event log data */
  1198. if (num_events == 0)
  1199. return;
  1200. switch (priv->ucode_type) {
  1201. case UCODE_RT:
  1202. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  1203. break;
  1204. case UCODE_INIT:
  1205. base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
  1206. break;
  1207. default:
  1208. IWL_ERR(priv, "uCode image not available\n");
  1209. return;
  1210. }
  1211. if (mode == 0)
  1212. event_size = 2 * sizeof(u32);
  1213. else
  1214. event_size = 3 * sizeof(u32);
  1215. ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
  1216. /* "time" is actually "data" for mode 0 (no timestamp).
  1217. * place event id # at far right for easier visual parsing. */
  1218. for (i = 0; i < num_events; i++) {
  1219. ev = iwl_read_targ_mem(priv, ptr);
  1220. ptr += sizeof(u32);
  1221. time = iwl_read_targ_mem(priv, ptr);
  1222. ptr += sizeof(u32);
  1223. if (mode == 0) {
  1224. /* data, ev */
  1225. IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n", time, ev);
  1226. } else {
  1227. data = iwl_read_targ_mem(priv, ptr);
  1228. ptr += sizeof(u32);
  1229. IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n",
  1230. time, data, ev);
  1231. }
  1232. }
  1233. }
  1234. void iwl_dump_nic_event_log(struct iwl_priv *priv)
  1235. {
  1236. u32 base; /* SRAM byte address of event log header */
  1237. u32 capacity; /* event log capacity in # entries */
  1238. u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
  1239. u32 num_wraps; /* # times uCode wrapped to top of log */
  1240. u32 next_entry; /* index of next entry to be written by uCode */
  1241. u32 size; /* # entries that we'll print */
  1242. switch (priv->ucode_type) {
  1243. case UCODE_RT:
  1244. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  1245. break;
  1246. case UCODE_INIT:
  1247. base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
  1248. break;
  1249. default:
  1250. IWL_ERR(priv, "uCode image not available\n");
  1251. return;
  1252. }
  1253. if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
  1254. IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
  1255. return;
  1256. }
  1257. /* event log header */
  1258. capacity = iwl_read_targ_mem(priv, base);
  1259. mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
  1260. num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
  1261. next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
  1262. size = num_wraps ? capacity : next_entry;
  1263. /* bail out if nothing in log */
  1264. if (size == 0) {
  1265. IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
  1266. return;
  1267. }
  1268. IWL_ERR(priv, "Start IWL Event Log Dump: display count %d, wraps %d\n",
  1269. size, num_wraps);
  1270. /* if uCode has wrapped back to top of log, start at the oldest entry,
  1271. * i.e the next one that uCode would fill. */
  1272. if (num_wraps)
  1273. iwl_print_event_log(priv, next_entry,
  1274. capacity - next_entry, mode);
  1275. /* (then/else) start at top of log */
  1276. iwl_print_event_log(priv, 0, next_entry, mode);
  1277. }
  1278. /**
  1279. * iwl_irq_handle_error - called for HW or SW error interrupt from card
  1280. */
  1281. void iwl_irq_handle_error(struct iwl_priv *priv)
  1282. {
  1283. /* Set the FW error flag -- cleared on iwl_down */
  1284. set_bit(STATUS_FW_ERROR, &priv->status);
  1285. /* Cancel currently queued command. */
  1286. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  1287. #ifdef CONFIG_IWLWIFI_DEBUG
  1288. if (iwl_debug_level & IWL_DL_FW_ERRORS) {
  1289. iwl_dump_nic_error_log(priv);
  1290. iwl_dump_nic_event_log(priv);
  1291. iwl_print_rx_config_cmd(priv);
  1292. }
  1293. #endif
  1294. wake_up_interruptible(&priv->wait_command_queue);
  1295. /* Keep the restart process from trying to send host
  1296. * commands by clearing the INIT status bit */
  1297. clear_bit(STATUS_READY, &priv->status);
  1298. if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  1299. IWL_DEBUG(priv, IWL_DL_FW_ERRORS,
  1300. "Restarting adapter due to uCode error.\n");
  1301. if (priv->cfg->mod_params->restart_fw)
  1302. queue_work(priv->workqueue, &priv->restart);
  1303. }
  1304. }
  1305. EXPORT_SYMBOL(iwl_irq_handle_error);
  1306. void iwl_configure_filter(struct ieee80211_hw *hw,
  1307. unsigned int changed_flags,
  1308. unsigned int *total_flags,
  1309. int mc_count, struct dev_addr_list *mc_list)
  1310. {
  1311. struct iwl_priv *priv = hw->priv;
  1312. __le32 *filter_flags = &priv->staging_rxon.filter_flags;
  1313. IWL_DEBUG_MAC80211(priv, "Enter: changed: 0x%x, total: 0x%x\n",
  1314. changed_flags, *total_flags);
  1315. if (changed_flags & (FIF_OTHER_BSS | FIF_PROMISC_IN_BSS)) {
  1316. if (*total_flags & (FIF_OTHER_BSS | FIF_PROMISC_IN_BSS))
  1317. *filter_flags |= RXON_FILTER_PROMISC_MSK;
  1318. else
  1319. *filter_flags &= ~RXON_FILTER_PROMISC_MSK;
  1320. }
  1321. if (changed_flags & FIF_ALLMULTI) {
  1322. if (*total_flags & FIF_ALLMULTI)
  1323. *filter_flags |= RXON_FILTER_ACCEPT_GRP_MSK;
  1324. else
  1325. *filter_flags &= ~RXON_FILTER_ACCEPT_GRP_MSK;
  1326. }
  1327. if (changed_flags & FIF_CONTROL) {
  1328. if (*total_flags & FIF_CONTROL)
  1329. *filter_flags |= RXON_FILTER_CTL2HOST_MSK;
  1330. else
  1331. *filter_flags &= ~RXON_FILTER_CTL2HOST_MSK;
  1332. }
  1333. if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
  1334. if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
  1335. *filter_flags |= RXON_FILTER_BCON_AWARE_MSK;
  1336. else
  1337. *filter_flags &= ~RXON_FILTER_BCON_AWARE_MSK;
  1338. }
  1339. /* We avoid iwl_commit_rxon here to commit the new filter flags
  1340. * since mac80211 will call ieee80211_hw_config immediately.
  1341. * (mc_list is not supported at this time). Otherwise, we need to
  1342. * queue a background iwl_commit_rxon work.
  1343. */
  1344. *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
  1345. FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
  1346. }
  1347. EXPORT_SYMBOL(iwl_configure_filter);
  1348. int iwl_setup_mac(struct iwl_priv *priv)
  1349. {
  1350. int ret;
  1351. struct ieee80211_hw *hw = priv->hw;
  1352. hw->rate_control_algorithm = "iwl-agn-rs";
  1353. /* Tell mac80211 our characteristics */
  1354. hw->flags = IEEE80211_HW_SIGNAL_DBM |
  1355. IEEE80211_HW_NOISE_DBM |
  1356. IEEE80211_HW_AMPDU_AGGREGATION |
  1357. IEEE80211_HW_SPECTRUM_MGMT |
  1358. IEEE80211_HW_SUPPORTS_PS;
  1359. hw->wiphy->interface_modes =
  1360. BIT(NL80211_IFTYPE_STATION) |
  1361. BIT(NL80211_IFTYPE_ADHOC);
  1362. hw->wiphy->custom_regulatory = true;
  1363. hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX;
  1364. /* we create the 802.11 header and a zero-length SSID element */
  1365. hw->wiphy->max_scan_ie_len = IWL_MAX_PROBE_REQUEST - 24 - 2;
  1366. /* Default value; 4 EDCA QOS priorities */
  1367. hw->queues = 4;
  1368. hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
  1369. if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
  1370. priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
  1371. &priv->bands[IEEE80211_BAND_2GHZ];
  1372. if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
  1373. priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
  1374. &priv->bands[IEEE80211_BAND_5GHZ];
  1375. ret = ieee80211_register_hw(priv->hw);
  1376. if (ret) {
  1377. IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
  1378. return ret;
  1379. }
  1380. priv->mac80211_registered = 1;
  1381. return 0;
  1382. }
  1383. EXPORT_SYMBOL(iwl_setup_mac);
  1384. int iwl_set_hw_params(struct iwl_priv *priv)
  1385. {
  1386. priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
  1387. priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
  1388. if (priv->cfg->mod_params->amsdu_size_8K)
  1389. priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_8K;
  1390. else
  1391. priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_4K;
  1392. priv->hw_params.max_pkt_size = priv->hw_params.rx_buf_size - 256;
  1393. priv->hw_params.max_beacon_itrvl = IWL_MAX_UCODE_BEACON_INTERVAL;
  1394. if (priv->cfg->mod_params->disable_11n)
  1395. priv->cfg->sku &= ~IWL_SKU_N;
  1396. /* Device-specific setup */
  1397. return priv->cfg->ops->lib->set_hw_params(priv);
  1398. }
  1399. EXPORT_SYMBOL(iwl_set_hw_params);
  1400. int iwl_init_drv(struct iwl_priv *priv)
  1401. {
  1402. int ret;
  1403. priv->ibss_beacon = NULL;
  1404. spin_lock_init(&priv->lock);
  1405. spin_lock_init(&priv->sta_lock);
  1406. spin_lock_init(&priv->hcmd_lock);
  1407. INIT_LIST_HEAD(&priv->free_frames);
  1408. mutex_init(&priv->mutex);
  1409. /* Clear the driver's (not device's) station table */
  1410. iwl_clear_stations_table(priv);
  1411. priv->data_retry_limit = -1;
  1412. priv->ieee_channels = NULL;
  1413. priv->ieee_rates = NULL;
  1414. priv->band = IEEE80211_BAND_2GHZ;
  1415. priv->iw_mode = NL80211_IFTYPE_STATION;
  1416. priv->current_ht_config.sm_ps = WLAN_HT_CAP_SM_PS_DISABLED;
  1417. /* Choose which receivers/antennas to use */
  1418. if (priv->cfg->ops->hcmd->set_rxon_chain)
  1419. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  1420. iwl_init_scan_params(priv);
  1421. iwl_reset_qos(priv);
  1422. priv->qos_data.qos_active = 0;
  1423. priv->qos_data.qos_cap.val = 0;
  1424. priv->rates_mask = IWL_RATES_MASK;
  1425. /* If power management is turned on, default to CAM mode */
  1426. priv->power_mode = IWL_POWER_MODE_CAM;
  1427. priv->tx_power_user_lmt = IWL_TX_POWER_TARGET_POWER_MAX;
  1428. ret = iwl_init_channel_map(priv);
  1429. if (ret) {
  1430. IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
  1431. goto err;
  1432. }
  1433. ret = iwlcore_init_geos(priv);
  1434. if (ret) {
  1435. IWL_ERR(priv, "initializing geos failed: %d\n", ret);
  1436. goto err_free_channel_map;
  1437. }
  1438. iwlcore_init_hw_rates(priv, priv->ieee_rates);
  1439. return 0;
  1440. err_free_channel_map:
  1441. iwl_free_channel_map(priv);
  1442. err:
  1443. return ret;
  1444. }
  1445. EXPORT_SYMBOL(iwl_init_drv);
  1446. int iwl_set_tx_power(struct iwl_priv *priv, s8 tx_power, bool force)
  1447. {
  1448. int ret = 0;
  1449. if (tx_power < IWL_TX_POWER_TARGET_POWER_MIN) {
  1450. IWL_WARN(priv, "Requested user TXPOWER %d below lower limit %d.\n",
  1451. tx_power,
  1452. IWL_TX_POWER_TARGET_POWER_MIN);
  1453. return -EINVAL;
  1454. }
  1455. if (tx_power > IWL_TX_POWER_TARGET_POWER_MAX) {
  1456. IWL_WARN(priv, "Requested user TXPOWER %d above upper limit %d.\n",
  1457. tx_power,
  1458. IWL_TX_POWER_TARGET_POWER_MAX);
  1459. return -EINVAL;
  1460. }
  1461. if (priv->tx_power_user_lmt != tx_power)
  1462. force = true;
  1463. priv->tx_power_user_lmt = tx_power;
  1464. /* if nic is not up don't send command */
  1465. if (!iwl_is_ready_rf(priv))
  1466. return ret;
  1467. if (force && priv->cfg->ops->lib->send_tx_power)
  1468. ret = priv->cfg->ops->lib->send_tx_power(priv);
  1469. return ret;
  1470. }
  1471. EXPORT_SYMBOL(iwl_set_tx_power);
  1472. void iwl_uninit_drv(struct iwl_priv *priv)
  1473. {
  1474. iwl_calib_free_results(priv);
  1475. iwlcore_free_geos(priv);
  1476. iwl_free_channel_map(priv);
  1477. kfree(priv->scan);
  1478. }
  1479. EXPORT_SYMBOL(iwl_uninit_drv);
  1480. void iwl_disable_interrupts(struct iwl_priv *priv)
  1481. {
  1482. clear_bit(STATUS_INT_ENABLED, &priv->status);
  1483. /* disable interrupts from uCode/NIC to host */
  1484. iwl_write32(priv, CSR_INT_MASK, 0x00000000);
  1485. /* acknowledge/clear/reset any interrupts still pending
  1486. * from uCode or flow handler (Rx/Tx DMA) */
  1487. iwl_write32(priv, CSR_INT, 0xffffffff);
  1488. iwl_write32(priv, CSR_FH_INT_STATUS, 0xffffffff);
  1489. IWL_DEBUG_ISR(priv, "Disabled interrupts\n");
  1490. }
  1491. EXPORT_SYMBOL(iwl_disable_interrupts);
  1492. void iwl_enable_interrupts(struct iwl_priv *priv)
  1493. {
  1494. IWL_DEBUG_ISR(priv, "Enabling interrupts\n");
  1495. set_bit(STATUS_INT_ENABLED, &priv->status);
  1496. iwl_write32(priv, CSR_INT_MASK, priv->inta_mask);
  1497. }
  1498. EXPORT_SYMBOL(iwl_enable_interrupts);
  1499. #define ICT_COUNT (PAGE_SIZE/sizeof(u32))
  1500. /* Free dram table */
  1501. void iwl_free_isr_ict(struct iwl_priv *priv)
  1502. {
  1503. if (priv->ict_tbl_vir) {
  1504. pci_free_consistent(priv->pci_dev, (sizeof(u32) * ICT_COUNT) +
  1505. PAGE_SIZE, priv->ict_tbl_vir,
  1506. priv->ict_tbl_dma);
  1507. priv->ict_tbl_vir = NULL;
  1508. }
  1509. }
  1510. EXPORT_SYMBOL(iwl_free_isr_ict);
  1511. /* allocate dram shared table it is a PAGE_SIZE aligned
  1512. * also reset all data related to ICT table interrupt.
  1513. */
  1514. int iwl_alloc_isr_ict(struct iwl_priv *priv)
  1515. {
  1516. if (priv->cfg->use_isr_legacy)
  1517. return 0;
  1518. /* allocate shrared data table */
  1519. priv->ict_tbl_vir = pci_alloc_consistent(priv->pci_dev, (sizeof(u32) *
  1520. ICT_COUNT) + PAGE_SIZE,
  1521. &priv->ict_tbl_dma);
  1522. if (!priv->ict_tbl_vir)
  1523. return -ENOMEM;
  1524. /* align table to PAGE_SIZE boundry */
  1525. priv->aligned_ict_tbl_dma = ALIGN(priv->ict_tbl_dma, PAGE_SIZE);
  1526. IWL_DEBUG_ISR(priv, "ict dma addr %Lx dma aligned %Lx diff %d\n",
  1527. (unsigned long long)priv->ict_tbl_dma,
  1528. (unsigned long long)priv->aligned_ict_tbl_dma,
  1529. (int)(priv->aligned_ict_tbl_dma - priv->ict_tbl_dma));
  1530. priv->ict_tbl = priv->ict_tbl_vir +
  1531. (priv->aligned_ict_tbl_dma - priv->ict_tbl_dma);
  1532. IWL_DEBUG_ISR(priv, "ict vir addr %p vir aligned %p diff %d\n",
  1533. priv->ict_tbl, priv->ict_tbl_vir,
  1534. (int)(priv->aligned_ict_tbl_dma - priv->ict_tbl_dma));
  1535. /* reset table and index to all 0 */
  1536. memset(priv->ict_tbl_vir,0, (sizeof(u32) * ICT_COUNT) + PAGE_SIZE);
  1537. priv->ict_index = 0;
  1538. /* add periodic RX interrupt */
  1539. priv->inta_mask |= CSR_INT_BIT_RX_PERIODIC;
  1540. return 0;
  1541. }
  1542. EXPORT_SYMBOL(iwl_alloc_isr_ict);
  1543. /* Device is going up inform it about using ICT interrupt table,
  1544. * also we need to tell the driver to start using ICT interrupt.
  1545. */
  1546. int iwl_reset_ict(struct iwl_priv *priv)
  1547. {
  1548. u32 val;
  1549. unsigned long flags;
  1550. if (!priv->ict_tbl_vir)
  1551. return 0;
  1552. spin_lock_irqsave(&priv->lock, flags);
  1553. iwl_disable_interrupts(priv);
  1554. memset(&priv->ict_tbl[0],0, sizeof(u32) * ICT_COUNT);
  1555. val = priv->aligned_ict_tbl_dma >> PAGE_SHIFT;
  1556. val |= CSR_DRAM_INT_TBL_ENABLE;
  1557. val |= CSR_DRAM_INIT_TBL_WRAP_CHECK;
  1558. IWL_DEBUG_ISR(priv, "CSR_DRAM_INT_TBL_REG =0x%X "
  1559. "aligned dma address %Lx\n",
  1560. val, (unsigned long long)priv->aligned_ict_tbl_dma);
  1561. iwl_write32(priv, CSR_DRAM_INT_TBL_REG, val);
  1562. priv->use_ict = true;
  1563. priv->ict_index = 0;
  1564. iwl_write32(priv, CSR_INT, priv->inta_mask);
  1565. iwl_enable_interrupts(priv);
  1566. spin_unlock_irqrestore(&priv->lock, flags);
  1567. return 0;
  1568. }
  1569. EXPORT_SYMBOL(iwl_reset_ict);
  1570. /* Device is going down disable ict interrupt usage */
  1571. void iwl_disable_ict(struct iwl_priv *priv)
  1572. {
  1573. unsigned long flags;
  1574. spin_lock_irqsave(&priv->lock, flags);
  1575. priv->use_ict = false;
  1576. spin_unlock_irqrestore(&priv->lock, flags);
  1577. }
  1578. EXPORT_SYMBOL(iwl_disable_ict);
  1579. /* interrupt handler using ict table, with this interrupt driver will
  1580. * stop using INTA register to get device's interrupt, reading this register
  1581. * is expensive, device will write interrupts in ICT dram table, increment
  1582. * index then will fire interrupt to driver, driver will OR all ICT table
  1583. * entries from current index up to table entry with 0 value. the result is
  1584. * the interrupt we need to service, driver will set the entries back to 0 and
  1585. * set index.
  1586. */
  1587. irqreturn_t iwl_isr_ict(int irq, void *data)
  1588. {
  1589. struct iwl_priv *priv = data;
  1590. u32 inta, inta_mask;
  1591. u32 val = 0;
  1592. if (!priv)
  1593. return IRQ_NONE;
  1594. /* dram interrupt table not set yet,
  1595. * use legacy interrupt.
  1596. */
  1597. if (!priv->use_ict)
  1598. return iwl_isr(irq, data);
  1599. spin_lock(&priv->lock);
  1600. /* Disable (but don't clear!) interrupts here to avoid
  1601. * back-to-back ISRs and sporadic interrupts from our NIC.
  1602. * If we have something to service, the tasklet will re-enable ints.
  1603. * If we *don't* have something, we'll re-enable before leaving here.
  1604. */
  1605. inta_mask = iwl_read32(priv, CSR_INT_MASK); /* just for debug */
  1606. iwl_write32(priv, CSR_INT_MASK, 0x00000000);
  1607. /* Ignore interrupt if there's nothing in NIC to service.
  1608. * This may be due to IRQ shared with another device,
  1609. * or due to sporadic interrupts thrown from our NIC. */
  1610. if (!priv->ict_tbl[priv->ict_index]) {
  1611. IWL_DEBUG_ISR(priv, "Ignore interrupt, inta == 0\n");
  1612. goto none;
  1613. }
  1614. /* read all entries that not 0 start with ict_index */
  1615. while (priv->ict_tbl[priv->ict_index]) {
  1616. val |= priv->ict_tbl[priv->ict_index];
  1617. IWL_DEBUG_ISR(priv, "ICT index %d value 0x%08X\n",
  1618. priv->ict_index,
  1619. priv->ict_tbl[priv->ict_index]);
  1620. priv->ict_tbl[priv->ict_index] = 0;
  1621. priv->ict_index = iwl_queue_inc_wrap(priv->ict_index,
  1622. ICT_COUNT);
  1623. }
  1624. /* We should not get this value, just ignore it. */
  1625. if (val == 0xffffffff)
  1626. val = 0;
  1627. inta = (0xff & val) | ((0xff00 & val) << 16);
  1628. IWL_DEBUG_ISR(priv, "ISR inta 0x%08x, enabled 0x%08x ict 0x%08x\n",
  1629. inta, inta_mask, val);
  1630. inta &= priv->inta_mask;
  1631. priv->inta |= inta;
  1632. /* iwl_irq_tasklet() will service interrupts and re-enable them */
  1633. if (likely(inta))
  1634. tasklet_schedule(&priv->irq_tasklet);
  1635. else if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->inta) {
  1636. /* Allow interrupt if was disabled by this handler and
  1637. * no tasklet was schedules, We should not enable interrupt,
  1638. * tasklet will enable it.
  1639. */
  1640. iwl_enable_interrupts(priv);
  1641. }
  1642. spin_unlock(&priv->lock);
  1643. return IRQ_HANDLED;
  1644. none:
  1645. /* re-enable interrupts here since we don't have anything to service.
  1646. * only Re-enable if disabled by irq.
  1647. */
  1648. if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->inta)
  1649. iwl_enable_interrupts(priv);
  1650. spin_unlock(&priv->lock);
  1651. return IRQ_NONE;
  1652. }
  1653. EXPORT_SYMBOL(iwl_isr_ict);
  1654. static irqreturn_t iwl_isr(int irq, void *data)
  1655. {
  1656. struct iwl_priv *priv = data;
  1657. u32 inta, inta_mask;
  1658. #ifdef CONFIG_IWLWIFI_DEBUG
  1659. u32 inta_fh;
  1660. #endif
  1661. if (!priv)
  1662. return IRQ_NONE;
  1663. spin_lock(&priv->lock);
  1664. /* Disable (but don't clear!) interrupts here to avoid
  1665. * back-to-back ISRs and sporadic interrupts from our NIC.
  1666. * If we have something to service, the tasklet will re-enable ints.
  1667. * If we *don't* have something, we'll re-enable before leaving here. */
  1668. inta_mask = iwl_read32(priv, CSR_INT_MASK); /* just for debug */
  1669. iwl_write32(priv, CSR_INT_MASK, 0x00000000);
  1670. /* Discover which interrupts are active/pending */
  1671. inta = iwl_read32(priv, CSR_INT);
  1672. /* Ignore interrupt if there's nothing in NIC to service.
  1673. * This may be due to IRQ shared with another device,
  1674. * or due to sporadic interrupts thrown from our NIC. */
  1675. if (!inta) {
  1676. IWL_DEBUG_ISR(priv, "Ignore interrupt, inta == 0\n");
  1677. goto none;
  1678. }
  1679. if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
  1680. /* Hardware disappeared. It might have already raised
  1681. * an interrupt */
  1682. IWL_WARN(priv, "HARDWARE GONE?? INTA == 0x%08x\n", inta);
  1683. goto unplugged;
  1684. }
  1685. #ifdef CONFIG_IWLWIFI_DEBUG
  1686. if (iwl_debug_level & (IWL_DL_ISR)) {
  1687. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  1688. IWL_DEBUG_ISR(priv, "ISR inta 0x%08x, enabled 0x%08x, "
  1689. "fh 0x%08x\n", inta, inta_mask, inta_fh);
  1690. }
  1691. #endif
  1692. priv->inta |= inta;
  1693. /* iwl_irq_tasklet() will service interrupts and re-enable them */
  1694. if (likely(inta))
  1695. tasklet_schedule(&priv->irq_tasklet);
  1696. else if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->inta)
  1697. iwl_enable_interrupts(priv);
  1698. unplugged:
  1699. spin_unlock(&priv->lock);
  1700. return IRQ_HANDLED;
  1701. none:
  1702. /* re-enable interrupts here since we don't have anything to service. */
  1703. /* only Re-enable if diabled by irq and no schedules tasklet. */
  1704. if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->inta)
  1705. iwl_enable_interrupts(priv);
  1706. spin_unlock(&priv->lock);
  1707. return IRQ_NONE;
  1708. }
  1709. irqreturn_t iwl_isr_legacy(int irq, void *data)
  1710. {
  1711. struct iwl_priv *priv = data;
  1712. u32 inta, inta_mask;
  1713. u32 inta_fh;
  1714. if (!priv)
  1715. return IRQ_NONE;
  1716. spin_lock(&priv->lock);
  1717. /* Disable (but don't clear!) interrupts here to avoid
  1718. * back-to-back ISRs and sporadic interrupts from our NIC.
  1719. * If we have something to service, the tasklet will re-enable ints.
  1720. * If we *don't* have something, we'll re-enable before leaving here. */
  1721. inta_mask = iwl_read32(priv, CSR_INT_MASK); /* just for debug */
  1722. iwl_write32(priv, CSR_INT_MASK, 0x00000000);
  1723. /* Discover which interrupts are active/pending */
  1724. inta = iwl_read32(priv, CSR_INT);
  1725. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  1726. /* Ignore interrupt if there's nothing in NIC to service.
  1727. * This may be due to IRQ shared with another device,
  1728. * or due to sporadic interrupts thrown from our NIC. */
  1729. if (!inta && !inta_fh) {
  1730. IWL_DEBUG_ISR(priv, "Ignore interrupt, inta == 0, inta_fh == 0\n");
  1731. goto none;
  1732. }
  1733. if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
  1734. /* Hardware disappeared. It might have already raised
  1735. * an interrupt */
  1736. IWL_WARN(priv, "HARDWARE GONE?? INTA == 0x%08x\n", inta);
  1737. goto unplugged;
  1738. }
  1739. IWL_DEBUG_ISR(priv, "ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
  1740. inta, inta_mask, inta_fh);
  1741. inta &= ~CSR_INT_BIT_SCD;
  1742. /* iwl_irq_tasklet() will service interrupts and re-enable them */
  1743. if (likely(inta || inta_fh))
  1744. tasklet_schedule(&priv->irq_tasklet);
  1745. unplugged:
  1746. spin_unlock(&priv->lock);
  1747. return IRQ_HANDLED;
  1748. none:
  1749. /* re-enable interrupts here since we don't have anything to service. */
  1750. /* only Re-enable if diabled by irq */
  1751. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  1752. iwl_enable_interrupts(priv);
  1753. spin_unlock(&priv->lock);
  1754. return IRQ_NONE;
  1755. }
  1756. EXPORT_SYMBOL(iwl_isr_legacy);
  1757. int iwl_send_bt_config(struct iwl_priv *priv)
  1758. {
  1759. struct iwl_bt_cmd bt_cmd = {
  1760. .flags = 3,
  1761. .lead_time = 0xAA,
  1762. .max_kill = 1,
  1763. .kill_ack_mask = 0,
  1764. .kill_cts_mask = 0,
  1765. };
  1766. return iwl_send_cmd_pdu(priv, REPLY_BT_CONFIG,
  1767. sizeof(struct iwl_bt_cmd), &bt_cmd);
  1768. }
  1769. EXPORT_SYMBOL(iwl_send_bt_config);
  1770. int iwl_send_statistics_request(struct iwl_priv *priv, u8 flags)
  1771. {
  1772. u32 stat_flags = 0;
  1773. struct iwl_host_cmd cmd = {
  1774. .id = REPLY_STATISTICS_CMD,
  1775. .meta.flags = flags,
  1776. .len = sizeof(stat_flags),
  1777. .data = (u8 *) &stat_flags,
  1778. };
  1779. return iwl_send_cmd(priv, &cmd);
  1780. }
  1781. EXPORT_SYMBOL(iwl_send_statistics_request);
  1782. /**
  1783. * iwl_verify_inst_sparse - verify runtime uCode image in card vs. host,
  1784. * using sample data 100 bytes apart. If these sample points are good,
  1785. * it's a pretty good bet that everything between them is good, too.
  1786. */
  1787. static int iwlcore_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32 len)
  1788. {
  1789. u32 val;
  1790. int ret = 0;
  1791. u32 errcnt = 0;
  1792. u32 i;
  1793. IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len);
  1794. for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
  1795. /* read data comes through single port, auto-incr addr */
  1796. /* NOTE: Use the debugless read so we don't flood kernel log
  1797. * if IWL_DL_IO is set */
  1798. iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
  1799. i + IWL49_RTC_INST_LOWER_BOUND);
  1800. val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  1801. if (val != le32_to_cpu(*image)) {
  1802. ret = -EIO;
  1803. errcnt++;
  1804. if (errcnt >= 3)
  1805. break;
  1806. }
  1807. }
  1808. return ret;
  1809. }
  1810. /**
  1811. * iwlcore_verify_inst_full - verify runtime uCode image in card vs. host,
  1812. * looking at all data.
  1813. */
  1814. static int iwl_verify_inst_full(struct iwl_priv *priv, __le32 *image,
  1815. u32 len)
  1816. {
  1817. u32 val;
  1818. u32 save_len = len;
  1819. int ret = 0;
  1820. u32 errcnt;
  1821. IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len);
  1822. iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
  1823. IWL49_RTC_INST_LOWER_BOUND);
  1824. errcnt = 0;
  1825. for (; len > 0; len -= sizeof(u32), image++) {
  1826. /* read data comes through single port, auto-incr addr */
  1827. /* NOTE: Use the debugless read so we don't flood kernel log
  1828. * if IWL_DL_IO is set */
  1829. val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  1830. if (val != le32_to_cpu(*image)) {
  1831. IWL_ERR(priv, "uCode INST section is invalid at "
  1832. "offset 0x%x, is 0x%x, s/b 0x%x\n",
  1833. save_len - len, val, le32_to_cpu(*image));
  1834. ret = -EIO;
  1835. errcnt++;
  1836. if (errcnt >= 20)
  1837. break;
  1838. }
  1839. }
  1840. if (!errcnt)
  1841. IWL_DEBUG_INFO(priv,
  1842. "ucode image in INSTRUCTION memory is good\n");
  1843. return ret;
  1844. }
  1845. /**
  1846. * iwl_verify_ucode - determine which instruction image is in SRAM,
  1847. * and verify its contents
  1848. */
  1849. int iwl_verify_ucode(struct iwl_priv *priv)
  1850. {
  1851. __le32 *image;
  1852. u32 len;
  1853. int ret;
  1854. /* Try bootstrap */
  1855. image = (__le32 *)priv->ucode_boot.v_addr;
  1856. len = priv->ucode_boot.len;
  1857. ret = iwlcore_verify_inst_sparse(priv, image, len);
  1858. if (!ret) {
  1859. IWL_DEBUG_INFO(priv, "Bootstrap uCode is good in inst SRAM\n");
  1860. return 0;
  1861. }
  1862. /* Try initialize */
  1863. image = (__le32 *)priv->ucode_init.v_addr;
  1864. len = priv->ucode_init.len;
  1865. ret = iwlcore_verify_inst_sparse(priv, image, len);
  1866. if (!ret) {
  1867. IWL_DEBUG_INFO(priv, "Initialize uCode is good in inst SRAM\n");
  1868. return 0;
  1869. }
  1870. /* Try runtime/protocol */
  1871. image = (__le32 *)priv->ucode_code.v_addr;
  1872. len = priv->ucode_code.len;
  1873. ret = iwlcore_verify_inst_sparse(priv, image, len);
  1874. if (!ret) {
  1875. IWL_DEBUG_INFO(priv, "Runtime uCode is good in inst SRAM\n");
  1876. return 0;
  1877. }
  1878. IWL_ERR(priv, "NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
  1879. /* Since nothing seems to match, show first several data entries in
  1880. * instruction SRAM, so maybe visual inspection will give a clue.
  1881. * Selection of bootstrap image (vs. other images) is arbitrary. */
  1882. image = (__le32 *)priv->ucode_boot.v_addr;
  1883. len = priv->ucode_boot.len;
  1884. ret = iwl_verify_inst_full(priv, image, len);
  1885. return ret;
  1886. }
  1887. EXPORT_SYMBOL(iwl_verify_ucode);
  1888. void iwl_rf_kill_ct_config(struct iwl_priv *priv)
  1889. {
  1890. struct iwl_ct_kill_config cmd;
  1891. unsigned long flags;
  1892. int ret = 0;
  1893. spin_lock_irqsave(&priv->lock, flags);
  1894. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  1895. CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
  1896. spin_unlock_irqrestore(&priv->lock, flags);
  1897. cmd.critical_temperature_R =
  1898. cpu_to_le32(priv->hw_params.ct_kill_threshold);
  1899. ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
  1900. sizeof(cmd), &cmd);
  1901. if (ret)
  1902. IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
  1903. else
  1904. IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD succeeded, "
  1905. "critical temperature is %d\n",
  1906. cmd.critical_temperature_R);
  1907. }
  1908. EXPORT_SYMBOL(iwl_rf_kill_ct_config);
  1909. /*
  1910. * CARD_STATE_CMD
  1911. *
  1912. * Use: Sets the device's internal card state to enable, disable, or halt
  1913. *
  1914. * When in the 'enable' state the card operates as normal.
  1915. * When in the 'disable' state, the card enters into a low power mode.
  1916. * When in the 'halt' state, the card is shut down and must be fully
  1917. * restarted to come back on.
  1918. */
  1919. int iwl_send_card_state(struct iwl_priv *priv, u32 flags, u8 meta_flag)
  1920. {
  1921. struct iwl_host_cmd cmd = {
  1922. .id = REPLY_CARD_STATE_CMD,
  1923. .len = sizeof(u32),
  1924. .data = &flags,
  1925. .meta.flags = meta_flag,
  1926. };
  1927. return iwl_send_cmd(priv, &cmd);
  1928. }
  1929. EXPORT_SYMBOL(iwl_send_card_state);
  1930. void iwl_rx_pm_sleep_notif(struct iwl_priv *priv,
  1931. struct iwl_rx_mem_buffer *rxb)
  1932. {
  1933. #ifdef CONFIG_IWLWIFI_DEBUG
  1934. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  1935. struct iwl_sleep_notification *sleep = &(pkt->u.sleep_notif);
  1936. IWL_DEBUG_RX(priv, "sleep mode: %d, src: %d\n",
  1937. sleep->pm_sleep_mode, sleep->pm_wakeup_src);
  1938. #endif
  1939. }
  1940. EXPORT_SYMBOL(iwl_rx_pm_sleep_notif);
  1941. void iwl_rx_pm_debug_statistics_notif(struct iwl_priv *priv,
  1942. struct iwl_rx_mem_buffer *rxb)
  1943. {
  1944. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  1945. IWL_DEBUG_RADIO(priv, "Dumping %d bytes of unhandled "
  1946. "notification for %s:\n",
  1947. le32_to_cpu(pkt->len), get_cmd_string(pkt->hdr.cmd));
  1948. iwl_print_hex_dump(IWL_DL_RADIO, pkt->u.raw, le32_to_cpu(pkt->len));
  1949. }
  1950. EXPORT_SYMBOL(iwl_rx_pm_debug_statistics_notif);
  1951. void iwl_rx_reply_error(struct iwl_priv *priv,
  1952. struct iwl_rx_mem_buffer *rxb)
  1953. {
  1954. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  1955. IWL_ERR(priv, "Error Reply type 0x%08X cmd %s (0x%02X) "
  1956. "seq 0x%04X ser 0x%08X\n",
  1957. le32_to_cpu(pkt->u.err_resp.error_type),
  1958. get_cmd_string(pkt->u.err_resp.cmd_id),
  1959. pkt->u.err_resp.cmd_id,
  1960. le16_to_cpu(pkt->u.err_resp.bad_cmd_seq_num),
  1961. le32_to_cpu(pkt->u.err_resp.error_info));
  1962. }
  1963. EXPORT_SYMBOL(iwl_rx_reply_error);
  1964. void iwl_clear_isr_stats(struct iwl_priv *priv)
  1965. {
  1966. memset(&priv->isr_stats, 0, sizeof(priv->isr_stats));
  1967. }
  1968. EXPORT_SYMBOL(iwl_clear_isr_stats);
  1969. int iwl_mac_conf_tx(struct ieee80211_hw *hw, u16 queue,
  1970. const struct ieee80211_tx_queue_params *params)
  1971. {
  1972. struct iwl_priv *priv = hw->priv;
  1973. unsigned long flags;
  1974. int q;
  1975. IWL_DEBUG_MAC80211(priv, "enter\n");
  1976. if (!iwl_is_ready_rf(priv)) {
  1977. IWL_DEBUG_MAC80211(priv, "leave - RF not ready\n");
  1978. return -EIO;
  1979. }
  1980. if (queue >= AC_NUM) {
  1981. IWL_DEBUG_MAC80211(priv, "leave - queue >= AC_NUM %d\n", queue);
  1982. return 0;
  1983. }
  1984. q = AC_NUM - 1 - queue;
  1985. spin_lock_irqsave(&priv->lock, flags);
  1986. priv->qos_data.def_qos_parm.ac[q].cw_min = cpu_to_le16(params->cw_min);
  1987. priv->qos_data.def_qos_parm.ac[q].cw_max = cpu_to_le16(params->cw_max);
  1988. priv->qos_data.def_qos_parm.ac[q].aifsn = params->aifs;
  1989. priv->qos_data.def_qos_parm.ac[q].edca_txop =
  1990. cpu_to_le16((params->txop * 32));
  1991. priv->qos_data.def_qos_parm.ac[q].reserved1 = 0;
  1992. priv->qos_data.qos_active = 1;
  1993. if (priv->iw_mode == NL80211_IFTYPE_AP)
  1994. iwl_activate_qos(priv, 1);
  1995. else if (priv->assoc_id && iwl_is_associated(priv))
  1996. iwl_activate_qos(priv, 0);
  1997. spin_unlock_irqrestore(&priv->lock, flags);
  1998. IWL_DEBUG_MAC80211(priv, "leave\n");
  1999. return 0;
  2000. }
  2001. EXPORT_SYMBOL(iwl_mac_conf_tx);
  2002. static void iwl_ht_conf(struct iwl_priv *priv,
  2003. struct ieee80211_bss_conf *bss_conf)
  2004. {
  2005. struct ieee80211_sta_ht_cap *ht_conf;
  2006. struct iwl_ht_info *iwl_conf = &priv->current_ht_config;
  2007. struct ieee80211_sta *sta;
  2008. IWL_DEBUG_MAC80211(priv, "enter: \n");
  2009. if (!iwl_conf->is_ht)
  2010. return;
  2011. /*
  2012. * It is totally wrong to base global information on something
  2013. * that is valid only when associated, alas, this driver works
  2014. * that way and I don't know how to fix it.
  2015. */
  2016. rcu_read_lock();
  2017. sta = ieee80211_find_sta(priv->hw, priv->bssid);
  2018. if (!sta) {
  2019. rcu_read_unlock();
  2020. return;
  2021. }
  2022. ht_conf = &sta->ht_cap;
  2023. if (ht_conf->cap & IEEE80211_HT_CAP_SGI_20)
  2024. iwl_conf->sgf |= HT_SHORT_GI_20MHZ;
  2025. if (ht_conf->cap & IEEE80211_HT_CAP_SGI_40)
  2026. iwl_conf->sgf |= HT_SHORT_GI_40MHZ;
  2027. iwl_conf->is_green_field = !!(ht_conf->cap & IEEE80211_HT_CAP_GRN_FLD);
  2028. iwl_conf->max_amsdu_size =
  2029. !!(ht_conf->cap & IEEE80211_HT_CAP_MAX_AMSDU);
  2030. iwl_conf->supported_chan_width =
  2031. !!(ht_conf->cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40);
  2032. /*
  2033. * XXX: The HT configuration needs to be moved into iwl_mac_config()
  2034. * to be done there correctly.
  2035. */
  2036. iwl_conf->extension_chan_offset = IEEE80211_HT_PARAM_CHA_SEC_NONE;
  2037. if (conf_is_ht40_minus(&priv->hw->conf))
  2038. iwl_conf->extension_chan_offset = IEEE80211_HT_PARAM_CHA_SEC_BELOW;
  2039. else if (conf_is_ht40_plus(&priv->hw->conf))
  2040. iwl_conf->extension_chan_offset = IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
  2041. /* If no above or below channel supplied disable FAT channel */
  2042. if (iwl_conf->extension_chan_offset != IEEE80211_HT_PARAM_CHA_SEC_ABOVE &&
  2043. iwl_conf->extension_chan_offset != IEEE80211_HT_PARAM_CHA_SEC_BELOW)
  2044. iwl_conf->supported_chan_width = 0;
  2045. iwl_conf->sm_ps = (u8)((ht_conf->cap & IEEE80211_HT_CAP_SM_PS) >> 2);
  2046. memcpy(&iwl_conf->mcs, &ht_conf->mcs, 16);
  2047. iwl_conf->tx_chan_width = iwl_conf->supported_chan_width != 0;
  2048. iwl_conf->ht_protection =
  2049. bss_conf->ht_operation_mode & IEEE80211_HT_OP_MODE_PROTECTION;
  2050. iwl_conf->non_GF_STA_present =
  2051. !!(bss_conf->ht_operation_mode & IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
  2052. rcu_read_unlock();
  2053. IWL_DEBUG_MAC80211(priv, "leave\n");
  2054. }
  2055. #define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
  2056. void iwl_bss_info_changed(struct ieee80211_hw *hw,
  2057. struct ieee80211_vif *vif,
  2058. struct ieee80211_bss_conf *bss_conf,
  2059. u32 changes)
  2060. {
  2061. struct iwl_priv *priv = hw->priv;
  2062. int ret;
  2063. IWL_DEBUG_MAC80211(priv, "changes = 0x%X\n", changes);
  2064. if (!iwl_is_alive(priv))
  2065. return;
  2066. mutex_lock(&priv->mutex);
  2067. if (changes & BSS_CHANGED_BEACON &&
  2068. priv->iw_mode == NL80211_IFTYPE_AP) {
  2069. dev_kfree_skb(priv->ibss_beacon);
  2070. priv->ibss_beacon = ieee80211_beacon_get(hw, vif);
  2071. }
  2072. if (changes & BSS_CHANGED_BEACON_INT) {
  2073. priv->beacon_int = bss_conf->beacon_int;
  2074. /* TODO: in AP mode, do something to make this take effect */
  2075. }
  2076. if (changes & BSS_CHANGED_BSSID) {
  2077. IWL_DEBUG_MAC80211(priv, "BSSID %pM\n", bss_conf->bssid);
  2078. /*
  2079. * If there is currently a HW scan going on in the
  2080. * background then we need to cancel it else the RXON
  2081. * below/in post_associate will fail.
  2082. */
  2083. if (iwl_scan_cancel_timeout(priv, 100)) {
  2084. IWL_WARN(priv, "Aborted scan still in progress after 100ms\n");
  2085. IWL_DEBUG_MAC80211(priv, "leaving - scan abort failed.\n");
  2086. mutex_unlock(&priv->mutex);
  2087. return;
  2088. }
  2089. /* mac80211 only sets assoc when in STATION mode */
  2090. if (priv->iw_mode == NL80211_IFTYPE_ADHOC ||
  2091. bss_conf->assoc) {
  2092. memcpy(priv->staging_rxon.bssid_addr,
  2093. bss_conf->bssid, ETH_ALEN);
  2094. /* currently needed in a few places */
  2095. memcpy(priv->bssid, bss_conf->bssid, ETH_ALEN);
  2096. } else {
  2097. priv->staging_rxon.filter_flags &=
  2098. ~RXON_FILTER_ASSOC_MSK;
  2099. }
  2100. }
  2101. /*
  2102. * This needs to be after setting the BSSID in case
  2103. * mac80211 decides to do both changes at once because
  2104. * it will invoke post_associate.
  2105. */
  2106. if (priv->iw_mode == NL80211_IFTYPE_ADHOC &&
  2107. changes & BSS_CHANGED_BEACON) {
  2108. struct sk_buff *beacon = ieee80211_beacon_get(hw, vif);
  2109. if (beacon)
  2110. iwl_mac_beacon_update(hw, beacon);
  2111. }
  2112. if (changes & BSS_CHANGED_ERP_PREAMBLE) {
  2113. IWL_DEBUG_MAC80211(priv, "ERP_PREAMBLE %d\n",
  2114. bss_conf->use_short_preamble);
  2115. if (bss_conf->use_short_preamble)
  2116. priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  2117. else
  2118. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  2119. }
  2120. if (changes & BSS_CHANGED_ERP_CTS_PROT) {
  2121. IWL_DEBUG_MAC80211(priv, "ERP_CTS %d\n", bss_conf->use_cts_prot);
  2122. if (bss_conf->use_cts_prot && (priv->band != IEEE80211_BAND_5GHZ))
  2123. priv->staging_rxon.flags |= RXON_FLG_TGG_PROTECT_MSK;
  2124. else
  2125. priv->staging_rxon.flags &= ~RXON_FLG_TGG_PROTECT_MSK;
  2126. }
  2127. if (changes & BSS_CHANGED_BASIC_RATES) {
  2128. /* XXX use this information
  2129. *
  2130. * To do that, remove code from iwl_set_rate() and put something
  2131. * like this here:
  2132. *
  2133. if (A-band)
  2134. priv->staging_rxon.ofdm_basic_rates =
  2135. bss_conf->basic_rates;
  2136. else
  2137. priv->staging_rxon.ofdm_basic_rates =
  2138. bss_conf->basic_rates >> 4;
  2139. priv->staging_rxon.cck_basic_rates =
  2140. bss_conf->basic_rates & 0xF;
  2141. */
  2142. }
  2143. if (changes & BSS_CHANGED_HT) {
  2144. iwl_ht_conf(priv, bss_conf);
  2145. if (priv->cfg->ops->hcmd->set_rxon_chain)
  2146. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  2147. }
  2148. if (changes & BSS_CHANGED_ASSOC) {
  2149. IWL_DEBUG_MAC80211(priv, "ASSOC %d\n", bss_conf->assoc);
  2150. if (bss_conf->assoc) {
  2151. priv->assoc_id = bss_conf->aid;
  2152. priv->beacon_int = bss_conf->beacon_int;
  2153. priv->power_data.dtim_period = bss_conf->dtim_period;
  2154. priv->timestamp = bss_conf->timestamp;
  2155. priv->assoc_capability = bss_conf->assoc_capability;
  2156. /*
  2157. * We have just associated, don't start scan too early
  2158. * leave time for EAPOL exchange to complete.
  2159. *
  2160. * XXX: do this in mac80211
  2161. */
  2162. priv->next_scan_jiffies = jiffies +
  2163. IWL_DELAY_NEXT_SCAN_AFTER_ASSOC;
  2164. if (!iwl_is_rfkill(priv))
  2165. priv->cfg->ops->lib->post_associate(priv);
  2166. } else
  2167. priv->assoc_id = 0;
  2168. }
  2169. if (changes && iwl_is_associated(priv) && priv->assoc_id) {
  2170. IWL_DEBUG_MAC80211(priv, "Changes (%#x) while associated\n",
  2171. changes);
  2172. ret = iwl_send_rxon_assoc(priv);
  2173. if (!ret) {
  2174. /* Sync active_rxon with latest change. */
  2175. memcpy((void *)&priv->active_rxon,
  2176. &priv->staging_rxon,
  2177. sizeof(struct iwl_rxon_cmd));
  2178. }
  2179. }
  2180. mutex_unlock(&priv->mutex);
  2181. IWL_DEBUG_MAC80211(priv, "leave\n");
  2182. }
  2183. EXPORT_SYMBOL(iwl_bss_info_changed);
  2184. int iwl_mac_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb)
  2185. {
  2186. struct iwl_priv *priv = hw->priv;
  2187. unsigned long flags;
  2188. __le64 timestamp;
  2189. IWL_DEBUG_MAC80211(priv, "enter\n");
  2190. if (!iwl_is_ready_rf(priv)) {
  2191. IWL_DEBUG_MAC80211(priv, "leave - RF not ready\n");
  2192. return -EIO;
  2193. }
  2194. if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
  2195. IWL_DEBUG_MAC80211(priv, "leave - not IBSS\n");
  2196. return -EIO;
  2197. }
  2198. spin_lock_irqsave(&priv->lock, flags);
  2199. if (priv->ibss_beacon)
  2200. dev_kfree_skb(priv->ibss_beacon);
  2201. priv->ibss_beacon = skb;
  2202. priv->assoc_id = 0;
  2203. timestamp = ((struct ieee80211_mgmt *)skb->data)->u.beacon.timestamp;
  2204. priv->timestamp = le64_to_cpu(timestamp);
  2205. IWL_DEBUG_MAC80211(priv, "leave\n");
  2206. spin_unlock_irqrestore(&priv->lock, flags);
  2207. iwl_reset_qos(priv);
  2208. priv->cfg->ops->lib->post_associate(priv);
  2209. return 0;
  2210. }
  2211. EXPORT_SYMBOL(iwl_mac_beacon_update);
  2212. int iwl_set_mode(struct iwl_priv *priv, int mode)
  2213. {
  2214. if (mode == NL80211_IFTYPE_ADHOC) {
  2215. const struct iwl_channel_info *ch_info;
  2216. ch_info = iwl_get_channel_info(priv,
  2217. priv->band,
  2218. le16_to_cpu(priv->staging_rxon.channel));
  2219. if (!ch_info || !is_channel_ibss(ch_info)) {
  2220. IWL_ERR(priv, "channel %d not IBSS channel\n",
  2221. le16_to_cpu(priv->staging_rxon.channel));
  2222. return -EINVAL;
  2223. }
  2224. }
  2225. iwl_connection_init_rx_config(priv, mode);
  2226. if (priv->cfg->ops->hcmd->set_rxon_chain)
  2227. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  2228. memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
  2229. iwl_clear_stations_table(priv);
  2230. /* dont commit rxon if rf-kill is on*/
  2231. if (!iwl_is_ready_rf(priv))
  2232. return -EAGAIN;
  2233. iwlcore_commit_rxon(priv);
  2234. return 0;
  2235. }
  2236. EXPORT_SYMBOL(iwl_set_mode);
  2237. int iwl_mac_add_interface(struct ieee80211_hw *hw,
  2238. struct ieee80211_if_init_conf *conf)
  2239. {
  2240. struct iwl_priv *priv = hw->priv;
  2241. unsigned long flags;
  2242. IWL_DEBUG_MAC80211(priv, "enter: type %d\n", conf->type);
  2243. if (priv->vif) {
  2244. IWL_DEBUG_MAC80211(priv, "leave - vif != NULL\n");
  2245. return -EOPNOTSUPP;
  2246. }
  2247. spin_lock_irqsave(&priv->lock, flags);
  2248. priv->vif = conf->vif;
  2249. priv->iw_mode = conf->type;
  2250. spin_unlock_irqrestore(&priv->lock, flags);
  2251. mutex_lock(&priv->mutex);
  2252. if (conf->mac_addr) {
  2253. IWL_DEBUG_MAC80211(priv, "Set %pM\n", conf->mac_addr);
  2254. memcpy(priv->mac_addr, conf->mac_addr, ETH_ALEN);
  2255. }
  2256. if (iwl_set_mode(priv, conf->type) == -EAGAIN)
  2257. /* we are not ready, will run again when ready */
  2258. set_bit(STATUS_MODE_PENDING, &priv->status);
  2259. mutex_unlock(&priv->mutex);
  2260. IWL_DEBUG_MAC80211(priv, "leave\n");
  2261. return 0;
  2262. }
  2263. EXPORT_SYMBOL(iwl_mac_add_interface);
  2264. void iwl_mac_remove_interface(struct ieee80211_hw *hw,
  2265. struct ieee80211_if_init_conf *conf)
  2266. {
  2267. struct iwl_priv *priv = hw->priv;
  2268. IWL_DEBUG_MAC80211(priv, "enter\n");
  2269. mutex_lock(&priv->mutex);
  2270. if (iwl_is_ready_rf(priv)) {
  2271. iwl_scan_cancel_timeout(priv, 100);
  2272. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  2273. iwlcore_commit_rxon(priv);
  2274. }
  2275. if (priv->vif == conf->vif) {
  2276. priv->vif = NULL;
  2277. memset(priv->bssid, 0, ETH_ALEN);
  2278. }
  2279. mutex_unlock(&priv->mutex);
  2280. IWL_DEBUG_MAC80211(priv, "leave\n");
  2281. }
  2282. EXPORT_SYMBOL(iwl_mac_remove_interface);
  2283. /**
  2284. * iwl_mac_config - mac80211 config callback
  2285. *
  2286. * We ignore conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME since it seems to
  2287. * be set inappropriately and the driver currently sets the hardware up to
  2288. * use it whenever needed.
  2289. */
  2290. int iwl_mac_config(struct ieee80211_hw *hw, u32 changed)
  2291. {
  2292. struct iwl_priv *priv = hw->priv;
  2293. const struct iwl_channel_info *ch_info;
  2294. struct ieee80211_conf *conf = &hw->conf;
  2295. unsigned long flags = 0;
  2296. int ret = 0;
  2297. u16 ch;
  2298. int scan_active = 0;
  2299. mutex_lock(&priv->mutex);
  2300. IWL_DEBUG_MAC80211(priv, "enter to channel %d changed 0x%X\n",
  2301. conf->channel->hw_value, changed);
  2302. if (unlikely(!priv->cfg->mod_params->disable_hw_scan &&
  2303. test_bit(STATUS_SCANNING, &priv->status))) {
  2304. scan_active = 1;
  2305. IWL_DEBUG_MAC80211(priv, "leave - scanning\n");
  2306. }
  2307. /* during scanning mac80211 will delay channel setting until
  2308. * scan finish with changed = 0
  2309. */
  2310. if (!changed || (changed & IEEE80211_CONF_CHANGE_CHANNEL)) {
  2311. if (scan_active)
  2312. goto set_ch_out;
  2313. ch = ieee80211_frequency_to_channel(conf->channel->center_freq);
  2314. ch_info = iwl_get_channel_info(priv, conf->channel->band, ch);
  2315. if (!is_channel_valid(ch_info)) {
  2316. IWL_DEBUG_MAC80211(priv, "leave - invalid channel\n");
  2317. ret = -EINVAL;
  2318. goto set_ch_out;
  2319. }
  2320. if (priv->iw_mode == NL80211_IFTYPE_ADHOC &&
  2321. !is_channel_ibss(ch_info)) {
  2322. IWL_ERR(priv, "channel %d in band %d not "
  2323. "IBSS channel\n",
  2324. conf->channel->hw_value, conf->channel->band);
  2325. ret = -EINVAL;
  2326. goto set_ch_out;
  2327. }
  2328. priv->current_ht_config.is_ht = conf_is_ht(conf);
  2329. spin_lock_irqsave(&priv->lock, flags);
  2330. /* if we are switching from ht to 2.4 clear flags
  2331. * from any ht related info since 2.4 does not
  2332. * support ht */
  2333. if ((le16_to_cpu(priv->staging_rxon.channel) != ch))
  2334. priv->staging_rxon.flags = 0;
  2335. iwl_set_rxon_channel(priv, conf->channel);
  2336. iwl_set_flags_for_band(priv, conf->channel->band);
  2337. spin_unlock_irqrestore(&priv->lock, flags);
  2338. set_ch_out:
  2339. /* The list of supported rates and rate mask can be different
  2340. * for each band; since the band may have changed, reset
  2341. * the rate mask to what mac80211 lists */
  2342. iwl_set_rate(priv);
  2343. }
  2344. if (changed & IEEE80211_CONF_CHANGE_PS &&
  2345. priv->iw_mode == NL80211_IFTYPE_STATION) {
  2346. priv->power_data.power_disabled =
  2347. !(conf->flags & IEEE80211_CONF_PS);
  2348. ret = iwl_power_update_mode(priv, 0);
  2349. if (ret)
  2350. IWL_DEBUG_MAC80211(priv, "Error setting power level\n");
  2351. }
  2352. if (changed & IEEE80211_CONF_CHANGE_POWER) {
  2353. IWL_DEBUG_MAC80211(priv, "TX Power old=%d new=%d\n",
  2354. priv->tx_power_user_lmt, conf->power_level);
  2355. iwl_set_tx_power(priv, conf->power_level, false);
  2356. }
  2357. /* call to ensure that 4965 rx_chain is set properly in monitor mode */
  2358. if (priv->cfg->ops->hcmd->set_rxon_chain)
  2359. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  2360. if (!iwl_is_ready(priv)) {
  2361. IWL_DEBUG_MAC80211(priv, "leave - not ready\n");
  2362. goto out;
  2363. }
  2364. if (scan_active)
  2365. goto out;
  2366. if (memcmp(&priv->active_rxon,
  2367. &priv->staging_rxon, sizeof(priv->staging_rxon)))
  2368. iwlcore_commit_rxon(priv);
  2369. else
  2370. IWL_DEBUG_INFO(priv, "Not re-sending same RXON configuration.\n");
  2371. out:
  2372. IWL_DEBUG_MAC80211(priv, "leave\n");
  2373. mutex_unlock(&priv->mutex);
  2374. return ret;
  2375. }
  2376. EXPORT_SYMBOL(iwl_mac_config);
  2377. int iwl_mac_get_tx_stats(struct ieee80211_hw *hw,
  2378. struct ieee80211_tx_queue_stats *stats)
  2379. {
  2380. struct iwl_priv *priv = hw->priv;
  2381. int i, avail;
  2382. struct iwl_tx_queue *txq;
  2383. struct iwl_queue *q;
  2384. unsigned long flags;
  2385. IWL_DEBUG_MAC80211(priv, "enter\n");
  2386. if (!iwl_is_ready_rf(priv)) {
  2387. IWL_DEBUG_MAC80211(priv, "leave - RF not ready\n");
  2388. return -EIO;
  2389. }
  2390. spin_lock_irqsave(&priv->lock, flags);
  2391. for (i = 0; i < AC_NUM; i++) {
  2392. txq = &priv->txq[i];
  2393. q = &txq->q;
  2394. avail = iwl_queue_space(q);
  2395. stats[i].len = q->n_window - avail;
  2396. stats[i].limit = q->n_window - q->high_mark;
  2397. stats[i].count = q->n_window;
  2398. }
  2399. spin_unlock_irqrestore(&priv->lock, flags);
  2400. IWL_DEBUG_MAC80211(priv, "leave\n");
  2401. return 0;
  2402. }
  2403. EXPORT_SYMBOL(iwl_mac_get_tx_stats);
  2404. void iwl_mac_reset_tsf(struct ieee80211_hw *hw)
  2405. {
  2406. struct iwl_priv *priv = hw->priv;
  2407. unsigned long flags;
  2408. mutex_lock(&priv->mutex);
  2409. IWL_DEBUG_MAC80211(priv, "enter\n");
  2410. spin_lock_irqsave(&priv->lock, flags);
  2411. memset(&priv->current_ht_config, 0, sizeof(struct iwl_ht_info));
  2412. spin_unlock_irqrestore(&priv->lock, flags);
  2413. iwl_reset_qos(priv);
  2414. spin_lock_irqsave(&priv->lock, flags);
  2415. priv->assoc_id = 0;
  2416. priv->assoc_capability = 0;
  2417. priv->assoc_station_added = 0;
  2418. /* new association get rid of ibss beacon skb */
  2419. if (priv->ibss_beacon)
  2420. dev_kfree_skb(priv->ibss_beacon);
  2421. priv->ibss_beacon = NULL;
  2422. priv->beacon_int = priv->vif->bss_conf.beacon_int;
  2423. priv->timestamp = 0;
  2424. if ((priv->iw_mode == NL80211_IFTYPE_STATION))
  2425. priv->beacon_int = 0;
  2426. spin_unlock_irqrestore(&priv->lock, flags);
  2427. if (!iwl_is_ready_rf(priv)) {
  2428. IWL_DEBUG_MAC80211(priv, "leave - not ready\n");
  2429. mutex_unlock(&priv->mutex);
  2430. return;
  2431. }
  2432. /* we are restarting association process
  2433. * clear RXON_FILTER_ASSOC_MSK bit
  2434. */
  2435. if (priv->iw_mode != NL80211_IFTYPE_AP) {
  2436. iwl_scan_cancel_timeout(priv, 100);
  2437. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  2438. iwlcore_commit_rxon(priv);
  2439. }
  2440. if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
  2441. IWL_DEBUG_MAC80211(priv, "leave - not in IBSS\n");
  2442. mutex_unlock(&priv->mutex);
  2443. return;
  2444. }
  2445. iwl_set_rate(priv);
  2446. mutex_unlock(&priv->mutex);
  2447. IWL_DEBUG_MAC80211(priv, "leave\n");
  2448. }
  2449. EXPORT_SYMBOL(iwl_mac_reset_tsf);
  2450. #ifdef CONFIG_PM
  2451. int iwl_pci_suspend(struct pci_dev *pdev, pm_message_t state)
  2452. {
  2453. struct iwl_priv *priv = pci_get_drvdata(pdev);
  2454. /*
  2455. * This function is called when system goes into suspend state
  2456. * mac80211 will call iwl_mac_stop() from the mac80211 suspend function
  2457. * first but since iwl_mac_stop() has no knowledge of who the caller is,
  2458. * it will not call apm_ops.stop() to stop the DMA operation.
  2459. * Calling apm_ops.stop here to make sure we stop the DMA.
  2460. */
  2461. priv->cfg->ops->lib->apm_ops.stop(priv);
  2462. pci_save_state(pdev);
  2463. pci_disable_device(pdev);
  2464. pci_set_power_state(pdev, PCI_D3hot);
  2465. return 0;
  2466. }
  2467. EXPORT_SYMBOL(iwl_pci_suspend);
  2468. int iwl_pci_resume(struct pci_dev *pdev)
  2469. {
  2470. struct iwl_priv *priv = pci_get_drvdata(pdev);
  2471. int ret;
  2472. pci_set_power_state(pdev, PCI_D0);
  2473. ret = pci_enable_device(pdev);
  2474. if (ret)
  2475. return ret;
  2476. pci_restore_state(pdev);
  2477. iwl_enable_interrupts(priv);
  2478. return 0;
  2479. }
  2480. EXPORT_SYMBOL(iwl_pci_resume);
  2481. #endif /* CONFIG_PM */