iwl-agn.c 88 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved.
  4. *
  5. * Portions of this file are derived from the ipw3945 project, as well
  6. * as portions of the ieee80211 subsystem header files.
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of version 2 of the GNU General Public License as
  10. * published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15. * more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along with
  18. * this program; if not, write to the Free Software Foundation, Inc.,
  19. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20. *
  21. * The full GNU General Public License is included in this distribution in the
  22. * file called LICENSE.
  23. *
  24. * Contact Information:
  25. * Intel Linux Wireless <ilw@linux.intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *
  28. *****************************************************************************/
  29. #include <linux/kernel.h>
  30. #include <linux/module.h>
  31. #include <linux/init.h>
  32. #include <linux/pci.h>
  33. #include <linux/dma-mapping.h>
  34. #include <linux/delay.h>
  35. #include <linux/skbuff.h>
  36. #include <linux/netdevice.h>
  37. #include <linux/wireless.h>
  38. #include <linux/firmware.h>
  39. #include <linux/etherdevice.h>
  40. #include <linux/if_arp.h>
  41. #include <net/mac80211.h>
  42. #include <asm/div64.h>
  43. #define DRV_NAME "iwlagn"
  44. #include "iwl-eeprom.h"
  45. #include "iwl-dev.h"
  46. #include "iwl-core.h"
  47. #include "iwl-io.h"
  48. #include "iwl-helpers.h"
  49. #include "iwl-sta.h"
  50. #include "iwl-calib.h"
  51. /******************************************************************************
  52. *
  53. * module boiler plate
  54. *
  55. ******************************************************************************/
  56. /*
  57. * module name, copyright, version, etc.
  58. */
  59. #define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
  60. #ifdef CONFIG_IWLWIFI_DEBUG
  61. #define VD "d"
  62. #else
  63. #define VD
  64. #endif
  65. #ifdef CONFIG_IWLWIFI_SPECTRUM_MEASUREMENT
  66. #define VS "s"
  67. #else
  68. #define VS
  69. #endif
  70. #define DRV_VERSION IWLWIFI_VERSION VD VS
  71. MODULE_DESCRIPTION(DRV_DESCRIPTION);
  72. MODULE_VERSION(DRV_VERSION);
  73. MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
  74. MODULE_LICENSE("GPL");
  75. MODULE_ALIAS("iwl4965");
  76. /*************** STATION TABLE MANAGEMENT ****
  77. * mac80211 should be examined to determine if sta_info is duplicating
  78. * the functionality provided here
  79. */
  80. /**************************************************************/
  81. /**
  82. * iwl_commit_rxon - commit staging_rxon to hardware
  83. *
  84. * The RXON command in staging_rxon is committed to the hardware and
  85. * the active_rxon structure is updated with the new data. This
  86. * function correctly transitions out of the RXON_ASSOC_MSK state if
  87. * a HW tune is required based on the RXON structure changes.
  88. */
  89. int iwl_commit_rxon(struct iwl_priv *priv)
  90. {
  91. /* cast away the const for active_rxon in this function */
  92. struct iwl_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
  93. int ret;
  94. bool new_assoc =
  95. !!(priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK);
  96. if (!iwl_is_alive(priv))
  97. return -EBUSY;
  98. /* always get timestamp with Rx frame */
  99. priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
  100. /* allow CTS-to-self if possible. this is relevant only for
  101. * 5000, but will not damage 4965 */
  102. priv->staging_rxon.flags |= RXON_FLG_SELF_CTS_EN;
  103. ret = iwl_check_rxon_cmd(priv);
  104. if (ret) {
  105. IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n");
  106. return -EINVAL;
  107. }
  108. /* If we don't need to send a full RXON, we can use
  109. * iwl_rxon_assoc_cmd which is used to reconfigure filter
  110. * and other flags for the current radio configuration. */
  111. if (!iwl_full_rxon_required(priv)) {
  112. ret = iwl_send_rxon_assoc(priv);
  113. if (ret) {
  114. IWL_ERR(priv, "Error setting RXON_ASSOC (%d)\n", ret);
  115. return ret;
  116. }
  117. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  118. return 0;
  119. }
  120. /* station table will be cleared */
  121. priv->assoc_station_added = 0;
  122. /* If we are currently associated and the new config requires
  123. * an RXON_ASSOC and the new config wants the associated mask enabled,
  124. * we must clear the associated from the active configuration
  125. * before we apply the new config */
  126. if (iwl_is_associated(priv) && new_assoc) {
  127. IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
  128. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  129. ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
  130. sizeof(struct iwl_rxon_cmd),
  131. &priv->active_rxon);
  132. /* If the mask clearing failed then we set
  133. * active_rxon back to what it was previously */
  134. if (ret) {
  135. active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
  136. IWL_ERR(priv, "Error clearing ASSOC_MSK (%d)\n", ret);
  137. return ret;
  138. }
  139. }
  140. IWL_DEBUG_INFO(priv, "Sending RXON\n"
  141. "* with%s RXON_FILTER_ASSOC_MSK\n"
  142. "* channel = %d\n"
  143. "* bssid = %pM\n",
  144. (new_assoc ? "" : "out"),
  145. le16_to_cpu(priv->staging_rxon.channel),
  146. priv->staging_rxon.bssid_addr);
  147. iwl_set_rxon_hwcrypto(priv, !priv->cfg->mod_params->sw_crypto);
  148. /* Apply the new configuration
  149. * RXON unassoc clears the station table in uCode, send it before
  150. * we add the bcast station. If assoc bit is set, we will send RXON
  151. * after having added the bcast and bssid station.
  152. */
  153. if (!new_assoc) {
  154. ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
  155. sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
  156. if (ret) {
  157. IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
  158. return ret;
  159. }
  160. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  161. }
  162. iwl_clear_stations_table(priv);
  163. priv->start_calib = 0;
  164. /* Add the broadcast address so we can send broadcast frames */
  165. if (iwl_rxon_add_station(priv, iwl_bcast_addr, 0) ==
  166. IWL_INVALID_STATION) {
  167. IWL_ERR(priv, "Error adding BROADCAST address for transmit.\n");
  168. return -EIO;
  169. }
  170. /* If we have set the ASSOC_MSK and we are in BSS mode then
  171. * add the IWL_AP_ID to the station rate table */
  172. if (new_assoc) {
  173. if (priv->iw_mode == NL80211_IFTYPE_STATION) {
  174. ret = iwl_rxon_add_station(priv,
  175. priv->active_rxon.bssid_addr, 1);
  176. if (ret == IWL_INVALID_STATION) {
  177. IWL_ERR(priv,
  178. "Error adding AP address for TX.\n");
  179. return -EIO;
  180. }
  181. priv->assoc_station_added = 1;
  182. if (priv->default_wep_key &&
  183. iwl_send_static_wepkey_cmd(priv, 0))
  184. IWL_ERR(priv,
  185. "Could not send WEP static key.\n");
  186. }
  187. /* Apply the new configuration
  188. * RXON assoc doesn't clear the station table in uCode,
  189. */
  190. ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
  191. sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
  192. if (ret) {
  193. IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
  194. return ret;
  195. }
  196. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  197. }
  198. iwl_init_sensitivity(priv);
  199. /* If we issue a new RXON command which required a tune then we must
  200. * send a new TXPOWER command or we won't be able to Tx any frames */
  201. ret = iwl_set_tx_power(priv, priv->tx_power_user_lmt, true);
  202. if (ret) {
  203. IWL_ERR(priv, "Error sending TX power (%d)\n", ret);
  204. return ret;
  205. }
  206. return 0;
  207. }
  208. void iwl_update_chain_flags(struct iwl_priv *priv)
  209. {
  210. if (priv->cfg->ops->hcmd->set_rxon_chain)
  211. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  212. iwlcore_commit_rxon(priv);
  213. }
  214. static void iwl_clear_free_frames(struct iwl_priv *priv)
  215. {
  216. struct list_head *element;
  217. IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
  218. priv->frames_count);
  219. while (!list_empty(&priv->free_frames)) {
  220. element = priv->free_frames.next;
  221. list_del(element);
  222. kfree(list_entry(element, struct iwl_frame, list));
  223. priv->frames_count--;
  224. }
  225. if (priv->frames_count) {
  226. IWL_WARN(priv, "%d frames still in use. Did we lose one?\n",
  227. priv->frames_count);
  228. priv->frames_count = 0;
  229. }
  230. }
  231. static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv)
  232. {
  233. struct iwl_frame *frame;
  234. struct list_head *element;
  235. if (list_empty(&priv->free_frames)) {
  236. frame = kzalloc(sizeof(*frame), GFP_KERNEL);
  237. if (!frame) {
  238. IWL_ERR(priv, "Could not allocate frame!\n");
  239. return NULL;
  240. }
  241. priv->frames_count++;
  242. return frame;
  243. }
  244. element = priv->free_frames.next;
  245. list_del(element);
  246. return list_entry(element, struct iwl_frame, list);
  247. }
  248. static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame)
  249. {
  250. memset(frame, 0, sizeof(*frame));
  251. list_add(&frame->list, &priv->free_frames);
  252. }
  253. static unsigned int iwl_fill_beacon_frame(struct iwl_priv *priv,
  254. struct ieee80211_hdr *hdr,
  255. int left)
  256. {
  257. if (!iwl_is_associated(priv) || !priv->ibss_beacon ||
  258. ((priv->iw_mode != NL80211_IFTYPE_ADHOC) &&
  259. (priv->iw_mode != NL80211_IFTYPE_AP)))
  260. return 0;
  261. if (priv->ibss_beacon->len > left)
  262. return 0;
  263. memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
  264. return priv->ibss_beacon->len;
  265. }
  266. static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
  267. struct iwl_frame *frame, u8 rate)
  268. {
  269. struct iwl_tx_beacon_cmd *tx_beacon_cmd;
  270. unsigned int frame_size;
  271. tx_beacon_cmd = &frame->u.beacon;
  272. memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
  273. tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
  274. tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  275. frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame,
  276. sizeof(frame->u) - sizeof(*tx_beacon_cmd));
  277. BUG_ON(frame_size > MAX_MPDU_SIZE);
  278. tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
  279. if ((rate == IWL_RATE_1M_PLCP) || (rate >= IWL_RATE_2M_PLCP))
  280. tx_beacon_cmd->tx.rate_n_flags =
  281. iwl_hw_set_rate_n_flags(rate, RATE_MCS_CCK_MSK);
  282. else
  283. tx_beacon_cmd->tx.rate_n_flags =
  284. iwl_hw_set_rate_n_flags(rate, 0);
  285. tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
  286. TX_CMD_FLG_TSF_MSK |
  287. TX_CMD_FLG_STA_RATE_MSK;
  288. return sizeof(*tx_beacon_cmd) + frame_size;
  289. }
  290. static int iwl_send_beacon_cmd(struct iwl_priv *priv)
  291. {
  292. struct iwl_frame *frame;
  293. unsigned int frame_size;
  294. int rc;
  295. u8 rate;
  296. frame = iwl_get_free_frame(priv);
  297. if (!frame) {
  298. IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
  299. "command.\n");
  300. return -ENOMEM;
  301. }
  302. rate = iwl_rate_get_lowest_plcp(priv);
  303. frame_size = iwl_hw_get_beacon_cmd(priv, frame, rate);
  304. rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
  305. &frame->u.cmd[0]);
  306. iwl_free_frame(priv, frame);
  307. return rc;
  308. }
  309. static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
  310. {
  311. struct iwl_tfd_tb *tb = &tfd->tbs[idx];
  312. dma_addr_t addr = get_unaligned_le32(&tb->lo);
  313. if (sizeof(dma_addr_t) > sizeof(u32))
  314. addr |=
  315. ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
  316. return addr;
  317. }
  318. static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
  319. {
  320. struct iwl_tfd_tb *tb = &tfd->tbs[idx];
  321. return le16_to_cpu(tb->hi_n_len) >> 4;
  322. }
  323. static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
  324. dma_addr_t addr, u16 len)
  325. {
  326. struct iwl_tfd_tb *tb = &tfd->tbs[idx];
  327. u16 hi_n_len = len << 4;
  328. put_unaligned_le32(addr, &tb->lo);
  329. if (sizeof(dma_addr_t) > sizeof(u32))
  330. hi_n_len |= ((addr >> 16) >> 16) & 0xF;
  331. tb->hi_n_len = cpu_to_le16(hi_n_len);
  332. tfd->num_tbs = idx + 1;
  333. }
  334. static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
  335. {
  336. return tfd->num_tbs & 0x1f;
  337. }
  338. /**
  339. * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
  340. * @priv - driver private data
  341. * @txq - tx queue
  342. *
  343. * Does NOT advance any TFD circular buffer read/write indexes
  344. * Does NOT free the TFD itself (which is within circular buffer)
  345. */
  346. void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
  347. {
  348. struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds;
  349. struct iwl_tfd *tfd;
  350. struct pci_dev *dev = priv->pci_dev;
  351. int index = txq->q.read_ptr;
  352. int i;
  353. int num_tbs;
  354. tfd = &tfd_tmp[index];
  355. /* Sanity check on number of chunks */
  356. num_tbs = iwl_tfd_get_num_tbs(tfd);
  357. if (num_tbs >= IWL_NUM_OF_TBS) {
  358. IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
  359. /* @todo issue fatal error, it is quite serious situation */
  360. return;
  361. }
  362. /* Unmap tx_cmd */
  363. if (num_tbs)
  364. pci_unmap_single(dev,
  365. pci_unmap_addr(&txq->cmd[index]->meta, mapping),
  366. pci_unmap_len(&txq->cmd[index]->meta, len),
  367. PCI_DMA_BIDIRECTIONAL);
  368. /* Unmap chunks, if any. */
  369. for (i = 1; i < num_tbs; i++) {
  370. pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i),
  371. iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE);
  372. if (txq->txb) {
  373. dev_kfree_skb(txq->txb[txq->q.read_ptr].skb[i - 1]);
  374. txq->txb[txq->q.read_ptr].skb[i - 1] = NULL;
  375. }
  376. }
  377. }
  378. int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
  379. struct iwl_tx_queue *txq,
  380. dma_addr_t addr, u16 len,
  381. u8 reset, u8 pad)
  382. {
  383. struct iwl_queue *q;
  384. struct iwl_tfd *tfd, *tfd_tmp;
  385. u32 num_tbs;
  386. q = &txq->q;
  387. tfd_tmp = (struct iwl_tfd *)txq->tfds;
  388. tfd = &tfd_tmp[q->write_ptr];
  389. if (reset)
  390. memset(tfd, 0, sizeof(*tfd));
  391. num_tbs = iwl_tfd_get_num_tbs(tfd);
  392. /* Each TFD can point to a maximum 20 Tx buffers */
  393. if (num_tbs >= IWL_NUM_OF_TBS) {
  394. IWL_ERR(priv, "Error can not send more than %d chunks\n",
  395. IWL_NUM_OF_TBS);
  396. return -EINVAL;
  397. }
  398. BUG_ON(addr & ~DMA_BIT_MASK(36));
  399. if (unlikely(addr & ~IWL_TX_DMA_MASK))
  400. IWL_ERR(priv, "Unaligned address = %llx\n",
  401. (unsigned long long)addr);
  402. iwl_tfd_set_tb(tfd, num_tbs, addr, len);
  403. return 0;
  404. }
  405. /*
  406. * Tell nic where to find circular buffer of Tx Frame Descriptors for
  407. * given Tx queue, and enable the DMA channel used for that queue.
  408. *
  409. * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
  410. * channels supported in hardware.
  411. */
  412. int iwl_hw_tx_queue_init(struct iwl_priv *priv,
  413. struct iwl_tx_queue *txq)
  414. {
  415. int txq_id = txq->q.id;
  416. /* Circular buffer (TFD queue in DRAM) physical base address */
  417. iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
  418. txq->q.dma_addr >> 8);
  419. return 0;
  420. }
  421. /******************************************************************************
  422. *
  423. * Generic RX handler implementations
  424. *
  425. ******************************************************************************/
  426. static void iwl_rx_reply_alive(struct iwl_priv *priv,
  427. struct iwl_rx_mem_buffer *rxb)
  428. {
  429. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  430. struct iwl_alive_resp *palive;
  431. struct delayed_work *pwork;
  432. palive = &pkt->u.alive_frame;
  433. IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
  434. "0x%01X 0x%01X\n",
  435. palive->is_valid, palive->ver_type,
  436. palive->ver_subtype);
  437. if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
  438. IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
  439. set_bit(STATUS_INIT_UCODE_ALIVE, &priv->status);
  440. wake_up_interruptible(&priv->wait_command_queue);
  441. memcpy(&priv->card_alive_init,
  442. &pkt->u.alive_frame,
  443. sizeof(struct iwl_init_alive_resp));
  444. pwork = &priv->init_alive_start;
  445. } else {
  446. IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
  447. set_bit(STATUS_RT_UCODE_ALIVE, &priv->status);
  448. wake_up_interruptible(&priv->wait_command_queue);
  449. memcpy(&priv->card_alive, &pkt->u.alive_frame,
  450. sizeof(struct iwl_alive_resp));
  451. pwork = &priv->alive_start;
  452. }
  453. /* We delay the ALIVE response by 5ms to
  454. * give the HW RF Kill time to activate... */
  455. if (palive->is_valid == UCODE_VALID_OK)
  456. queue_delayed_work(priv->workqueue, pwork,
  457. msecs_to_jiffies(5));
  458. else
  459. IWL_WARN(priv, "uCode did not respond OK.\n");
  460. }
  461. static void iwl_bg_beacon_update(struct work_struct *work)
  462. {
  463. struct iwl_priv *priv =
  464. container_of(work, struct iwl_priv, beacon_update);
  465. struct sk_buff *beacon;
  466. /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
  467. beacon = ieee80211_beacon_get(priv->hw, priv->vif);
  468. if (!beacon) {
  469. IWL_ERR(priv, "update beacon failed\n");
  470. return;
  471. }
  472. mutex_lock(&priv->mutex);
  473. /* new beacon skb is allocated every time; dispose previous.*/
  474. if (priv->ibss_beacon)
  475. dev_kfree_skb(priv->ibss_beacon);
  476. priv->ibss_beacon = beacon;
  477. mutex_unlock(&priv->mutex);
  478. iwl_send_beacon_cmd(priv);
  479. }
  480. /**
  481. * iwl_bg_statistics_periodic - Timer callback to queue statistics
  482. *
  483. * This callback is provided in order to send a statistics request.
  484. *
  485. * This timer function is continually reset to execute within
  486. * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
  487. * was received. We need to ensure we receive the statistics in order
  488. * to update the temperature used for calibrating the TXPOWER.
  489. */
  490. static void iwl_bg_statistics_periodic(unsigned long data)
  491. {
  492. struct iwl_priv *priv = (struct iwl_priv *)data;
  493. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  494. return;
  495. /* dont send host command if rf-kill is on */
  496. if (!iwl_is_ready_rf(priv))
  497. return;
  498. iwl_send_statistics_request(priv, CMD_ASYNC);
  499. }
  500. static void iwl_rx_beacon_notif(struct iwl_priv *priv,
  501. struct iwl_rx_mem_buffer *rxb)
  502. {
  503. #ifdef CONFIG_IWLWIFI_DEBUG
  504. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  505. struct iwl4965_beacon_notif *beacon =
  506. (struct iwl4965_beacon_notif *)pkt->u.raw;
  507. u8 rate = iwl_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
  508. IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d "
  509. "tsf %d %d rate %d\n",
  510. le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK,
  511. beacon->beacon_notify_hdr.failure_frame,
  512. le32_to_cpu(beacon->ibss_mgr_status),
  513. le32_to_cpu(beacon->high_tsf),
  514. le32_to_cpu(beacon->low_tsf), rate);
  515. #endif
  516. if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
  517. (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
  518. queue_work(priv->workqueue, &priv->beacon_update);
  519. }
  520. /* Handle notification from uCode that card's power state is changing
  521. * due to software, hardware, or critical temperature RFKILL */
  522. static void iwl_rx_card_state_notif(struct iwl_priv *priv,
  523. struct iwl_rx_mem_buffer *rxb)
  524. {
  525. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  526. u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
  527. unsigned long status = priv->status;
  528. unsigned long reg_flags;
  529. IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s\n",
  530. (flags & HW_CARD_DISABLED) ? "Kill" : "On",
  531. (flags & SW_CARD_DISABLED) ? "Kill" : "On");
  532. if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED |
  533. RF_CARD_DISABLED)) {
  534. iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
  535. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  536. iwl_write_direct32(priv, HBUS_TARG_MBX_C,
  537. HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
  538. if (!(flags & RXON_CARD_DISABLED)) {
  539. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  540. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  541. iwl_write_direct32(priv, HBUS_TARG_MBX_C,
  542. HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
  543. }
  544. if (flags & RF_CARD_DISABLED) {
  545. iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
  546. CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
  547. iwl_read32(priv, CSR_UCODE_DRV_GP1);
  548. spin_lock_irqsave(&priv->reg_lock, reg_flags);
  549. if (!iwl_grab_nic_access(priv))
  550. iwl_release_nic_access(priv);
  551. spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
  552. }
  553. }
  554. if (flags & HW_CARD_DISABLED)
  555. set_bit(STATUS_RF_KILL_HW, &priv->status);
  556. else
  557. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  558. if (!(flags & RXON_CARD_DISABLED))
  559. iwl_scan_cancel(priv);
  560. if ((test_bit(STATUS_RF_KILL_HW, &status) !=
  561. test_bit(STATUS_RF_KILL_HW, &priv->status)))
  562. wiphy_rfkill_set_hw_state(priv->hw->wiphy,
  563. test_bit(STATUS_RF_KILL_HW, &priv->status));
  564. else
  565. wake_up_interruptible(&priv->wait_command_queue);
  566. }
  567. int iwl_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
  568. {
  569. if (src == IWL_PWR_SRC_VAUX) {
  570. if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
  571. iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
  572. APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
  573. ~APMG_PS_CTRL_MSK_PWR_SRC);
  574. } else {
  575. iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
  576. APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
  577. ~APMG_PS_CTRL_MSK_PWR_SRC);
  578. }
  579. return 0;
  580. }
  581. /**
  582. * iwl_setup_rx_handlers - Initialize Rx handler callbacks
  583. *
  584. * Setup the RX handlers for each of the reply types sent from the uCode
  585. * to the host.
  586. *
  587. * This function chains into the hardware specific files for them to setup
  588. * any hardware specific handlers as well.
  589. */
  590. static void iwl_setup_rx_handlers(struct iwl_priv *priv)
  591. {
  592. priv->rx_handlers[REPLY_ALIVE] = iwl_rx_reply_alive;
  593. priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error;
  594. priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa;
  595. priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif;
  596. priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
  597. iwl_rx_pm_debug_statistics_notif;
  598. priv->rx_handlers[BEACON_NOTIFICATION] = iwl_rx_beacon_notif;
  599. /*
  600. * The same handler is used for both the REPLY to a discrete
  601. * statistics request from the host as well as for the periodic
  602. * statistics notifications (after received beacons) from the uCode.
  603. */
  604. priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl_rx_statistics;
  605. priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl_rx_statistics;
  606. iwl_setup_spectrum_handlers(priv);
  607. iwl_setup_rx_scan_handlers(priv);
  608. /* status change handler */
  609. priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl_rx_card_state_notif;
  610. priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
  611. iwl_rx_missed_beacon_notif;
  612. /* Rx handlers */
  613. priv->rx_handlers[REPLY_RX_PHY_CMD] = iwl_rx_reply_rx_phy;
  614. priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwl_rx_reply_rx;
  615. /* block ack */
  616. priv->rx_handlers[REPLY_COMPRESSED_BA] = iwl_rx_reply_compressed_ba;
  617. /* Set up hardware specific Rx handlers */
  618. priv->cfg->ops->lib->rx_handler_setup(priv);
  619. }
  620. /**
  621. * iwl_rx_handle - Main entry function for receiving responses from uCode
  622. *
  623. * Uses the priv->rx_handlers callback function array to invoke
  624. * the appropriate handlers, including command responses,
  625. * frame-received notifications, and other notifications.
  626. */
  627. void iwl_rx_handle(struct iwl_priv *priv)
  628. {
  629. struct iwl_rx_mem_buffer *rxb;
  630. struct iwl_rx_packet *pkt;
  631. struct iwl_rx_queue *rxq = &priv->rxq;
  632. u32 r, i;
  633. int reclaim;
  634. unsigned long flags;
  635. u8 fill_rx = 0;
  636. u32 count = 8;
  637. int total_empty;
  638. /* uCode's read index (stored in shared DRAM) indicates the last Rx
  639. * buffer that the driver may process (last buffer filled by ucode). */
  640. r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
  641. i = rxq->read;
  642. /* Rx interrupt, but nothing sent from uCode */
  643. if (i == r)
  644. IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
  645. /* calculate total frames need to be restock after handling RX */
  646. total_empty = r - priv->rxq.write_actual;
  647. if (total_empty < 0)
  648. total_empty += RX_QUEUE_SIZE;
  649. if (total_empty > (RX_QUEUE_SIZE / 2))
  650. fill_rx = 1;
  651. while (i != r) {
  652. rxb = rxq->queue[i];
  653. /* If an RXB doesn't have a Rx queue slot associated with it,
  654. * then a bug has been introduced in the queue refilling
  655. * routines -- catch it here */
  656. BUG_ON(rxb == NULL);
  657. rxq->queue[i] = NULL;
  658. pci_unmap_single(priv->pci_dev, rxb->real_dma_addr,
  659. priv->hw_params.rx_buf_size + 256,
  660. PCI_DMA_FROMDEVICE);
  661. pkt = (struct iwl_rx_packet *)rxb->skb->data;
  662. /* Reclaim a command buffer only if this packet is a response
  663. * to a (driver-originated) command.
  664. * If the packet (e.g. Rx frame) originated from uCode,
  665. * there is no command buffer to reclaim.
  666. * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
  667. * but apparently a few don't get set; catch them here. */
  668. reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
  669. (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
  670. (pkt->hdr.cmd != REPLY_RX) &&
  671. (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
  672. (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
  673. (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
  674. (pkt->hdr.cmd != REPLY_TX);
  675. /* Based on type of command response or notification,
  676. * handle those that need handling via function in
  677. * rx_handlers table. See iwl_setup_rx_handlers() */
  678. if (priv->rx_handlers[pkt->hdr.cmd]) {
  679. IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
  680. i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
  681. priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
  682. priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
  683. } else {
  684. /* No handling needed */
  685. IWL_DEBUG_RX(priv,
  686. "r %d i %d No handler needed for %s, 0x%02x\n",
  687. r, i, get_cmd_string(pkt->hdr.cmd),
  688. pkt->hdr.cmd);
  689. }
  690. if (reclaim) {
  691. /* Invoke any callbacks, transfer the skb to caller, and
  692. * fire off the (possibly) blocking iwl_send_cmd()
  693. * as we reclaim the driver command queue */
  694. if (rxb && rxb->skb)
  695. iwl_tx_cmd_complete(priv, rxb);
  696. else
  697. IWL_WARN(priv, "Claim null rxb?\n");
  698. }
  699. /* For now we just don't re-use anything. We can tweak this
  700. * later to try and re-use notification packets and SKBs that
  701. * fail to Rx correctly */
  702. if (rxb->skb != NULL) {
  703. priv->alloc_rxb_skb--;
  704. dev_kfree_skb_any(rxb->skb);
  705. rxb->skb = NULL;
  706. }
  707. spin_lock_irqsave(&rxq->lock, flags);
  708. list_add_tail(&rxb->list, &priv->rxq.rx_used);
  709. spin_unlock_irqrestore(&rxq->lock, flags);
  710. i = (i + 1) & RX_QUEUE_MASK;
  711. /* If there are a lot of unused frames,
  712. * restock the Rx queue so ucode wont assert. */
  713. if (fill_rx) {
  714. count++;
  715. if (count >= 8) {
  716. priv->rxq.read = i;
  717. iwl_rx_replenish_now(priv);
  718. count = 0;
  719. }
  720. }
  721. }
  722. /* Backtrack one entry */
  723. priv->rxq.read = i;
  724. if (fill_rx)
  725. iwl_rx_replenish_now(priv);
  726. else
  727. iwl_rx_queue_restock(priv);
  728. }
  729. /* call this function to flush any scheduled tasklet */
  730. static inline void iwl_synchronize_irq(struct iwl_priv *priv)
  731. {
  732. /* wait to make sure we flush pending tasklet*/
  733. synchronize_irq(priv->pci_dev->irq);
  734. tasklet_kill(&priv->irq_tasklet);
  735. }
  736. static void iwl_irq_tasklet_legacy(struct iwl_priv *priv)
  737. {
  738. u32 inta, handled = 0;
  739. u32 inta_fh;
  740. unsigned long flags;
  741. #ifdef CONFIG_IWLWIFI_DEBUG
  742. u32 inta_mask;
  743. #endif
  744. spin_lock_irqsave(&priv->lock, flags);
  745. /* Ack/clear/reset pending uCode interrupts.
  746. * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
  747. * and will clear only when CSR_FH_INT_STATUS gets cleared. */
  748. inta = iwl_read32(priv, CSR_INT);
  749. iwl_write32(priv, CSR_INT, inta);
  750. /* Ack/clear/reset pending flow-handler (DMA) interrupts.
  751. * Any new interrupts that happen after this, either while we're
  752. * in this tasklet, or later, will show up in next ISR/tasklet. */
  753. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  754. iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
  755. #ifdef CONFIG_IWLWIFI_DEBUG
  756. if (iwl_debug_level & IWL_DL_ISR) {
  757. /* just for debug */
  758. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  759. IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
  760. inta, inta_mask, inta_fh);
  761. }
  762. #endif
  763. /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
  764. * atomic, make sure that inta covers all the interrupts that
  765. * we've discovered, even if FH interrupt came in just after
  766. * reading CSR_INT. */
  767. if (inta_fh & CSR49_FH_INT_RX_MASK)
  768. inta |= CSR_INT_BIT_FH_RX;
  769. if (inta_fh & CSR49_FH_INT_TX_MASK)
  770. inta |= CSR_INT_BIT_FH_TX;
  771. /* Now service all interrupt bits discovered above. */
  772. if (inta & CSR_INT_BIT_HW_ERR) {
  773. IWL_ERR(priv, "Microcode HW error detected. Restarting.\n");
  774. /* Tell the device to stop sending interrupts */
  775. iwl_disable_interrupts(priv);
  776. priv->isr_stats.hw++;
  777. iwl_irq_handle_error(priv);
  778. handled |= CSR_INT_BIT_HW_ERR;
  779. spin_unlock_irqrestore(&priv->lock, flags);
  780. return;
  781. }
  782. #ifdef CONFIG_IWLWIFI_DEBUG
  783. if (iwl_debug_level & (IWL_DL_ISR)) {
  784. /* NIC fires this, but we don't use it, redundant with WAKEUP */
  785. if (inta & CSR_INT_BIT_SCD) {
  786. IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
  787. "the frame/frames.\n");
  788. priv->isr_stats.sch++;
  789. }
  790. /* Alive notification via Rx interrupt will do the real work */
  791. if (inta & CSR_INT_BIT_ALIVE) {
  792. IWL_DEBUG_ISR(priv, "Alive interrupt\n");
  793. priv->isr_stats.alive++;
  794. }
  795. }
  796. #endif
  797. /* Safely ignore these bits for debug checks below */
  798. inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
  799. /* HW RF KILL switch toggled */
  800. if (inta & CSR_INT_BIT_RF_KILL) {
  801. int hw_rf_kill = 0;
  802. if (!(iwl_read32(priv, CSR_GP_CNTRL) &
  803. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
  804. hw_rf_kill = 1;
  805. IWL_DEBUG_RF_KILL(priv, "RF_KILL bit toggled to %s.\n",
  806. hw_rf_kill ? "disable radio" : "enable radio");
  807. priv->isr_stats.rfkill++;
  808. /* driver only loads ucode once setting the interface up.
  809. * the driver allows loading the ucode even if the radio
  810. * is killed. Hence update the killswitch state here. The
  811. * rfkill handler will care about restarting if needed.
  812. */
  813. if (!test_bit(STATUS_ALIVE, &priv->status)) {
  814. if (hw_rf_kill)
  815. set_bit(STATUS_RF_KILL_HW, &priv->status);
  816. else
  817. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  818. wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
  819. }
  820. handled |= CSR_INT_BIT_RF_KILL;
  821. }
  822. /* Chip got too hot and stopped itself */
  823. if (inta & CSR_INT_BIT_CT_KILL) {
  824. IWL_ERR(priv, "Microcode CT kill error detected.\n");
  825. priv->isr_stats.ctkill++;
  826. handled |= CSR_INT_BIT_CT_KILL;
  827. }
  828. /* Error detected by uCode */
  829. if (inta & CSR_INT_BIT_SW_ERR) {
  830. IWL_ERR(priv, "Microcode SW error detected. "
  831. " Restarting 0x%X.\n", inta);
  832. priv->isr_stats.sw++;
  833. priv->isr_stats.sw_err = inta;
  834. iwl_irq_handle_error(priv);
  835. handled |= CSR_INT_BIT_SW_ERR;
  836. }
  837. /* uCode wakes up after power-down sleep */
  838. if (inta & CSR_INT_BIT_WAKEUP) {
  839. IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
  840. iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
  841. iwl_txq_update_write_ptr(priv, &priv->txq[0]);
  842. iwl_txq_update_write_ptr(priv, &priv->txq[1]);
  843. iwl_txq_update_write_ptr(priv, &priv->txq[2]);
  844. iwl_txq_update_write_ptr(priv, &priv->txq[3]);
  845. iwl_txq_update_write_ptr(priv, &priv->txq[4]);
  846. iwl_txq_update_write_ptr(priv, &priv->txq[5]);
  847. priv->isr_stats.wakeup++;
  848. handled |= CSR_INT_BIT_WAKEUP;
  849. }
  850. /* All uCode command responses, including Tx command responses,
  851. * Rx "responses" (frame-received notification), and other
  852. * notifications from uCode come through here*/
  853. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
  854. iwl_rx_handle(priv);
  855. priv->isr_stats.rx++;
  856. handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
  857. }
  858. if (inta & CSR_INT_BIT_FH_TX) {
  859. IWL_DEBUG_ISR(priv, "Tx interrupt\n");
  860. priv->isr_stats.tx++;
  861. handled |= CSR_INT_BIT_FH_TX;
  862. /* FH finished to write, send event */
  863. priv->ucode_write_complete = 1;
  864. wake_up_interruptible(&priv->wait_command_queue);
  865. }
  866. if (inta & ~handled) {
  867. IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
  868. priv->isr_stats.unhandled++;
  869. }
  870. if (inta & ~(priv->inta_mask)) {
  871. IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
  872. inta & ~priv->inta_mask);
  873. IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh);
  874. }
  875. /* Re-enable all interrupts */
  876. /* only Re-enable if diabled by irq */
  877. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  878. iwl_enable_interrupts(priv);
  879. #ifdef CONFIG_IWLWIFI_DEBUG
  880. if (iwl_debug_level & (IWL_DL_ISR)) {
  881. inta = iwl_read32(priv, CSR_INT);
  882. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  883. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  884. IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
  885. "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
  886. }
  887. #endif
  888. spin_unlock_irqrestore(&priv->lock, flags);
  889. }
  890. /* tasklet for iwlagn interrupt */
  891. static void iwl_irq_tasklet(struct iwl_priv *priv)
  892. {
  893. u32 inta = 0;
  894. u32 handled = 0;
  895. unsigned long flags;
  896. #ifdef CONFIG_IWLWIFI_DEBUG
  897. u32 inta_mask;
  898. #endif
  899. spin_lock_irqsave(&priv->lock, flags);
  900. /* Ack/clear/reset pending uCode interrupts.
  901. * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
  902. */
  903. iwl_write32(priv, CSR_INT, priv->inta);
  904. inta = priv->inta;
  905. #ifdef CONFIG_IWLWIFI_DEBUG
  906. if (iwl_debug_level & IWL_DL_ISR) {
  907. /* just for debug */
  908. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  909. IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ",
  910. inta, inta_mask);
  911. }
  912. #endif
  913. /* saved interrupt in inta variable now we can reset priv->inta */
  914. priv->inta = 0;
  915. /* Now service all interrupt bits discovered above. */
  916. if (inta & CSR_INT_BIT_HW_ERR) {
  917. IWL_ERR(priv, "Microcode HW error detected. Restarting.\n");
  918. /* Tell the device to stop sending interrupts */
  919. iwl_disable_interrupts(priv);
  920. priv->isr_stats.hw++;
  921. iwl_irq_handle_error(priv);
  922. handled |= CSR_INT_BIT_HW_ERR;
  923. spin_unlock_irqrestore(&priv->lock, flags);
  924. return;
  925. }
  926. #ifdef CONFIG_IWLWIFI_DEBUG
  927. if (iwl_debug_level & (IWL_DL_ISR)) {
  928. /* NIC fires this, but we don't use it, redundant with WAKEUP */
  929. if (inta & CSR_INT_BIT_SCD) {
  930. IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
  931. "the frame/frames.\n");
  932. priv->isr_stats.sch++;
  933. }
  934. /* Alive notification via Rx interrupt will do the real work */
  935. if (inta & CSR_INT_BIT_ALIVE) {
  936. IWL_DEBUG_ISR(priv, "Alive interrupt\n");
  937. priv->isr_stats.alive++;
  938. }
  939. }
  940. #endif
  941. /* Safely ignore these bits for debug checks below */
  942. inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
  943. /* HW RF KILL switch toggled */
  944. if (inta & CSR_INT_BIT_RF_KILL) {
  945. int hw_rf_kill = 0;
  946. if (!(iwl_read32(priv, CSR_GP_CNTRL) &
  947. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
  948. hw_rf_kill = 1;
  949. IWL_DEBUG_RF_KILL(priv, "RF_KILL bit toggled to %s.\n",
  950. hw_rf_kill ? "disable radio" : "enable radio");
  951. priv->isr_stats.rfkill++;
  952. /* driver only loads ucode once setting the interface up.
  953. * the driver allows loading the ucode even if the radio
  954. * is killed. Hence update the killswitch state here. The
  955. * rfkill handler will care about restarting if needed.
  956. */
  957. if (!test_bit(STATUS_ALIVE, &priv->status)) {
  958. if (hw_rf_kill)
  959. set_bit(STATUS_RF_KILL_HW, &priv->status);
  960. else
  961. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  962. wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
  963. }
  964. handled |= CSR_INT_BIT_RF_KILL;
  965. }
  966. /* Chip got too hot and stopped itself */
  967. if (inta & CSR_INT_BIT_CT_KILL) {
  968. IWL_ERR(priv, "Microcode CT kill error detected.\n");
  969. priv->isr_stats.ctkill++;
  970. handled |= CSR_INT_BIT_CT_KILL;
  971. }
  972. /* Error detected by uCode */
  973. if (inta & CSR_INT_BIT_SW_ERR) {
  974. IWL_ERR(priv, "Microcode SW error detected. "
  975. " Restarting 0x%X.\n", inta);
  976. priv->isr_stats.sw++;
  977. priv->isr_stats.sw_err = inta;
  978. iwl_irq_handle_error(priv);
  979. handled |= CSR_INT_BIT_SW_ERR;
  980. }
  981. /* uCode wakes up after power-down sleep */
  982. if (inta & CSR_INT_BIT_WAKEUP) {
  983. IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
  984. iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
  985. iwl_txq_update_write_ptr(priv, &priv->txq[0]);
  986. iwl_txq_update_write_ptr(priv, &priv->txq[1]);
  987. iwl_txq_update_write_ptr(priv, &priv->txq[2]);
  988. iwl_txq_update_write_ptr(priv, &priv->txq[3]);
  989. iwl_txq_update_write_ptr(priv, &priv->txq[4]);
  990. iwl_txq_update_write_ptr(priv, &priv->txq[5]);
  991. priv->isr_stats.wakeup++;
  992. handled |= CSR_INT_BIT_WAKEUP;
  993. }
  994. /* All uCode command responses, including Tx command responses,
  995. * Rx "responses" (frame-received notification), and other
  996. * notifications from uCode come through here*/
  997. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
  998. CSR_INT_BIT_RX_PERIODIC)) {
  999. IWL_DEBUG_ISR(priv, "Rx interrupt\n");
  1000. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
  1001. handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
  1002. iwl_write32(priv, CSR_FH_INT_STATUS,
  1003. CSR49_FH_INT_RX_MASK);
  1004. }
  1005. if (inta & CSR_INT_BIT_RX_PERIODIC) {
  1006. handled |= CSR_INT_BIT_RX_PERIODIC;
  1007. iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC);
  1008. }
  1009. /* Sending RX interrupt require many steps to be done in the
  1010. * the device:
  1011. * 1- write interrupt to current index in ICT table.
  1012. * 2- dma RX frame.
  1013. * 3- update RX shared data to indicate last write index.
  1014. * 4- send interrupt.
  1015. * This could lead to RX race, driver could receive RX interrupt
  1016. * but the shared data changes does not reflect this.
  1017. * this could lead to RX race, RX periodic will solve this race
  1018. */
  1019. iwl_write32(priv, CSR_INT_PERIODIC_REG,
  1020. CSR_INT_PERIODIC_DIS);
  1021. iwl_rx_handle(priv);
  1022. /* Only set RX periodic if real RX is received. */
  1023. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
  1024. iwl_write32(priv, CSR_INT_PERIODIC_REG,
  1025. CSR_INT_PERIODIC_ENA);
  1026. priv->isr_stats.rx++;
  1027. }
  1028. if (inta & CSR_INT_BIT_FH_TX) {
  1029. iwl_write32(priv, CSR_FH_INT_STATUS, CSR49_FH_INT_TX_MASK);
  1030. IWL_DEBUG_ISR(priv, "Tx interrupt\n");
  1031. priv->isr_stats.tx++;
  1032. handled |= CSR_INT_BIT_FH_TX;
  1033. /* FH finished to write, send event */
  1034. priv->ucode_write_complete = 1;
  1035. wake_up_interruptible(&priv->wait_command_queue);
  1036. }
  1037. if (inta & ~handled) {
  1038. IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
  1039. priv->isr_stats.unhandled++;
  1040. }
  1041. if (inta & ~(priv->inta_mask)) {
  1042. IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
  1043. inta & ~priv->inta_mask);
  1044. }
  1045. /* Re-enable all interrupts */
  1046. /* only Re-enable if diabled by irq */
  1047. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  1048. iwl_enable_interrupts(priv);
  1049. spin_unlock_irqrestore(&priv->lock, flags);
  1050. }
  1051. /******************************************************************************
  1052. *
  1053. * uCode download functions
  1054. *
  1055. ******************************************************************************/
  1056. static void iwl_dealloc_ucode_pci(struct iwl_priv *priv)
  1057. {
  1058. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
  1059. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
  1060. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  1061. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
  1062. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  1063. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
  1064. }
  1065. static void iwl_nic_start(struct iwl_priv *priv)
  1066. {
  1067. /* Remove all resets to allow NIC to operate */
  1068. iwl_write32(priv, CSR_RESET, 0);
  1069. }
  1070. /**
  1071. * iwl_read_ucode - Read uCode images from disk file.
  1072. *
  1073. * Copy into buffers for card to fetch via bus-mastering
  1074. */
  1075. static int iwl_read_ucode(struct iwl_priv *priv)
  1076. {
  1077. struct iwl_ucode_header *ucode;
  1078. int ret = -EINVAL, index;
  1079. const struct firmware *ucode_raw;
  1080. const char *name_pre = priv->cfg->fw_name_pre;
  1081. const unsigned int api_max = priv->cfg->ucode_api_max;
  1082. const unsigned int api_min = priv->cfg->ucode_api_min;
  1083. char buf[25];
  1084. u8 *src;
  1085. size_t len;
  1086. u32 api_ver, build;
  1087. u32 inst_size, data_size, init_size, init_data_size, boot_size;
  1088. /* Ask kernel firmware_class module to get the boot firmware off disk.
  1089. * request_firmware() is synchronous, file is in memory on return. */
  1090. for (index = api_max; index >= api_min; index--) {
  1091. sprintf(buf, "%s%d%s", name_pre, index, ".ucode");
  1092. ret = request_firmware(&ucode_raw, buf, &priv->pci_dev->dev);
  1093. if (ret < 0) {
  1094. IWL_ERR(priv, "%s firmware file req failed: %d\n",
  1095. buf, ret);
  1096. if (ret == -ENOENT)
  1097. continue;
  1098. else
  1099. goto error;
  1100. } else {
  1101. if (index < api_max)
  1102. IWL_ERR(priv, "Loaded firmware %s, "
  1103. "which is deprecated. "
  1104. "Please use API v%u instead.\n",
  1105. buf, api_max);
  1106. IWL_DEBUG_INFO(priv, "Got firmware '%s' file (%zd bytes) from disk\n",
  1107. buf, ucode_raw->size);
  1108. break;
  1109. }
  1110. }
  1111. if (ret < 0)
  1112. goto error;
  1113. /* Make sure that we got at least the v1 header! */
  1114. if (ucode_raw->size < priv->cfg->ops->ucode->get_header_size(1)) {
  1115. IWL_ERR(priv, "File size way too small!\n");
  1116. ret = -EINVAL;
  1117. goto err_release;
  1118. }
  1119. /* Data from ucode file: header followed by uCode images */
  1120. ucode = (struct iwl_ucode_header *)ucode_raw->data;
  1121. priv->ucode_ver = le32_to_cpu(ucode->ver);
  1122. api_ver = IWL_UCODE_API(priv->ucode_ver);
  1123. build = priv->cfg->ops->ucode->get_build(ucode, api_ver);
  1124. inst_size = priv->cfg->ops->ucode->get_inst_size(ucode, api_ver);
  1125. data_size = priv->cfg->ops->ucode->get_data_size(ucode, api_ver);
  1126. init_size = priv->cfg->ops->ucode->get_init_size(ucode, api_ver);
  1127. init_data_size =
  1128. priv->cfg->ops->ucode->get_init_data_size(ucode, api_ver);
  1129. boot_size = priv->cfg->ops->ucode->get_boot_size(ucode, api_ver);
  1130. src = priv->cfg->ops->ucode->get_data(ucode, api_ver);
  1131. /* api_ver should match the api version forming part of the
  1132. * firmware filename ... but we don't check for that and only rely
  1133. * on the API version read from firmware header from here on forward */
  1134. if (api_ver < api_min || api_ver > api_max) {
  1135. IWL_ERR(priv, "Driver unable to support your firmware API. "
  1136. "Driver supports v%u, firmware is v%u.\n",
  1137. api_max, api_ver);
  1138. priv->ucode_ver = 0;
  1139. ret = -EINVAL;
  1140. goto err_release;
  1141. }
  1142. if (api_ver != api_max)
  1143. IWL_ERR(priv, "Firmware has old API version. Expected v%u, "
  1144. "got v%u. New firmware can be obtained "
  1145. "from http://www.intellinuxwireless.org.\n",
  1146. api_max, api_ver);
  1147. IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u\n",
  1148. IWL_UCODE_MAJOR(priv->ucode_ver),
  1149. IWL_UCODE_MINOR(priv->ucode_ver),
  1150. IWL_UCODE_API(priv->ucode_ver),
  1151. IWL_UCODE_SERIAL(priv->ucode_ver));
  1152. if (build)
  1153. IWL_DEBUG_INFO(priv, "Build %u\n", build);
  1154. IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
  1155. priv->ucode_ver);
  1156. IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %u\n",
  1157. inst_size);
  1158. IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %u\n",
  1159. data_size);
  1160. IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %u\n",
  1161. init_size);
  1162. IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %u\n",
  1163. init_data_size);
  1164. IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %u\n",
  1165. boot_size);
  1166. /* Verify size of file vs. image size info in file's header */
  1167. if (ucode_raw->size !=
  1168. priv->cfg->ops->ucode->get_header_size(api_ver) +
  1169. inst_size + data_size + init_size +
  1170. init_data_size + boot_size) {
  1171. IWL_DEBUG_INFO(priv,
  1172. "uCode file size %d does not match expected size\n",
  1173. (int)ucode_raw->size);
  1174. ret = -EINVAL;
  1175. goto err_release;
  1176. }
  1177. /* Verify that uCode images will fit in card's SRAM */
  1178. if (inst_size > priv->hw_params.max_inst_size) {
  1179. IWL_DEBUG_INFO(priv, "uCode instr len %d too large to fit in\n",
  1180. inst_size);
  1181. ret = -EINVAL;
  1182. goto err_release;
  1183. }
  1184. if (data_size > priv->hw_params.max_data_size) {
  1185. IWL_DEBUG_INFO(priv, "uCode data len %d too large to fit in\n",
  1186. data_size);
  1187. ret = -EINVAL;
  1188. goto err_release;
  1189. }
  1190. if (init_size > priv->hw_params.max_inst_size) {
  1191. IWL_INFO(priv, "uCode init instr len %d too large to fit in\n",
  1192. init_size);
  1193. ret = -EINVAL;
  1194. goto err_release;
  1195. }
  1196. if (init_data_size > priv->hw_params.max_data_size) {
  1197. IWL_INFO(priv, "uCode init data len %d too large to fit in\n",
  1198. init_data_size);
  1199. ret = -EINVAL;
  1200. goto err_release;
  1201. }
  1202. if (boot_size > priv->hw_params.max_bsm_size) {
  1203. IWL_INFO(priv, "uCode boot instr len %d too large to fit in\n",
  1204. boot_size);
  1205. ret = -EINVAL;
  1206. goto err_release;
  1207. }
  1208. /* Allocate ucode buffers for card's bus-master loading ... */
  1209. /* Runtime instructions and 2 copies of data:
  1210. * 1) unmodified from disk
  1211. * 2) backup cache for save/restore during power-downs */
  1212. priv->ucode_code.len = inst_size;
  1213. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
  1214. priv->ucode_data.len = data_size;
  1215. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
  1216. priv->ucode_data_backup.len = data_size;
  1217. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  1218. if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
  1219. !priv->ucode_data_backup.v_addr)
  1220. goto err_pci_alloc;
  1221. /* Initialization instructions and data */
  1222. if (init_size && init_data_size) {
  1223. priv->ucode_init.len = init_size;
  1224. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
  1225. priv->ucode_init_data.len = init_data_size;
  1226. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  1227. if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
  1228. goto err_pci_alloc;
  1229. }
  1230. /* Bootstrap (instructions only, no data) */
  1231. if (boot_size) {
  1232. priv->ucode_boot.len = boot_size;
  1233. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
  1234. if (!priv->ucode_boot.v_addr)
  1235. goto err_pci_alloc;
  1236. }
  1237. /* Copy images into buffers for card's bus-master reads ... */
  1238. /* Runtime instructions (first block of data in file) */
  1239. len = inst_size;
  1240. IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n", len);
  1241. memcpy(priv->ucode_code.v_addr, src, len);
  1242. src += len;
  1243. IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
  1244. priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
  1245. /* Runtime data (2nd block)
  1246. * NOTE: Copy into backup buffer will be done in iwl_up() */
  1247. len = data_size;
  1248. IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n", len);
  1249. memcpy(priv->ucode_data.v_addr, src, len);
  1250. memcpy(priv->ucode_data_backup.v_addr, src, len);
  1251. src += len;
  1252. /* Initialization instructions (3rd block) */
  1253. if (init_size) {
  1254. len = init_size;
  1255. IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n",
  1256. len);
  1257. memcpy(priv->ucode_init.v_addr, src, len);
  1258. src += len;
  1259. }
  1260. /* Initialization data (4th block) */
  1261. if (init_data_size) {
  1262. len = init_data_size;
  1263. IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n",
  1264. len);
  1265. memcpy(priv->ucode_init_data.v_addr, src, len);
  1266. src += len;
  1267. }
  1268. /* Bootstrap instructions (5th block) */
  1269. len = boot_size;
  1270. IWL_DEBUG_INFO(priv, "Copying (but not loading) boot instr len %Zd\n", len);
  1271. memcpy(priv->ucode_boot.v_addr, src, len);
  1272. /* We have our copies now, allow OS release its copies */
  1273. release_firmware(ucode_raw);
  1274. return 0;
  1275. err_pci_alloc:
  1276. IWL_ERR(priv, "failed to allocate pci memory\n");
  1277. ret = -ENOMEM;
  1278. iwl_dealloc_ucode_pci(priv);
  1279. err_release:
  1280. release_firmware(ucode_raw);
  1281. error:
  1282. return ret;
  1283. }
  1284. /**
  1285. * iwl_alive_start - called after REPLY_ALIVE notification received
  1286. * from protocol/runtime uCode (initialization uCode's
  1287. * Alive gets handled by iwl_init_alive_start()).
  1288. */
  1289. static void iwl_alive_start(struct iwl_priv *priv)
  1290. {
  1291. int ret = 0;
  1292. IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
  1293. if (priv->card_alive.is_valid != UCODE_VALID_OK) {
  1294. /* We had an error bringing up the hardware, so take it
  1295. * all the way back down so we can try again */
  1296. IWL_DEBUG_INFO(priv, "Alive failed.\n");
  1297. goto restart;
  1298. }
  1299. /* Initialize uCode has loaded Runtime uCode ... verify inst image.
  1300. * This is a paranoid check, because we would not have gotten the
  1301. * "runtime" alive if code weren't properly loaded. */
  1302. if (iwl_verify_ucode(priv)) {
  1303. /* Runtime instruction load was bad;
  1304. * take it all the way back down so we can try again */
  1305. IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
  1306. goto restart;
  1307. }
  1308. iwl_clear_stations_table(priv);
  1309. ret = priv->cfg->ops->lib->alive_notify(priv);
  1310. if (ret) {
  1311. IWL_WARN(priv,
  1312. "Could not complete ALIVE transition [ntf]: %d\n", ret);
  1313. goto restart;
  1314. }
  1315. /* After the ALIVE response, we can send host commands to the uCode */
  1316. set_bit(STATUS_ALIVE, &priv->status);
  1317. if (iwl_is_rfkill(priv))
  1318. return;
  1319. ieee80211_wake_queues(priv->hw);
  1320. priv->active_rate = priv->rates_mask;
  1321. priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
  1322. if (iwl_is_associated(priv)) {
  1323. struct iwl_rxon_cmd *active_rxon =
  1324. (struct iwl_rxon_cmd *)&priv->active_rxon;
  1325. /* apply any changes in staging */
  1326. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  1327. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  1328. } else {
  1329. /* Initialize our rx_config data */
  1330. iwl_connection_init_rx_config(priv, priv->iw_mode);
  1331. if (priv->cfg->ops->hcmd->set_rxon_chain)
  1332. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  1333. memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
  1334. }
  1335. /* Configure Bluetooth device coexistence support */
  1336. iwl_send_bt_config(priv);
  1337. iwl_reset_run_time_calib(priv);
  1338. /* Configure the adapter for unassociated operation */
  1339. iwlcore_commit_rxon(priv);
  1340. /* At this point, the NIC is initialized and operational */
  1341. iwl_rf_kill_ct_config(priv);
  1342. iwl_leds_register(priv);
  1343. IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
  1344. set_bit(STATUS_READY, &priv->status);
  1345. wake_up_interruptible(&priv->wait_command_queue);
  1346. iwl_power_update_mode(priv, 1);
  1347. /* reassociate for ADHOC mode */
  1348. if (priv->vif && (priv->iw_mode == NL80211_IFTYPE_ADHOC)) {
  1349. struct sk_buff *beacon = ieee80211_beacon_get(priv->hw,
  1350. priv->vif);
  1351. if (beacon)
  1352. iwl_mac_beacon_update(priv->hw, beacon);
  1353. }
  1354. if (test_and_clear_bit(STATUS_MODE_PENDING, &priv->status))
  1355. iwl_set_mode(priv, priv->iw_mode);
  1356. return;
  1357. restart:
  1358. queue_work(priv->workqueue, &priv->restart);
  1359. }
  1360. static void iwl_cancel_deferred_work(struct iwl_priv *priv);
  1361. static void __iwl_down(struct iwl_priv *priv)
  1362. {
  1363. unsigned long flags;
  1364. int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
  1365. IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
  1366. if (!exit_pending)
  1367. set_bit(STATUS_EXIT_PENDING, &priv->status);
  1368. iwl_leds_unregister(priv);
  1369. iwl_clear_stations_table(priv);
  1370. /* Unblock any waiting calls */
  1371. wake_up_interruptible_all(&priv->wait_command_queue);
  1372. /* Wipe out the EXIT_PENDING status bit if we are not actually
  1373. * exiting the module */
  1374. if (!exit_pending)
  1375. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  1376. /* stop and reset the on-board processor */
  1377. iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
  1378. /* tell the device to stop sending interrupts */
  1379. spin_lock_irqsave(&priv->lock, flags);
  1380. iwl_disable_interrupts(priv);
  1381. spin_unlock_irqrestore(&priv->lock, flags);
  1382. iwl_synchronize_irq(priv);
  1383. if (priv->mac80211_registered)
  1384. ieee80211_stop_queues(priv->hw);
  1385. /* If we have not previously called iwl_init() then
  1386. * clear all bits but the RF Kill bit and return */
  1387. if (!iwl_is_init(priv)) {
  1388. priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  1389. STATUS_RF_KILL_HW |
  1390. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  1391. STATUS_GEO_CONFIGURED |
  1392. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  1393. STATUS_EXIT_PENDING;
  1394. goto exit;
  1395. }
  1396. /* ...otherwise clear out all the status bits but the RF Kill
  1397. * bit and continue taking the NIC down. */
  1398. priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  1399. STATUS_RF_KILL_HW |
  1400. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  1401. STATUS_GEO_CONFIGURED |
  1402. test_bit(STATUS_FW_ERROR, &priv->status) <<
  1403. STATUS_FW_ERROR |
  1404. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  1405. STATUS_EXIT_PENDING;
  1406. /* device going down, Stop using ICT table */
  1407. iwl_disable_ict(priv);
  1408. spin_lock_irqsave(&priv->lock, flags);
  1409. iwl_clear_bit(priv, CSR_GP_CNTRL,
  1410. CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  1411. spin_unlock_irqrestore(&priv->lock, flags);
  1412. iwl_txq_ctx_stop(priv);
  1413. iwl_rxq_stop(priv);
  1414. iwl_write_prph(priv, APMG_CLK_DIS_REG,
  1415. APMG_CLK_VAL_DMA_CLK_RQT);
  1416. udelay(5);
  1417. /* FIXME: apm_ops.suspend(priv) */
  1418. if (exit_pending)
  1419. priv->cfg->ops->lib->apm_ops.stop(priv);
  1420. else
  1421. priv->cfg->ops->lib->apm_ops.reset(priv);
  1422. exit:
  1423. memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
  1424. if (priv->ibss_beacon)
  1425. dev_kfree_skb(priv->ibss_beacon);
  1426. priv->ibss_beacon = NULL;
  1427. /* clear out any free frames */
  1428. iwl_clear_free_frames(priv);
  1429. }
  1430. static void iwl_down(struct iwl_priv *priv)
  1431. {
  1432. mutex_lock(&priv->mutex);
  1433. __iwl_down(priv);
  1434. mutex_unlock(&priv->mutex);
  1435. iwl_cancel_deferred_work(priv);
  1436. }
  1437. #define HW_READY_TIMEOUT (50)
  1438. static int iwl_set_hw_ready(struct iwl_priv *priv)
  1439. {
  1440. int ret = 0;
  1441. iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  1442. CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
  1443. /* See if we got it */
  1444. ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
  1445. CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
  1446. CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
  1447. HW_READY_TIMEOUT);
  1448. if (ret != -ETIMEDOUT)
  1449. priv->hw_ready = true;
  1450. else
  1451. priv->hw_ready = false;
  1452. IWL_DEBUG_INFO(priv, "hardware %s\n",
  1453. (priv->hw_ready == 1) ? "ready" : "not ready");
  1454. return ret;
  1455. }
  1456. static int iwl_prepare_card_hw(struct iwl_priv *priv)
  1457. {
  1458. int ret = 0;
  1459. IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter \n");
  1460. ret = iwl_set_hw_ready(priv);
  1461. if (priv->hw_ready)
  1462. return ret;
  1463. /* If HW is not ready, prepare the conditions to check again */
  1464. iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  1465. CSR_HW_IF_CONFIG_REG_PREPARE);
  1466. ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
  1467. ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
  1468. CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
  1469. /* HW should be ready by now, check again. */
  1470. if (ret != -ETIMEDOUT)
  1471. iwl_set_hw_ready(priv);
  1472. return ret;
  1473. }
  1474. #define MAX_HW_RESTARTS 5
  1475. static int __iwl_up(struct iwl_priv *priv)
  1476. {
  1477. int i;
  1478. int ret;
  1479. unsigned long status;
  1480. if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  1481. IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
  1482. return -EIO;
  1483. }
  1484. if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
  1485. IWL_ERR(priv, "ucode not available for device bringup\n");
  1486. return -EIO;
  1487. }
  1488. iwl_prepare_card_hw(priv);
  1489. if (!priv->hw_ready) {
  1490. IWL_WARN(priv, "Exit HW not ready\n");
  1491. return -EIO;
  1492. }
  1493. /* If platform's RF_KILL switch is NOT set to KILL */
  1494. if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
  1495. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  1496. else
  1497. set_bit(STATUS_RF_KILL_HW, &priv->status);
  1498. if (iwl_is_rfkill(priv)) {
  1499. wiphy_rfkill_set_hw_state(priv->hw->wiphy, true);
  1500. iwl_enable_interrupts(priv);
  1501. IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
  1502. return 0;
  1503. }
  1504. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  1505. ret = iwl_hw_nic_init(priv);
  1506. if (ret) {
  1507. IWL_ERR(priv, "Unable to init nic\n");
  1508. return ret;
  1509. }
  1510. /* make sure rfkill handshake bits are cleared */
  1511. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  1512. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  1513. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  1514. /* clear (again), then enable host interrupts */
  1515. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  1516. iwl_enable_interrupts(priv);
  1517. /* really make sure rfkill handshake bits are cleared */
  1518. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  1519. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  1520. /* Copy original ucode data image from disk into backup cache.
  1521. * This will be used to initialize the on-board processor's
  1522. * data SRAM for a clean start when the runtime program first loads. */
  1523. memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
  1524. priv->ucode_data.len);
  1525. for (i = 0; i < MAX_HW_RESTARTS; i++) {
  1526. iwl_clear_stations_table(priv);
  1527. /* load bootstrap state machine,
  1528. * load bootstrap program into processor's memory,
  1529. * prepare to load the "initialize" uCode */
  1530. ret = priv->cfg->ops->lib->load_ucode(priv);
  1531. if (ret) {
  1532. IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n",
  1533. ret);
  1534. continue;
  1535. }
  1536. /* start card; "initialize" will load runtime ucode */
  1537. iwl_nic_start(priv);
  1538. /* Just finish download Init or Runtime uCode image to device
  1539. * now we wait here for uCode send REPLY_ALIVE notification
  1540. * to indicate uCode is ready.
  1541. * 1) For Init uCode image, all iwlagn devices should wait here
  1542. * on STATUS_INIT_UCODE_ALIVE status bit; if timeout before
  1543. * receive the REPLY_ALIVE notification, go back and try to
  1544. * download the Init uCode image again.
  1545. * 2) For Runtime uCode image, all iwlagn devices except 4965
  1546. * wait here on STATUS_RT_UCODE_ALIVE status bit; if
  1547. * timeout before receive the REPLY_ALIVE notification, go back
  1548. * and download the Runtime uCode image again.
  1549. * 3) For 4965 Runtime uCode, it will not go through this path,
  1550. * need to wait for STATUS_RT_UCODE_ALIVE status bit in
  1551. * iwl4965_init_alive_start() function; if timeout, need to
  1552. * restart and download Init uCode image.
  1553. */
  1554. if (priv->ucode_type == UCODE_INIT)
  1555. status = STATUS_INIT_UCODE_ALIVE;
  1556. else
  1557. status = STATUS_RT_UCODE_ALIVE;
  1558. if (test_bit(status, &priv->status)) {
  1559. IWL_WARN(priv,
  1560. "%s uCode already alive? "
  1561. "Waiting for alive anyway\n",
  1562. (status == STATUS_INIT_UCODE_ALIVE)
  1563. ? "INIT" : "Runtime");
  1564. clear_bit(status, &priv->status);
  1565. }
  1566. ret = wait_event_interruptible_timeout(
  1567. priv->wait_command_queue,
  1568. test_bit(status, &priv->status),
  1569. UCODE_ALIVE_TIMEOUT);
  1570. if (!ret) {
  1571. if (!test_bit(status, &priv->status)) {
  1572. priv->ucode_type =
  1573. (status == STATUS_INIT_UCODE_ALIVE)
  1574. ? UCODE_NONE : UCODE_INIT;
  1575. IWL_ERR(priv,
  1576. "%s timeout after %dms\n",
  1577. (status == STATUS_INIT_UCODE_ALIVE)
  1578. ? "INIT" : "Runtime",
  1579. jiffies_to_msecs(UCODE_ALIVE_TIMEOUT));
  1580. continue;
  1581. }
  1582. }
  1583. IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
  1584. return 0;
  1585. }
  1586. set_bit(STATUS_EXIT_PENDING, &priv->status);
  1587. __iwl_down(priv);
  1588. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  1589. /* tried to restart and config the device for as long as our
  1590. * patience could withstand */
  1591. IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
  1592. return -EIO;
  1593. }
  1594. /*****************************************************************************
  1595. *
  1596. * Workqueue callbacks
  1597. *
  1598. *****************************************************************************/
  1599. static void iwl_bg_init_alive_start(struct work_struct *data)
  1600. {
  1601. struct iwl_priv *priv =
  1602. container_of(data, struct iwl_priv, init_alive_start.work);
  1603. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1604. return;
  1605. mutex_lock(&priv->mutex);
  1606. priv->cfg->ops->lib->init_alive_start(priv);
  1607. mutex_unlock(&priv->mutex);
  1608. }
  1609. static void iwl_bg_alive_start(struct work_struct *data)
  1610. {
  1611. struct iwl_priv *priv =
  1612. container_of(data, struct iwl_priv, alive_start.work);
  1613. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1614. return;
  1615. /* enable dram interrupt */
  1616. iwl_reset_ict(priv);
  1617. mutex_lock(&priv->mutex);
  1618. iwl_alive_start(priv);
  1619. mutex_unlock(&priv->mutex);
  1620. }
  1621. static void iwl_bg_run_time_calib_work(struct work_struct *work)
  1622. {
  1623. struct iwl_priv *priv = container_of(work, struct iwl_priv,
  1624. run_time_calib_work);
  1625. mutex_lock(&priv->mutex);
  1626. if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
  1627. test_bit(STATUS_SCANNING, &priv->status)) {
  1628. mutex_unlock(&priv->mutex);
  1629. return;
  1630. }
  1631. if (priv->start_calib) {
  1632. iwl_chain_noise_calibration(priv, &priv->statistics);
  1633. iwl_sensitivity_calibration(priv, &priv->statistics);
  1634. }
  1635. mutex_unlock(&priv->mutex);
  1636. return;
  1637. }
  1638. static void iwl_bg_up(struct work_struct *data)
  1639. {
  1640. struct iwl_priv *priv = container_of(data, struct iwl_priv, up);
  1641. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1642. return;
  1643. mutex_lock(&priv->mutex);
  1644. __iwl_up(priv);
  1645. mutex_unlock(&priv->mutex);
  1646. }
  1647. static void iwl_bg_restart(struct work_struct *data)
  1648. {
  1649. struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
  1650. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1651. return;
  1652. if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
  1653. mutex_lock(&priv->mutex);
  1654. priv->vif = NULL;
  1655. priv->is_open = 0;
  1656. mutex_unlock(&priv->mutex);
  1657. iwl_down(priv);
  1658. ieee80211_restart_hw(priv->hw);
  1659. } else {
  1660. iwl_down(priv);
  1661. queue_work(priv->workqueue, &priv->up);
  1662. }
  1663. }
  1664. static void iwl_bg_rx_replenish(struct work_struct *data)
  1665. {
  1666. struct iwl_priv *priv =
  1667. container_of(data, struct iwl_priv, rx_replenish);
  1668. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1669. return;
  1670. mutex_lock(&priv->mutex);
  1671. iwl_rx_replenish(priv);
  1672. mutex_unlock(&priv->mutex);
  1673. }
  1674. #define IWL_DELAY_NEXT_SCAN (HZ*2)
  1675. void iwl_post_associate(struct iwl_priv *priv)
  1676. {
  1677. struct ieee80211_conf *conf = NULL;
  1678. int ret = 0;
  1679. unsigned long flags;
  1680. if (priv->iw_mode == NL80211_IFTYPE_AP) {
  1681. IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__);
  1682. return;
  1683. }
  1684. IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n",
  1685. priv->assoc_id, priv->active_rxon.bssid_addr);
  1686. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1687. return;
  1688. if (!priv->vif || !priv->is_open)
  1689. return;
  1690. iwl_scan_cancel_timeout(priv, 200);
  1691. conf = ieee80211_get_hw_conf(priv->hw);
  1692. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  1693. iwlcore_commit_rxon(priv);
  1694. iwl_setup_rxon_timing(priv);
  1695. ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  1696. sizeof(priv->rxon_timing), &priv->rxon_timing);
  1697. if (ret)
  1698. IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
  1699. "Attempting to continue.\n");
  1700. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  1701. iwl_set_rxon_ht(priv, &priv->current_ht_config);
  1702. if (priv->cfg->ops->hcmd->set_rxon_chain)
  1703. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  1704. priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
  1705. IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n",
  1706. priv->assoc_id, priv->beacon_int);
  1707. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
  1708. priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  1709. else
  1710. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  1711. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  1712. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
  1713. priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  1714. else
  1715. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  1716. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  1717. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  1718. }
  1719. iwlcore_commit_rxon(priv);
  1720. switch (priv->iw_mode) {
  1721. case NL80211_IFTYPE_STATION:
  1722. break;
  1723. case NL80211_IFTYPE_ADHOC:
  1724. /* assume default assoc id */
  1725. priv->assoc_id = 1;
  1726. iwl_rxon_add_station(priv, priv->bssid, 0);
  1727. iwl_send_beacon_cmd(priv);
  1728. break;
  1729. default:
  1730. IWL_ERR(priv, "%s Should not be called in %d mode\n",
  1731. __func__, priv->iw_mode);
  1732. break;
  1733. }
  1734. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  1735. priv->assoc_station_added = 1;
  1736. spin_lock_irqsave(&priv->lock, flags);
  1737. iwl_activate_qos(priv, 0);
  1738. spin_unlock_irqrestore(&priv->lock, flags);
  1739. /* the chain noise calibration will enabled PM upon completion
  1740. * If chain noise has already been run, then we need to enable
  1741. * power management here */
  1742. if (priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE)
  1743. iwl_power_update_mode(priv, 0);
  1744. /* Enable Rx differential gain and sensitivity calibrations */
  1745. iwl_chain_noise_reset(priv);
  1746. priv->start_calib = 1;
  1747. }
  1748. /*****************************************************************************
  1749. *
  1750. * mac80211 entry point functions
  1751. *
  1752. *****************************************************************************/
  1753. #define UCODE_READY_TIMEOUT (4 * HZ)
  1754. static int iwl_mac_start(struct ieee80211_hw *hw)
  1755. {
  1756. struct iwl_priv *priv = hw->priv;
  1757. int ret;
  1758. IWL_DEBUG_MAC80211(priv, "enter\n");
  1759. /* we should be verifying the device is ready to be opened */
  1760. mutex_lock(&priv->mutex);
  1761. /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
  1762. * ucode filename and max sizes are card-specific. */
  1763. if (!priv->ucode_code.len) {
  1764. ret = iwl_read_ucode(priv);
  1765. if (ret) {
  1766. IWL_ERR(priv, "Could not read microcode: %d\n", ret);
  1767. mutex_unlock(&priv->mutex);
  1768. return ret;
  1769. }
  1770. }
  1771. ret = __iwl_up(priv);
  1772. mutex_unlock(&priv->mutex);
  1773. if (ret)
  1774. return ret;
  1775. if (iwl_is_rfkill(priv))
  1776. goto out;
  1777. IWL_DEBUG_INFO(priv, "Start UP work done.\n");
  1778. /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
  1779. * mac80211 will not be run successfully. */
  1780. ret = wait_event_interruptible_timeout(priv->wait_command_queue,
  1781. test_bit(STATUS_READY, &priv->status),
  1782. UCODE_READY_TIMEOUT);
  1783. if (!ret) {
  1784. if (!test_bit(STATUS_READY, &priv->status)) {
  1785. IWL_ERR(priv, "START_ALIVE timeout after %dms.\n",
  1786. jiffies_to_msecs(UCODE_READY_TIMEOUT));
  1787. return -ETIMEDOUT;
  1788. }
  1789. }
  1790. out:
  1791. priv->is_open = 1;
  1792. IWL_DEBUG_MAC80211(priv, "leave\n");
  1793. return 0;
  1794. }
  1795. static void iwl_mac_stop(struct ieee80211_hw *hw)
  1796. {
  1797. struct iwl_priv *priv = hw->priv;
  1798. IWL_DEBUG_MAC80211(priv, "enter\n");
  1799. if (!priv->is_open)
  1800. return;
  1801. priv->is_open = 0;
  1802. if (iwl_is_ready_rf(priv)) {
  1803. /* stop mac, cancel any scan request and clear
  1804. * RXON_FILTER_ASSOC_MSK BIT
  1805. */
  1806. mutex_lock(&priv->mutex);
  1807. iwl_scan_cancel_timeout(priv, 100);
  1808. mutex_unlock(&priv->mutex);
  1809. }
  1810. iwl_down(priv);
  1811. flush_workqueue(priv->workqueue);
  1812. /* enable interrupts again in order to receive rfkill changes */
  1813. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  1814. iwl_enable_interrupts(priv);
  1815. IWL_DEBUG_MAC80211(priv, "leave\n");
  1816. }
  1817. static int iwl_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
  1818. {
  1819. struct iwl_priv *priv = hw->priv;
  1820. IWL_DEBUG_MACDUMP(priv, "enter\n");
  1821. IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
  1822. ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
  1823. if (iwl_tx_skb(priv, skb))
  1824. dev_kfree_skb_any(skb);
  1825. IWL_DEBUG_MACDUMP(priv, "leave\n");
  1826. return NETDEV_TX_OK;
  1827. }
  1828. void iwl_config_ap(struct iwl_priv *priv)
  1829. {
  1830. int ret = 0;
  1831. unsigned long flags;
  1832. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1833. return;
  1834. /* The following should be done only at AP bring up */
  1835. if (!iwl_is_associated(priv)) {
  1836. /* RXON - unassoc (to set timing command) */
  1837. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  1838. iwlcore_commit_rxon(priv);
  1839. /* RXON Timing */
  1840. iwl_setup_rxon_timing(priv);
  1841. ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  1842. sizeof(priv->rxon_timing), &priv->rxon_timing);
  1843. if (ret)
  1844. IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
  1845. "Attempting to continue.\n");
  1846. if (priv->cfg->ops->hcmd->set_rxon_chain)
  1847. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  1848. /* FIXME: what should be the assoc_id for AP? */
  1849. priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
  1850. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
  1851. priv->staging_rxon.flags |=
  1852. RXON_FLG_SHORT_PREAMBLE_MSK;
  1853. else
  1854. priv->staging_rxon.flags &=
  1855. ~RXON_FLG_SHORT_PREAMBLE_MSK;
  1856. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  1857. if (priv->assoc_capability &
  1858. WLAN_CAPABILITY_SHORT_SLOT_TIME)
  1859. priv->staging_rxon.flags |=
  1860. RXON_FLG_SHORT_SLOT_MSK;
  1861. else
  1862. priv->staging_rxon.flags &=
  1863. ~RXON_FLG_SHORT_SLOT_MSK;
  1864. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  1865. priv->staging_rxon.flags &=
  1866. ~RXON_FLG_SHORT_SLOT_MSK;
  1867. }
  1868. /* restore RXON assoc */
  1869. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  1870. iwlcore_commit_rxon(priv);
  1871. spin_lock_irqsave(&priv->lock, flags);
  1872. iwl_activate_qos(priv, 1);
  1873. spin_unlock_irqrestore(&priv->lock, flags);
  1874. iwl_rxon_add_station(priv, iwl_bcast_addr, 0);
  1875. }
  1876. iwl_send_beacon_cmd(priv);
  1877. /* FIXME - we need to add code here to detect a totally new
  1878. * configuration, reset the AP, unassoc, rxon timing, assoc,
  1879. * clear sta table, add BCAST sta... */
  1880. }
  1881. static void iwl_mac_update_tkip_key(struct ieee80211_hw *hw,
  1882. struct ieee80211_key_conf *keyconf, const u8 *addr,
  1883. u32 iv32, u16 *phase1key)
  1884. {
  1885. struct iwl_priv *priv = hw->priv;
  1886. IWL_DEBUG_MAC80211(priv, "enter\n");
  1887. iwl_update_tkip_key(priv, keyconf, addr, iv32, phase1key);
  1888. IWL_DEBUG_MAC80211(priv, "leave\n");
  1889. }
  1890. static int iwl_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
  1891. struct ieee80211_vif *vif,
  1892. struct ieee80211_sta *sta,
  1893. struct ieee80211_key_conf *key)
  1894. {
  1895. struct iwl_priv *priv = hw->priv;
  1896. const u8 *addr;
  1897. int ret;
  1898. u8 sta_id;
  1899. bool is_default_wep_key = false;
  1900. IWL_DEBUG_MAC80211(priv, "enter\n");
  1901. if (priv->cfg->mod_params->sw_crypto) {
  1902. IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
  1903. return -EOPNOTSUPP;
  1904. }
  1905. addr = sta ? sta->addr : iwl_bcast_addr;
  1906. sta_id = iwl_find_station(priv, addr);
  1907. if (sta_id == IWL_INVALID_STATION) {
  1908. IWL_DEBUG_MAC80211(priv, "leave - %pM not in station map.\n",
  1909. addr);
  1910. return -EINVAL;
  1911. }
  1912. mutex_lock(&priv->mutex);
  1913. iwl_scan_cancel_timeout(priv, 100);
  1914. mutex_unlock(&priv->mutex);
  1915. /* If we are getting WEP group key and we didn't receive any key mapping
  1916. * so far, we are in legacy wep mode (group key only), otherwise we are
  1917. * in 1X mode.
  1918. * In legacy wep mode, we use another host command to the uCode */
  1919. if (key->alg == ALG_WEP && sta_id == priv->hw_params.bcast_sta_id &&
  1920. priv->iw_mode != NL80211_IFTYPE_AP) {
  1921. if (cmd == SET_KEY)
  1922. is_default_wep_key = !priv->key_mapping_key;
  1923. else
  1924. is_default_wep_key =
  1925. (key->hw_key_idx == HW_KEY_DEFAULT);
  1926. }
  1927. switch (cmd) {
  1928. case SET_KEY:
  1929. if (is_default_wep_key)
  1930. ret = iwl_set_default_wep_key(priv, key);
  1931. else
  1932. ret = iwl_set_dynamic_key(priv, key, sta_id);
  1933. IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
  1934. break;
  1935. case DISABLE_KEY:
  1936. if (is_default_wep_key)
  1937. ret = iwl_remove_default_wep_key(priv, key);
  1938. else
  1939. ret = iwl_remove_dynamic_key(priv, key, sta_id);
  1940. IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
  1941. break;
  1942. default:
  1943. ret = -EINVAL;
  1944. }
  1945. IWL_DEBUG_MAC80211(priv, "leave\n");
  1946. return ret;
  1947. }
  1948. static int iwl_mac_ampdu_action(struct ieee80211_hw *hw,
  1949. enum ieee80211_ampdu_mlme_action action,
  1950. struct ieee80211_sta *sta, u16 tid, u16 *ssn)
  1951. {
  1952. struct iwl_priv *priv = hw->priv;
  1953. int ret;
  1954. IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
  1955. sta->addr, tid);
  1956. if (!(priv->cfg->sku & IWL_SKU_N))
  1957. return -EACCES;
  1958. switch (action) {
  1959. case IEEE80211_AMPDU_RX_START:
  1960. IWL_DEBUG_HT(priv, "start Rx\n");
  1961. return iwl_sta_rx_agg_start(priv, sta->addr, tid, *ssn);
  1962. case IEEE80211_AMPDU_RX_STOP:
  1963. IWL_DEBUG_HT(priv, "stop Rx\n");
  1964. ret = iwl_sta_rx_agg_stop(priv, sta->addr, tid);
  1965. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1966. return 0;
  1967. else
  1968. return ret;
  1969. case IEEE80211_AMPDU_TX_START:
  1970. IWL_DEBUG_HT(priv, "start Tx\n");
  1971. return iwl_tx_agg_start(priv, sta->addr, tid, ssn);
  1972. case IEEE80211_AMPDU_TX_STOP:
  1973. IWL_DEBUG_HT(priv, "stop Tx\n");
  1974. ret = iwl_tx_agg_stop(priv, sta->addr, tid);
  1975. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1976. return 0;
  1977. else
  1978. return ret;
  1979. default:
  1980. IWL_DEBUG_HT(priv, "unknown\n");
  1981. return -EINVAL;
  1982. break;
  1983. }
  1984. return 0;
  1985. }
  1986. static int iwl_mac_get_stats(struct ieee80211_hw *hw,
  1987. struct ieee80211_low_level_stats *stats)
  1988. {
  1989. struct iwl_priv *priv = hw->priv;
  1990. priv = hw->priv;
  1991. IWL_DEBUG_MAC80211(priv, "enter\n");
  1992. IWL_DEBUG_MAC80211(priv, "leave\n");
  1993. return 0;
  1994. }
  1995. /*****************************************************************************
  1996. *
  1997. * sysfs attributes
  1998. *
  1999. *****************************************************************************/
  2000. #ifdef CONFIG_IWLWIFI_DEBUG
  2001. /*
  2002. * The following adds a new attribute to the sysfs representation
  2003. * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
  2004. * used for controlling the debug level.
  2005. *
  2006. * See the level definitions in iwl for details.
  2007. *
  2008. * FIXME This file can be deprecated as the module parameter is
  2009. * writable and users can thus also change the debug level
  2010. * using the /sys/module/iwl3945/parameters/debug file.
  2011. */
  2012. static ssize_t show_debug_level(struct device *d,
  2013. struct device_attribute *attr, char *buf)
  2014. {
  2015. return sprintf(buf, "0x%08X\n", iwl_debug_level);
  2016. }
  2017. static ssize_t store_debug_level(struct device *d,
  2018. struct device_attribute *attr,
  2019. const char *buf, size_t count)
  2020. {
  2021. struct iwl_priv *priv = dev_get_drvdata(d);
  2022. unsigned long val;
  2023. int ret;
  2024. ret = strict_strtoul(buf, 0, &val);
  2025. if (ret)
  2026. IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
  2027. else
  2028. iwl_debug_level = val;
  2029. return strnlen(buf, count);
  2030. }
  2031. static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
  2032. show_debug_level, store_debug_level);
  2033. #endif /* CONFIG_IWLWIFI_DEBUG */
  2034. static ssize_t show_version(struct device *d,
  2035. struct device_attribute *attr, char *buf)
  2036. {
  2037. struct iwl_priv *priv = dev_get_drvdata(d);
  2038. struct iwl_alive_resp *palive = &priv->card_alive;
  2039. ssize_t pos = 0;
  2040. u16 eeprom_ver;
  2041. if (palive->is_valid)
  2042. pos += sprintf(buf + pos,
  2043. "fw version: 0x%01X.0x%01X.0x%01X.0x%01X\n"
  2044. "fw type: 0x%01X 0x%01X\n",
  2045. palive->ucode_major, palive->ucode_minor,
  2046. palive->sw_rev[0], palive->sw_rev[1],
  2047. palive->ver_type, palive->ver_subtype);
  2048. else
  2049. pos += sprintf(buf + pos, "fw not loaded\n");
  2050. if (priv->eeprom) {
  2051. eeprom_ver = iwl_eeprom_query16(priv, EEPROM_VERSION);
  2052. pos += sprintf(buf + pos, "NVM Type: %s, version: 0x%x\n",
  2053. (priv->nvm_device_type == NVM_DEVICE_TYPE_OTP)
  2054. ? "OTP" : "EEPROM", eeprom_ver);
  2055. } else {
  2056. pos += sprintf(buf + pos, "EEPROM not initialzed\n");
  2057. }
  2058. return pos;
  2059. }
  2060. static DEVICE_ATTR(version, S_IWUSR | S_IRUGO, show_version, NULL);
  2061. static ssize_t show_temperature(struct device *d,
  2062. struct device_attribute *attr, char *buf)
  2063. {
  2064. struct iwl_priv *priv = dev_get_drvdata(d);
  2065. if (!iwl_is_alive(priv))
  2066. return -EAGAIN;
  2067. return sprintf(buf, "%d\n", priv->temperature);
  2068. }
  2069. static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
  2070. static ssize_t show_tx_power(struct device *d,
  2071. struct device_attribute *attr, char *buf)
  2072. {
  2073. struct iwl_priv *priv = dev_get_drvdata(d);
  2074. if (!iwl_is_ready_rf(priv))
  2075. return sprintf(buf, "off\n");
  2076. else
  2077. return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
  2078. }
  2079. static ssize_t store_tx_power(struct device *d,
  2080. struct device_attribute *attr,
  2081. const char *buf, size_t count)
  2082. {
  2083. struct iwl_priv *priv = dev_get_drvdata(d);
  2084. unsigned long val;
  2085. int ret;
  2086. ret = strict_strtoul(buf, 10, &val);
  2087. if (ret)
  2088. IWL_INFO(priv, "%s is not in decimal form.\n", buf);
  2089. else
  2090. iwl_set_tx_power(priv, val, false);
  2091. return count;
  2092. }
  2093. static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
  2094. static ssize_t show_flags(struct device *d,
  2095. struct device_attribute *attr, char *buf)
  2096. {
  2097. struct iwl_priv *priv = dev_get_drvdata(d);
  2098. return sprintf(buf, "0x%04X\n", priv->active_rxon.flags);
  2099. }
  2100. static ssize_t store_flags(struct device *d,
  2101. struct device_attribute *attr,
  2102. const char *buf, size_t count)
  2103. {
  2104. struct iwl_priv *priv = dev_get_drvdata(d);
  2105. unsigned long val;
  2106. u32 flags;
  2107. int ret = strict_strtoul(buf, 0, &val);
  2108. if (ret)
  2109. return ret;
  2110. flags = (u32)val;
  2111. mutex_lock(&priv->mutex);
  2112. if (le32_to_cpu(priv->staging_rxon.flags) != flags) {
  2113. /* Cancel any currently running scans... */
  2114. if (iwl_scan_cancel_timeout(priv, 100))
  2115. IWL_WARN(priv, "Could not cancel scan.\n");
  2116. else {
  2117. IWL_DEBUG_INFO(priv, "Commit rxon.flags = 0x%04X\n", flags);
  2118. priv->staging_rxon.flags = cpu_to_le32(flags);
  2119. iwlcore_commit_rxon(priv);
  2120. }
  2121. }
  2122. mutex_unlock(&priv->mutex);
  2123. return count;
  2124. }
  2125. static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags);
  2126. static ssize_t show_filter_flags(struct device *d,
  2127. struct device_attribute *attr, char *buf)
  2128. {
  2129. struct iwl_priv *priv = dev_get_drvdata(d);
  2130. return sprintf(buf, "0x%04X\n",
  2131. le32_to_cpu(priv->active_rxon.filter_flags));
  2132. }
  2133. static ssize_t store_filter_flags(struct device *d,
  2134. struct device_attribute *attr,
  2135. const char *buf, size_t count)
  2136. {
  2137. struct iwl_priv *priv = dev_get_drvdata(d);
  2138. unsigned long val;
  2139. u32 filter_flags;
  2140. int ret = strict_strtoul(buf, 0, &val);
  2141. if (ret)
  2142. return ret;
  2143. filter_flags = (u32)val;
  2144. mutex_lock(&priv->mutex);
  2145. if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) {
  2146. /* Cancel any currently running scans... */
  2147. if (iwl_scan_cancel_timeout(priv, 100))
  2148. IWL_WARN(priv, "Could not cancel scan.\n");
  2149. else {
  2150. IWL_DEBUG_INFO(priv, "Committing rxon.filter_flags = "
  2151. "0x%04X\n", filter_flags);
  2152. priv->staging_rxon.filter_flags =
  2153. cpu_to_le32(filter_flags);
  2154. iwlcore_commit_rxon(priv);
  2155. }
  2156. }
  2157. mutex_unlock(&priv->mutex);
  2158. return count;
  2159. }
  2160. static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags,
  2161. store_filter_flags);
  2162. static ssize_t store_power_level(struct device *d,
  2163. struct device_attribute *attr,
  2164. const char *buf, size_t count)
  2165. {
  2166. struct iwl_priv *priv = dev_get_drvdata(d);
  2167. int ret;
  2168. unsigned long mode;
  2169. mutex_lock(&priv->mutex);
  2170. ret = strict_strtoul(buf, 10, &mode);
  2171. if (ret)
  2172. goto out;
  2173. ret = iwl_power_set_user_mode(priv, mode);
  2174. if (ret) {
  2175. IWL_DEBUG_MAC80211(priv, "failed setting power mode.\n");
  2176. goto out;
  2177. }
  2178. ret = count;
  2179. out:
  2180. mutex_unlock(&priv->mutex);
  2181. return ret;
  2182. }
  2183. static ssize_t show_power_level(struct device *d,
  2184. struct device_attribute *attr, char *buf)
  2185. {
  2186. struct iwl_priv *priv = dev_get_drvdata(d);
  2187. int level = priv->power_data.power_mode;
  2188. char *p = buf;
  2189. p += sprintf(p, "%d\n", level);
  2190. return p - buf + 1;
  2191. }
  2192. static DEVICE_ATTR(power_level, S_IWUSR | S_IRUSR, show_power_level,
  2193. store_power_level);
  2194. static ssize_t show_statistics(struct device *d,
  2195. struct device_attribute *attr, char *buf)
  2196. {
  2197. struct iwl_priv *priv = dev_get_drvdata(d);
  2198. u32 size = sizeof(struct iwl_notif_statistics);
  2199. u32 len = 0, ofs = 0;
  2200. u8 *data = (u8 *)&priv->statistics;
  2201. int rc = 0;
  2202. if (!iwl_is_alive(priv))
  2203. return -EAGAIN;
  2204. mutex_lock(&priv->mutex);
  2205. rc = iwl_send_statistics_request(priv, 0);
  2206. mutex_unlock(&priv->mutex);
  2207. if (rc) {
  2208. len = sprintf(buf,
  2209. "Error sending statistics request: 0x%08X\n", rc);
  2210. return len;
  2211. }
  2212. while (size && (PAGE_SIZE - len)) {
  2213. hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
  2214. PAGE_SIZE - len, 1);
  2215. len = strlen(buf);
  2216. if (PAGE_SIZE - len)
  2217. buf[len++] = '\n';
  2218. ofs += 16;
  2219. size -= min(size, 16U);
  2220. }
  2221. return len;
  2222. }
  2223. static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL);
  2224. /*****************************************************************************
  2225. *
  2226. * driver setup and teardown
  2227. *
  2228. *****************************************************************************/
  2229. static void iwl_setup_deferred_work(struct iwl_priv *priv)
  2230. {
  2231. priv->workqueue = create_singlethread_workqueue(DRV_NAME);
  2232. init_waitqueue_head(&priv->wait_command_queue);
  2233. INIT_WORK(&priv->up, iwl_bg_up);
  2234. INIT_WORK(&priv->restart, iwl_bg_restart);
  2235. INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
  2236. INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
  2237. INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
  2238. INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start);
  2239. INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start);
  2240. iwl_setup_scan_deferred_work(priv);
  2241. if (priv->cfg->ops->lib->setup_deferred_work)
  2242. priv->cfg->ops->lib->setup_deferred_work(priv);
  2243. init_timer(&priv->statistics_periodic);
  2244. priv->statistics_periodic.data = (unsigned long)priv;
  2245. priv->statistics_periodic.function = iwl_bg_statistics_periodic;
  2246. if (!priv->cfg->use_isr_legacy)
  2247. tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
  2248. iwl_irq_tasklet, (unsigned long)priv);
  2249. else
  2250. tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
  2251. iwl_irq_tasklet_legacy, (unsigned long)priv);
  2252. }
  2253. static void iwl_cancel_deferred_work(struct iwl_priv *priv)
  2254. {
  2255. if (priv->cfg->ops->lib->cancel_deferred_work)
  2256. priv->cfg->ops->lib->cancel_deferred_work(priv);
  2257. cancel_delayed_work_sync(&priv->init_alive_start);
  2258. cancel_delayed_work(&priv->scan_check);
  2259. cancel_delayed_work(&priv->alive_start);
  2260. cancel_work_sync(&priv->beacon_update);
  2261. del_timer_sync(&priv->statistics_periodic);
  2262. }
  2263. static struct attribute *iwl_sysfs_entries[] = {
  2264. &dev_attr_flags.attr,
  2265. &dev_attr_filter_flags.attr,
  2266. &dev_attr_power_level.attr,
  2267. &dev_attr_statistics.attr,
  2268. &dev_attr_temperature.attr,
  2269. &dev_attr_tx_power.attr,
  2270. #ifdef CONFIG_IWLWIFI_DEBUG
  2271. &dev_attr_debug_level.attr,
  2272. #endif
  2273. &dev_attr_version.attr,
  2274. NULL
  2275. };
  2276. static struct attribute_group iwl_attribute_group = {
  2277. .name = NULL, /* put in device directory */
  2278. .attrs = iwl_sysfs_entries,
  2279. };
  2280. static struct ieee80211_ops iwl_hw_ops = {
  2281. .tx = iwl_mac_tx,
  2282. .start = iwl_mac_start,
  2283. .stop = iwl_mac_stop,
  2284. .add_interface = iwl_mac_add_interface,
  2285. .remove_interface = iwl_mac_remove_interface,
  2286. .config = iwl_mac_config,
  2287. .configure_filter = iwl_configure_filter,
  2288. .set_key = iwl_mac_set_key,
  2289. .update_tkip_key = iwl_mac_update_tkip_key,
  2290. .get_stats = iwl_mac_get_stats,
  2291. .get_tx_stats = iwl_mac_get_tx_stats,
  2292. .conf_tx = iwl_mac_conf_tx,
  2293. .reset_tsf = iwl_mac_reset_tsf,
  2294. .bss_info_changed = iwl_bss_info_changed,
  2295. .ampdu_action = iwl_mac_ampdu_action,
  2296. .hw_scan = iwl_mac_hw_scan
  2297. };
  2298. static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  2299. {
  2300. int err = 0;
  2301. struct iwl_priv *priv;
  2302. struct ieee80211_hw *hw;
  2303. struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
  2304. unsigned long flags;
  2305. u16 pci_cmd;
  2306. /************************
  2307. * 1. Allocating HW data
  2308. ************************/
  2309. /* Disabling hardware scan means that mac80211 will perform scans
  2310. * "the hard way", rather than using device's scan. */
  2311. if (cfg->mod_params->disable_hw_scan) {
  2312. if (iwl_debug_level & IWL_DL_INFO)
  2313. dev_printk(KERN_DEBUG, &(pdev->dev),
  2314. "Disabling hw_scan\n");
  2315. iwl_hw_ops.hw_scan = NULL;
  2316. }
  2317. hw = iwl_alloc_all(cfg, &iwl_hw_ops);
  2318. if (!hw) {
  2319. err = -ENOMEM;
  2320. goto out;
  2321. }
  2322. priv = hw->priv;
  2323. /* At this point both hw and priv are allocated. */
  2324. SET_IEEE80211_DEV(hw, &pdev->dev);
  2325. IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
  2326. priv->cfg = cfg;
  2327. priv->pci_dev = pdev;
  2328. priv->inta_mask = CSR_INI_SET_MASK;
  2329. #ifdef CONFIG_IWLWIFI_DEBUG
  2330. atomic_set(&priv->restrict_refcnt, 0);
  2331. #endif
  2332. /**************************
  2333. * 2. Initializing PCI bus
  2334. **************************/
  2335. if (pci_enable_device(pdev)) {
  2336. err = -ENODEV;
  2337. goto out_ieee80211_free_hw;
  2338. }
  2339. pci_set_master(pdev);
  2340. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
  2341. if (!err)
  2342. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
  2343. if (err) {
  2344. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  2345. if (!err)
  2346. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
  2347. /* both attempts failed: */
  2348. if (err) {
  2349. IWL_WARN(priv, "No suitable DMA available.\n");
  2350. goto out_pci_disable_device;
  2351. }
  2352. }
  2353. err = pci_request_regions(pdev, DRV_NAME);
  2354. if (err)
  2355. goto out_pci_disable_device;
  2356. pci_set_drvdata(pdev, priv);
  2357. /***********************
  2358. * 3. Read REV register
  2359. ***********************/
  2360. priv->hw_base = pci_iomap(pdev, 0, 0);
  2361. if (!priv->hw_base) {
  2362. err = -ENODEV;
  2363. goto out_pci_release_regions;
  2364. }
  2365. IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
  2366. (unsigned long long) pci_resource_len(pdev, 0));
  2367. IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
  2368. /* this spin lock will be used in apm_ops.init and EEPROM access
  2369. * we should init now
  2370. */
  2371. spin_lock_init(&priv->reg_lock);
  2372. iwl_hw_detect(priv);
  2373. IWL_INFO(priv, "Detected Intel Wireless WiFi Link %s REV=0x%X\n",
  2374. priv->cfg->name, priv->hw_rev);
  2375. /* We disable the RETRY_TIMEOUT register (0x41) to keep
  2376. * PCI Tx retries from interfering with C3 CPU state */
  2377. pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
  2378. iwl_prepare_card_hw(priv);
  2379. if (!priv->hw_ready) {
  2380. IWL_WARN(priv, "Failed, HW not ready\n");
  2381. goto out_iounmap;
  2382. }
  2383. /* amp init */
  2384. err = priv->cfg->ops->lib->apm_ops.init(priv);
  2385. if (err < 0) {
  2386. IWL_ERR(priv, "Failed to init APMG\n");
  2387. goto out_iounmap;
  2388. }
  2389. /*****************
  2390. * 4. Read EEPROM
  2391. *****************/
  2392. /* Read the EEPROM */
  2393. err = iwl_eeprom_init(priv);
  2394. if (err) {
  2395. IWL_ERR(priv, "Unable to init EEPROM\n");
  2396. goto out_iounmap;
  2397. }
  2398. err = iwl_eeprom_check_version(priv);
  2399. if (err)
  2400. goto out_free_eeprom;
  2401. /* extract MAC Address */
  2402. iwl_eeprom_get_mac(priv, priv->mac_addr);
  2403. IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->mac_addr);
  2404. SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
  2405. /************************
  2406. * 5. Setup HW constants
  2407. ************************/
  2408. if (iwl_set_hw_params(priv)) {
  2409. IWL_ERR(priv, "failed to set hw parameters\n");
  2410. goto out_free_eeprom;
  2411. }
  2412. /*******************
  2413. * 6. Setup priv
  2414. *******************/
  2415. err = iwl_init_drv(priv);
  2416. if (err)
  2417. goto out_free_eeprom;
  2418. /* At this point both hw and priv are initialized. */
  2419. /********************
  2420. * 7. Setup services
  2421. ********************/
  2422. spin_lock_irqsave(&priv->lock, flags);
  2423. iwl_disable_interrupts(priv);
  2424. spin_unlock_irqrestore(&priv->lock, flags);
  2425. pci_enable_msi(priv->pci_dev);
  2426. iwl_alloc_isr_ict(priv);
  2427. err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr,
  2428. IRQF_SHARED, DRV_NAME, priv);
  2429. if (err) {
  2430. IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
  2431. goto out_disable_msi;
  2432. }
  2433. err = sysfs_create_group(&pdev->dev.kobj, &iwl_attribute_group);
  2434. if (err) {
  2435. IWL_ERR(priv, "failed to create sysfs device attributes\n");
  2436. goto out_free_irq;
  2437. }
  2438. iwl_setup_deferred_work(priv);
  2439. iwl_setup_rx_handlers(priv);
  2440. /**********************************
  2441. * 8. Setup and register mac80211
  2442. **********************************/
  2443. /* enable interrupts if needed: hw bug w/a */
  2444. pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
  2445. if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
  2446. pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
  2447. pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
  2448. }
  2449. iwl_enable_interrupts(priv);
  2450. err = iwl_setup_mac(priv);
  2451. if (err)
  2452. goto out_remove_sysfs;
  2453. err = iwl_dbgfs_register(priv, DRV_NAME);
  2454. if (err)
  2455. IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
  2456. /* If platform's RF_KILL switch is NOT set to KILL */
  2457. if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
  2458. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  2459. else
  2460. set_bit(STATUS_RF_KILL_HW, &priv->status);
  2461. wiphy_rfkill_set_hw_state(priv->hw->wiphy,
  2462. test_bit(STATUS_RF_KILL_HW, &priv->status));
  2463. iwl_power_initialize(priv);
  2464. return 0;
  2465. out_remove_sysfs:
  2466. destroy_workqueue(priv->workqueue);
  2467. priv->workqueue = NULL;
  2468. sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
  2469. out_free_irq:
  2470. free_irq(priv->pci_dev->irq, priv);
  2471. iwl_free_isr_ict(priv);
  2472. out_disable_msi:
  2473. pci_disable_msi(priv->pci_dev);
  2474. iwl_uninit_drv(priv);
  2475. out_free_eeprom:
  2476. iwl_eeprom_free(priv);
  2477. out_iounmap:
  2478. pci_iounmap(pdev, priv->hw_base);
  2479. out_pci_release_regions:
  2480. pci_set_drvdata(pdev, NULL);
  2481. pci_release_regions(pdev);
  2482. out_pci_disable_device:
  2483. pci_disable_device(pdev);
  2484. out_ieee80211_free_hw:
  2485. ieee80211_free_hw(priv->hw);
  2486. out:
  2487. return err;
  2488. }
  2489. static void __devexit iwl_pci_remove(struct pci_dev *pdev)
  2490. {
  2491. struct iwl_priv *priv = pci_get_drvdata(pdev);
  2492. unsigned long flags;
  2493. if (!priv)
  2494. return;
  2495. IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
  2496. iwl_dbgfs_unregister(priv);
  2497. sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
  2498. /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
  2499. * to be called and iwl_down since we are removing the device
  2500. * we need to set STATUS_EXIT_PENDING bit.
  2501. */
  2502. set_bit(STATUS_EXIT_PENDING, &priv->status);
  2503. if (priv->mac80211_registered) {
  2504. ieee80211_unregister_hw(priv->hw);
  2505. priv->mac80211_registered = 0;
  2506. } else {
  2507. iwl_down(priv);
  2508. }
  2509. /* make sure we flush any pending irq or
  2510. * tasklet for the driver
  2511. */
  2512. spin_lock_irqsave(&priv->lock, flags);
  2513. iwl_disable_interrupts(priv);
  2514. spin_unlock_irqrestore(&priv->lock, flags);
  2515. iwl_synchronize_irq(priv);
  2516. iwl_dealloc_ucode_pci(priv);
  2517. if (priv->rxq.bd)
  2518. iwl_rx_queue_free(priv, &priv->rxq);
  2519. iwl_hw_txq_ctx_free(priv);
  2520. iwl_clear_stations_table(priv);
  2521. iwl_eeprom_free(priv);
  2522. /*netif_stop_queue(dev); */
  2523. flush_workqueue(priv->workqueue);
  2524. /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
  2525. * priv->workqueue... so we can't take down the workqueue
  2526. * until now... */
  2527. destroy_workqueue(priv->workqueue);
  2528. priv->workqueue = NULL;
  2529. free_irq(priv->pci_dev->irq, priv);
  2530. pci_disable_msi(priv->pci_dev);
  2531. pci_iounmap(pdev, priv->hw_base);
  2532. pci_release_regions(pdev);
  2533. pci_disable_device(pdev);
  2534. pci_set_drvdata(pdev, NULL);
  2535. iwl_uninit_drv(priv);
  2536. iwl_free_isr_ict(priv);
  2537. if (priv->ibss_beacon)
  2538. dev_kfree_skb(priv->ibss_beacon);
  2539. ieee80211_free_hw(priv->hw);
  2540. }
  2541. /*****************************************************************************
  2542. *
  2543. * driver and module entry point
  2544. *
  2545. *****************************************************************************/
  2546. /* Hardware specific file defines the PCI IDs table for that hardware module */
  2547. static struct pci_device_id iwl_hw_card_ids[] = {
  2548. #ifdef CONFIG_IWL4965
  2549. {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_agn_cfg)},
  2550. {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_agn_cfg)},
  2551. #endif /* CONFIG_IWL4965 */
  2552. #ifdef CONFIG_IWL5000
  2553. {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bg_cfg)},
  2554. {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bg_cfg)},
  2555. {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)},
  2556. {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)},
  2557. {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)},
  2558. {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)},
  2559. {IWL_PCI_DEVICE(0x4232, PCI_ANY_ID, iwl5100_agn_cfg)},
  2560. {IWL_PCI_DEVICE(0x4235, PCI_ANY_ID, iwl5300_agn_cfg)},
  2561. {IWL_PCI_DEVICE(0x4236, PCI_ANY_ID, iwl5300_agn_cfg)},
  2562. {IWL_PCI_DEVICE(0x4237, PCI_ANY_ID, iwl5100_agn_cfg)},
  2563. /* 5350 WiFi/WiMax */
  2564. {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)},
  2565. {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)},
  2566. {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)},
  2567. /* 5150 Wifi/WiMax */
  2568. {IWL_PCI_DEVICE(0x423C, PCI_ANY_ID, iwl5150_agn_cfg)},
  2569. {IWL_PCI_DEVICE(0x423D, PCI_ANY_ID, iwl5150_agn_cfg)},
  2570. /* 6000/6050 Series */
  2571. {IWL_PCI_DEVICE(0x0082, 0x1102, iwl6000_2ag_cfg)},
  2572. {IWL_PCI_DEVICE(0x0085, 0x1112, iwl6000_2ag_cfg)},
  2573. {IWL_PCI_DEVICE(0x0082, 0x1122, iwl6000_2ag_cfg)},
  2574. {IWL_PCI_DEVICE(0x422B, PCI_ANY_ID, iwl6000_3agn_cfg)},
  2575. {IWL_PCI_DEVICE(0x422C, PCI_ANY_ID, iwl6000_2agn_cfg)},
  2576. {IWL_PCI_DEVICE(0x4238, PCI_ANY_ID, iwl6000_3agn_cfg)},
  2577. {IWL_PCI_DEVICE(0x4239, PCI_ANY_ID, iwl6000_2agn_cfg)},
  2578. {IWL_PCI_DEVICE(0x0082, PCI_ANY_ID, iwl6000_2agn_cfg)},
  2579. {IWL_PCI_DEVICE(0x0085, PCI_ANY_ID, iwl6000_3agn_cfg)},
  2580. {IWL_PCI_DEVICE(0x0086, PCI_ANY_ID, iwl6050_3agn_cfg)},
  2581. {IWL_PCI_DEVICE(0x0087, PCI_ANY_ID, iwl6050_2agn_cfg)},
  2582. {IWL_PCI_DEVICE(0x0088, PCI_ANY_ID, iwl6050_3agn_cfg)},
  2583. {IWL_PCI_DEVICE(0x0089, PCI_ANY_ID, iwl6050_2agn_cfg)},
  2584. /* 1000 Series WiFi */
  2585. {IWL_PCI_DEVICE(0x0083, PCI_ANY_ID, iwl1000_bgn_cfg)},
  2586. {IWL_PCI_DEVICE(0x0084, PCI_ANY_ID, iwl1000_bgn_cfg)},
  2587. #endif /* CONFIG_IWL5000 */
  2588. {0}
  2589. };
  2590. MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
  2591. static struct pci_driver iwl_driver = {
  2592. .name = DRV_NAME,
  2593. .id_table = iwl_hw_card_ids,
  2594. .probe = iwl_pci_probe,
  2595. .remove = __devexit_p(iwl_pci_remove),
  2596. #ifdef CONFIG_PM
  2597. .suspend = iwl_pci_suspend,
  2598. .resume = iwl_pci_resume,
  2599. #endif
  2600. };
  2601. static int __init iwl_init(void)
  2602. {
  2603. int ret;
  2604. printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
  2605. printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
  2606. ret = iwlagn_rate_control_register();
  2607. if (ret) {
  2608. printk(KERN_ERR DRV_NAME
  2609. "Unable to register rate control algorithm: %d\n", ret);
  2610. return ret;
  2611. }
  2612. ret = pci_register_driver(&iwl_driver);
  2613. if (ret) {
  2614. printk(KERN_ERR DRV_NAME "Unable to initialize PCI module\n");
  2615. goto error_register;
  2616. }
  2617. return ret;
  2618. error_register:
  2619. iwlagn_rate_control_unregister();
  2620. return ret;
  2621. }
  2622. static void __exit iwl_exit(void)
  2623. {
  2624. pci_unregister_driver(&iwl_driver);
  2625. iwlagn_rate_control_unregister();
  2626. }
  2627. module_exit(iwl_exit);
  2628. module_init(iwl_init);
  2629. #ifdef CONFIG_IWLWIFI_DEBUG
  2630. module_param_named(debug50, iwl_debug_level, uint, 0444);
  2631. MODULE_PARM_DESC(debug50, "50XX debug output mask (deprecated)");
  2632. module_param_named(debug, iwl_debug_level, uint, 0644);
  2633. MODULE_PARM_DESC(debug, "debug output mask");
  2634. #endif