dmaengine.c 29 KB

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  1. /*
  2. * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
  3. *
  4. * This program is free software; you can redistribute it and/or modify it
  5. * under the terms of the GNU General Public License as published by the Free
  6. * Software Foundation; either version 2 of the License, or (at your option)
  7. * any later version.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program; if not, write to the Free Software Foundation, Inc., 59
  16. * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  17. *
  18. * The full GNU General Public License is included in this distribution in the
  19. * file called COPYING.
  20. */
  21. /*
  22. * This code implements the DMA subsystem. It provides a HW-neutral interface
  23. * for other kernel code to use asynchronous memory copy capabilities,
  24. * if present, and allows different HW DMA drivers to register as providing
  25. * this capability.
  26. *
  27. * Due to the fact we are accelerating what is already a relatively fast
  28. * operation, the code goes to great lengths to avoid additional overhead,
  29. * such as locking.
  30. *
  31. * LOCKING:
  32. *
  33. * The subsystem keeps a global list of dma_device structs it is protected by a
  34. * mutex, dma_list_mutex.
  35. *
  36. * A subsystem can get access to a channel by calling dmaengine_get() followed
  37. * by dma_find_channel(), or if it has need for an exclusive channel it can call
  38. * dma_request_channel(). Once a channel is allocated a reference is taken
  39. * against its corresponding driver to disable removal.
  40. *
  41. * Each device has a channels list, which runs unlocked but is never modified
  42. * once the device is registered, it's just setup by the driver.
  43. *
  44. * See Documentation/dmaengine.txt for more details
  45. */
  46. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  47. #include <linux/dma-mapping.h>
  48. #include <linux/init.h>
  49. #include <linux/module.h>
  50. #include <linux/mm.h>
  51. #include <linux/device.h>
  52. #include <linux/dmaengine.h>
  53. #include <linux/hardirq.h>
  54. #include <linux/spinlock.h>
  55. #include <linux/percpu.h>
  56. #include <linux/rcupdate.h>
  57. #include <linux/mutex.h>
  58. #include <linux/jiffies.h>
  59. #include <linux/rculist.h>
  60. #include <linux/idr.h>
  61. #include <linux/slab.h>
  62. #include <linux/of_dma.h>
  63. static DEFINE_MUTEX(dma_list_mutex);
  64. static DEFINE_IDR(dma_idr);
  65. static LIST_HEAD(dma_device_list);
  66. static long dmaengine_ref_count;
  67. /* --- sysfs implementation --- */
  68. /**
  69. * dev_to_dma_chan - convert a device pointer to the its sysfs container object
  70. * @dev - device node
  71. *
  72. * Must be called under dma_list_mutex
  73. */
  74. static struct dma_chan *dev_to_dma_chan(struct device *dev)
  75. {
  76. struct dma_chan_dev *chan_dev;
  77. chan_dev = container_of(dev, typeof(*chan_dev), device);
  78. return chan_dev->chan;
  79. }
  80. static ssize_t show_memcpy_count(struct device *dev, struct device_attribute *attr, char *buf)
  81. {
  82. struct dma_chan *chan;
  83. unsigned long count = 0;
  84. int i;
  85. int err;
  86. mutex_lock(&dma_list_mutex);
  87. chan = dev_to_dma_chan(dev);
  88. if (chan) {
  89. for_each_possible_cpu(i)
  90. count += per_cpu_ptr(chan->local, i)->memcpy_count;
  91. err = sprintf(buf, "%lu\n", count);
  92. } else
  93. err = -ENODEV;
  94. mutex_unlock(&dma_list_mutex);
  95. return err;
  96. }
  97. static ssize_t show_bytes_transferred(struct device *dev, struct device_attribute *attr,
  98. char *buf)
  99. {
  100. struct dma_chan *chan;
  101. unsigned long count = 0;
  102. int i;
  103. int err;
  104. mutex_lock(&dma_list_mutex);
  105. chan = dev_to_dma_chan(dev);
  106. if (chan) {
  107. for_each_possible_cpu(i)
  108. count += per_cpu_ptr(chan->local, i)->bytes_transferred;
  109. err = sprintf(buf, "%lu\n", count);
  110. } else
  111. err = -ENODEV;
  112. mutex_unlock(&dma_list_mutex);
  113. return err;
  114. }
  115. static ssize_t show_in_use(struct device *dev, struct device_attribute *attr, char *buf)
  116. {
  117. struct dma_chan *chan;
  118. int err;
  119. mutex_lock(&dma_list_mutex);
  120. chan = dev_to_dma_chan(dev);
  121. if (chan)
  122. err = sprintf(buf, "%d\n", chan->client_count);
  123. else
  124. err = -ENODEV;
  125. mutex_unlock(&dma_list_mutex);
  126. return err;
  127. }
  128. static struct device_attribute dma_attrs[] = {
  129. __ATTR(memcpy_count, S_IRUGO, show_memcpy_count, NULL),
  130. __ATTR(bytes_transferred, S_IRUGO, show_bytes_transferred, NULL),
  131. __ATTR(in_use, S_IRUGO, show_in_use, NULL),
  132. __ATTR_NULL
  133. };
  134. static void chan_dev_release(struct device *dev)
  135. {
  136. struct dma_chan_dev *chan_dev;
  137. chan_dev = container_of(dev, typeof(*chan_dev), device);
  138. if (atomic_dec_and_test(chan_dev->idr_ref)) {
  139. mutex_lock(&dma_list_mutex);
  140. idr_remove(&dma_idr, chan_dev->dev_id);
  141. mutex_unlock(&dma_list_mutex);
  142. kfree(chan_dev->idr_ref);
  143. }
  144. kfree(chan_dev);
  145. }
  146. static struct class dma_devclass = {
  147. .name = "dma",
  148. .dev_attrs = dma_attrs,
  149. .dev_release = chan_dev_release,
  150. };
  151. /* --- client and device registration --- */
  152. #define dma_device_satisfies_mask(device, mask) \
  153. __dma_device_satisfies_mask((device), &(mask))
  154. static int
  155. __dma_device_satisfies_mask(struct dma_device *device,
  156. const dma_cap_mask_t *want)
  157. {
  158. dma_cap_mask_t has;
  159. bitmap_and(has.bits, want->bits, device->cap_mask.bits,
  160. DMA_TX_TYPE_END);
  161. return bitmap_equal(want->bits, has.bits, DMA_TX_TYPE_END);
  162. }
  163. static struct module *dma_chan_to_owner(struct dma_chan *chan)
  164. {
  165. return chan->device->dev->driver->owner;
  166. }
  167. /**
  168. * balance_ref_count - catch up the channel reference count
  169. * @chan - channel to balance ->client_count versus dmaengine_ref_count
  170. *
  171. * balance_ref_count must be called under dma_list_mutex
  172. */
  173. static void balance_ref_count(struct dma_chan *chan)
  174. {
  175. struct module *owner = dma_chan_to_owner(chan);
  176. while (chan->client_count < dmaengine_ref_count) {
  177. __module_get(owner);
  178. chan->client_count++;
  179. }
  180. }
  181. /**
  182. * dma_chan_get - try to grab a dma channel's parent driver module
  183. * @chan - channel to grab
  184. *
  185. * Must be called under dma_list_mutex
  186. */
  187. static int dma_chan_get(struct dma_chan *chan)
  188. {
  189. int err = -ENODEV;
  190. struct module *owner = dma_chan_to_owner(chan);
  191. if (chan->client_count) {
  192. __module_get(owner);
  193. err = 0;
  194. } else if (try_module_get(owner))
  195. err = 0;
  196. if (err == 0)
  197. chan->client_count++;
  198. /* allocate upon first client reference */
  199. if (chan->client_count == 1 && err == 0) {
  200. int desc_cnt = chan->device->device_alloc_chan_resources(chan);
  201. if (desc_cnt < 0) {
  202. err = desc_cnt;
  203. chan->client_count = 0;
  204. module_put(owner);
  205. } else if (!dma_has_cap(DMA_PRIVATE, chan->device->cap_mask))
  206. balance_ref_count(chan);
  207. }
  208. return err;
  209. }
  210. /**
  211. * dma_chan_put - drop a reference to a dma channel's parent driver module
  212. * @chan - channel to release
  213. *
  214. * Must be called under dma_list_mutex
  215. */
  216. static void dma_chan_put(struct dma_chan *chan)
  217. {
  218. if (!chan->client_count)
  219. return; /* this channel failed alloc_chan_resources */
  220. chan->client_count--;
  221. module_put(dma_chan_to_owner(chan));
  222. if (chan->client_count == 0)
  223. chan->device->device_free_chan_resources(chan);
  224. }
  225. enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie)
  226. {
  227. enum dma_status status;
  228. unsigned long dma_sync_wait_timeout = jiffies + msecs_to_jiffies(5000);
  229. dma_async_issue_pending(chan);
  230. do {
  231. status = dma_async_is_tx_complete(chan, cookie, NULL, NULL);
  232. if (time_after_eq(jiffies, dma_sync_wait_timeout)) {
  233. pr_err("%s: timeout!\n", __func__);
  234. return DMA_ERROR;
  235. }
  236. if (status != DMA_IN_PROGRESS)
  237. break;
  238. cpu_relax();
  239. } while (1);
  240. return status;
  241. }
  242. EXPORT_SYMBOL(dma_sync_wait);
  243. /**
  244. * dma_cap_mask_all - enable iteration over all operation types
  245. */
  246. static dma_cap_mask_t dma_cap_mask_all;
  247. /**
  248. * dma_chan_tbl_ent - tracks channel allocations per core/operation
  249. * @chan - associated channel for this entry
  250. */
  251. struct dma_chan_tbl_ent {
  252. struct dma_chan *chan;
  253. };
  254. /**
  255. * channel_table - percpu lookup table for memory-to-memory offload providers
  256. */
  257. static struct dma_chan_tbl_ent __percpu *channel_table[DMA_TX_TYPE_END];
  258. static int __init dma_channel_table_init(void)
  259. {
  260. enum dma_transaction_type cap;
  261. int err = 0;
  262. bitmap_fill(dma_cap_mask_all.bits, DMA_TX_TYPE_END);
  263. /* 'interrupt', 'private', and 'slave' are channel capabilities,
  264. * but are not associated with an operation so they do not need
  265. * an entry in the channel_table
  266. */
  267. clear_bit(DMA_INTERRUPT, dma_cap_mask_all.bits);
  268. clear_bit(DMA_PRIVATE, dma_cap_mask_all.bits);
  269. clear_bit(DMA_SLAVE, dma_cap_mask_all.bits);
  270. for_each_dma_cap_mask(cap, dma_cap_mask_all) {
  271. channel_table[cap] = alloc_percpu(struct dma_chan_tbl_ent);
  272. if (!channel_table[cap]) {
  273. err = -ENOMEM;
  274. break;
  275. }
  276. }
  277. if (err) {
  278. pr_err("initialization failure\n");
  279. for_each_dma_cap_mask(cap, dma_cap_mask_all)
  280. if (channel_table[cap])
  281. free_percpu(channel_table[cap]);
  282. }
  283. return err;
  284. }
  285. arch_initcall(dma_channel_table_init);
  286. /**
  287. * dma_find_channel - find a channel to carry out the operation
  288. * @tx_type: transaction type
  289. */
  290. struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type)
  291. {
  292. return this_cpu_read(channel_table[tx_type]->chan);
  293. }
  294. EXPORT_SYMBOL(dma_find_channel);
  295. /*
  296. * net_dma_find_channel - find a channel for net_dma
  297. * net_dma has alignment requirements
  298. */
  299. struct dma_chan *net_dma_find_channel(void)
  300. {
  301. struct dma_chan *chan = dma_find_channel(DMA_MEMCPY);
  302. if (chan && !is_dma_copy_aligned(chan->device, 1, 1, 1))
  303. return NULL;
  304. return chan;
  305. }
  306. EXPORT_SYMBOL(net_dma_find_channel);
  307. /**
  308. * dma_issue_pending_all - flush all pending operations across all channels
  309. */
  310. void dma_issue_pending_all(void)
  311. {
  312. struct dma_device *device;
  313. struct dma_chan *chan;
  314. rcu_read_lock();
  315. list_for_each_entry_rcu(device, &dma_device_list, global_node) {
  316. if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
  317. continue;
  318. list_for_each_entry(chan, &device->channels, device_node)
  319. if (chan->client_count)
  320. device->device_issue_pending(chan);
  321. }
  322. rcu_read_unlock();
  323. }
  324. EXPORT_SYMBOL(dma_issue_pending_all);
  325. /**
  326. * nth_chan - returns the nth channel of the given capability
  327. * @cap: capability to match
  328. * @n: nth channel desired
  329. *
  330. * Defaults to returning the channel with the desired capability and the
  331. * lowest reference count when 'n' cannot be satisfied. Must be called
  332. * under dma_list_mutex.
  333. */
  334. static struct dma_chan *nth_chan(enum dma_transaction_type cap, int n)
  335. {
  336. struct dma_device *device;
  337. struct dma_chan *chan;
  338. struct dma_chan *ret = NULL;
  339. struct dma_chan *min = NULL;
  340. list_for_each_entry(device, &dma_device_list, global_node) {
  341. if (!dma_has_cap(cap, device->cap_mask) ||
  342. dma_has_cap(DMA_PRIVATE, device->cap_mask))
  343. continue;
  344. list_for_each_entry(chan, &device->channels, device_node) {
  345. if (!chan->client_count)
  346. continue;
  347. if (!min)
  348. min = chan;
  349. else if (chan->table_count < min->table_count)
  350. min = chan;
  351. if (n-- == 0) {
  352. ret = chan;
  353. break; /* done */
  354. }
  355. }
  356. if (ret)
  357. break; /* done */
  358. }
  359. if (!ret)
  360. ret = min;
  361. if (ret)
  362. ret->table_count++;
  363. return ret;
  364. }
  365. /**
  366. * dma_channel_rebalance - redistribute the available channels
  367. *
  368. * Optimize for cpu isolation (each cpu gets a dedicated channel for an
  369. * operation type) in the SMP case, and operation isolation (avoid
  370. * multi-tasking channels) in the non-SMP case. Must be called under
  371. * dma_list_mutex.
  372. */
  373. static void dma_channel_rebalance(void)
  374. {
  375. struct dma_chan *chan;
  376. struct dma_device *device;
  377. int cpu;
  378. int cap;
  379. int n;
  380. /* undo the last distribution */
  381. for_each_dma_cap_mask(cap, dma_cap_mask_all)
  382. for_each_possible_cpu(cpu)
  383. per_cpu_ptr(channel_table[cap], cpu)->chan = NULL;
  384. list_for_each_entry(device, &dma_device_list, global_node) {
  385. if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
  386. continue;
  387. list_for_each_entry(chan, &device->channels, device_node)
  388. chan->table_count = 0;
  389. }
  390. /* don't populate the channel_table if no clients are available */
  391. if (!dmaengine_ref_count)
  392. return;
  393. /* redistribute available channels */
  394. n = 0;
  395. for_each_dma_cap_mask(cap, dma_cap_mask_all)
  396. for_each_online_cpu(cpu) {
  397. if (num_possible_cpus() > 1)
  398. chan = nth_chan(cap, n++);
  399. else
  400. chan = nth_chan(cap, -1);
  401. per_cpu_ptr(channel_table[cap], cpu)->chan = chan;
  402. }
  403. }
  404. static struct dma_chan *private_candidate(const dma_cap_mask_t *mask,
  405. struct dma_device *dev,
  406. dma_filter_fn fn, void *fn_param)
  407. {
  408. struct dma_chan *chan;
  409. if (!__dma_device_satisfies_mask(dev, mask)) {
  410. pr_debug("%s: wrong capabilities\n", __func__);
  411. return NULL;
  412. }
  413. /* devices with multiple channels need special handling as we need to
  414. * ensure that all channels are either private or public.
  415. */
  416. if (dev->chancnt > 1 && !dma_has_cap(DMA_PRIVATE, dev->cap_mask))
  417. list_for_each_entry(chan, &dev->channels, device_node) {
  418. /* some channels are already publicly allocated */
  419. if (chan->client_count)
  420. return NULL;
  421. }
  422. list_for_each_entry(chan, &dev->channels, device_node) {
  423. if (chan->client_count) {
  424. pr_debug("%s: %s busy\n",
  425. __func__, dma_chan_name(chan));
  426. continue;
  427. }
  428. if (fn && !fn(chan, fn_param)) {
  429. pr_debug("%s: %s filter said false\n",
  430. __func__, dma_chan_name(chan));
  431. continue;
  432. }
  433. return chan;
  434. }
  435. return NULL;
  436. }
  437. /**
  438. * dma_request_channel - try to allocate an exclusive channel
  439. * @mask: capabilities that the channel must satisfy
  440. * @fn: optional callback to disposition available channels
  441. * @fn_param: opaque parameter to pass to dma_filter_fn
  442. */
  443. struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask,
  444. dma_filter_fn fn, void *fn_param)
  445. {
  446. struct dma_device *device, *_d;
  447. struct dma_chan *chan = NULL;
  448. int err;
  449. /* Find a channel */
  450. mutex_lock(&dma_list_mutex);
  451. list_for_each_entry_safe(device, _d, &dma_device_list, global_node) {
  452. chan = private_candidate(mask, device, fn, fn_param);
  453. if (chan) {
  454. /* Found a suitable channel, try to grab, prep, and
  455. * return it. We first set DMA_PRIVATE to disable
  456. * balance_ref_count as this channel will not be
  457. * published in the general-purpose allocator
  458. */
  459. dma_cap_set(DMA_PRIVATE, device->cap_mask);
  460. device->privatecnt++;
  461. err = dma_chan_get(chan);
  462. if (err == -ENODEV) {
  463. pr_debug("%s: %s module removed\n",
  464. __func__, dma_chan_name(chan));
  465. list_del_rcu(&device->global_node);
  466. } else if (err)
  467. pr_debug("%s: failed to get %s: (%d)\n",
  468. __func__, dma_chan_name(chan), err);
  469. else
  470. break;
  471. if (--device->privatecnt == 0)
  472. dma_cap_clear(DMA_PRIVATE, device->cap_mask);
  473. chan = NULL;
  474. }
  475. }
  476. mutex_unlock(&dma_list_mutex);
  477. pr_debug("%s: %s (%s)\n",
  478. __func__,
  479. chan ? "success" : "fail",
  480. chan ? dma_chan_name(chan) : NULL);
  481. return chan;
  482. }
  483. EXPORT_SYMBOL_GPL(__dma_request_channel);
  484. /**
  485. * dma_request_slave_channel - try to allocate an exclusive slave channel
  486. * @dev: pointer to client device structure
  487. * @name: slave channel name
  488. */
  489. struct dma_chan *dma_request_slave_channel(struct device *dev, char *name)
  490. {
  491. /* If device-tree is present get slave info from here */
  492. if (dev->of_node)
  493. return of_dma_request_slave_channel(dev->of_node, name);
  494. return NULL;
  495. }
  496. EXPORT_SYMBOL_GPL(dma_request_slave_channel);
  497. void dma_release_channel(struct dma_chan *chan)
  498. {
  499. mutex_lock(&dma_list_mutex);
  500. WARN_ONCE(chan->client_count != 1,
  501. "chan reference count %d != 1\n", chan->client_count);
  502. dma_chan_put(chan);
  503. /* drop PRIVATE cap enabled by __dma_request_channel() */
  504. if (--chan->device->privatecnt == 0)
  505. dma_cap_clear(DMA_PRIVATE, chan->device->cap_mask);
  506. mutex_unlock(&dma_list_mutex);
  507. }
  508. EXPORT_SYMBOL_GPL(dma_release_channel);
  509. /**
  510. * dmaengine_get - register interest in dma_channels
  511. */
  512. void dmaengine_get(void)
  513. {
  514. struct dma_device *device, *_d;
  515. struct dma_chan *chan;
  516. int err;
  517. mutex_lock(&dma_list_mutex);
  518. dmaengine_ref_count++;
  519. /* try to grab channels */
  520. list_for_each_entry_safe(device, _d, &dma_device_list, global_node) {
  521. if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
  522. continue;
  523. list_for_each_entry(chan, &device->channels, device_node) {
  524. err = dma_chan_get(chan);
  525. if (err == -ENODEV) {
  526. /* module removed before we could use it */
  527. list_del_rcu(&device->global_node);
  528. break;
  529. } else if (err)
  530. pr_debug("%s: failed to get %s: (%d)\n",
  531. __func__, dma_chan_name(chan), err);
  532. }
  533. }
  534. /* if this is the first reference and there were channels
  535. * waiting we need to rebalance to get those channels
  536. * incorporated into the channel table
  537. */
  538. if (dmaengine_ref_count == 1)
  539. dma_channel_rebalance();
  540. mutex_unlock(&dma_list_mutex);
  541. }
  542. EXPORT_SYMBOL(dmaengine_get);
  543. /**
  544. * dmaengine_put - let dma drivers be removed when ref_count == 0
  545. */
  546. void dmaengine_put(void)
  547. {
  548. struct dma_device *device;
  549. struct dma_chan *chan;
  550. mutex_lock(&dma_list_mutex);
  551. dmaengine_ref_count--;
  552. BUG_ON(dmaengine_ref_count < 0);
  553. /* drop channel references */
  554. list_for_each_entry(device, &dma_device_list, global_node) {
  555. if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
  556. continue;
  557. list_for_each_entry(chan, &device->channels, device_node)
  558. dma_chan_put(chan);
  559. }
  560. mutex_unlock(&dma_list_mutex);
  561. }
  562. EXPORT_SYMBOL(dmaengine_put);
  563. static bool device_has_all_tx_types(struct dma_device *device)
  564. {
  565. /* A device that satisfies this test has channels that will never cause
  566. * an async_tx channel switch event as all possible operation types can
  567. * be handled.
  568. */
  569. #ifdef CONFIG_ASYNC_TX_DMA
  570. if (!dma_has_cap(DMA_INTERRUPT, device->cap_mask))
  571. return false;
  572. #endif
  573. #if defined(CONFIG_ASYNC_MEMCPY) || defined(CONFIG_ASYNC_MEMCPY_MODULE)
  574. if (!dma_has_cap(DMA_MEMCPY, device->cap_mask))
  575. return false;
  576. #endif
  577. #if defined(CONFIG_ASYNC_MEMSET) || defined(CONFIG_ASYNC_MEMSET_MODULE)
  578. if (!dma_has_cap(DMA_MEMSET, device->cap_mask))
  579. return false;
  580. #endif
  581. #if defined(CONFIG_ASYNC_XOR) || defined(CONFIG_ASYNC_XOR_MODULE)
  582. if (!dma_has_cap(DMA_XOR, device->cap_mask))
  583. return false;
  584. #ifndef CONFIG_ASYNC_TX_DISABLE_XOR_VAL_DMA
  585. if (!dma_has_cap(DMA_XOR_VAL, device->cap_mask))
  586. return false;
  587. #endif
  588. #endif
  589. #if defined(CONFIG_ASYNC_PQ) || defined(CONFIG_ASYNC_PQ_MODULE)
  590. if (!dma_has_cap(DMA_PQ, device->cap_mask))
  591. return false;
  592. #ifndef CONFIG_ASYNC_TX_DISABLE_PQ_VAL_DMA
  593. if (!dma_has_cap(DMA_PQ_VAL, device->cap_mask))
  594. return false;
  595. #endif
  596. #endif
  597. return true;
  598. }
  599. static int get_dma_id(struct dma_device *device)
  600. {
  601. int rc;
  602. mutex_lock(&dma_list_mutex);
  603. rc = idr_alloc(&dma_idr, NULL, 0, 0, GFP_KERNEL);
  604. if (rc >= 0)
  605. device->dev_id = rc;
  606. mutex_unlock(&dma_list_mutex);
  607. return rc < 0 ? rc : 0;
  608. }
  609. /**
  610. * dma_async_device_register - registers DMA devices found
  611. * @device: &dma_device
  612. */
  613. int dma_async_device_register(struct dma_device *device)
  614. {
  615. int chancnt = 0, rc;
  616. struct dma_chan* chan;
  617. atomic_t *idr_ref;
  618. if (!device)
  619. return -ENODEV;
  620. /* validate device routines */
  621. BUG_ON(dma_has_cap(DMA_MEMCPY, device->cap_mask) &&
  622. !device->device_prep_dma_memcpy);
  623. BUG_ON(dma_has_cap(DMA_XOR, device->cap_mask) &&
  624. !device->device_prep_dma_xor);
  625. BUG_ON(dma_has_cap(DMA_XOR_VAL, device->cap_mask) &&
  626. !device->device_prep_dma_xor_val);
  627. BUG_ON(dma_has_cap(DMA_PQ, device->cap_mask) &&
  628. !device->device_prep_dma_pq);
  629. BUG_ON(dma_has_cap(DMA_PQ_VAL, device->cap_mask) &&
  630. !device->device_prep_dma_pq_val);
  631. BUG_ON(dma_has_cap(DMA_MEMSET, device->cap_mask) &&
  632. !device->device_prep_dma_memset);
  633. BUG_ON(dma_has_cap(DMA_INTERRUPT, device->cap_mask) &&
  634. !device->device_prep_dma_interrupt);
  635. BUG_ON(dma_has_cap(DMA_SG, device->cap_mask) &&
  636. !device->device_prep_dma_sg);
  637. BUG_ON(dma_has_cap(DMA_CYCLIC, device->cap_mask) &&
  638. !device->device_prep_dma_cyclic);
  639. BUG_ON(dma_has_cap(DMA_SLAVE, device->cap_mask) &&
  640. !device->device_control);
  641. BUG_ON(dma_has_cap(DMA_INTERLEAVE, device->cap_mask) &&
  642. !device->device_prep_interleaved_dma);
  643. BUG_ON(!device->device_alloc_chan_resources);
  644. BUG_ON(!device->device_free_chan_resources);
  645. BUG_ON(!device->device_tx_status);
  646. BUG_ON(!device->device_issue_pending);
  647. BUG_ON(!device->dev);
  648. /* note: this only matters in the
  649. * CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=n case
  650. */
  651. if (device_has_all_tx_types(device))
  652. dma_cap_set(DMA_ASYNC_TX, device->cap_mask);
  653. idr_ref = kmalloc(sizeof(*idr_ref), GFP_KERNEL);
  654. if (!idr_ref)
  655. return -ENOMEM;
  656. rc = get_dma_id(device);
  657. if (rc != 0) {
  658. kfree(idr_ref);
  659. return rc;
  660. }
  661. atomic_set(idr_ref, 0);
  662. /* represent channels in sysfs. Probably want devs too */
  663. list_for_each_entry(chan, &device->channels, device_node) {
  664. rc = -ENOMEM;
  665. chan->local = alloc_percpu(typeof(*chan->local));
  666. if (chan->local == NULL)
  667. goto err_out;
  668. chan->dev = kzalloc(sizeof(*chan->dev), GFP_KERNEL);
  669. if (chan->dev == NULL) {
  670. free_percpu(chan->local);
  671. chan->local = NULL;
  672. goto err_out;
  673. }
  674. chan->chan_id = chancnt++;
  675. chan->dev->device.class = &dma_devclass;
  676. chan->dev->device.parent = device->dev;
  677. chan->dev->chan = chan;
  678. chan->dev->idr_ref = idr_ref;
  679. chan->dev->dev_id = device->dev_id;
  680. atomic_inc(idr_ref);
  681. dev_set_name(&chan->dev->device, "dma%dchan%d",
  682. device->dev_id, chan->chan_id);
  683. rc = device_register(&chan->dev->device);
  684. if (rc) {
  685. free_percpu(chan->local);
  686. chan->local = NULL;
  687. kfree(chan->dev);
  688. atomic_dec(idr_ref);
  689. goto err_out;
  690. }
  691. chan->client_count = 0;
  692. }
  693. device->chancnt = chancnt;
  694. mutex_lock(&dma_list_mutex);
  695. /* take references on public channels */
  696. if (dmaengine_ref_count && !dma_has_cap(DMA_PRIVATE, device->cap_mask))
  697. list_for_each_entry(chan, &device->channels, device_node) {
  698. /* if clients are already waiting for channels we need
  699. * to take references on their behalf
  700. */
  701. if (dma_chan_get(chan) == -ENODEV) {
  702. /* note we can only get here for the first
  703. * channel as the remaining channels are
  704. * guaranteed to get a reference
  705. */
  706. rc = -ENODEV;
  707. mutex_unlock(&dma_list_mutex);
  708. goto err_out;
  709. }
  710. }
  711. list_add_tail_rcu(&device->global_node, &dma_device_list);
  712. if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
  713. device->privatecnt++; /* Always private */
  714. dma_channel_rebalance();
  715. mutex_unlock(&dma_list_mutex);
  716. return 0;
  717. err_out:
  718. /* if we never registered a channel just release the idr */
  719. if (atomic_read(idr_ref) == 0) {
  720. mutex_lock(&dma_list_mutex);
  721. idr_remove(&dma_idr, device->dev_id);
  722. mutex_unlock(&dma_list_mutex);
  723. kfree(idr_ref);
  724. return rc;
  725. }
  726. list_for_each_entry(chan, &device->channels, device_node) {
  727. if (chan->local == NULL)
  728. continue;
  729. mutex_lock(&dma_list_mutex);
  730. chan->dev->chan = NULL;
  731. mutex_unlock(&dma_list_mutex);
  732. device_unregister(&chan->dev->device);
  733. free_percpu(chan->local);
  734. }
  735. return rc;
  736. }
  737. EXPORT_SYMBOL(dma_async_device_register);
  738. /**
  739. * dma_async_device_unregister - unregister a DMA device
  740. * @device: &dma_device
  741. *
  742. * This routine is called by dma driver exit routines, dmaengine holds module
  743. * references to prevent it being called while channels are in use.
  744. */
  745. void dma_async_device_unregister(struct dma_device *device)
  746. {
  747. struct dma_chan *chan;
  748. mutex_lock(&dma_list_mutex);
  749. list_del_rcu(&device->global_node);
  750. dma_channel_rebalance();
  751. mutex_unlock(&dma_list_mutex);
  752. list_for_each_entry(chan, &device->channels, device_node) {
  753. WARN_ONCE(chan->client_count,
  754. "%s called while %d clients hold a reference\n",
  755. __func__, chan->client_count);
  756. mutex_lock(&dma_list_mutex);
  757. chan->dev->chan = NULL;
  758. mutex_unlock(&dma_list_mutex);
  759. device_unregister(&chan->dev->device);
  760. free_percpu(chan->local);
  761. }
  762. }
  763. EXPORT_SYMBOL(dma_async_device_unregister);
  764. /**
  765. * dma_async_memcpy_buf_to_buf - offloaded copy between virtual addresses
  766. * @chan: DMA channel to offload copy to
  767. * @dest: destination address (virtual)
  768. * @src: source address (virtual)
  769. * @len: length
  770. *
  771. * Both @dest and @src must be mappable to a bus address according to the
  772. * DMA mapping API rules for streaming mappings.
  773. * Both @dest and @src must stay memory resident (kernel memory or locked
  774. * user space pages).
  775. */
  776. dma_cookie_t
  777. dma_async_memcpy_buf_to_buf(struct dma_chan *chan, void *dest,
  778. void *src, size_t len)
  779. {
  780. struct dma_device *dev = chan->device;
  781. struct dma_async_tx_descriptor *tx;
  782. dma_addr_t dma_dest, dma_src;
  783. dma_cookie_t cookie;
  784. unsigned long flags;
  785. dma_src = dma_map_single(dev->dev, src, len, DMA_TO_DEVICE);
  786. dma_dest = dma_map_single(dev->dev, dest, len, DMA_FROM_DEVICE);
  787. flags = DMA_CTRL_ACK |
  788. DMA_COMPL_SRC_UNMAP_SINGLE |
  789. DMA_COMPL_DEST_UNMAP_SINGLE;
  790. tx = dev->device_prep_dma_memcpy(chan, dma_dest, dma_src, len, flags);
  791. if (!tx) {
  792. dma_unmap_single(dev->dev, dma_src, len, DMA_TO_DEVICE);
  793. dma_unmap_single(dev->dev, dma_dest, len, DMA_FROM_DEVICE);
  794. return -ENOMEM;
  795. }
  796. tx->callback = NULL;
  797. cookie = tx->tx_submit(tx);
  798. preempt_disable();
  799. __this_cpu_add(chan->local->bytes_transferred, len);
  800. __this_cpu_inc(chan->local->memcpy_count);
  801. preempt_enable();
  802. return cookie;
  803. }
  804. EXPORT_SYMBOL(dma_async_memcpy_buf_to_buf);
  805. /**
  806. * dma_async_memcpy_buf_to_pg - offloaded copy from address to page
  807. * @chan: DMA channel to offload copy to
  808. * @page: destination page
  809. * @offset: offset in page to copy to
  810. * @kdata: source address (virtual)
  811. * @len: length
  812. *
  813. * Both @page/@offset and @kdata must be mappable to a bus address according
  814. * to the DMA mapping API rules for streaming mappings.
  815. * Both @page/@offset and @kdata must stay memory resident (kernel memory or
  816. * locked user space pages)
  817. */
  818. dma_cookie_t
  819. dma_async_memcpy_buf_to_pg(struct dma_chan *chan, struct page *page,
  820. unsigned int offset, void *kdata, size_t len)
  821. {
  822. struct dma_device *dev = chan->device;
  823. struct dma_async_tx_descriptor *tx;
  824. dma_addr_t dma_dest, dma_src;
  825. dma_cookie_t cookie;
  826. unsigned long flags;
  827. dma_src = dma_map_single(dev->dev, kdata, len, DMA_TO_DEVICE);
  828. dma_dest = dma_map_page(dev->dev, page, offset, len, DMA_FROM_DEVICE);
  829. flags = DMA_CTRL_ACK | DMA_COMPL_SRC_UNMAP_SINGLE;
  830. tx = dev->device_prep_dma_memcpy(chan, dma_dest, dma_src, len, flags);
  831. if (!tx) {
  832. dma_unmap_single(dev->dev, dma_src, len, DMA_TO_DEVICE);
  833. dma_unmap_page(dev->dev, dma_dest, len, DMA_FROM_DEVICE);
  834. return -ENOMEM;
  835. }
  836. tx->callback = NULL;
  837. cookie = tx->tx_submit(tx);
  838. preempt_disable();
  839. __this_cpu_add(chan->local->bytes_transferred, len);
  840. __this_cpu_inc(chan->local->memcpy_count);
  841. preempt_enable();
  842. return cookie;
  843. }
  844. EXPORT_SYMBOL(dma_async_memcpy_buf_to_pg);
  845. /**
  846. * dma_async_memcpy_pg_to_pg - offloaded copy from page to page
  847. * @chan: DMA channel to offload copy to
  848. * @dest_pg: destination page
  849. * @dest_off: offset in page to copy to
  850. * @src_pg: source page
  851. * @src_off: offset in page to copy from
  852. * @len: length
  853. *
  854. * Both @dest_page/@dest_off and @src_page/@src_off must be mappable to a bus
  855. * address according to the DMA mapping API rules for streaming mappings.
  856. * Both @dest_page/@dest_off and @src_page/@src_off must stay memory resident
  857. * (kernel memory or locked user space pages).
  858. */
  859. dma_cookie_t
  860. dma_async_memcpy_pg_to_pg(struct dma_chan *chan, struct page *dest_pg,
  861. unsigned int dest_off, struct page *src_pg, unsigned int src_off,
  862. size_t len)
  863. {
  864. struct dma_device *dev = chan->device;
  865. struct dma_async_tx_descriptor *tx;
  866. dma_addr_t dma_dest, dma_src;
  867. dma_cookie_t cookie;
  868. unsigned long flags;
  869. dma_src = dma_map_page(dev->dev, src_pg, src_off, len, DMA_TO_DEVICE);
  870. dma_dest = dma_map_page(dev->dev, dest_pg, dest_off, len,
  871. DMA_FROM_DEVICE);
  872. flags = DMA_CTRL_ACK;
  873. tx = dev->device_prep_dma_memcpy(chan, dma_dest, dma_src, len, flags);
  874. if (!tx) {
  875. dma_unmap_page(dev->dev, dma_src, len, DMA_TO_DEVICE);
  876. dma_unmap_page(dev->dev, dma_dest, len, DMA_FROM_DEVICE);
  877. return -ENOMEM;
  878. }
  879. tx->callback = NULL;
  880. cookie = tx->tx_submit(tx);
  881. preempt_disable();
  882. __this_cpu_add(chan->local->bytes_transferred, len);
  883. __this_cpu_inc(chan->local->memcpy_count);
  884. preempt_enable();
  885. return cookie;
  886. }
  887. EXPORT_SYMBOL(dma_async_memcpy_pg_to_pg);
  888. void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx,
  889. struct dma_chan *chan)
  890. {
  891. tx->chan = chan;
  892. #ifdef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
  893. spin_lock_init(&tx->lock);
  894. #endif
  895. }
  896. EXPORT_SYMBOL(dma_async_tx_descriptor_init);
  897. /* dma_wait_for_async_tx - spin wait for a transaction to complete
  898. * @tx: in-flight transaction to wait on
  899. */
  900. enum dma_status
  901. dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx)
  902. {
  903. unsigned long dma_sync_wait_timeout = jiffies + msecs_to_jiffies(5000);
  904. if (!tx)
  905. return DMA_SUCCESS;
  906. while (tx->cookie == -EBUSY) {
  907. if (time_after_eq(jiffies, dma_sync_wait_timeout)) {
  908. pr_err("%s timeout waiting for descriptor submission\n",
  909. __func__);
  910. return DMA_ERROR;
  911. }
  912. cpu_relax();
  913. }
  914. return dma_sync_wait(tx->chan, tx->cookie);
  915. }
  916. EXPORT_SYMBOL_GPL(dma_wait_for_async_tx);
  917. /* dma_run_dependencies - helper routine for dma drivers to process
  918. * (start) dependent operations on their target channel
  919. * @tx: transaction with dependencies
  920. */
  921. void dma_run_dependencies(struct dma_async_tx_descriptor *tx)
  922. {
  923. struct dma_async_tx_descriptor *dep = txd_next(tx);
  924. struct dma_async_tx_descriptor *dep_next;
  925. struct dma_chan *chan;
  926. if (!dep)
  927. return;
  928. /* we'll submit tx->next now, so clear the link */
  929. txd_clear_next(tx);
  930. chan = dep->chan;
  931. /* keep submitting up until a channel switch is detected
  932. * in that case we will be called again as a result of
  933. * processing the interrupt from async_tx_channel_switch
  934. */
  935. for (; dep; dep = dep_next) {
  936. txd_lock(dep);
  937. txd_clear_parent(dep);
  938. dep_next = txd_next(dep);
  939. if (dep_next && dep_next->chan == chan)
  940. txd_clear_next(dep); /* ->next will be submitted */
  941. else
  942. dep_next = NULL; /* submit current dep and terminate */
  943. txd_unlock(dep);
  944. dep->tx_submit(dep);
  945. }
  946. chan->device->device_issue_pending(chan);
  947. }
  948. EXPORT_SYMBOL_GPL(dma_run_dependencies);
  949. static int __init dma_bus_init(void)
  950. {
  951. return class_register(&dma_devclass);
  952. }
  953. arch_initcall(dma_bus_init);