tilcdc_drv.c 15 KB

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  1. /*
  2. * Copyright (C) 2012 Texas Instruments
  3. * Author: Rob Clark <robdclark@gmail.com>
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of the GNU General Public License version 2 as published by
  7. * the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program. If not, see <http://www.gnu.org/licenses/>.
  16. */
  17. /* LCDC DRM driver, based on da8xx-fb */
  18. #include "tilcdc_drv.h"
  19. #include "tilcdc_regs.h"
  20. #include "tilcdc_tfp410.h"
  21. #include "tilcdc_slave.h"
  22. #include "tilcdc_panel.h"
  23. #include "drm_fb_helper.h"
  24. static LIST_HEAD(module_list);
  25. void tilcdc_module_init(struct tilcdc_module *mod, const char *name,
  26. const struct tilcdc_module_ops *funcs)
  27. {
  28. mod->name = name;
  29. mod->funcs = funcs;
  30. INIT_LIST_HEAD(&mod->list);
  31. list_add(&mod->list, &module_list);
  32. }
  33. void tilcdc_module_cleanup(struct tilcdc_module *mod)
  34. {
  35. list_del(&mod->list);
  36. }
  37. static struct of_device_id tilcdc_of_match[];
  38. static struct drm_framebuffer *tilcdc_fb_create(struct drm_device *dev,
  39. struct drm_file *file_priv, struct drm_mode_fb_cmd2 *mode_cmd)
  40. {
  41. return drm_fb_cma_create(dev, file_priv, mode_cmd);
  42. }
  43. static void tilcdc_fb_output_poll_changed(struct drm_device *dev)
  44. {
  45. struct tilcdc_drm_private *priv = dev->dev_private;
  46. if (priv->fbdev)
  47. drm_fbdev_cma_hotplug_event(priv->fbdev);
  48. }
  49. static const struct drm_mode_config_funcs mode_config_funcs = {
  50. .fb_create = tilcdc_fb_create,
  51. .output_poll_changed = tilcdc_fb_output_poll_changed,
  52. };
  53. static int modeset_init(struct drm_device *dev)
  54. {
  55. struct tilcdc_drm_private *priv = dev->dev_private;
  56. struct tilcdc_module *mod;
  57. drm_mode_config_init(dev);
  58. priv->crtc = tilcdc_crtc_create(dev);
  59. list_for_each_entry(mod, &module_list, list) {
  60. DBG("loading module: %s", mod->name);
  61. mod->funcs->modeset_init(mod, dev);
  62. }
  63. if ((priv->num_encoders == 0) || (priv->num_connectors == 0)) {
  64. /* oh nos! */
  65. dev_err(dev->dev, "no encoders/connectors found\n");
  66. return -ENXIO;
  67. }
  68. dev->mode_config.min_width = 0;
  69. dev->mode_config.min_height = 0;
  70. dev->mode_config.max_width = tilcdc_crtc_max_width(priv->crtc);
  71. dev->mode_config.max_height = 2048;
  72. dev->mode_config.funcs = &mode_config_funcs;
  73. return 0;
  74. }
  75. #ifdef CONFIG_CPU_FREQ
  76. static int cpufreq_transition(struct notifier_block *nb,
  77. unsigned long val, void *data)
  78. {
  79. struct tilcdc_drm_private *priv = container_of(nb,
  80. struct tilcdc_drm_private, freq_transition);
  81. if (val == CPUFREQ_POSTCHANGE) {
  82. if (priv->lcd_fck_rate != clk_get_rate(priv->clk)) {
  83. priv->lcd_fck_rate = clk_get_rate(priv->clk);
  84. tilcdc_crtc_update_clk(priv->crtc);
  85. }
  86. }
  87. return 0;
  88. }
  89. #endif
  90. /*
  91. * DRM operations:
  92. */
  93. static int tilcdc_unload(struct drm_device *dev)
  94. {
  95. struct tilcdc_drm_private *priv = dev->dev_private;
  96. struct tilcdc_module *mod, *cur;
  97. drm_kms_helper_poll_fini(dev);
  98. drm_mode_config_cleanup(dev);
  99. drm_vblank_cleanup(dev);
  100. pm_runtime_get_sync(dev->dev);
  101. drm_irq_uninstall(dev);
  102. pm_runtime_put_sync(dev->dev);
  103. #ifdef CONFIG_CPU_FREQ
  104. cpufreq_unregister_notifier(&priv->freq_transition,
  105. CPUFREQ_TRANSITION_NOTIFIER);
  106. #endif
  107. if (priv->clk)
  108. clk_put(priv->clk);
  109. if (priv->mmio)
  110. iounmap(priv->mmio);
  111. flush_workqueue(priv->wq);
  112. destroy_workqueue(priv->wq);
  113. dev->dev_private = NULL;
  114. pm_runtime_disable(dev->dev);
  115. list_for_each_entry_safe(mod, cur, &module_list, list) {
  116. DBG("destroying module: %s", mod->name);
  117. mod->funcs->destroy(mod);
  118. }
  119. kfree(priv);
  120. return 0;
  121. }
  122. static int tilcdc_load(struct drm_device *dev, unsigned long flags)
  123. {
  124. struct platform_device *pdev = dev->platformdev;
  125. struct device_node *node = pdev->dev.of_node;
  126. struct tilcdc_drm_private *priv;
  127. struct resource *res;
  128. int ret;
  129. priv = kzalloc(sizeof(*priv), GFP_KERNEL);
  130. if (!priv) {
  131. dev_err(dev->dev, "failed to allocate private data\n");
  132. return -ENOMEM;
  133. }
  134. dev->dev_private = priv;
  135. priv->wq = alloc_ordered_workqueue("tilcdc", 0);
  136. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  137. if (!res) {
  138. dev_err(dev->dev, "failed to get memory resource\n");
  139. ret = -EINVAL;
  140. goto fail;
  141. }
  142. priv->mmio = ioremap_nocache(res->start, resource_size(res));
  143. if (!priv->mmio) {
  144. dev_err(dev->dev, "failed to ioremap\n");
  145. ret = -ENOMEM;
  146. goto fail;
  147. }
  148. priv->clk = clk_get(dev->dev, "fck");
  149. if (IS_ERR(priv->clk)) {
  150. dev_err(dev->dev, "failed to get functional clock\n");
  151. ret = -ENODEV;
  152. goto fail;
  153. }
  154. priv->disp_clk = clk_get(dev->dev, "dpll_disp_ck");
  155. if (IS_ERR(priv->clk)) {
  156. dev_err(dev->dev, "failed to get display clock\n");
  157. ret = -ENODEV;
  158. goto fail;
  159. }
  160. #ifdef CONFIG_CPU_FREQ
  161. priv->lcd_fck_rate = clk_get_rate(priv->clk);
  162. priv->freq_transition.notifier_call = cpufreq_transition;
  163. ret = cpufreq_register_notifier(&priv->freq_transition,
  164. CPUFREQ_TRANSITION_NOTIFIER);
  165. if (ret) {
  166. dev_err(dev->dev, "failed to register cpufreq notifier\n");
  167. goto fail;
  168. }
  169. #endif
  170. if (of_property_read_u32(node, "max-bandwidth", &priv->max_bandwidth))
  171. priv->max_bandwidth = 1280 * 1024 * 60;
  172. pm_runtime_enable(dev->dev);
  173. /* Determine LCD IP Version */
  174. pm_runtime_get_sync(dev->dev);
  175. switch (tilcdc_read(dev, LCDC_PID_REG)) {
  176. case 0x4c100102:
  177. priv->rev = 1;
  178. break;
  179. case 0x4f200800:
  180. case 0x4f201000:
  181. priv->rev = 2;
  182. break;
  183. default:
  184. dev_warn(dev->dev, "Unknown PID Reg value 0x%08x, "
  185. "defaulting to LCD revision 1\n",
  186. tilcdc_read(dev, LCDC_PID_REG));
  187. priv->rev = 1;
  188. break;
  189. }
  190. pm_runtime_put_sync(dev->dev);
  191. ret = modeset_init(dev);
  192. if (ret < 0) {
  193. dev_err(dev->dev, "failed to initialize mode setting\n");
  194. goto fail;
  195. }
  196. ret = drm_vblank_init(dev, 1);
  197. if (ret < 0) {
  198. dev_err(dev->dev, "failed to initialize vblank\n");
  199. goto fail;
  200. }
  201. pm_runtime_get_sync(dev->dev);
  202. ret = drm_irq_install(dev);
  203. pm_runtime_put_sync(dev->dev);
  204. if (ret < 0) {
  205. dev_err(dev->dev, "failed to install IRQ handler\n");
  206. goto fail;
  207. }
  208. platform_set_drvdata(pdev, dev);
  209. priv->fbdev = drm_fbdev_cma_init(dev, 16,
  210. dev->mode_config.num_crtc,
  211. dev->mode_config.num_connector);
  212. drm_kms_helper_poll_init(dev);
  213. return 0;
  214. fail:
  215. tilcdc_unload(dev);
  216. return ret;
  217. }
  218. static void tilcdc_preclose(struct drm_device *dev, struct drm_file *file)
  219. {
  220. struct tilcdc_drm_private *priv = dev->dev_private;
  221. tilcdc_crtc_cancel_page_flip(priv->crtc, file);
  222. }
  223. static void tilcdc_lastclose(struct drm_device *dev)
  224. {
  225. struct tilcdc_drm_private *priv = dev->dev_private;
  226. drm_fbdev_cma_restore_mode(priv->fbdev);
  227. }
  228. static irqreturn_t tilcdc_irq(DRM_IRQ_ARGS)
  229. {
  230. struct drm_device *dev = arg;
  231. struct tilcdc_drm_private *priv = dev->dev_private;
  232. return tilcdc_crtc_irq(priv->crtc);
  233. }
  234. static void tilcdc_irq_preinstall(struct drm_device *dev)
  235. {
  236. tilcdc_clear_irqstatus(dev, 0xffffffff);
  237. }
  238. static int tilcdc_irq_postinstall(struct drm_device *dev)
  239. {
  240. struct tilcdc_drm_private *priv = dev->dev_private;
  241. /* enable FIFO underflow irq: */
  242. if (priv->rev == 1)
  243. tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_V1_UNDERFLOW_INT_ENA);
  244. else
  245. tilcdc_set(dev, LCDC_INT_ENABLE_SET_REG, LCDC_V2_UNDERFLOW_INT_ENA);
  246. return 0;
  247. }
  248. static void tilcdc_irq_uninstall(struct drm_device *dev)
  249. {
  250. struct tilcdc_drm_private *priv = dev->dev_private;
  251. /* disable irqs that we might have enabled: */
  252. if (priv->rev == 1) {
  253. tilcdc_clear(dev, LCDC_RASTER_CTRL_REG,
  254. LCDC_V1_UNDERFLOW_INT_ENA | LCDC_V1_PL_INT_ENA);
  255. tilcdc_clear(dev, LCDC_DMA_CTRL_REG, LCDC_V1_END_OF_FRAME_INT_ENA);
  256. } else {
  257. tilcdc_clear(dev, LCDC_INT_ENABLE_SET_REG,
  258. LCDC_V2_UNDERFLOW_INT_ENA | LCDC_V2_PL_INT_ENA |
  259. LCDC_V2_END_OF_FRAME0_INT_ENA | LCDC_V2_END_OF_FRAME1_INT_ENA |
  260. LCDC_FRAME_DONE);
  261. }
  262. }
  263. static void enable_vblank(struct drm_device *dev, bool enable)
  264. {
  265. struct tilcdc_drm_private *priv = dev->dev_private;
  266. u32 reg, mask;
  267. if (priv->rev == 1) {
  268. reg = LCDC_DMA_CTRL_REG;
  269. mask = LCDC_V1_END_OF_FRAME_INT_ENA;
  270. } else {
  271. reg = LCDC_INT_ENABLE_SET_REG;
  272. mask = LCDC_V2_END_OF_FRAME0_INT_ENA |
  273. LCDC_V2_END_OF_FRAME1_INT_ENA | LCDC_FRAME_DONE;
  274. }
  275. if (enable)
  276. tilcdc_set(dev, reg, mask);
  277. else
  278. tilcdc_clear(dev, reg, mask);
  279. }
  280. static int tilcdc_enable_vblank(struct drm_device *dev, int crtc)
  281. {
  282. enable_vblank(dev, true);
  283. return 0;
  284. }
  285. static void tilcdc_disable_vblank(struct drm_device *dev, int crtc)
  286. {
  287. enable_vblank(dev, false);
  288. }
  289. #if defined(CONFIG_DEBUG_FS) || defined(CONFIG_PM_SLEEP)
  290. static const struct {
  291. const char *name;
  292. uint8_t rev;
  293. uint8_t save;
  294. uint32_t reg;
  295. } registers[] = {
  296. #define REG(rev, save, reg) { #reg, rev, save, reg }
  297. /* exists in revision 1: */
  298. REG(1, false, LCDC_PID_REG),
  299. REG(1, true, LCDC_CTRL_REG),
  300. REG(1, false, LCDC_STAT_REG),
  301. REG(1, true, LCDC_RASTER_CTRL_REG),
  302. REG(1, true, LCDC_RASTER_TIMING_0_REG),
  303. REG(1, true, LCDC_RASTER_TIMING_1_REG),
  304. REG(1, true, LCDC_RASTER_TIMING_2_REG),
  305. REG(1, true, LCDC_DMA_CTRL_REG),
  306. REG(1, true, LCDC_DMA_FB_BASE_ADDR_0_REG),
  307. REG(1, true, LCDC_DMA_FB_CEILING_ADDR_0_REG),
  308. REG(1, true, LCDC_DMA_FB_BASE_ADDR_1_REG),
  309. REG(1, true, LCDC_DMA_FB_CEILING_ADDR_1_REG),
  310. /* new in revision 2: */
  311. REG(2, false, LCDC_RAW_STAT_REG),
  312. REG(2, false, LCDC_MASKED_STAT_REG),
  313. REG(2, false, LCDC_INT_ENABLE_SET_REG),
  314. REG(2, false, LCDC_INT_ENABLE_CLR_REG),
  315. REG(2, false, LCDC_END_OF_INT_IND_REG),
  316. REG(2, true, LCDC_CLK_ENABLE_REG),
  317. REG(2, true, LCDC_INT_ENABLE_SET_REG),
  318. #undef REG
  319. };
  320. #endif
  321. #ifdef CONFIG_DEBUG_FS
  322. static int tilcdc_regs_show(struct seq_file *m, void *arg)
  323. {
  324. struct drm_info_node *node = (struct drm_info_node *) m->private;
  325. struct drm_device *dev = node->minor->dev;
  326. struct tilcdc_drm_private *priv = dev->dev_private;
  327. unsigned i;
  328. pm_runtime_get_sync(dev->dev);
  329. seq_printf(m, "revision: %d\n", priv->rev);
  330. for (i = 0; i < ARRAY_SIZE(registers); i++)
  331. if (priv->rev >= registers[i].rev)
  332. seq_printf(m, "%s:\t %08x\n", registers[i].name,
  333. tilcdc_read(dev, registers[i].reg));
  334. pm_runtime_put_sync(dev->dev);
  335. return 0;
  336. }
  337. static int tilcdc_mm_show(struct seq_file *m, void *arg)
  338. {
  339. struct drm_info_node *node = (struct drm_info_node *) m->private;
  340. struct drm_device *dev = node->minor->dev;
  341. return drm_mm_dump_table(m, dev->mm_private);
  342. }
  343. static struct drm_info_list tilcdc_debugfs_list[] = {
  344. { "regs", tilcdc_regs_show, 0 },
  345. { "mm", tilcdc_mm_show, 0 },
  346. { "fb", drm_fb_cma_debugfs_show, 0 },
  347. };
  348. static int tilcdc_debugfs_init(struct drm_minor *minor)
  349. {
  350. struct drm_device *dev = minor->dev;
  351. struct tilcdc_module *mod;
  352. int ret;
  353. ret = drm_debugfs_create_files(tilcdc_debugfs_list,
  354. ARRAY_SIZE(tilcdc_debugfs_list),
  355. minor->debugfs_root, minor);
  356. list_for_each_entry(mod, &module_list, list)
  357. if (mod->funcs->debugfs_init)
  358. mod->funcs->debugfs_init(mod, minor);
  359. if (ret) {
  360. dev_err(dev->dev, "could not install tilcdc_debugfs_list\n");
  361. return ret;
  362. }
  363. return ret;
  364. }
  365. static void tilcdc_debugfs_cleanup(struct drm_minor *minor)
  366. {
  367. struct tilcdc_module *mod;
  368. drm_debugfs_remove_files(tilcdc_debugfs_list,
  369. ARRAY_SIZE(tilcdc_debugfs_list), minor);
  370. list_for_each_entry(mod, &module_list, list)
  371. if (mod->funcs->debugfs_cleanup)
  372. mod->funcs->debugfs_cleanup(mod, minor);
  373. }
  374. #endif
  375. static const struct file_operations fops = {
  376. .owner = THIS_MODULE,
  377. .open = drm_open,
  378. .release = drm_release,
  379. .unlocked_ioctl = drm_ioctl,
  380. #ifdef CONFIG_COMPAT
  381. .compat_ioctl = drm_compat_ioctl,
  382. #endif
  383. .poll = drm_poll,
  384. .read = drm_read,
  385. .fasync = drm_fasync,
  386. .llseek = no_llseek,
  387. .mmap = drm_gem_cma_mmap,
  388. };
  389. static struct drm_driver tilcdc_driver = {
  390. .driver_features = DRIVER_HAVE_IRQ | DRIVER_GEM | DRIVER_MODESET,
  391. .load = tilcdc_load,
  392. .unload = tilcdc_unload,
  393. .preclose = tilcdc_preclose,
  394. .lastclose = tilcdc_lastclose,
  395. .irq_handler = tilcdc_irq,
  396. .irq_preinstall = tilcdc_irq_preinstall,
  397. .irq_postinstall = tilcdc_irq_postinstall,
  398. .irq_uninstall = tilcdc_irq_uninstall,
  399. .get_vblank_counter = drm_vblank_count,
  400. .enable_vblank = tilcdc_enable_vblank,
  401. .disable_vblank = tilcdc_disable_vblank,
  402. .gem_free_object = drm_gem_cma_free_object,
  403. .gem_vm_ops = &drm_gem_cma_vm_ops,
  404. .dumb_create = drm_gem_cma_dumb_create,
  405. .dumb_map_offset = drm_gem_cma_dumb_map_offset,
  406. .dumb_destroy = drm_gem_cma_dumb_destroy,
  407. #ifdef CONFIG_DEBUG_FS
  408. .debugfs_init = tilcdc_debugfs_init,
  409. .debugfs_cleanup = tilcdc_debugfs_cleanup,
  410. #endif
  411. .fops = &fops,
  412. .name = "tilcdc",
  413. .desc = "TI LCD Controller DRM",
  414. .date = "20121205",
  415. .major = 1,
  416. .minor = 0,
  417. };
  418. /*
  419. * Power management:
  420. */
  421. #ifdef CONFIG_PM_SLEEP
  422. static int tilcdc_pm_suspend(struct device *dev)
  423. {
  424. struct drm_device *ddev = dev_get_drvdata(dev);
  425. struct tilcdc_drm_private *priv = ddev->dev_private;
  426. unsigned i, n = 0;
  427. drm_kms_helper_poll_disable(ddev);
  428. /* Save register state: */
  429. for (i = 0; i < ARRAY_SIZE(registers); i++)
  430. if (registers[i].save && (priv->rev >= registers[i].rev))
  431. priv->saved_register[n++] = tilcdc_read(ddev, registers[i].reg);
  432. return 0;
  433. }
  434. static int tilcdc_pm_resume(struct device *dev)
  435. {
  436. struct drm_device *ddev = dev_get_drvdata(dev);
  437. struct tilcdc_drm_private *priv = ddev->dev_private;
  438. unsigned i, n = 0;
  439. /* Restore register state: */
  440. for (i = 0; i < ARRAY_SIZE(registers); i++)
  441. if (registers[i].save && (priv->rev >= registers[i].rev))
  442. tilcdc_write(ddev, registers[i].reg, priv->saved_register[n++]);
  443. drm_kms_helper_poll_enable(ddev);
  444. return 0;
  445. }
  446. #endif
  447. static const struct dev_pm_ops tilcdc_pm_ops = {
  448. SET_SYSTEM_SLEEP_PM_OPS(tilcdc_pm_suspend, tilcdc_pm_resume)
  449. };
  450. /*
  451. * Platform driver:
  452. */
  453. static int tilcdc_pdev_probe(struct platform_device *pdev)
  454. {
  455. /* bail out early if no DT data: */
  456. if (!pdev->dev.of_node) {
  457. dev_err(&pdev->dev, "device-tree data is missing\n");
  458. return -ENXIO;
  459. }
  460. return drm_platform_init(&tilcdc_driver, pdev);
  461. }
  462. static int tilcdc_pdev_remove(struct platform_device *pdev)
  463. {
  464. drm_platform_exit(&tilcdc_driver, pdev);
  465. return 0;
  466. }
  467. static struct of_device_id tilcdc_of_match[] = {
  468. { .compatible = "ti,am33xx-tilcdc", },
  469. { },
  470. };
  471. MODULE_DEVICE_TABLE(of, tilcdc_of_match);
  472. static struct platform_driver tilcdc_platform_driver = {
  473. .probe = tilcdc_pdev_probe,
  474. .remove = tilcdc_pdev_remove,
  475. .driver = {
  476. .owner = THIS_MODULE,
  477. .name = "tilcdc",
  478. .pm = &tilcdc_pm_ops,
  479. .of_match_table = tilcdc_of_match,
  480. },
  481. };
  482. static int __init tilcdc_drm_init(void)
  483. {
  484. DBG("init");
  485. tilcdc_tfp410_init();
  486. tilcdc_slave_init();
  487. tilcdc_panel_init();
  488. return platform_driver_register(&tilcdc_platform_driver);
  489. }
  490. static void __exit tilcdc_drm_fini(void)
  491. {
  492. DBG("fini");
  493. tilcdc_tfp410_fini();
  494. tilcdc_slave_fini();
  495. tilcdc_panel_fini();
  496. platform_driver_unregister(&tilcdc_platform_driver);
  497. }
  498. late_initcall(tilcdc_drm_init);
  499. module_exit(tilcdc_drm_fini);
  500. MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
  501. MODULE_DESCRIPTION("TI LCD Controller DRM Driver");
  502. MODULE_LICENSE("GPL");