sharpsl.c 8.1 KB

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  1. /*
  2. * drivers/mtd/nand/sharpsl.c
  3. *
  4. * Copyright (C) 2004 Richard Purdie
  5. *
  6. * Based on Sharp's NAND driver sharp_sl.c
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. *
  12. */
  13. #include <linux/genhd.h>
  14. #include <linux/slab.h>
  15. #include <linux/module.h>
  16. #include <linux/delay.h>
  17. #include <linux/mtd/mtd.h>
  18. #include <linux/mtd/nand.h>
  19. #include <linux/mtd/nand_ecc.h>
  20. #include <linux/mtd/partitions.h>
  21. #include <linux/interrupt.h>
  22. #include <linux/platform_device.h>
  23. #include <asm/io.h>
  24. #include <mach/hardware.h>
  25. #include <asm/mach-types.h>
  26. struct sharpsl_nand {
  27. struct mtd_info mtd;
  28. struct nand_chip chip;
  29. void __iomem *io;
  30. };
  31. #define mtd_to_sharpsl(_mtd) container_of(_mtd, struct sharpsl_nand, mtd)
  32. /* register offset */
  33. #define ECCLPLB 0x00 /* line parity 7 - 0 bit */
  34. #define ECCLPUB 0x04 /* line parity 15 - 8 bit */
  35. #define ECCCP 0x08 /* column parity 5 - 0 bit */
  36. #define ECCCNTR 0x0C /* ECC byte counter */
  37. #define ECCCLRR 0x10 /* cleare ECC */
  38. #define FLASHIO 0x14 /* Flash I/O */
  39. #define FLASHCTL 0x18 /* Flash Control */
  40. /* Flash control bit */
  41. #define FLRYBY (1 << 5)
  42. #define FLCE1 (1 << 4)
  43. #define FLWP (1 << 3)
  44. #define FLALE (1 << 2)
  45. #define FLCLE (1 << 1)
  46. #define FLCE0 (1 << 0)
  47. /*
  48. * Define partitions for flash device
  49. */
  50. #define DEFAULT_NUM_PARTITIONS 3
  51. static int nr_partitions;
  52. static struct mtd_partition sharpsl_nand_default_partition_info[] = {
  53. {
  54. .name = "System Area",
  55. .offset = 0,
  56. .size = 7 * 1024 * 1024,
  57. },
  58. {
  59. .name = "Root Filesystem",
  60. .offset = 7 * 1024 * 1024,
  61. .size = 30 * 1024 * 1024,
  62. },
  63. {
  64. .name = "Home Filesystem",
  65. .offset = MTDPART_OFS_APPEND,
  66. .size = MTDPART_SIZ_FULL,
  67. },
  68. };
  69. /*
  70. * hardware specific access to control-lines
  71. * ctrl:
  72. * NAND_CNE: bit 0 -> ! bit 0 & 4
  73. * NAND_CLE: bit 1 -> bit 1
  74. * NAND_ALE: bit 2 -> bit 2
  75. *
  76. */
  77. static void sharpsl_nand_hwcontrol(struct mtd_info *mtd, int cmd,
  78. unsigned int ctrl)
  79. {
  80. struct sharpsl_nand *sharpsl = mtd_to_sharpsl(mtd);
  81. struct nand_chip *chip = mtd->priv;
  82. if (ctrl & NAND_CTRL_CHANGE) {
  83. unsigned char bits = ctrl & 0x07;
  84. bits |= (ctrl & 0x01) << 4;
  85. bits ^= 0x11;
  86. writeb((readb(sharpsl->io + FLASHCTL) & ~0x17) | bits, sharpsl->io + FLASHCTL);
  87. }
  88. if (cmd != NAND_CMD_NONE)
  89. writeb(cmd, chip->IO_ADDR_W);
  90. }
  91. static uint8_t scan_ff_pattern[] = { 0xff, 0xff };
  92. static struct nand_bbt_descr sharpsl_bbt = {
  93. .options = 0,
  94. .offs = 4,
  95. .len = 2,
  96. .pattern = scan_ff_pattern
  97. };
  98. static struct nand_bbt_descr sharpsl_akita_bbt = {
  99. .options = 0,
  100. .offs = 4,
  101. .len = 1,
  102. .pattern = scan_ff_pattern
  103. };
  104. static struct nand_ecclayout akita_oobinfo = {
  105. .eccbytes = 24,
  106. .eccpos = {
  107. 0x5, 0x1, 0x2, 0x3, 0x6, 0x7, 0x15, 0x11,
  108. 0x12, 0x13, 0x16, 0x17, 0x25, 0x21, 0x22, 0x23,
  109. 0x26, 0x27, 0x35, 0x31, 0x32, 0x33, 0x36, 0x37},
  110. .oobfree = {{0x08, 0x09}}
  111. };
  112. static int sharpsl_nand_dev_ready(struct mtd_info *mtd)
  113. {
  114. struct sharpsl_nand *sharpsl = mtd_to_sharpsl(mtd);
  115. return !((readb(sharpsl->io + FLASHCTL) & FLRYBY) == 0);
  116. }
  117. static void sharpsl_nand_enable_hwecc(struct mtd_info *mtd, int mode)
  118. {
  119. struct sharpsl_nand *sharpsl = mtd_to_sharpsl(mtd);
  120. writeb(0, sharpsl->io + ECCCLRR);
  121. }
  122. static int sharpsl_nand_calculate_ecc(struct mtd_info *mtd, const u_char * dat, u_char * ecc_code)
  123. {
  124. struct sharpsl_nand *sharpsl = mtd_to_sharpsl(mtd);
  125. ecc_code[0] = ~readb(sharpsl->io + ECCLPUB);
  126. ecc_code[1] = ~readb(sharpsl->io + ECCLPLB);
  127. ecc_code[2] = (~readb(sharpsl->io + ECCCP) << 2) | 0x03;
  128. return readb(sharpsl->io + ECCCNTR) != 0;
  129. }
  130. #ifdef CONFIG_MTD_PARTITIONS
  131. const char *part_probes[] = { "cmdlinepart", NULL };
  132. #endif
  133. /*
  134. * Main initialization routine
  135. */
  136. static int __devinit sharpsl_nand_probe(struct platform_device *pdev)
  137. {
  138. struct nand_chip *this;
  139. struct mtd_partition *sharpsl_partition_info;
  140. struct resource *r;
  141. int err = 0;
  142. struct sharpsl_nand *sharpsl;
  143. /* Allocate memory for MTD device structure and private data */
  144. sharpsl = kzalloc(sizeof(struct sharpsl_nand), GFP_KERNEL);
  145. if (!sharpsl) {
  146. printk("Unable to allocate SharpSL NAND MTD device structure.\n");
  147. return -ENOMEM;
  148. }
  149. r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  150. if (!r) {
  151. dev_err(&pdev->dev, "no io memory resource defined!\n");
  152. err = -ENODEV;
  153. goto err_get_res;
  154. }
  155. /* map physical address */
  156. sharpsl->io = ioremap(r->start, resource_size(r));
  157. if (!sharpsl->io) {
  158. printk("ioremap to access Sharp SL NAND chip failed\n");
  159. err = -EIO;
  160. goto err_ioremap;
  161. }
  162. /* Get pointer to private data */
  163. this = (struct nand_chip *)(&sharpsl->chip);
  164. /* Link the private data with the MTD structure */
  165. sharpsl->mtd.priv = this;
  166. sharpsl->mtd.owner = THIS_MODULE;
  167. platform_set_drvdata(pdev, sharpsl);
  168. /*
  169. * PXA initialize
  170. */
  171. writeb(readb(sharpsl->io + FLASHCTL) | FLWP, sharpsl->io + FLASHCTL);
  172. /* Set address of NAND IO lines */
  173. this->IO_ADDR_R = sharpsl->io + FLASHIO;
  174. this->IO_ADDR_W = sharpsl->io + FLASHIO;
  175. /* Set address of hardware control function */
  176. this->cmd_ctrl = sharpsl_nand_hwcontrol;
  177. this->dev_ready = sharpsl_nand_dev_ready;
  178. /* 15 us command delay time */
  179. this->chip_delay = 15;
  180. /* set eccmode using hardware ECC */
  181. this->ecc.mode = NAND_ECC_HW;
  182. this->ecc.size = 256;
  183. this->ecc.bytes = 3;
  184. this->badblock_pattern = &sharpsl_bbt;
  185. if (machine_is_akita() || machine_is_borzoi()) {
  186. this->badblock_pattern = &sharpsl_akita_bbt;
  187. this->ecc.layout = &akita_oobinfo;
  188. }
  189. this->ecc.hwctl = sharpsl_nand_enable_hwecc;
  190. this->ecc.calculate = sharpsl_nand_calculate_ecc;
  191. this->ecc.correct = nand_correct_data;
  192. /* Scan to find existence of the device */
  193. err = nand_scan(&sharpsl->mtd, 1);
  194. if (err)
  195. goto err_scan;
  196. /* Register the partitions */
  197. sharpsl->mtd.name = "sharpsl-nand";
  198. nr_partitions = parse_mtd_partitions(&sharpsl->mtd, part_probes, &sharpsl_partition_info, 0);
  199. if (nr_partitions <= 0) {
  200. nr_partitions = DEFAULT_NUM_PARTITIONS;
  201. sharpsl_partition_info = sharpsl_nand_default_partition_info;
  202. if (machine_is_poodle()) {
  203. sharpsl_partition_info[1].size = 22 * 1024 * 1024;
  204. } else if (machine_is_corgi() || machine_is_shepherd()) {
  205. sharpsl_partition_info[1].size = 25 * 1024 * 1024;
  206. } else if (machine_is_husky()) {
  207. sharpsl_partition_info[1].size = 53 * 1024 * 1024;
  208. } else if (machine_is_spitz()) {
  209. sharpsl_partition_info[1].size = 5 * 1024 * 1024;
  210. } else if (machine_is_akita()) {
  211. sharpsl_partition_info[1].size = 58 * 1024 * 1024;
  212. } else if (machine_is_borzoi()) {
  213. sharpsl_partition_info[1].size = 32 * 1024 * 1024;
  214. }
  215. }
  216. add_mtd_partitions(&sharpsl->mtd, sharpsl_partition_info, nr_partitions);
  217. /* Return happy */
  218. return 0;
  219. err_scan:
  220. platform_set_drvdata(pdev, NULL);
  221. iounmap(sharpsl->io);
  222. err_ioremap:
  223. err_get_res:
  224. kfree(sharpsl);
  225. return err;
  226. }
  227. /*
  228. * Clean up routine
  229. */
  230. static int __devexit sharpsl_nand_remove(struct platform_device *pdev)
  231. {
  232. struct sharpsl_nand *sharpsl = platform_get_drvdata(pdev);
  233. /* Release resources, unregister device */
  234. nand_release(&sharpsl->mtd);
  235. platform_set_drvdata(pdev, NULL);
  236. iounmap(sharpsl->io);
  237. /* Free the MTD device structure */
  238. kfree(sharpsl);
  239. return 0;
  240. }
  241. static struct platform_driver sharpsl_nand_driver = {
  242. .driver = {
  243. .name = "sharpsl-nand",
  244. .owner = THIS_MODULE,
  245. },
  246. .probe = sharpsl_nand_probe,
  247. .remove = __devexit_p(sharpsl_nand_remove),
  248. };
  249. static struct resource sharpsl_nand_resources[] = {
  250. {
  251. .start = 0x0C000000,
  252. .end = 0x0C000FFF,
  253. .flags = IORESOURCE_MEM,
  254. },
  255. };
  256. static struct platform_device sharpsl_nand_device = {
  257. .name = "sharpsl-nand",
  258. .id = -1,
  259. .resource = sharpsl_nand_resources,
  260. .num_resources = ARRAY_SIZE(sharpsl_nand_resources),
  261. };
  262. static int __init sharpsl_nand_init(void)
  263. {
  264. platform_device_register(&sharpsl_nand_device);
  265. return platform_driver_register(&sharpsl_nand_driver);
  266. }
  267. module_init(sharpsl_nand_init);
  268. static void __exit sharpsl_nand_exit(void)
  269. {
  270. platform_driver_unregister(&sharpsl_nand_driver);
  271. platform_device_unregister(&sharpsl_nand_device);
  272. }
  273. module_exit(sharpsl_nand_exit);
  274. MODULE_LICENSE("GPL");
  275. MODULE_AUTHOR("Richard Purdie <rpurdie@rpsys.net>");
  276. MODULE_DESCRIPTION("Device specific logic for NAND flash on Sharp SL-C7xx Series");