clk.h 3.3 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110
  1. #ifndef __MACH_IMX_CLK_H
  2. #define __MACH_IMX_CLK_H
  3. #include <linux/spinlock.h>
  4. #include <linux/clk-provider.h>
  5. extern spinlock_t imx_ccm_lock;
  6. struct clk *imx_clk_pllv1(const char *name, const char *parent,
  7. void __iomem *base);
  8. struct clk *imx_clk_pllv2(const char *name, const char *parent,
  9. void __iomem *base);
  10. enum imx_pllv3_type {
  11. IMX_PLLV3_GENERIC,
  12. IMX_PLLV3_SYS,
  13. IMX_PLLV3_USB,
  14. IMX_PLLV3_AV,
  15. IMX_PLLV3_ENET,
  16. };
  17. struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
  18. const char *parent_name, void __iomem *base, u32 div_mask);
  19. struct clk *clk_register_gate2(struct device *dev, const char *name,
  20. const char *parent_name, unsigned long flags,
  21. void __iomem *reg, u8 bit_idx,
  22. u8 clk_gate_flags, spinlock_t *lock);
  23. struct clk * imx_obtain_fixed_clock(
  24. const char *name, unsigned long rate);
  25. static inline struct clk *imx_clk_gate2(const char *name, const char *parent,
  26. void __iomem *reg, u8 shift)
  27. {
  28. return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
  29. shift, 0, &imx_ccm_lock);
  30. }
  31. struct clk *imx_clk_pfd(const char *name, const char *parent_name,
  32. void __iomem *reg, u8 idx);
  33. struct clk *imx_clk_busy_divider(const char *name, const char *parent_name,
  34. void __iomem *reg, u8 shift, u8 width,
  35. void __iomem *busy_reg, u8 busy_shift);
  36. struct clk *imx_clk_busy_mux(const char *name, void __iomem *reg, u8 shift,
  37. u8 width, void __iomem *busy_reg, u8 busy_shift,
  38. const char **parent_names, int num_parents);
  39. struct clk *imx_clk_fixup_divider(const char *name, const char *parent,
  40. void __iomem *reg, u8 shift, u8 width,
  41. void (*fixup)(u32 *val));
  42. struct clk *imx_clk_fixup_mux(const char *name, void __iomem *reg,
  43. u8 shift, u8 width, const char **parents,
  44. int num_parents, void (*fixup)(u32 *val));
  45. static inline struct clk *imx_clk_fixed(const char *name, int rate)
  46. {
  47. return clk_register_fixed_rate(NULL, name, NULL, CLK_IS_ROOT, rate);
  48. }
  49. static inline struct clk *imx_clk_divider(const char *name, const char *parent,
  50. void __iomem *reg, u8 shift, u8 width)
  51. {
  52. return clk_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT,
  53. reg, shift, width, 0, &imx_ccm_lock);
  54. }
  55. static inline struct clk *imx_clk_divider_flags(const char *name,
  56. const char *parent, void __iomem *reg, u8 shift, u8 width,
  57. unsigned long flags)
  58. {
  59. return clk_register_divider(NULL, name, parent, flags,
  60. reg, shift, width, 0, &imx_ccm_lock);
  61. }
  62. static inline struct clk *imx_clk_gate(const char *name, const char *parent,
  63. void __iomem *reg, u8 shift)
  64. {
  65. return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
  66. shift, 0, &imx_ccm_lock);
  67. }
  68. static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg,
  69. u8 shift, u8 width, const char **parents, int num_parents)
  70. {
  71. return clk_register_mux(NULL, name, parents, num_parents, 0, reg, shift,
  72. width, 0, &imx_ccm_lock);
  73. }
  74. static inline struct clk *imx_clk_mux_flags(const char *name,
  75. void __iomem *reg, u8 shift, u8 width, const char **parents,
  76. int num_parents, unsigned long flags)
  77. {
  78. return clk_register_mux(NULL, name, parents, num_parents,
  79. flags, reg, shift, width, 0,
  80. &imx_ccm_lock);
  81. }
  82. static inline struct clk *imx_clk_fixed_factor(const char *name,
  83. const char *parent, unsigned int mult, unsigned int div)
  84. {
  85. return clk_register_fixed_factor(NULL, name, parent,
  86. CLK_SET_RATE_PARENT, mult, div);
  87. }
  88. #endif