be_main.c 127 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525152615271528152915301531153215331534153515361537153815391540154115421543154415451546154715481549155015511552155315541555155615571558155915601561156215631564156515661567156815691570157115721573157415751576157715781579158015811582158315841585158615871588158915901591159215931594159515961597159815991600160116021603160416051606160716081609161016111612161316141615161616171618161916201621162216231624162516261627162816291630163116321633163416351636163716381639164016411642164316441645164616471648164916501651165216531654165516561657165816591660166116621663166416651666166716681669167016711672167316741675167616771678167916801681168216831684168516861687168816891690169116921693169416951696169716981699170017011702170317041705170617071708170917101711171217131714171517161717171817191720172117221723172417251726172717281729173017311732173317341735173617371738173917401741174217431744174517461747174817491750175117521753175417551756175717581759176017611762176317641765176617671768176917701771177217731774177517761777177817791780178117821783178417851786178717881789179017911792179317941795179617971798179918001801180218031804180518061807180818091810181118121813181418151816181718181819182018211822182318241825182618271828182918301831183218331834183518361837183818391840184118421843184418451846184718481849185018511852185318541855185618571858185918601861186218631864186518661867186818691870187118721873187418751876187718781879188018811882188318841885188618871888188918901891189218931894189518961897189818991900190119021903190419051906190719081909191019111912191319141915191619171918191919201921192219231924192519261927192819291930193119321933193419351936193719381939194019411942194319441945194619471948194919501951195219531954195519561957195819591960196119621963196419651966196719681969197019711972197319741975197619771978197919801981198219831984198519861987198819891990199119921993199419951996199719981999200020012002200320042005200620072008200920102011201220132014201520162017201820192020202120222023202420252026202720282029203020312032203320342035203620372038203920402041204220432044204520462047204820492050205120522053205420552056205720582059206020612062206320642065206620672068206920702071207220732074207520762077207820792080208120822083208420852086208720882089209020912092209320942095209620972098209921002101210221032104210521062107210821092110211121122113211421152116211721182119212021212122212321242125212621272128212921302131213221332134213521362137213821392140214121422143214421452146214721482149215021512152215321542155215621572158215921602161216221632164216521662167216821692170217121722173217421752176217721782179218021812182218321842185218621872188218921902191219221932194219521962197219821992200220122022203220422052206220722082209221022112212221322142215221622172218221922202221222222232224222522262227222822292230223122322233223422352236223722382239224022412242224322442245224622472248224922502251225222532254225522562257225822592260226122622263226422652266226722682269227022712272227322742275227622772278227922802281228222832284228522862287228822892290229122922293229422952296229722982299230023012302230323042305230623072308230923102311231223132314231523162317231823192320232123222323232423252326232723282329233023312332233323342335233623372338233923402341234223432344234523462347234823492350235123522353235423552356235723582359236023612362236323642365236623672368236923702371237223732374237523762377237823792380238123822383238423852386238723882389239023912392239323942395239623972398239924002401240224032404240524062407240824092410241124122413241424152416241724182419242024212422242324242425242624272428242924302431243224332434243524362437243824392440244124422443244424452446244724482449245024512452245324542455245624572458245924602461246224632464246524662467246824692470247124722473247424752476247724782479248024812482248324842485248624872488248924902491249224932494249524962497249824992500250125022503250425052506250725082509251025112512251325142515251625172518251925202521252225232524252525262527252825292530253125322533253425352536253725382539254025412542254325442545254625472548254925502551255225532554255525562557255825592560256125622563256425652566256725682569257025712572257325742575257625772578257925802581258225832584258525862587258825892590259125922593259425952596259725982599260026012602260326042605260626072608260926102611261226132614261526162617261826192620262126222623262426252626262726282629263026312632263326342635263626372638263926402641264226432644264526462647264826492650265126522653265426552656265726582659266026612662266326642665266626672668266926702671267226732674267526762677267826792680268126822683268426852686268726882689269026912692269326942695269626972698269927002701270227032704270527062707270827092710271127122713271427152716271727182719272027212722272327242725272627272728272927302731273227332734273527362737273827392740274127422743274427452746274727482749275027512752275327542755275627572758275927602761276227632764276527662767276827692770277127722773277427752776277727782779278027812782278327842785278627872788278927902791279227932794279527962797279827992800280128022803280428052806280728082809281028112812281328142815281628172818281928202821282228232824282528262827282828292830283128322833283428352836283728382839284028412842284328442845284628472848284928502851285228532854285528562857285828592860286128622863286428652866286728682869287028712872287328742875287628772878287928802881288228832884288528862887288828892890289128922893289428952896289728982899290029012902290329042905290629072908290929102911291229132914291529162917291829192920292129222923292429252926292729282929293029312932293329342935293629372938293929402941294229432944294529462947294829492950295129522953295429552956295729582959296029612962296329642965296629672968296929702971297229732974297529762977297829792980298129822983298429852986298729882989299029912992299329942995299629972998299930003001300230033004300530063007300830093010301130123013301430153016301730183019302030213022302330243025302630273028302930303031303230333034303530363037303830393040304130423043304430453046304730483049305030513052305330543055305630573058305930603061306230633064306530663067306830693070307130723073307430753076307730783079308030813082308330843085308630873088308930903091309230933094309530963097309830993100310131023103310431053106310731083109311031113112311331143115311631173118311931203121312231233124312531263127312831293130313131323133313431353136313731383139314031413142314331443145314631473148314931503151315231533154315531563157315831593160316131623163316431653166316731683169317031713172317331743175317631773178317931803181318231833184318531863187318831893190319131923193319431953196319731983199320032013202320332043205320632073208320932103211321232133214321532163217321832193220322132223223322432253226322732283229323032313232323332343235323632373238323932403241324232433244324532463247324832493250325132523253325432553256325732583259326032613262326332643265326632673268326932703271327232733274327532763277327832793280328132823283328432853286328732883289329032913292329332943295329632973298329933003301330233033304330533063307330833093310331133123313331433153316331733183319332033213322332333243325332633273328332933303331333233333334333533363337333833393340334133423343334433453346334733483349335033513352335333543355335633573358335933603361336233633364336533663367336833693370337133723373337433753376337733783379338033813382338333843385338633873388338933903391339233933394339533963397339833993400340134023403340434053406340734083409341034113412341334143415341634173418341934203421342234233424342534263427342834293430343134323433343434353436343734383439344034413442344334443445344634473448344934503451345234533454345534563457345834593460346134623463346434653466346734683469347034713472347334743475347634773478347934803481348234833484348534863487348834893490349134923493349434953496349734983499350035013502350335043505350635073508350935103511351235133514351535163517351835193520352135223523352435253526352735283529353035313532353335343535353635373538353935403541354235433544354535463547354835493550355135523553355435553556355735583559356035613562356335643565356635673568356935703571357235733574357535763577357835793580358135823583358435853586358735883589359035913592359335943595359635973598359936003601360236033604360536063607360836093610361136123613361436153616361736183619362036213622362336243625362636273628362936303631363236333634363536363637363836393640364136423643364436453646364736483649365036513652365336543655365636573658365936603661366236633664366536663667366836693670367136723673367436753676367736783679368036813682368336843685368636873688368936903691369236933694369536963697369836993700370137023703370437053706370737083709371037113712371337143715371637173718371937203721372237233724372537263727372837293730373137323733373437353736373737383739374037413742374337443745374637473748374937503751375237533754375537563757375837593760376137623763376437653766376737683769377037713772377337743775377637773778377937803781378237833784378537863787378837893790379137923793379437953796379737983799380038013802380338043805380638073808380938103811381238133814381538163817381838193820382138223823382438253826382738283829383038313832383338343835383638373838383938403841384238433844384538463847384838493850385138523853385438553856385738583859386038613862386338643865386638673868386938703871387238733874387538763877387838793880388138823883388438853886388738883889389038913892389338943895389638973898389939003901390239033904390539063907390839093910391139123913391439153916391739183919392039213922392339243925392639273928392939303931393239333934393539363937393839393940394139423943394439453946394739483949395039513952395339543955395639573958395939603961396239633964396539663967396839693970397139723973397439753976397739783979398039813982398339843985398639873988398939903991399239933994399539963997399839994000400140024003400440054006400740084009401040114012401340144015401640174018401940204021402240234024402540264027402840294030403140324033403440354036403740384039404040414042404340444045404640474048404940504051405240534054405540564057405840594060406140624063406440654066406740684069407040714072407340744075407640774078407940804081408240834084408540864087408840894090409140924093409440954096409740984099410041014102410341044105410641074108410941104111411241134114411541164117411841194120412141224123412441254126412741284129413041314132413341344135413641374138413941404141414241434144414541464147414841494150415141524153415441554156415741584159416041614162416341644165416641674168416941704171417241734174417541764177417841794180418141824183418441854186418741884189419041914192419341944195419641974198419942004201420242034204420542064207420842094210421142124213421442154216421742184219422042214222422342244225422642274228422942304231423242334234423542364237423842394240424142424243424442454246424742484249425042514252425342544255425642574258425942604261426242634264426542664267426842694270427142724273427442754276427742784279428042814282428342844285428642874288428942904291429242934294429542964297429842994300430143024303430443054306430743084309431043114312431343144315431643174318431943204321432243234324432543264327432843294330433143324333433443354336433743384339434043414342434343444345434643474348434943504351435243534354435543564357435843594360436143624363436443654366436743684369437043714372437343744375437643774378437943804381438243834384438543864387438843894390439143924393439443954396439743984399440044014402440344044405440644074408440944104411441244134414441544164417441844194420442144224423442444254426442744284429443044314432443344344435443644374438443944404441444244434444444544464447444844494450445144524453445444554456445744584459446044614462446344644465446644674468446944704471447244734474447544764477447844794480448144824483448444854486448744884489449044914492449344944495449644974498449945004501
  1. /**
  2. * Copyright (C) 2005 - 2011 Emulex
  3. * All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License version 2
  7. * as published by the Free Software Foundation. The full GNU General
  8. * Public License is included in this distribution in the file called COPYING.
  9. *
  10. * Written by: Jayamohan Kallickal (jayamohan.kallickal@emulex.com)
  11. *
  12. * Contact Information:
  13. * linux-drivers@emulex.com
  14. *
  15. * Emulex
  16. * 3333 Susan Street
  17. * Costa Mesa, CA 92626
  18. */
  19. #include <linux/reboot.h>
  20. #include <linux/delay.h>
  21. #include <linux/slab.h>
  22. #include <linux/interrupt.h>
  23. #include <linux/blkdev.h>
  24. #include <linux/pci.h>
  25. #include <linux/string.h>
  26. #include <linux/kernel.h>
  27. #include <linux/semaphore.h>
  28. #include <linux/iscsi_boot_sysfs.h>
  29. #include <linux/module.h>
  30. #include <scsi/libiscsi.h>
  31. #include <scsi/scsi_transport_iscsi.h>
  32. #include <scsi/scsi_transport.h>
  33. #include <scsi/scsi_cmnd.h>
  34. #include <scsi/scsi_device.h>
  35. #include <scsi/scsi_host.h>
  36. #include <scsi/scsi.h>
  37. #include "be_main.h"
  38. #include "be_iscsi.h"
  39. #include "be_mgmt.h"
  40. static unsigned int be_iopoll_budget = 10;
  41. static unsigned int be_max_phys_size = 64;
  42. static unsigned int enable_msix = 1;
  43. static unsigned int gcrashmode = 0;
  44. static unsigned int num_hba = 0;
  45. MODULE_DEVICE_TABLE(pci, beiscsi_pci_id_table);
  46. MODULE_DESCRIPTION(DRV_DESC " " BUILD_STR);
  47. MODULE_AUTHOR("ServerEngines Corporation");
  48. MODULE_LICENSE("GPL");
  49. module_param(be_iopoll_budget, int, 0);
  50. module_param(enable_msix, int, 0);
  51. module_param(be_max_phys_size, uint, S_IRUGO);
  52. MODULE_PARM_DESC(be_max_phys_size, "Maximum Size (In Kilobytes) of physically"
  53. "contiguous memory that can be allocated."
  54. "Range is 16 - 128");
  55. static int beiscsi_slave_configure(struct scsi_device *sdev)
  56. {
  57. blk_queue_max_segment_size(sdev->request_queue, 65536);
  58. return 0;
  59. }
  60. static int beiscsi_eh_abort(struct scsi_cmnd *sc)
  61. {
  62. struct iscsi_cls_session *cls_session;
  63. struct iscsi_task *aborted_task = (struct iscsi_task *)sc->SCp.ptr;
  64. struct beiscsi_io_task *aborted_io_task;
  65. struct iscsi_conn *conn;
  66. struct beiscsi_conn *beiscsi_conn;
  67. struct beiscsi_hba *phba;
  68. struct iscsi_session *session;
  69. struct invalidate_command_table *inv_tbl;
  70. struct be_dma_mem nonemb_cmd;
  71. unsigned int cid, tag, num_invalidate;
  72. cls_session = starget_to_session(scsi_target(sc->device));
  73. session = cls_session->dd_data;
  74. spin_lock_bh(&session->lock);
  75. if (!aborted_task || !aborted_task->sc) {
  76. /* we raced */
  77. spin_unlock_bh(&session->lock);
  78. return SUCCESS;
  79. }
  80. aborted_io_task = aborted_task->dd_data;
  81. if (!aborted_io_task->scsi_cmnd) {
  82. /* raced or invalid command */
  83. spin_unlock_bh(&session->lock);
  84. return SUCCESS;
  85. }
  86. spin_unlock_bh(&session->lock);
  87. conn = aborted_task->conn;
  88. beiscsi_conn = conn->dd_data;
  89. phba = beiscsi_conn->phba;
  90. /* invalidate iocb */
  91. cid = beiscsi_conn->beiscsi_conn_cid;
  92. inv_tbl = phba->inv_tbl;
  93. memset(inv_tbl, 0x0, sizeof(*inv_tbl));
  94. inv_tbl->cid = cid;
  95. inv_tbl->icd = aborted_io_task->psgl_handle->sgl_index;
  96. num_invalidate = 1;
  97. nonemb_cmd.va = pci_alloc_consistent(phba->ctrl.pdev,
  98. sizeof(struct invalidate_commands_params_in),
  99. &nonemb_cmd.dma);
  100. if (nonemb_cmd.va == NULL) {
  101. SE_DEBUG(DBG_LVL_1,
  102. "Failed to allocate memory for"
  103. "mgmt_invalidate_icds\n");
  104. return FAILED;
  105. }
  106. nonemb_cmd.size = sizeof(struct invalidate_commands_params_in);
  107. tag = mgmt_invalidate_icds(phba, inv_tbl, num_invalidate,
  108. cid, &nonemb_cmd);
  109. if (!tag) {
  110. shost_printk(KERN_WARNING, phba->shost,
  111. "mgmt_invalidate_icds could not be"
  112. " submitted\n");
  113. pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
  114. nonemb_cmd.va, nonemb_cmd.dma);
  115. return FAILED;
  116. } else {
  117. wait_event_interruptible(phba->ctrl.mcc_wait[tag],
  118. phba->ctrl.mcc_numtag[tag]);
  119. free_mcc_tag(&phba->ctrl, tag);
  120. }
  121. pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
  122. nonemb_cmd.va, nonemb_cmd.dma);
  123. return iscsi_eh_abort(sc);
  124. }
  125. static int beiscsi_eh_device_reset(struct scsi_cmnd *sc)
  126. {
  127. struct iscsi_task *abrt_task;
  128. struct beiscsi_io_task *abrt_io_task;
  129. struct iscsi_conn *conn;
  130. struct beiscsi_conn *beiscsi_conn;
  131. struct beiscsi_hba *phba;
  132. struct iscsi_session *session;
  133. struct iscsi_cls_session *cls_session;
  134. struct invalidate_command_table *inv_tbl;
  135. struct be_dma_mem nonemb_cmd;
  136. unsigned int cid, tag, i, num_invalidate;
  137. /* invalidate iocbs */
  138. cls_session = starget_to_session(scsi_target(sc->device));
  139. session = cls_session->dd_data;
  140. spin_lock_bh(&session->lock);
  141. if (!session->leadconn || session->state != ISCSI_STATE_LOGGED_IN) {
  142. spin_unlock_bh(&session->lock);
  143. return FAILED;
  144. }
  145. conn = session->leadconn;
  146. beiscsi_conn = conn->dd_data;
  147. phba = beiscsi_conn->phba;
  148. cid = beiscsi_conn->beiscsi_conn_cid;
  149. inv_tbl = phba->inv_tbl;
  150. memset(inv_tbl, 0x0, sizeof(*inv_tbl) * BE2_CMDS_PER_CXN);
  151. num_invalidate = 0;
  152. for (i = 0; i < conn->session->cmds_max; i++) {
  153. abrt_task = conn->session->cmds[i];
  154. abrt_io_task = abrt_task->dd_data;
  155. if (!abrt_task->sc || abrt_task->state == ISCSI_TASK_FREE)
  156. continue;
  157. if (abrt_task->sc->device->lun != abrt_task->sc->device->lun)
  158. continue;
  159. inv_tbl->cid = cid;
  160. inv_tbl->icd = abrt_io_task->psgl_handle->sgl_index;
  161. num_invalidate++;
  162. inv_tbl++;
  163. }
  164. spin_unlock_bh(&session->lock);
  165. inv_tbl = phba->inv_tbl;
  166. nonemb_cmd.va = pci_alloc_consistent(phba->ctrl.pdev,
  167. sizeof(struct invalidate_commands_params_in),
  168. &nonemb_cmd.dma);
  169. if (nonemb_cmd.va == NULL) {
  170. SE_DEBUG(DBG_LVL_1,
  171. "Failed to allocate memory for"
  172. "mgmt_invalidate_icds\n");
  173. return FAILED;
  174. }
  175. nonemb_cmd.size = sizeof(struct invalidate_commands_params_in);
  176. memset(nonemb_cmd.va, 0, nonemb_cmd.size);
  177. tag = mgmt_invalidate_icds(phba, inv_tbl, num_invalidate,
  178. cid, &nonemb_cmd);
  179. if (!tag) {
  180. shost_printk(KERN_WARNING, phba->shost,
  181. "mgmt_invalidate_icds could not be"
  182. " submitted\n");
  183. pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
  184. nonemb_cmd.va, nonemb_cmd.dma);
  185. return FAILED;
  186. } else {
  187. wait_event_interruptible(phba->ctrl.mcc_wait[tag],
  188. phba->ctrl.mcc_numtag[tag]);
  189. free_mcc_tag(&phba->ctrl, tag);
  190. }
  191. pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
  192. nonemb_cmd.va, nonemb_cmd.dma);
  193. return iscsi_eh_device_reset(sc);
  194. }
  195. static ssize_t beiscsi_show_boot_tgt_info(void *data, int type, char *buf)
  196. {
  197. struct beiscsi_hba *phba = data;
  198. struct mgmt_session_info *boot_sess = &phba->boot_sess;
  199. struct mgmt_conn_info *boot_conn = &boot_sess->conn_list[0];
  200. char *str = buf;
  201. int rc;
  202. switch (type) {
  203. case ISCSI_BOOT_TGT_NAME:
  204. rc = sprintf(buf, "%.*s\n",
  205. (int)strlen(boot_sess->target_name),
  206. (char *)&boot_sess->target_name);
  207. break;
  208. case ISCSI_BOOT_TGT_IP_ADDR:
  209. if (boot_conn->dest_ipaddr.ip_type == 0x1)
  210. rc = sprintf(buf, "%pI4\n",
  211. (char *)&boot_conn->dest_ipaddr.ip_address);
  212. else
  213. rc = sprintf(str, "%pI6\n",
  214. (char *)&boot_conn->dest_ipaddr.ip_address);
  215. break;
  216. case ISCSI_BOOT_TGT_PORT:
  217. rc = sprintf(str, "%d\n", boot_conn->dest_port);
  218. break;
  219. case ISCSI_BOOT_TGT_CHAP_NAME:
  220. rc = sprintf(str, "%.*s\n",
  221. boot_conn->negotiated_login_options.auth_data.chap.
  222. target_chap_name_length,
  223. (char *)&boot_conn->negotiated_login_options.
  224. auth_data.chap.target_chap_name);
  225. break;
  226. case ISCSI_BOOT_TGT_CHAP_SECRET:
  227. rc = sprintf(str, "%.*s\n",
  228. boot_conn->negotiated_login_options.auth_data.chap.
  229. target_secret_length,
  230. (char *)&boot_conn->negotiated_login_options.
  231. auth_data.chap.target_secret);
  232. break;
  233. case ISCSI_BOOT_TGT_REV_CHAP_NAME:
  234. rc = sprintf(str, "%.*s\n",
  235. boot_conn->negotiated_login_options.auth_data.chap.
  236. intr_chap_name_length,
  237. (char *)&boot_conn->negotiated_login_options.
  238. auth_data.chap.intr_chap_name);
  239. break;
  240. case ISCSI_BOOT_TGT_REV_CHAP_SECRET:
  241. rc = sprintf(str, "%.*s\n",
  242. boot_conn->negotiated_login_options.auth_data.chap.
  243. intr_secret_length,
  244. (char *)&boot_conn->negotiated_login_options.
  245. auth_data.chap.intr_secret);
  246. break;
  247. case ISCSI_BOOT_TGT_FLAGS:
  248. rc = sprintf(str, "2\n");
  249. break;
  250. case ISCSI_BOOT_TGT_NIC_ASSOC:
  251. rc = sprintf(str, "0\n");
  252. break;
  253. default:
  254. rc = -ENOSYS;
  255. break;
  256. }
  257. return rc;
  258. }
  259. static ssize_t beiscsi_show_boot_ini_info(void *data, int type, char *buf)
  260. {
  261. struct beiscsi_hba *phba = data;
  262. char *str = buf;
  263. int rc;
  264. switch (type) {
  265. case ISCSI_BOOT_INI_INITIATOR_NAME:
  266. rc = sprintf(str, "%s\n", phba->boot_sess.initiator_iscsiname);
  267. break;
  268. default:
  269. rc = -ENOSYS;
  270. break;
  271. }
  272. return rc;
  273. }
  274. static ssize_t beiscsi_show_boot_eth_info(void *data, int type, char *buf)
  275. {
  276. struct beiscsi_hba *phba = data;
  277. char *str = buf;
  278. int rc;
  279. switch (type) {
  280. case ISCSI_BOOT_ETH_FLAGS:
  281. rc = sprintf(str, "2\n");
  282. break;
  283. case ISCSI_BOOT_ETH_INDEX:
  284. rc = sprintf(str, "0\n");
  285. break;
  286. case ISCSI_BOOT_ETH_MAC:
  287. rc = beiscsi_get_macaddr(buf, phba);
  288. if (rc < 0) {
  289. SE_DEBUG(DBG_LVL_1, "beiscsi_get_macaddr Failed\n");
  290. return rc;
  291. }
  292. break;
  293. default:
  294. rc = -ENOSYS;
  295. break;
  296. }
  297. return rc;
  298. }
  299. static umode_t beiscsi_tgt_get_attr_visibility(void *data, int type)
  300. {
  301. umode_t rc;
  302. switch (type) {
  303. case ISCSI_BOOT_TGT_NAME:
  304. case ISCSI_BOOT_TGT_IP_ADDR:
  305. case ISCSI_BOOT_TGT_PORT:
  306. case ISCSI_BOOT_TGT_CHAP_NAME:
  307. case ISCSI_BOOT_TGT_CHAP_SECRET:
  308. case ISCSI_BOOT_TGT_REV_CHAP_NAME:
  309. case ISCSI_BOOT_TGT_REV_CHAP_SECRET:
  310. case ISCSI_BOOT_TGT_NIC_ASSOC:
  311. case ISCSI_BOOT_TGT_FLAGS:
  312. rc = S_IRUGO;
  313. break;
  314. default:
  315. rc = 0;
  316. break;
  317. }
  318. return rc;
  319. }
  320. static umode_t beiscsi_ini_get_attr_visibility(void *data, int type)
  321. {
  322. umode_t rc;
  323. switch (type) {
  324. case ISCSI_BOOT_INI_INITIATOR_NAME:
  325. rc = S_IRUGO;
  326. break;
  327. default:
  328. rc = 0;
  329. break;
  330. }
  331. return rc;
  332. }
  333. static umode_t beiscsi_eth_get_attr_visibility(void *data, int type)
  334. {
  335. umode_t rc;
  336. switch (type) {
  337. case ISCSI_BOOT_ETH_FLAGS:
  338. case ISCSI_BOOT_ETH_MAC:
  339. case ISCSI_BOOT_ETH_INDEX:
  340. rc = S_IRUGO;
  341. break;
  342. default:
  343. rc = 0;
  344. break;
  345. }
  346. return rc;
  347. }
  348. /*------------------- PCI Driver operations and data ----------------- */
  349. static DEFINE_PCI_DEVICE_TABLE(beiscsi_pci_id_table) = {
  350. { PCI_DEVICE(BE_VENDOR_ID, BE_DEVICE_ID1) },
  351. { PCI_DEVICE(BE_VENDOR_ID, BE_DEVICE_ID2) },
  352. { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID1) },
  353. { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID2) },
  354. { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID3) },
  355. { 0 }
  356. };
  357. MODULE_DEVICE_TABLE(pci, beiscsi_pci_id_table);
  358. static struct scsi_host_template beiscsi_sht = {
  359. .module = THIS_MODULE,
  360. .name = "ServerEngines 10Gbe open-iscsi Initiator Driver",
  361. .proc_name = DRV_NAME,
  362. .queuecommand = iscsi_queuecommand,
  363. .change_queue_depth = iscsi_change_queue_depth,
  364. .slave_configure = beiscsi_slave_configure,
  365. .target_alloc = iscsi_target_alloc,
  366. .eh_abort_handler = beiscsi_eh_abort,
  367. .eh_device_reset_handler = beiscsi_eh_device_reset,
  368. .eh_target_reset_handler = iscsi_eh_session_reset,
  369. .sg_tablesize = BEISCSI_SGLIST_ELEMENTS,
  370. .can_queue = BE2_IO_DEPTH,
  371. .this_id = -1,
  372. .max_sectors = BEISCSI_MAX_SECTORS,
  373. .cmd_per_lun = BEISCSI_CMD_PER_LUN,
  374. .use_clustering = ENABLE_CLUSTERING,
  375. };
  376. static struct scsi_transport_template *beiscsi_scsi_transport;
  377. static struct beiscsi_hba *beiscsi_hba_alloc(struct pci_dev *pcidev)
  378. {
  379. struct beiscsi_hba *phba;
  380. struct Scsi_Host *shost;
  381. shost = iscsi_host_alloc(&beiscsi_sht, sizeof(*phba), 0);
  382. if (!shost) {
  383. dev_err(&pcidev->dev, "beiscsi_hba_alloc -"
  384. "iscsi_host_alloc failed\n");
  385. return NULL;
  386. }
  387. shost->dma_boundary = pcidev->dma_mask;
  388. shost->max_id = BE2_MAX_SESSIONS;
  389. shost->max_channel = 0;
  390. shost->max_cmd_len = BEISCSI_MAX_CMD_LEN;
  391. shost->max_lun = BEISCSI_NUM_MAX_LUN;
  392. shost->transportt = beiscsi_scsi_transport;
  393. phba = iscsi_host_priv(shost);
  394. memset(phba, 0, sizeof(*phba));
  395. phba->shost = shost;
  396. phba->pcidev = pci_dev_get(pcidev);
  397. pci_set_drvdata(pcidev, phba);
  398. if (iscsi_host_add(shost, &phba->pcidev->dev))
  399. goto free_devices;
  400. return phba;
  401. free_devices:
  402. pci_dev_put(phba->pcidev);
  403. iscsi_host_free(phba->shost);
  404. return NULL;
  405. }
  406. static void beiscsi_unmap_pci_function(struct beiscsi_hba *phba)
  407. {
  408. if (phba->csr_va) {
  409. iounmap(phba->csr_va);
  410. phba->csr_va = NULL;
  411. }
  412. if (phba->db_va) {
  413. iounmap(phba->db_va);
  414. phba->db_va = NULL;
  415. }
  416. if (phba->pci_va) {
  417. iounmap(phba->pci_va);
  418. phba->pci_va = NULL;
  419. }
  420. }
  421. static int beiscsi_map_pci_bars(struct beiscsi_hba *phba,
  422. struct pci_dev *pcidev)
  423. {
  424. u8 __iomem *addr;
  425. int pcicfg_reg;
  426. addr = ioremap_nocache(pci_resource_start(pcidev, 2),
  427. pci_resource_len(pcidev, 2));
  428. if (addr == NULL)
  429. return -ENOMEM;
  430. phba->ctrl.csr = addr;
  431. phba->csr_va = addr;
  432. phba->csr_pa.u.a64.address = pci_resource_start(pcidev, 2);
  433. addr = ioremap_nocache(pci_resource_start(pcidev, 4), 128 * 1024);
  434. if (addr == NULL)
  435. goto pci_map_err;
  436. phba->ctrl.db = addr;
  437. phba->db_va = addr;
  438. phba->db_pa.u.a64.address = pci_resource_start(pcidev, 4);
  439. if (phba->generation == BE_GEN2)
  440. pcicfg_reg = 1;
  441. else
  442. pcicfg_reg = 0;
  443. addr = ioremap_nocache(pci_resource_start(pcidev, pcicfg_reg),
  444. pci_resource_len(pcidev, pcicfg_reg));
  445. if (addr == NULL)
  446. goto pci_map_err;
  447. phba->ctrl.pcicfg = addr;
  448. phba->pci_va = addr;
  449. phba->pci_pa.u.a64.address = pci_resource_start(pcidev, pcicfg_reg);
  450. return 0;
  451. pci_map_err:
  452. beiscsi_unmap_pci_function(phba);
  453. return -ENOMEM;
  454. }
  455. static int beiscsi_enable_pci(struct pci_dev *pcidev)
  456. {
  457. int ret;
  458. ret = pci_enable_device(pcidev);
  459. if (ret) {
  460. dev_err(&pcidev->dev, "beiscsi_enable_pci - enable device "
  461. "failed. Returning -ENODEV\n");
  462. return ret;
  463. }
  464. pci_set_master(pcidev);
  465. if (pci_set_consistent_dma_mask(pcidev, DMA_BIT_MASK(64))) {
  466. ret = pci_set_consistent_dma_mask(pcidev, DMA_BIT_MASK(32));
  467. if (ret) {
  468. dev_err(&pcidev->dev, "Could not set PCI DMA Mask\n");
  469. pci_disable_device(pcidev);
  470. return ret;
  471. }
  472. }
  473. return 0;
  474. }
  475. static int be_ctrl_init(struct beiscsi_hba *phba, struct pci_dev *pdev)
  476. {
  477. struct be_ctrl_info *ctrl = &phba->ctrl;
  478. struct be_dma_mem *mbox_mem_alloc = &ctrl->mbox_mem_alloced;
  479. struct be_dma_mem *mbox_mem_align = &ctrl->mbox_mem;
  480. int status = 0;
  481. ctrl->pdev = pdev;
  482. status = beiscsi_map_pci_bars(phba, pdev);
  483. if (status)
  484. return status;
  485. mbox_mem_alloc->size = sizeof(struct be_mcc_mailbox) + 16;
  486. mbox_mem_alloc->va = pci_alloc_consistent(pdev,
  487. mbox_mem_alloc->size,
  488. &mbox_mem_alloc->dma);
  489. if (!mbox_mem_alloc->va) {
  490. beiscsi_unmap_pci_function(phba);
  491. return -ENOMEM;
  492. }
  493. mbox_mem_align->size = sizeof(struct be_mcc_mailbox);
  494. mbox_mem_align->va = PTR_ALIGN(mbox_mem_alloc->va, 16);
  495. mbox_mem_align->dma = PTR_ALIGN(mbox_mem_alloc->dma, 16);
  496. memset(mbox_mem_align->va, 0, sizeof(struct be_mcc_mailbox));
  497. spin_lock_init(&ctrl->mbox_lock);
  498. spin_lock_init(&phba->ctrl.mcc_lock);
  499. spin_lock_init(&phba->ctrl.mcc_cq_lock);
  500. return status;
  501. }
  502. static void beiscsi_get_params(struct beiscsi_hba *phba)
  503. {
  504. phba->params.ios_per_ctrl = (phba->fw_config.iscsi_icd_count
  505. - (phba->fw_config.iscsi_cid_count
  506. + BE2_TMFS
  507. + BE2_NOPOUT_REQ));
  508. phba->params.cxns_per_ctrl = phba->fw_config.iscsi_cid_count;
  509. phba->params.asyncpdus_per_ctrl = phba->fw_config.iscsi_cid_count * 2;
  510. phba->params.icds_per_ctrl = phba->fw_config.iscsi_icd_count;
  511. phba->params.num_sge_per_io = BE2_SGE;
  512. phba->params.defpdu_hdr_sz = BE2_DEFPDU_HDR_SZ;
  513. phba->params.defpdu_data_sz = BE2_DEFPDU_DATA_SZ;
  514. phba->params.eq_timer = 64;
  515. phba->params.num_eq_entries =
  516. (((BE2_CMDS_PER_CXN * 2 + phba->fw_config.iscsi_cid_count * 2
  517. + BE2_TMFS) / 512) + 1) * 512;
  518. phba->params.num_eq_entries = (phba->params.num_eq_entries < 1024)
  519. ? 1024 : phba->params.num_eq_entries;
  520. SE_DEBUG(DBG_LVL_8, "phba->params.num_eq_entries=%d\n",
  521. phba->params.num_eq_entries);
  522. phba->params.num_cq_entries =
  523. (((BE2_CMDS_PER_CXN * 2 + phba->fw_config.iscsi_cid_count * 2
  524. + BE2_TMFS) / 512) + 1) * 512;
  525. phba->params.wrbs_per_cxn = 256;
  526. }
  527. static void hwi_ring_eq_db(struct beiscsi_hba *phba,
  528. unsigned int id, unsigned int clr_interrupt,
  529. unsigned int num_processed,
  530. unsigned char rearm, unsigned char event)
  531. {
  532. u32 val = 0;
  533. val |= id & DB_EQ_RING_ID_MASK;
  534. if (rearm)
  535. val |= 1 << DB_EQ_REARM_SHIFT;
  536. if (clr_interrupt)
  537. val |= 1 << DB_EQ_CLR_SHIFT;
  538. if (event)
  539. val |= 1 << DB_EQ_EVNT_SHIFT;
  540. val |= num_processed << DB_EQ_NUM_POPPED_SHIFT;
  541. iowrite32(val, phba->db_va + DB_EQ_OFFSET);
  542. }
  543. /**
  544. * be_isr_mcc - The isr routine of the driver.
  545. * @irq: Not used
  546. * @dev_id: Pointer to host adapter structure
  547. */
  548. static irqreturn_t be_isr_mcc(int irq, void *dev_id)
  549. {
  550. struct beiscsi_hba *phba;
  551. struct be_eq_entry *eqe = NULL;
  552. struct be_queue_info *eq;
  553. struct be_queue_info *mcc;
  554. unsigned int num_eq_processed;
  555. struct be_eq_obj *pbe_eq;
  556. unsigned long flags;
  557. pbe_eq = dev_id;
  558. eq = &pbe_eq->q;
  559. phba = pbe_eq->phba;
  560. mcc = &phba->ctrl.mcc_obj.cq;
  561. eqe = queue_tail_node(eq);
  562. if (!eqe)
  563. SE_DEBUG(DBG_LVL_1, "eqe is NULL\n");
  564. num_eq_processed = 0;
  565. while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
  566. & EQE_VALID_MASK) {
  567. if (((eqe->dw[offsetof(struct amap_eq_entry,
  568. resource_id) / 32] &
  569. EQE_RESID_MASK) >> 16) == mcc->id) {
  570. spin_lock_irqsave(&phba->isr_lock, flags);
  571. phba->todo_mcc_cq = 1;
  572. spin_unlock_irqrestore(&phba->isr_lock, flags);
  573. }
  574. AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
  575. queue_tail_inc(eq);
  576. eqe = queue_tail_node(eq);
  577. num_eq_processed++;
  578. }
  579. if (phba->todo_mcc_cq)
  580. queue_work(phba->wq, &phba->work_cqs);
  581. if (num_eq_processed)
  582. hwi_ring_eq_db(phba, eq->id, 1, num_eq_processed, 1, 1);
  583. return IRQ_HANDLED;
  584. }
  585. /**
  586. * be_isr_msix - The isr routine of the driver.
  587. * @irq: Not used
  588. * @dev_id: Pointer to host adapter structure
  589. */
  590. static irqreturn_t be_isr_msix(int irq, void *dev_id)
  591. {
  592. struct beiscsi_hba *phba;
  593. struct be_eq_entry *eqe = NULL;
  594. struct be_queue_info *eq;
  595. struct be_queue_info *cq;
  596. unsigned int num_eq_processed;
  597. struct be_eq_obj *pbe_eq;
  598. unsigned long flags;
  599. pbe_eq = dev_id;
  600. eq = &pbe_eq->q;
  601. cq = pbe_eq->cq;
  602. eqe = queue_tail_node(eq);
  603. if (!eqe)
  604. SE_DEBUG(DBG_LVL_1, "eqe is NULL\n");
  605. phba = pbe_eq->phba;
  606. num_eq_processed = 0;
  607. if (blk_iopoll_enabled) {
  608. while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
  609. & EQE_VALID_MASK) {
  610. if (!blk_iopoll_sched_prep(&pbe_eq->iopoll))
  611. blk_iopoll_sched(&pbe_eq->iopoll);
  612. AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
  613. queue_tail_inc(eq);
  614. eqe = queue_tail_node(eq);
  615. num_eq_processed++;
  616. }
  617. if (num_eq_processed)
  618. hwi_ring_eq_db(phba, eq->id, 1, num_eq_processed, 0, 1);
  619. return IRQ_HANDLED;
  620. } else {
  621. while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
  622. & EQE_VALID_MASK) {
  623. spin_lock_irqsave(&phba->isr_lock, flags);
  624. phba->todo_cq = 1;
  625. spin_unlock_irqrestore(&phba->isr_lock, flags);
  626. AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
  627. queue_tail_inc(eq);
  628. eqe = queue_tail_node(eq);
  629. num_eq_processed++;
  630. }
  631. if (phba->todo_cq)
  632. queue_work(phba->wq, &phba->work_cqs);
  633. if (num_eq_processed)
  634. hwi_ring_eq_db(phba, eq->id, 1, num_eq_processed, 1, 1);
  635. return IRQ_HANDLED;
  636. }
  637. }
  638. /**
  639. * be_isr - The isr routine of the driver.
  640. * @irq: Not used
  641. * @dev_id: Pointer to host adapter structure
  642. */
  643. static irqreturn_t be_isr(int irq, void *dev_id)
  644. {
  645. struct beiscsi_hba *phba;
  646. struct hwi_controller *phwi_ctrlr;
  647. struct hwi_context_memory *phwi_context;
  648. struct be_eq_entry *eqe = NULL;
  649. struct be_queue_info *eq;
  650. struct be_queue_info *cq;
  651. struct be_queue_info *mcc;
  652. unsigned long flags, index;
  653. unsigned int num_mcceq_processed, num_ioeq_processed;
  654. struct be_ctrl_info *ctrl;
  655. struct be_eq_obj *pbe_eq;
  656. int isr;
  657. phba = dev_id;
  658. ctrl = &phba->ctrl;
  659. isr = ioread32(ctrl->csr + CEV_ISR0_OFFSET +
  660. (PCI_FUNC(ctrl->pdev->devfn) * CEV_ISR_SIZE));
  661. if (!isr)
  662. return IRQ_NONE;
  663. phwi_ctrlr = phba->phwi_ctrlr;
  664. phwi_context = phwi_ctrlr->phwi_ctxt;
  665. pbe_eq = &phwi_context->be_eq[0];
  666. eq = &phwi_context->be_eq[0].q;
  667. mcc = &phba->ctrl.mcc_obj.cq;
  668. index = 0;
  669. eqe = queue_tail_node(eq);
  670. if (!eqe)
  671. SE_DEBUG(DBG_LVL_1, "eqe is NULL\n");
  672. num_ioeq_processed = 0;
  673. num_mcceq_processed = 0;
  674. if (blk_iopoll_enabled) {
  675. while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
  676. & EQE_VALID_MASK) {
  677. if (((eqe->dw[offsetof(struct amap_eq_entry,
  678. resource_id) / 32] &
  679. EQE_RESID_MASK) >> 16) == mcc->id) {
  680. spin_lock_irqsave(&phba->isr_lock, flags);
  681. phba->todo_mcc_cq = 1;
  682. spin_unlock_irqrestore(&phba->isr_lock, flags);
  683. num_mcceq_processed++;
  684. } else {
  685. if (!blk_iopoll_sched_prep(&pbe_eq->iopoll))
  686. blk_iopoll_sched(&pbe_eq->iopoll);
  687. num_ioeq_processed++;
  688. }
  689. AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
  690. queue_tail_inc(eq);
  691. eqe = queue_tail_node(eq);
  692. }
  693. if (num_ioeq_processed || num_mcceq_processed) {
  694. if (phba->todo_mcc_cq)
  695. queue_work(phba->wq, &phba->work_cqs);
  696. if ((num_mcceq_processed) && (!num_ioeq_processed))
  697. hwi_ring_eq_db(phba, eq->id, 0,
  698. (num_ioeq_processed +
  699. num_mcceq_processed) , 1, 1);
  700. else
  701. hwi_ring_eq_db(phba, eq->id, 0,
  702. (num_ioeq_processed +
  703. num_mcceq_processed), 0, 1);
  704. return IRQ_HANDLED;
  705. } else
  706. return IRQ_NONE;
  707. } else {
  708. cq = &phwi_context->be_cq[0];
  709. while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
  710. & EQE_VALID_MASK) {
  711. if (((eqe->dw[offsetof(struct amap_eq_entry,
  712. resource_id) / 32] &
  713. EQE_RESID_MASK) >> 16) != cq->id) {
  714. spin_lock_irqsave(&phba->isr_lock, flags);
  715. phba->todo_mcc_cq = 1;
  716. spin_unlock_irqrestore(&phba->isr_lock, flags);
  717. } else {
  718. spin_lock_irqsave(&phba->isr_lock, flags);
  719. phba->todo_cq = 1;
  720. spin_unlock_irqrestore(&phba->isr_lock, flags);
  721. }
  722. AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
  723. queue_tail_inc(eq);
  724. eqe = queue_tail_node(eq);
  725. num_ioeq_processed++;
  726. }
  727. if (phba->todo_cq || phba->todo_mcc_cq)
  728. queue_work(phba->wq, &phba->work_cqs);
  729. if (num_ioeq_processed) {
  730. hwi_ring_eq_db(phba, eq->id, 0,
  731. num_ioeq_processed, 1, 1);
  732. return IRQ_HANDLED;
  733. } else
  734. return IRQ_NONE;
  735. }
  736. }
  737. static int beiscsi_init_irqs(struct beiscsi_hba *phba)
  738. {
  739. struct pci_dev *pcidev = phba->pcidev;
  740. struct hwi_controller *phwi_ctrlr;
  741. struct hwi_context_memory *phwi_context;
  742. int ret, msix_vec, i, j;
  743. phwi_ctrlr = phba->phwi_ctrlr;
  744. phwi_context = phwi_ctrlr->phwi_ctxt;
  745. if (phba->msix_enabled) {
  746. for (i = 0; i < phba->num_cpus; i++) {
  747. phba->msi_name[i] = kzalloc(BEISCSI_MSI_NAME,
  748. GFP_KERNEL);
  749. if (!phba->msi_name[i]) {
  750. ret = -ENOMEM;
  751. goto free_msix_irqs;
  752. }
  753. sprintf(phba->msi_name[i], "beiscsi_%02x_%02x",
  754. phba->shost->host_no, i);
  755. msix_vec = phba->msix_entries[i].vector;
  756. ret = request_irq(msix_vec, be_isr_msix, 0,
  757. phba->msi_name[i],
  758. &phwi_context->be_eq[i]);
  759. if (ret) {
  760. shost_printk(KERN_ERR, phba->shost,
  761. "beiscsi_init_irqs-Failed to"
  762. "register msix for i = %d\n", i);
  763. kfree(phba->msi_name[i]);
  764. goto free_msix_irqs;
  765. }
  766. }
  767. phba->msi_name[i] = kzalloc(BEISCSI_MSI_NAME, GFP_KERNEL);
  768. if (!phba->msi_name[i]) {
  769. ret = -ENOMEM;
  770. goto free_msix_irqs;
  771. }
  772. sprintf(phba->msi_name[i], "beiscsi_mcc_%02x",
  773. phba->shost->host_no);
  774. msix_vec = phba->msix_entries[i].vector;
  775. ret = request_irq(msix_vec, be_isr_mcc, 0, phba->msi_name[i],
  776. &phwi_context->be_eq[i]);
  777. if (ret) {
  778. shost_printk(KERN_ERR, phba->shost, "beiscsi_init_irqs-"
  779. "Failed to register beiscsi_msix_mcc\n");
  780. kfree(phba->msi_name[i]);
  781. goto free_msix_irqs;
  782. }
  783. } else {
  784. ret = request_irq(pcidev->irq, be_isr, IRQF_SHARED,
  785. "beiscsi", phba);
  786. if (ret) {
  787. shost_printk(KERN_ERR, phba->shost, "beiscsi_init_irqs-"
  788. "Failed to register irq\\n");
  789. return ret;
  790. }
  791. }
  792. return 0;
  793. free_msix_irqs:
  794. for (j = i - 1; j >= 0; j--) {
  795. kfree(phba->msi_name[j]);
  796. msix_vec = phba->msix_entries[j].vector;
  797. free_irq(msix_vec, &phwi_context->be_eq[j]);
  798. }
  799. return ret;
  800. }
  801. static void hwi_ring_cq_db(struct beiscsi_hba *phba,
  802. unsigned int id, unsigned int num_processed,
  803. unsigned char rearm, unsigned char event)
  804. {
  805. u32 val = 0;
  806. val |= id & DB_CQ_RING_ID_MASK;
  807. if (rearm)
  808. val |= 1 << DB_CQ_REARM_SHIFT;
  809. val |= num_processed << DB_CQ_NUM_POPPED_SHIFT;
  810. iowrite32(val, phba->db_va + DB_CQ_OFFSET);
  811. }
  812. static unsigned int
  813. beiscsi_process_async_pdu(struct beiscsi_conn *beiscsi_conn,
  814. struct beiscsi_hba *phba,
  815. unsigned short cid,
  816. struct pdu_base *ppdu,
  817. unsigned long pdu_len,
  818. void *pbuffer, unsigned long buf_len)
  819. {
  820. struct iscsi_conn *conn = beiscsi_conn->conn;
  821. struct iscsi_session *session = conn->session;
  822. struct iscsi_task *task;
  823. struct beiscsi_io_task *io_task;
  824. struct iscsi_hdr *login_hdr;
  825. switch (ppdu->dw[offsetof(struct amap_pdu_base, opcode) / 32] &
  826. PDUBASE_OPCODE_MASK) {
  827. case ISCSI_OP_NOOP_IN:
  828. pbuffer = NULL;
  829. buf_len = 0;
  830. break;
  831. case ISCSI_OP_ASYNC_EVENT:
  832. break;
  833. case ISCSI_OP_REJECT:
  834. WARN_ON(!pbuffer);
  835. WARN_ON(!(buf_len == 48));
  836. SE_DEBUG(DBG_LVL_1, "In ISCSI_OP_REJECT\n");
  837. break;
  838. case ISCSI_OP_LOGIN_RSP:
  839. case ISCSI_OP_TEXT_RSP:
  840. task = conn->login_task;
  841. io_task = task->dd_data;
  842. login_hdr = (struct iscsi_hdr *)ppdu;
  843. login_hdr->itt = io_task->libiscsi_itt;
  844. break;
  845. default:
  846. shost_printk(KERN_WARNING, phba->shost,
  847. "Unrecognized opcode 0x%x in async msg\n",
  848. (ppdu->
  849. dw[offsetof(struct amap_pdu_base, opcode) / 32]
  850. & PDUBASE_OPCODE_MASK));
  851. return 1;
  852. }
  853. spin_lock_bh(&session->lock);
  854. __iscsi_complete_pdu(conn, (struct iscsi_hdr *)ppdu, pbuffer, buf_len);
  855. spin_unlock_bh(&session->lock);
  856. return 0;
  857. }
  858. static struct sgl_handle *alloc_io_sgl_handle(struct beiscsi_hba *phba)
  859. {
  860. struct sgl_handle *psgl_handle;
  861. if (phba->io_sgl_hndl_avbl) {
  862. SE_DEBUG(DBG_LVL_8,
  863. "In alloc_io_sgl_handle,io_sgl_alloc_index=%d\n",
  864. phba->io_sgl_alloc_index);
  865. psgl_handle = phba->io_sgl_hndl_base[phba->
  866. io_sgl_alloc_index];
  867. phba->io_sgl_hndl_base[phba->io_sgl_alloc_index] = NULL;
  868. phba->io_sgl_hndl_avbl--;
  869. if (phba->io_sgl_alloc_index == (phba->params.
  870. ios_per_ctrl - 1))
  871. phba->io_sgl_alloc_index = 0;
  872. else
  873. phba->io_sgl_alloc_index++;
  874. } else
  875. psgl_handle = NULL;
  876. return psgl_handle;
  877. }
  878. static void
  879. free_io_sgl_handle(struct beiscsi_hba *phba, struct sgl_handle *psgl_handle)
  880. {
  881. SE_DEBUG(DBG_LVL_8, "In free_,io_sgl_free_index=%d\n",
  882. phba->io_sgl_free_index);
  883. if (phba->io_sgl_hndl_base[phba->io_sgl_free_index]) {
  884. /*
  885. * this can happen if clean_task is called on a task that
  886. * failed in xmit_task or alloc_pdu.
  887. */
  888. SE_DEBUG(DBG_LVL_8,
  889. "Double Free in IO SGL io_sgl_free_index=%d,"
  890. "value there=%p\n", phba->io_sgl_free_index,
  891. phba->io_sgl_hndl_base[phba->io_sgl_free_index]);
  892. return;
  893. }
  894. phba->io_sgl_hndl_base[phba->io_sgl_free_index] = psgl_handle;
  895. phba->io_sgl_hndl_avbl++;
  896. if (phba->io_sgl_free_index == (phba->params.ios_per_ctrl - 1))
  897. phba->io_sgl_free_index = 0;
  898. else
  899. phba->io_sgl_free_index++;
  900. }
  901. /**
  902. * alloc_wrb_handle - To allocate a wrb handle
  903. * @phba: The hba pointer
  904. * @cid: The cid to use for allocation
  905. *
  906. * This happens under session_lock until submission to chip
  907. */
  908. struct wrb_handle *alloc_wrb_handle(struct beiscsi_hba *phba, unsigned int cid)
  909. {
  910. struct hwi_wrb_context *pwrb_context;
  911. struct hwi_controller *phwi_ctrlr;
  912. struct wrb_handle *pwrb_handle, *pwrb_handle_tmp;
  913. phwi_ctrlr = phba->phwi_ctrlr;
  914. pwrb_context = &phwi_ctrlr->wrb_context[cid];
  915. if (pwrb_context->wrb_handles_available >= 2) {
  916. pwrb_handle = pwrb_context->pwrb_handle_base[
  917. pwrb_context->alloc_index];
  918. pwrb_context->wrb_handles_available--;
  919. if (pwrb_context->alloc_index ==
  920. (phba->params.wrbs_per_cxn - 1))
  921. pwrb_context->alloc_index = 0;
  922. else
  923. pwrb_context->alloc_index++;
  924. pwrb_handle_tmp = pwrb_context->pwrb_handle_base[
  925. pwrb_context->alloc_index];
  926. pwrb_handle->nxt_wrb_index = pwrb_handle_tmp->wrb_index;
  927. } else
  928. pwrb_handle = NULL;
  929. return pwrb_handle;
  930. }
  931. /**
  932. * free_wrb_handle - To free the wrb handle back to pool
  933. * @phba: The hba pointer
  934. * @pwrb_context: The context to free from
  935. * @pwrb_handle: The wrb_handle to free
  936. *
  937. * This happens under session_lock until submission to chip
  938. */
  939. static void
  940. free_wrb_handle(struct beiscsi_hba *phba, struct hwi_wrb_context *pwrb_context,
  941. struct wrb_handle *pwrb_handle)
  942. {
  943. pwrb_context->pwrb_handle_base[pwrb_context->free_index] = pwrb_handle;
  944. pwrb_context->wrb_handles_available++;
  945. if (pwrb_context->free_index == (phba->params.wrbs_per_cxn - 1))
  946. pwrb_context->free_index = 0;
  947. else
  948. pwrb_context->free_index++;
  949. SE_DEBUG(DBG_LVL_8,
  950. "FREE WRB: pwrb_handle=%p free_index=0x%x"
  951. "wrb_handles_available=%d\n",
  952. pwrb_handle, pwrb_context->free_index,
  953. pwrb_context->wrb_handles_available);
  954. }
  955. static struct sgl_handle *alloc_mgmt_sgl_handle(struct beiscsi_hba *phba)
  956. {
  957. struct sgl_handle *psgl_handle;
  958. if (phba->eh_sgl_hndl_avbl) {
  959. psgl_handle = phba->eh_sgl_hndl_base[phba->eh_sgl_alloc_index];
  960. phba->eh_sgl_hndl_base[phba->eh_sgl_alloc_index] = NULL;
  961. SE_DEBUG(DBG_LVL_8, "mgmt_sgl_alloc_index=%d=0x%x\n",
  962. phba->eh_sgl_alloc_index, phba->eh_sgl_alloc_index);
  963. phba->eh_sgl_hndl_avbl--;
  964. if (phba->eh_sgl_alloc_index ==
  965. (phba->params.icds_per_ctrl - phba->params.ios_per_ctrl -
  966. 1))
  967. phba->eh_sgl_alloc_index = 0;
  968. else
  969. phba->eh_sgl_alloc_index++;
  970. } else
  971. psgl_handle = NULL;
  972. return psgl_handle;
  973. }
  974. void
  975. free_mgmt_sgl_handle(struct beiscsi_hba *phba, struct sgl_handle *psgl_handle)
  976. {
  977. SE_DEBUG(DBG_LVL_8, "In free_mgmt_sgl_handle,eh_sgl_free_index=%d\n",
  978. phba->eh_sgl_free_index);
  979. if (phba->eh_sgl_hndl_base[phba->eh_sgl_free_index]) {
  980. /*
  981. * this can happen if clean_task is called on a task that
  982. * failed in xmit_task or alloc_pdu.
  983. */
  984. SE_DEBUG(DBG_LVL_8,
  985. "Double Free in eh SGL ,eh_sgl_free_index=%d\n",
  986. phba->eh_sgl_free_index);
  987. return;
  988. }
  989. phba->eh_sgl_hndl_base[phba->eh_sgl_free_index] = psgl_handle;
  990. phba->eh_sgl_hndl_avbl++;
  991. if (phba->eh_sgl_free_index ==
  992. (phba->params.icds_per_ctrl - phba->params.ios_per_ctrl - 1))
  993. phba->eh_sgl_free_index = 0;
  994. else
  995. phba->eh_sgl_free_index++;
  996. }
  997. static void
  998. be_complete_io(struct beiscsi_conn *beiscsi_conn,
  999. struct iscsi_task *task, struct sol_cqe *psol)
  1000. {
  1001. struct beiscsi_io_task *io_task = task->dd_data;
  1002. struct be_status_bhs *sts_bhs =
  1003. (struct be_status_bhs *)io_task->cmd_bhs;
  1004. struct iscsi_conn *conn = beiscsi_conn->conn;
  1005. unsigned char *sense;
  1006. u32 resid = 0, exp_cmdsn, max_cmdsn;
  1007. u8 rsp, status, flags;
  1008. exp_cmdsn = (psol->
  1009. dw[offsetof(struct amap_sol_cqe, i_exp_cmd_sn) / 32]
  1010. & SOL_EXP_CMD_SN_MASK);
  1011. max_cmdsn = ((psol->
  1012. dw[offsetof(struct amap_sol_cqe, i_exp_cmd_sn) / 32]
  1013. & SOL_EXP_CMD_SN_MASK) +
  1014. ((psol->dw[offsetof(struct amap_sol_cqe, i_cmd_wnd)
  1015. / 32] & SOL_CMD_WND_MASK) >> 24) - 1);
  1016. rsp = ((psol->dw[offsetof(struct amap_sol_cqe, i_resp) / 32]
  1017. & SOL_RESP_MASK) >> 16);
  1018. status = ((psol->dw[offsetof(struct amap_sol_cqe, i_sts) / 32]
  1019. & SOL_STS_MASK) >> 8);
  1020. flags = ((psol->dw[offsetof(struct amap_sol_cqe, i_flags) / 32]
  1021. & SOL_FLAGS_MASK) >> 24) | 0x80;
  1022. if (!task->sc) {
  1023. if (io_task->scsi_cmnd)
  1024. scsi_dma_unmap(io_task->scsi_cmnd);
  1025. return;
  1026. }
  1027. task->sc->result = (DID_OK << 16) | status;
  1028. if (rsp != ISCSI_STATUS_CMD_COMPLETED) {
  1029. task->sc->result = DID_ERROR << 16;
  1030. goto unmap;
  1031. }
  1032. /* bidi not initially supported */
  1033. if (flags & (ISCSI_FLAG_CMD_UNDERFLOW | ISCSI_FLAG_CMD_OVERFLOW)) {
  1034. resid = (psol->dw[offsetof(struct amap_sol_cqe, i_res_cnt) /
  1035. 32] & SOL_RES_CNT_MASK);
  1036. if (!status && (flags & ISCSI_FLAG_CMD_OVERFLOW))
  1037. task->sc->result = DID_ERROR << 16;
  1038. if (flags & ISCSI_FLAG_CMD_UNDERFLOW) {
  1039. scsi_set_resid(task->sc, resid);
  1040. if (!status && (scsi_bufflen(task->sc) - resid <
  1041. task->sc->underflow))
  1042. task->sc->result = DID_ERROR << 16;
  1043. }
  1044. }
  1045. if (status == SAM_STAT_CHECK_CONDITION) {
  1046. u16 sense_len;
  1047. unsigned short *slen = (unsigned short *)sts_bhs->sense_info;
  1048. sense = sts_bhs->sense_info + sizeof(unsigned short);
  1049. sense_len = be16_to_cpu(*slen);
  1050. memcpy(task->sc->sense_buffer, sense,
  1051. min_t(u16, sense_len, SCSI_SENSE_BUFFERSIZE));
  1052. }
  1053. if (io_task->cmd_bhs->iscsi_hdr.flags & ISCSI_FLAG_CMD_READ) {
  1054. if (psol->dw[offsetof(struct amap_sol_cqe, i_res_cnt) / 32]
  1055. & SOL_RES_CNT_MASK)
  1056. conn->rxdata_octets += (psol->
  1057. dw[offsetof(struct amap_sol_cqe, i_res_cnt) / 32]
  1058. & SOL_RES_CNT_MASK);
  1059. }
  1060. unmap:
  1061. scsi_dma_unmap(io_task->scsi_cmnd);
  1062. iscsi_complete_scsi_task(task, exp_cmdsn, max_cmdsn);
  1063. }
  1064. static void
  1065. be_complete_logout(struct beiscsi_conn *beiscsi_conn,
  1066. struct iscsi_task *task, struct sol_cqe *psol)
  1067. {
  1068. struct iscsi_logout_rsp *hdr;
  1069. struct beiscsi_io_task *io_task = task->dd_data;
  1070. struct iscsi_conn *conn = beiscsi_conn->conn;
  1071. hdr = (struct iscsi_logout_rsp *)task->hdr;
  1072. hdr->opcode = ISCSI_OP_LOGOUT_RSP;
  1073. hdr->t2wait = 5;
  1074. hdr->t2retain = 0;
  1075. hdr->flags = ((psol->dw[offsetof(struct amap_sol_cqe, i_flags) / 32]
  1076. & SOL_FLAGS_MASK) >> 24) | 0x80;
  1077. hdr->response = (psol->dw[offsetof(struct amap_sol_cqe, i_resp) /
  1078. 32] & SOL_RESP_MASK);
  1079. hdr->exp_cmdsn = cpu_to_be32(psol->
  1080. dw[offsetof(struct amap_sol_cqe, i_exp_cmd_sn) / 32]
  1081. & SOL_EXP_CMD_SN_MASK);
  1082. hdr->max_cmdsn = be32_to_cpu((psol->
  1083. dw[offsetof(struct amap_sol_cqe, i_exp_cmd_sn) / 32]
  1084. & SOL_EXP_CMD_SN_MASK) +
  1085. ((psol->dw[offsetof(struct amap_sol_cqe, i_cmd_wnd)
  1086. / 32] & SOL_CMD_WND_MASK) >> 24) - 1);
  1087. hdr->dlength[0] = 0;
  1088. hdr->dlength[1] = 0;
  1089. hdr->dlength[2] = 0;
  1090. hdr->hlength = 0;
  1091. hdr->itt = io_task->libiscsi_itt;
  1092. __iscsi_complete_pdu(conn, (struct iscsi_hdr *)hdr, NULL, 0);
  1093. }
  1094. static void
  1095. be_complete_tmf(struct beiscsi_conn *beiscsi_conn,
  1096. struct iscsi_task *task, struct sol_cqe *psol)
  1097. {
  1098. struct iscsi_tm_rsp *hdr;
  1099. struct iscsi_conn *conn = beiscsi_conn->conn;
  1100. struct beiscsi_io_task *io_task = task->dd_data;
  1101. hdr = (struct iscsi_tm_rsp *)task->hdr;
  1102. hdr->opcode = ISCSI_OP_SCSI_TMFUNC_RSP;
  1103. hdr->flags = ((psol->dw[offsetof(struct amap_sol_cqe, i_flags) / 32]
  1104. & SOL_FLAGS_MASK) >> 24) | 0x80;
  1105. hdr->response = (psol->dw[offsetof(struct amap_sol_cqe, i_resp) /
  1106. 32] & SOL_RESP_MASK);
  1107. hdr->exp_cmdsn = cpu_to_be32(psol->dw[offsetof(struct amap_sol_cqe,
  1108. i_exp_cmd_sn) / 32] & SOL_EXP_CMD_SN_MASK);
  1109. hdr->max_cmdsn = be32_to_cpu((psol->dw[offsetof(struct amap_sol_cqe,
  1110. i_exp_cmd_sn) / 32] & SOL_EXP_CMD_SN_MASK) +
  1111. ((psol->dw[offsetof(struct amap_sol_cqe, i_cmd_wnd)
  1112. / 32] & SOL_CMD_WND_MASK) >> 24) - 1);
  1113. hdr->itt = io_task->libiscsi_itt;
  1114. __iscsi_complete_pdu(conn, (struct iscsi_hdr *)hdr, NULL, 0);
  1115. }
  1116. static void
  1117. hwi_complete_drvr_msgs(struct beiscsi_conn *beiscsi_conn,
  1118. struct beiscsi_hba *phba, struct sol_cqe *psol)
  1119. {
  1120. struct hwi_wrb_context *pwrb_context;
  1121. struct wrb_handle *pwrb_handle = NULL;
  1122. struct hwi_controller *phwi_ctrlr;
  1123. struct iscsi_task *task;
  1124. struct beiscsi_io_task *io_task;
  1125. struct iscsi_conn *conn = beiscsi_conn->conn;
  1126. struct iscsi_session *session = conn->session;
  1127. phwi_ctrlr = phba->phwi_ctrlr;
  1128. pwrb_context = &phwi_ctrlr->wrb_context[((psol->
  1129. dw[offsetof(struct amap_sol_cqe, cid) / 32] &
  1130. SOL_CID_MASK) >> 6) -
  1131. phba->fw_config.iscsi_cid_start];
  1132. pwrb_handle = pwrb_context->pwrb_handle_basestd[((psol->
  1133. dw[offsetof(struct amap_sol_cqe, wrb_index) /
  1134. 32] & SOL_WRB_INDEX_MASK) >> 16)];
  1135. task = pwrb_handle->pio_handle;
  1136. io_task = task->dd_data;
  1137. spin_lock_bh(&phba->mgmt_sgl_lock);
  1138. free_mgmt_sgl_handle(phba, io_task->psgl_handle);
  1139. spin_unlock_bh(&phba->mgmt_sgl_lock);
  1140. spin_lock_bh(&session->lock);
  1141. free_wrb_handle(phba, pwrb_context, pwrb_handle);
  1142. spin_unlock_bh(&session->lock);
  1143. }
  1144. static void
  1145. be_complete_nopin_resp(struct beiscsi_conn *beiscsi_conn,
  1146. struct iscsi_task *task, struct sol_cqe *psol)
  1147. {
  1148. struct iscsi_nopin *hdr;
  1149. struct iscsi_conn *conn = beiscsi_conn->conn;
  1150. struct beiscsi_io_task *io_task = task->dd_data;
  1151. hdr = (struct iscsi_nopin *)task->hdr;
  1152. hdr->flags = ((psol->dw[offsetof(struct amap_sol_cqe, i_flags) / 32]
  1153. & SOL_FLAGS_MASK) >> 24) | 0x80;
  1154. hdr->exp_cmdsn = cpu_to_be32(psol->dw[offsetof(struct amap_sol_cqe,
  1155. i_exp_cmd_sn) / 32] & SOL_EXP_CMD_SN_MASK);
  1156. hdr->max_cmdsn = be32_to_cpu((psol->dw[offsetof(struct amap_sol_cqe,
  1157. i_exp_cmd_sn) / 32] & SOL_EXP_CMD_SN_MASK) +
  1158. ((psol->dw[offsetof(struct amap_sol_cqe, i_cmd_wnd)
  1159. / 32] & SOL_CMD_WND_MASK) >> 24) - 1);
  1160. hdr->opcode = ISCSI_OP_NOOP_IN;
  1161. hdr->itt = io_task->libiscsi_itt;
  1162. __iscsi_complete_pdu(conn, (struct iscsi_hdr *)hdr, NULL, 0);
  1163. }
  1164. static void hwi_complete_cmd(struct beiscsi_conn *beiscsi_conn,
  1165. struct beiscsi_hba *phba, struct sol_cqe *psol)
  1166. {
  1167. struct hwi_wrb_context *pwrb_context;
  1168. struct wrb_handle *pwrb_handle;
  1169. struct iscsi_wrb *pwrb = NULL;
  1170. struct hwi_controller *phwi_ctrlr;
  1171. struct iscsi_task *task;
  1172. unsigned int type;
  1173. struct iscsi_conn *conn = beiscsi_conn->conn;
  1174. struct iscsi_session *session = conn->session;
  1175. phwi_ctrlr = phba->phwi_ctrlr;
  1176. pwrb_context = &phwi_ctrlr->wrb_context[((psol->dw[offsetof
  1177. (struct amap_sol_cqe, cid) / 32]
  1178. & SOL_CID_MASK) >> 6) -
  1179. phba->fw_config.iscsi_cid_start];
  1180. pwrb_handle = pwrb_context->pwrb_handle_basestd[((psol->
  1181. dw[offsetof(struct amap_sol_cqe, wrb_index) /
  1182. 32] & SOL_WRB_INDEX_MASK) >> 16)];
  1183. task = pwrb_handle->pio_handle;
  1184. pwrb = pwrb_handle->pwrb;
  1185. type = (pwrb->dw[offsetof(struct amap_iscsi_wrb, type) / 32] &
  1186. WRB_TYPE_MASK) >> 28;
  1187. spin_lock_bh(&session->lock);
  1188. switch (type) {
  1189. case HWH_TYPE_IO:
  1190. case HWH_TYPE_IO_RD:
  1191. if ((task->hdr->opcode & ISCSI_OPCODE_MASK) ==
  1192. ISCSI_OP_NOOP_OUT)
  1193. be_complete_nopin_resp(beiscsi_conn, task, psol);
  1194. else
  1195. be_complete_io(beiscsi_conn, task, psol);
  1196. break;
  1197. case HWH_TYPE_LOGOUT:
  1198. if ((task->hdr->opcode & ISCSI_OPCODE_MASK) == ISCSI_OP_LOGOUT)
  1199. be_complete_logout(beiscsi_conn, task, psol);
  1200. else
  1201. be_complete_tmf(beiscsi_conn, task, psol);
  1202. break;
  1203. case HWH_TYPE_LOGIN:
  1204. SE_DEBUG(DBG_LVL_1,
  1205. "\t\t No HWH_TYPE_LOGIN Expected in hwi_complete_cmd"
  1206. "- Solicited path\n");
  1207. break;
  1208. case HWH_TYPE_NOP:
  1209. be_complete_nopin_resp(beiscsi_conn, task, psol);
  1210. break;
  1211. default:
  1212. shost_printk(KERN_WARNING, phba->shost,
  1213. "In hwi_complete_cmd, unknown type = %d"
  1214. "wrb_index 0x%x CID 0x%x\n", type,
  1215. ((psol->dw[offsetof(struct amap_iscsi_wrb,
  1216. type) / 32] & SOL_WRB_INDEX_MASK) >> 16),
  1217. ((psol->dw[offsetof(struct amap_sol_cqe,
  1218. cid) / 32] & SOL_CID_MASK) >> 6));
  1219. break;
  1220. }
  1221. spin_unlock_bh(&session->lock);
  1222. }
  1223. static struct list_head *hwi_get_async_busy_list(struct hwi_async_pdu_context
  1224. *pasync_ctx, unsigned int is_header,
  1225. unsigned int host_write_ptr)
  1226. {
  1227. if (is_header)
  1228. return &pasync_ctx->async_entry[host_write_ptr].
  1229. header_busy_list;
  1230. else
  1231. return &pasync_ctx->async_entry[host_write_ptr].data_busy_list;
  1232. }
  1233. static struct async_pdu_handle *
  1234. hwi_get_async_handle(struct beiscsi_hba *phba,
  1235. struct beiscsi_conn *beiscsi_conn,
  1236. struct hwi_async_pdu_context *pasync_ctx,
  1237. struct i_t_dpdu_cqe *pdpdu_cqe, unsigned int *pcq_index)
  1238. {
  1239. struct be_bus_address phys_addr;
  1240. struct list_head *pbusy_list;
  1241. struct async_pdu_handle *pasync_handle = NULL;
  1242. unsigned char is_header = 0;
  1243. phys_addr.u.a32.address_lo =
  1244. pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe, db_addr_lo) / 32] -
  1245. ((pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe, dpl) / 32]
  1246. & PDUCQE_DPL_MASK) >> 16);
  1247. phys_addr.u.a32.address_hi =
  1248. pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe, db_addr_hi) / 32];
  1249. phys_addr.u.a64.address =
  1250. *((unsigned long long *)(&phys_addr.u.a64.address));
  1251. switch (pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe, code) / 32]
  1252. & PDUCQE_CODE_MASK) {
  1253. case UNSOL_HDR_NOTIFY:
  1254. is_header = 1;
  1255. pbusy_list = hwi_get_async_busy_list(pasync_ctx, 1,
  1256. (pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe,
  1257. index) / 32] & PDUCQE_INDEX_MASK));
  1258. break;
  1259. case UNSOL_DATA_NOTIFY:
  1260. pbusy_list = hwi_get_async_busy_list(pasync_ctx, 0, (pdpdu_cqe->
  1261. dw[offsetof(struct amap_i_t_dpdu_cqe,
  1262. index) / 32] & PDUCQE_INDEX_MASK));
  1263. break;
  1264. default:
  1265. pbusy_list = NULL;
  1266. shost_printk(KERN_WARNING, phba->shost,
  1267. "Unexpected code=%d\n",
  1268. pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe,
  1269. code) / 32] & PDUCQE_CODE_MASK);
  1270. return NULL;
  1271. }
  1272. WARN_ON(list_empty(pbusy_list));
  1273. list_for_each_entry(pasync_handle, pbusy_list, link) {
  1274. if (pasync_handle->pa.u.a64.address == phys_addr.u.a64.address)
  1275. break;
  1276. }
  1277. WARN_ON(!pasync_handle);
  1278. pasync_handle->cri = (unsigned short)beiscsi_conn->beiscsi_conn_cid -
  1279. phba->fw_config.iscsi_cid_start;
  1280. pasync_handle->is_header = is_header;
  1281. pasync_handle->buffer_len = ((pdpdu_cqe->
  1282. dw[offsetof(struct amap_i_t_dpdu_cqe, dpl) / 32]
  1283. & PDUCQE_DPL_MASK) >> 16);
  1284. *pcq_index = (pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe,
  1285. index) / 32] & PDUCQE_INDEX_MASK);
  1286. return pasync_handle;
  1287. }
  1288. static unsigned int
  1289. hwi_update_async_writables(struct hwi_async_pdu_context *pasync_ctx,
  1290. unsigned int is_header, unsigned int cq_index)
  1291. {
  1292. struct list_head *pbusy_list;
  1293. struct async_pdu_handle *pasync_handle;
  1294. unsigned int num_entries, writables = 0;
  1295. unsigned int *pep_read_ptr, *pwritables;
  1296. num_entries = pasync_ctx->num_entries;
  1297. if (is_header) {
  1298. pep_read_ptr = &pasync_ctx->async_header.ep_read_ptr;
  1299. pwritables = &pasync_ctx->async_header.writables;
  1300. } else {
  1301. pep_read_ptr = &pasync_ctx->async_data.ep_read_ptr;
  1302. pwritables = &pasync_ctx->async_data.writables;
  1303. }
  1304. while ((*pep_read_ptr) != cq_index) {
  1305. (*pep_read_ptr)++;
  1306. *pep_read_ptr = (*pep_read_ptr) % num_entries;
  1307. pbusy_list = hwi_get_async_busy_list(pasync_ctx, is_header,
  1308. *pep_read_ptr);
  1309. if (writables == 0)
  1310. WARN_ON(list_empty(pbusy_list));
  1311. if (!list_empty(pbusy_list)) {
  1312. pasync_handle = list_entry(pbusy_list->next,
  1313. struct async_pdu_handle,
  1314. link);
  1315. WARN_ON(!pasync_handle);
  1316. pasync_handle->consumed = 1;
  1317. }
  1318. writables++;
  1319. }
  1320. if (!writables) {
  1321. SE_DEBUG(DBG_LVL_1,
  1322. "Duplicate notification received - index 0x%x!!\n",
  1323. cq_index);
  1324. WARN_ON(1);
  1325. }
  1326. *pwritables = *pwritables + writables;
  1327. return 0;
  1328. }
  1329. static unsigned int hwi_free_async_msg(struct beiscsi_hba *phba,
  1330. unsigned int cri)
  1331. {
  1332. struct hwi_controller *phwi_ctrlr;
  1333. struct hwi_async_pdu_context *pasync_ctx;
  1334. struct async_pdu_handle *pasync_handle, *tmp_handle;
  1335. struct list_head *plist;
  1336. unsigned int i = 0;
  1337. phwi_ctrlr = phba->phwi_ctrlr;
  1338. pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr);
  1339. plist = &pasync_ctx->async_entry[cri].wait_queue.list;
  1340. list_for_each_entry_safe(pasync_handle, tmp_handle, plist, link) {
  1341. list_del(&pasync_handle->link);
  1342. if (i == 0) {
  1343. list_add_tail(&pasync_handle->link,
  1344. &pasync_ctx->async_header.free_list);
  1345. pasync_ctx->async_header.free_entries++;
  1346. i++;
  1347. } else {
  1348. list_add_tail(&pasync_handle->link,
  1349. &pasync_ctx->async_data.free_list);
  1350. pasync_ctx->async_data.free_entries++;
  1351. i++;
  1352. }
  1353. }
  1354. INIT_LIST_HEAD(&pasync_ctx->async_entry[cri].wait_queue.list);
  1355. pasync_ctx->async_entry[cri].wait_queue.hdr_received = 0;
  1356. pasync_ctx->async_entry[cri].wait_queue.bytes_received = 0;
  1357. return 0;
  1358. }
  1359. static struct phys_addr *
  1360. hwi_get_ring_address(struct hwi_async_pdu_context *pasync_ctx,
  1361. unsigned int is_header, unsigned int host_write_ptr)
  1362. {
  1363. struct phys_addr *pasync_sge = NULL;
  1364. if (is_header)
  1365. pasync_sge = pasync_ctx->async_header.ring_base;
  1366. else
  1367. pasync_sge = pasync_ctx->async_data.ring_base;
  1368. return pasync_sge + host_write_ptr;
  1369. }
  1370. static void hwi_post_async_buffers(struct beiscsi_hba *phba,
  1371. unsigned int is_header)
  1372. {
  1373. struct hwi_controller *phwi_ctrlr;
  1374. struct hwi_async_pdu_context *pasync_ctx;
  1375. struct async_pdu_handle *pasync_handle;
  1376. struct list_head *pfree_link, *pbusy_list;
  1377. struct phys_addr *pasync_sge;
  1378. unsigned int ring_id, num_entries;
  1379. unsigned int host_write_num;
  1380. unsigned int writables;
  1381. unsigned int i = 0;
  1382. u32 doorbell = 0;
  1383. phwi_ctrlr = phba->phwi_ctrlr;
  1384. pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr);
  1385. num_entries = pasync_ctx->num_entries;
  1386. if (is_header) {
  1387. writables = min(pasync_ctx->async_header.writables,
  1388. pasync_ctx->async_header.free_entries);
  1389. pfree_link = pasync_ctx->async_header.free_list.next;
  1390. host_write_num = pasync_ctx->async_header.host_write_ptr;
  1391. ring_id = phwi_ctrlr->default_pdu_hdr.id;
  1392. } else {
  1393. writables = min(pasync_ctx->async_data.writables,
  1394. pasync_ctx->async_data.free_entries);
  1395. pfree_link = pasync_ctx->async_data.free_list.next;
  1396. host_write_num = pasync_ctx->async_data.host_write_ptr;
  1397. ring_id = phwi_ctrlr->default_pdu_data.id;
  1398. }
  1399. writables = (writables / 8) * 8;
  1400. if (writables) {
  1401. for (i = 0; i < writables; i++) {
  1402. pbusy_list =
  1403. hwi_get_async_busy_list(pasync_ctx, is_header,
  1404. host_write_num);
  1405. pasync_handle =
  1406. list_entry(pfree_link, struct async_pdu_handle,
  1407. link);
  1408. WARN_ON(!pasync_handle);
  1409. pasync_handle->consumed = 0;
  1410. pfree_link = pfree_link->next;
  1411. pasync_sge = hwi_get_ring_address(pasync_ctx,
  1412. is_header, host_write_num);
  1413. pasync_sge->hi = pasync_handle->pa.u.a32.address_lo;
  1414. pasync_sge->lo = pasync_handle->pa.u.a32.address_hi;
  1415. list_move(&pasync_handle->link, pbusy_list);
  1416. host_write_num++;
  1417. host_write_num = host_write_num % num_entries;
  1418. }
  1419. if (is_header) {
  1420. pasync_ctx->async_header.host_write_ptr =
  1421. host_write_num;
  1422. pasync_ctx->async_header.free_entries -= writables;
  1423. pasync_ctx->async_header.writables -= writables;
  1424. pasync_ctx->async_header.busy_entries += writables;
  1425. } else {
  1426. pasync_ctx->async_data.host_write_ptr = host_write_num;
  1427. pasync_ctx->async_data.free_entries -= writables;
  1428. pasync_ctx->async_data.writables -= writables;
  1429. pasync_ctx->async_data.busy_entries += writables;
  1430. }
  1431. doorbell |= ring_id & DB_DEF_PDU_RING_ID_MASK;
  1432. doorbell |= 1 << DB_DEF_PDU_REARM_SHIFT;
  1433. doorbell |= 0 << DB_DEF_PDU_EVENT_SHIFT;
  1434. doorbell |= (writables & DB_DEF_PDU_CQPROC_MASK)
  1435. << DB_DEF_PDU_CQPROC_SHIFT;
  1436. iowrite32(doorbell, phba->db_va + DB_RXULP0_OFFSET);
  1437. }
  1438. }
  1439. static void hwi_flush_default_pdu_buffer(struct beiscsi_hba *phba,
  1440. struct beiscsi_conn *beiscsi_conn,
  1441. struct i_t_dpdu_cqe *pdpdu_cqe)
  1442. {
  1443. struct hwi_controller *phwi_ctrlr;
  1444. struct hwi_async_pdu_context *pasync_ctx;
  1445. struct async_pdu_handle *pasync_handle = NULL;
  1446. unsigned int cq_index = -1;
  1447. phwi_ctrlr = phba->phwi_ctrlr;
  1448. pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr);
  1449. pasync_handle = hwi_get_async_handle(phba, beiscsi_conn, pasync_ctx,
  1450. pdpdu_cqe, &cq_index);
  1451. BUG_ON(pasync_handle->is_header != 0);
  1452. if (pasync_handle->consumed == 0)
  1453. hwi_update_async_writables(pasync_ctx, pasync_handle->is_header,
  1454. cq_index);
  1455. hwi_free_async_msg(phba, pasync_handle->cri);
  1456. hwi_post_async_buffers(phba, pasync_handle->is_header);
  1457. }
  1458. static unsigned int
  1459. hwi_fwd_async_msg(struct beiscsi_conn *beiscsi_conn,
  1460. struct beiscsi_hba *phba,
  1461. struct hwi_async_pdu_context *pasync_ctx, unsigned short cri)
  1462. {
  1463. struct list_head *plist;
  1464. struct async_pdu_handle *pasync_handle;
  1465. void *phdr = NULL;
  1466. unsigned int hdr_len = 0, buf_len = 0;
  1467. unsigned int status, index = 0, offset = 0;
  1468. void *pfirst_buffer = NULL;
  1469. unsigned int num_buf = 0;
  1470. plist = &pasync_ctx->async_entry[cri].wait_queue.list;
  1471. list_for_each_entry(pasync_handle, plist, link) {
  1472. if (index == 0) {
  1473. phdr = pasync_handle->pbuffer;
  1474. hdr_len = pasync_handle->buffer_len;
  1475. } else {
  1476. buf_len = pasync_handle->buffer_len;
  1477. if (!num_buf) {
  1478. pfirst_buffer = pasync_handle->pbuffer;
  1479. num_buf++;
  1480. }
  1481. memcpy(pfirst_buffer + offset,
  1482. pasync_handle->pbuffer, buf_len);
  1483. offset += buf_len;
  1484. }
  1485. index++;
  1486. }
  1487. status = beiscsi_process_async_pdu(beiscsi_conn, phba,
  1488. (beiscsi_conn->beiscsi_conn_cid -
  1489. phba->fw_config.iscsi_cid_start),
  1490. phdr, hdr_len, pfirst_buffer,
  1491. offset);
  1492. if (status == 0)
  1493. hwi_free_async_msg(phba, cri);
  1494. return 0;
  1495. }
  1496. static unsigned int
  1497. hwi_gather_async_pdu(struct beiscsi_conn *beiscsi_conn,
  1498. struct beiscsi_hba *phba,
  1499. struct async_pdu_handle *pasync_handle)
  1500. {
  1501. struct hwi_async_pdu_context *pasync_ctx;
  1502. struct hwi_controller *phwi_ctrlr;
  1503. unsigned int bytes_needed = 0, status = 0;
  1504. unsigned short cri = pasync_handle->cri;
  1505. struct pdu_base *ppdu;
  1506. phwi_ctrlr = phba->phwi_ctrlr;
  1507. pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr);
  1508. list_del(&pasync_handle->link);
  1509. if (pasync_handle->is_header) {
  1510. pasync_ctx->async_header.busy_entries--;
  1511. if (pasync_ctx->async_entry[cri].wait_queue.hdr_received) {
  1512. hwi_free_async_msg(phba, cri);
  1513. BUG();
  1514. }
  1515. pasync_ctx->async_entry[cri].wait_queue.bytes_received = 0;
  1516. pasync_ctx->async_entry[cri].wait_queue.hdr_received = 1;
  1517. pasync_ctx->async_entry[cri].wait_queue.hdr_len =
  1518. (unsigned short)pasync_handle->buffer_len;
  1519. list_add_tail(&pasync_handle->link,
  1520. &pasync_ctx->async_entry[cri].wait_queue.list);
  1521. ppdu = pasync_handle->pbuffer;
  1522. bytes_needed = ((((ppdu->dw[offsetof(struct amap_pdu_base,
  1523. data_len_hi) / 32] & PDUBASE_DATALENHI_MASK) << 8) &
  1524. 0xFFFF0000) | ((be16_to_cpu((ppdu->
  1525. dw[offsetof(struct amap_pdu_base, data_len_lo) / 32]
  1526. & PDUBASE_DATALENLO_MASK) >> 16)) & 0x0000FFFF));
  1527. if (status == 0) {
  1528. pasync_ctx->async_entry[cri].wait_queue.bytes_needed =
  1529. bytes_needed;
  1530. if (bytes_needed == 0)
  1531. status = hwi_fwd_async_msg(beiscsi_conn, phba,
  1532. pasync_ctx, cri);
  1533. }
  1534. } else {
  1535. pasync_ctx->async_data.busy_entries--;
  1536. if (pasync_ctx->async_entry[cri].wait_queue.hdr_received) {
  1537. list_add_tail(&pasync_handle->link,
  1538. &pasync_ctx->async_entry[cri].wait_queue.
  1539. list);
  1540. pasync_ctx->async_entry[cri].wait_queue.
  1541. bytes_received +=
  1542. (unsigned short)pasync_handle->buffer_len;
  1543. if (pasync_ctx->async_entry[cri].wait_queue.
  1544. bytes_received >=
  1545. pasync_ctx->async_entry[cri].wait_queue.
  1546. bytes_needed)
  1547. status = hwi_fwd_async_msg(beiscsi_conn, phba,
  1548. pasync_ctx, cri);
  1549. }
  1550. }
  1551. return status;
  1552. }
  1553. static void hwi_process_default_pdu_ring(struct beiscsi_conn *beiscsi_conn,
  1554. struct beiscsi_hba *phba,
  1555. struct i_t_dpdu_cqe *pdpdu_cqe)
  1556. {
  1557. struct hwi_controller *phwi_ctrlr;
  1558. struct hwi_async_pdu_context *pasync_ctx;
  1559. struct async_pdu_handle *pasync_handle = NULL;
  1560. unsigned int cq_index = -1;
  1561. phwi_ctrlr = phba->phwi_ctrlr;
  1562. pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr);
  1563. pasync_handle = hwi_get_async_handle(phba, beiscsi_conn, pasync_ctx,
  1564. pdpdu_cqe, &cq_index);
  1565. if (pasync_handle->consumed == 0)
  1566. hwi_update_async_writables(pasync_ctx, pasync_handle->is_header,
  1567. cq_index);
  1568. hwi_gather_async_pdu(beiscsi_conn, phba, pasync_handle);
  1569. hwi_post_async_buffers(phba, pasync_handle->is_header);
  1570. }
  1571. static void beiscsi_process_mcc_isr(struct beiscsi_hba *phba)
  1572. {
  1573. struct be_queue_info *mcc_cq;
  1574. struct be_mcc_compl *mcc_compl;
  1575. unsigned int num_processed = 0;
  1576. mcc_cq = &phba->ctrl.mcc_obj.cq;
  1577. mcc_compl = queue_tail_node(mcc_cq);
  1578. mcc_compl->flags = le32_to_cpu(mcc_compl->flags);
  1579. while (mcc_compl->flags & CQE_FLAGS_VALID_MASK) {
  1580. if (num_processed >= 32) {
  1581. hwi_ring_cq_db(phba, mcc_cq->id,
  1582. num_processed, 0, 0);
  1583. num_processed = 0;
  1584. }
  1585. if (mcc_compl->flags & CQE_FLAGS_ASYNC_MASK) {
  1586. /* Interpret flags as an async trailer */
  1587. if (is_link_state_evt(mcc_compl->flags))
  1588. /* Interpret compl as a async link evt */
  1589. beiscsi_async_link_state_process(phba,
  1590. (struct be_async_event_link_state *) mcc_compl);
  1591. else
  1592. SE_DEBUG(DBG_LVL_1,
  1593. " Unsupported Async Event, flags"
  1594. " = 0x%08x\n", mcc_compl->flags);
  1595. } else if (mcc_compl->flags & CQE_FLAGS_COMPLETED_MASK) {
  1596. be_mcc_compl_process_isr(&phba->ctrl, mcc_compl);
  1597. atomic_dec(&phba->ctrl.mcc_obj.q.used);
  1598. }
  1599. mcc_compl->flags = 0;
  1600. queue_tail_inc(mcc_cq);
  1601. mcc_compl = queue_tail_node(mcc_cq);
  1602. mcc_compl->flags = le32_to_cpu(mcc_compl->flags);
  1603. num_processed++;
  1604. }
  1605. if (num_processed > 0)
  1606. hwi_ring_cq_db(phba, mcc_cq->id, num_processed, 1, 0);
  1607. }
  1608. static unsigned int beiscsi_process_cq(struct be_eq_obj *pbe_eq)
  1609. {
  1610. struct be_queue_info *cq;
  1611. struct sol_cqe *sol;
  1612. struct dmsg_cqe *dmsg;
  1613. unsigned int num_processed = 0;
  1614. unsigned int tot_nump = 0;
  1615. struct beiscsi_conn *beiscsi_conn;
  1616. struct beiscsi_endpoint *beiscsi_ep;
  1617. struct iscsi_endpoint *ep;
  1618. struct beiscsi_hba *phba;
  1619. cq = pbe_eq->cq;
  1620. sol = queue_tail_node(cq);
  1621. phba = pbe_eq->phba;
  1622. while (sol->dw[offsetof(struct amap_sol_cqe, valid) / 32] &
  1623. CQE_VALID_MASK) {
  1624. be_dws_le_to_cpu(sol, sizeof(struct sol_cqe));
  1625. ep = phba->ep_array[(u32) ((sol->
  1626. dw[offsetof(struct amap_sol_cqe, cid) / 32] &
  1627. SOL_CID_MASK) >> 6) -
  1628. phba->fw_config.iscsi_cid_start];
  1629. beiscsi_ep = ep->dd_data;
  1630. beiscsi_conn = beiscsi_ep->conn;
  1631. if (num_processed >= 32) {
  1632. hwi_ring_cq_db(phba, cq->id,
  1633. num_processed, 0, 0);
  1634. tot_nump += num_processed;
  1635. num_processed = 0;
  1636. }
  1637. switch ((u32) sol->dw[offsetof(struct amap_sol_cqe, code) /
  1638. 32] & CQE_CODE_MASK) {
  1639. case SOL_CMD_COMPLETE:
  1640. hwi_complete_cmd(beiscsi_conn, phba, sol);
  1641. break;
  1642. case DRIVERMSG_NOTIFY:
  1643. SE_DEBUG(DBG_LVL_8, "Received DRIVERMSG_NOTIFY\n");
  1644. dmsg = (struct dmsg_cqe *)sol;
  1645. hwi_complete_drvr_msgs(beiscsi_conn, phba, sol);
  1646. break;
  1647. case UNSOL_HDR_NOTIFY:
  1648. SE_DEBUG(DBG_LVL_8, "Received UNSOL_HDR_ NOTIFY\n");
  1649. hwi_process_default_pdu_ring(beiscsi_conn, phba,
  1650. (struct i_t_dpdu_cqe *)sol);
  1651. break;
  1652. case UNSOL_DATA_NOTIFY:
  1653. SE_DEBUG(DBG_LVL_8, "Received UNSOL_DATA_NOTIFY\n");
  1654. hwi_process_default_pdu_ring(beiscsi_conn, phba,
  1655. (struct i_t_dpdu_cqe *)sol);
  1656. break;
  1657. case CXN_INVALIDATE_INDEX_NOTIFY:
  1658. case CMD_INVALIDATED_NOTIFY:
  1659. case CXN_INVALIDATE_NOTIFY:
  1660. SE_DEBUG(DBG_LVL_1,
  1661. "Ignoring CQ Error notification for cmd/cxn"
  1662. "invalidate\n");
  1663. break;
  1664. case SOL_CMD_KILLED_DATA_DIGEST_ERR:
  1665. case CMD_KILLED_INVALID_STATSN_RCVD:
  1666. case CMD_KILLED_INVALID_R2T_RCVD:
  1667. case CMD_CXN_KILLED_LUN_INVALID:
  1668. case CMD_CXN_KILLED_ICD_INVALID:
  1669. case CMD_CXN_KILLED_ITT_INVALID:
  1670. case CMD_CXN_KILLED_SEQ_OUTOFORDER:
  1671. case CMD_CXN_KILLED_INVALID_DATASN_RCVD:
  1672. SE_DEBUG(DBG_LVL_1,
  1673. "CQ Error notification for cmd.. "
  1674. "code %d cid 0x%x\n",
  1675. sol->dw[offsetof(struct amap_sol_cqe, code) /
  1676. 32] & CQE_CODE_MASK,
  1677. (sol->dw[offsetof(struct amap_sol_cqe, cid) /
  1678. 32] & SOL_CID_MASK));
  1679. break;
  1680. case UNSOL_DATA_DIGEST_ERROR_NOTIFY:
  1681. SE_DEBUG(DBG_LVL_1,
  1682. "Digest error on def pdu ring, dropping..\n");
  1683. hwi_flush_default_pdu_buffer(phba, beiscsi_conn,
  1684. (struct i_t_dpdu_cqe *) sol);
  1685. break;
  1686. case CXN_KILLED_PDU_SIZE_EXCEEDS_DSL:
  1687. case CXN_KILLED_BURST_LEN_MISMATCH:
  1688. case CXN_KILLED_AHS_RCVD:
  1689. case CXN_KILLED_HDR_DIGEST_ERR:
  1690. case CXN_KILLED_UNKNOWN_HDR:
  1691. case CXN_KILLED_STALE_ITT_TTT_RCVD:
  1692. case CXN_KILLED_INVALID_ITT_TTT_RCVD:
  1693. case CXN_KILLED_TIMED_OUT:
  1694. case CXN_KILLED_FIN_RCVD:
  1695. case CXN_KILLED_BAD_UNSOL_PDU_RCVD:
  1696. case CXN_KILLED_BAD_WRB_INDEX_ERROR:
  1697. case CXN_KILLED_OVER_RUN_RESIDUAL:
  1698. case CXN_KILLED_UNDER_RUN_RESIDUAL:
  1699. case CXN_KILLED_CMND_DATA_NOT_ON_SAME_CONN:
  1700. SE_DEBUG(DBG_LVL_1, "CQ Error %d, reset CID "
  1701. "0x%x...\n",
  1702. sol->dw[offsetof(struct amap_sol_cqe, code) /
  1703. 32] & CQE_CODE_MASK,
  1704. (sol->dw[offsetof(struct amap_sol_cqe, cid) /
  1705. 32] & CQE_CID_MASK));
  1706. iscsi_conn_failure(beiscsi_conn->conn,
  1707. ISCSI_ERR_CONN_FAILED);
  1708. break;
  1709. case CXN_KILLED_RST_SENT:
  1710. case CXN_KILLED_RST_RCVD:
  1711. SE_DEBUG(DBG_LVL_1, "CQ Error %d, reset"
  1712. "received/sent on CID 0x%x...\n",
  1713. sol->dw[offsetof(struct amap_sol_cqe, code) /
  1714. 32] & CQE_CODE_MASK,
  1715. (sol->dw[offsetof(struct amap_sol_cqe, cid) /
  1716. 32] & CQE_CID_MASK));
  1717. iscsi_conn_failure(beiscsi_conn->conn,
  1718. ISCSI_ERR_CONN_FAILED);
  1719. break;
  1720. default:
  1721. SE_DEBUG(DBG_LVL_1, "CQ Error Invalid code= %d "
  1722. "received on CID 0x%x...\n",
  1723. sol->dw[offsetof(struct amap_sol_cqe, code) /
  1724. 32] & CQE_CODE_MASK,
  1725. (sol->dw[offsetof(struct amap_sol_cqe, cid) /
  1726. 32] & CQE_CID_MASK));
  1727. break;
  1728. }
  1729. AMAP_SET_BITS(struct amap_sol_cqe, valid, sol, 0);
  1730. queue_tail_inc(cq);
  1731. sol = queue_tail_node(cq);
  1732. num_processed++;
  1733. }
  1734. if (num_processed > 0) {
  1735. tot_nump += num_processed;
  1736. hwi_ring_cq_db(phba, cq->id, num_processed, 1, 0);
  1737. }
  1738. return tot_nump;
  1739. }
  1740. void beiscsi_process_all_cqs(struct work_struct *work)
  1741. {
  1742. unsigned long flags;
  1743. struct hwi_controller *phwi_ctrlr;
  1744. struct hwi_context_memory *phwi_context;
  1745. struct be_eq_obj *pbe_eq;
  1746. struct beiscsi_hba *phba =
  1747. container_of(work, struct beiscsi_hba, work_cqs);
  1748. phwi_ctrlr = phba->phwi_ctrlr;
  1749. phwi_context = phwi_ctrlr->phwi_ctxt;
  1750. if (phba->msix_enabled)
  1751. pbe_eq = &phwi_context->be_eq[phba->num_cpus];
  1752. else
  1753. pbe_eq = &phwi_context->be_eq[0];
  1754. if (phba->todo_mcc_cq) {
  1755. spin_lock_irqsave(&phba->isr_lock, flags);
  1756. phba->todo_mcc_cq = 0;
  1757. spin_unlock_irqrestore(&phba->isr_lock, flags);
  1758. beiscsi_process_mcc_isr(phba);
  1759. }
  1760. if (phba->todo_cq) {
  1761. spin_lock_irqsave(&phba->isr_lock, flags);
  1762. phba->todo_cq = 0;
  1763. spin_unlock_irqrestore(&phba->isr_lock, flags);
  1764. beiscsi_process_cq(pbe_eq);
  1765. }
  1766. }
  1767. static int be_iopoll(struct blk_iopoll *iop, int budget)
  1768. {
  1769. static unsigned int ret;
  1770. struct beiscsi_hba *phba;
  1771. struct be_eq_obj *pbe_eq;
  1772. pbe_eq = container_of(iop, struct be_eq_obj, iopoll);
  1773. ret = beiscsi_process_cq(pbe_eq);
  1774. if (ret < budget) {
  1775. phba = pbe_eq->phba;
  1776. blk_iopoll_complete(iop);
  1777. SE_DEBUG(DBG_LVL_8, "rearm pbe_eq->q.id =%d\n", pbe_eq->q.id);
  1778. hwi_ring_eq_db(phba, pbe_eq->q.id, 0, 0, 1, 1);
  1779. }
  1780. return ret;
  1781. }
  1782. static void
  1783. hwi_write_sgl(struct iscsi_wrb *pwrb, struct scatterlist *sg,
  1784. unsigned int num_sg, struct beiscsi_io_task *io_task)
  1785. {
  1786. struct iscsi_sge *psgl;
  1787. unsigned int sg_len, index;
  1788. unsigned int sge_len = 0;
  1789. unsigned long long addr;
  1790. struct scatterlist *l_sg;
  1791. unsigned int offset;
  1792. AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_lo, pwrb,
  1793. io_task->bhs_pa.u.a32.address_lo);
  1794. AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_hi, pwrb,
  1795. io_task->bhs_pa.u.a32.address_hi);
  1796. l_sg = sg;
  1797. for (index = 0; (index < num_sg) && (index < 2); index++,
  1798. sg = sg_next(sg)) {
  1799. if (index == 0) {
  1800. sg_len = sg_dma_len(sg);
  1801. addr = (u64) sg_dma_address(sg);
  1802. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_lo, pwrb,
  1803. ((u32)(addr & 0xFFFFFFFF)));
  1804. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_hi, pwrb,
  1805. ((u32)(addr >> 32)));
  1806. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_len, pwrb,
  1807. sg_len);
  1808. sge_len = sg_len;
  1809. } else {
  1810. AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_r2t_offset,
  1811. pwrb, sge_len);
  1812. sg_len = sg_dma_len(sg);
  1813. addr = (u64) sg_dma_address(sg);
  1814. AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_addr_lo, pwrb,
  1815. ((u32)(addr & 0xFFFFFFFF)));
  1816. AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_addr_hi, pwrb,
  1817. ((u32)(addr >> 32)));
  1818. AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_len, pwrb,
  1819. sg_len);
  1820. }
  1821. }
  1822. psgl = (struct iscsi_sge *)io_task->psgl_handle->pfrag;
  1823. memset(psgl, 0, sizeof(*psgl) * BE2_SGE);
  1824. AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, io_task->bhs_len - 2);
  1825. AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
  1826. io_task->bhs_pa.u.a32.address_hi);
  1827. AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
  1828. io_task->bhs_pa.u.a32.address_lo);
  1829. if (num_sg == 1) {
  1830. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb,
  1831. 1);
  1832. AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_last, pwrb,
  1833. 0);
  1834. } else if (num_sg == 2) {
  1835. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb,
  1836. 0);
  1837. AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_last, pwrb,
  1838. 1);
  1839. } else {
  1840. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb,
  1841. 0);
  1842. AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_last, pwrb,
  1843. 0);
  1844. }
  1845. sg = l_sg;
  1846. psgl++;
  1847. psgl++;
  1848. offset = 0;
  1849. for (index = 0; index < num_sg; index++, sg = sg_next(sg), psgl++) {
  1850. sg_len = sg_dma_len(sg);
  1851. addr = (u64) sg_dma_address(sg);
  1852. AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
  1853. (addr & 0xFFFFFFFF));
  1854. AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
  1855. (addr >> 32));
  1856. AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, sg_len);
  1857. AMAP_SET_BITS(struct amap_iscsi_sge, sge_offset, psgl, offset);
  1858. AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 0);
  1859. offset += sg_len;
  1860. }
  1861. psgl--;
  1862. AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 1);
  1863. }
  1864. static void hwi_write_buffer(struct iscsi_wrb *pwrb, struct iscsi_task *task)
  1865. {
  1866. struct iscsi_sge *psgl;
  1867. unsigned long long addr;
  1868. struct beiscsi_io_task *io_task = task->dd_data;
  1869. struct beiscsi_conn *beiscsi_conn = io_task->conn;
  1870. struct beiscsi_hba *phba = beiscsi_conn->phba;
  1871. io_task->bhs_len = sizeof(struct be_nonio_bhs) - 2;
  1872. AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_lo, pwrb,
  1873. io_task->bhs_pa.u.a32.address_lo);
  1874. AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_hi, pwrb,
  1875. io_task->bhs_pa.u.a32.address_hi);
  1876. if (task->data) {
  1877. if (task->data_count) {
  1878. AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 1);
  1879. addr = (u64) pci_map_single(phba->pcidev,
  1880. task->data,
  1881. task->data_count, 1);
  1882. } else {
  1883. AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 0);
  1884. addr = 0;
  1885. }
  1886. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_lo, pwrb,
  1887. ((u32)(addr & 0xFFFFFFFF)));
  1888. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_hi, pwrb,
  1889. ((u32)(addr >> 32)));
  1890. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_len, pwrb,
  1891. task->data_count);
  1892. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb, 1);
  1893. } else {
  1894. AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 0);
  1895. addr = 0;
  1896. }
  1897. psgl = (struct iscsi_sge *)io_task->psgl_handle->pfrag;
  1898. AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, io_task->bhs_len);
  1899. AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
  1900. io_task->bhs_pa.u.a32.address_hi);
  1901. AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
  1902. io_task->bhs_pa.u.a32.address_lo);
  1903. if (task->data) {
  1904. psgl++;
  1905. AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl, 0);
  1906. AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl, 0);
  1907. AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, 0);
  1908. AMAP_SET_BITS(struct amap_iscsi_sge, sge_offset, psgl, 0);
  1909. AMAP_SET_BITS(struct amap_iscsi_sge, rsvd0, psgl, 0);
  1910. AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 0);
  1911. psgl++;
  1912. if (task->data) {
  1913. AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
  1914. ((u32)(addr & 0xFFFFFFFF)));
  1915. AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
  1916. ((u32)(addr >> 32)));
  1917. }
  1918. AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, 0x106);
  1919. }
  1920. AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 1);
  1921. }
  1922. static void beiscsi_find_mem_req(struct beiscsi_hba *phba)
  1923. {
  1924. unsigned int num_cq_pages, num_async_pdu_buf_pages;
  1925. unsigned int num_async_pdu_data_pages, wrb_sz_per_cxn;
  1926. unsigned int num_async_pdu_buf_sgl_pages, num_async_pdu_data_sgl_pages;
  1927. num_cq_pages = PAGES_REQUIRED(phba->params.num_cq_entries * \
  1928. sizeof(struct sol_cqe));
  1929. num_async_pdu_buf_pages =
  1930. PAGES_REQUIRED(phba->params.asyncpdus_per_ctrl * \
  1931. phba->params.defpdu_hdr_sz);
  1932. num_async_pdu_buf_sgl_pages =
  1933. PAGES_REQUIRED(phba->params.asyncpdus_per_ctrl * \
  1934. sizeof(struct phys_addr));
  1935. num_async_pdu_data_pages =
  1936. PAGES_REQUIRED(phba->params.asyncpdus_per_ctrl * \
  1937. phba->params.defpdu_data_sz);
  1938. num_async_pdu_data_sgl_pages =
  1939. PAGES_REQUIRED(phba->params.asyncpdus_per_ctrl * \
  1940. sizeof(struct phys_addr));
  1941. phba->params.hwi_ws_sz = sizeof(struct hwi_controller);
  1942. phba->mem_req[ISCSI_MEM_GLOBAL_HEADER] = 2 *
  1943. BE_ISCSI_PDU_HEADER_SIZE;
  1944. phba->mem_req[HWI_MEM_ADDN_CONTEXT] =
  1945. sizeof(struct hwi_context_memory);
  1946. phba->mem_req[HWI_MEM_WRB] = sizeof(struct iscsi_wrb)
  1947. * (phba->params.wrbs_per_cxn)
  1948. * phba->params.cxns_per_ctrl;
  1949. wrb_sz_per_cxn = sizeof(struct wrb_handle) *
  1950. (phba->params.wrbs_per_cxn);
  1951. phba->mem_req[HWI_MEM_WRBH] = roundup_pow_of_two((wrb_sz_per_cxn) *
  1952. phba->params.cxns_per_ctrl);
  1953. phba->mem_req[HWI_MEM_SGLH] = sizeof(struct sgl_handle) *
  1954. phba->params.icds_per_ctrl;
  1955. phba->mem_req[HWI_MEM_SGE] = sizeof(struct iscsi_sge) *
  1956. phba->params.num_sge_per_io * phba->params.icds_per_ctrl;
  1957. phba->mem_req[HWI_MEM_ASYNC_HEADER_BUF] =
  1958. num_async_pdu_buf_pages * PAGE_SIZE;
  1959. phba->mem_req[HWI_MEM_ASYNC_DATA_BUF] =
  1960. num_async_pdu_data_pages * PAGE_SIZE;
  1961. phba->mem_req[HWI_MEM_ASYNC_HEADER_RING] =
  1962. num_async_pdu_buf_sgl_pages * PAGE_SIZE;
  1963. phba->mem_req[HWI_MEM_ASYNC_DATA_RING] =
  1964. num_async_pdu_data_sgl_pages * PAGE_SIZE;
  1965. phba->mem_req[HWI_MEM_ASYNC_HEADER_HANDLE] =
  1966. phba->params.asyncpdus_per_ctrl *
  1967. sizeof(struct async_pdu_handle);
  1968. phba->mem_req[HWI_MEM_ASYNC_DATA_HANDLE] =
  1969. phba->params.asyncpdus_per_ctrl *
  1970. sizeof(struct async_pdu_handle);
  1971. phba->mem_req[HWI_MEM_ASYNC_PDU_CONTEXT] =
  1972. sizeof(struct hwi_async_pdu_context) +
  1973. (phba->params.cxns_per_ctrl * sizeof(struct hwi_async_entry));
  1974. }
  1975. static int beiscsi_alloc_mem(struct beiscsi_hba *phba)
  1976. {
  1977. struct be_mem_descriptor *mem_descr;
  1978. dma_addr_t bus_add;
  1979. struct mem_array *mem_arr, *mem_arr_orig;
  1980. unsigned int i, j, alloc_size, curr_alloc_size;
  1981. phba->phwi_ctrlr = kzalloc(phba->params.hwi_ws_sz, GFP_KERNEL);
  1982. if (!phba->phwi_ctrlr)
  1983. return -ENOMEM;
  1984. phba->init_mem = kcalloc(SE_MEM_MAX, sizeof(*mem_descr),
  1985. GFP_KERNEL);
  1986. if (!phba->init_mem) {
  1987. kfree(phba->phwi_ctrlr);
  1988. return -ENOMEM;
  1989. }
  1990. mem_arr_orig = kmalloc(sizeof(*mem_arr_orig) * BEISCSI_MAX_FRAGS_INIT,
  1991. GFP_KERNEL);
  1992. if (!mem_arr_orig) {
  1993. kfree(phba->init_mem);
  1994. kfree(phba->phwi_ctrlr);
  1995. return -ENOMEM;
  1996. }
  1997. mem_descr = phba->init_mem;
  1998. for (i = 0; i < SE_MEM_MAX; i++) {
  1999. j = 0;
  2000. mem_arr = mem_arr_orig;
  2001. alloc_size = phba->mem_req[i];
  2002. memset(mem_arr, 0, sizeof(struct mem_array) *
  2003. BEISCSI_MAX_FRAGS_INIT);
  2004. curr_alloc_size = min(be_max_phys_size * 1024, alloc_size);
  2005. do {
  2006. mem_arr->virtual_address = pci_alloc_consistent(
  2007. phba->pcidev,
  2008. curr_alloc_size,
  2009. &bus_add);
  2010. if (!mem_arr->virtual_address) {
  2011. if (curr_alloc_size <= BE_MIN_MEM_SIZE)
  2012. goto free_mem;
  2013. if (curr_alloc_size -
  2014. rounddown_pow_of_two(curr_alloc_size))
  2015. curr_alloc_size = rounddown_pow_of_two
  2016. (curr_alloc_size);
  2017. else
  2018. curr_alloc_size = curr_alloc_size / 2;
  2019. } else {
  2020. mem_arr->bus_address.u.
  2021. a64.address = (__u64) bus_add;
  2022. mem_arr->size = curr_alloc_size;
  2023. alloc_size -= curr_alloc_size;
  2024. curr_alloc_size = min(be_max_phys_size *
  2025. 1024, alloc_size);
  2026. j++;
  2027. mem_arr++;
  2028. }
  2029. } while (alloc_size);
  2030. mem_descr->num_elements = j;
  2031. mem_descr->size_in_bytes = phba->mem_req[i];
  2032. mem_descr->mem_array = kmalloc(sizeof(*mem_arr) * j,
  2033. GFP_KERNEL);
  2034. if (!mem_descr->mem_array)
  2035. goto free_mem;
  2036. memcpy(mem_descr->mem_array, mem_arr_orig,
  2037. sizeof(struct mem_array) * j);
  2038. mem_descr++;
  2039. }
  2040. kfree(mem_arr_orig);
  2041. return 0;
  2042. free_mem:
  2043. mem_descr->num_elements = j;
  2044. while ((i) || (j)) {
  2045. for (j = mem_descr->num_elements; j > 0; j--) {
  2046. pci_free_consistent(phba->pcidev,
  2047. mem_descr->mem_array[j - 1].size,
  2048. mem_descr->mem_array[j - 1].
  2049. virtual_address,
  2050. (unsigned long)mem_descr->
  2051. mem_array[j - 1].
  2052. bus_address.u.a64.address);
  2053. }
  2054. if (i) {
  2055. i--;
  2056. kfree(mem_descr->mem_array);
  2057. mem_descr--;
  2058. }
  2059. }
  2060. kfree(mem_arr_orig);
  2061. kfree(phba->init_mem);
  2062. kfree(phba->phwi_ctrlr);
  2063. return -ENOMEM;
  2064. }
  2065. static int beiscsi_get_memory(struct beiscsi_hba *phba)
  2066. {
  2067. beiscsi_find_mem_req(phba);
  2068. return beiscsi_alloc_mem(phba);
  2069. }
  2070. static void iscsi_init_global_templates(struct beiscsi_hba *phba)
  2071. {
  2072. struct pdu_data_out *pdata_out;
  2073. struct pdu_nop_out *pnop_out;
  2074. struct be_mem_descriptor *mem_descr;
  2075. mem_descr = phba->init_mem;
  2076. mem_descr += ISCSI_MEM_GLOBAL_HEADER;
  2077. pdata_out =
  2078. (struct pdu_data_out *)mem_descr->mem_array[0].virtual_address;
  2079. memset(pdata_out, 0, BE_ISCSI_PDU_HEADER_SIZE);
  2080. AMAP_SET_BITS(struct amap_pdu_data_out, opcode, pdata_out,
  2081. IIOC_SCSI_DATA);
  2082. pnop_out =
  2083. (struct pdu_nop_out *)((unsigned char *)mem_descr->mem_array[0].
  2084. virtual_address + BE_ISCSI_PDU_HEADER_SIZE);
  2085. memset(pnop_out, 0, BE_ISCSI_PDU_HEADER_SIZE);
  2086. AMAP_SET_BITS(struct amap_pdu_nop_out, ttt, pnop_out, 0xFFFFFFFF);
  2087. AMAP_SET_BITS(struct amap_pdu_nop_out, f_bit, pnop_out, 1);
  2088. AMAP_SET_BITS(struct amap_pdu_nop_out, i_bit, pnop_out, 0);
  2089. }
  2090. static int beiscsi_init_wrb_handle(struct beiscsi_hba *phba)
  2091. {
  2092. struct be_mem_descriptor *mem_descr_wrbh, *mem_descr_wrb;
  2093. struct wrb_handle *pwrb_handle = NULL;
  2094. struct hwi_controller *phwi_ctrlr;
  2095. struct hwi_wrb_context *pwrb_context;
  2096. struct iscsi_wrb *pwrb = NULL;
  2097. unsigned int num_cxn_wrbh = 0;
  2098. unsigned int num_cxn_wrb = 0, j, idx = 0, index;
  2099. mem_descr_wrbh = phba->init_mem;
  2100. mem_descr_wrbh += HWI_MEM_WRBH;
  2101. mem_descr_wrb = phba->init_mem;
  2102. mem_descr_wrb += HWI_MEM_WRB;
  2103. phwi_ctrlr = phba->phwi_ctrlr;
  2104. for (index = 0; index < phba->params.cxns_per_ctrl * 2; index += 2) {
  2105. pwrb_context = &phwi_ctrlr->wrb_context[index];
  2106. pwrb_context->pwrb_handle_base =
  2107. kzalloc(sizeof(struct wrb_handle *) *
  2108. phba->params.wrbs_per_cxn, GFP_KERNEL);
  2109. if (!pwrb_context->pwrb_handle_base) {
  2110. shost_printk(KERN_ERR, phba->shost,
  2111. "Mem Alloc Failed. Failing to load\n");
  2112. goto init_wrb_hndl_failed;
  2113. }
  2114. pwrb_context->pwrb_handle_basestd =
  2115. kzalloc(sizeof(struct wrb_handle *) *
  2116. phba->params.wrbs_per_cxn, GFP_KERNEL);
  2117. if (!pwrb_context->pwrb_handle_basestd) {
  2118. shost_printk(KERN_ERR, phba->shost,
  2119. "Mem Alloc Failed. Failing to load\n");
  2120. goto init_wrb_hndl_failed;
  2121. }
  2122. if (!num_cxn_wrbh) {
  2123. pwrb_handle =
  2124. mem_descr_wrbh->mem_array[idx].virtual_address;
  2125. num_cxn_wrbh = ((mem_descr_wrbh->mem_array[idx].size) /
  2126. ((sizeof(struct wrb_handle)) *
  2127. phba->params.wrbs_per_cxn));
  2128. idx++;
  2129. }
  2130. pwrb_context->alloc_index = 0;
  2131. pwrb_context->wrb_handles_available = 0;
  2132. pwrb_context->free_index = 0;
  2133. if (num_cxn_wrbh) {
  2134. for (j = 0; j < phba->params.wrbs_per_cxn; j++) {
  2135. pwrb_context->pwrb_handle_base[j] = pwrb_handle;
  2136. pwrb_context->pwrb_handle_basestd[j] =
  2137. pwrb_handle;
  2138. pwrb_context->wrb_handles_available++;
  2139. pwrb_handle->wrb_index = j;
  2140. pwrb_handle++;
  2141. }
  2142. num_cxn_wrbh--;
  2143. }
  2144. }
  2145. idx = 0;
  2146. for (index = 0; index < phba->params.cxns_per_ctrl * 2; index += 2) {
  2147. pwrb_context = &phwi_ctrlr->wrb_context[index];
  2148. if (!num_cxn_wrb) {
  2149. pwrb = mem_descr_wrb->mem_array[idx].virtual_address;
  2150. num_cxn_wrb = (mem_descr_wrb->mem_array[idx].size) /
  2151. ((sizeof(struct iscsi_wrb) *
  2152. phba->params.wrbs_per_cxn));
  2153. idx++;
  2154. }
  2155. if (num_cxn_wrb) {
  2156. for (j = 0; j < phba->params.wrbs_per_cxn; j++) {
  2157. pwrb_handle = pwrb_context->pwrb_handle_base[j];
  2158. pwrb_handle->pwrb = pwrb;
  2159. pwrb++;
  2160. }
  2161. num_cxn_wrb--;
  2162. }
  2163. }
  2164. return 0;
  2165. init_wrb_hndl_failed:
  2166. for (j = index; j > 0; j--) {
  2167. pwrb_context = &phwi_ctrlr->wrb_context[j];
  2168. kfree(pwrb_context->pwrb_handle_base);
  2169. kfree(pwrb_context->pwrb_handle_basestd);
  2170. }
  2171. return -ENOMEM;
  2172. }
  2173. static void hwi_init_async_pdu_ctx(struct beiscsi_hba *phba)
  2174. {
  2175. struct hwi_controller *phwi_ctrlr;
  2176. struct hba_parameters *p = &phba->params;
  2177. struct hwi_async_pdu_context *pasync_ctx;
  2178. struct async_pdu_handle *pasync_header_h, *pasync_data_h;
  2179. unsigned int index, idx, num_per_mem, num_async_data;
  2180. struct be_mem_descriptor *mem_descr;
  2181. mem_descr = (struct be_mem_descriptor *)phba->init_mem;
  2182. mem_descr += HWI_MEM_ASYNC_PDU_CONTEXT;
  2183. phwi_ctrlr = phba->phwi_ctrlr;
  2184. phwi_ctrlr->phwi_ctxt->pasync_ctx = (struct hwi_async_pdu_context *)
  2185. mem_descr->mem_array[0].virtual_address;
  2186. pasync_ctx = phwi_ctrlr->phwi_ctxt->pasync_ctx;
  2187. memset(pasync_ctx, 0, sizeof(*pasync_ctx));
  2188. pasync_ctx->num_entries = p->asyncpdus_per_ctrl;
  2189. pasync_ctx->buffer_size = p->defpdu_hdr_sz;
  2190. mem_descr = (struct be_mem_descriptor *)phba->init_mem;
  2191. mem_descr += HWI_MEM_ASYNC_HEADER_BUF;
  2192. if (mem_descr->mem_array[0].virtual_address) {
  2193. SE_DEBUG(DBG_LVL_8,
  2194. "hwi_init_async_pdu_ctx HWI_MEM_ASYNC_HEADER_BUF"
  2195. "va=%p\n", mem_descr->mem_array[0].virtual_address);
  2196. } else
  2197. shost_printk(KERN_WARNING, phba->shost,
  2198. "No Virtual address\n");
  2199. pasync_ctx->async_header.va_base =
  2200. mem_descr->mem_array[0].virtual_address;
  2201. pasync_ctx->async_header.pa_base.u.a64.address =
  2202. mem_descr->mem_array[0].bus_address.u.a64.address;
  2203. mem_descr = (struct be_mem_descriptor *)phba->init_mem;
  2204. mem_descr += HWI_MEM_ASYNC_HEADER_RING;
  2205. if (mem_descr->mem_array[0].virtual_address) {
  2206. SE_DEBUG(DBG_LVL_8,
  2207. "hwi_init_async_pdu_ctx HWI_MEM_ASYNC_HEADER_RING"
  2208. "va=%p\n", mem_descr->mem_array[0].virtual_address);
  2209. } else
  2210. shost_printk(KERN_WARNING, phba->shost,
  2211. "No Virtual address\n");
  2212. pasync_ctx->async_header.ring_base =
  2213. mem_descr->mem_array[0].virtual_address;
  2214. mem_descr = (struct be_mem_descriptor *)phba->init_mem;
  2215. mem_descr += HWI_MEM_ASYNC_HEADER_HANDLE;
  2216. if (mem_descr->mem_array[0].virtual_address) {
  2217. SE_DEBUG(DBG_LVL_8,
  2218. "hwi_init_async_pdu_ctx HWI_MEM_ASYNC_HEADER_HANDLE"
  2219. "va=%p\n", mem_descr->mem_array[0].virtual_address);
  2220. } else
  2221. shost_printk(KERN_WARNING, phba->shost,
  2222. "No Virtual address\n");
  2223. pasync_ctx->async_header.handle_base =
  2224. mem_descr->mem_array[0].virtual_address;
  2225. pasync_ctx->async_header.writables = 0;
  2226. INIT_LIST_HEAD(&pasync_ctx->async_header.free_list);
  2227. mem_descr = (struct be_mem_descriptor *)phba->init_mem;
  2228. mem_descr += HWI_MEM_ASYNC_DATA_RING;
  2229. if (mem_descr->mem_array[0].virtual_address) {
  2230. SE_DEBUG(DBG_LVL_8,
  2231. "hwi_init_async_pdu_ctx HWI_MEM_ASYNC_DATA_RING"
  2232. "va=%p\n", mem_descr->mem_array[0].virtual_address);
  2233. } else
  2234. shost_printk(KERN_WARNING, phba->shost,
  2235. "No Virtual address\n");
  2236. pasync_ctx->async_data.ring_base =
  2237. mem_descr->mem_array[0].virtual_address;
  2238. mem_descr = (struct be_mem_descriptor *)phba->init_mem;
  2239. mem_descr += HWI_MEM_ASYNC_DATA_HANDLE;
  2240. if (!mem_descr->mem_array[0].virtual_address)
  2241. shost_printk(KERN_WARNING, phba->shost,
  2242. "No Virtual address\n");
  2243. pasync_ctx->async_data.handle_base =
  2244. mem_descr->mem_array[0].virtual_address;
  2245. pasync_ctx->async_data.writables = 0;
  2246. INIT_LIST_HEAD(&pasync_ctx->async_data.free_list);
  2247. pasync_header_h =
  2248. (struct async_pdu_handle *)pasync_ctx->async_header.handle_base;
  2249. pasync_data_h =
  2250. (struct async_pdu_handle *)pasync_ctx->async_data.handle_base;
  2251. mem_descr = (struct be_mem_descriptor *)phba->init_mem;
  2252. mem_descr += HWI_MEM_ASYNC_DATA_BUF;
  2253. if (mem_descr->mem_array[0].virtual_address) {
  2254. SE_DEBUG(DBG_LVL_8,
  2255. "hwi_init_async_pdu_ctx HWI_MEM_ASYNC_DATA_BUF"
  2256. "va=%p\n", mem_descr->mem_array[0].virtual_address);
  2257. } else
  2258. shost_printk(KERN_WARNING, phba->shost,
  2259. "No Virtual address\n");
  2260. idx = 0;
  2261. pasync_ctx->async_data.va_base =
  2262. mem_descr->mem_array[idx].virtual_address;
  2263. pasync_ctx->async_data.pa_base.u.a64.address =
  2264. mem_descr->mem_array[idx].bus_address.u.a64.address;
  2265. num_async_data = ((mem_descr->mem_array[idx].size) /
  2266. phba->params.defpdu_data_sz);
  2267. num_per_mem = 0;
  2268. for (index = 0; index < p->asyncpdus_per_ctrl; index++) {
  2269. pasync_header_h->cri = -1;
  2270. pasync_header_h->index = (char)index;
  2271. INIT_LIST_HEAD(&pasync_header_h->link);
  2272. pasync_header_h->pbuffer =
  2273. (void *)((unsigned long)
  2274. (pasync_ctx->async_header.va_base) +
  2275. (p->defpdu_hdr_sz * index));
  2276. pasync_header_h->pa.u.a64.address =
  2277. pasync_ctx->async_header.pa_base.u.a64.address +
  2278. (p->defpdu_hdr_sz * index);
  2279. list_add_tail(&pasync_header_h->link,
  2280. &pasync_ctx->async_header.free_list);
  2281. pasync_header_h++;
  2282. pasync_ctx->async_header.free_entries++;
  2283. pasync_ctx->async_header.writables++;
  2284. INIT_LIST_HEAD(&pasync_ctx->async_entry[index].wait_queue.list);
  2285. INIT_LIST_HEAD(&pasync_ctx->async_entry[index].
  2286. header_busy_list);
  2287. pasync_data_h->cri = -1;
  2288. pasync_data_h->index = (char)index;
  2289. INIT_LIST_HEAD(&pasync_data_h->link);
  2290. if (!num_async_data) {
  2291. num_per_mem = 0;
  2292. idx++;
  2293. pasync_ctx->async_data.va_base =
  2294. mem_descr->mem_array[idx].virtual_address;
  2295. pasync_ctx->async_data.pa_base.u.a64.address =
  2296. mem_descr->mem_array[idx].
  2297. bus_address.u.a64.address;
  2298. num_async_data = ((mem_descr->mem_array[idx].size) /
  2299. phba->params.defpdu_data_sz);
  2300. }
  2301. pasync_data_h->pbuffer =
  2302. (void *)((unsigned long)
  2303. (pasync_ctx->async_data.va_base) +
  2304. (p->defpdu_data_sz * num_per_mem));
  2305. pasync_data_h->pa.u.a64.address =
  2306. pasync_ctx->async_data.pa_base.u.a64.address +
  2307. (p->defpdu_data_sz * num_per_mem);
  2308. num_per_mem++;
  2309. num_async_data--;
  2310. list_add_tail(&pasync_data_h->link,
  2311. &pasync_ctx->async_data.free_list);
  2312. pasync_data_h++;
  2313. pasync_ctx->async_data.free_entries++;
  2314. pasync_ctx->async_data.writables++;
  2315. INIT_LIST_HEAD(&pasync_ctx->async_entry[index].data_busy_list);
  2316. }
  2317. pasync_ctx->async_header.host_write_ptr = 0;
  2318. pasync_ctx->async_header.ep_read_ptr = -1;
  2319. pasync_ctx->async_data.host_write_ptr = 0;
  2320. pasync_ctx->async_data.ep_read_ptr = -1;
  2321. }
  2322. static int
  2323. be_sgl_create_contiguous(void *virtual_address,
  2324. u64 physical_address, u32 length,
  2325. struct be_dma_mem *sgl)
  2326. {
  2327. WARN_ON(!virtual_address);
  2328. WARN_ON(!physical_address);
  2329. WARN_ON(!length > 0);
  2330. WARN_ON(!sgl);
  2331. sgl->va = virtual_address;
  2332. sgl->dma = (unsigned long)physical_address;
  2333. sgl->size = length;
  2334. return 0;
  2335. }
  2336. static void be_sgl_destroy_contiguous(struct be_dma_mem *sgl)
  2337. {
  2338. memset(sgl, 0, sizeof(*sgl));
  2339. }
  2340. static void
  2341. hwi_build_be_sgl_arr(struct beiscsi_hba *phba,
  2342. struct mem_array *pmem, struct be_dma_mem *sgl)
  2343. {
  2344. if (sgl->va)
  2345. be_sgl_destroy_contiguous(sgl);
  2346. be_sgl_create_contiguous(pmem->virtual_address,
  2347. pmem->bus_address.u.a64.address,
  2348. pmem->size, sgl);
  2349. }
  2350. static void
  2351. hwi_build_be_sgl_by_offset(struct beiscsi_hba *phba,
  2352. struct mem_array *pmem, struct be_dma_mem *sgl)
  2353. {
  2354. if (sgl->va)
  2355. be_sgl_destroy_contiguous(sgl);
  2356. be_sgl_create_contiguous((unsigned char *)pmem->virtual_address,
  2357. pmem->bus_address.u.a64.address,
  2358. pmem->size, sgl);
  2359. }
  2360. static int be_fill_queue(struct be_queue_info *q,
  2361. u16 len, u16 entry_size, void *vaddress)
  2362. {
  2363. struct be_dma_mem *mem = &q->dma_mem;
  2364. memset(q, 0, sizeof(*q));
  2365. q->len = len;
  2366. q->entry_size = entry_size;
  2367. mem->size = len * entry_size;
  2368. mem->va = vaddress;
  2369. if (!mem->va)
  2370. return -ENOMEM;
  2371. memset(mem->va, 0, mem->size);
  2372. return 0;
  2373. }
  2374. static int beiscsi_create_eqs(struct beiscsi_hba *phba,
  2375. struct hwi_context_memory *phwi_context)
  2376. {
  2377. unsigned int i, num_eq_pages;
  2378. int ret, eq_for_mcc;
  2379. struct be_queue_info *eq;
  2380. struct be_dma_mem *mem;
  2381. void *eq_vaddress;
  2382. dma_addr_t paddr;
  2383. num_eq_pages = PAGES_REQUIRED(phba->params.num_eq_entries * \
  2384. sizeof(struct be_eq_entry));
  2385. if (phba->msix_enabled)
  2386. eq_for_mcc = 1;
  2387. else
  2388. eq_for_mcc = 0;
  2389. for (i = 0; i < (phba->num_cpus + eq_for_mcc); i++) {
  2390. eq = &phwi_context->be_eq[i].q;
  2391. mem = &eq->dma_mem;
  2392. phwi_context->be_eq[i].phba = phba;
  2393. eq_vaddress = pci_alloc_consistent(phba->pcidev,
  2394. num_eq_pages * PAGE_SIZE,
  2395. &paddr);
  2396. if (!eq_vaddress)
  2397. goto create_eq_error;
  2398. mem->va = eq_vaddress;
  2399. ret = be_fill_queue(eq, phba->params.num_eq_entries,
  2400. sizeof(struct be_eq_entry), eq_vaddress);
  2401. if (ret) {
  2402. shost_printk(KERN_ERR, phba->shost,
  2403. "be_fill_queue Failed for EQ\n");
  2404. goto create_eq_error;
  2405. }
  2406. mem->dma = paddr;
  2407. ret = beiscsi_cmd_eq_create(&phba->ctrl, eq,
  2408. phwi_context->cur_eqd);
  2409. if (ret) {
  2410. shost_printk(KERN_ERR, phba->shost,
  2411. "beiscsi_cmd_eq_create"
  2412. "Failedfor EQ\n");
  2413. goto create_eq_error;
  2414. }
  2415. SE_DEBUG(DBG_LVL_8, "eqid = %d\n", phwi_context->be_eq[i].q.id);
  2416. }
  2417. return 0;
  2418. create_eq_error:
  2419. for (i = 0; i < (phba->num_cpus + 1); i++) {
  2420. eq = &phwi_context->be_eq[i].q;
  2421. mem = &eq->dma_mem;
  2422. if (mem->va)
  2423. pci_free_consistent(phba->pcidev, num_eq_pages
  2424. * PAGE_SIZE,
  2425. mem->va, mem->dma);
  2426. }
  2427. return ret;
  2428. }
  2429. static int beiscsi_create_cqs(struct beiscsi_hba *phba,
  2430. struct hwi_context_memory *phwi_context)
  2431. {
  2432. unsigned int i, num_cq_pages;
  2433. int ret;
  2434. struct be_queue_info *cq, *eq;
  2435. struct be_dma_mem *mem;
  2436. struct be_eq_obj *pbe_eq;
  2437. void *cq_vaddress;
  2438. dma_addr_t paddr;
  2439. num_cq_pages = PAGES_REQUIRED(phba->params.num_cq_entries * \
  2440. sizeof(struct sol_cqe));
  2441. for (i = 0; i < phba->num_cpus; i++) {
  2442. cq = &phwi_context->be_cq[i];
  2443. eq = &phwi_context->be_eq[i].q;
  2444. pbe_eq = &phwi_context->be_eq[i];
  2445. pbe_eq->cq = cq;
  2446. pbe_eq->phba = phba;
  2447. mem = &cq->dma_mem;
  2448. cq_vaddress = pci_alloc_consistent(phba->pcidev,
  2449. num_cq_pages * PAGE_SIZE,
  2450. &paddr);
  2451. if (!cq_vaddress)
  2452. goto create_cq_error;
  2453. ret = be_fill_queue(cq, phba->params.num_cq_entries,
  2454. sizeof(struct sol_cqe), cq_vaddress);
  2455. if (ret) {
  2456. shost_printk(KERN_ERR, phba->shost,
  2457. "be_fill_queue Failed for ISCSI CQ\n");
  2458. goto create_cq_error;
  2459. }
  2460. mem->dma = paddr;
  2461. ret = beiscsi_cmd_cq_create(&phba->ctrl, cq, eq, false,
  2462. false, 0);
  2463. if (ret) {
  2464. shost_printk(KERN_ERR, phba->shost,
  2465. "beiscsi_cmd_eq_create"
  2466. "Failed for ISCSI CQ\n");
  2467. goto create_cq_error;
  2468. }
  2469. SE_DEBUG(DBG_LVL_8, "iscsi cq_id is %d for eq_id %d\n",
  2470. cq->id, eq->id);
  2471. SE_DEBUG(DBG_LVL_8, "ISCSI CQ CREATED\n");
  2472. }
  2473. return 0;
  2474. create_cq_error:
  2475. for (i = 0; i < phba->num_cpus; i++) {
  2476. cq = &phwi_context->be_cq[i];
  2477. mem = &cq->dma_mem;
  2478. if (mem->va)
  2479. pci_free_consistent(phba->pcidev, num_cq_pages
  2480. * PAGE_SIZE,
  2481. mem->va, mem->dma);
  2482. }
  2483. return ret;
  2484. }
  2485. static int
  2486. beiscsi_create_def_hdr(struct beiscsi_hba *phba,
  2487. struct hwi_context_memory *phwi_context,
  2488. struct hwi_controller *phwi_ctrlr,
  2489. unsigned int def_pdu_ring_sz)
  2490. {
  2491. unsigned int idx;
  2492. int ret;
  2493. struct be_queue_info *dq, *cq;
  2494. struct be_dma_mem *mem;
  2495. struct be_mem_descriptor *mem_descr;
  2496. void *dq_vaddress;
  2497. idx = 0;
  2498. dq = &phwi_context->be_def_hdrq;
  2499. cq = &phwi_context->be_cq[0];
  2500. mem = &dq->dma_mem;
  2501. mem_descr = phba->init_mem;
  2502. mem_descr += HWI_MEM_ASYNC_HEADER_RING;
  2503. dq_vaddress = mem_descr->mem_array[idx].virtual_address;
  2504. ret = be_fill_queue(dq, mem_descr->mem_array[0].size /
  2505. sizeof(struct phys_addr),
  2506. sizeof(struct phys_addr), dq_vaddress);
  2507. if (ret) {
  2508. shost_printk(KERN_ERR, phba->shost,
  2509. "be_fill_queue Failed for DEF PDU HDR\n");
  2510. return ret;
  2511. }
  2512. mem->dma = (unsigned long)mem_descr->mem_array[idx].
  2513. bus_address.u.a64.address;
  2514. ret = be_cmd_create_default_pdu_queue(&phba->ctrl, cq, dq,
  2515. def_pdu_ring_sz,
  2516. phba->params.defpdu_hdr_sz);
  2517. if (ret) {
  2518. shost_printk(KERN_ERR, phba->shost,
  2519. "be_cmd_create_default_pdu_queue Failed DEFHDR\n");
  2520. return ret;
  2521. }
  2522. phwi_ctrlr->default_pdu_hdr.id = phwi_context->be_def_hdrq.id;
  2523. SE_DEBUG(DBG_LVL_8, "iscsi def pdu id is %d\n",
  2524. phwi_context->be_def_hdrq.id);
  2525. hwi_post_async_buffers(phba, 1);
  2526. return 0;
  2527. }
  2528. static int
  2529. beiscsi_create_def_data(struct beiscsi_hba *phba,
  2530. struct hwi_context_memory *phwi_context,
  2531. struct hwi_controller *phwi_ctrlr,
  2532. unsigned int def_pdu_ring_sz)
  2533. {
  2534. unsigned int idx;
  2535. int ret;
  2536. struct be_queue_info *dataq, *cq;
  2537. struct be_dma_mem *mem;
  2538. struct be_mem_descriptor *mem_descr;
  2539. void *dq_vaddress;
  2540. idx = 0;
  2541. dataq = &phwi_context->be_def_dataq;
  2542. cq = &phwi_context->be_cq[0];
  2543. mem = &dataq->dma_mem;
  2544. mem_descr = phba->init_mem;
  2545. mem_descr += HWI_MEM_ASYNC_DATA_RING;
  2546. dq_vaddress = mem_descr->mem_array[idx].virtual_address;
  2547. ret = be_fill_queue(dataq, mem_descr->mem_array[0].size /
  2548. sizeof(struct phys_addr),
  2549. sizeof(struct phys_addr), dq_vaddress);
  2550. if (ret) {
  2551. shost_printk(KERN_ERR, phba->shost,
  2552. "be_fill_queue Failed for DEF PDU DATA\n");
  2553. return ret;
  2554. }
  2555. mem->dma = (unsigned long)mem_descr->mem_array[idx].
  2556. bus_address.u.a64.address;
  2557. ret = be_cmd_create_default_pdu_queue(&phba->ctrl, cq, dataq,
  2558. def_pdu_ring_sz,
  2559. phba->params.defpdu_data_sz);
  2560. if (ret) {
  2561. shost_printk(KERN_ERR, phba->shost,
  2562. "be_cmd_create_default_pdu_queue Failed"
  2563. " for DEF PDU DATA\n");
  2564. return ret;
  2565. }
  2566. phwi_ctrlr->default_pdu_data.id = phwi_context->be_def_dataq.id;
  2567. SE_DEBUG(DBG_LVL_8, "iscsi def data id is %d\n",
  2568. phwi_context->be_def_dataq.id);
  2569. hwi_post_async_buffers(phba, 0);
  2570. SE_DEBUG(DBG_LVL_8, "DEFAULT PDU DATA RING CREATED\n");
  2571. return 0;
  2572. }
  2573. static int
  2574. beiscsi_post_pages(struct beiscsi_hba *phba)
  2575. {
  2576. struct be_mem_descriptor *mem_descr;
  2577. struct mem_array *pm_arr;
  2578. unsigned int page_offset, i;
  2579. struct be_dma_mem sgl;
  2580. int status;
  2581. mem_descr = phba->init_mem;
  2582. mem_descr += HWI_MEM_SGE;
  2583. pm_arr = mem_descr->mem_array;
  2584. page_offset = (sizeof(struct iscsi_sge) * phba->params.num_sge_per_io *
  2585. phba->fw_config.iscsi_icd_start) / PAGE_SIZE;
  2586. for (i = 0; i < mem_descr->num_elements; i++) {
  2587. hwi_build_be_sgl_arr(phba, pm_arr, &sgl);
  2588. status = be_cmd_iscsi_post_sgl_pages(&phba->ctrl, &sgl,
  2589. page_offset,
  2590. (pm_arr->size / PAGE_SIZE));
  2591. page_offset += pm_arr->size / PAGE_SIZE;
  2592. if (status != 0) {
  2593. shost_printk(KERN_ERR, phba->shost,
  2594. "post sgl failed.\n");
  2595. return status;
  2596. }
  2597. pm_arr++;
  2598. }
  2599. SE_DEBUG(DBG_LVL_8, "POSTED PAGES\n");
  2600. return 0;
  2601. }
  2602. static void be_queue_free(struct beiscsi_hba *phba, struct be_queue_info *q)
  2603. {
  2604. struct be_dma_mem *mem = &q->dma_mem;
  2605. if (mem->va) {
  2606. pci_free_consistent(phba->pcidev, mem->size,
  2607. mem->va, mem->dma);
  2608. mem->va = NULL;
  2609. }
  2610. }
  2611. static int be_queue_alloc(struct beiscsi_hba *phba, struct be_queue_info *q,
  2612. u16 len, u16 entry_size)
  2613. {
  2614. struct be_dma_mem *mem = &q->dma_mem;
  2615. memset(q, 0, sizeof(*q));
  2616. q->len = len;
  2617. q->entry_size = entry_size;
  2618. mem->size = len * entry_size;
  2619. mem->va = pci_alloc_consistent(phba->pcidev, mem->size, &mem->dma);
  2620. if (!mem->va)
  2621. return -ENOMEM;
  2622. memset(mem->va, 0, mem->size);
  2623. return 0;
  2624. }
  2625. static int
  2626. beiscsi_create_wrb_rings(struct beiscsi_hba *phba,
  2627. struct hwi_context_memory *phwi_context,
  2628. struct hwi_controller *phwi_ctrlr)
  2629. {
  2630. unsigned int wrb_mem_index, offset, size, num_wrb_rings;
  2631. u64 pa_addr_lo;
  2632. unsigned int idx, num, i;
  2633. struct mem_array *pwrb_arr;
  2634. void *wrb_vaddr;
  2635. struct be_dma_mem sgl;
  2636. struct be_mem_descriptor *mem_descr;
  2637. int status;
  2638. idx = 0;
  2639. mem_descr = phba->init_mem;
  2640. mem_descr += HWI_MEM_WRB;
  2641. pwrb_arr = kmalloc(sizeof(*pwrb_arr) * phba->params.cxns_per_ctrl,
  2642. GFP_KERNEL);
  2643. if (!pwrb_arr) {
  2644. shost_printk(KERN_ERR, phba->shost,
  2645. "Memory alloc failed in create wrb ring.\n");
  2646. return -ENOMEM;
  2647. }
  2648. wrb_vaddr = mem_descr->mem_array[idx].virtual_address;
  2649. pa_addr_lo = mem_descr->mem_array[idx].bus_address.u.a64.address;
  2650. num_wrb_rings = mem_descr->mem_array[idx].size /
  2651. (phba->params.wrbs_per_cxn * sizeof(struct iscsi_wrb));
  2652. for (num = 0; num < phba->params.cxns_per_ctrl; num++) {
  2653. if (num_wrb_rings) {
  2654. pwrb_arr[num].virtual_address = wrb_vaddr;
  2655. pwrb_arr[num].bus_address.u.a64.address = pa_addr_lo;
  2656. pwrb_arr[num].size = phba->params.wrbs_per_cxn *
  2657. sizeof(struct iscsi_wrb);
  2658. wrb_vaddr += pwrb_arr[num].size;
  2659. pa_addr_lo += pwrb_arr[num].size;
  2660. num_wrb_rings--;
  2661. } else {
  2662. idx++;
  2663. wrb_vaddr = mem_descr->mem_array[idx].virtual_address;
  2664. pa_addr_lo = mem_descr->mem_array[idx].\
  2665. bus_address.u.a64.address;
  2666. num_wrb_rings = mem_descr->mem_array[idx].size /
  2667. (phba->params.wrbs_per_cxn *
  2668. sizeof(struct iscsi_wrb));
  2669. pwrb_arr[num].virtual_address = wrb_vaddr;
  2670. pwrb_arr[num].bus_address.u.a64.address\
  2671. = pa_addr_lo;
  2672. pwrb_arr[num].size = phba->params.wrbs_per_cxn *
  2673. sizeof(struct iscsi_wrb);
  2674. wrb_vaddr += pwrb_arr[num].size;
  2675. pa_addr_lo += pwrb_arr[num].size;
  2676. num_wrb_rings--;
  2677. }
  2678. }
  2679. for (i = 0; i < phba->params.cxns_per_ctrl; i++) {
  2680. wrb_mem_index = 0;
  2681. offset = 0;
  2682. size = 0;
  2683. hwi_build_be_sgl_by_offset(phba, &pwrb_arr[i], &sgl);
  2684. status = be_cmd_wrbq_create(&phba->ctrl, &sgl,
  2685. &phwi_context->be_wrbq[i]);
  2686. if (status != 0) {
  2687. shost_printk(KERN_ERR, phba->shost,
  2688. "wrbq create failed.");
  2689. kfree(pwrb_arr);
  2690. return status;
  2691. }
  2692. phwi_ctrlr->wrb_context[i * 2].cid = phwi_context->be_wrbq[i].
  2693. id;
  2694. }
  2695. kfree(pwrb_arr);
  2696. return 0;
  2697. }
  2698. static void free_wrb_handles(struct beiscsi_hba *phba)
  2699. {
  2700. unsigned int index;
  2701. struct hwi_controller *phwi_ctrlr;
  2702. struct hwi_wrb_context *pwrb_context;
  2703. phwi_ctrlr = phba->phwi_ctrlr;
  2704. for (index = 0; index < phba->params.cxns_per_ctrl * 2; index += 2) {
  2705. pwrb_context = &phwi_ctrlr->wrb_context[index];
  2706. kfree(pwrb_context->pwrb_handle_base);
  2707. kfree(pwrb_context->pwrb_handle_basestd);
  2708. }
  2709. }
  2710. static void be_mcc_queues_destroy(struct beiscsi_hba *phba)
  2711. {
  2712. struct be_queue_info *q;
  2713. struct be_ctrl_info *ctrl = &phba->ctrl;
  2714. q = &phba->ctrl.mcc_obj.q;
  2715. if (q->created)
  2716. beiscsi_cmd_q_destroy(ctrl, q, QTYPE_MCCQ);
  2717. be_queue_free(phba, q);
  2718. q = &phba->ctrl.mcc_obj.cq;
  2719. if (q->created)
  2720. beiscsi_cmd_q_destroy(ctrl, q, QTYPE_CQ);
  2721. be_queue_free(phba, q);
  2722. }
  2723. static void hwi_cleanup(struct beiscsi_hba *phba)
  2724. {
  2725. struct be_queue_info *q;
  2726. struct be_ctrl_info *ctrl = &phba->ctrl;
  2727. struct hwi_controller *phwi_ctrlr;
  2728. struct hwi_context_memory *phwi_context;
  2729. int i, eq_num;
  2730. phwi_ctrlr = phba->phwi_ctrlr;
  2731. phwi_context = phwi_ctrlr->phwi_ctxt;
  2732. for (i = 0; i < phba->params.cxns_per_ctrl; i++) {
  2733. q = &phwi_context->be_wrbq[i];
  2734. if (q->created)
  2735. beiscsi_cmd_q_destroy(ctrl, q, QTYPE_WRBQ);
  2736. }
  2737. free_wrb_handles(phba);
  2738. q = &phwi_context->be_def_hdrq;
  2739. if (q->created)
  2740. beiscsi_cmd_q_destroy(ctrl, q, QTYPE_DPDUQ);
  2741. q = &phwi_context->be_def_dataq;
  2742. if (q->created)
  2743. beiscsi_cmd_q_destroy(ctrl, q, QTYPE_DPDUQ);
  2744. beiscsi_cmd_q_destroy(ctrl, NULL, QTYPE_SGL);
  2745. for (i = 0; i < (phba->num_cpus); i++) {
  2746. q = &phwi_context->be_cq[i];
  2747. if (q->created)
  2748. beiscsi_cmd_q_destroy(ctrl, q, QTYPE_CQ);
  2749. }
  2750. if (phba->msix_enabled)
  2751. eq_num = 1;
  2752. else
  2753. eq_num = 0;
  2754. for (i = 0; i < (phba->num_cpus + eq_num); i++) {
  2755. q = &phwi_context->be_eq[i].q;
  2756. if (q->created)
  2757. beiscsi_cmd_q_destroy(ctrl, q, QTYPE_EQ);
  2758. }
  2759. be_mcc_queues_destroy(phba);
  2760. }
  2761. static int be_mcc_queues_create(struct beiscsi_hba *phba,
  2762. struct hwi_context_memory *phwi_context)
  2763. {
  2764. struct be_queue_info *q, *cq;
  2765. struct be_ctrl_info *ctrl = &phba->ctrl;
  2766. /* Alloc MCC compl queue */
  2767. cq = &phba->ctrl.mcc_obj.cq;
  2768. if (be_queue_alloc(phba, cq, MCC_CQ_LEN,
  2769. sizeof(struct be_mcc_compl)))
  2770. goto err;
  2771. /* Ask BE to create MCC compl queue; */
  2772. if (phba->msix_enabled) {
  2773. if (beiscsi_cmd_cq_create(ctrl, cq, &phwi_context->be_eq
  2774. [phba->num_cpus].q, false, true, 0))
  2775. goto mcc_cq_free;
  2776. } else {
  2777. if (beiscsi_cmd_cq_create(ctrl, cq, &phwi_context->be_eq[0].q,
  2778. false, true, 0))
  2779. goto mcc_cq_free;
  2780. }
  2781. /* Alloc MCC queue */
  2782. q = &phba->ctrl.mcc_obj.q;
  2783. if (be_queue_alloc(phba, q, MCC_Q_LEN, sizeof(struct be_mcc_wrb)))
  2784. goto mcc_cq_destroy;
  2785. /* Ask BE to create MCC queue */
  2786. if (beiscsi_cmd_mccq_create(phba, q, cq))
  2787. goto mcc_q_free;
  2788. return 0;
  2789. mcc_q_free:
  2790. be_queue_free(phba, q);
  2791. mcc_cq_destroy:
  2792. beiscsi_cmd_q_destroy(ctrl, cq, QTYPE_CQ);
  2793. mcc_cq_free:
  2794. be_queue_free(phba, cq);
  2795. err:
  2796. return -ENOMEM;
  2797. }
  2798. static int find_num_cpus(void)
  2799. {
  2800. int num_cpus = 0;
  2801. num_cpus = num_online_cpus();
  2802. if (num_cpus >= MAX_CPUS)
  2803. num_cpus = MAX_CPUS - 1;
  2804. SE_DEBUG(DBG_LVL_8, "num_cpus = %d\n", num_cpus);
  2805. return num_cpus;
  2806. }
  2807. static int hwi_init_port(struct beiscsi_hba *phba)
  2808. {
  2809. struct hwi_controller *phwi_ctrlr;
  2810. struct hwi_context_memory *phwi_context;
  2811. unsigned int def_pdu_ring_sz;
  2812. struct be_ctrl_info *ctrl = &phba->ctrl;
  2813. int status;
  2814. def_pdu_ring_sz =
  2815. phba->params.asyncpdus_per_ctrl * sizeof(struct phys_addr);
  2816. phwi_ctrlr = phba->phwi_ctrlr;
  2817. phwi_context = phwi_ctrlr->phwi_ctxt;
  2818. phwi_context->max_eqd = 0;
  2819. phwi_context->min_eqd = 0;
  2820. phwi_context->cur_eqd = 64;
  2821. be_cmd_fw_initialize(&phba->ctrl);
  2822. status = beiscsi_create_eqs(phba, phwi_context);
  2823. if (status != 0) {
  2824. shost_printk(KERN_ERR, phba->shost, "EQ not created\n");
  2825. goto error;
  2826. }
  2827. status = be_mcc_queues_create(phba, phwi_context);
  2828. if (status != 0)
  2829. goto error;
  2830. status = mgmt_check_supported_fw(ctrl, phba);
  2831. if (status != 0) {
  2832. shost_printk(KERN_ERR, phba->shost,
  2833. "Unsupported fw version\n");
  2834. goto error;
  2835. }
  2836. status = beiscsi_create_cqs(phba, phwi_context);
  2837. if (status != 0) {
  2838. shost_printk(KERN_ERR, phba->shost, "CQ not created\n");
  2839. goto error;
  2840. }
  2841. status = beiscsi_create_def_hdr(phba, phwi_context, phwi_ctrlr,
  2842. def_pdu_ring_sz);
  2843. if (status != 0) {
  2844. shost_printk(KERN_ERR, phba->shost,
  2845. "Default Header not created\n");
  2846. goto error;
  2847. }
  2848. status = beiscsi_create_def_data(phba, phwi_context,
  2849. phwi_ctrlr, def_pdu_ring_sz);
  2850. if (status != 0) {
  2851. shost_printk(KERN_ERR, phba->shost,
  2852. "Default Data not created\n");
  2853. goto error;
  2854. }
  2855. status = beiscsi_post_pages(phba);
  2856. if (status != 0) {
  2857. shost_printk(KERN_ERR, phba->shost, "Post SGL Pages Failed\n");
  2858. goto error;
  2859. }
  2860. status = beiscsi_create_wrb_rings(phba, phwi_context, phwi_ctrlr);
  2861. if (status != 0) {
  2862. shost_printk(KERN_ERR, phba->shost,
  2863. "WRB Rings not created\n");
  2864. goto error;
  2865. }
  2866. SE_DEBUG(DBG_LVL_8, "hwi_init_port success\n");
  2867. return 0;
  2868. error:
  2869. shost_printk(KERN_ERR, phba->shost, "hwi_init_port failed");
  2870. hwi_cleanup(phba);
  2871. return status;
  2872. }
  2873. static int hwi_init_controller(struct beiscsi_hba *phba)
  2874. {
  2875. struct hwi_controller *phwi_ctrlr;
  2876. phwi_ctrlr = phba->phwi_ctrlr;
  2877. if (1 == phba->init_mem[HWI_MEM_ADDN_CONTEXT].num_elements) {
  2878. phwi_ctrlr->phwi_ctxt = (struct hwi_context_memory *)phba->
  2879. init_mem[HWI_MEM_ADDN_CONTEXT].mem_array[0].virtual_address;
  2880. SE_DEBUG(DBG_LVL_8, " phwi_ctrlr->phwi_ctxt=%p\n",
  2881. phwi_ctrlr->phwi_ctxt);
  2882. } else {
  2883. shost_printk(KERN_ERR, phba->shost,
  2884. "HWI_MEM_ADDN_CONTEXT is more than one element."
  2885. "Failing to load\n");
  2886. return -ENOMEM;
  2887. }
  2888. iscsi_init_global_templates(phba);
  2889. if (beiscsi_init_wrb_handle(phba))
  2890. return -ENOMEM;
  2891. hwi_init_async_pdu_ctx(phba);
  2892. if (hwi_init_port(phba) != 0) {
  2893. shost_printk(KERN_ERR, phba->shost,
  2894. "hwi_init_controller failed\n");
  2895. return -ENOMEM;
  2896. }
  2897. return 0;
  2898. }
  2899. static void beiscsi_free_mem(struct beiscsi_hba *phba)
  2900. {
  2901. struct be_mem_descriptor *mem_descr;
  2902. int i, j;
  2903. mem_descr = phba->init_mem;
  2904. i = 0;
  2905. j = 0;
  2906. for (i = 0; i < SE_MEM_MAX; i++) {
  2907. for (j = mem_descr->num_elements; j > 0; j--) {
  2908. pci_free_consistent(phba->pcidev,
  2909. mem_descr->mem_array[j - 1].size,
  2910. mem_descr->mem_array[j - 1].virtual_address,
  2911. (unsigned long)mem_descr->mem_array[j - 1].
  2912. bus_address.u.a64.address);
  2913. }
  2914. kfree(mem_descr->mem_array);
  2915. mem_descr++;
  2916. }
  2917. kfree(phba->init_mem);
  2918. kfree(phba->phwi_ctrlr);
  2919. }
  2920. static int beiscsi_init_controller(struct beiscsi_hba *phba)
  2921. {
  2922. int ret = -ENOMEM;
  2923. ret = beiscsi_get_memory(phba);
  2924. if (ret < 0) {
  2925. shost_printk(KERN_ERR, phba->shost, "beiscsi_dev_probe -"
  2926. "Failed in beiscsi_alloc_memory\n");
  2927. return ret;
  2928. }
  2929. ret = hwi_init_controller(phba);
  2930. if (ret)
  2931. goto free_init;
  2932. SE_DEBUG(DBG_LVL_8, "Return success from beiscsi_init_controller");
  2933. return 0;
  2934. free_init:
  2935. beiscsi_free_mem(phba);
  2936. return ret;
  2937. }
  2938. static int beiscsi_init_sgl_handle(struct beiscsi_hba *phba)
  2939. {
  2940. struct be_mem_descriptor *mem_descr_sglh, *mem_descr_sg;
  2941. struct sgl_handle *psgl_handle;
  2942. struct iscsi_sge *pfrag;
  2943. unsigned int arr_index, i, idx;
  2944. phba->io_sgl_hndl_avbl = 0;
  2945. phba->eh_sgl_hndl_avbl = 0;
  2946. mem_descr_sglh = phba->init_mem;
  2947. mem_descr_sglh += HWI_MEM_SGLH;
  2948. if (1 == mem_descr_sglh->num_elements) {
  2949. phba->io_sgl_hndl_base = kzalloc(sizeof(struct sgl_handle *) *
  2950. phba->params.ios_per_ctrl,
  2951. GFP_KERNEL);
  2952. if (!phba->io_sgl_hndl_base) {
  2953. shost_printk(KERN_ERR, phba->shost,
  2954. "Mem Alloc Failed. Failing to load\n");
  2955. return -ENOMEM;
  2956. }
  2957. phba->eh_sgl_hndl_base = kzalloc(sizeof(struct sgl_handle *) *
  2958. (phba->params.icds_per_ctrl -
  2959. phba->params.ios_per_ctrl),
  2960. GFP_KERNEL);
  2961. if (!phba->eh_sgl_hndl_base) {
  2962. kfree(phba->io_sgl_hndl_base);
  2963. shost_printk(KERN_ERR, phba->shost,
  2964. "Mem Alloc Failed. Failing to load\n");
  2965. return -ENOMEM;
  2966. }
  2967. } else {
  2968. shost_printk(KERN_ERR, phba->shost,
  2969. "HWI_MEM_SGLH is more than one element."
  2970. "Failing to load\n");
  2971. return -ENOMEM;
  2972. }
  2973. arr_index = 0;
  2974. idx = 0;
  2975. while (idx < mem_descr_sglh->num_elements) {
  2976. psgl_handle = mem_descr_sglh->mem_array[idx].virtual_address;
  2977. for (i = 0; i < (mem_descr_sglh->mem_array[idx].size /
  2978. sizeof(struct sgl_handle)); i++) {
  2979. if (arr_index < phba->params.ios_per_ctrl) {
  2980. phba->io_sgl_hndl_base[arr_index] = psgl_handle;
  2981. phba->io_sgl_hndl_avbl++;
  2982. arr_index++;
  2983. } else {
  2984. phba->eh_sgl_hndl_base[arr_index -
  2985. phba->params.ios_per_ctrl] =
  2986. psgl_handle;
  2987. arr_index++;
  2988. phba->eh_sgl_hndl_avbl++;
  2989. }
  2990. psgl_handle++;
  2991. }
  2992. idx++;
  2993. }
  2994. SE_DEBUG(DBG_LVL_8,
  2995. "phba->io_sgl_hndl_avbl=%d"
  2996. "phba->eh_sgl_hndl_avbl=%d\n",
  2997. phba->io_sgl_hndl_avbl,
  2998. phba->eh_sgl_hndl_avbl);
  2999. mem_descr_sg = phba->init_mem;
  3000. mem_descr_sg += HWI_MEM_SGE;
  3001. SE_DEBUG(DBG_LVL_8, "\n mem_descr_sg->num_elements=%d\n",
  3002. mem_descr_sg->num_elements);
  3003. arr_index = 0;
  3004. idx = 0;
  3005. while (idx < mem_descr_sg->num_elements) {
  3006. pfrag = mem_descr_sg->mem_array[idx].virtual_address;
  3007. for (i = 0;
  3008. i < (mem_descr_sg->mem_array[idx].size) /
  3009. (sizeof(struct iscsi_sge) * phba->params.num_sge_per_io);
  3010. i++) {
  3011. if (arr_index < phba->params.ios_per_ctrl)
  3012. psgl_handle = phba->io_sgl_hndl_base[arr_index];
  3013. else
  3014. psgl_handle = phba->eh_sgl_hndl_base[arr_index -
  3015. phba->params.ios_per_ctrl];
  3016. psgl_handle->pfrag = pfrag;
  3017. AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, pfrag, 0);
  3018. AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, pfrag, 0);
  3019. pfrag += phba->params.num_sge_per_io;
  3020. psgl_handle->sgl_index =
  3021. phba->fw_config.iscsi_icd_start + arr_index++;
  3022. }
  3023. idx++;
  3024. }
  3025. phba->io_sgl_free_index = 0;
  3026. phba->io_sgl_alloc_index = 0;
  3027. phba->eh_sgl_free_index = 0;
  3028. phba->eh_sgl_alloc_index = 0;
  3029. return 0;
  3030. }
  3031. static int hba_setup_cid_tbls(struct beiscsi_hba *phba)
  3032. {
  3033. int i, new_cid;
  3034. phba->cid_array = kzalloc(sizeof(void *) * phba->params.cxns_per_ctrl,
  3035. GFP_KERNEL);
  3036. if (!phba->cid_array) {
  3037. shost_printk(KERN_ERR, phba->shost,
  3038. "Failed to allocate memory in "
  3039. "hba_setup_cid_tbls\n");
  3040. return -ENOMEM;
  3041. }
  3042. phba->ep_array = kzalloc(sizeof(struct iscsi_endpoint *) *
  3043. phba->params.cxns_per_ctrl * 2, GFP_KERNEL);
  3044. if (!phba->ep_array) {
  3045. shost_printk(KERN_ERR, phba->shost,
  3046. "Failed to allocate memory in "
  3047. "hba_setup_cid_tbls\n");
  3048. kfree(phba->cid_array);
  3049. return -ENOMEM;
  3050. }
  3051. new_cid = phba->fw_config.iscsi_cid_start;
  3052. for (i = 0; i < phba->params.cxns_per_ctrl; i++) {
  3053. phba->cid_array[i] = new_cid;
  3054. new_cid += 2;
  3055. }
  3056. phba->avlbl_cids = phba->params.cxns_per_ctrl;
  3057. return 0;
  3058. }
  3059. static void hwi_enable_intr(struct beiscsi_hba *phba)
  3060. {
  3061. struct be_ctrl_info *ctrl = &phba->ctrl;
  3062. struct hwi_controller *phwi_ctrlr;
  3063. struct hwi_context_memory *phwi_context;
  3064. struct be_queue_info *eq;
  3065. u8 __iomem *addr;
  3066. u32 reg, i;
  3067. u32 enabled;
  3068. phwi_ctrlr = phba->phwi_ctrlr;
  3069. phwi_context = phwi_ctrlr->phwi_ctxt;
  3070. addr = (u8 __iomem *) ((u8 __iomem *) ctrl->pcicfg +
  3071. PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET);
  3072. reg = ioread32(addr);
  3073. enabled = reg & MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
  3074. if (!enabled) {
  3075. reg |= MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
  3076. SE_DEBUG(DBG_LVL_8, "reg =x%08x addr=%p\n", reg, addr);
  3077. iowrite32(reg, addr);
  3078. }
  3079. if (!phba->msix_enabled) {
  3080. eq = &phwi_context->be_eq[0].q;
  3081. SE_DEBUG(DBG_LVL_8, "eq->id=%d\n", eq->id);
  3082. hwi_ring_eq_db(phba, eq->id, 0, 0, 1, 1);
  3083. } else {
  3084. for (i = 0; i <= phba->num_cpus; i++) {
  3085. eq = &phwi_context->be_eq[i].q;
  3086. SE_DEBUG(DBG_LVL_8, "eq->id=%d\n", eq->id);
  3087. hwi_ring_eq_db(phba, eq->id, 0, 0, 1, 1);
  3088. }
  3089. }
  3090. }
  3091. static void hwi_disable_intr(struct beiscsi_hba *phba)
  3092. {
  3093. struct be_ctrl_info *ctrl = &phba->ctrl;
  3094. u8 __iomem *addr = ctrl->pcicfg + PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET;
  3095. u32 reg = ioread32(addr);
  3096. u32 enabled = reg & MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
  3097. if (enabled) {
  3098. reg &= ~MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
  3099. iowrite32(reg, addr);
  3100. } else
  3101. shost_printk(KERN_WARNING, phba->shost,
  3102. "In hwi_disable_intr, Already Disabled\n");
  3103. }
  3104. static int beiscsi_get_boot_info(struct beiscsi_hba *phba)
  3105. {
  3106. struct be_cmd_resp_get_boot_target *boot_resp;
  3107. struct be_cmd_resp_get_session *session_resp;
  3108. struct be_mcc_wrb *wrb;
  3109. struct be_dma_mem nonemb_cmd;
  3110. unsigned int tag, wrb_num;
  3111. unsigned short status, extd_status;
  3112. struct be_queue_info *mccq = &phba->ctrl.mcc_obj.q;
  3113. int ret = -ENOMEM;
  3114. tag = beiscsi_get_boot_target(phba);
  3115. if (!tag) {
  3116. SE_DEBUG(DBG_LVL_1, "be_cmd_get_mac_addr Failed\n");
  3117. return -EAGAIN;
  3118. } else
  3119. wait_event_interruptible(phba->ctrl.mcc_wait[tag],
  3120. phba->ctrl.mcc_numtag[tag]);
  3121. wrb_num = (phba->ctrl.mcc_numtag[tag] & 0x00FF0000) >> 16;
  3122. extd_status = (phba->ctrl.mcc_numtag[tag] & 0x0000FF00) >> 8;
  3123. status = phba->ctrl.mcc_numtag[tag] & 0x000000FF;
  3124. if (status || extd_status) {
  3125. SE_DEBUG(DBG_LVL_1, "be_cmd_get_mac_addr Failed"
  3126. " status = %d extd_status = %d\n",
  3127. status, extd_status);
  3128. free_mcc_tag(&phba->ctrl, tag);
  3129. return -EBUSY;
  3130. }
  3131. wrb = queue_get_wrb(mccq, wrb_num);
  3132. free_mcc_tag(&phba->ctrl, tag);
  3133. boot_resp = embedded_payload(wrb);
  3134. if (boot_resp->boot_session_handle < 0) {
  3135. shost_printk(KERN_INFO, phba->shost, "No Boot Session.\n");
  3136. return -ENXIO;
  3137. }
  3138. nonemb_cmd.va = pci_alloc_consistent(phba->ctrl.pdev,
  3139. sizeof(*session_resp),
  3140. &nonemb_cmd.dma);
  3141. if (nonemb_cmd.va == NULL) {
  3142. SE_DEBUG(DBG_LVL_1,
  3143. "Failed to allocate memory for"
  3144. "beiscsi_get_session_info\n");
  3145. return -ENOMEM;
  3146. }
  3147. memset(nonemb_cmd.va, 0, sizeof(*session_resp));
  3148. tag = beiscsi_get_session_info(phba,
  3149. boot_resp->boot_session_handle, &nonemb_cmd);
  3150. if (!tag) {
  3151. SE_DEBUG(DBG_LVL_1, "beiscsi_get_session_info"
  3152. " Failed\n");
  3153. goto boot_freemem;
  3154. } else
  3155. wait_event_interruptible(phba->ctrl.mcc_wait[tag],
  3156. phba->ctrl.mcc_numtag[tag]);
  3157. wrb_num = (phba->ctrl.mcc_numtag[tag] & 0x00FF0000) >> 16;
  3158. extd_status = (phba->ctrl.mcc_numtag[tag] & 0x0000FF00) >> 8;
  3159. status = phba->ctrl.mcc_numtag[tag] & 0x000000FF;
  3160. if (status || extd_status) {
  3161. SE_DEBUG(DBG_LVL_1, "beiscsi_get_session_info Failed"
  3162. " status = %d extd_status = %d\n",
  3163. status, extd_status);
  3164. free_mcc_tag(&phba->ctrl, tag);
  3165. goto boot_freemem;
  3166. }
  3167. wrb = queue_get_wrb(mccq, wrb_num);
  3168. free_mcc_tag(&phba->ctrl, tag);
  3169. session_resp = nonemb_cmd.va ;
  3170. memcpy(&phba->boot_sess, &session_resp->session_info,
  3171. sizeof(struct mgmt_session_info));
  3172. ret = 0;
  3173. boot_freemem:
  3174. pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
  3175. nonemb_cmd.va, nonemb_cmd.dma);
  3176. return ret;
  3177. }
  3178. static void beiscsi_boot_release(void *data)
  3179. {
  3180. struct beiscsi_hba *phba = data;
  3181. scsi_host_put(phba->shost);
  3182. }
  3183. static int beiscsi_setup_boot_info(struct beiscsi_hba *phba)
  3184. {
  3185. struct iscsi_boot_kobj *boot_kobj;
  3186. /* get boot info using mgmt cmd */
  3187. if (beiscsi_get_boot_info(phba))
  3188. /* Try to see if we can carry on without this */
  3189. return 0;
  3190. phba->boot_kset = iscsi_boot_create_host_kset(phba->shost->host_no);
  3191. if (!phba->boot_kset)
  3192. return -ENOMEM;
  3193. /* get a ref because the show function will ref the phba */
  3194. if (!scsi_host_get(phba->shost))
  3195. goto free_kset;
  3196. boot_kobj = iscsi_boot_create_target(phba->boot_kset, 0, phba,
  3197. beiscsi_show_boot_tgt_info,
  3198. beiscsi_tgt_get_attr_visibility,
  3199. beiscsi_boot_release);
  3200. if (!boot_kobj)
  3201. goto put_shost;
  3202. if (!scsi_host_get(phba->shost))
  3203. goto free_kset;
  3204. boot_kobj = iscsi_boot_create_initiator(phba->boot_kset, 0, phba,
  3205. beiscsi_show_boot_ini_info,
  3206. beiscsi_ini_get_attr_visibility,
  3207. beiscsi_boot_release);
  3208. if (!boot_kobj)
  3209. goto put_shost;
  3210. if (!scsi_host_get(phba->shost))
  3211. goto free_kset;
  3212. boot_kobj = iscsi_boot_create_ethernet(phba->boot_kset, 0, phba,
  3213. beiscsi_show_boot_eth_info,
  3214. beiscsi_eth_get_attr_visibility,
  3215. beiscsi_boot_release);
  3216. if (!boot_kobj)
  3217. goto put_shost;
  3218. return 0;
  3219. put_shost:
  3220. scsi_host_put(phba->shost);
  3221. free_kset:
  3222. iscsi_boot_destroy_kset(phba->boot_kset);
  3223. return -ENOMEM;
  3224. }
  3225. static int beiscsi_init_port(struct beiscsi_hba *phba)
  3226. {
  3227. int ret;
  3228. ret = beiscsi_init_controller(phba);
  3229. if (ret < 0) {
  3230. shost_printk(KERN_ERR, phba->shost,
  3231. "beiscsi_dev_probe - Failed in"
  3232. "beiscsi_init_controller\n");
  3233. return ret;
  3234. }
  3235. ret = beiscsi_init_sgl_handle(phba);
  3236. if (ret < 0) {
  3237. shost_printk(KERN_ERR, phba->shost,
  3238. "beiscsi_dev_probe - Failed in"
  3239. "beiscsi_init_sgl_handle\n");
  3240. goto do_cleanup_ctrlr;
  3241. }
  3242. if (hba_setup_cid_tbls(phba)) {
  3243. shost_printk(KERN_ERR, phba->shost,
  3244. "Failed in hba_setup_cid_tbls\n");
  3245. kfree(phba->io_sgl_hndl_base);
  3246. kfree(phba->eh_sgl_hndl_base);
  3247. goto do_cleanup_ctrlr;
  3248. }
  3249. return ret;
  3250. do_cleanup_ctrlr:
  3251. hwi_cleanup(phba);
  3252. return ret;
  3253. }
  3254. static void hwi_purge_eq(struct beiscsi_hba *phba)
  3255. {
  3256. struct hwi_controller *phwi_ctrlr;
  3257. struct hwi_context_memory *phwi_context;
  3258. struct be_queue_info *eq;
  3259. struct be_eq_entry *eqe = NULL;
  3260. int i, eq_msix;
  3261. unsigned int num_processed;
  3262. phwi_ctrlr = phba->phwi_ctrlr;
  3263. phwi_context = phwi_ctrlr->phwi_ctxt;
  3264. if (phba->msix_enabled)
  3265. eq_msix = 1;
  3266. else
  3267. eq_msix = 0;
  3268. for (i = 0; i < (phba->num_cpus + eq_msix); i++) {
  3269. eq = &phwi_context->be_eq[i].q;
  3270. eqe = queue_tail_node(eq);
  3271. num_processed = 0;
  3272. while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
  3273. & EQE_VALID_MASK) {
  3274. AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
  3275. queue_tail_inc(eq);
  3276. eqe = queue_tail_node(eq);
  3277. num_processed++;
  3278. }
  3279. if (num_processed)
  3280. hwi_ring_eq_db(phba, eq->id, 1, num_processed, 1, 1);
  3281. }
  3282. }
  3283. static void beiscsi_clean_port(struct beiscsi_hba *phba)
  3284. {
  3285. int mgmt_status;
  3286. mgmt_status = mgmt_epfw_cleanup(phba, CMD_CONNECTION_CHUTE_0);
  3287. if (mgmt_status)
  3288. shost_printk(KERN_WARNING, phba->shost,
  3289. "mgmt_epfw_cleanup FAILED\n");
  3290. hwi_purge_eq(phba);
  3291. hwi_cleanup(phba);
  3292. kfree(phba->io_sgl_hndl_base);
  3293. kfree(phba->eh_sgl_hndl_base);
  3294. kfree(phba->cid_array);
  3295. kfree(phba->ep_array);
  3296. }
  3297. static void beiscsi_cleanup_task(struct iscsi_task *task)
  3298. {
  3299. struct beiscsi_io_task *io_task = task->dd_data;
  3300. struct iscsi_conn *conn = task->conn;
  3301. struct beiscsi_conn *beiscsi_conn = conn->dd_data;
  3302. struct beiscsi_hba *phba = beiscsi_conn->phba;
  3303. struct beiscsi_session *beiscsi_sess = beiscsi_conn->beiscsi_sess;
  3304. struct hwi_wrb_context *pwrb_context;
  3305. struct hwi_controller *phwi_ctrlr;
  3306. phwi_ctrlr = phba->phwi_ctrlr;
  3307. pwrb_context = &phwi_ctrlr->wrb_context[beiscsi_conn->beiscsi_conn_cid
  3308. - phba->fw_config.iscsi_cid_start];
  3309. if (io_task->cmd_bhs) {
  3310. pci_pool_free(beiscsi_sess->bhs_pool, io_task->cmd_bhs,
  3311. io_task->bhs_pa.u.a64.address);
  3312. io_task->cmd_bhs = NULL;
  3313. }
  3314. if (task->sc) {
  3315. if (io_task->pwrb_handle) {
  3316. free_wrb_handle(phba, pwrb_context,
  3317. io_task->pwrb_handle);
  3318. io_task->pwrb_handle = NULL;
  3319. }
  3320. if (io_task->psgl_handle) {
  3321. spin_lock(&phba->io_sgl_lock);
  3322. free_io_sgl_handle(phba, io_task->psgl_handle);
  3323. spin_unlock(&phba->io_sgl_lock);
  3324. io_task->psgl_handle = NULL;
  3325. }
  3326. } else {
  3327. if (!beiscsi_conn->login_in_progress) {
  3328. if (io_task->pwrb_handle) {
  3329. free_wrb_handle(phba, pwrb_context,
  3330. io_task->pwrb_handle);
  3331. io_task->pwrb_handle = NULL;
  3332. }
  3333. if (io_task->psgl_handle) {
  3334. spin_lock(&phba->mgmt_sgl_lock);
  3335. free_mgmt_sgl_handle(phba,
  3336. io_task->psgl_handle);
  3337. spin_unlock(&phba->mgmt_sgl_lock);
  3338. io_task->psgl_handle = NULL;
  3339. }
  3340. }
  3341. }
  3342. }
  3343. void
  3344. beiscsi_offload_connection(struct beiscsi_conn *beiscsi_conn,
  3345. struct beiscsi_offload_params *params)
  3346. {
  3347. struct wrb_handle *pwrb_handle;
  3348. struct iscsi_target_context_update_wrb *pwrb = NULL;
  3349. struct be_mem_descriptor *mem_descr;
  3350. struct beiscsi_hba *phba = beiscsi_conn->phba;
  3351. struct iscsi_task *task = beiscsi_conn->task;
  3352. struct iscsi_session *session = task->conn->session;
  3353. u32 doorbell = 0;
  3354. /*
  3355. * We can always use 0 here because it is reserved by libiscsi for
  3356. * login/startup related tasks.
  3357. */
  3358. beiscsi_conn->login_in_progress = 0;
  3359. spin_lock_bh(&session->lock);
  3360. beiscsi_cleanup_task(task);
  3361. spin_unlock_bh(&session->lock);
  3362. pwrb_handle = alloc_wrb_handle(phba, (beiscsi_conn->beiscsi_conn_cid -
  3363. phba->fw_config.iscsi_cid_start));
  3364. pwrb = (struct iscsi_target_context_update_wrb *)pwrb_handle->pwrb;
  3365. memset(pwrb, 0, sizeof(*pwrb));
  3366. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb,
  3367. max_burst_length, pwrb, params->dw[offsetof
  3368. (struct amap_beiscsi_offload_params,
  3369. max_burst_length) / 32]);
  3370. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb,
  3371. max_send_data_segment_length, pwrb,
  3372. params->dw[offsetof(struct amap_beiscsi_offload_params,
  3373. max_send_data_segment_length) / 32]);
  3374. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb,
  3375. first_burst_length,
  3376. pwrb,
  3377. params->dw[offsetof(struct amap_beiscsi_offload_params,
  3378. first_burst_length) / 32]);
  3379. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, erl, pwrb,
  3380. (params->dw[offsetof(struct amap_beiscsi_offload_params,
  3381. erl) / 32] & OFFLD_PARAMS_ERL));
  3382. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, dde, pwrb,
  3383. (params->dw[offsetof(struct amap_beiscsi_offload_params,
  3384. dde) / 32] & OFFLD_PARAMS_DDE) >> 2);
  3385. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, hde, pwrb,
  3386. (params->dw[offsetof(struct amap_beiscsi_offload_params,
  3387. hde) / 32] & OFFLD_PARAMS_HDE) >> 3);
  3388. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, ir2t, pwrb,
  3389. (params->dw[offsetof(struct amap_beiscsi_offload_params,
  3390. ir2t) / 32] & OFFLD_PARAMS_IR2T) >> 4);
  3391. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, imd, pwrb,
  3392. (params->dw[offsetof(struct amap_beiscsi_offload_params,
  3393. imd) / 32] & OFFLD_PARAMS_IMD) >> 5);
  3394. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, stat_sn,
  3395. pwrb,
  3396. (params->dw[offsetof(struct amap_beiscsi_offload_params,
  3397. exp_statsn) / 32] + 1));
  3398. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, type, pwrb,
  3399. 0x7);
  3400. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, wrb_idx,
  3401. pwrb, pwrb_handle->wrb_index);
  3402. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, ptr2nextwrb,
  3403. pwrb, pwrb_handle->nxt_wrb_index);
  3404. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb,
  3405. session_state, pwrb, 0);
  3406. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, compltonack,
  3407. pwrb, 1);
  3408. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, notpredblq,
  3409. pwrb, 0);
  3410. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, mode, pwrb,
  3411. 0);
  3412. mem_descr = phba->init_mem;
  3413. mem_descr += ISCSI_MEM_GLOBAL_HEADER;
  3414. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb,
  3415. pad_buffer_addr_hi, pwrb,
  3416. mem_descr->mem_array[0].bus_address.u.a32.address_hi);
  3417. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb,
  3418. pad_buffer_addr_lo, pwrb,
  3419. mem_descr->mem_array[0].bus_address.u.a32.address_lo);
  3420. be_dws_le_to_cpu(pwrb, sizeof(struct iscsi_target_context_update_wrb));
  3421. doorbell |= beiscsi_conn->beiscsi_conn_cid & DB_WRB_POST_CID_MASK;
  3422. doorbell |= (pwrb_handle->wrb_index & DB_DEF_PDU_WRB_INDEX_MASK)
  3423. << DB_DEF_PDU_WRB_INDEX_SHIFT;
  3424. doorbell |= 1 << DB_DEF_PDU_NUM_POSTED_SHIFT;
  3425. iowrite32(doorbell, phba->db_va + DB_TXULP0_OFFSET);
  3426. }
  3427. static void beiscsi_parse_pdu(struct iscsi_conn *conn, itt_t itt,
  3428. int *index, int *age)
  3429. {
  3430. *index = (int)itt;
  3431. if (age)
  3432. *age = conn->session->age;
  3433. }
  3434. /**
  3435. * beiscsi_alloc_pdu - allocates pdu and related resources
  3436. * @task: libiscsi task
  3437. * @opcode: opcode of pdu for task
  3438. *
  3439. * This is called with the session lock held. It will allocate
  3440. * the wrb and sgl if needed for the command. And it will prep
  3441. * the pdu's itt. beiscsi_parse_pdu will later translate
  3442. * the pdu itt to the libiscsi task itt.
  3443. */
  3444. static int beiscsi_alloc_pdu(struct iscsi_task *task, uint8_t opcode)
  3445. {
  3446. struct beiscsi_io_task *io_task = task->dd_data;
  3447. struct iscsi_conn *conn = task->conn;
  3448. struct beiscsi_conn *beiscsi_conn = conn->dd_data;
  3449. struct beiscsi_hba *phba = beiscsi_conn->phba;
  3450. struct hwi_wrb_context *pwrb_context;
  3451. struct hwi_controller *phwi_ctrlr;
  3452. itt_t itt;
  3453. struct beiscsi_session *beiscsi_sess = beiscsi_conn->beiscsi_sess;
  3454. dma_addr_t paddr;
  3455. io_task->cmd_bhs = pci_pool_alloc(beiscsi_sess->bhs_pool,
  3456. GFP_ATOMIC, &paddr);
  3457. if (!io_task->cmd_bhs)
  3458. return -ENOMEM;
  3459. io_task->bhs_pa.u.a64.address = paddr;
  3460. io_task->libiscsi_itt = (itt_t)task->itt;
  3461. io_task->conn = beiscsi_conn;
  3462. task->hdr = (struct iscsi_hdr *)&io_task->cmd_bhs->iscsi_hdr;
  3463. task->hdr_max = sizeof(struct be_cmd_bhs);
  3464. io_task->psgl_handle = NULL;
  3465. io_task->pwrb_handle = NULL;
  3466. if (task->sc) {
  3467. spin_lock(&phba->io_sgl_lock);
  3468. io_task->psgl_handle = alloc_io_sgl_handle(phba);
  3469. spin_unlock(&phba->io_sgl_lock);
  3470. if (!io_task->psgl_handle)
  3471. goto free_hndls;
  3472. io_task->pwrb_handle = alloc_wrb_handle(phba,
  3473. beiscsi_conn->beiscsi_conn_cid -
  3474. phba->fw_config.iscsi_cid_start);
  3475. if (!io_task->pwrb_handle)
  3476. goto free_io_hndls;
  3477. } else {
  3478. io_task->scsi_cmnd = NULL;
  3479. if ((opcode & ISCSI_OPCODE_MASK) == ISCSI_OP_LOGIN) {
  3480. if (!beiscsi_conn->login_in_progress) {
  3481. spin_lock(&phba->mgmt_sgl_lock);
  3482. io_task->psgl_handle = (struct sgl_handle *)
  3483. alloc_mgmt_sgl_handle(phba);
  3484. spin_unlock(&phba->mgmt_sgl_lock);
  3485. if (!io_task->psgl_handle)
  3486. goto free_hndls;
  3487. beiscsi_conn->login_in_progress = 1;
  3488. beiscsi_conn->plogin_sgl_handle =
  3489. io_task->psgl_handle;
  3490. io_task->pwrb_handle =
  3491. alloc_wrb_handle(phba,
  3492. beiscsi_conn->beiscsi_conn_cid -
  3493. phba->fw_config.iscsi_cid_start);
  3494. if (!io_task->pwrb_handle)
  3495. goto free_io_hndls;
  3496. beiscsi_conn->plogin_wrb_handle =
  3497. io_task->pwrb_handle;
  3498. } else {
  3499. io_task->psgl_handle =
  3500. beiscsi_conn->plogin_sgl_handle;
  3501. io_task->pwrb_handle =
  3502. beiscsi_conn->plogin_wrb_handle;
  3503. }
  3504. beiscsi_conn->task = task;
  3505. } else {
  3506. spin_lock(&phba->mgmt_sgl_lock);
  3507. io_task->psgl_handle = alloc_mgmt_sgl_handle(phba);
  3508. spin_unlock(&phba->mgmt_sgl_lock);
  3509. if (!io_task->psgl_handle)
  3510. goto free_hndls;
  3511. io_task->pwrb_handle =
  3512. alloc_wrb_handle(phba,
  3513. beiscsi_conn->beiscsi_conn_cid -
  3514. phba->fw_config.iscsi_cid_start);
  3515. if (!io_task->pwrb_handle)
  3516. goto free_mgmt_hndls;
  3517. }
  3518. }
  3519. itt = (itt_t) cpu_to_be32(((unsigned int)io_task->pwrb_handle->
  3520. wrb_index << 16) | (unsigned int)
  3521. (io_task->psgl_handle->sgl_index));
  3522. io_task->pwrb_handle->pio_handle = task;
  3523. io_task->cmd_bhs->iscsi_hdr.itt = itt;
  3524. return 0;
  3525. free_io_hndls:
  3526. spin_lock(&phba->io_sgl_lock);
  3527. free_io_sgl_handle(phba, io_task->psgl_handle);
  3528. spin_unlock(&phba->io_sgl_lock);
  3529. goto free_hndls;
  3530. free_mgmt_hndls:
  3531. spin_lock(&phba->mgmt_sgl_lock);
  3532. free_mgmt_sgl_handle(phba, io_task->psgl_handle);
  3533. spin_unlock(&phba->mgmt_sgl_lock);
  3534. free_hndls:
  3535. phwi_ctrlr = phba->phwi_ctrlr;
  3536. pwrb_context = &phwi_ctrlr->wrb_context[
  3537. beiscsi_conn->beiscsi_conn_cid -
  3538. phba->fw_config.iscsi_cid_start];
  3539. if (io_task->pwrb_handle)
  3540. free_wrb_handle(phba, pwrb_context, io_task->pwrb_handle);
  3541. io_task->pwrb_handle = NULL;
  3542. pci_pool_free(beiscsi_sess->bhs_pool, io_task->cmd_bhs,
  3543. io_task->bhs_pa.u.a64.address);
  3544. io_task->cmd_bhs = NULL;
  3545. SE_DEBUG(DBG_LVL_1, "Alloc of SGL_ICD Failed\n");
  3546. return -ENOMEM;
  3547. }
  3548. static int beiscsi_iotask(struct iscsi_task *task, struct scatterlist *sg,
  3549. unsigned int num_sg, unsigned int xferlen,
  3550. unsigned int writedir)
  3551. {
  3552. struct beiscsi_io_task *io_task = task->dd_data;
  3553. struct iscsi_conn *conn = task->conn;
  3554. struct beiscsi_conn *beiscsi_conn = conn->dd_data;
  3555. struct beiscsi_hba *phba = beiscsi_conn->phba;
  3556. struct iscsi_wrb *pwrb = NULL;
  3557. unsigned int doorbell = 0;
  3558. pwrb = io_task->pwrb_handle->pwrb;
  3559. io_task->cmd_bhs->iscsi_hdr.exp_statsn = 0;
  3560. io_task->bhs_len = sizeof(struct be_cmd_bhs);
  3561. if (writedir) {
  3562. memset(&io_task->cmd_bhs->iscsi_data_pdu, 0, 48);
  3563. AMAP_SET_BITS(struct amap_pdu_data_out, itt,
  3564. &io_task->cmd_bhs->iscsi_data_pdu,
  3565. (unsigned int)io_task->cmd_bhs->iscsi_hdr.itt);
  3566. AMAP_SET_BITS(struct amap_pdu_data_out, opcode,
  3567. &io_task->cmd_bhs->iscsi_data_pdu,
  3568. ISCSI_OPCODE_SCSI_DATA_OUT);
  3569. AMAP_SET_BITS(struct amap_pdu_data_out, final_bit,
  3570. &io_task->cmd_bhs->iscsi_data_pdu, 1);
  3571. AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb,
  3572. INI_WR_CMD);
  3573. AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 1);
  3574. } else {
  3575. AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb,
  3576. INI_RD_CMD);
  3577. AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 0);
  3578. }
  3579. memcpy(&io_task->cmd_bhs->iscsi_data_pdu.
  3580. dw[offsetof(struct amap_pdu_data_out, lun) / 32],
  3581. &io_task->cmd_bhs->iscsi_hdr.lun, sizeof(struct scsi_lun));
  3582. AMAP_SET_BITS(struct amap_iscsi_wrb, lun, pwrb,
  3583. cpu_to_be16(*(unsigned short *)
  3584. &io_task->cmd_bhs->iscsi_hdr.lun));
  3585. AMAP_SET_BITS(struct amap_iscsi_wrb, r2t_exp_dtl, pwrb, xferlen);
  3586. AMAP_SET_BITS(struct amap_iscsi_wrb, wrb_idx, pwrb,
  3587. io_task->pwrb_handle->wrb_index);
  3588. AMAP_SET_BITS(struct amap_iscsi_wrb, cmdsn_itt, pwrb,
  3589. be32_to_cpu(task->cmdsn));
  3590. AMAP_SET_BITS(struct amap_iscsi_wrb, sgl_icd_idx, pwrb,
  3591. io_task->psgl_handle->sgl_index);
  3592. hwi_write_sgl(pwrb, sg, num_sg, io_task);
  3593. AMAP_SET_BITS(struct amap_iscsi_wrb, ptr2nextwrb, pwrb,
  3594. io_task->pwrb_handle->nxt_wrb_index);
  3595. be_dws_le_to_cpu(pwrb, sizeof(struct iscsi_wrb));
  3596. doorbell |= beiscsi_conn->beiscsi_conn_cid & DB_WRB_POST_CID_MASK;
  3597. doorbell |= (io_task->pwrb_handle->wrb_index &
  3598. DB_DEF_PDU_WRB_INDEX_MASK) << DB_DEF_PDU_WRB_INDEX_SHIFT;
  3599. doorbell |= 1 << DB_DEF_PDU_NUM_POSTED_SHIFT;
  3600. iowrite32(doorbell, phba->db_va + DB_TXULP0_OFFSET);
  3601. return 0;
  3602. }
  3603. static int beiscsi_mtask(struct iscsi_task *task)
  3604. {
  3605. struct beiscsi_io_task *io_task = task->dd_data;
  3606. struct iscsi_conn *conn = task->conn;
  3607. struct beiscsi_conn *beiscsi_conn = conn->dd_data;
  3608. struct beiscsi_hba *phba = beiscsi_conn->phba;
  3609. struct iscsi_wrb *pwrb = NULL;
  3610. unsigned int doorbell = 0;
  3611. unsigned int cid;
  3612. cid = beiscsi_conn->beiscsi_conn_cid;
  3613. pwrb = io_task->pwrb_handle->pwrb;
  3614. memset(pwrb, 0, sizeof(*pwrb));
  3615. AMAP_SET_BITS(struct amap_iscsi_wrb, cmdsn_itt, pwrb,
  3616. be32_to_cpu(task->cmdsn));
  3617. AMAP_SET_BITS(struct amap_iscsi_wrb, wrb_idx, pwrb,
  3618. io_task->pwrb_handle->wrb_index);
  3619. AMAP_SET_BITS(struct amap_iscsi_wrb, sgl_icd_idx, pwrb,
  3620. io_task->psgl_handle->sgl_index);
  3621. switch (task->hdr->opcode & ISCSI_OPCODE_MASK) {
  3622. case ISCSI_OP_LOGIN:
  3623. AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb,
  3624. TGT_DM_CMD);
  3625. AMAP_SET_BITS(struct amap_iscsi_wrb, dmsg, pwrb, 0);
  3626. AMAP_SET_BITS(struct amap_iscsi_wrb, cmdsn_itt, pwrb, 1);
  3627. hwi_write_buffer(pwrb, task);
  3628. break;
  3629. case ISCSI_OP_NOOP_OUT:
  3630. if (task->hdr->ttt != ISCSI_RESERVED_TAG) {
  3631. AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb,
  3632. TGT_DM_CMD);
  3633. AMAP_SET_BITS(struct amap_iscsi_wrb, cmdsn_itt,
  3634. pwrb, 0);
  3635. AMAP_SET_BITS(struct amap_iscsi_wrb, dmsg, pwrb, 1);
  3636. } else {
  3637. AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb,
  3638. INI_RD_CMD);
  3639. AMAP_SET_BITS(struct amap_iscsi_wrb, dmsg, pwrb, 0);
  3640. }
  3641. hwi_write_buffer(pwrb, task);
  3642. break;
  3643. case ISCSI_OP_TEXT:
  3644. AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb,
  3645. TGT_DM_CMD);
  3646. AMAP_SET_BITS(struct amap_iscsi_wrb, dmsg, pwrb, 0);
  3647. hwi_write_buffer(pwrb, task);
  3648. break;
  3649. case ISCSI_OP_SCSI_TMFUNC:
  3650. AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb,
  3651. INI_TMF_CMD);
  3652. AMAP_SET_BITS(struct amap_iscsi_wrb, dmsg, pwrb, 0);
  3653. hwi_write_buffer(pwrb, task);
  3654. break;
  3655. case ISCSI_OP_LOGOUT:
  3656. AMAP_SET_BITS(struct amap_iscsi_wrb, dmsg, pwrb, 0);
  3657. AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb,
  3658. HWH_TYPE_LOGOUT);
  3659. hwi_write_buffer(pwrb, task);
  3660. break;
  3661. default:
  3662. SE_DEBUG(DBG_LVL_1, "opcode =%d Not supported\n",
  3663. task->hdr->opcode & ISCSI_OPCODE_MASK);
  3664. return -EINVAL;
  3665. }
  3666. AMAP_SET_BITS(struct amap_iscsi_wrb, r2t_exp_dtl, pwrb,
  3667. task->data_count);
  3668. AMAP_SET_BITS(struct amap_iscsi_wrb, ptr2nextwrb, pwrb,
  3669. io_task->pwrb_handle->nxt_wrb_index);
  3670. be_dws_le_to_cpu(pwrb, sizeof(struct iscsi_wrb));
  3671. doorbell |= cid & DB_WRB_POST_CID_MASK;
  3672. doorbell |= (io_task->pwrb_handle->wrb_index &
  3673. DB_DEF_PDU_WRB_INDEX_MASK) << DB_DEF_PDU_WRB_INDEX_SHIFT;
  3674. doorbell |= 1 << DB_DEF_PDU_NUM_POSTED_SHIFT;
  3675. iowrite32(doorbell, phba->db_va + DB_TXULP0_OFFSET);
  3676. return 0;
  3677. }
  3678. static int beiscsi_task_xmit(struct iscsi_task *task)
  3679. {
  3680. struct beiscsi_io_task *io_task = task->dd_data;
  3681. struct scsi_cmnd *sc = task->sc;
  3682. struct scatterlist *sg;
  3683. int num_sg;
  3684. unsigned int writedir = 0, xferlen = 0;
  3685. if (!sc)
  3686. return beiscsi_mtask(task);
  3687. io_task->scsi_cmnd = sc;
  3688. num_sg = scsi_dma_map(sc);
  3689. if (num_sg < 0) {
  3690. SE_DEBUG(DBG_LVL_1, " scsi_dma_map Failed\n")
  3691. return num_sg;
  3692. }
  3693. xferlen = scsi_bufflen(sc);
  3694. sg = scsi_sglist(sc);
  3695. if (sc->sc_data_direction == DMA_TO_DEVICE) {
  3696. writedir = 1;
  3697. SE_DEBUG(DBG_LVL_4, "task->imm_count=0x%08x\n",
  3698. task->imm_count);
  3699. } else
  3700. writedir = 0;
  3701. return beiscsi_iotask(task, sg, num_sg, xferlen, writedir);
  3702. }
  3703. static void beiscsi_quiesce(struct beiscsi_hba *phba)
  3704. {
  3705. struct hwi_controller *phwi_ctrlr;
  3706. struct hwi_context_memory *phwi_context;
  3707. struct be_eq_obj *pbe_eq;
  3708. unsigned int i, msix_vec;
  3709. u8 *real_offset = 0;
  3710. u32 value = 0;
  3711. phwi_ctrlr = phba->phwi_ctrlr;
  3712. phwi_context = phwi_ctrlr->phwi_ctxt;
  3713. hwi_disable_intr(phba);
  3714. if (phba->msix_enabled) {
  3715. for (i = 0; i <= phba->num_cpus; i++) {
  3716. msix_vec = phba->msix_entries[i].vector;
  3717. free_irq(msix_vec, &phwi_context->be_eq[i]);
  3718. kfree(phba->msi_name[i]);
  3719. }
  3720. } else
  3721. if (phba->pcidev->irq)
  3722. free_irq(phba->pcidev->irq, phba);
  3723. pci_disable_msix(phba->pcidev);
  3724. destroy_workqueue(phba->wq);
  3725. if (blk_iopoll_enabled)
  3726. for (i = 0; i < phba->num_cpus; i++) {
  3727. pbe_eq = &phwi_context->be_eq[i];
  3728. blk_iopoll_disable(&pbe_eq->iopoll);
  3729. }
  3730. beiscsi_clean_port(phba);
  3731. beiscsi_free_mem(phba);
  3732. real_offset = (u8 *)phba->csr_va + MPU_EP_SEMAPHORE;
  3733. value = readl((void *)real_offset);
  3734. if (value & 0x00010000) {
  3735. value &= 0xfffeffff;
  3736. writel(value, (void *)real_offset);
  3737. }
  3738. beiscsi_unmap_pci_function(phba);
  3739. pci_free_consistent(phba->pcidev,
  3740. phba->ctrl.mbox_mem_alloced.size,
  3741. phba->ctrl.mbox_mem_alloced.va,
  3742. phba->ctrl.mbox_mem_alloced.dma);
  3743. }
  3744. static void beiscsi_remove(struct pci_dev *pcidev)
  3745. {
  3746. struct beiscsi_hba *phba = NULL;
  3747. phba = pci_get_drvdata(pcidev);
  3748. if (!phba) {
  3749. dev_err(&pcidev->dev, "beiscsi_remove called with no phba\n");
  3750. return;
  3751. }
  3752. beiscsi_quiesce(phba);
  3753. iscsi_boot_destroy_kset(phba->boot_kset);
  3754. iscsi_host_remove(phba->shost);
  3755. pci_dev_put(phba->pcidev);
  3756. iscsi_host_free(phba->shost);
  3757. pci_disable_device(pcidev);
  3758. }
  3759. static void beiscsi_shutdown(struct pci_dev *pcidev)
  3760. {
  3761. struct beiscsi_hba *phba = NULL;
  3762. phba = (struct beiscsi_hba *)pci_get_drvdata(pcidev);
  3763. if (!phba) {
  3764. dev_err(&pcidev->dev, "beiscsi_shutdown called with no phba\n");
  3765. return;
  3766. }
  3767. beiscsi_quiesce(phba);
  3768. pci_disable_device(pcidev);
  3769. }
  3770. static void beiscsi_msix_enable(struct beiscsi_hba *phba)
  3771. {
  3772. int i, status;
  3773. for (i = 0; i <= phba->num_cpus; i++)
  3774. phba->msix_entries[i].entry = i;
  3775. status = pci_enable_msix(phba->pcidev, phba->msix_entries,
  3776. (phba->num_cpus + 1));
  3777. if (!status)
  3778. phba->msix_enabled = true;
  3779. return;
  3780. }
  3781. static int __devinit beiscsi_dev_probe(struct pci_dev *pcidev,
  3782. const struct pci_device_id *id)
  3783. {
  3784. struct beiscsi_hba *phba = NULL;
  3785. struct hwi_controller *phwi_ctrlr;
  3786. struct hwi_context_memory *phwi_context;
  3787. struct be_eq_obj *pbe_eq;
  3788. int ret, num_cpus, i;
  3789. u8 *real_offset = 0;
  3790. u32 value = 0;
  3791. ret = beiscsi_enable_pci(pcidev);
  3792. if (ret < 0) {
  3793. dev_err(&pcidev->dev, "beiscsi_dev_probe-"
  3794. " Failed to enable pci device\n");
  3795. return ret;
  3796. }
  3797. phba = beiscsi_hba_alloc(pcidev);
  3798. if (!phba) {
  3799. dev_err(&pcidev->dev, "beiscsi_dev_probe-"
  3800. " Failed in beiscsi_hba_alloc\n");
  3801. goto disable_pci;
  3802. }
  3803. switch (pcidev->device) {
  3804. case BE_DEVICE_ID1:
  3805. case OC_DEVICE_ID1:
  3806. case OC_DEVICE_ID2:
  3807. phba->generation = BE_GEN2;
  3808. break;
  3809. case BE_DEVICE_ID2:
  3810. case OC_DEVICE_ID3:
  3811. phba->generation = BE_GEN3;
  3812. break;
  3813. default:
  3814. phba->generation = 0;
  3815. }
  3816. if (enable_msix)
  3817. num_cpus = find_num_cpus();
  3818. else
  3819. num_cpus = 1;
  3820. phba->num_cpus = num_cpus;
  3821. SE_DEBUG(DBG_LVL_8, "num_cpus = %d\n", phba->num_cpus);
  3822. if (enable_msix) {
  3823. beiscsi_msix_enable(phba);
  3824. if (!phba->msix_enabled)
  3825. phba->num_cpus = 1;
  3826. }
  3827. ret = be_ctrl_init(phba, pcidev);
  3828. if (ret) {
  3829. shost_printk(KERN_ERR, phba->shost, "beiscsi_dev_probe-"
  3830. "Failed in be_ctrl_init\n");
  3831. goto hba_free;
  3832. }
  3833. if (!num_hba) {
  3834. real_offset = (u8 *)phba->csr_va + MPU_EP_SEMAPHORE;
  3835. value = readl((void *)real_offset);
  3836. if (value & 0x00010000) {
  3837. gcrashmode++;
  3838. shost_printk(KERN_ERR, phba->shost,
  3839. "Loading Driver in crashdump mode\n");
  3840. ret = beiscsi_cmd_reset_function(phba);
  3841. if (ret) {
  3842. shost_printk(KERN_ERR, phba->shost,
  3843. "Reset Failed. Aborting Crashdump\n");
  3844. goto hba_free;
  3845. }
  3846. ret = be_chk_reset_complete(phba);
  3847. if (ret) {
  3848. shost_printk(KERN_ERR, phba->shost,
  3849. "Failed to get out of reset."
  3850. "Aborting Crashdump\n");
  3851. goto hba_free;
  3852. }
  3853. } else {
  3854. value |= 0x00010000;
  3855. writel(value, (void *)real_offset);
  3856. num_hba++;
  3857. }
  3858. }
  3859. spin_lock_init(&phba->io_sgl_lock);
  3860. spin_lock_init(&phba->mgmt_sgl_lock);
  3861. spin_lock_init(&phba->isr_lock);
  3862. ret = mgmt_get_fw_config(&phba->ctrl, phba);
  3863. if (ret != 0) {
  3864. shost_printk(KERN_ERR, phba->shost,
  3865. "Error getting fw config\n");
  3866. goto free_port;
  3867. }
  3868. phba->shost->max_id = phba->fw_config.iscsi_cid_count;
  3869. beiscsi_get_params(phba);
  3870. phba->shost->can_queue = phba->params.ios_per_ctrl;
  3871. ret = beiscsi_init_port(phba);
  3872. if (ret < 0) {
  3873. shost_printk(KERN_ERR, phba->shost, "beiscsi_dev_probe-"
  3874. "Failed in beiscsi_init_port\n");
  3875. goto free_port;
  3876. }
  3877. for (i = 0; i < MAX_MCC_CMD ; i++) {
  3878. init_waitqueue_head(&phba->ctrl.mcc_wait[i + 1]);
  3879. phba->ctrl.mcc_tag[i] = i + 1;
  3880. phba->ctrl.mcc_numtag[i + 1] = 0;
  3881. phba->ctrl.mcc_tag_available++;
  3882. }
  3883. phba->ctrl.mcc_alloc_index = phba->ctrl.mcc_free_index = 0;
  3884. snprintf(phba->wq_name, sizeof(phba->wq_name), "beiscsi_q_irq%u",
  3885. phba->shost->host_no);
  3886. phba->wq = alloc_workqueue(phba->wq_name, WQ_MEM_RECLAIM, 1);
  3887. if (!phba->wq) {
  3888. shost_printk(KERN_ERR, phba->shost, "beiscsi_dev_probe-"
  3889. "Failed to allocate work queue\n");
  3890. goto free_twq;
  3891. }
  3892. INIT_WORK(&phba->work_cqs, beiscsi_process_all_cqs);
  3893. phwi_ctrlr = phba->phwi_ctrlr;
  3894. phwi_context = phwi_ctrlr->phwi_ctxt;
  3895. if (blk_iopoll_enabled) {
  3896. for (i = 0; i < phba->num_cpus; i++) {
  3897. pbe_eq = &phwi_context->be_eq[i];
  3898. blk_iopoll_init(&pbe_eq->iopoll, be_iopoll_budget,
  3899. be_iopoll);
  3900. blk_iopoll_enable(&pbe_eq->iopoll);
  3901. }
  3902. }
  3903. ret = beiscsi_init_irqs(phba);
  3904. if (ret < 0) {
  3905. shost_printk(KERN_ERR, phba->shost, "beiscsi_dev_probe-"
  3906. "Failed to beiscsi_init_irqs\n");
  3907. goto free_blkenbld;
  3908. }
  3909. hwi_enable_intr(phba);
  3910. if (beiscsi_setup_boot_info(phba))
  3911. /*
  3912. * log error but continue, because we may not be using
  3913. * iscsi boot.
  3914. */
  3915. shost_printk(KERN_ERR, phba->shost, "Could not set up "
  3916. "iSCSI boot info.");
  3917. SE_DEBUG(DBG_LVL_8, "\n\n\n SUCCESS - DRIVER LOADED\n\n\n");
  3918. return 0;
  3919. free_blkenbld:
  3920. destroy_workqueue(phba->wq);
  3921. if (blk_iopoll_enabled)
  3922. for (i = 0; i < phba->num_cpus; i++) {
  3923. pbe_eq = &phwi_context->be_eq[i];
  3924. blk_iopoll_disable(&pbe_eq->iopoll);
  3925. }
  3926. free_twq:
  3927. beiscsi_clean_port(phba);
  3928. beiscsi_free_mem(phba);
  3929. free_port:
  3930. real_offset = (u8 *)phba->csr_va + MPU_EP_SEMAPHORE;
  3931. value = readl((void *)real_offset);
  3932. if (value & 0x00010000) {
  3933. value &= 0xfffeffff;
  3934. writel(value, (void *)real_offset);
  3935. }
  3936. pci_free_consistent(phba->pcidev,
  3937. phba->ctrl.mbox_mem_alloced.size,
  3938. phba->ctrl.mbox_mem_alloced.va,
  3939. phba->ctrl.mbox_mem_alloced.dma);
  3940. beiscsi_unmap_pci_function(phba);
  3941. hba_free:
  3942. if (phba->msix_enabled)
  3943. pci_disable_msix(phba->pcidev);
  3944. iscsi_host_remove(phba->shost);
  3945. pci_dev_put(phba->pcidev);
  3946. iscsi_host_free(phba->shost);
  3947. disable_pci:
  3948. pci_disable_device(pcidev);
  3949. return ret;
  3950. }
  3951. struct iscsi_transport beiscsi_iscsi_transport = {
  3952. .owner = THIS_MODULE,
  3953. .name = DRV_NAME,
  3954. .caps = CAP_RECOVERY_L0 | CAP_HDRDGST | CAP_TEXT_NEGO |
  3955. CAP_MULTI_R2T | CAP_DATADGST | CAP_DATA_PATH_OFFLOAD,
  3956. .create_session = beiscsi_session_create,
  3957. .destroy_session = beiscsi_session_destroy,
  3958. .create_conn = beiscsi_conn_create,
  3959. .bind_conn = beiscsi_conn_bind,
  3960. .destroy_conn = iscsi_conn_teardown,
  3961. .attr_is_visible = be2iscsi_attr_is_visible,
  3962. .set_param = beiscsi_set_param,
  3963. .get_conn_param = iscsi_conn_get_param,
  3964. .get_session_param = iscsi_session_get_param,
  3965. .get_host_param = beiscsi_get_host_param,
  3966. .start_conn = beiscsi_conn_start,
  3967. .stop_conn = iscsi_conn_stop,
  3968. .send_pdu = iscsi_conn_send_pdu,
  3969. .xmit_task = beiscsi_task_xmit,
  3970. .cleanup_task = beiscsi_cleanup_task,
  3971. .alloc_pdu = beiscsi_alloc_pdu,
  3972. .parse_pdu_itt = beiscsi_parse_pdu,
  3973. .get_stats = beiscsi_conn_get_stats,
  3974. .get_ep_param = beiscsi_ep_get_param,
  3975. .ep_connect = beiscsi_ep_connect,
  3976. .ep_poll = beiscsi_ep_poll,
  3977. .ep_disconnect = beiscsi_ep_disconnect,
  3978. .session_recovery_timedout = iscsi_session_recovery_timedout,
  3979. };
  3980. static struct pci_driver beiscsi_pci_driver = {
  3981. .name = DRV_NAME,
  3982. .probe = beiscsi_dev_probe,
  3983. .remove = beiscsi_remove,
  3984. .shutdown = beiscsi_shutdown,
  3985. .id_table = beiscsi_pci_id_table
  3986. };
  3987. static int __init beiscsi_module_init(void)
  3988. {
  3989. int ret;
  3990. beiscsi_scsi_transport =
  3991. iscsi_register_transport(&beiscsi_iscsi_transport);
  3992. if (!beiscsi_scsi_transport) {
  3993. SE_DEBUG(DBG_LVL_1,
  3994. "beiscsi_module_init - Unable to register beiscsi"
  3995. "transport.\n");
  3996. return -ENOMEM;
  3997. }
  3998. SE_DEBUG(DBG_LVL_8, "In beiscsi_module_init, tt=%p\n",
  3999. &beiscsi_iscsi_transport);
  4000. ret = pci_register_driver(&beiscsi_pci_driver);
  4001. if (ret) {
  4002. SE_DEBUG(DBG_LVL_1,
  4003. "beiscsi_module_init - Unable to register"
  4004. "beiscsi pci driver.\n");
  4005. goto unregister_iscsi_transport;
  4006. }
  4007. return 0;
  4008. unregister_iscsi_transport:
  4009. iscsi_unregister_transport(&beiscsi_iscsi_transport);
  4010. return ret;
  4011. }
  4012. static void __exit beiscsi_module_exit(void)
  4013. {
  4014. pci_unregister_driver(&beiscsi_pci_driver);
  4015. iscsi_unregister_transport(&beiscsi_iscsi_transport);
  4016. }
  4017. module_init(beiscsi_module_init);
  4018. module_exit(beiscsi_module_exit);