smsc95xx.c 34 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324
  1. /***************************************************************************
  2. *
  3. * Copyright (C) 2007-2008 SMSC
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License
  7. * as published by the Free Software Foundation; either version 2
  8. * of the License, or (at your option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  18. *
  19. *****************************************************************************/
  20. #include <linux/module.h>
  21. #include <linux/kmod.h>
  22. #include <linux/init.h>
  23. #include <linux/netdevice.h>
  24. #include <linux/etherdevice.h>
  25. #include <linux/ethtool.h>
  26. #include <linux/mii.h>
  27. #include <linux/usb.h>
  28. #include <linux/crc32.h>
  29. #include <linux/usb/usbnet.h>
  30. #include "smsc95xx.h"
  31. #define SMSC_CHIPNAME "smsc95xx"
  32. #define SMSC_DRIVER_VERSION "1.0.4"
  33. #define HS_USB_PKT_SIZE (512)
  34. #define FS_USB_PKT_SIZE (64)
  35. #define DEFAULT_HS_BURST_CAP_SIZE (16 * 1024 + 5 * HS_USB_PKT_SIZE)
  36. #define DEFAULT_FS_BURST_CAP_SIZE (6 * 1024 + 33 * FS_USB_PKT_SIZE)
  37. #define DEFAULT_BULK_IN_DELAY (0x00002000)
  38. #define MAX_SINGLE_PACKET_SIZE (2048)
  39. #define LAN95XX_EEPROM_MAGIC (0x9500)
  40. #define EEPROM_MAC_OFFSET (0x01)
  41. #define DEFAULT_TX_CSUM_ENABLE (true)
  42. #define DEFAULT_RX_CSUM_ENABLE (true)
  43. #define SMSC95XX_INTERNAL_PHY_ID (1)
  44. #define SMSC95XX_TX_OVERHEAD (8)
  45. #define SMSC95XX_TX_OVERHEAD_CSUM (12)
  46. struct smsc95xx_priv {
  47. u32 mac_cr;
  48. spinlock_t mac_cr_lock;
  49. bool use_tx_csum;
  50. bool use_rx_csum;
  51. };
  52. struct usb_context {
  53. struct usb_ctrlrequest req;
  54. struct usbnet *dev;
  55. };
  56. static int turbo_mode = true;
  57. module_param(turbo_mode, bool, 0644);
  58. MODULE_PARM_DESC(turbo_mode, "Enable multiple frames per Rx transaction");
  59. static int smsc95xx_read_reg(struct usbnet *dev, u32 index, u32 *data)
  60. {
  61. u32 *buf = kmalloc(4, GFP_KERNEL);
  62. int ret;
  63. BUG_ON(!dev);
  64. if (!buf)
  65. return -ENOMEM;
  66. ret = usb_control_msg(dev->udev, usb_rcvctrlpipe(dev->udev, 0),
  67. USB_VENDOR_REQUEST_READ_REGISTER,
  68. USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  69. 00, index, buf, 4, USB_CTRL_GET_TIMEOUT);
  70. if (unlikely(ret < 0))
  71. netdev_warn(dev->net, "Failed to read register index 0x%08x\n", index);
  72. le32_to_cpus(buf);
  73. *data = *buf;
  74. kfree(buf);
  75. return ret;
  76. }
  77. static int smsc95xx_write_reg(struct usbnet *dev, u32 index, u32 data)
  78. {
  79. u32 *buf = kmalloc(4, GFP_KERNEL);
  80. int ret;
  81. BUG_ON(!dev);
  82. if (!buf)
  83. return -ENOMEM;
  84. *buf = data;
  85. cpu_to_le32s(buf);
  86. ret = usb_control_msg(dev->udev, usb_sndctrlpipe(dev->udev, 0),
  87. USB_VENDOR_REQUEST_WRITE_REGISTER,
  88. USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  89. 00, index, buf, 4, USB_CTRL_SET_TIMEOUT);
  90. if (unlikely(ret < 0))
  91. netdev_warn(dev->net, "Failed to write register index 0x%08x\n", index);
  92. kfree(buf);
  93. return ret;
  94. }
  95. /* Loop until the read is completed with timeout
  96. * called with phy_mutex held */
  97. static int smsc95xx_phy_wait_not_busy(struct usbnet *dev)
  98. {
  99. unsigned long start_time = jiffies;
  100. u32 val;
  101. do {
  102. smsc95xx_read_reg(dev, MII_ADDR, &val);
  103. if (!(val & MII_BUSY_))
  104. return 0;
  105. } while (!time_after(jiffies, start_time + HZ));
  106. return -EIO;
  107. }
  108. static int smsc95xx_mdio_read(struct net_device *netdev, int phy_id, int idx)
  109. {
  110. struct usbnet *dev = netdev_priv(netdev);
  111. u32 val, addr;
  112. mutex_lock(&dev->phy_mutex);
  113. /* confirm MII not busy */
  114. if (smsc95xx_phy_wait_not_busy(dev)) {
  115. netdev_warn(dev->net, "MII is busy in smsc95xx_mdio_read\n");
  116. mutex_unlock(&dev->phy_mutex);
  117. return -EIO;
  118. }
  119. /* set the address, index & direction (read from PHY) */
  120. phy_id &= dev->mii.phy_id_mask;
  121. idx &= dev->mii.reg_num_mask;
  122. addr = (phy_id << 11) | (idx << 6) | MII_READ_;
  123. smsc95xx_write_reg(dev, MII_ADDR, addr);
  124. if (smsc95xx_phy_wait_not_busy(dev)) {
  125. netdev_warn(dev->net, "Timed out reading MII reg %02X\n", idx);
  126. mutex_unlock(&dev->phy_mutex);
  127. return -EIO;
  128. }
  129. smsc95xx_read_reg(dev, MII_DATA, &val);
  130. mutex_unlock(&dev->phy_mutex);
  131. return (u16)(val & 0xFFFF);
  132. }
  133. static void smsc95xx_mdio_write(struct net_device *netdev, int phy_id, int idx,
  134. int regval)
  135. {
  136. struct usbnet *dev = netdev_priv(netdev);
  137. u32 val, addr;
  138. mutex_lock(&dev->phy_mutex);
  139. /* confirm MII not busy */
  140. if (smsc95xx_phy_wait_not_busy(dev)) {
  141. netdev_warn(dev->net, "MII is busy in smsc95xx_mdio_write\n");
  142. mutex_unlock(&dev->phy_mutex);
  143. return;
  144. }
  145. val = regval;
  146. smsc95xx_write_reg(dev, MII_DATA, val);
  147. /* set the address, index & direction (write to PHY) */
  148. phy_id &= dev->mii.phy_id_mask;
  149. idx &= dev->mii.reg_num_mask;
  150. addr = (phy_id << 11) | (idx << 6) | MII_WRITE_;
  151. smsc95xx_write_reg(dev, MII_ADDR, addr);
  152. if (smsc95xx_phy_wait_not_busy(dev))
  153. netdev_warn(dev->net, "Timed out writing MII reg %02X\n", idx);
  154. mutex_unlock(&dev->phy_mutex);
  155. }
  156. static int smsc95xx_wait_eeprom(struct usbnet *dev)
  157. {
  158. unsigned long start_time = jiffies;
  159. u32 val;
  160. do {
  161. smsc95xx_read_reg(dev, E2P_CMD, &val);
  162. if (!(val & E2P_CMD_BUSY_) || (val & E2P_CMD_TIMEOUT_))
  163. break;
  164. udelay(40);
  165. } while (!time_after(jiffies, start_time + HZ));
  166. if (val & (E2P_CMD_TIMEOUT_ | E2P_CMD_BUSY_)) {
  167. netdev_warn(dev->net, "EEPROM read operation timeout\n");
  168. return -EIO;
  169. }
  170. return 0;
  171. }
  172. static int smsc95xx_eeprom_confirm_not_busy(struct usbnet *dev)
  173. {
  174. unsigned long start_time = jiffies;
  175. u32 val;
  176. do {
  177. smsc95xx_read_reg(dev, E2P_CMD, &val);
  178. if (!(val & E2P_CMD_BUSY_))
  179. return 0;
  180. udelay(40);
  181. } while (!time_after(jiffies, start_time + HZ));
  182. netdev_warn(dev->net, "EEPROM is busy\n");
  183. return -EIO;
  184. }
  185. static int smsc95xx_read_eeprom(struct usbnet *dev, u32 offset, u32 length,
  186. u8 *data)
  187. {
  188. u32 val;
  189. int i, ret;
  190. BUG_ON(!dev);
  191. BUG_ON(!data);
  192. ret = smsc95xx_eeprom_confirm_not_busy(dev);
  193. if (ret)
  194. return ret;
  195. for (i = 0; i < length; i++) {
  196. val = E2P_CMD_BUSY_ | E2P_CMD_READ_ | (offset & E2P_CMD_ADDR_);
  197. smsc95xx_write_reg(dev, E2P_CMD, val);
  198. ret = smsc95xx_wait_eeprom(dev);
  199. if (ret < 0)
  200. return ret;
  201. smsc95xx_read_reg(dev, E2P_DATA, &val);
  202. data[i] = val & 0xFF;
  203. offset++;
  204. }
  205. return 0;
  206. }
  207. static int smsc95xx_write_eeprom(struct usbnet *dev, u32 offset, u32 length,
  208. u8 *data)
  209. {
  210. u32 val;
  211. int i, ret;
  212. BUG_ON(!dev);
  213. BUG_ON(!data);
  214. ret = smsc95xx_eeprom_confirm_not_busy(dev);
  215. if (ret)
  216. return ret;
  217. /* Issue write/erase enable command */
  218. val = E2P_CMD_BUSY_ | E2P_CMD_EWEN_;
  219. smsc95xx_write_reg(dev, E2P_CMD, val);
  220. ret = smsc95xx_wait_eeprom(dev);
  221. if (ret < 0)
  222. return ret;
  223. for (i = 0; i < length; i++) {
  224. /* Fill data register */
  225. val = data[i];
  226. smsc95xx_write_reg(dev, E2P_DATA, val);
  227. /* Send "write" command */
  228. val = E2P_CMD_BUSY_ | E2P_CMD_WRITE_ | (offset & E2P_CMD_ADDR_);
  229. smsc95xx_write_reg(dev, E2P_CMD, val);
  230. ret = smsc95xx_wait_eeprom(dev);
  231. if (ret < 0)
  232. return ret;
  233. offset++;
  234. }
  235. return 0;
  236. }
  237. static void smsc95xx_async_cmd_callback(struct urb *urb)
  238. {
  239. struct usb_context *usb_context = urb->context;
  240. struct usbnet *dev = usb_context->dev;
  241. int status = urb->status;
  242. if (status < 0)
  243. netdev_warn(dev->net, "async callback failed with %d\n", status);
  244. kfree(usb_context);
  245. usb_free_urb(urb);
  246. }
  247. static int smsc95xx_write_reg_async(struct usbnet *dev, u16 index, u32 *data)
  248. {
  249. struct usb_context *usb_context;
  250. int status;
  251. struct urb *urb;
  252. const u16 size = 4;
  253. urb = usb_alloc_urb(0, GFP_ATOMIC);
  254. if (!urb) {
  255. netdev_warn(dev->net, "Error allocating URB\n");
  256. return -ENOMEM;
  257. }
  258. usb_context = kmalloc(sizeof(struct usb_context), GFP_ATOMIC);
  259. if (usb_context == NULL) {
  260. netdev_warn(dev->net, "Error allocating control msg\n");
  261. usb_free_urb(urb);
  262. return -ENOMEM;
  263. }
  264. usb_context->req.bRequestType =
  265. USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE;
  266. usb_context->req.bRequest = USB_VENDOR_REQUEST_WRITE_REGISTER;
  267. usb_context->req.wValue = 00;
  268. usb_context->req.wIndex = cpu_to_le16(index);
  269. usb_context->req.wLength = cpu_to_le16(size);
  270. usb_fill_control_urb(urb, dev->udev, usb_sndctrlpipe(dev->udev, 0),
  271. (void *)&usb_context->req, data, size,
  272. smsc95xx_async_cmd_callback,
  273. (void *)usb_context);
  274. status = usb_submit_urb(urb, GFP_ATOMIC);
  275. if (status < 0) {
  276. netdev_warn(dev->net, "Error submitting control msg, sts=%d\n",
  277. status);
  278. kfree(usb_context);
  279. usb_free_urb(urb);
  280. }
  281. return status;
  282. }
  283. /* returns hash bit number for given MAC address
  284. * example:
  285. * 01 00 5E 00 00 01 -> returns bit number 31 */
  286. static unsigned int smsc95xx_hash(char addr[ETH_ALEN])
  287. {
  288. return (ether_crc(ETH_ALEN, addr) >> 26) & 0x3f;
  289. }
  290. static void smsc95xx_set_multicast(struct net_device *netdev)
  291. {
  292. struct usbnet *dev = netdev_priv(netdev);
  293. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  294. u32 hash_hi = 0;
  295. u32 hash_lo = 0;
  296. unsigned long flags;
  297. spin_lock_irqsave(&pdata->mac_cr_lock, flags);
  298. if (dev->net->flags & IFF_PROMISC) {
  299. netif_dbg(dev, drv, dev->net, "promiscuous mode enabled\n");
  300. pdata->mac_cr |= MAC_CR_PRMS_;
  301. pdata->mac_cr &= ~(MAC_CR_MCPAS_ | MAC_CR_HPFILT_);
  302. } else if (dev->net->flags & IFF_ALLMULTI) {
  303. netif_dbg(dev, drv, dev->net, "receive all multicast enabled\n");
  304. pdata->mac_cr |= MAC_CR_MCPAS_;
  305. pdata->mac_cr &= ~(MAC_CR_PRMS_ | MAC_CR_HPFILT_);
  306. } else if (!netdev_mc_empty(dev->net)) {
  307. struct dev_mc_list *mc_list = dev->net->mc_list;
  308. int count = 0;
  309. pdata->mac_cr |= MAC_CR_HPFILT_;
  310. pdata->mac_cr &= ~(MAC_CR_PRMS_ | MAC_CR_MCPAS_);
  311. while (mc_list) {
  312. count++;
  313. if (mc_list->dmi_addrlen == ETH_ALEN) {
  314. u32 bitnum = smsc95xx_hash(mc_list->dmi_addr);
  315. u32 mask = 0x01 << (bitnum & 0x1F);
  316. if (bitnum & 0x20)
  317. hash_hi |= mask;
  318. else
  319. hash_lo |= mask;
  320. } else {
  321. netdev_warn(dev->net, "dmi_addrlen != 6\n");
  322. }
  323. mc_list = mc_list->next;
  324. }
  325. if (count != ((u32) netdev_mc_count(dev->net)))
  326. netdev_warn(dev->net, "mc_count != dev->mc_count\n");
  327. netif_dbg(dev, drv, dev->net, "HASHH=0x%08X, HASHL=0x%08X\n",
  328. hash_hi, hash_lo);
  329. } else {
  330. netif_dbg(dev, drv, dev->net, "receive own packets only\n");
  331. pdata->mac_cr &=
  332. ~(MAC_CR_PRMS_ | MAC_CR_MCPAS_ | MAC_CR_HPFILT_);
  333. }
  334. spin_unlock_irqrestore(&pdata->mac_cr_lock, flags);
  335. /* Initiate async writes, as we can't wait for completion here */
  336. smsc95xx_write_reg_async(dev, HASHH, &hash_hi);
  337. smsc95xx_write_reg_async(dev, HASHL, &hash_lo);
  338. smsc95xx_write_reg_async(dev, MAC_CR, &pdata->mac_cr);
  339. }
  340. static void smsc95xx_phy_update_flowcontrol(struct usbnet *dev, u8 duplex,
  341. u16 lcladv, u16 rmtadv)
  342. {
  343. u32 flow, afc_cfg = 0;
  344. int ret = smsc95xx_read_reg(dev, AFC_CFG, &afc_cfg);
  345. if (ret < 0) {
  346. netdev_warn(dev->net, "error reading AFC_CFG\n");
  347. return;
  348. }
  349. if (duplex == DUPLEX_FULL) {
  350. u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
  351. if (cap & FLOW_CTRL_RX)
  352. flow = 0xFFFF0002;
  353. else
  354. flow = 0;
  355. if (cap & FLOW_CTRL_TX)
  356. afc_cfg |= 0xF;
  357. else
  358. afc_cfg &= ~0xF;
  359. netif_dbg(dev, link, dev->net, "rx pause %s, tx pause %s\n",
  360. cap & FLOW_CTRL_RX ? "enabled" : "disabled",
  361. cap & FLOW_CTRL_TX ? "enabled" : "disabled");
  362. } else {
  363. netif_dbg(dev, link, dev->net, "half duplex\n");
  364. flow = 0;
  365. afc_cfg |= 0xF;
  366. }
  367. smsc95xx_write_reg(dev, FLOW, flow);
  368. smsc95xx_write_reg(dev, AFC_CFG, afc_cfg);
  369. }
  370. static int smsc95xx_link_reset(struct usbnet *dev)
  371. {
  372. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  373. struct mii_if_info *mii = &dev->mii;
  374. struct ethtool_cmd ecmd;
  375. unsigned long flags;
  376. u16 lcladv, rmtadv;
  377. u32 intdata;
  378. /* clear interrupt status */
  379. smsc95xx_mdio_read(dev->net, mii->phy_id, PHY_INT_SRC);
  380. intdata = 0xFFFFFFFF;
  381. smsc95xx_write_reg(dev, INT_STS, intdata);
  382. mii_check_media(mii, 1, 1);
  383. mii_ethtool_gset(&dev->mii, &ecmd);
  384. lcladv = smsc95xx_mdio_read(dev->net, mii->phy_id, MII_ADVERTISE);
  385. rmtadv = smsc95xx_mdio_read(dev->net, mii->phy_id, MII_LPA);
  386. netif_dbg(dev, link, dev->net, "speed: %d duplex: %d lcladv: %04x rmtadv: %04x\n",
  387. ecmd.speed, ecmd.duplex, lcladv, rmtadv);
  388. spin_lock_irqsave(&pdata->mac_cr_lock, flags);
  389. if (ecmd.duplex != DUPLEX_FULL) {
  390. pdata->mac_cr &= ~MAC_CR_FDPX_;
  391. pdata->mac_cr |= MAC_CR_RCVOWN_;
  392. } else {
  393. pdata->mac_cr &= ~MAC_CR_RCVOWN_;
  394. pdata->mac_cr |= MAC_CR_FDPX_;
  395. }
  396. spin_unlock_irqrestore(&pdata->mac_cr_lock, flags);
  397. smsc95xx_write_reg(dev, MAC_CR, pdata->mac_cr);
  398. smsc95xx_phy_update_flowcontrol(dev, ecmd.duplex, lcladv, rmtadv);
  399. return 0;
  400. }
  401. static void smsc95xx_status(struct usbnet *dev, struct urb *urb)
  402. {
  403. u32 intdata;
  404. if (urb->actual_length != 4) {
  405. netdev_warn(dev->net, "unexpected urb length %d\n",
  406. urb->actual_length);
  407. return;
  408. }
  409. memcpy(&intdata, urb->transfer_buffer, 4);
  410. le32_to_cpus(&intdata);
  411. netif_dbg(dev, link, dev->net, "intdata: 0x%08X\n", intdata);
  412. if (intdata & INT_ENP_PHY_INT_)
  413. usbnet_defer_kevent(dev, EVENT_LINK_RESET);
  414. else
  415. netdev_warn(dev->net, "unexpected interrupt, intdata=0x%08X\n",
  416. intdata);
  417. }
  418. /* Enable or disable Tx & Rx checksum offload engines */
  419. static int smsc95xx_set_csums(struct usbnet *dev)
  420. {
  421. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  422. u32 read_buf;
  423. int ret = smsc95xx_read_reg(dev, COE_CR, &read_buf);
  424. if (ret < 0) {
  425. netdev_warn(dev->net, "Failed to read COE_CR: %d\n", ret);
  426. return ret;
  427. }
  428. if (pdata->use_tx_csum)
  429. read_buf |= Tx_COE_EN_;
  430. else
  431. read_buf &= ~Tx_COE_EN_;
  432. if (pdata->use_rx_csum)
  433. read_buf |= Rx_COE_EN_;
  434. else
  435. read_buf &= ~Rx_COE_EN_;
  436. ret = smsc95xx_write_reg(dev, COE_CR, read_buf);
  437. if (ret < 0) {
  438. netdev_warn(dev->net, "Failed to write COE_CR: %d\n", ret);
  439. return ret;
  440. }
  441. netif_dbg(dev, hw, dev->net, "COE_CR = 0x%08x\n", read_buf);
  442. return 0;
  443. }
  444. static int smsc95xx_ethtool_get_eeprom_len(struct net_device *net)
  445. {
  446. return MAX_EEPROM_SIZE;
  447. }
  448. static int smsc95xx_ethtool_get_eeprom(struct net_device *netdev,
  449. struct ethtool_eeprom *ee, u8 *data)
  450. {
  451. struct usbnet *dev = netdev_priv(netdev);
  452. ee->magic = LAN95XX_EEPROM_MAGIC;
  453. return smsc95xx_read_eeprom(dev, ee->offset, ee->len, data);
  454. }
  455. static int smsc95xx_ethtool_set_eeprom(struct net_device *netdev,
  456. struct ethtool_eeprom *ee, u8 *data)
  457. {
  458. struct usbnet *dev = netdev_priv(netdev);
  459. if (ee->magic != LAN95XX_EEPROM_MAGIC) {
  460. netdev_warn(dev->net, "EEPROM: magic value mismatch, magic = 0x%x\n",
  461. ee->magic);
  462. return -EINVAL;
  463. }
  464. return smsc95xx_write_eeprom(dev, ee->offset, ee->len, data);
  465. }
  466. static u32 smsc95xx_ethtool_get_rx_csum(struct net_device *netdev)
  467. {
  468. struct usbnet *dev = netdev_priv(netdev);
  469. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  470. return pdata->use_rx_csum;
  471. }
  472. static int smsc95xx_ethtool_set_rx_csum(struct net_device *netdev, u32 val)
  473. {
  474. struct usbnet *dev = netdev_priv(netdev);
  475. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  476. pdata->use_rx_csum = !!val;
  477. return smsc95xx_set_csums(dev);
  478. }
  479. static u32 smsc95xx_ethtool_get_tx_csum(struct net_device *netdev)
  480. {
  481. struct usbnet *dev = netdev_priv(netdev);
  482. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  483. return pdata->use_tx_csum;
  484. }
  485. static int smsc95xx_ethtool_set_tx_csum(struct net_device *netdev, u32 val)
  486. {
  487. struct usbnet *dev = netdev_priv(netdev);
  488. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  489. pdata->use_tx_csum = !!val;
  490. ethtool_op_set_tx_hw_csum(netdev, pdata->use_tx_csum);
  491. return smsc95xx_set_csums(dev);
  492. }
  493. static const struct ethtool_ops smsc95xx_ethtool_ops = {
  494. .get_link = usbnet_get_link,
  495. .nway_reset = usbnet_nway_reset,
  496. .get_drvinfo = usbnet_get_drvinfo,
  497. .get_msglevel = usbnet_get_msglevel,
  498. .set_msglevel = usbnet_set_msglevel,
  499. .get_settings = usbnet_get_settings,
  500. .set_settings = usbnet_set_settings,
  501. .get_eeprom_len = smsc95xx_ethtool_get_eeprom_len,
  502. .get_eeprom = smsc95xx_ethtool_get_eeprom,
  503. .set_eeprom = smsc95xx_ethtool_set_eeprom,
  504. .get_tx_csum = smsc95xx_ethtool_get_tx_csum,
  505. .set_tx_csum = smsc95xx_ethtool_set_tx_csum,
  506. .get_rx_csum = smsc95xx_ethtool_get_rx_csum,
  507. .set_rx_csum = smsc95xx_ethtool_set_rx_csum,
  508. };
  509. static int smsc95xx_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
  510. {
  511. struct usbnet *dev = netdev_priv(netdev);
  512. if (!netif_running(netdev))
  513. return -EINVAL;
  514. return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL);
  515. }
  516. static void smsc95xx_init_mac_address(struct usbnet *dev)
  517. {
  518. /* try reading mac address from EEPROM */
  519. if (smsc95xx_read_eeprom(dev, EEPROM_MAC_OFFSET, ETH_ALEN,
  520. dev->net->dev_addr) == 0) {
  521. if (is_valid_ether_addr(dev->net->dev_addr)) {
  522. /* eeprom values are valid so use them */
  523. netif_dbg(dev, ifup, dev->net, "MAC address read from EEPROM\n");
  524. return;
  525. }
  526. }
  527. /* no eeprom, or eeprom values are invalid. generate random MAC */
  528. random_ether_addr(dev->net->dev_addr);
  529. netif_dbg(dev, ifup, dev->net, "MAC address set to random_ether_addr\n");
  530. }
  531. static int smsc95xx_set_mac_address(struct usbnet *dev)
  532. {
  533. u32 addr_lo = dev->net->dev_addr[0] | dev->net->dev_addr[1] << 8 |
  534. dev->net->dev_addr[2] << 16 | dev->net->dev_addr[3] << 24;
  535. u32 addr_hi = dev->net->dev_addr[4] | dev->net->dev_addr[5] << 8;
  536. int ret;
  537. ret = smsc95xx_write_reg(dev, ADDRL, addr_lo);
  538. if (ret < 0) {
  539. netdev_warn(dev->net, "Failed to write ADDRL: %d\n", ret);
  540. return ret;
  541. }
  542. ret = smsc95xx_write_reg(dev, ADDRH, addr_hi);
  543. if (ret < 0) {
  544. netdev_warn(dev->net, "Failed to write ADDRH: %d\n", ret);
  545. return ret;
  546. }
  547. return 0;
  548. }
  549. /* starts the TX path */
  550. static void smsc95xx_start_tx_path(struct usbnet *dev)
  551. {
  552. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  553. unsigned long flags;
  554. u32 reg_val;
  555. /* Enable Tx at MAC */
  556. spin_lock_irqsave(&pdata->mac_cr_lock, flags);
  557. pdata->mac_cr |= MAC_CR_TXEN_;
  558. spin_unlock_irqrestore(&pdata->mac_cr_lock, flags);
  559. smsc95xx_write_reg(dev, MAC_CR, pdata->mac_cr);
  560. /* Enable Tx at SCSRs */
  561. reg_val = TX_CFG_ON_;
  562. smsc95xx_write_reg(dev, TX_CFG, reg_val);
  563. }
  564. /* Starts the Receive path */
  565. static void smsc95xx_start_rx_path(struct usbnet *dev)
  566. {
  567. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  568. unsigned long flags;
  569. spin_lock_irqsave(&pdata->mac_cr_lock, flags);
  570. pdata->mac_cr |= MAC_CR_RXEN_;
  571. spin_unlock_irqrestore(&pdata->mac_cr_lock, flags);
  572. smsc95xx_write_reg(dev, MAC_CR, pdata->mac_cr);
  573. }
  574. static int smsc95xx_phy_initialize(struct usbnet *dev)
  575. {
  576. /* Initialize MII structure */
  577. dev->mii.dev = dev->net;
  578. dev->mii.mdio_read = smsc95xx_mdio_read;
  579. dev->mii.mdio_write = smsc95xx_mdio_write;
  580. dev->mii.phy_id_mask = 0x1f;
  581. dev->mii.reg_num_mask = 0x1f;
  582. dev->mii.phy_id = SMSC95XX_INTERNAL_PHY_ID;
  583. smsc95xx_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, BMCR_RESET);
  584. smsc95xx_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,
  585. ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP |
  586. ADVERTISE_PAUSE_ASYM);
  587. /* read to clear */
  588. smsc95xx_mdio_read(dev->net, dev->mii.phy_id, PHY_INT_SRC);
  589. smsc95xx_mdio_write(dev->net, dev->mii.phy_id, PHY_INT_MASK,
  590. PHY_INT_MASK_DEFAULT_);
  591. mii_nway_restart(&dev->mii);
  592. netif_dbg(dev, ifup, dev->net, "phy initialised successfully\n");
  593. return 0;
  594. }
  595. static int smsc95xx_reset(struct usbnet *dev)
  596. {
  597. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  598. struct net_device *netdev = dev->net;
  599. u32 read_buf, write_buf, burst_cap;
  600. int ret = 0, timeout;
  601. netif_dbg(dev, ifup, dev->net, "entering smsc95xx_reset\n");
  602. write_buf = HW_CFG_LRST_;
  603. ret = smsc95xx_write_reg(dev, HW_CFG, write_buf);
  604. if (ret < 0) {
  605. netdev_warn(dev->net, "Failed to write HW_CFG_LRST_ bit in HW_CFG register, ret = %d\n",
  606. ret);
  607. return ret;
  608. }
  609. timeout = 0;
  610. do {
  611. ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
  612. if (ret < 0) {
  613. netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
  614. return ret;
  615. }
  616. msleep(10);
  617. timeout++;
  618. } while ((read_buf & HW_CFG_LRST_) && (timeout < 100));
  619. if (timeout >= 100) {
  620. netdev_warn(dev->net, "timeout waiting for completion of Lite Reset\n");
  621. return ret;
  622. }
  623. write_buf = PM_CTL_PHY_RST_;
  624. ret = smsc95xx_write_reg(dev, PM_CTRL, write_buf);
  625. if (ret < 0) {
  626. netdev_warn(dev->net, "Failed to write PM_CTRL: %d\n", ret);
  627. return ret;
  628. }
  629. timeout = 0;
  630. do {
  631. ret = smsc95xx_read_reg(dev, PM_CTRL, &read_buf);
  632. if (ret < 0) {
  633. netdev_warn(dev->net, "Failed to read PM_CTRL: %d\n", ret);
  634. return ret;
  635. }
  636. msleep(10);
  637. timeout++;
  638. } while ((read_buf & PM_CTL_PHY_RST_) && (timeout < 100));
  639. if (timeout >= 100) {
  640. netdev_warn(dev->net, "timeout waiting for PHY Reset\n");
  641. return ret;
  642. }
  643. smsc95xx_init_mac_address(dev);
  644. ret = smsc95xx_set_mac_address(dev);
  645. if (ret < 0)
  646. return ret;
  647. netif_dbg(dev, ifup, dev->net,
  648. "MAC Address: %pM\n", dev->net->dev_addr);
  649. ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
  650. if (ret < 0) {
  651. netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
  652. return ret;
  653. }
  654. netif_dbg(dev, ifup, dev->net,
  655. "Read Value from HW_CFG : 0x%08x\n", read_buf);
  656. read_buf |= HW_CFG_BIR_;
  657. ret = smsc95xx_write_reg(dev, HW_CFG, read_buf);
  658. if (ret < 0) {
  659. netdev_warn(dev->net, "Failed to write HW_CFG_BIR_ bit in HW_CFG register, ret = %d\n",
  660. ret);
  661. return ret;
  662. }
  663. ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
  664. if (ret < 0) {
  665. netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
  666. return ret;
  667. }
  668. netif_dbg(dev, ifup, dev->net,
  669. "Read Value from HW_CFG after writing HW_CFG_BIR_: 0x%08x\n",
  670. read_buf);
  671. if (!turbo_mode) {
  672. burst_cap = 0;
  673. dev->rx_urb_size = MAX_SINGLE_PACKET_SIZE;
  674. } else if (dev->udev->speed == USB_SPEED_HIGH) {
  675. burst_cap = DEFAULT_HS_BURST_CAP_SIZE / HS_USB_PKT_SIZE;
  676. dev->rx_urb_size = DEFAULT_HS_BURST_CAP_SIZE;
  677. } else {
  678. burst_cap = DEFAULT_FS_BURST_CAP_SIZE / FS_USB_PKT_SIZE;
  679. dev->rx_urb_size = DEFAULT_FS_BURST_CAP_SIZE;
  680. }
  681. netif_dbg(dev, ifup, dev->net,
  682. "rx_urb_size=%ld\n", (ulong)dev->rx_urb_size);
  683. ret = smsc95xx_write_reg(dev, BURST_CAP, burst_cap);
  684. if (ret < 0) {
  685. netdev_warn(dev->net, "Failed to write BURST_CAP: %d\n", ret);
  686. return ret;
  687. }
  688. ret = smsc95xx_read_reg(dev, BURST_CAP, &read_buf);
  689. if (ret < 0) {
  690. netdev_warn(dev->net, "Failed to read BURST_CAP: %d\n", ret);
  691. return ret;
  692. }
  693. netif_dbg(dev, ifup, dev->net,
  694. "Read Value from BURST_CAP after writing: 0x%08x\n",
  695. read_buf);
  696. read_buf = DEFAULT_BULK_IN_DELAY;
  697. ret = smsc95xx_write_reg(dev, BULK_IN_DLY, read_buf);
  698. if (ret < 0) {
  699. netdev_warn(dev->net, "ret = %d\n", ret);
  700. return ret;
  701. }
  702. ret = smsc95xx_read_reg(dev, BULK_IN_DLY, &read_buf);
  703. if (ret < 0) {
  704. netdev_warn(dev->net, "Failed to read BULK_IN_DLY: %d\n", ret);
  705. return ret;
  706. }
  707. netif_dbg(dev, ifup, dev->net,
  708. "Read Value from BULK_IN_DLY after writing: 0x%08x\n",
  709. read_buf);
  710. ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
  711. if (ret < 0) {
  712. netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
  713. return ret;
  714. }
  715. netif_dbg(dev, ifup, dev->net,
  716. "Read Value from HW_CFG: 0x%08x\n", read_buf);
  717. if (turbo_mode)
  718. read_buf |= (HW_CFG_MEF_ | HW_CFG_BCE_);
  719. read_buf &= ~HW_CFG_RXDOFF_;
  720. /* set Rx data offset=2, Make IP header aligns on word boundary. */
  721. read_buf |= NET_IP_ALIGN << 9;
  722. ret = smsc95xx_write_reg(dev, HW_CFG, read_buf);
  723. if (ret < 0) {
  724. netdev_warn(dev->net, "Failed to write HW_CFG register, ret=%d\n",
  725. ret);
  726. return ret;
  727. }
  728. ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
  729. if (ret < 0) {
  730. netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
  731. return ret;
  732. }
  733. netif_dbg(dev, ifup, dev->net,
  734. "Read Value from HW_CFG after writing: 0x%08x\n", read_buf);
  735. write_buf = 0xFFFFFFFF;
  736. ret = smsc95xx_write_reg(dev, INT_STS, write_buf);
  737. if (ret < 0) {
  738. netdev_warn(dev->net, "Failed to write INT_STS register, ret=%d\n",
  739. ret);
  740. return ret;
  741. }
  742. ret = smsc95xx_read_reg(dev, ID_REV, &read_buf);
  743. if (ret < 0) {
  744. netdev_warn(dev->net, "Failed to read ID_REV: %d\n", ret);
  745. return ret;
  746. }
  747. netif_dbg(dev, ifup, dev->net, "ID_REV = 0x%08x\n", read_buf);
  748. /* Configure GPIO pins as LED outputs */
  749. write_buf = LED_GPIO_CFG_SPD_LED | LED_GPIO_CFG_LNK_LED |
  750. LED_GPIO_CFG_FDX_LED;
  751. ret = smsc95xx_write_reg(dev, LED_GPIO_CFG, write_buf);
  752. if (ret < 0) {
  753. netdev_warn(dev->net, "Failed to write LED_GPIO_CFG register, ret=%d\n",
  754. ret);
  755. return ret;
  756. }
  757. /* Init Tx */
  758. write_buf = 0;
  759. ret = smsc95xx_write_reg(dev, FLOW, write_buf);
  760. if (ret < 0) {
  761. netdev_warn(dev->net, "Failed to write FLOW: %d\n", ret);
  762. return ret;
  763. }
  764. read_buf = AFC_CFG_DEFAULT;
  765. ret = smsc95xx_write_reg(dev, AFC_CFG, read_buf);
  766. if (ret < 0) {
  767. netdev_warn(dev->net, "Failed to write AFC_CFG: %d\n", ret);
  768. return ret;
  769. }
  770. /* Don't need mac_cr_lock during initialisation */
  771. ret = smsc95xx_read_reg(dev, MAC_CR, &pdata->mac_cr);
  772. if (ret < 0) {
  773. netdev_warn(dev->net, "Failed to read MAC_CR: %d\n", ret);
  774. return ret;
  775. }
  776. /* Init Rx */
  777. /* Set Vlan */
  778. write_buf = (u32)ETH_P_8021Q;
  779. ret = smsc95xx_write_reg(dev, VLAN1, write_buf);
  780. if (ret < 0) {
  781. netdev_warn(dev->net, "Failed to write VAN1: %d\n", ret);
  782. return ret;
  783. }
  784. /* Enable or disable checksum offload engines */
  785. ethtool_op_set_tx_hw_csum(netdev, pdata->use_tx_csum);
  786. ret = smsc95xx_set_csums(dev);
  787. if (ret < 0) {
  788. netdev_warn(dev->net, "Failed to set csum offload: %d\n", ret);
  789. return ret;
  790. }
  791. smsc95xx_set_multicast(dev->net);
  792. if (smsc95xx_phy_initialize(dev) < 0)
  793. return -EIO;
  794. ret = smsc95xx_read_reg(dev, INT_EP_CTL, &read_buf);
  795. if (ret < 0) {
  796. netdev_warn(dev->net, "Failed to read INT_EP_CTL: %d\n", ret);
  797. return ret;
  798. }
  799. /* enable PHY interrupts */
  800. read_buf |= INT_EP_CTL_PHY_INT_;
  801. ret = smsc95xx_write_reg(dev, INT_EP_CTL, read_buf);
  802. if (ret < 0) {
  803. netdev_warn(dev->net, "Failed to write INT_EP_CTL: %d\n", ret);
  804. return ret;
  805. }
  806. smsc95xx_start_tx_path(dev);
  807. smsc95xx_start_rx_path(dev);
  808. netif_dbg(dev, ifup, dev->net, "smsc95xx_reset, return 0\n");
  809. return 0;
  810. }
  811. static const struct net_device_ops smsc95xx_netdev_ops = {
  812. .ndo_open = usbnet_open,
  813. .ndo_stop = usbnet_stop,
  814. .ndo_start_xmit = usbnet_start_xmit,
  815. .ndo_tx_timeout = usbnet_tx_timeout,
  816. .ndo_change_mtu = usbnet_change_mtu,
  817. .ndo_set_mac_address = eth_mac_addr,
  818. .ndo_validate_addr = eth_validate_addr,
  819. .ndo_do_ioctl = smsc95xx_ioctl,
  820. .ndo_set_multicast_list = smsc95xx_set_multicast,
  821. };
  822. static int smsc95xx_bind(struct usbnet *dev, struct usb_interface *intf)
  823. {
  824. struct smsc95xx_priv *pdata = NULL;
  825. int ret;
  826. printk(KERN_INFO SMSC_CHIPNAME " v" SMSC_DRIVER_VERSION "\n");
  827. ret = usbnet_get_endpoints(dev, intf);
  828. if (ret < 0) {
  829. netdev_warn(dev->net, "usbnet_get_endpoints failed: %d\n", ret);
  830. return ret;
  831. }
  832. dev->data[0] = (unsigned long)kzalloc(sizeof(struct smsc95xx_priv),
  833. GFP_KERNEL);
  834. pdata = (struct smsc95xx_priv *)(dev->data[0]);
  835. if (!pdata) {
  836. netdev_warn(dev->net, "Unable to allocate struct smsc95xx_priv\n");
  837. return -ENOMEM;
  838. }
  839. spin_lock_init(&pdata->mac_cr_lock);
  840. pdata->use_tx_csum = DEFAULT_TX_CSUM_ENABLE;
  841. pdata->use_rx_csum = DEFAULT_RX_CSUM_ENABLE;
  842. /* Init all registers */
  843. ret = smsc95xx_reset(dev);
  844. dev->net->netdev_ops = &smsc95xx_netdev_ops;
  845. dev->net->ethtool_ops = &smsc95xx_ethtool_ops;
  846. dev->net->flags |= IFF_MULTICAST;
  847. dev->net->hard_header_len += SMSC95XX_TX_OVERHEAD;
  848. return 0;
  849. }
  850. static void smsc95xx_unbind(struct usbnet *dev, struct usb_interface *intf)
  851. {
  852. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  853. if (pdata) {
  854. netif_dbg(dev, ifdown, dev->net, "free pdata\n");
  855. kfree(pdata);
  856. pdata = NULL;
  857. dev->data[0] = 0;
  858. }
  859. }
  860. static void smsc95xx_rx_csum_offload(struct sk_buff *skb)
  861. {
  862. skb->csum = *(u16 *)(skb_tail_pointer(skb) - 2);
  863. skb->ip_summed = CHECKSUM_COMPLETE;
  864. skb_trim(skb, skb->len - 2);
  865. }
  866. static int smsc95xx_rx_fixup(struct usbnet *dev, struct sk_buff *skb)
  867. {
  868. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  869. while (skb->len > 0) {
  870. u32 header, align_count;
  871. struct sk_buff *ax_skb;
  872. unsigned char *packet;
  873. u16 size;
  874. memcpy(&header, skb->data, sizeof(header));
  875. le32_to_cpus(&header);
  876. skb_pull(skb, 4 + NET_IP_ALIGN);
  877. packet = skb->data;
  878. /* get the packet length */
  879. size = (u16)((header & RX_STS_FL_) >> 16);
  880. align_count = (4 - ((size + NET_IP_ALIGN) % 4)) % 4;
  881. if (unlikely(header & RX_STS_ES_)) {
  882. netif_dbg(dev, rx_err, dev->net,
  883. "Error header=0x%08x\n", header);
  884. dev->net->stats.rx_errors++;
  885. dev->net->stats.rx_dropped++;
  886. if (header & RX_STS_CRC_) {
  887. dev->net->stats.rx_crc_errors++;
  888. } else {
  889. if (header & (RX_STS_TL_ | RX_STS_RF_))
  890. dev->net->stats.rx_frame_errors++;
  891. if ((header & RX_STS_LE_) &&
  892. (!(header & RX_STS_FT_)))
  893. dev->net->stats.rx_length_errors++;
  894. }
  895. } else {
  896. /* ETH_FRAME_LEN + 4(CRC) + 2(COE) + 4(Vlan) */
  897. if (unlikely(size > (ETH_FRAME_LEN + 12))) {
  898. netif_dbg(dev, rx_err, dev->net,
  899. "size err header=0x%08x\n", header);
  900. return 0;
  901. }
  902. /* last frame in this batch */
  903. if (skb->len == size) {
  904. if (pdata->use_rx_csum)
  905. smsc95xx_rx_csum_offload(skb);
  906. skb_trim(skb, skb->len - 4); /* remove fcs */
  907. skb->truesize = size + sizeof(struct sk_buff);
  908. return 1;
  909. }
  910. ax_skb = skb_clone(skb, GFP_ATOMIC);
  911. if (unlikely(!ax_skb)) {
  912. netdev_warn(dev->net, "Error allocating skb\n");
  913. return 0;
  914. }
  915. ax_skb->len = size;
  916. ax_skb->data = packet;
  917. skb_set_tail_pointer(ax_skb, size);
  918. if (pdata->use_rx_csum)
  919. smsc95xx_rx_csum_offload(ax_skb);
  920. skb_trim(ax_skb, ax_skb->len - 4); /* remove fcs */
  921. ax_skb->truesize = size + sizeof(struct sk_buff);
  922. usbnet_skb_return(dev, ax_skb);
  923. }
  924. skb_pull(skb, size);
  925. /* padding bytes before the next frame starts */
  926. if (skb->len)
  927. skb_pull(skb, align_count);
  928. }
  929. if (unlikely(skb->len < 0)) {
  930. netdev_warn(dev->net, "invalid rx length<0 %d\n", skb->len);
  931. return 0;
  932. }
  933. return 1;
  934. }
  935. static u32 smsc95xx_calc_csum_preamble(struct sk_buff *skb)
  936. {
  937. int len = skb->data - skb->head;
  938. u16 high_16 = (u16)(skb->csum_offset + skb->csum_start - len);
  939. u16 low_16 = (u16)(skb->csum_start - len);
  940. return (high_16 << 16) | low_16;
  941. }
  942. static struct sk_buff *smsc95xx_tx_fixup(struct usbnet *dev,
  943. struct sk_buff *skb, gfp_t flags)
  944. {
  945. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  946. bool csum = pdata->use_tx_csum && (skb->ip_summed == CHECKSUM_PARTIAL);
  947. int overhead = csum ? SMSC95XX_TX_OVERHEAD_CSUM : SMSC95XX_TX_OVERHEAD;
  948. u32 tx_cmd_a, tx_cmd_b;
  949. /* We do not advertise SG, so skbs should be already linearized */
  950. BUG_ON(skb_shinfo(skb)->nr_frags);
  951. if (skb_headroom(skb) < overhead) {
  952. struct sk_buff *skb2 = skb_copy_expand(skb,
  953. overhead, 0, flags);
  954. dev_kfree_skb_any(skb);
  955. skb = skb2;
  956. if (!skb)
  957. return NULL;
  958. }
  959. if (csum) {
  960. u32 csum_preamble = smsc95xx_calc_csum_preamble(skb);
  961. skb_push(skb, 4);
  962. memcpy(skb->data, &csum_preamble, 4);
  963. }
  964. skb_push(skb, 4);
  965. tx_cmd_b = (u32)(skb->len - 4);
  966. if (csum)
  967. tx_cmd_b |= TX_CMD_B_CSUM_ENABLE;
  968. cpu_to_le32s(&tx_cmd_b);
  969. memcpy(skb->data, &tx_cmd_b, 4);
  970. skb_push(skb, 4);
  971. tx_cmd_a = (u32)(skb->len - 8) | TX_CMD_A_FIRST_SEG_ |
  972. TX_CMD_A_LAST_SEG_;
  973. cpu_to_le32s(&tx_cmd_a);
  974. memcpy(skb->data, &tx_cmd_a, 4);
  975. return skb;
  976. }
  977. static const struct driver_info smsc95xx_info = {
  978. .description = "smsc95xx USB 2.0 Ethernet",
  979. .bind = smsc95xx_bind,
  980. .unbind = smsc95xx_unbind,
  981. .link_reset = smsc95xx_link_reset,
  982. .reset = smsc95xx_reset,
  983. .rx_fixup = smsc95xx_rx_fixup,
  984. .tx_fixup = smsc95xx_tx_fixup,
  985. .status = smsc95xx_status,
  986. .flags = FLAG_ETHER | FLAG_SEND_ZLP,
  987. };
  988. static const struct usb_device_id products[] = {
  989. {
  990. /* SMSC9500 USB Ethernet Device */
  991. USB_DEVICE(0x0424, 0x9500),
  992. .driver_info = (unsigned long) &smsc95xx_info,
  993. },
  994. {
  995. /* SMSC9505 USB Ethernet Device */
  996. USB_DEVICE(0x0424, 0x9505),
  997. .driver_info = (unsigned long) &smsc95xx_info,
  998. },
  999. {
  1000. /* SMSC9500A USB Ethernet Device */
  1001. USB_DEVICE(0x0424, 0x9E00),
  1002. .driver_info = (unsigned long) &smsc95xx_info,
  1003. },
  1004. {
  1005. /* SMSC9505A USB Ethernet Device */
  1006. USB_DEVICE(0x0424, 0x9E01),
  1007. .driver_info = (unsigned long) &smsc95xx_info,
  1008. },
  1009. {
  1010. /* SMSC9512/9514 USB Hub & Ethernet Device */
  1011. USB_DEVICE(0x0424, 0xec00),
  1012. .driver_info = (unsigned long) &smsc95xx_info,
  1013. },
  1014. {
  1015. /* SMSC9500 USB Ethernet Device (SAL10) */
  1016. USB_DEVICE(0x0424, 0x9900),
  1017. .driver_info = (unsigned long) &smsc95xx_info,
  1018. },
  1019. {
  1020. /* SMSC9505 USB Ethernet Device (SAL10) */
  1021. USB_DEVICE(0x0424, 0x9901),
  1022. .driver_info = (unsigned long) &smsc95xx_info,
  1023. },
  1024. {
  1025. /* SMSC9500A USB Ethernet Device (SAL10) */
  1026. USB_DEVICE(0x0424, 0x9902),
  1027. .driver_info = (unsigned long) &smsc95xx_info,
  1028. },
  1029. {
  1030. /* SMSC9505A USB Ethernet Device (SAL10) */
  1031. USB_DEVICE(0x0424, 0x9903),
  1032. .driver_info = (unsigned long) &smsc95xx_info,
  1033. },
  1034. {
  1035. /* SMSC9512/9514 USB Hub & Ethernet Device (SAL10) */
  1036. USB_DEVICE(0x0424, 0x9904),
  1037. .driver_info = (unsigned long) &smsc95xx_info,
  1038. },
  1039. {
  1040. /* SMSC9500A USB Ethernet Device (HAL) */
  1041. USB_DEVICE(0x0424, 0x9905),
  1042. .driver_info = (unsigned long) &smsc95xx_info,
  1043. },
  1044. {
  1045. /* SMSC9505A USB Ethernet Device (HAL) */
  1046. USB_DEVICE(0x0424, 0x9906),
  1047. .driver_info = (unsigned long) &smsc95xx_info,
  1048. },
  1049. {
  1050. /* SMSC9500 USB Ethernet Device (Alternate ID) */
  1051. USB_DEVICE(0x0424, 0x9907),
  1052. .driver_info = (unsigned long) &smsc95xx_info,
  1053. },
  1054. {
  1055. /* SMSC9500A USB Ethernet Device (Alternate ID) */
  1056. USB_DEVICE(0x0424, 0x9908),
  1057. .driver_info = (unsigned long) &smsc95xx_info,
  1058. },
  1059. {
  1060. /* SMSC9512/9514 USB Hub & Ethernet Device (Alternate ID) */
  1061. USB_DEVICE(0x0424, 0x9909),
  1062. .driver_info = (unsigned long) &smsc95xx_info,
  1063. },
  1064. { }, /* END */
  1065. };
  1066. MODULE_DEVICE_TABLE(usb, products);
  1067. static struct usb_driver smsc95xx_driver = {
  1068. .name = "smsc95xx",
  1069. .id_table = products,
  1070. .probe = usbnet_probe,
  1071. .suspend = usbnet_suspend,
  1072. .resume = usbnet_resume,
  1073. .disconnect = usbnet_disconnect,
  1074. };
  1075. static int __init smsc95xx_init(void)
  1076. {
  1077. return usb_register(&smsc95xx_driver);
  1078. }
  1079. module_init(smsc95xx_init);
  1080. static void __exit smsc95xx_exit(void)
  1081. {
  1082. usb_deregister(&smsc95xx_driver);
  1083. }
  1084. module_exit(smsc95xx_exit);
  1085. MODULE_AUTHOR("Nancy Lin");
  1086. MODULE_AUTHOR("Steve Glendinning <steve.glendinning@smsc.com>");
  1087. MODULE_DESCRIPTION("SMSC95XX USB 2.0 Ethernet Devices");
  1088. MODULE_LICENSE("GPL");