i810_dma.c 33 KB

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  1. /* i810_dma.c -- DMA support for the i810 -*- linux-c -*-
  2. * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com
  3. *
  4. * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
  5. * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
  6. * All Rights Reserved.
  7. *
  8. * Permission is hereby granted, free of charge, to any person obtaining a
  9. * copy of this software and associated documentation files (the "Software"),
  10. * to deal in the Software without restriction, including without limitation
  11. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12. * and/or sell copies of the Software, and to permit persons to whom the
  13. * Software is furnished to do so, subject to the following conditions:
  14. *
  15. * The above copyright notice and this permission notice (including the next
  16. * paragraph) shall be included in all copies or substantial portions of the
  17. * Software.
  18. *
  19. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  22. * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  23. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  24. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  25. * DEALINGS IN THE SOFTWARE.
  26. *
  27. * Authors: Rickard E. (Rik) Faith <faith@valinux.com>
  28. * Jeff Hartmann <jhartmann@valinux.com>
  29. * Keith Whitwell <keith@tungstengraphics.com>
  30. *
  31. */
  32. #include "drmP.h"
  33. #include "drm.h"
  34. #include "i810_drm.h"
  35. #include "i810_drv.h"
  36. #include <linux/interrupt.h> /* For task queue support */
  37. #include <linux/delay.h>
  38. #include <linux/slab.h>
  39. #include <linux/pagemap.h>
  40. #define I810_BUF_FREE 2
  41. #define I810_BUF_CLIENT 1
  42. #define I810_BUF_HARDWARE 0
  43. #define I810_BUF_UNMAPPED 0
  44. #define I810_BUF_MAPPED 1
  45. static struct drm_buf *i810_freelist_get(struct drm_device * dev)
  46. {
  47. struct drm_device_dma *dma = dev->dma;
  48. int i;
  49. int used;
  50. /* Linear search might not be the best solution */
  51. for (i = 0; i < dma->buf_count; i++) {
  52. struct drm_buf *buf = dma->buflist[i];
  53. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  54. /* In use is already a pointer */
  55. used = cmpxchg(buf_priv->in_use, I810_BUF_FREE,
  56. I810_BUF_CLIENT);
  57. if (used == I810_BUF_FREE)
  58. return buf;
  59. }
  60. return NULL;
  61. }
  62. /* This should only be called if the buffer is not sent to the hardware
  63. * yet, the hardware updates in use for us once its on the ring buffer.
  64. */
  65. static int i810_freelist_put(struct drm_device *dev, struct drm_buf *buf)
  66. {
  67. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  68. int used;
  69. /* In use is already a pointer */
  70. used = cmpxchg(buf_priv->in_use, I810_BUF_CLIENT, I810_BUF_FREE);
  71. if (used != I810_BUF_CLIENT) {
  72. DRM_ERROR("Freeing buffer thats not in use : %d\n", buf->idx);
  73. return -EINVAL;
  74. }
  75. return 0;
  76. }
  77. static int i810_mmap_buffers(struct file *filp, struct vm_area_struct *vma)
  78. {
  79. struct drm_file *priv = filp->private_data;
  80. struct drm_device *dev;
  81. drm_i810_private_t *dev_priv;
  82. struct drm_buf *buf;
  83. drm_i810_buf_priv_t *buf_priv;
  84. dev = priv->minor->dev;
  85. dev_priv = dev->dev_private;
  86. buf = dev_priv->mmap_buffer;
  87. buf_priv = buf->dev_private;
  88. vma->vm_flags |= (VM_IO | VM_DONTCOPY);
  89. buf_priv->currently_mapped = I810_BUF_MAPPED;
  90. if (io_remap_pfn_range(vma, vma->vm_start,
  91. vma->vm_pgoff,
  92. vma->vm_end - vma->vm_start, vma->vm_page_prot))
  93. return -EAGAIN;
  94. return 0;
  95. }
  96. static const struct file_operations i810_buffer_fops = {
  97. .open = drm_open,
  98. .release = drm_release,
  99. .unlocked_ioctl = drm_ioctl,
  100. .mmap = i810_mmap_buffers,
  101. .fasync = drm_fasync,
  102. .llseek = noop_llseek,
  103. };
  104. static int i810_map_buffer(struct drm_buf *buf, struct drm_file *file_priv)
  105. {
  106. struct drm_device *dev = file_priv->minor->dev;
  107. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  108. drm_i810_private_t *dev_priv = dev->dev_private;
  109. const struct file_operations *old_fops;
  110. int retcode = 0;
  111. if (buf_priv->currently_mapped == I810_BUF_MAPPED)
  112. return -EINVAL;
  113. down_write(&current->mm->mmap_sem);
  114. old_fops = file_priv->filp->f_op;
  115. file_priv->filp->f_op = &i810_buffer_fops;
  116. dev_priv->mmap_buffer = buf;
  117. buf_priv->virtual = (void *)do_mmap(file_priv->filp, 0, buf->total,
  118. PROT_READ | PROT_WRITE,
  119. MAP_SHARED, buf->bus_address);
  120. dev_priv->mmap_buffer = NULL;
  121. file_priv->filp->f_op = old_fops;
  122. if (IS_ERR(buf_priv->virtual)) {
  123. /* Real error */
  124. DRM_ERROR("mmap error\n");
  125. retcode = PTR_ERR(buf_priv->virtual);
  126. buf_priv->virtual = NULL;
  127. }
  128. up_write(&current->mm->mmap_sem);
  129. return retcode;
  130. }
  131. static int i810_unmap_buffer(struct drm_buf *buf)
  132. {
  133. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  134. int retcode = 0;
  135. if (buf_priv->currently_mapped != I810_BUF_MAPPED)
  136. return -EINVAL;
  137. retcode = vm_munmap(current->mm,
  138. (unsigned long)buf_priv->virtual,
  139. (size_t) buf->total);
  140. buf_priv->currently_mapped = I810_BUF_UNMAPPED;
  141. buf_priv->virtual = NULL;
  142. return retcode;
  143. }
  144. static int i810_dma_get_buffer(struct drm_device *dev, drm_i810_dma_t *d,
  145. struct drm_file *file_priv)
  146. {
  147. struct drm_buf *buf;
  148. drm_i810_buf_priv_t *buf_priv;
  149. int retcode = 0;
  150. buf = i810_freelist_get(dev);
  151. if (!buf) {
  152. retcode = -ENOMEM;
  153. DRM_DEBUG("retcode=%d\n", retcode);
  154. return retcode;
  155. }
  156. retcode = i810_map_buffer(buf, file_priv);
  157. if (retcode) {
  158. i810_freelist_put(dev, buf);
  159. DRM_ERROR("mapbuf failed, retcode %d\n", retcode);
  160. return retcode;
  161. }
  162. buf->file_priv = file_priv;
  163. buf_priv = buf->dev_private;
  164. d->granted = 1;
  165. d->request_idx = buf->idx;
  166. d->request_size = buf->total;
  167. d->virtual = buf_priv->virtual;
  168. return retcode;
  169. }
  170. static int i810_dma_cleanup(struct drm_device *dev)
  171. {
  172. struct drm_device_dma *dma = dev->dma;
  173. /* Make sure interrupts are disabled here because the uninstall ioctl
  174. * may not have been called from userspace and after dev_private
  175. * is freed, it's too late.
  176. */
  177. if (drm_core_check_feature(dev, DRIVER_HAVE_IRQ) && dev->irq_enabled)
  178. drm_irq_uninstall(dev);
  179. if (dev->dev_private) {
  180. int i;
  181. drm_i810_private_t *dev_priv =
  182. (drm_i810_private_t *) dev->dev_private;
  183. if (dev_priv->ring.virtual_start)
  184. drm_core_ioremapfree(&dev_priv->ring.map, dev);
  185. if (dev_priv->hw_status_page) {
  186. pci_free_consistent(dev->pdev, PAGE_SIZE,
  187. dev_priv->hw_status_page,
  188. dev_priv->dma_status_page);
  189. }
  190. kfree(dev->dev_private);
  191. dev->dev_private = NULL;
  192. for (i = 0; i < dma->buf_count; i++) {
  193. struct drm_buf *buf = dma->buflist[i];
  194. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  195. if (buf_priv->kernel_virtual && buf->total)
  196. drm_core_ioremapfree(&buf_priv->map, dev);
  197. }
  198. }
  199. return 0;
  200. }
  201. static int i810_wait_ring(struct drm_device *dev, int n)
  202. {
  203. drm_i810_private_t *dev_priv = dev->dev_private;
  204. drm_i810_ring_buffer_t *ring = &(dev_priv->ring);
  205. int iters = 0;
  206. unsigned long end;
  207. unsigned int last_head = I810_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
  208. end = jiffies + (HZ * 3);
  209. while (ring->space < n) {
  210. ring->head = I810_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
  211. ring->space = ring->head - (ring->tail + 8);
  212. if (ring->space < 0)
  213. ring->space += ring->Size;
  214. if (ring->head != last_head) {
  215. end = jiffies + (HZ * 3);
  216. last_head = ring->head;
  217. }
  218. iters++;
  219. if (time_before(end, jiffies)) {
  220. DRM_ERROR("space: %d wanted %d\n", ring->space, n);
  221. DRM_ERROR("lockup\n");
  222. goto out_wait_ring;
  223. }
  224. udelay(1);
  225. }
  226. out_wait_ring:
  227. return iters;
  228. }
  229. static void i810_kernel_lost_context(struct drm_device *dev)
  230. {
  231. drm_i810_private_t *dev_priv = dev->dev_private;
  232. drm_i810_ring_buffer_t *ring = &(dev_priv->ring);
  233. ring->head = I810_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
  234. ring->tail = I810_READ(LP_RING + RING_TAIL);
  235. ring->space = ring->head - (ring->tail + 8);
  236. if (ring->space < 0)
  237. ring->space += ring->Size;
  238. }
  239. static int i810_freelist_init(struct drm_device *dev, drm_i810_private_t *dev_priv)
  240. {
  241. struct drm_device_dma *dma = dev->dma;
  242. int my_idx = 24;
  243. u32 *hw_status = (u32 *) (dev_priv->hw_status_page + my_idx);
  244. int i;
  245. if (dma->buf_count > 1019) {
  246. /* Not enough space in the status page for the freelist */
  247. return -EINVAL;
  248. }
  249. for (i = 0; i < dma->buf_count; i++) {
  250. struct drm_buf *buf = dma->buflist[i];
  251. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  252. buf_priv->in_use = hw_status++;
  253. buf_priv->my_use_idx = my_idx;
  254. my_idx += 4;
  255. *buf_priv->in_use = I810_BUF_FREE;
  256. buf_priv->map.offset = buf->bus_address;
  257. buf_priv->map.size = buf->total;
  258. buf_priv->map.type = _DRM_AGP;
  259. buf_priv->map.flags = 0;
  260. buf_priv->map.mtrr = 0;
  261. drm_core_ioremap(&buf_priv->map, dev);
  262. buf_priv->kernel_virtual = buf_priv->map.handle;
  263. }
  264. return 0;
  265. }
  266. static int i810_dma_initialize(struct drm_device *dev,
  267. drm_i810_private_t *dev_priv,
  268. drm_i810_init_t *init)
  269. {
  270. struct drm_map_list *r_list;
  271. memset(dev_priv, 0, sizeof(drm_i810_private_t));
  272. list_for_each_entry(r_list, &dev->maplist, head) {
  273. if (r_list->map &&
  274. r_list->map->type == _DRM_SHM &&
  275. r_list->map->flags & _DRM_CONTAINS_LOCK) {
  276. dev_priv->sarea_map = r_list->map;
  277. break;
  278. }
  279. }
  280. if (!dev_priv->sarea_map) {
  281. dev->dev_private = (void *)dev_priv;
  282. i810_dma_cleanup(dev);
  283. DRM_ERROR("can not find sarea!\n");
  284. return -EINVAL;
  285. }
  286. dev_priv->mmio_map = drm_core_findmap(dev, init->mmio_offset);
  287. if (!dev_priv->mmio_map) {
  288. dev->dev_private = (void *)dev_priv;
  289. i810_dma_cleanup(dev);
  290. DRM_ERROR("can not find mmio map!\n");
  291. return -EINVAL;
  292. }
  293. dev->agp_buffer_token = init->buffers_offset;
  294. dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
  295. if (!dev->agp_buffer_map) {
  296. dev->dev_private = (void *)dev_priv;
  297. i810_dma_cleanup(dev);
  298. DRM_ERROR("can not find dma buffer map!\n");
  299. return -EINVAL;
  300. }
  301. dev_priv->sarea_priv = (drm_i810_sarea_t *)
  302. ((u8 *) dev_priv->sarea_map->handle + init->sarea_priv_offset);
  303. dev_priv->ring.Start = init->ring_start;
  304. dev_priv->ring.End = init->ring_end;
  305. dev_priv->ring.Size = init->ring_size;
  306. dev_priv->ring.map.offset = dev->agp->base + init->ring_start;
  307. dev_priv->ring.map.size = init->ring_size;
  308. dev_priv->ring.map.type = _DRM_AGP;
  309. dev_priv->ring.map.flags = 0;
  310. dev_priv->ring.map.mtrr = 0;
  311. drm_core_ioremap(&dev_priv->ring.map, dev);
  312. if (dev_priv->ring.map.handle == NULL) {
  313. dev->dev_private = (void *)dev_priv;
  314. i810_dma_cleanup(dev);
  315. DRM_ERROR("can not ioremap virtual address for"
  316. " ring buffer\n");
  317. return -ENOMEM;
  318. }
  319. dev_priv->ring.virtual_start = dev_priv->ring.map.handle;
  320. dev_priv->ring.tail_mask = dev_priv->ring.Size - 1;
  321. dev_priv->w = init->w;
  322. dev_priv->h = init->h;
  323. dev_priv->pitch = init->pitch;
  324. dev_priv->back_offset = init->back_offset;
  325. dev_priv->depth_offset = init->depth_offset;
  326. dev_priv->front_offset = init->front_offset;
  327. dev_priv->overlay_offset = init->overlay_offset;
  328. dev_priv->overlay_physical = init->overlay_physical;
  329. dev_priv->front_di1 = init->front_offset | init->pitch_bits;
  330. dev_priv->back_di1 = init->back_offset | init->pitch_bits;
  331. dev_priv->zi1 = init->depth_offset | init->pitch_bits;
  332. /* Program Hardware Status Page */
  333. dev_priv->hw_status_page =
  334. pci_alloc_consistent(dev->pdev, PAGE_SIZE,
  335. &dev_priv->dma_status_page);
  336. if (!dev_priv->hw_status_page) {
  337. dev->dev_private = (void *)dev_priv;
  338. i810_dma_cleanup(dev);
  339. DRM_ERROR("Can not allocate hardware status page\n");
  340. return -ENOMEM;
  341. }
  342. memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
  343. DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page);
  344. I810_WRITE(0x02080, dev_priv->dma_status_page);
  345. DRM_DEBUG("Enabled hardware status page\n");
  346. /* Now we need to init our freelist */
  347. if (i810_freelist_init(dev, dev_priv) != 0) {
  348. dev->dev_private = (void *)dev_priv;
  349. i810_dma_cleanup(dev);
  350. DRM_ERROR("Not enough space in the status page for"
  351. " the freelist\n");
  352. return -ENOMEM;
  353. }
  354. dev->dev_private = (void *)dev_priv;
  355. return 0;
  356. }
  357. static int i810_dma_init(struct drm_device *dev, void *data,
  358. struct drm_file *file_priv)
  359. {
  360. drm_i810_private_t *dev_priv;
  361. drm_i810_init_t *init = data;
  362. int retcode = 0;
  363. switch (init->func) {
  364. case I810_INIT_DMA_1_4:
  365. DRM_INFO("Using v1.4 init.\n");
  366. dev_priv = kmalloc(sizeof(drm_i810_private_t), GFP_KERNEL);
  367. if (dev_priv == NULL)
  368. return -ENOMEM;
  369. retcode = i810_dma_initialize(dev, dev_priv, init);
  370. break;
  371. case I810_CLEANUP_DMA:
  372. DRM_INFO("DMA Cleanup\n");
  373. retcode = i810_dma_cleanup(dev);
  374. break;
  375. default:
  376. return -EINVAL;
  377. }
  378. return retcode;
  379. }
  380. /* Most efficient way to verify state for the i810 is as it is
  381. * emitted. Non-conformant state is silently dropped.
  382. *
  383. * Use 'volatile' & local var tmp to force the emitted values to be
  384. * identical to the verified ones.
  385. */
  386. static void i810EmitContextVerified(struct drm_device *dev,
  387. volatile unsigned int *code)
  388. {
  389. drm_i810_private_t *dev_priv = dev->dev_private;
  390. int i, j = 0;
  391. unsigned int tmp;
  392. RING_LOCALS;
  393. BEGIN_LP_RING(I810_CTX_SETUP_SIZE);
  394. OUT_RING(GFX_OP_COLOR_FACTOR);
  395. OUT_RING(code[I810_CTXREG_CF1]);
  396. OUT_RING(GFX_OP_STIPPLE);
  397. OUT_RING(code[I810_CTXREG_ST1]);
  398. for (i = 4; i < I810_CTX_SETUP_SIZE; i++) {
  399. tmp = code[i];
  400. if ((tmp & (7 << 29)) == (3 << 29) &&
  401. (tmp & (0x1f << 24)) < (0x1d << 24)) {
  402. OUT_RING(tmp);
  403. j++;
  404. } else
  405. printk("constext state dropped!!!\n");
  406. }
  407. if (j & 1)
  408. OUT_RING(0);
  409. ADVANCE_LP_RING();
  410. }
  411. static void i810EmitTexVerified(struct drm_device *dev, volatile unsigned int *code)
  412. {
  413. drm_i810_private_t *dev_priv = dev->dev_private;
  414. int i, j = 0;
  415. unsigned int tmp;
  416. RING_LOCALS;
  417. BEGIN_LP_RING(I810_TEX_SETUP_SIZE);
  418. OUT_RING(GFX_OP_MAP_INFO);
  419. OUT_RING(code[I810_TEXREG_MI1]);
  420. OUT_RING(code[I810_TEXREG_MI2]);
  421. OUT_RING(code[I810_TEXREG_MI3]);
  422. for (i = 4; i < I810_TEX_SETUP_SIZE; i++) {
  423. tmp = code[i];
  424. if ((tmp & (7 << 29)) == (3 << 29) &&
  425. (tmp & (0x1f << 24)) < (0x1d << 24)) {
  426. OUT_RING(tmp);
  427. j++;
  428. } else
  429. printk("texture state dropped!!!\n");
  430. }
  431. if (j & 1)
  432. OUT_RING(0);
  433. ADVANCE_LP_RING();
  434. }
  435. /* Need to do some additional checking when setting the dest buffer.
  436. */
  437. static void i810EmitDestVerified(struct drm_device *dev,
  438. volatile unsigned int *code)
  439. {
  440. drm_i810_private_t *dev_priv = dev->dev_private;
  441. unsigned int tmp;
  442. RING_LOCALS;
  443. BEGIN_LP_RING(I810_DEST_SETUP_SIZE + 2);
  444. tmp = code[I810_DESTREG_DI1];
  445. if (tmp == dev_priv->front_di1 || tmp == dev_priv->back_di1) {
  446. OUT_RING(CMD_OP_DESTBUFFER_INFO);
  447. OUT_RING(tmp);
  448. } else
  449. DRM_DEBUG("bad di1 %x (allow %x or %x)\n",
  450. tmp, dev_priv->front_di1, dev_priv->back_di1);
  451. /* invarient:
  452. */
  453. OUT_RING(CMD_OP_Z_BUFFER_INFO);
  454. OUT_RING(dev_priv->zi1);
  455. OUT_RING(GFX_OP_DESTBUFFER_VARS);
  456. OUT_RING(code[I810_DESTREG_DV1]);
  457. OUT_RING(GFX_OP_DRAWRECT_INFO);
  458. OUT_RING(code[I810_DESTREG_DR1]);
  459. OUT_RING(code[I810_DESTREG_DR2]);
  460. OUT_RING(code[I810_DESTREG_DR3]);
  461. OUT_RING(code[I810_DESTREG_DR4]);
  462. OUT_RING(0);
  463. ADVANCE_LP_RING();
  464. }
  465. static void i810EmitState(struct drm_device *dev)
  466. {
  467. drm_i810_private_t *dev_priv = dev->dev_private;
  468. drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
  469. unsigned int dirty = sarea_priv->dirty;
  470. DRM_DEBUG("%x\n", dirty);
  471. if (dirty & I810_UPLOAD_BUFFERS) {
  472. i810EmitDestVerified(dev, sarea_priv->BufferState);
  473. sarea_priv->dirty &= ~I810_UPLOAD_BUFFERS;
  474. }
  475. if (dirty & I810_UPLOAD_CTX) {
  476. i810EmitContextVerified(dev, sarea_priv->ContextState);
  477. sarea_priv->dirty &= ~I810_UPLOAD_CTX;
  478. }
  479. if (dirty & I810_UPLOAD_TEX0) {
  480. i810EmitTexVerified(dev, sarea_priv->TexState[0]);
  481. sarea_priv->dirty &= ~I810_UPLOAD_TEX0;
  482. }
  483. if (dirty & I810_UPLOAD_TEX1) {
  484. i810EmitTexVerified(dev, sarea_priv->TexState[1]);
  485. sarea_priv->dirty &= ~I810_UPLOAD_TEX1;
  486. }
  487. }
  488. /* need to verify
  489. */
  490. static void i810_dma_dispatch_clear(struct drm_device *dev, int flags,
  491. unsigned int clear_color,
  492. unsigned int clear_zval)
  493. {
  494. drm_i810_private_t *dev_priv = dev->dev_private;
  495. drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
  496. int nbox = sarea_priv->nbox;
  497. struct drm_clip_rect *pbox = sarea_priv->boxes;
  498. int pitch = dev_priv->pitch;
  499. int cpp = 2;
  500. int i;
  501. RING_LOCALS;
  502. if (dev_priv->current_page == 1) {
  503. unsigned int tmp = flags;
  504. flags &= ~(I810_FRONT | I810_BACK);
  505. if (tmp & I810_FRONT)
  506. flags |= I810_BACK;
  507. if (tmp & I810_BACK)
  508. flags |= I810_FRONT;
  509. }
  510. i810_kernel_lost_context(dev);
  511. if (nbox > I810_NR_SAREA_CLIPRECTS)
  512. nbox = I810_NR_SAREA_CLIPRECTS;
  513. for (i = 0; i < nbox; i++, pbox++) {
  514. unsigned int x = pbox->x1;
  515. unsigned int y = pbox->y1;
  516. unsigned int width = (pbox->x2 - x) * cpp;
  517. unsigned int height = pbox->y2 - y;
  518. unsigned int start = y * pitch + x * cpp;
  519. if (pbox->x1 > pbox->x2 ||
  520. pbox->y1 > pbox->y2 ||
  521. pbox->x2 > dev_priv->w || pbox->y2 > dev_priv->h)
  522. continue;
  523. if (flags & I810_FRONT) {
  524. BEGIN_LP_RING(6);
  525. OUT_RING(BR00_BITBLT_CLIENT | BR00_OP_COLOR_BLT | 0x3);
  526. OUT_RING(BR13_SOLID_PATTERN | (0xF0 << 16) | pitch);
  527. OUT_RING((height << 16) | width);
  528. OUT_RING(start);
  529. OUT_RING(clear_color);
  530. OUT_RING(0);
  531. ADVANCE_LP_RING();
  532. }
  533. if (flags & I810_BACK) {
  534. BEGIN_LP_RING(6);
  535. OUT_RING(BR00_BITBLT_CLIENT | BR00_OP_COLOR_BLT | 0x3);
  536. OUT_RING(BR13_SOLID_PATTERN | (0xF0 << 16) | pitch);
  537. OUT_RING((height << 16) | width);
  538. OUT_RING(dev_priv->back_offset + start);
  539. OUT_RING(clear_color);
  540. OUT_RING(0);
  541. ADVANCE_LP_RING();
  542. }
  543. if (flags & I810_DEPTH) {
  544. BEGIN_LP_RING(6);
  545. OUT_RING(BR00_BITBLT_CLIENT | BR00_OP_COLOR_BLT | 0x3);
  546. OUT_RING(BR13_SOLID_PATTERN | (0xF0 << 16) | pitch);
  547. OUT_RING((height << 16) | width);
  548. OUT_RING(dev_priv->depth_offset + start);
  549. OUT_RING(clear_zval);
  550. OUT_RING(0);
  551. ADVANCE_LP_RING();
  552. }
  553. }
  554. }
  555. static void i810_dma_dispatch_swap(struct drm_device *dev)
  556. {
  557. drm_i810_private_t *dev_priv = dev->dev_private;
  558. drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
  559. int nbox = sarea_priv->nbox;
  560. struct drm_clip_rect *pbox = sarea_priv->boxes;
  561. int pitch = dev_priv->pitch;
  562. int cpp = 2;
  563. int i;
  564. RING_LOCALS;
  565. DRM_DEBUG("swapbuffers\n");
  566. i810_kernel_lost_context(dev);
  567. if (nbox > I810_NR_SAREA_CLIPRECTS)
  568. nbox = I810_NR_SAREA_CLIPRECTS;
  569. for (i = 0; i < nbox; i++, pbox++) {
  570. unsigned int w = pbox->x2 - pbox->x1;
  571. unsigned int h = pbox->y2 - pbox->y1;
  572. unsigned int dst = pbox->x1 * cpp + pbox->y1 * pitch;
  573. unsigned int start = dst;
  574. if (pbox->x1 > pbox->x2 ||
  575. pbox->y1 > pbox->y2 ||
  576. pbox->x2 > dev_priv->w || pbox->y2 > dev_priv->h)
  577. continue;
  578. BEGIN_LP_RING(6);
  579. OUT_RING(BR00_BITBLT_CLIENT | BR00_OP_SRC_COPY_BLT | 0x4);
  580. OUT_RING(pitch | (0xCC << 16));
  581. OUT_RING((h << 16) | (w * cpp));
  582. if (dev_priv->current_page == 0)
  583. OUT_RING(dev_priv->front_offset + start);
  584. else
  585. OUT_RING(dev_priv->back_offset + start);
  586. OUT_RING(pitch);
  587. if (dev_priv->current_page == 0)
  588. OUT_RING(dev_priv->back_offset + start);
  589. else
  590. OUT_RING(dev_priv->front_offset + start);
  591. ADVANCE_LP_RING();
  592. }
  593. }
  594. static void i810_dma_dispatch_vertex(struct drm_device *dev,
  595. struct drm_buf *buf, int discard, int used)
  596. {
  597. drm_i810_private_t *dev_priv = dev->dev_private;
  598. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  599. drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
  600. struct drm_clip_rect *box = sarea_priv->boxes;
  601. int nbox = sarea_priv->nbox;
  602. unsigned long address = (unsigned long)buf->bus_address;
  603. unsigned long start = address - dev->agp->base;
  604. int i = 0;
  605. RING_LOCALS;
  606. i810_kernel_lost_context(dev);
  607. if (nbox > I810_NR_SAREA_CLIPRECTS)
  608. nbox = I810_NR_SAREA_CLIPRECTS;
  609. if (used > 4 * 1024)
  610. used = 0;
  611. if (sarea_priv->dirty)
  612. i810EmitState(dev);
  613. if (buf_priv->currently_mapped == I810_BUF_MAPPED) {
  614. unsigned int prim = (sarea_priv->vertex_prim & PR_MASK);
  615. *(u32 *) buf_priv->kernel_virtual =
  616. ((GFX_OP_PRIMITIVE | prim | ((used / 4) - 2)));
  617. if (used & 4) {
  618. *(u32 *) ((char *) buf_priv->kernel_virtual + used) = 0;
  619. used += 4;
  620. }
  621. i810_unmap_buffer(buf);
  622. }
  623. if (used) {
  624. do {
  625. if (i < nbox) {
  626. BEGIN_LP_RING(4);
  627. OUT_RING(GFX_OP_SCISSOR | SC_UPDATE_SCISSOR |
  628. SC_ENABLE);
  629. OUT_RING(GFX_OP_SCISSOR_INFO);
  630. OUT_RING(box[i].x1 | (box[i].y1 << 16));
  631. OUT_RING((box[i].x2 -
  632. 1) | ((box[i].y2 - 1) << 16));
  633. ADVANCE_LP_RING();
  634. }
  635. BEGIN_LP_RING(4);
  636. OUT_RING(CMD_OP_BATCH_BUFFER);
  637. OUT_RING(start | BB1_PROTECTED);
  638. OUT_RING(start + used - 4);
  639. OUT_RING(0);
  640. ADVANCE_LP_RING();
  641. } while (++i < nbox);
  642. }
  643. if (discard) {
  644. dev_priv->counter++;
  645. (void)cmpxchg(buf_priv->in_use, I810_BUF_CLIENT,
  646. I810_BUF_HARDWARE);
  647. BEGIN_LP_RING(8);
  648. OUT_RING(CMD_STORE_DWORD_IDX);
  649. OUT_RING(20);
  650. OUT_RING(dev_priv->counter);
  651. OUT_RING(CMD_STORE_DWORD_IDX);
  652. OUT_RING(buf_priv->my_use_idx);
  653. OUT_RING(I810_BUF_FREE);
  654. OUT_RING(CMD_REPORT_HEAD);
  655. OUT_RING(0);
  656. ADVANCE_LP_RING();
  657. }
  658. }
  659. static void i810_dma_dispatch_flip(struct drm_device *dev)
  660. {
  661. drm_i810_private_t *dev_priv = dev->dev_private;
  662. int pitch = dev_priv->pitch;
  663. RING_LOCALS;
  664. DRM_DEBUG("page=%d pfCurrentPage=%d\n",
  665. dev_priv->current_page,
  666. dev_priv->sarea_priv->pf_current_page);
  667. i810_kernel_lost_context(dev);
  668. BEGIN_LP_RING(2);
  669. OUT_RING(INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE);
  670. OUT_RING(0);
  671. ADVANCE_LP_RING();
  672. BEGIN_LP_RING(I810_DEST_SETUP_SIZE + 2);
  673. /* On i815 at least ASYNC is buggy */
  674. /* pitch<<5 is from 11.2.8 p158,
  675. its the pitch / 8 then left shifted 8,
  676. so (pitch >> 3) << 8 */
  677. OUT_RING(CMD_OP_FRONTBUFFER_INFO | (pitch << 5) /*| ASYNC_FLIP */ );
  678. if (dev_priv->current_page == 0) {
  679. OUT_RING(dev_priv->back_offset);
  680. dev_priv->current_page = 1;
  681. } else {
  682. OUT_RING(dev_priv->front_offset);
  683. dev_priv->current_page = 0;
  684. }
  685. OUT_RING(0);
  686. ADVANCE_LP_RING();
  687. BEGIN_LP_RING(2);
  688. OUT_RING(CMD_OP_WAIT_FOR_EVENT | WAIT_FOR_PLANE_A_FLIP);
  689. OUT_RING(0);
  690. ADVANCE_LP_RING();
  691. /* Increment the frame counter. The client-side 3D driver must
  692. * throttle the framerate by waiting for this value before
  693. * performing the swapbuffer ioctl.
  694. */
  695. dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
  696. }
  697. static void i810_dma_quiescent(struct drm_device *dev)
  698. {
  699. drm_i810_private_t *dev_priv = dev->dev_private;
  700. RING_LOCALS;
  701. i810_kernel_lost_context(dev);
  702. BEGIN_LP_RING(4);
  703. OUT_RING(INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE);
  704. OUT_RING(CMD_REPORT_HEAD);
  705. OUT_RING(0);
  706. OUT_RING(0);
  707. ADVANCE_LP_RING();
  708. i810_wait_ring(dev, dev_priv->ring.Size - 8);
  709. }
  710. static int i810_flush_queue(struct drm_device *dev)
  711. {
  712. drm_i810_private_t *dev_priv = dev->dev_private;
  713. struct drm_device_dma *dma = dev->dma;
  714. int i, ret = 0;
  715. RING_LOCALS;
  716. i810_kernel_lost_context(dev);
  717. BEGIN_LP_RING(2);
  718. OUT_RING(CMD_REPORT_HEAD);
  719. OUT_RING(0);
  720. ADVANCE_LP_RING();
  721. i810_wait_ring(dev, dev_priv->ring.Size - 8);
  722. for (i = 0; i < dma->buf_count; i++) {
  723. struct drm_buf *buf = dma->buflist[i];
  724. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  725. int used = cmpxchg(buf_priv->in_use, I810_BUF_HARDWARE,
  726. I810_BUF_FREE);
  727. if (used == I810_BUF_HARDWARE)
  728. DRM_DEBUG("reclaimed from HARDWARE\n");
  729. if (used == I810_BUF_CLIENT)
  730. DRM_DEBUG("still on client\n");
  731. }
  732. return ret;
  733. }
  734. /* Must be called with the lock held */
  735. static void i810_reclaim_buffers(struct drm_device *dev,
  736. struct drm_file *file_priv)
  737. {
  738. struct drm_device_dma *dma = dev->dma;
  739. int i;
  740. if (!dma)
  741. return;
  742. if (!dev->dev_private)
  743. return;
  744. if (!dma->buflist)
  745. return;
  746. i810_flush_queue(dev);
  747. for (i = 0; i < dma->buf_count; i++) {
  748. struct drm_buf *buf = dma->buflist[i];
  749. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  750. if (buf->file_priv == file_priv && buf_priv) {
  751. int used = cmpxchg(buf_priv->in_use, I810_BUF_CLIENT,
  752. I810_BUF_FREE);
  753. if (used == I810_BUF_CLIENT)
  754. DRM_DEBUG("reclaimed from client\n");
  755. if (buf_priv->currently_mapped == I810_BUF_MAPPED)
  756. buf_priv->currently_mapped = I810_BUF_UNMAPPED;
  757. }
  758. }
  759. }
  760. static int i810_flush_ioctl(struct drm_device *dev, void *data,
  761. struct drm_file *file_priv)
  762. {
  763. LOCK_TEST_WITH_RETURN(dev, file_priv);
  764. i810_flush_queue(dev);
  765. return 0;
  766. }
  767. static int i810_dma_vertex(struct drm_device *dev, void *data,
  768. struct drm_file *file_priv)
  769. {
  770. struct drm_device_dma *dma = dev->dma;
  771. drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
  772. u32 *hw_status = dev_priv->hw_status_page;
  773. drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *)
  774. dev_priv->sarea_priv;
  775. drm_i810_vertex_t *vertex = data;
  776. LOCK_TEST_WITH_RETURN(dev, file_priv);
  777. DRM_DEBUG("idx %d used %d discard %d\n",
  778. vertex->idx, vertex->used, vertex->discard);
  779. if (vertex->idx < 0 || vertex->idx > dma->buf_count)
  780. return -EINVAL;
  781. i810_dma_dispatch_vertex(dev,
  782. dma->buflist[vertex->idx],
  783. vertex->discard, vertex->used);
  784. atomic_add(vertex->used, &dev->counts[_DRM_STAT_SECONDARY]);
  785. atomic_inc(&dev->counts[_DRM_STAT_DMA]);
  786. sarea_priv->last_enqueue = dev_priv->counter - 1;
  787. sarea_priv->last_dispatch = (int)hw_status[5];
  788. return 0;
  789. }
  790. static int i810_clear_bufs(struct drm_device *dev, void *data,
  791. struct drm_file *file_priv)
  792. {
  793. drm_i810_clear_t *clear = data;
  794. LOCK_TEST_WITH_RETURN(dev, file_priv);
  795. /* GH: Someone's doing nasty things... */
  796. if (!dev->dev_private)
  797. return -EINVAL;
  798. i810_dma_dispatch_clear(dev, clear->flags,
  799. clear->clear_color, clear->clear_depth);
  800. return 0;
  801. }
  802. static int i810_swap_bufs(struct drm_device *dev, void *data,
  803. struct drm_file *file_priv)
  804. {
  805. DRM_DEBUG("\n");
  806. LOCK_TEST_WITH_RETURN(dev, file_priv);
  807. i810_dma_dispatch_swap(dev);
  808. return 0;
  809. }
  810. static int i810_getage(struct drm_device *dev, void *data,
  811. struct drm_file *file_priv)
  812. {
  813. drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
  814. u32 *hw_status = dev_priv->hw_status_page;
  815. drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *)
  816. dev_priv->sarea_priv;
  817. sarea_priv->last_dispatch = (int)hw_status[5];
  818. return 0;
  819. }
  820. static int i810_getbuf(struct drm_device *dev, void *data,
  821. struct drm_file *file_priv)
  822. {
  823. int retcode = 0;
  824. drm_i810_dma_t *d = data;
  825. drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
  826. u32 *hw_status = dev_priv->hw_status_page;
  827. drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *)
  828. dev_priv->sarea_priv;
  829. LOCK_TEST_WITH_RETURN(dev, file_priv);
  830. d->granted = 0;
  831. retcode = i810_dma_get_buffer(dev, d, file_priv);
  832. DRM_DEBUG("i810_dma: %d returning %d, granted = %d\n",
  833. task_pid_nr(current), retcode, d->granted);
  834. sarea_priv->last_dispatch = (int)hw_status[5];
  835. return retcode;
  836. }
  837. static int i810_copybuf(struct drm_device *dev, void *data,
  838. struct drm_file *file_priv)
  839. {
  840. /* Never copy - 2.4.x doesn't need it */
  841. return 0;
  842. }
  843. static int i810_docopy(struct drm_device *dev, void *data,
  844. struct drm_file *file_priv)
  845. {
  846. /* Never copy - 2.4.x doesn't need it */
  847. return 0;
  848. }
  849. static void i810_dma_dispatch_mc(struct drm_device *dev, struct drm_buf *buf, int used,
  850. unsigned int last_render)
  851. {
  852. drm_i810_private_t *dev_priv = dev->dev_private;
  853. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  854. drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
  855. unsigned long address = (unsigned long)buf->bus_address;
  856. unsigned long start = address - dev->agp->base;
  857. int u;
  858. RING_LOCALS;
  859. i810_kernel_lost_context(dev);
  860. u = cmpxchg(buf_priv->in_use, I810_BUF_CLIENT, I810_BUF_HARDWARE);
  861. if (u != I810_BUF_CLIENT)
  862. DRM_DEBUG("MC found buffer that isn't mine!\n");
  863. if (used > 4 * 1024)
  864. used = 0;
  865. sarea_priv->dirty = 0x7f;
  866. DRM_DEBUG("addr 0x%lx, used 0x%x\n", address, used);
  867. dev_priv->counter++;
  868. DRM_DEBUG("dispatch counter : %ld\n", dev_priv->counter);
  869. DRM_DEBUG("start : %lx\n", start);
  870. DRM_DEBUG("used : %d\n", used);
  871. DRM_DEBUG("start + used - 4 : %ld\n", start + used - 4);
  872. if (buf_priv->currently_mapped == I810_BUF_MAPPED) {
  873. if (used & 4) {
  874. *(u32 *) ((char *) buf_priv->virtual + used) = 0;
  875. used += 4;
  876. }
  877. i810_unmap_buffer(buf);
  878. }
  879. BEGIN_LP_RING(4);
  880. OUT_RING(CMD_OP_BATCH_BUFFER);
  881. OUT_RING(start | BB1_PROTECTED);
  882. OUT_RING(start + used - 4);
  883. OUT_RING(0);
  884. ADVANCE_LP_RING();
  885. BEGIN_LP_RING(8);
  886. OUT_RING(CMD_STORE_DWORD_IDX);
  887. OUT_RING(buf_priv->my_use_idx);
  888. OUT_RING(I810_BUF_FREE);
  889. OUT_RING(0);
  890. OUT_RING(CMD_STORE_DWORD_IDX);
  891. OUT_RING(16);
  892. OUT_RING(last_render);
  893. OUT_RING(0);
  894. ADVANCE_LP_RING();
  895. }
  896. static int i810_dma_mc(struct drm_device *dev, void *data,
  897. struct drm_file *file_priv)
  898. {
  899. struct drm_device_dma *dma = dev->dma;
  900. drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
  901. u32 *hw_status = dev_priv->hw_status_page;
  902. drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *)
  903. dev_priv->sarea_priv;
  904. drm_i810_mc_t *mc = data;
  905. LOCK_TEST_WITH_RETURN(dev, file_priv);
  906. if (mc->idx >= dma->buf_count || mc->idx < 0)
  907. return -EINVAL;
  908. i810_dma_dispatch_mc(dev, dma->buflist[mc->idx], mc->used,
  909. mc->last_render);
  910. atomic_add(mc->used, &dev->counts[_DRM_STAT_SECONDARY]);
  911. atomic_inc(&dev->counts[_DRM_STAT_DMA]);
  912. sarea_priv->last_enqueue = dev_priv->counter - 1;
  913. sarea_priv->last_dispatch = (int)hw_status[5];
  914. return 0;
  915. }
  916. static int i810_rstatus(struct drm_device *dev, void *data,
  917. struct drm_file *file_priv)
  918. {
  919. drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
  920. return (int)(((u32 *) (dev_priv->hw_status_page))[4]);
  921. }
  922. static int i810_ov0_info(struct drm_device *dev, void *data,
  923. struct drm_file *file_priv)
  924. {
  925. drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
  926. drm_i810_overlay_t *ov = data;
  927. ov->offset = dev_priv->overlay_offset;
  928. ov->physical = dev_priv->overlay_physical;
  929. return 0;
  930. }
  931. static int i810_fstatus(struct drm_device *dev, void *data,
  932. struct drm_file *file_priv)
  933. {
  934. drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
  935. LOCK_TEST_WITH_RETURN(dev, file_priv);
  936. return I810_READ(0x30008);
  937. }
  938. static int i810_ov0_flip(struct drm_device *dev, void *data,
  939. struct drm_file *file_priv)
  940. {
  941. drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
  942. LOCK_TEST_WITH_RETURN(dev, file_priv);
  943. /* Tell the overlay to update */
  944. I810_WRITE(0x30000, dev_priv->overlay_physical | 0x80000000);
  945. return 0;
  946. }
  947. /* Not sure why this isn't set all the time:
  948. */
  949. static void i810_do_init_pageflip(struct drm_device *dev)
  950. {
  951. drm_i810_private_t *dev_priv = dev->dev_private;
  952. DRM_DEBUG("\n");
  953. dev_priv->page_flipping = 1;
  954. dev_priv->current_page = 0;
  955. dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
  956. }
  957. static int i810_do_cleanup_pageflip(struct drm_device *dev)
  958. {
  959. drm_i810_private_t *dev_priv = dev->dev_private;
  960. DRM_DEBUG("\n");
  961. if (dev_priv->current_page != 0)
  962. i810_dma_dispatch_flip(dev);
  963. dev_priv->page_flipping = 0;
  964. return 0;
  965. }
  966. static int i810_flip_bufs(struct drm_device *dev, void *data,
  967. struct drm_file *file_priv)
  968. {
  969. drm_i810_private_t *dev_priv = dev->dev_private;
  970. DRM_DEBUG("\n");
  971. LOCK_TEST_WITH_RETURN(dev, file_priv);
  972. if (!dev_priv->page_flipping)
  973. i810_do_init_pageflip(dev);
  974. i810_dma_dispatch_flip(dev);
  975. return 0;
  976. }
  977. int i810_driver_load(struct drm_device *dev, unsigned long flags)
  978. {
  979. /* i810 has 4 more counters */
  980. dev->counters += 4;
  981. dev->types[6] = _DRM_STAT_IRQ;
  982. dev->types[7] = _DRM_STAT_PRIMARY;
  983. dev->types[8] = _DRM_STAT_SECONDARY;
  984. dev->types[9] = _DRM_STAT_DMA;
  985. pci_set_master(dev->pdev);
  986. return 0;
  987. }
  988. void i810_driver_lastclose(struct drm_device *dev)
  989. {
  990. i810_dma_cleanup(dev);
  991. }
  992. void i810_driver_preclose(struct drm_device *dev, struct drm_file *file_priv)
  993. {
  994. if (dev->dev_private) {
  995. drm_i810_private_t *dev_priv = dev->dev_private;
  996. if (dev_priv->page_flipping)
  997. i810_do_cleanup_pageflip(dev);
  998. }
  999. }
  1000. void i810_driver_reclaim_buffers_locked(struct drm_device *dev,
  1001. struct drm_file *file_priv)
  1002. {
  1003. i810_reclaim_buffers(dev, file_priv);
  1004. }
  1005. int i810_driver_dma_quiescent(struct drm_device *dev)
  1006. {
  1007. i810_dma_quiescent(dev);
  1008. return 0;
  1009. }
  1010. struct drm_ioctl_desc i810_ioctls[] = {
  1011. DRM_IOCTL_DEF_DRV(I810_INIT, i810_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
  1012. DRM_IOCTL_DEF_DRV(I810_VERTEX, i810_dma_vertex, DRM_AUTH|DRM_UNLOCKED),
  1013. DRM_IOCTL_DEF_DRV(I810_CLEAR, i810_clear_bufs, DRM_AUTH|DRM_UNLOCKED),
  1014. DRM_IOCTL_DEF_DRV(I810_FLUSH, i810_flush_ioctl, DRM_AUTH|DRM_UNLOCKED),
  1015. DRM_IOCTL_DEF_DRV(I810_GETAGE, i810_getage, DRM_AUTH|DRM_UNLOCKED),
  1016. DRM_IOCTL_DEF_DRV(I810_GETBUF, i810_getbuf, DRM_AUTH|DRM_UNLOCKED),
  1017. DRM_IOCTL_DEF_DRV(I810_SWAP, i810_swap_bufs, DRM_AUTH|DRM_UNLOCKED),
  1018. DRM_IOCTL_DEF_DRV(I810_COPY, i810_copybuf, DRM_AUTH|DRM_UNLOCKED),
  1019. DRM_IOCTL_DEF_DRV(I810_DOCOPY, i810_docopy, DRM_AUTH|DRM_UNLOCKED),
  1020. DRM_IOCTL_DEF_DRV(I810_OV0INFO, i810_ov0_info, DRM_AUTH|DRM_UNLOCKED),
  1021. DRM_IOCTL_DEF_DRV(I810_FSTATUS, i810_fstatus, DRM_AUTH|DRM_UNLOCKED),
  1022. DRM_IOCTL_DEF_DRV(I810_OV0FLIP, i810_ov0_flip, DRM_AUTH|DRM_UNLOCKED),
  1023. DRM_IOCTL_DEF_DRV(I810_MC, i810_dma_mc, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
  1024. DRM_IOCTL_DEF_DRV(I810_RSTATUS, i810_rstatus, DRM_AUTH|DRM_UNLOCKED),
  1025. DRM_IOCTL_DEF_DRV(I810_FLIP, i810_flip_bufs, DRM_AUTH|DRM_UNLOCKED),
  1026. };
  1027. int i810_max_ioctl = DRM_ARRAY_SIZE(i810_ioctls);
  1028. /**
  1029. * Determine if the device really is AGP or not.
  1030. *
  1031. * All Intel graphics chipsets are treated as AGP, even if they are really
  1032. * PCI-e.
  1033. *
  1034. * \param dev The device to be tested.
  1035. *
  1036. * \returns
  1037. * A value of 1 is always retured to indictate every i810 is AGP.
  1038. */
  1039. int i810_driver_device_is_agp(struct drm_device *dev)
  1040. {
  1041. return 1;
  1042. }