exynos_tmu.c 15 KB

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  1. /*
  2. * exynos_tmu.c - Samsung EXYNOS TMU (Thermal Management Unit)
  3. *
  4. * Copyright (C) 2011 Samsung Electronics
  5. * Donggeun Kim <dg77.kim@samsung.com>
  6. * Amit Daniel Kachhap <amit.kachhap@linaro.org>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2 of the License, or
  11. * (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  21. *
  22. */
  23. #include <linux/clk.h>
  24. #include <linux/io.h>
  25. #include <linux/interrupt.h>
  26. #include <linux/module.h>
  27. #include <linux/of.h>
  28. #include <linux/platform_device.h>
  29. #include "exynos_thermal_common.h"
  30. #include "exynos_tmu.h"
  31. #include "exynos_tmu_data.h"
  32. struct exynos_tmu_data {
  33. struct exynos_tmu_platform_data *pdata;
  34. struct resource *mem;
  35. void __iomem *base;
  36. int irq;
  37. enum soc_type soc;
  38. struct work_struct irq_work;
  39. struct mutex lock;
  40. struct clk *clk;
  41. u8 temp_error1, temp_error2;
  42. };
  43. /*
  44. * TMU treats temperature as a mapped temperature code.
  45. * The temperature is converted differently depending on the calibration type.
  46. */
  47. static int temp_to_code(struct exynos_tmu_data *data, u8 temp)
  48. {
  49. struct exynos_tmu_platform_data *pdata = data->pdata;
  50. int temp_code;
  51. if (data->soc == SOC_ARCH_EXYNOS4210)
  52. /* temp should range between 25 and 125 */
  53. if (temp < 25 || temp > 125) {
  54. temp_code = -EINVAL;
  55. goto out;
  56. }
  57. switch (pdata->cal_type) {
  58. case TYPE_TWO_POINT_TRIMMING:
  59. temp_code = (temp - pdata->first_point_trim) *
  60. (data->temp_error2 - data->temp_error1) /
  61. (pdata->second_point_trim - pdata->first_point_trim) +
  62. data->temp_error1;
  63. break;
  64. case TYPE_ONE_POINT_TRIMMING:
  65. temp_code = temp + data->temp_error1 - pdata->first_point_trim;
  66. break;
  67. default:
  68. temp_code = temp + pdata->default_temp_offset;
  69. break;
  70. }
  71. out:
  72. return temp_code;
  73. }
  74. /*
  75. * Calculate a temperature value from a temperature code.
  76. * The unit of the temperature is degree Celsius.
  77. */
  78. static int code_to_temp(struct exynos_tmu_data *data, u8 temp_code)
  79. {
  80. struct exynos_tmu_platform_data *pdata = data->pdata;
  81. int temp;
  82. if (data->soc == SOC_ARCH_EXYNOS4210)
  83. /* temp_code should range between 75 and 175 */
  84. if (temp_code < 75 || temp_code > 175) {
  85. temp = -ENODATA;
  86. goto out;
  87. }
  88. switch (pdata->cal_type) {
  89. case TYPE_TWO_POINT_TRIMMING:
  90. temp = (temp_code - data->temp_error1) *
  91. (pdata->second_point_trim - pdata->first_point_trim) /
  92. (data->temp_error2 - data->temp_error1) +
  93. pdata->first_point_trim;
  94. break;
  95. case TYPE_ONE_POINT_TRIMMING:
  96. temp = temp_code - data->temp_error1 + pdata->first_point_trim;
  97. break;
  98. default:
  99. temp = temp_code - pdata->default_temp_offset;
  100. break;
  101. }
  102. out:
  103. return temp;
  104. }
  105. static int exynos_tmu_initialize(struct platform_device *pdev)
  106. {
  107. struct exynos_tmu_data *data = platform_get_drvdata(pdev);
  108. struct exynos_tmu_platform_data *pdata = data->pdata;
  109. const struct exynos_tmu_registers *reg = pdata->registers;
  110. unsigned int status, trim_info = 0, con;
  111. unsigned int rising_threshold = 0, falling_threshold = 0;
  112. int ret = 0, threshold_code, i, trigger_levs = 0;
  113. mutex_lock(&data->lock);
  114. clk_enable(data->clk);
  115. status = readb(data->base + reg->tmu_status);
  116. if (!status) {
  117. ret = -EBUSY;
  118. goto out;
  119. }
  120. if (data->soc == SOC_ARCH_EXYNOS)
  121. __raw_writel(1, data->base + reg->triminfo_ctrl);
  122. /* Save trimming info in order to perform calibration */
  123. trim_info = readl(data->base + reg->triminfo_data);
  124. data->temp_error1 = trim_info & EXYNOS_TMU_TEMP_MASK;
  125. data->temp_error2 = ((trim_info >> reg->triminfo_85_shift) &
  126. EXYNOS_TMU_TEMP_MASK);
  127. if ((pdata->min_efuse_value > data->temp_error1) ||
  128. (data->temp_error1 > pdata->max_efuse_value) ||
  129. (data->temp_error2 != 0))
  130. data->temp_error1 = pdata->efuse_value;
  131. if (pdata->max_trigger_level > MAX_THRESHOLD_LEVS) {
  132. dev_err(&pdev->dev, "Invalid max trigger level\n");
  133. goto out;
  134. }
  135. for (i = 0; i < pdata->max_trigger_level; i++) {
  136. if (!pdata->trigger_levels[i])
  137. continue;
  138. if ((pdata->trigger_type[i] == HW_TRIP) &&
  139. (!pdata->trigger_levels[pdata->max_trigger_level - 1])) {
  140. dev_err(&pdev->dev, "Invalid hw trigger level\n");
  141. ret = -EINVAL;
  142. goto out;
  143. }
  144. /* Count trigger levels except the HW trip*/
  145. if (!(pdata->trigger_type[i] == HW_TRIP))
  146. trigger_levs++;
  147. }
  148. if (data->soc == SOC_ARCH_EXYNOS4210) {
  149. /* Write temperature code for threshold */
  150. threshold_code = temp_to_code(data, pdata->threshold);
  151. if (threshold_code < 0) {
  152. ret = threshold_code;
  153. goto out;
  154. }
  155. writeb(threshold_code,
  156. data->base + reg->threshold_temp);
  157. for (i = 0; i < trigger_levs; i++)
  158. writeb(pdata->trigger_levels[i], data->base +
  159. reg->threshold_th0 + i * sizeof(reg->threshold_th0));
  160. writel(reg->inten_rise_mask, data->base + reg->tmu_intclear);
  161. } else if (data->soc == SOC_ARCH_EXYNOS) {
  162. /* Write temperature code for rising and falling threshold */
  163. for (i = 0;
  164. i < trigger_levs && i < EXYNOS_MAX_TRIGGER_PER_REG; i++) {
  165. threshold_code = temp_to_code(data,
  166. pdata->trigger_levels[i]);
  167. if (threshold_code < 0) {
  168. ret = threshold_code;
  169. goto out;
  170. }
  171. rising_threshold |= threshold_code << 8 * i;
  172. if (pdata->threshold_falling) {
  173. threshold_code = temp_to_code(data,
  174. pdata->trigger_levels[i] -
  175. pdata->threshold_falling);
  176. if (threshold_code > 0)
  177. falling_threshold |=
  178. threshold_code << 8 * i;
  179. }
  180. }
  181. writel(rising_threshold,
  182. data->base + reg->threshold_th0);
  183. writel(falling_threshold,
  184. data->base + reg->threshold_th1);
  185. writel((reg->inten_rise_mask << reg->inten_rise_shift) |
  186. (reg->inten_fall_mask << reg->inten_fall_shift),
  187. data->base + reg->tmu_intclear);
  188. /* if last threshold limit is also present */
  189. i = pdata->max_trigger_level - 1;
  190. if (pdata->trigger_levels[i] &&
  191. (pdata->trigger_type[i] == HW_TRIP)) {
  192. threshold_code = temp_to_code(data,
  193. pdata->trigger_levels[i]);
  194. if (threshold_code < 0) {
  195. ret = threshold_code;
  196. goto out;
  197. }
  198. rising_threshold |= threshold_code << 8 * i;
  199. writel(rising_threshold,
  200. data->base + reg->threshold_th0);
  201. con = readl(data->base + reg->tmu_ctrl);
  202. con |= (1 << reg->therm_trip_en_shift);
  203. writel(con, data->base + reg->tmu_ctrl);
  204. }
  205. }
  206. out:
  207. clk_disable(data->clk);
  208. mutex_unlock(&data->lock);
  209. return ret;
  210. }
  211. static void exynos_tmu_control(struct platform_device *pdev, bool on)
  212. {
  213. struct exynos_tmu_data *data = platform_get_drvdata(pdev);
  214. struct exynos_tmu_platform_data *pdata = data->pdata;
  215. const struct exynos_tmu_registers *reg = pdata->registers;
  216. unsigned int con, interrupt_en;
  217. mutex_lock(&data->lock);
  218. clk_enable(data->clk);
  219. con = readl(data->base + reg->tmu_ctrl);
  220. if (pdata->reference_voltage) {
  221. con &= ~(reg->buf_vref_sel_mask << reg->buf_vref_sel_shift);
  222. con |= pdata->reference_voltage << reg->buf_vref_sel_shift;
  223. }
  224. if (pdata->gain) {
  225. con &= ~(reg->buf_slope_sel_mask << reg->buf_slope_sel_shift);
  226. con |= (pdata->gain << reg->buf_slope_sel_shift);
  227. }
  228. if (pdata->noise_cancel_mode) {
  229. con &= ~(reg->therm_trip_mode_mask <<
  230. reg->therm_trip_mode_shift);
  231. con |= (pdata->noise_cancel_mode << reg->therm_trip_mode_shift);
  232. }
  233. if (on) {
  234. con |= (1 << reg->core_en_shift);
  235. interrupt_en =
  236. pdata->trigger_enable[3] << reg->inten_rise3_shift |
  237. pdata->trigger_enable[2] << reg->inten_rise2_shift |
  238. pdata->trigger_enable[1] << reg->inten_rise1_shift |
  239. pdata->trigger_enable[0] << reg->inten_rise0_shift;
  240. if (pdata->threshold_falling)
  241. interrupt_en |=
  242. interrupt_en << reg->inten_fall0_shift;
  243. } else {
  244. con &= ~(1 << reg->core_en_shift);
  245. interrupt_en = 0; /* Disable all interrupts */
  246. }
  247. writel(interrupt_en, data->base + reg->tmu_inten);
  248. writel(con, data->base + reg->tmu_ctrl);
  249. clk_disable(data->clk);
  250. mutex_unlock(&data->lock);
  251. }
  252. static int exynos_tmu_read(struct exynos_tmu_data *data)
  253. {
  254. struct exynos_tmu_platform_data *pdata = data->pdata;
  255. const struct exynos_tmu_registers *reg = pdata->registers;
  256. u8 temp_code;
  257. int temp;
  258. mutex_lock(&data->lock);
  259. clk_enable(data->clk);
  260. temp_code = readb(data->base + reg->tmu_cur_temp);
  261. temp = code_to_temp(data, temp_code);
  262. clk_disable(data->clk);
  263. mutex_unlock(&data->lock);
  264. return temp;
  265. }
  266. #ifdef CONFIG_THERMAL_EMULATION
  267. static int exynos_tmu_set_emulation(void *drv_data, unsigned long temp)
  268. {
  269. struct exynos_tmu_data *data = drv_data;
  270. struct exynos_tmu_platform_data *pdata = data->pdata;
  271. const struct exynos_tmu_registers *reg = pdata->registers;
  272. unsigned int val;
  273. int ret = -EINVAL;
  274. if (data->soc == SOC_ARCH_EXYNOS4210)
  275. goto out;
  276. if (temp && temp < MCELSIUS)
  277. goto out;
  278. mutex_lock(&data->lock);
  279. clk_enable(data->clk);
  280. val = readl(data->base + reg->emul_con);
  281. if (temp) {
  282. temp /= MCELSIUS;
  283. val = (EXYNOS_EMUL_TIME << reg->emul_time_shift) |
  284. (temp_to_code(data, temp)
  285. << reg->emul_temp_shift) | EXYNOS_EMUL_ENABLE;
  286. } else {
  287. val &= ~EXYNOS_EMUL_ENABLE;
  288. }
  289. writel(val, data->base + reg->emul_con);
  290. clk_disable(data->clk);
  291. mutex_unlock(&data->lock);
  292. return 0;
  293. out:
  294. return ret;
  295. }
  296. #else
  297. static int exynos_tmu_set_emulation(void *drv_data, unsigned long temp)
  298. { return -EINVAL; }
  299. #endif/*CONFIG_THERMAL_EMULATION*/
  300. static void exynos_tmu_work(struct work_struct *work)
  301. {
  302. struct exynos_tmu_data *data = container_of(work,
  303. struct exynos_tmu_data, irq_work);
  304. struct exynos_tmu_platform_data *pdata = data->pdata;
  305. const struct exynos_tmu_registers *reg = pdata->registers;
  306. unsigned int val_irq;
  307. exynos_report_trigger();
  308. mutex_lock(&data->lock);
  309. clk_enable(data->clk);
  310. /* TODO: take action based on particular interrupt */
  311. val_irq = readl(data->base + reg->tmu_intstat);
  312. /* clear the interrupts */
  313. writel(val_irq, data->base + reg->tmu_intclear);
  314. clk_disable(data->clk);
  315. mutex_unlock(&data->lock);
  316. enable_irq(data->irq);
  317. }
  318. static irqreturn_t exynos_tmu_irq(int irq, void *id)
  319. {
  320. struct exynos_tmu_data *data = id;
  321. disable_irq_nosync(irq);
  322. schedule_work(&data->irq_work);
  323. return IRQ_HANDLED;
  324. }
  325. static struct thermal_sensor_conf exynos_sensor_conf = {
  326. .name = "exynos-therm",
  327. .read_temperature = (int (*)(void *))exynos_tmu_read,
  328. .write_emul_temp = exynos_tmu_set_emulation,
  329. };
  330. #ifdef CONFIG_OF
  331. static const struct of_device_id exynos_tmu_match[] = {
  332. {
  333. .compatible = "samsung,exynos4210-tmu",
  334. .data = (void *)EXYNOS4210_TMU_DRV_DATA,
  335. },
  336. {
  337. .compatible = "samsung,exynos4412-tmu",
  338. .data = (void *)EXYNOS5250_TMU_DRV_DATA,
  339. },
  340. {
  341. .compatible = "samsung,exynos5250-tmu",
  342. .data = (void *)EXYNOS5250_TMU_DRV_DATA,
  343. },
  344. {},
  345. };
  346. MODULE_DEVICE_TABLE(of, exynos_tmu_match);
  347. #endif
  348. static struct platform_device_id exynos_tmu_driver_ids[] = {
  349. {
  350. .name = "exynos4210-tmu",
  351. .driver_data = (kernel_ulong_t)EXYNOS4210_TMU_DRV_DATA,
  352. },
  353. {
  354. .name = "exynos5250-tmu",
  355. .driver_data = (kernel_ulong_t)EXYNOS5250_TMU_DRV_DATA,
  356. },
  357. { },
  358. };
  359. MODULE_DEVICE_TABLE(platform, exynos_tmu_driver_ids);
  360. static inline struct exynos_tmu_platform_data *exynos_get_driver_data(
  361. struct platform_device *pdev)
  362. {
  363. #ifdef CONFIG_OF
  364. if (pdev->dev.of_node) {
  365. const struct of_device_id *match;
  366. match = of_match_node(exynos_tmu_match, pdev->dev.of_node);
  367. if (!match)
  368. return NULL;
  369. return (struct exynos_tmu_platform_data *) match->data;
  370. }
  371. #endif
  372. return (struct exynos_tmu_platform_data *)
  373. platform_get_device_id(pdev)->driver_data;
  374. }
  375. static int exynos_tmu_probe(struct platform_device *pdev)
  376. {
  377. struct exynos_tmu_data *data;
  378. struct exynos_tmu_platform_data *pdata = pdev->dev.platform_data;
  379. int ret, i;
  380. if (!pdata)
  381. pdata = exynos_get_driver_data(pdev);
  382. if (!pdata) {
  383. dev_err(&pdev->dev, "No platform init data supplied.\n");
  384. return -ENODEV;
  385. }
  386. data = devm_kzalloc(&pdev->dev, sizeof(struct exynos_tmu_data),
  387. GFP_KERNEL);
  388. if (!data) {
  389. dev_err(&pdev->dev, "Failed to allocate driver structure\n");
  390. return -ENOMEM;
  391. }
  392. data->irq = platform_get_irq(pdev, 0);
  393. if (data->irq < 0) {
  394. dev_err(&pdev->dev, "Failed to get platform irq\n");
  395. return data->irq;
  396. }
  397. INIT_WORK(&data->irq_work, exynos_tmu_work);
  398. data->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  399. data->base = devm_ioremap_resource(&pdev->dev, data->mem);
  400. if (IS_ERR(data->base))
  401. return PTR_ERR(data->base);
  402. ret = devm_request_irq(&pdev->dev, data->irq, exynos_tmu_irq,
  403. IRQF_TRIGGER_RISING, "exynos-tmu", data);
  404. if (ret) {
  405. dev_err(&pdev->dev, "Failed to request irq: %d\n", data->irq);
  406. return ret;
  407. }
  408. data->clk = devm_clk_get(&pdev->dev, "tmu_apbif");
  409. if (IS_ERR(data->clk)) {
  410. dev_err(&pdev->dev, "Failed to get clock\n");
  411. return PTR_ERR(data->clk);
  412. }
  413. ret = clk_prepare(data->clk);
  414. if (ret)
  415. return ret;
  416. if (pdata->type == SOC_ARCH_EXYNOS ||
  417. pdata->type == SOC_ARCH_EXYNOS4210)
  418. data->soc = pdata->type;
  419. else {
  420. ret = -EINVAL;
  421. dev_err(&pdev->dev, "Platform not supported\n");
  422. goto err_clk;
  423. }
  424. data->pdata = pdata;
  425. platform_set_drvdata(pdev, data);
  426. mutex_init(&data->lock);
  427. ret = exynos_tmu_initialize(pdev);
  428. if (ret) {
  429. dev_err(&pdev->dev, "Failed to initialize TMU\n");
  430. goto err_clk;
  431. }
  432. exynos_tmu_control(pdev, true);
  433. /* Register the sensor with thermal management interface */
  434. (&exynos_sensor_conf)->private_data = data;
  435. exynos_sensor_conf.trip_data.trip_count = pdata->trigger_enable[0] +
  436. pdata->trigger_enable[1] + pdata->trigger_enable[2]+
  437. pdata->trigger_enable[3];
  438. for (i = 0; i < exynos_sensor_conf.trip_data.trip_count; i++)
  439. exynos_sensor_conf.trip_data.trip_val[i] =
  440. pdata->threshold + pdata->trigger_levels[i];
  441. exynos_sensor_conf.trip_data.trigger_falling = pdata->threshold_falling;
  442. exynos_sensor_conf.cooling_data.freq_clip_count =
  443. pdata->freq_tab_count;
  444. for (i = 0; i < pdata->freq_tab_count; i++) {
  445. exynos_sensor_conf.cooling_data.freq_data[i].freq_clip_max =
  446. pdata->freq_tab[i].freq_clip_max;
  447. exynos_sensor_conf.cooling_data.freq_data[i].temp_level =
  448. pdata->freq_tab[i].temp_level;
  449. }
  450. ret = exynos_register_thermal(&exynos_sensor_conf);
  451. if (ret) {
  452. dev_err(&pdev->dev, "Failed to register thermal interface\n");
  453. goto err_clk;
  454. }
  455. return 0;
  456. err_clk:
  457. clk_unprepare(data->clk);
  458. return ret;
  459. }
  460. static int exynos_tmu_remove(struct platform_device *pdev)
  461. {
  462. struct exynos_tmu_data *data = platform_get_drvdata(pdev);
  463. exynos_tmu_control(pdev, false);
  464. exynos_unregister_thermal();
  465. clk_unprepare(data->clk);
  466. return 0;
  467. }
  468. #ifdef CONFIG_PM_SLEEP
  469. static int exynos_tmu_suspend(struct device *dev)
  470. {
  471. exynos_tmu_control(to_platform_device(dev), false);
  472. return 0;
  473. }
  474. static int exynos_tmu_resume(struct device *dev)
  475. {
  476. struct platform_device *pdev = to_platform_device(dev);
  477. exynos_tmu_initialize(pdev);
  478. exynos_tmu_control(pdev, true);
  479. return 0;
  480. }
  481. static SIMPLE_DEV_PM_OPS(exynos_tmu_pm,
  482. exynos_tmu_suspend, exynos_tmu_resume);
  483. #define EXYNOS_TMU_PM (&exynos_tmu_pm)
  484. #else
  485. #define EXYNOS_TMU_PM NULL
  486. #endif
  487. static struct platform_driver exynos_tmu_driver = {
  488. .driver = {
  489. .name = "exynos-tmu",
  490. .owner = THIS_MODULE,
  491. .pm = EXYNOS_TMU_PM,
  492. .of_match_table = of_match_ptr(exynos_tmu_match),
  493. },
  494. .probe = exynos_tmu_probe,
  495. .remove = exynos_tmu_remove,
  496. .id_table = exynos_tmu_driver_ids,
  497. };
  498. module_platform_driver(exynos_tmu_driver);
  499. MODULE_DESCRIPTION("EXYNOS TMU Driver");
  500. MODULE_AUTHOR("Donggeun Kim <dg77.kim@samsung.com>");
  501. MODULE_LICENSE("GPL");
  502. MODULE_ALIAS("platform:exynos-tmu");