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linux-vybrid_pu...
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arch
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arm
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mach-davinci
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include
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mach
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asp.h

asp.h 2.1 KB
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  1. /*
    2. 

  2.  * <mach/asp.h> - DaVinci Audio Serial Port support
    3. 

  3.  */
    4. 

  4. #ifndef __ASM_ARCH_DAVINCI_ASP_H
    5. 

  5. #define __ASM_ARCH_DAVINCI_ASP_H
    6. 

  6. 

  7. #include <mach/irqs.h>
    8. 

  8. #include <mach/edma.h>
    9. 

  9. 

  10. /* Bases of dm644x and dm355 register banks */
    11. 

  11. #define DAVINCI_ASP0_BASE	0x01E02000
    12. 

  12. #define DAVINCI_ASP1_BASE	0x01E04000
    13. 

  13. 

  14. /* Bases of dm646x register banks */
    15. 

  15. #define	DAVINCI_DM646X_MCASP0_REG_BASE		0x01D01000
    16. 

  16. #define DAVINCI_DM646X_MCASP1_REG_BASE		0x01D01800
    17. 

  17. 

  18. /* Bases of da850/da830 McASP0  register banks */
    19. 

  19. #define DAVINCI_DA8XX_MCASP0_REG_BASE	0x01D00000
    20. 

  20. 

  21. /* Bases of da830 McASP1 register banks */
    22. 

  22. #define DAVINCI_DA830_MCASP1_REG_BASE	0x01D04000
    23. 

  23. 

  24. /* EDMA channels of dm644x and dm355 */
    25. 

  25. #define DAVINCI_DMA_ASP0_TX	2
    26. 

  26. #define DAVINCI_DMA_ASP0_RX	3
    27. 

  27. #define DAVINCI_DMA_ASP1_TX	8
    28. 

  28. #define DAVINCI_DMA_ASP1_RX	9
    29. 

  29. 

  30. /* EDMA channels of dm646x */
    31. 

  31. #define	DAVINCI_DM646X_DMA_MCASP0_AXEVT0	6
    32. 

  32. #define	DAVINCI_DM646X_DMA_MCASP0_AREVT0	9
    33. 

  33. #define	DAVINCI_DM646X_DMA_MCASP1_AXEVT1	12
    34. 

  34. 

  35. /* EDMA channels of da850/da830 McASP0 */
    36. 

  36. #define	DAVINCI_DA8XX_DMA_MCASP0_AREVT	0
    37. 

  37. #define	DAVINCI_DA8XX_DMA_MCASP0_AXEVT	1
    38. 

  38. 

  39. /* EDMA channels of da830 McASP1 */
    40. 

  40. #define	DAVINCI_DA830_DMA_MCASP1_AREVT	2
    41. 

  41. #define	DAVINCI_DA830_DMA_MCASP1_AXEVT	3
    42. 

  42. 

  43. /* Interrupts */
    44. 

  44. #define DAVINCI_ASP0_RX_INT	IRQ_MBRINT
    45. 

  45. #define DAVINCI_ASP0_TX_INT	IRQ_MBXINT
    46. 

  46. #define DAVINCI_ASP1_RX_INT	IRQ_MBRINT
    47. 

  47. #define DAVINCI_ASP1_TX_INT	IRQ_MBXINT
    48. 

  48. 

  49. struct snd_platform_data {
    50. 

  50. 	u32 tx_dma_offset;
    51. 

  51. 	u32 rx_dma_offset;
    52. 

  52. 	enum dma_event_q eventq_no;	/* event queue number */
    53. 

  53. 	unsigned int codec_fmt;
    54. 

  54. 	/*
    55. 

  55. 	 * Allowing this is more efficient and eliminates left and right swaps
    56. 

  56. 	 * caused by underruns, but will swap the left and right channels
    57. 

  57. 	 * when compared to previous behavior.
    58. 

  58. 	 */
    59. 

  59. 	unsigned enable_channel_combine:1;
    60. 

  60. 	unsigned sram_size_playback;
    61. 

  61. 	unsigned sram_size_capture;
    62. 

  62. 

  63. 	/* McASP specific fields */
    64. 

  64. 	int tdm_slots;
    65. 

  65. 	u8 op_mode;
    66. 

  66. 	u8 num_serializer;
    67. 

  67. 	u8 *serial_dir;
    68. 

  68. 	u8 version;
    69. 

  69. 	u8 txnumevt;
    70. 

  70. 	u8 rxnumevt;
    71. 

  71. };
    72. 

  72. 

  73. enum {
    74. 

  74. 	MCASP_VERSION_1 = 0,	/* DM646x */
    75. 

  75. 	MCASP_VERSION_2,	/* DA8xx/OMAPL1x */
    76. 

  76. };
    77. 

  77. 

  78. #define INACTIVE_MODE	0
    79. 

  79. #define TX_MODE		1
    80. 

  80. #define RX_MODE		2
    81. 

  81. 

  82. #define DAVINCI_MCASP_IIS_MODE	0
    83. 

  83. #define DAVINCI_MCASP_DIT_MODE	1
    84. 

  84. 

  85. #endif /* __ASM_ARCH_DAVINCI_ASP_H */
    86.