omap3isp.h 4.4 KB

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  1. /*
  2. * omap3isp.h
  3. *
  4. * TI OMAP3 ISP - Platform data
  5. *
  6. * Copyright (C) 2011 Nokia Corporation
  7. *
  8. * Contacts: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
  9. * Sakari Ailus <sakari.ailus@iki.fi>
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License version 2 as
  13. * published by the Free Software Foundation.
  14. *
  15. * This program is distributed in the hope that it will be useful, but
  16. * WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  18. * General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software
  22. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  23. * 02110-1301 USA
  24. */
  25. #ifndef __MEDIA_OMAP3ISP_H__
  26. #define __MEDIA_OMAP3ISP_H__
  27. struct i2c_board_info;
  28. struct isp_device;
  29. #define ISP_XCLK_NONE 0
  30. #define ISP_XCLK_A 1
  31. #define ISP_XCLK_B 2
  32. enum isp_interface_type {
  33. ISP_INTERFACE_PARALLEL,
  34. ISP_INTERFACE_CSI2A_PHY2,
  35. ISP_INTERFACE_CCP2B_PHY1,
  36. ISP_INTERFACE_CCP2B_PHY2,
  37. ISP_INTERFACE_CSI2C_PHY1,
  38. };
  39. enum {
  40. ISP_BRIDGE_DISABLE = 0,
  41. ISP_BRIDGE_LITTLE_ENDIAN = 2,
  42. ISP_BRIDGE_BIG_ENDIAN = 3,
  43. };
  44. enum {
  45. ISP_LANE_SHIFT_0 = 0,
  46. ISP_LANE_SHIFT_2 = 1,
  47. ISP_LANE_SHIFT_4 = 2,
  48. ISP_LANE_SHIFT_6 = 3,
  49. };
  50. /**
  51. * struct isp_parallel_platform_data - Parallel interface platform data
  52. * @data_lane_shift: Data lane shifter
  53. * ISP_LANE_SHIFT_0 - CAMEXT[13:0] -> CAM[13:0]
  54. * ISP_LANE_SHIFT_2 - CAMEXT[13:2] -> CAM[11:0]
  55. * ISP_LANE_SHIFT_4 - CAMEXT[13:4] -> CAM[9:0]
  56. * ISP_LANE_SHIFT_6 - CAMEXT[13:6] -> CAM[7:0]
  57. * @clk_pol: Pixel clock polarity
  58. * 0 - Sample on rising edge, 1 - Sample on falling edge
  59. * @hs_pol: Horizontal synchronization polarity
  60. * 0 - Active high, 1 - Active low
  61. * @vs_pol: Vertical synchronization polarity
  62. * 0 - Active high, 1 - Active low
  63. * @bridge: CCDC Bridge input control
  64. * ISP_BRIDGE_DISABLE - Disable
  65. * ISP_BRIDGE_LITTLE_ENDIAN - Little endian
  66. * ISP_BRIDGE_BIG_ENDIAN - Big endian
  67. */
  68. struct isp_parallel_platform_data {
  69. unsigned int data_lane_shift:2;
  70. unsigned int clk_pol:1;
  71. unsigned int hs_pol:1;
  72. unsigned int vs_pol:1;
  73. unsigned int bridge:2;
  74. };
  75. enum {
  76. ISP_CCP2_PHY_DATA_CLOCK = 0,
  77. ISP_CCP2_PHY_DATA_STROBE = 1,
  78. };
  79. enum {
  80. ISP_CCP2_MODE_MIPI = 0,
  81. ISP_CCP2_MODE_CCP2 = 1,
  82. };
  83. /**
  84. * struct isp_csiphy_lane: CCP2/CSI2 lane position and polarity
  85. * @pos: position of the lane
  86. * @pol: polarity of the lane
  87. */
  88. struct isp_csiphy_lane {
  89. u8 pos;
  90. u8 pol;
  91. };
  92. #define ISP_CSIPHY1_NUM_DATA_LANES 1
  93. #define ISP_CSIPHY2_NUM_DATA_LANES 2
  94. /**
  95. * struct isp_csiphy_lanes_cfg - CCP2/CSI2 lane configuration
  96. * @data: Configuration of one or two data lanes
  97. * @clk: Clock lane configuration
  98. */
  99. struct isp_csiphy_lanes_cfg {
  100. struct isp_csiphy_lane data[ISP_CSIPHY2_NUM_DATA_LANES];
  101. struct isp_csiphy_lane clk;
  102. };
  103. /**
  104. * struct isp_ccp2_platform_data - CCP2 interface platform data
  105. * @strobe_clk_pol: Strobe/clock polarity
  106. * 0 - Non Inverted, 1 - Inverted
  107. * @crc: Enable the cyclic redundancy check
  108. * @ccp2_mode: Enable CCP2 compatibility mode
  109. * ISP_CCP2_MODE_MIPI - MIPI-CSI1 mode
  110. * ISP_CCP2_MODE_CCP2 - CCP2 mode
  111. * @phy_layer: Physical layer selection
  112. * ISP_CCP2_PHY_DATA_CLOCK - Data/clock physical layer
  113. * ISP_CCP2_PHY_DATA_STROBE - Data/strobe physical layer
  114. * @vpclk_div: Video port output clock control
  115. */
  116. struct isp_ccp2_platform_data {
  117. unsigned int strobe_clk_pol:1;
  118. unsigned int crc:1;
  119. unsigned int ccp2_mode:1;
  120. unsigned int phy_layer:1;
  121. unsigned int vpclk_div:2;
  122. struct isp_csiphy_lanes_cfg lanecfg;
  123. };
  124. /**
  125. * struct isp_csi2_platform_data - CSI2 interface platform data
  126. * @crc: Enable the cyclic redundancy check
  127. * @vpclk_div: Video port output clock control
  128. */
  129. struct isp_csi2_platform_data {
  130. unsigned crc:1;
  131. unsigned vpclk_div:2;
  132. struct isp_csiphy_lanes_cfg lanecfg;
  133. };
  134. struct isp_subdev_i2c_board_info {
  135. struct i2c_board_info *board_info;
  136. int i2c_adapter_id;
  137. };
  138. struct isp_v4l2_subdevs_group {
  139. struct isp_subdev_i2c_board_info *subdevs;
  140. enum isp_interface_type interface;
  141. union {
  142. struct isp_parallel_platform_data parallel;
  143. struct isp_ccp2_platform_data ccp2;
  144. struct isp_csi2_platform_data csi2;
  145. } bus; /* gcc < 4.6.0 chokes on anonymous union initializers */
  146. };
  147. struct isp_platform_data {
  148. struct isp_v4l2_subdevs_group *subdevs;
  149. void (*set_constraints)(struct isp_device *isp, bool enable);
  150. };
  151. #endif /* __MEDIA_OMAP3ISP_H__ */