s3c2410_wdt.c 13 KB

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  1. /* linux/drivers/char/watchdog/s3c2410_wdt.c
  2. *
  3. * Copyright (c) 2004 Simtec Electronics
  4. * Ben Dooks <ben@simtec.co.uk>
  5. *
  6. * S3C2410 Watchdog Timer Support
  7. *
  8. * Based on, softdog.c by Alan Cox,
  9. * (c) Copyright 1996 Alan Cox <alan@lxorguk.ukuu.org.uk>
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License as published by
  13. * the Free Software Foundation; either version 2 of the License, or
  14. * (at your option) any later version.
  15. *
  16. * This program is distributed in the hope that it will be useful,
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19. * GNU General Public License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with this program; if not, write to the Free Software
  23. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  24. */
  25. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  26. #include <linux/module.h>
  27. #include <linux/moduleparam.h>
  28. #include <linux/types.h>
  29. #include <linux/timer.h>
  30. #include <linux/miscdevice.h> /* for MODULE_ALIAS_MISCDEV */
  31. #include <linux/watchdog.h>
  32. #include <linux/init.h>
  33. #include <linux/platform_device.h>
  34. #include <linux/interrupt.h>
  35. #include <linux/clk.h>
  36. #include <linux/uaccess.h>
  37. #include <linux/io.h>
  38. #include <linux/cpufreq.h>
  39. #include <linux/slab.h>
  40. #include <linux/err.h>
  41. #include <linux/of.h>
  42. #include <mach/map.h>
  43. #undef S3C_VA_WATCHDOG
  44. #define S3C_VA_WATCHDOG (0)
  45. #include <plat/regs-watchdog.h>
  46. #define CONFIG_S3C2410_WATCHDOG_ATBOOT (0)
  47. #define CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME (15)
  48. static bool nowayout = WATCHDOG_NOWAYOUT;
  49. static int tmr_margin = CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME;
  50. static int tmr_atboot = CONFIG_S3C2410_WATCHDOG_ATBOOT;
  51. static int soft_noboot;
  52. static int debug;
  53. module_param(tmr_margin, int, 0);
  54. module_param(tmr_atboot, int, 0);
  55. module_param(nowayout, bool, 0);
  56. module_param(soft_noboot, int, 0);
  57. module_param(debug, int, 0);
  58. MODULE_PARM_DESC(tmr_margin, "Watchdog tmr_margin in seconds. (default="
  59. __MODULE_STRING(CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME) ")");
  60. MODULE_PARM_DESC(tmr_atboot,
  61. "Watchdog is started at boot time if set to 1, default="
  62. __MODULE_STRING(CONFIG_S3C2410_WATCHDOG_ATBOOT));
  63. MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
  64. __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
  65. MODULE_PARM_DESC(soft_noboot, "Watchdog action, set to 1 to ignore reboots, "
  66. "0 to reboot (default 0)");
  67. MODULE_PARM_DESC(debug, "Watchdog debug, set to >1 for debug (default 0)");
  68. static struct device *wdt_dev; /* platform device attached to */
  69. static struct resource *wdt_mem;
  70. static struct resource *wdt_irq;
  71. static struct clk *wdt_clock;
  72. static void __iomem *wdt_base;
  73. static unsigned int wdt_count;
  74. static DEFINE_SPINLOCK(wdt_lock);
  75. /* watchdog control routines */
  76. #define DBG(fmt, ...) \
  77. do { \
  78. if (debug) \
  79. pr_info(fmt, ##__VA_ARGS__); \
  80. } while (0)
  81. /* functions */
  82. static int s3c2410wdt_keepalive(struct watchdog_device *wdd)
  83. {
  84. spin_lock(&wdt_lock);
  85. writel(wdt_count, wdt_base + S3C2410_WTCNT);
  86. spin_unlock(&wdt_lock);
  87. return 0;
  88. }
  89. static void __s3c2410wdt_stop(void)
  90. {
  91. unsigned long wtcon;
  92. wtcon = readl(wdt_base + S3C2410_WTCON);
  93. wtcon &= ~(S3C2410_WTCON_ENABLE | S3C2410_WTCON_RSTEN);
  94. writel(wtcon, wdt_base + S3C2410_WTCON);
  95. }
  96. static int s3c2410wdt_stop(struct watchdog_device *wdd)
  97. {
  98. spin_lock(&wdt_lock);
  99. __s3c2410wdt_stop();
  100. spin_unlock(&wdt_lock);
  101. return 0;
  102. }
  103. static int s3c2410wdt_start(struct watchdog_device *wdd)
  104. {
  105. unsigned long wtcon;
  106. spin_lock(&wdt_lock);
  107. __s3c2410wdt_stop();
  108. wtcon = readl(wdt_base + S3C2410_WTCON);
  109. wtcon |= S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128;
  110. if (soft_noboot) {
  111. wtcon |= S3C2410_WTCON_INTEN;
  112. wtcon &= ~S3C2410_WTCON_RSTEN;
  113. } else {
  114. wtcon &= ~S3C2410_WTCON_INTEN;
  115. wtcon |= S3C2410_WTCON_RSTEN;
  116. }
  117. DBG("%s: wdt_count=0x%08x, wtcon=%08lx\n",
  118. __func__, wdt_count, wtcon);
  119. writel(wdt_count, wdt_base + S3C2410_WTDAT);
  120. writel(wdt_count, wdt_base + S3C2410_WTCNT);
  121. writel(wtcon, wdt_base + S3C2410_WTCON);
  122. spin_unlock(&wdt_lock);
  123. return 0;
  124. }
  125. static inline int s3c2410wdt_is_running(void)
  126. {
  127. return readl(wdt_base + S3C2410_WTCON) & S3C2410_WTCON_ENABLE;
  128. }
  129. static int s3c2410wdt_set_heartbeat(struct watchdog_device *wdd, unsigned timeout)
  130. {
  131. unsigned long freq = clk_get_rate(wdt_clock);
  132. unsigned int count;
  133. unsigned int divisor = 1;
  134. unsigned long wtcon;
  135. if (timeout < 1)
  136. return -EINVAL;
  137. freq /= 128;
  138. count = timeout * freq;
  139. DBG("%s: count=%d, timeout=%d, freq=%lu\n",
  140. __func__, count, timeout, freq);
  141. /* if the count is bigger than the watchdog register,
  142. then work out what we need to do (and if) we can
  143. actually make this value
  144. */
  145. if (count >= 0x10000) {
  146. for (divisor = 1; divisor <= 0x100; divisor++) {
  147. if ((count / divisor) < 0x10000)
  148. break;
  149. }
  150. if ((count / divisor) >= 0x10000) {
  151. dev_err(wdt_dev, "timeout %d too big\n", timeout);
  152. return -EINVAL;
  153. }
  154. }
  155. DBG("%s: timeout=%d, divisor=%d, count=%d (%08x)\n",
  156. __func__, timeout, divisor, count, count/divisor);
  157. count /= divisor;
  158. wdt_count = count;
  159. /* update the pre-scaler */
  160. wtcon = readl(wdt_base + S3C2410_WTCON);
  161. wtcon &= ~S3C2410_WTCON_PRESCALE_MASK;
  162. wtcon |= S3C2410_WTCON_PRESCALE(divisor-1);
  163. writel(count, wdt_base + S3C2410_WTDAT);
  164. writel(wtcon, wdt_base + S3C2410_WTCON);
  165. wdd->timeout = (count * divisor) / freq;
  166. return 0;
  167. }
  168. #define OPTIONS (WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE)
  169. static const struct watchdog_info s3c2410_wdt_ident = {
  170. .options = OPTIONS,
  171. .firmware_version = 0,
  172. .identity = "S3C2410 Watchdog",
  173. };
  174. static struct watchdog_ops s3c2410wdt_ops = {
  175. .owner = THIS_MODULE,
  176. .start = s3c2410wdt_start,
  177. .stop = s3c2410wdt_stop,
  178. .ping = s3c2410wdt_keepalive,
  179. .set_timeout = s3c2410wdt_set_heartbeat,
  180. };
  181. static struct watchdog_device s3c2410_wdd = {
  182. .info = &s3c2410_wdt_ident,
  183. .ops = &s3c2410wdt_ops,
  184. };
  185. /* interrupt handler code */
  186. static irqreturn_t s3c2410wdt_irq(int irqno, void *param)
  187. {
  188. dev_info(wdt_dev, "watchdog timer expired (irq)\n");
  189. s3c2410wdt_keepalive(&s3c2410_wdd);
  190. return IRQ_HANDLED;
  191. }
  192. #ifdef CONFIG_CPU_FREQ
  193. static int s3c2410wdt_cpufreq_transition(struct notifier_block *nb,
  194. unsigned long val, void *data)
  195. {
  196. int ret;
  197. if (!s3c2410wdt_is_running())
  198. goto done;
  199. if (val == CPUFREQ_PRECHANGE) {
  200. /* To ensure that over the change we don't cause the
  201. * watchdog to trigger, we perform an keep-alive if
  202. * the watchdog is running.
  203. */
  204. s3c2410wdt_keepalive(&s3c2410_wdd);
  205. } else if (val == CPUFREQ_POSTCHANGE) {
  206. s3c2410wdt_stop(&s3c2410_wdd);
  207. ret = s3c2410wdt_set_heartbeat(&s3c2410_wdd, s3c2410_wdd.timeout);
  208. if (ret >= 0)
  209. s3c2410wdt_start(&s3c2410_wdd);
  210. else
  211. goto err;
  212. }
  213. done:
  214. return 0;
  215. err:
  216. dev_err(wdt_dev, "cannot set new value for timeout %d\n",
  217. s3c2410_wdd.timeout);
  218. return ret;
  219. }
  220. static struct notifier_block s3c2410wdt_cpufreq_transition_nb = {
  221. .notifier_call = s3c2410wdt_cpufreq_transition,
  222. };
  223. static inline int s3c2410wdt_cpufreq_register(void)
  224. {
  225. return cpufreq_register_notifier(&s3c2410wdt_cpufreq_transition_nb,
  226. CPUFREQ_TRANSITION_NOTIFIER);
  227. }
  228. static inline void s3c2410wdt_cpufreq_deregister(void)
  229. {
  230. cpufreq_unregister_notifier(&s3c2410wdt_cpufreq_transition_nb,
  231. CPUFREQ_TRANSITION_NOTIFIER);
  232. }
  233. #else
  234. static inline int s3c2410wdt_cpufreq_register(void)
  235. {
  236. return 0;
  237. }
  238. static inline void s3c2410wdt_cpufreq_deregister(void)
  239. {
  240. }
  241. #endif
  242. static int __devinit s3c2410wdt_probe(struct platform_device *pdev)
  243. {
  244. struct device *dev;
  245. unsigned int wtcon;
  246. int started = 0;
  247. int ret;
  248. int size;
  249. DBG("%s: probe=%p\n", __func__, pdev);
  250. dev = &pdev->dev;
  251. wdt_dev = &pdev->dev;
  252. wdt_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  253. if (wdt_mem == NULL) {
  254. dev_err(dev, "no memory resource specified\n");
  255. return -ENOENT;
  256. }
  257. wdt_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  258. if (wdt_irq == NULL) {
  259. dev_err(dev, "no irq resource specified\n");
  260. ret = -ENOENT;
  261. goto err;
  262. }
  263. /* get the memory region for the watchdog timer */
  264. size = resource_size(wdt_mem);
  265. if (!request_mem_region(wdt_mem->start, size, pdev->name)) {
  266. dev_err(dev, "failed to get memory region\n");
  267. ret = -EBUSY;
  268. goto err;
  269. }
  270. wdt_base = ioremap(wdt_mem->start, size);
  271. if (wdt_base == NULL) {
  272. dev_err(dev, "failed to ioremap() region\n");
  273. ret = -EINVAL;
  274. goto err_req;
  275. }
  276. DBG("probe: mapped wdt_base=%p\n", wdt_base);
  277. wdt_clock = clk_get(&pdev->dev, "watchdog");
  278. if (IS_ERR(wdt_clock)) {
  279. dev_err(dev, "failed to find watchdog clock source\n");
  280. ret = PTR_ERR(wdt_clock);
  281. goto err_map;
  282. }
  283. clk_enable(wdt_clock);
  284. ret = s3c2410wdt_cpufreq_register();
  285. if (ret < 0) {
  286. pr_err("failed to register cpufreq\n");
  287. goto err_clk;
  288. }
  289. /* see if we can actually set the requested timer margin, and if
  290. * not, try the default value */
  291. if (s3c2410wdt_set_heartbeat(&s3c2410_wdd, tmr_margin)) {
  292. started = s3c2410wdt_set_heartbeat(&s3c2410_wdd,
  293. CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME);
  294. if (started == 0)
  295. dev_info(dev,
  296. "tmr_margin value out of range, default %d used\n",
  297. CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME);
  298. else
  299. dev_info(dev, "default timer value is out of range, "
  300. "cannot start\n");
  301. }
  302. ret = request_irq(wdt_irq->start, s3c2410wdt_irq, 0, pdev->name, pdev);
  303. if (ret != 0) {
  304. dev_err(dev, "failed to install irq (%d)\n", ret);
  305. goto err_cpufreq;
  306. }
  307. watchdog_set_nowayout(&s3c2410_wdd, nowayout);
  308. ret = watchdog_register_device(&s3c2410_wdd);
  309. if (ret) {
  310. dev_err(dev, "cannot register watchdog (%d)\n", ret);
  311. goto err_irq;
  312. }
  313. if (tmr_atboot && started == 0) {
  314. dev_info(dev, "starting watchdog timer\n");
  315. s3c2410wdt_start(&s3c2410_wdd);
  316. } else if (!tmr_atboot) {
  317. /* if we're not enabling the watchdog, then ensure it is
  318. * disabled if it has been left running from the bootloader
  319. * or other source */
  320. s3c2410wdt_stop(&s3c2410_wdd);
  321. }
  322. /* print out a statement of readiness */
  323. wtcon = readl(wdt_base + S3C2410_WTCON);
  324. dev_info(dev, "watchdog %sactive, reset %sabled, irq %sabled\n",
  325. (wtcon & S3C2410_WTCON_ENABLE) ? "" : "in",
  326. (wtcon & S3C2410_WTCON_RSTEN) ? "en" : "dis",
  327. (wtcon & S3C2410_WTCON_INTEN) ? "en" : "dis");
  328. return 0;
  329. err_irq:
  330. free_irq(wdt_irq->start, pdev);
  331. err_cpufreq:
  332. s3c2410wdt_cpufreq_deregister();
  333. err_clk:
  334. clk_disable(wdt_clock);
  335. clk_put(wdt_clock);
  336. wdt_clock = NULL;
  337. err_map:
  338. iounmap(wdt_base);
  339. err_req:
  340. release_mem_region(wdt_mem->start, size);
  341. err:
  342. wdt_irq = NULL;
  343. wdt_mem = NULL;
  344. return ret;
  345. }
  346. static int __devexit s3c2410wdt_remove(struct platform_device *dev)
  347. {
  348. watchdog_unregister_device(&s3c2410_wdd);
  349. free_irq(wdt_irq->start, dev);
  350. s3c2410wdt_cpufreq_deregister();
  351. clk_disable(wdt_clock);
  352. clk_put(wdt_clock);
  353. wdt_clock = NULL;
  354. iounmap(wdt_base);
  355. release_mem_region(wdt_mem->start, resource_size(wdt_mem));
  356. wdt_irq = NULL;
  357. wdt_mem = NULL;
  358. return 0;
  359. }
  360. static void s3c2410wdt_shutdown(struct platform_device *dev)
  361. {
  362. s3c2410wdt_stop(&s3c2410_wdd);
  363. }
  364. #ifdef CONFIG_PM
  365. static unsigned long wtcon_save;
  366. static unsigned long wtdat_save;
  367. static int s3c2410wdt_suspend(struct platform_device *dev, pm_message_t state)
  368. {
  369. /* Save watchdog state, and turn it off. */
  370. wtcon_save = readl(wdt_base + S3C2410_WTCON);
  371. wtdat_save = readl(wdt_base + S3C2410_WTDAT);
  372. /* Note that WTCNT doesn't need to be saved. */
  373. s3c2410wdt_stop(&s3c2410_wdd);
  374. return 0;
  375. }
  376. static int s3c2410wdt_resume(struct platform_device *dev)
  377. {
  378. /* Restore watchdog state. */
  379. writel(wtdat_save, wdt_base + S3C2410_WTDAT);
  380. writel(wtdat_save, wdt_base + S3C2410_WTCNT); /* Reset count */
  381. writel(wtcon_save, wdt_base + S3C2410_WTCON);
  382. pr_info("watchdog %sabled\n",
  383. (wtcon_save & S3C2410_WTCON_ENABLE) ? "en" : "dis");
  384. return 0;
  385. }
  386. #else
  387. #define s3c2410wdt_suspend NULL
  388. #define s3c2410wdt_resume NULL
  389. #endif /* CONFIG_PM */
  390. #ifdef CONFIG_OF
  391. static const struct of_device_id s3c2410_wdt_match[] = {
  392. { .compatible = "samsung,s3c2410-wdt" },
  393. {},
  394. };
  395. MODULE_DEVICE_TABLE(of, s3c2410_wdt_match);
  396. #endif
  397. static struct platform_driver s3c2410wdt_driver = {
  398. .probe = s3c2410wdt_probe,
  399. .remove = __devexit_p(s3c2410wdt_remove),
  400. .shutdown = s3c2410wdt_shutdown,
  401. .suspend = s3c2410wdt_suspend,
  402. .resume = s3c2410wdt_resume,
  403. .driver = {
  404. .owner = THIS_MODULE,
  405. .name = "s3c2410-wdt",
  406. .of_match_table = of_match_ptr(s3c2410_wdt_match),
  407. },
  408. };
  409. static int __init watchdog_init(void)
  410. {
  411. pr_info("S3C2410 Watchdog Timer, (c) 2004 Simtec Electronics\n");
  412. return platform_driver_register(&s3c2410wdt_driver);
  413. }
  414. static void __exit watchdog_exit(void)
  415. {
  416. platform_driver_unregister(&s3c2410wdt_driver);
  417. }
  418. module_init(watchdog_init);
  419. module_exit(watchdog_exit);
  420. MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>, "
  421. "Dimitry Andric <dimitry.andric@tomtom.com>");
  422. MODULE_DESCRIPTION("S3C2410 Watchdog Device Driver");
  423. MODULE_LICENSE("GPL");
  424. MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
  425. MODULE_ALIAS("platform:s3c2410-wdt");