vme_tsi148.c 71 KB

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  1. /*
  2. * Support for the Tundra TSI148 VME-PCI Bridge Chip
  3. *
  4. * Author: Martyn Welch <martyn.welch@ge.com>
  5. * Copyright 2008 GE Intelligent Platforms Embedded Systems, Inc.
  6. *
  7. * Based on work by Tom Armistead and Ajit Prem
  8. * Copyright 2004 Motorola Inc.
  9. *
  10. * This program is free software; you can redistribute it and/or modify it
  11. * under the terms of the GNU General Public License as published by the
  12. * Free Software Foundation; either version 2 of the License, or (at your
  13. * option) any later version.
  14. */
  15. #include <linux/module.h>
  16. #include <linux/moduleparam.h>
  17. #include <linux/mm.h>
  18. #include <linux/types.h>
  19. #include <linux/errno.h>
  20. #include <linux/proc_fs.h>
  21. #include <linux/pci.h>
  22. #include <linux/poll.h>
  23. #include <linux/dma-mapping.h>
  24. #include <linux/interrupt.h>
  25. #include <linux/spinlock.h>
  26. #include <linux/sched.h>
  27. #include <linux/slab.h>
  28. #include <linux/time.h>
  29. #include <linux/io.h>
  30. #include <linux/uaccess.h>
  31. #include <linux/byteorder/generic.h>
  32. #include <linux/vme.h>
  33. #include "../vme_bridge.h"
  34. #include "vme_tsi148.h"
  35. static int __init tsi148_init(void);
  36. static int tsi148_probe(struct pci_dev *, const struct pci_device_id *);
  37. static void tsi148_remove(struct pci_dev *);
  38. static void __exit tsi148_exit(void);
  39. /* Module parameter */
  40. static bool err_chk;
  41. static int geoid;
  42. static const char driver_name[] = "vme_tsi148";
  43. static DEFINE_PCI_DEVICE_TABLE(tsi148_ids) = {
  44. { PCI_DEVICE(PCI_VENDOR_ID_TUNDRA, PCI_DEVICE_ID_TUNDRA_TSI148) },
  45. { },
  46. };
  47. static struct pci_driver tsi148_driver = {
  48. .name = driver_name,
  49. .id_table = tsi148_ids,
  50. .probe = tsi148_probe,
  51. .remove = tsi148_remove,
  52. };
  53. static void reg_join(unsigned int high, unsigned int low,
  54. unsigned long long *variable)
  55. {
  56. *variable = (unsigned long long)high << 32;
  57. *variable |= (unsigned long long)low;
  58. }
  59. static void reg_split(unsigned long long variable, unsigned int *high,
  60. unsigned int *low)
  61. {
  62. *low = (unsigned int)variable & 0xFFFFFFFF;
  63. *high = (unsigned int)(variable >> 32);
  64. }
  65. /*
  66. * Wakes up DMA queue.
  67. */
  68. static u32 tsi148_DMA_irqhandler(struct tsi148_driver *bridge,
  69. int channel_mask)
  70. {
  71. u32 serviced = 0;
  72. if (channel_mask & TSI148_LCSR_INTS_DMA0S) {
  73. wake_up(&bridge->dma_queue[0]);
  74. serviced |= TSI148_LCSR_INTC_DMA0C;
  75. }
  76. if (channel_mask & TSI148_LCSR_INTS_DMA1S) {
  77. wake_up(&bridge->dma_queue[1]);
  78. serviced |= TSI148_LCSR_INTC_DMA1C;
  79. }
  80. return serviced;
  81. }
  82. /*
  83. * Wake up location monitor queue
  84. */
  85. static u32 tsi148_LM_irqhandler(struct tsi148_driver *bridge, u32 stat)
  86. {
  87. int i;
  88. u32 serviced = 0;
  89. for (i = 0; i < 4; i++) {
  90. if (stat & TSI148_LCSR_INTS_LMS[i]) {
  91. /* We only enable interrupts if the callback is set */
  92. bridge->lm_callback[i](i);
  93. serviced |= TSI148_LCSR_INTC_LMC[i];
  94. }
  95. }
  96. return serviced;
  97. }
  98. /*
  99. * Wake up mail box queue.
  100. *
  101. * XXX This functionality is not exposed up though API.
  102. */
  103. static u32 tsi148_MB_irqhandler(struct vme_bridge *tsi148_bridge, u32 stat)
  104. {
  105. int i;
  106. u32 val;
  107. u32 serviced = 0;
  108. struct tsi148_driver *bridge;
  109. bridge = tsi148_bridge->driver_priv;
  110. for (i = 0; i < 4; i++) {
  111. if (stat & TSI148_LCSR_INTS_MBS[i]) {
  112. val = ioread32be(bridge->base + TSI148_GCSR_MBOX[i]);
  113. dev_err(tsi148_bridge->parent, "VME Mailbox %d received"
  114. ": 0x%x\n", i, val);
  115. serviced |= TSI148_LCSR_INTC_MBC[i];
  116. }
  117. }
  118. return serviced;
  119. }
  120. /*
  121. * Display error & status message when PERR (PCI) exception interrupt occurs.
  122. */
  123. static u32 tsi148_PERR_irqhandler(struct vme_bridge *tsi148_bridge)
  124. {
  125. struct tsi148_driver *bridge;
  126. bridge = tsi148_bridge->driver_priv;
  127. dev_err(tsi148_bridge->parent, "PCI Exception at address: 0x%08x:%08x, "
  128. "attributes: %08x\n",
  129. ioread32be(bridge->base + TSI148_LCSR_EDPAU),
  130. ioread32be(bridge->base + TSI148_LCSR_EDPAL),
  131. ioread32be(bridge->base + TSI148_LCSR_EDPAT));
  132. dev_err(tsi148_bridge->parent, "PCI-X attribute reg: %08x, PCI-X split "
  133. "completion reg: %08x\n",
  134. ioread32be(bridge->base + TSI148_LCSR_EDPXA),
  135. ioread32be(bridge->base + TSI148_LCSR_EDPXS));
  136. iowrite32be(TSI148_LCSR_EDPAT_EDPCL, bridge->base + TSI148_LCSR_EDPAT);
  137. return TSI148_LCSR_INTC_PERRC;
  138. }
  139. /*
  140. * Save address and status when VME error interrupt occurs.
  141. */
  142. static u32 tsi148_VERR_irqhandler(struct vme_bridge *tsi148_bridge)
  143. {
  144. unsigned int error_addr_high, error_addr_low;
  145. unsigned long long error_addr;
  146. u32 error_attrib;
  147. struct vme_bus_error *error;
  148. struct tsi148_driver *bridge;
  149. bridge = tsi148_bridge->driver_priv;
  150. error_addr_high = ioread32be(bridge->base + TSI148_LCSR_VEAU);
  151. error_addr_low = ioread32be(bridge->base + TSI148_LCSR_VEAL);
  152. error_attrib = ioread32be(bridge->base + TSI148_LCSR_VEAT);
  153. reg_join(error_addr_high, error_addr_low, &error_addr);
  154. /* Check for exception register overflow (we have lost error data) */
  155. if (error_attrib & TSI148_LCSR_VEAT_VEOF) {
  156. dev_err(tsi148_bridge->parent, "VME Bus Exception Overflow "
  157. "Occurred\n");
  158. }
  159. error = kmalloc(sizeof(struct vme_bus_error), GFP_ATOMIC);
  160. if (error) {
  161. error->address = error_addr;
  162. error->attributes = error_attrib;
  163. list_add_tail(&error->list, &tsi148_bridge->vme_errors);
  164. } else {
  165. dev_err(tsi148_bridge->parent, "Unable to alloc memory for "
  166. "VMEbus Error reporting\n");
  167. dev_err(tsi148_bridge->parent, "VME Bus Error at address: "
  168. "0x%llx, attributes: %08x\n", error_addr, error_attrib);
  169. }
  170. /* Clear Status */
  171. iowrite32be(TSI148_LCSR_VEAT_VESCL, bridge->base + TSI148_LCSR_VEAT);
  172. return TSI148_LCSR_INTC_VERRC;
  173. }
  174. /*
  175. * Wake up IACK queue.
  176. */
  177. static u32 tsi148_IACK_irqhandler(struct tsi148_driver *bridge)
  178. {
  179. wake_up(&bridge->iack_queue);
  180. return TSI148_LCSR_INTC_IACKC;
  181. }
  182. /*
  183. * Calling VME bus interrupt callback if provided.
  184. */
  185. static u32 tsi148_VIRQ_irqhandler(struct vme_bridge *tsi148_bridge,
  186. u32 stat)
  187. {
  188. int vec, i, serviced = 0;
  189. struct tsi148_driver *bridge;
  190. bridge = tsi148_bridge->driver_priv;
  191. for (i = 7; i > 0; i--) {
  192. if (stat & (1 << i)) {
  193. /*
  194. * Note: Even though the registers are defined as
  195. * 32-bits in the spec, we only want to issue 8-bit
  196. * IACK cycles on the bus, read from offset 3.
  197. */
  198. vec = ioread8(bridge->base + TSI148_LCSR_VIACK[i] + 3);
  199. vme_irq_handler(tsi148_bridge, i, vec);
  200. serviced |= (1 << i);
  201. }
  202. }
  203. return serviced;
  204. }
  205. /*
  206. * Top level interrupt handler. Clears appropriate interrupt status bits and
  207. * then calls appropriate sub handler(s).
  208. */
  209. static irqreturn_t tsi148_irqhandler(int irq, void *ptr)
  210. {
  211. u32 stat, enable, serviced = 0;
  212. struct vme_bridge *tsi148_bridge;
  213. struct tsi148_driver *bridge;
  214. tsi148_bridge = ptr;
  215. bridge = tsi148_bridge->driver_priv;
  216. /* Determine which interrupts are unmasked and set */
  217. enable = ioread32be(bridge->base + TSI148_LCSR_INTEO);
  218. stat = ioread32be(bridge->base + TSI148_LCSR_INTS);
  219. /* Only look at unmasked interrupts */
  220. stat &= enable;
  221. if (unlikely(!stat))
  222. return IRQ_NONE;
  223. /* Call subhandlers as appropriate */
  224. /* DMA irqs */
  225. if (stat & (TSI148_LCSR_INTS_DMA1S | TSI148_LCSR_INTS_DMA0S))
  226. serviced |= tsi148_DMA_irqhandler(bridge, stat);
  227. /* Location monitor irqs */
  228. if (stat & (TSI148_LCSR_INTS_LM3S | TSI148_LCSR_INTS_LM2S |
  229. TSI148_LCSR_INTS_LM1S | TSI148_LCSR_INTS_LM0S))
  230. serviced |= tsi148_LM_irqhandler(bridge, stat);
  231. /* Mail box irqs */
  232. if (stat & (TSI148_LCSR_INTS_MB3S | TSI148_LCSR_INTS_MB2S |
  233. TSI148_LCSR_INTS_MB1S | TSI148_LCSR_INTS_MB0S))
  234. serviced |= tsi148_MB_irqhandler(tsi148_bridge, stat);
  235. /* PCI bus error */
  236. if (stat & TSI148_LCSR_INTS_PERRS)
  237. serviced |= tsi148_PERR_irqhandler(tsi148_bridge);
  238. /* VME bus error */
  239. if (stat & TSI148_LCSR_INTS_VERRS)
  240. serviced |= tsi148_VERR_irqhandler(tsi148_bridge);
  241. /* IACK irq */
  242. if (stat & TSI148_LCSR_INTS_IACKS)
  243. serviced |= tsi148_IACK_irqhandler(bridge);
  244. /* VME bus irqs */
  245. if (stat & (TSI148_LCSR_INTS_IRQ7S | TSI148_LCSR_INTS_IRQ6S |
  246. TSI148_LCSR_INTS_IRQ5S | TSI148_LCSR_INTS_IRQ4S |
  247. TSI148_LCSR_INTS_IRQ3S | TSI148_LCSR_INTS_IRQ2S |
  248. TSI148_LCSR_INTS_IRQ1S))
  249. serviced |= tsi148_VIRQ_irqhandler(tsi148_bridge, stat);
  250. /* Clear serviced interrupts */
  251. iowrite32be(serviced, bridge->base + TSI148_LCSR_INTC);
  252. return IRQ_HANDLED;
  253. }
  254. static int tsi148_irq_init(struct vme_bridge *tsi148_bridge)
  255. {
  256. int result;
  257. unsigned int tmp;
  258. struct pci_dev *pdev;
  259. struct tsi148_driver *bridge;
  260. pdev = container_of(tsi148_bridge->parent, struct pci_dev, dev);
  261. bridge = tsi148_bridge->driver_priv;
  262. /* Initialise list for VME bus errors */
  263. INIT_LIST_HEAD(&tsi148_bridge->vme_errors);
  264. mutex_init(&tsi148_bridge->irq_mtx);
  265. result = request_irq(pdev->irq,
  266. tsi148_irqhandler,
  267. IRQF_SHARED,
  268. driver_name, tsi148_bridge);
  269. if (result) {
  270. dev_err(tsi148_bridge->parent, "Can't get assigned pci irq "
  271. "vector %02X\n", pdev->irq);
  272. return result;
  273. }
  274. /* Enable and unmask interrupts */
  275. tmp = TSI148_LCSR_INTEO_DMA1EO | TSI148_LCSR_INTEO_DMA0EO |
  276. TSI148_LCSR_INTEO_MB3EO | TSI148_LCSR_INTEO_MB2EO |
  277. TSI148_LCSR_INTEO_MB1EO | TSI148_LCSR_INTEO_MB0EO |
  278. TSI148_LCSR_INTEO_PERREO | TSI148_LCSR_INTEO_VERREO |
  279. TSI148_LCSR_INTEO_IACKEO;
  280. /* This leaves the following interrupts masked.
  281. * TSI148_LCSR_INTEO_VIEEO
  282. * TSI148_LCSR_INTEO_SYSFLEO
  283. * TSI148_LCSR_INTEO_ACFLEO
  284. */
  285. /* Don't enable Location Monitor interrupts here - they will be
  286. * enabled when the location monitors are properly configured and
  287. * a callback has been attached.
  288. * TSI148_LCSR_INTEO_LM0EO
  289. * TSI148_LCSR_INTEO_LM1EO
  290. * TSI148_LCSR_INTEO_LM2EO
  291. * TSI148_LCSR_INTEO_LM3EO
  292. */
  293. /* Don't enable VME interrupts until we add a handler, else the board
  294. * will respond to it and we don't want that unless it knows how to
  295. * properly deal with it.
  296. * TSI148_LCSR_INTEO_IRQ7EO
  297. * TSI148_LCSR_INTEO_IRQ6EO
  298. * TSI148_LCSR_INTEO_IRQ5EO
  299. * TSI148_LCSR_INTEO_IRQ4EO
  300. * TSI148_LCSR_INTEO_IRQ3EO
  301. * TSI148_LCSR_INTEO_IRQ2EO
  302. * TSI148_LCSR_INTEO_IRQ1EO
  303. */
  304. iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO);
  305. iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN);
  306. return 0;
  307. }
  308. static void tsi148_irq_exit(struct vme_bridge *tsi148_bridge,
  309. struct pci_dev *pdev)
  310. {
  311. struct tsi148_driver *bridge = tsi148_bridge->driver_priv;
  312. /* Turn off interrupts */
  313. iowrite32be(0x0, bridge->base + TSI148_LCSR_INTEO);
  314. iowrite32be(0x0, bridge->base + TSI148_LCSR_INTEN);
  315. /* Clear all interrupts */
  316. iowrite32be(0xFFFFFFFF, bridge->base + TSI148_LCSR_INTC);
  317. /* Detach interrupt handler */
  318. free_irq(pdev->irq, tsi148_bridge);
  319. }
  320. /*
  321. * Check to see if an IACk has been received, return true (1) or false (0).
  322. */
  323. static int tsi148_iack_received(struct tsi148_driver *bridge)
  324. {
  325. u32 tmp;
  326. tmp = ioread32be(bridge->base + TSI148_LCSR_VICR);
  327. if (tmp & TSI148_LCSR_VICR_IRQS)
  328. return 0;
  329. else
  330. return 1;
  331. }
  332. /*
  333. * Configure VME interrupt
  334. */
  335. static void tsi148_irq_set(struct vme_bridge *tsi148_bridge, int level,
  336. int state, int sync)
  337. {
  338. struct pci_dev *pdev;
  339. u32 tmp;
  340. struct tsi148_driver *bridge;
  341. bridge = tsi148_bridge->driver_priv;
  342. /* We need to do the ordering differently for enabling and disabling */
  343. if (state == 0) {
  344. tmp = ioread32be(bridge->base + TSI148_LCSR_INTEN);
  345. tmp &= ~TSI148_LCSR_INTEN_IRQEN[level - 1];
  346. iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN);
  347. tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO);
  348. tmp &= ~TSI148_LCSR_INTEO_IRQEO[level - 1];
  349. iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO);
  350. if (sync != 0) {
  351. pdev = container_of(tsi148_bridge->parent,
  352. struct pci_dev, dev);
  353. synchronize_irq(pdev->irq);
  354. }
  355. } else {
  356. tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO);
  357. tmp |= TSI148_LCSR_INTEO_IRQEO[level - 1];
  358. iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO);
  359. tmp = ioread32be(bridge->base + TSI148_LCSR_INTEN);
  360. tmp |= TSI148_LCSR_INTEN_IRQEN[level - 1];
  361. iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN);
  362. }
  363. }
  364. /*
  365. * Generate a VME bus interrupt at the requested level & vector. Wait for
  366. * interrupt to be acked.
  367. */
  368. static int tsi148_irq_generate(struct vme_bridge *tsi148_bridge, int level,
  369. int statid)
  370. {
  371. u32 tmp;
  372. struct tsi148_driver *bridge;
  373. bridge = tsi148_bridge->driver_priv;
  374. mutex_lock(&bridge->vme_int);
  375. /* Read VICR register */
  376. tmp = ioread32be(bridge->base + TSI148_LCSR_VICR);
  377. /* Set Status/ID */
  378. tmp = (tmp & ~TSI148_LCSR_VICR_STID_M) |
  379. (statid & TSI148_LCSR_VICR_STID_M);
  380. iowrite32be(tmp, bridge->base + TSI148_LCSR_VICR);
  381. /* Assert VMEbus IRQ */
  382. tmp = tmp | TSI148_LCSR_VICR_IRQL[level];
  383. iowrite32be(tmp, bridge->base + TSI148_LCSR_VICR);
  384. /* XXX Consider implementing a timeout? */
  385. wait_event_interruptible(bridge->iack_queue,
  386. tsi148_iack_received(bridge));
  387. mutex_unlock(&bridge->vme_int);
  388. return 0;
  389. }
  390. /*
  391. * Find the first error in this address range
  392. */
  393. static struct vme_bus_error *tsi148_find_error(struct vme_bridge *tsi148_bridge,
  394. u32 aspace, unsigned long long address, size_t count)
  395. {
  396. struct list_head *err_pos;
  397. struct vme_bus_error *vme_err, *valid = NULL;
  398. unsigned long long bound;
  399. bound = address + count;
  400. /*
  401. * XXX We are currently not looking at the address space when parsing
  402. * for errors. This is because parsing the Address Modifier Codes
  403. * is going to be quite resource intensive to do properly. We
  404. * should be OK just looking at the addresses and this is certainly
  405. * much better than what we had before.
  406. */
  407. err_pos = NULL;
  408. /* Iterate through errors */
  409. list_for_each(err_pos, &tsi148_bridge->vme_errors) {
  410. vme_err = list_entry(err_pos, struct vme_bus_error, list);
  411. if ((vme_err->address >= address) &&
  412. (vme_err->address < bound)) {
  413. valid = vme_err;
  414. break;
  415. }
  416. }
  417. return valid;
  418. }
  419. /*
  420. * Clear errors in the provided address range.
  421. */
  422. static void tsi148_clear_errors(struct vme_bridge *tsi148_bridge,
  423. u32 aspace, unsigned long long address, size_t count)
  424. {
  425. struct list_head *err_pos, *temp;
  426. struct vme_bus_error *vme_err;
  427. unsigned long long bound;
  428. bound = address + count;
  429. /*
  430. * XXX We are currently not looking at the address space when parsing
  431. * for errors. This is because parsing the Address Modifier Codes
  432. * is going to be quite resource intensive to do properly. We
  433. * should be OK just looking at the addresses and this is certainly
  434. * much better than what we had before.
  435. */
  436. err_pos = NULL;
  437. /* Iterate through errors */
  438. list_for_each_safe(err_pos, temp, &tsi148_bridge->vme_errors) {
  439. vme_err = list_entry(err_pos, struct vme_bus_error, list);
  440. if ((vme_err->address >= address) &&
  441. (vme_err->address < bound)) {
  442. list_del(err_pos);
  443. kfree(vme_err);
  444. }
  445. }
  446. }
  447. /*
  448. * Initialize a slave window with the requested attributes.
  449. */
  450. static int tsi148_slave_set(struct vme_slave_resource *image, int enabled,
  451. unsigned long long vme_base, unsigned long long size,
  452. dma_addr_t pci_base, u32 aspace, u32 cycle)
  453. {
  454. unsigned int i, addr = 0, granularity = 0;
  455. unsigned int temp_ctl = 0;
  456. unsigned int vme_base_low, vme_base_high;
  457. unsigned int vme_bound_low, vme_bound_high;
  458. unsigned int pci_offset_low, pci_offset_high;
  459. unsigned long long vme_bound, pci_offset;
  460. struct vme_bridge *tsi148_bridge;
  461. struct tsi148_driver *bridge;
  462. tsi148_bridge = image->parent;
  463. bridge = tsi148_bridge->driver_priv;
  464. i = image->number;
  465. switch (aspace) {
  466. case VME_A16:
  467. granularity = 0x10;
  468. addr |= TSI148_LCSR_ITAT_AS_A16;
  469. break;
  470. case VME_A24:
  471. granularity = 0x1000;
  472. addr |= TSI148_LCSR_ITAT_AS_A24;
  473. break;
  474. case VME_A32:
  475. granularity = 0x10000;
  476. addr |= TSI148_LCSR_ITAT_AS_A32;
  477. break;
  478. case VME_A64:
  479. granularity = 0x10000;
  480. addr |= TSI148_LCSR_ITAT_AS_A64;
  481. break;
  482. case VME_CRCSR:
  483. case VME_USER1:
  484. case VME_USER2:
  485. case VME_USER3:
  486. case VME_USER4:
  487. default:
  488. dev_err(tsi148_bridge->parent, "Invalid address space\n");
  489. return -EINVAL;
  490. break;
  491. }
  492. /* Convert 64-bit variables to 2x 32-bit variables */
  493. reg_split(vme_base, &vme_base_high, &vme_base_low);
  494. /*
  495. * Bound address is a valid address for the window, adjust
  496. * accordingly
  497. */
  498. vme_bound = vme_base + size - granularity;
  499. reg_split(vme_bound, &vme_bound_high, &vme_bound_low);
  500. pci_offset = (unsigned long long)pci_base - vme_base;
  501. reg_split(pci_offset, &pci_offset_high, &pci_offset_low);
  502. if (vme_base_low & (granularity - 1)) {
  503. dev_err(tsi148_bridge->parent, "Invalid VME base alignment\n");
  504. return -EINVAL;
  505. }
  506. if (vme_bound_low & (granularity - 1)) {
  507. dev_err(tsi148_bridge->parent, "Invalid VME bound alignment\n");
  508. return -EINVAL;
  509. }
  510. if (pci_offset_low & (granularity - 1)) {
  511. dev_err(tsi148_bridge->parent, "Invalid PCI Offset "
  512. "alignment\n");
  513. return -EINVAL;
  514. }
  515. /* Disable while we are mucking around */
  516. temp_ctl = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
  517. TSI148_LCSR_OFFSET_ITAT);
  518. temp_ctl &= ~TSI148_LCSR_ITAT_EN;
  519. iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_IT[i] +
  520. TSI148_LCSR_OFFSET_ITAT);
  521. /* Setup mapping */
  522. iowrite32be(vme_base_high, bridge->base + TSI148_LCSR_IT[i] +
  523. TSI148_LCSR_OFFSET_ITSAU);
  524. iowrite32be(vme_base_low, bridge->base + TSI148_LCSR_IT[i] +
  525. TSI148_LCSR_OFFSET_ITSAL);
  526. iowrite32be(vme_bound_high, bridge->base + TSI148_LCSR_IT[i] +
  527. TSI148_LCSR_OFFSET_ITEAU);
  528. iowrite32be(vme_bound_low, bridge->base + TSI148_LCSR_IT[i] +
  529. TSI148_LCSR_OFFSET_ITEAL);
  530. iowrite32be(pci_offset_high, bridge->base + TSI148_LCSR_IT[i] +
  531. TSI148_LCSR_OFFSET_ITOFU);
  532. iowrite32be(pci_offset_low, bridge->base + TSI148_LCSR_IT[i] +
  533. TSI148_LCSR_OFFSET_ITOFL);
  534. /* Setup 2eSST speeds */
  535. temp_ctl &= ~TSI148_LCSR_ITAT_2eSSTM_M;
  536. switch (cycle & (VME_2eSST160 | VME_2eSST267 | VME_2eSST320)) {
  537. case VME_2eSST160:
  538. temp_ctl |= TSI148_LCSR_ITAT_2eSSTM_160;
  539. break;
  540. case VME_2eSST267:
  541. temp_ctl |= TSI148_LCSR_ITAT_2eSSTM_267;
  542. break;
  543. case VME_2eSST320:
  544. temp_ctl |= TSI148_LCSR_ITAT_2eSSTM_320;
  545. break;
  546. }
  547. /* Setup cycle types */
  548. temp_ctl &= ~(0x1F << 7);
  549. if (cycle & VME_BLT)
  550. temp_ctl |= TSI148_LCSR_ITAT_BLT;
  551. if (cycle & VME_MBLT)
  552. temp_ctl |= TSI148_LCSR_ITAT_MBLT;
  553. if (cycle & VME_2eVME)
  554. temp_ctl |= TSI148_LCSR_ITAT_2eVME;
  555. if (cycle & VME_2eSST)
  556. temp_ctl |= TSI148_LCSR_ITAT_2eSST;
  557. if (cycle & VME_2eSSTB)
  558. temp_ctl |= TSI148_LCSR_ITAT_2eSSTB;
  559. /* Setup address space */
  560. temp_ctl &= ~TSI148_LCSR_ITAT_AS_M;
  561. temp_ctl |= addr;
  562. temp_ctl &= ~0xF;
  563. if (cycle & VME_SUPER)
  564. temp_ctl |= TSI148_LCSR_ITAT_SUPR ;
  565. if (cycle & VME_USER)
  566. temp_ctl |= TSI148_LCSR_ITAT_NPRIV;
  567. if (cycle & VME_PROG)
  568. temp_ctl |= TSI148_LCSR_ITAT_PGM;
  569. if (cycle & VME_DATA)
  570. temp_ctl |= TSI148_LCSR_ITAT_DATA;
  571. /* Write ctl reg without enable */
  572. iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_IT[i] +
  573. TSI148_LCSR_OFFSET_ITAT);
  574. if (enabled)
  575. temp_ctl |= TSI148_LCSR_ITAT_EN;
  576. iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_IT[i] +
  577. TSI148_LCSR_OFFSET_ITAT);
  578. return 0;
  579. }
  580. /*
  581. * Get slave window configuration.
  582. */
  583. static int tsi148_slave_get(struct vme_slave_resource *image, int *enabled,
  584. unsigned long long *vme_base, unsigned long long *size,
  585. dma_addr_t *pci_base, u32 *aspace, u32 *cycle)
  586. {
  587. unsigned int i, granularity = 0, ctl = 0;
  588. unsigned int vme_base_low, vme_base_high;
  589. unsigned int vme_bound_low, vme_bound_high;
  590. unsigned int pci_offset_low, pci_offset_high;
  591. unsigned long long vme_bound, pci_offset;
  592. struct tsi148_driver *bridge;
  593. bridge = image->parent->driver_priv;
  594. i = image->number;
  595. /* Read registers */
  596. ctl = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
  597. TSI148_LCSR_OFFSET_ITAT);
  598. vme_base_high = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
  599. TSI148_LCSR_OFFSET_ITSAU);
  600. vme_base_low = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
  601. TSI148_LCSR_OFFSET_ITSAL);
  602. vme_bound_high = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
  603. TSI148_LCSR_OFFSET_ITEAU);
  604. vme_bound_low = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
  605. TSI148_LCSR_OFFSET_ITEAL);
  606. pci_offset_high = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
  607. TSI148_LCSR_OFFSET_ITOFU);
  608. pci_offset_low = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
  609. TSI148_LCSR_OFFSET_ITOFL);
  610. /* Convert 64-bit variables to 2x 32-bit variables */
  611. reg_join(vme_base_high, vme_base_low, vme_base);
  612. reg_join(vme_bound_high, vme_bound_low, &vme_bound);
  613. reg_join(pci_offset_high, pci_offset_low, &pci_offset);
  614. *pci_base = (dma_addr_t)vme_base + pci_offset;
  615. *enabled = 0;
  616. *aspace = 0;
  617. *cycle = 0;
  618. if (ctl & TSI148_LCSR_ITAT_EN)
  619. *enabled = 1;
  620. if ((ctl & TSI148_LCSR_ITAT_AS_M) == TSI148_LCSR_ITAT_AS_A16) {
  621. granularity = 0x10;
  622. *aspace |= VME_A16;
  623. }
  624. if ((ctl & TSI148_LCSR_ITAT_AS_M) == TSI148_LCSR_ITAT_AS_A24) {
  625. granularity = 0x1000;
  626. *aspace |= VME_A24;
  627. }
  628. if ((ctl & TSI148_LCSR_ITAT_AS_M) == TSI148_LCSR_ITAT_AS_A32) {
  629. granularity = 0x10000;
  630. *aspace |= VME_A32;
  631. }
  632. if ((ctl & TSI148_LCSR_ITAT_AS_M) == TSI148_LCSR_ITAT_AS_A64) {
  633. granularity = 0x10000;
  634. *aspace |= VME_A64;
  635. }
  636. /* Need granularity before we set the size */
  637. *size = (unsigned long long)((vme_bound - *vme_base) + granularity);
  638. if ((ctl & TSI148_LCSR_ITAT_2eSSTM_M) == TSI148_LCSR_ITAT_2eSSTM_160)
  639. *cycle |= VME_2eSST160;
  640. if ((ctl & TSI148_LCSR_ITAT_2eSSTM_M) == TSI148_LCSR_ITAT_2eSSTM_267)
  641. *cycle |= VME_2eSST267;
  642. if ((ctl & TSI148_LCSR_ITAT_2eSSTM_M) == TSI148_LCSR_ITAT_2eSSTM_320)
  643. *cycle |= VME_2eSST320;
  644. if (ctl & TSI148_LCSR_ITAT_BLT)
  645. *cycle |= VME_BLT;
  646. if (ctl & TSI148_LCSR_ITAT_MBLT)
  647. *cycle |= VME_MBLT;
  648. if (ctl & TSI148_LCSR_ITAT_2eVME)
  649. *cycle |= VME_2eVME;
  650. if (ctl & TSI148_LCSR_ITAT_2eSST)
  651. *cycle |= VME_2eSST;
  652. if (ctl & TSI148_LCSR_ITAT_2eSSTB)
  653. *cycle |= VME_2eSSTB;
  654. if (ctl & TSI148_LCSR_ITAT_SUPR)
  655. *cycle |= VME_SUPER;
  656. if (ctl & TSI148_LCSR_ITAT_NPRIV)
  657. *cycle |= VME_USER;
  658. if (ctl & TSI148_LCSR_ITAT_PGM)
  659. *cycle |= VME_PROG;
  660. if (ctl & TSI148_LCSR_ITAT_DATA)
  661. *cycle |= VME_DATA;
  662. return 0;
  663. }
  664. /*
  665. * Allocate and map PCI Resource
  666. */
  667. static int tsi148_alloc_resource(struct vme_master_resource *image,
  668. unsigned long long size)
  669. {
  670. unsigned long long existing_size;
  671. int retval = 0;
  672. struct pci_dev *pdev;
  673. struct vme_bridge *tsi148_bridge;
  674. tsi148_bridge = image->parent;
  675. pdev = container_of(tsi148_bridge->parent, struct pci_dev, dev);
  676. existing_size = (unsigned long long)(image->bus_resource.end -
  677. image->bus_resource.start);
  678. /* If the existing size is OK, return */
  679. if ((size != 0) && (existing_size == (size - 1)))
  680. return 0;
  681. if (existing_size != 0) {
  682. iounmap(image->kern_base);
  683. image->kern_base = NULL;
  684. kfree(image->bus_resource.name);
  685. release_resource(&image->bus_resource);
  686. memset(&image->bus_resource, 0, sizeof(struct resource));
  687. }
  688. /* Exit here if size is zero */
  689. if (size == 0)
  690. return 0;
  691. if (image->bus_resource.name == NULL) {
  692. image->bus_resource.name = kmalloc(VMENAMSIZ+3, GFP_ATOMIC);
  693. if (image->bus_resource.name == NULL) {
  694. dev_err(tsi148_bridge->parent, "Unable to allocate "
  695. "memory for resource name\n");
  696. retval = -ENOMEM;
  697. goto err_name;
  698. }
  699. }
  700. sprintf((char *)image->bus_resource.name, "%s.%d", tsi148_bridge->name,
  701. image->number);
  702. image->bus_resource.start = 0;
  703. image->bus_resource.end = (unsigned long)size;
  704. image->bus_resource.flags = IORESOURCE_MEM;
  705. retval = pci_bus_alloc_resource(pdev->bus,
  706. &image->bus_resource, size, size, PCIBIOS_MIN_MEM,
  707. 0, NULL, NULL);
  708. if (retval) {
  709. dev_err(tsi148_bridge->parent, "Failed to allocate mem "
  710. "resource for window %d size 0x%lx start 0x%lx\n",
  711. image->number, (unsigned long)size,
  712. (unsigned long)image->bus_resource.start);
  713. goto err_resource;
  714. }
  715. image->kern_base = ioremap_nocache(
  716. image->bus_resource.start, size);
  717. if (image->kern_base == NULL) {
  718. dev_err(tsi148_bridge->parent, "Failed to remap resource\n");
  719. retval = -ENOMEM;
  720. goto err_remap;
  721. }
  722. return 0;
  723. err_remap:
  724. release_resource(&image->bus_resource);
  725. err_resource:
  726. kfree(image->bus_resource.name);
  727. memset(&image->bus_resource, 0, sizeof(struct resource));
  728. err_name:
  729. return retval;
  730. }
  731. /*
  732. * Free and unmap PCI Resource
  733. */
  734. static void tsi148_free_resource(struct vme_master_resource *image)
  735. {
  736. iounmap(image->kern_base);
  737. image->kern_base = NULL;
  738. release_resource(&image->bus_resource);
  739. kfree(image->bus_resource.name);
  740. memset(&image->bus_resource, 0, sizeof(struct resource));
  741. }
  742. /*
  743. * Set the attributes of an outbound window.
  744. */
  745. static int tsi148_master_set(struct vme_master_resource *image, int enabled,
  746. unsigned long long vme_base, unsigned long long size, u32 aspace,
  747. u32 cycle, u32 dwidth)
  748. {
  749. int retval = 0;
  750. unsigned int i;
  751. unsigned int temp_ctl = 0;
  752. unsigned int pci_base_low, pci_base_high;
  753. unsigned int pci_bound_low, pci_bound_high;
  754. unsigned int vme_offset_low, vme_offset_high;
  755. unsigned long long pci_bound, vme_offset, pci_base;
  756. struct vme_bridge *tsi148_bridge;
  757. struct tsi148_driver *bridge;
  758. tsi148_bridge = image->parent;
  759. bridge = tsi148_bridge->driver_priv;
  760. /* Verify input data */
  761. if (vme_base & 0xFFFF) {
  762. dev_err(tsi148_bridge->parent, "Invalid VME Window "
  763. "alignment\n");
  764. retval = -EINVAL;
  765. goto err_window;
  766. }
  767. if ((size == 0) && (enabled != 0)) {
  768. dev_err(tsi148_bridge->parent, "Size must be non-zero for "
  769. "enabled windows\n");
  770. retval = -EINVAL;
  771. goto err_window;
  772. }
  773. spin_lock(&image->lock);
  774. /* Let's allocate the resource here rather than further up the stack as
  775. * it avoids pushing loads of bus dependent stuff up the stack. If size
  776. * is zero, any existing resource will be freed.
  777. */
  778. retval = tsi148_alloc_resource(image, size);
  779. if (retval) {
  780. spin_unlock(&image->lock);
  781. dev_err(tsi148_bridge->parent, "Unable to allocate memory for "
  782. "resource\n");
  783. goto err_res;
  784. }
  785. if (size == 0) {
  786. pci_base = 0;
  787. pci_bound = 0;
  788. vme_offset = 0;
  789. } else {
  790. pci_base = (unsigned long long)image->bus_resource.start;
  791. /*
  792. * Bound address is a valid address for the window, adjust
  793. * according to window granularity.
  794. */
  795. pci_bound = pci_base + (size - 0x10000);
  796. vme_offset = vme_base - pci_base;
  797. }
  798. /* Convert 64-bit variables to 2x 32-bit variables */
  799. reg_split(pci_base, &pci_base_high, &pci_base_low);
  800. reg_split(pci_bound, &pci_bound_high, &pci_bound_low);
  801. reg_split(vme_offset, &vme_offset_high, &vme_offset_low);
  802. if (pci_base_low & 0xFFFF) {
  803. spin_unlock(&image->lock);
  804. dev_err(tsi148_bridge->parent, "Invalid PCI base alignment\n");
  805. retval = -EINVAL;
  806. goto err_gran;
  807. }
  808. if (pci_bound_low & 0xFFFF) {
  809. spin_unlock(&image->lock);
  810. dev_err(tsi148_bridge->parent, "Invalid PCI bound alignment\n");
  811. retval = -EINVAL;
  812. goto err_gran;
  813. }
  814. if (vme_offset_low & 0xFFFF) {
  815. spin_unlock(&image->lock);
  816. dev_err(tsi148_bridge->parent, "Invalid VME Offset "
  817. "alignment\n");
  818. retval = -EINVAL;
  819. goto err_gran;
  820. }
  821. i = image->number;
  822. /* Disable while we are mucking around */
  823. temp_ctl = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
  824. TSI148_LCSR_OFFSET_OTAT);
  825. temp_ctl &= ~TSI148_LCSR_OTAT_EN;
  826. iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_OT[i] +
  827. TSI148_LCSR_OFFSET_OTAT);
  828. /* Setup 2eSST speeds */
  829. temp_ctl &= ~TSI148_LCSR_OTAT_2eSSTM_M;
  830. switch (cycle & (VME_2eSST160 | VME_2eSST267 | VME_2eSST320)) {
  831. case VME_2eSST160:
  832. temp_ctl |= TSI148_LCSR_OTAT_2eSSTM_160;
  833. break;
  834. case VME_2eSST267:
  835. temp_ctl |= TSI148_LCSR_OTAT_2eSSTM_267;
  836. break;
  837. case VME_2eSST320:
  838. temp_ctl |= TSI148_LCSR_OTAT_2eSSTM_320;
  839. break;
  840. }
  841. /* Setup cycle types */
  842. if (cycle & VME_BLT) {
  843. temp_ctl &= ~TSI148_LCSR_OTAT_TM_M;
  844. temp_ctl |= TSI148_LCSR_OTAT_TM_BLT;
  845. }
  846. if (cycle & VME_MBLT) {
  847. temp_ctl &= ~TSI148_LCSR_OTAT_TM_M;
  848. temp_ctl |= TSI148_LCSR_OTAT_TM_MBLT;
  849. }
  850. if (cycle & VME_2eVME) {
  851. temp_ctl &= ~TSI148_LCSR_OTAT_TM_M;
  852. temp_ctl |= TSI148_LCSR_OTAT_TM_2eVME;
  853. }
  854. if (cycle & VME_2eSST) {
  855. temp_ctl &= ~TSI148_LCSR_OTAT_TM_M;
  856. temp_ctl |= TSI148_LCSR_OTAT_TM_2eSST;
  857. }
  858. if (cycle & VME_2eSSTB) {
  859. dev_warn(tsi148_bridge->parent, "Currently not setting "
  860. "Broadcast Select Registers\n");
  861. temp_ctl &= ~TSI148_LCSR_OTAT_TM_M;
  862. temp_ctl |= TSI148_LCSR_OTAT_TM_2eSSTB;
  863. }
  864. /* Setup data width */
  865. temp_ctl &= ~TSI148_LCSR_OTAT_DBW_M;
  866. switch (dwidth) {
  867. case VME_D16:
  868. temp_ctl |= TSI148_LCSR_OTAT_DBW_16;
  869. break;
  870. case VME_D32:
  871. temp_ctl |= TSI148_LCSR_OTAT_DBW_32;
  872. break;
  873. default:
  874. spin_unlock(&image->lock);
  875. dev_err(tsi148_bridge->parent, "Invalid data width\n");
  876. retval = -EINVAL;
  877. goto err_dwidth;
  878. }
  879. /* Setup address space */
  880. temp_ctl &= ~TSI148_LCSR_OTAT_AMODE_M;
  881. switch (aspace) {
  882. case VME_A16:
  883. temp_ctl |= TSI148_LCSR_OTAT_AMODE_A16;
  884. break;
  885. case VME_A24:
  886. temp_ctl |= TSI148_LCSR_OTAT_AMODE_A24;
  887. break;
  888. case VME_A32:
  889. temp_ctl |= TSI148_LCSR_OTAT_AMODE_A32;
  890. break;
  891. case VME_A64:
  892. temp_ctl |= TSI148_LCSR_OTAT_AMODE_A64;
  893. break;
  894. case VME_CRCSR:
  895. temp_ctl |= TSI148_LCSR_OTAT_AMODE_CRCSR;
  896. break;
  897. case VME_USER1:
  898. temp_ctl |= TSI148_LCSR_OTAT_AMODE_USER1;
  899. break;
  900. case VME_USER2:
  901. temp_ctl |= TSI148_LCSR_OTAT_AMODE_USER2;
  902. break;
  903. case VME_USER3:
  904. temp_ctl |= TSI148_LCSR_OTAT_AMODE_USER3;
  905. break;
  906. case VME_USER4:
  907. temp_ctl |= TSI148_LCSR_OTAT_AMODE_USER4;
  908. break;
  909. default:
  910. spin_unlock(&image->lock);
  911. dev_err(tsi148_bridge->parent, "Invalid address space\n");
  912. retval = -EINVAL;
  913. goto err_aspace;
  914. break;
  915. }
  916. temp_ctl &= ~(3<<4);
  917. if (cycle & VME_SUPER)
  918. temp_ctl |= TSI148_LCSR_OTAT_SUP;
  919. if (cycle & VME_PROG)
  920. temp_ctl |= TSI148_LCSR_OTAT_PGM;
  921. /* Setup mapping */
  922. iowrite32be(pci_base_high, bridge->base + TSI148_LCSR_OT[i] +
  923. TSI148_LCSR_OFFSET_OTSAU);
  924. iowrite32be(pci_base_low, bridge->base + TSI148_LCSR_OT[i] +
  925. TSI148_LCSR_OFFSET_OTSAL);
  926. iowrite32be(pci_bound_high, bridge->base + TSI148_LCSR_OT[i] +
  927. TSI148_LCSR_OFFSET_OTEAU);
  928. iowrite32be(pci_bound_low, bridge->base + TSI148_LCSR_OT[i] +
  929. TSI148_LCSR_OFFSET_OTEAL);
  930. iowrite32be(vme_offset_high, bridge->base + TSI148_LCSR_OT[i] +
  931. TSI148_LCSR_OFFSET_OTOFU);
  932. iowrite32be(vme_offset_low, bridge->base + TSI148_LCSR_OT[i] +
  933. TSI148_LCSR_OFFSET_OTOFL);
  934. /* Write ctl reg without enable */
  935. iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_OT[i] +
  936. TSI148_LCSR_OFFSET_OTAT);
  937. if (enabled)
  938. temp_ctl |= TSI148_LCSR_OTAT_EN;
  939. iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_OT[i] +
  940. TSI148_LCSR_OFFSET_OTAT);
  941. spin_unlock(&image->lock);
  942. return 0;
  943. err_aspace:
  944. err_dwidth:
  945. err_gran:
  946. tsi148_free_resource(image);
  947. err_res:
  948. err_window:
  949. return retval;
  950. }
  951. /*
  952. * Set the attributes of an outbound window.
  953. *
  954. * XXX Not parsing prefetch information.
  955. */
  956. static int __tsi148_master_get(struct vme_master_resource *image, int *enabled,
  957. unsigned long long *vme_base, unsigned long long *size, u32 *aspace,
  958. u32 *cycle, u32 *dwidth)
  959. {
  960. unsigned int i, ctl;
  961. unsigned int pci_base_low, pci_base_high;
  962. unsigned int pci_bound_low, pci_bound_high;
  963. unsigned int vme_offset_low, vme_offset_high;
  964. unsigned long long pci_base, pci_bound, vme_offset;
  965. struct tsi148_driver *bridge;
  966. bridge = image->parent->driver_priv;
  967. i = image->number;
  968. ctl = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
  969. TSI148_LCSR_OFFSET_OTAT);
  970. pci_base_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
  971. TSI148_LCSR_OFFSET_OTSAU);
  972. pci_base_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
  973. TSI148_LCSR_OFFSET_OTSAL);
  974. pci_bound_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
  975. TSI148_LCSR_OFFSET_OTEAU);
  976. pci_bound_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
  977. TSI148_LCSR_OFFSET_OTEAL);
  978. vme_offset_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
  979. TSI148_LCSR_OFFSET_OTOFU);
  980. vme_offset_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
  981. TSI148_LCSR_OFFSET_OTOFL);
  982. /* Convert 64-bit variables to 2x 32-bit variables */
  983. reg_join(pci_base_high, pci_base_low, &pci_base);
  984. reg_join(pci_bound_high, pci_bound_low, &pci_bound);
  985. reg_join(vme_offset_high, vme_offset_low, &vme_offset);
  986. *vme_base = pci_base + vme_offset;
  987. *size = (unsigned long long)(pci_bound - pci_base) + 0x10000;
  988. *enabled = 0;
  989. *aspace = 0;
  990. *cycle = 0;
  991. *dwidth = 0;
  992. if (ctl & TSI148_LCSR_OTAT_EN)
  993. *enabled = 1;
  994. /* Setup address space */
  995. if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_A16)
  996. *aspace |= VME_A16;
  997. if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_A24)
  998. *aspace |= VME_A24;
  999. if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_A32)
  1000. *aspace |= VME_A32;
  1001. if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_A64)
  1002. *aspace |= VME_A64;
  1003. if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_CRCSR)
  1004. *aspace |= VME_CRCSR;
  1005. if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_USER1)
  1006. *aspace |= VME_USER1;
  1007. if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_USER2)
  1008. *aspace |= VME_USER2;
  1009. if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_USER3)
  1010. *aspace |= VME_USER3;
  1011. if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_USER4)
  1012. *aspace |= VME_USER4;
  1013. /* Setup 2eSST speeds */
  1014. if ((ctl & TSI148_LCSR_OTAT_2eSSTM_M) == TSI148_LCSR_OTAT_2eSSTM_160)
  1015. *cycle |= VME_2eSST160;
  1016. if ((ctl & TSI148_LCSR_OTAT_2eSSTM_M) == TSI148_LCSR_OTAT_2eSSTM_267)
  1017. *cycle |= VME_2eSST267;
  1018. if ((ctl & TSI148_LCSR_OTAT_2eSSTM_M) == TSI148_LCSR_OTAT_2eSSTM_320)
  1019. *cycle |= VME_2eSST320;
  1020. /* Setup cycle types */
  1021. if ((ctl & TSI148_LCSR_OTAT_TM_M) == TSI148_LCSR_OTAT_TM_SCT)
  1022. *cycle |= VME_SCT;
  1023. if ((ctl & TSI148_LCSR_OTAT_TM_M) == TSI148_LCSR_OTAT_TM_BLT)
  1024. *cycle |= VME_BLT;
  1025. if ((ctl & TSI148_LCSR_OTAT_TM_M) == TSI148_LCSR_OTAT_TM_MBLT)
  1026. *cycle |= VME_MBLT;
  1027. if ((ctl & TSI148_LCSR_OTAT_TM_M) == TSI148_LCSR_OTAT_TM_2eVME)
  1028. *cycle |= VME_2eVME;
  1029. if ((ctl & TSI148_LCSR_OTAT_TM_M) == TSI148_LCSR_OTAT_TM_2eSST)
  1030. *cycle |= VME_2eSST;
  1031. if ((ctl & TSI148_LCSR_OTAT_TM_M) == TSI148_LCSR_OTAT_TM_2eSSTB)
  1032. *cycle |= VME_2eSSTB;
  1033. if (ctl & TSI148_LCSR_OTAT_SUP)
  1034. *cycle |= VME_SUPER;
  1035. else
  1036. *cycle |= VME_USER;
  1037. if (ctl & TSI148_LCSR_OTAT_PGM)
  1038. *cycle |= VME_PROG;
  1039. else
  1040. *cycle |= VME_DATA;
  1041. /* Setup data width */
  1042. if ((ctl & TSI148_LCSR_OTAT_DBW_M) == TSI148_LCSR_OTAT_DBW_16)
  1043. *dwidth = VME_D16;
  1044. if ((ctl & TSI148_LCSR_OTAT_DBW_M) == TSI148_LCSR_OTAT_DBW_32)
  1045. *dwidth = VME_D32;
  1046. return 0;
  1047. }
  1048. static int tsi148_master_get(struct vme_master_resource *image, int *enabled,
  1049. unsigned long long *vme_base, unsigned long long *size, u32 *aspace,
  1050. u32 *cycle, u32 *dwidth)
  1051. {
  1052. int retval;
  1053. spin_lock(&image->lock);
  1054. retval = __tsi148_master_get(image, enabled, vme_base, size, aspace,
  1055. cycle, dwidth);
  1056. spin_unlock(&image->lock);
  1057. return retval;
  1058. }
  1059. static ssize_t tsi148_master_read(struct vme_master_resource *image, void *buf,
  1060. size_t count, loff_t offset)
  1061. {
  1062. int retval, enabled;
  1063. unsigned long long vme_base, size;
  1064. u32 aspace, cycle, dwidth;
  1065. struct vme_bus_error *vme_err = NULL;
  1066. struct vme_bridge *tsi148_bridge;
  1067. tsi148_bridge = image->parent;
  1068. spin_lock(&image->lock);
  1069. memcpy_fromio(buf, image->kern_base + offset, (unsigned int)count);
  1070. retval = count;
  1071. if (!err_chk)
  1072. goto skip_chk;
  1073. __tsi148_master_get(image, &enabled, &vme_base, &size, &aspace, &cycle,
  1074. &dwidth);
  1075. vme_err = tsi148_find_error(tsi148_bridge, aspace, vme_base + offset,
  1076. count);
  1077. if (vme_err != NULL) {
  1078. dev_err(image->parent->parent, "First VME read error detected "
  1079. "an at address 0x%llx\n", vme_err->address);
  1080. retval = vme_err->address - (vme_base + offset);
  1081. /* Clear down save errors in this address range */
  1082. tsi148_clear_errors(tsi148_bridge, aspace, vme_base + offset,
  1083. count);
  1084. }
  1085. skip_chk:
  1086. spin_unlock(&image->lock);
  1087. return retval;
  1088. }
  1089. static ssize_t tsi148_master_write(struct vme_master_resource *image, void *buf,
  1090. size_t count, loff_t offset)
  1091. {
  1092. int retval = 0, enabled;
  1093. unsigned long long vme_base, size;
  1094. u32 aspace, cycle, dwidth;
  1095. struct vme_bus_error *vme_err = NULL;
  1096. struct vme_bridge *tsi148_bridge;
  1097. struct tsi148_driver *bridge;
  1098. tsi148_bridge = image->parent;
  1099. bridge = tsi148_bridge->driver_priv;
  1100. spin_lock(&image->lock);
  1101. memcpy_toio(image->kern_base + offset, buf, (unsigned int)count);
  1102. retval = count;
  1103. /*
  1104. * Writes are posted. We need to do a read on the VME bus to flush out
  1105. * all of the writes before we check for errors. We can't guarantee
  1106. * that reading the data we have just written is safe. It is believed
  1107. * that there isn't any read, write re-ordering, so we can read any
  1108. * location in VME space, so lets read the Device ID from the tsi148's
  1109. * own registers as mapped into CR/CSR space.
  1110. *
  1111. * We check for saved errors in the written address range/space.
  1112. */
  1113. if (!err_chk)
  1114. goto skip_chk;
  1115. /*
  1116. * Get window info first, to maximise the time that the buffers may
  1117. * fluch on their own
  1118. */
  1119. __tsi148_master_get(image, &enabled, &vme_base, &size, &aspace, &cycle,
  1120. &dwidth);
  1121. ioread16(bridge->flush_image->kern_base + 0x7F000);
  1122. vme_err = tsi148_find_error(tsi148_bridge, aspace, vme_base + offset,
  1123. count);
  1124. if (vme_err != NULL) {
  1125. dev_warn(tsi148_bridge->parent, "First VME write error detected"
  1126. " an at address 0x%llx\n", vme_err->address);
  1127. retval = vme_err->address - (vme_base + offset);
  1128. /* Clear down save errors in this address range */
  1129. tsi148_clear_errors(tsi148_bridge, aspace, vme_base + offset,
  1130. count);
  1131. }
  1132. skip_chk:
  1133. spin_unlock(&image->lock);
  1134. return retval;
  1135. }
  1136. /*
  1137. * Perform an RMW cycle on the VME bus.
  1138. *
  1139. * Requires a previously configured master window, returns final value.
  1140. */
  1141. static unsigned int tsi148_master_rmw(struct vme_master_resource *image,
  1142. unsigned int mask, unsigned int compare, unsigned int swap,
  1143. loff_t offset)
  1144. {
  1145. unsigned long long pci_addr;
  1146. unsigned int pci_addr_high, pci_addr_low;
  1147. u32 tmp, result;
  1148. int i;
  1149. struct tsi148_driver *bridge;
  1150. bridge = image->parent->driver_priv;
  1151. /* Find the PCI address that maps to the desired VME address */
  1152. i = image->number;
  1153. /* Locking as we can only do one of these at a time */
  1154. mutex_lock(&bridge->vme_rmw);
  1155. /* Lock image */
  1156. spin_lock(&image->lock);
  1157. pci_addr_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
  1158. TSI148_LCSR_OFFSET_OTSAU);
  1159. pci_addr_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
  1160. TSI148_LCSR_OFFSET_OTSAL);
  1161. reg_join(pci_addr_high, pci_addr_low, &pci_addr);
  1162. reg_split(pci_addr + offset, &pci_addr_high, &pci_addr_low);
  1163. /* Configure registers */
  1164. iowrite32be(mask, bridge->base + TSI148_LCSR_RMWEN);
  1165. iowrite32be(compare, bridge->base + TSI148_LCSR_RMWC);
  1166. iowrite32be(swap, bridge->base + TSI148_LCSR_RMWS);
  1167. iowrite32be(pci_addr_high, bridge->base + TSI148_LCSR_RMWAU);
  1168. iowrite32be(pci_addr_low, bridge->base + TSI148_LCSR_RMWAL);
  1169. /* Enable RMW */
  1170. tmp = ioread32be(bridge->base + TSI148_LCSR_VMCTRL);
  1171. tmp |= TSI148_LCSR_VMCTRL_RMWEN;
  1172. iowrite32be(tmp, bridge->base + TSI148_LCSR_VMCTRL);
  1173. /* Kick process off with a read to the required address. */
  1174. result = ioread32be(image->kern_base + offset);
  1175. /* Disable RMW */
  1176. tmp = ioread32be(bridge->base + TSI148_LCSR_VMCTRL);
  1177. tmp &= ~TSI148_LCSR_VMCTRL_RMWEN;
  1178. iowrite32be(tmp, bridge->base + TSI148_LCSR_VMCTRL);
  1179. spin_unlock(&image->lock);
  1180. mutex_unlock(&bridge->vme_rmw);
  1181. return result;
  1182. }
  1183. static int tsi148_dma_set_vme_src_attributes(struct device *dev, __be32 *attr,
  1184. u32 aspace, u32 cycle, u32 dwidth)
  1185. {
  1186. u32 val;
  1187. val = be32_to_cpu(*attr);
  1188. /* Setup 2eSST speeds */
  1189. switch (cycle & (VME_2eSST160 | VME_2eSST267 | VME_2eSST320)) {
  1190. case VME_2eSST160:
  1191. val |= TSI148_LCSR_DSAT_2eSSTM_160;
  1192. break;
  1193. case VME_2eSST267:
  1194. val |= TSI148_LCSR_DSAT_2eSSTM_267;
  1195. break;
  1196. case VME_2eSST320:
  1197. val |= TSI148_LCSR_DSAT_2eSSTM_320;
  1198. break;
  1199. }
  1200. /* Setup cycle types */
  1201. if (cycle & VME_SCT)
  1202. val |= TSI148_LCSR_DSAT_TM_SCT;
  1203. if (cycle & VME_BLT)
  1204. val |= TSI148_LCSR_DSAT_TM_BLT;
  1205. if (cycle & VME_MBLT)
  1206. val |= TSI148_LCSR_DSAT_TM_MBLT;
  1207. if (cycle & VME_2eVME)
  1208. val |= TSI148_LCSR_DSAT_TM_2eVME;
  1209. if (cycle & VME_2eSST)
  1210. val |= TSI148_LCSR_DSAT_TM_2eSST;
  1211. if (cycle & VME_2eSSTB) {
  1212. dev_err(dev, "Currently not setting Broadcast Select "
  1213. "Registers\n");
  1214. val |= TSI148_LCSR_DSAT_TM_2eSSTB;
  1215. }
  1216. /* Setup data width */
  1217. switch (dwidth) {
  1218. case VME_D16:
  1219. val |= TSI148_LCSR_DSAT_DBW_16;
  1220. break;
  1221. case VME_D32:
  1222. val |= TSI148_LCSR_DSAT_DBW_32;
  1223. break;
  1224. default:
  1225. dev_err(dev, "Invalid data width\n");
  1226. return -EINVAL;
  1227. }
  1228. /* Setup address space */
  1229. switch (aspace) {
  1230. case VME_A16:
  1231. val |= TSI148_LCSR_DSAT_AMODE_A16;
  1232. break;
  1233. case VME_A24:
  1234. val |= TSI148_LCSR_DSAT_AMODE_A24;
  1235. break;
  1236. case VME_A32:
  1237. val |= TSI148_LCSR_DSAT_AMODE_A32;
  1238. break;
  1239. case VME_A64:
  1240. val |= TSI148_LCSR_DSAT_AMODE_A64;
  1241. break;
  1242. case VME_CRCSR:
  1243. val |= TSI148_LCSR_DSAT_AMODE_CRCSR;
  1244. break;
  1245. case VME_USER1:
  1246. val |= TSI148_LCSR_DSAT_AMODE_USER1;
  1247. break;
  1248. case VME_USER2:
  1249. val |= TSI148_LCSR_DSAT_AMODE_USER2;
  1250. break;
  1251. case VME_USER3:
  1252. val |= TSI148_LCSR_DSAT_AMODE_USER3;
  1253. break;
  1254. case VME_USER4:
  1255. val |= TSI148_LCSR_DSAT_AMODE_USER4;
  1256. break;
  1257. default:
  1258. dev_err(dev, "Invalid address space\n");
  1259. return -EINVAL;
  1260. break;
  1261. }
  1262. if (cycle & VME_SUPER)
  1263. val |= TSI148_LCSR_DSAT_SUP;
  1264. if (cycle & VME_PROG)
  1265. val |= TSI148_LCSR_DSAT_PGM;
  1266. *attr = cpu_to_be32(val);
  1267. return 0;
  1268. }
  1269. static int tsi148_dma_set_vme_dest_attributes(struct device *dev, __be32 *attr,
  1270. u32 aspace, u32 cycle, u32 dwidth)
  1271. {
  1272. u32 val;
  1273. val = be32_to_cpu(*attr);
  1274. /* Setup 2eSST speeds */
  1275. switch (cycle & (VME_2eSST160 | VME_2eSST267 | VME_2eSST320)) {
  1276. case VME_2eSST160:
  1277. val |= TSI148_LCSR_DDAT_2eSSTM_160;
  1278. break;
  1279. case VME_2eSST267:
  1280. val |= TSI148_LCSR_DDAT_2eSSTM_267;
  1281. break;
  1282. case VME_2eSST320:
  1283. val |= TSI148_LCSR_DDAT_2eSSTM_320;
  1284. break;
  1285. }
  1286. /* Setup cycle types */
  1287. if (cycle & VME_SCT)
  1288. val |= TSI148_LCSR_DDAT_TM_SCT;
  1289. if (cycle & VME_BLT)
  1290. val |= TSI148_LCSR_DDAT_TM_BLT;
  1291. if (cycle & VME_MBLT)
  1292. val |= TSI148_LCSR_DDAT_TM_MBLT;
  1293. if (cycle & VME_2eVME)
  1294. val |= TSI148_LCSR_DDAT_TM_2eVME;
  1295. if (cycle & VME_2eSST)
  1296. val |= TSI148_LCSR_DDAT_TM_2eSST;
  1297. if (cycle & VME_2eSSTB) {
  1298. dev_err(dev, "Currently not setting Broadcast Select "
  1299. "Registers\n");
  1300. val |= TSI148_LCSR_DDAT_TM_2eSSTB;
  1301. }
  1302. /* Setup data width */
  1303. switch (dwidth) {
  1304. case VME_D16:
  1305. val |= TSI148_LCSR_DDAT_DBW_16;
  1306. break;
  1307. case VME_D32:
  1308. val |= TSI148_LCSR_DDAT_DBW_32;
  1309. break;
  1310. default:
  1311. dev_err(dev, "Invalid data width\n");
  1312. return -EINVAL;
  1313. }
  1314. /* Setup address space */
  1315. switch (aspace) {
  1316. case VME_A16:
  1317. val |= TSI148_LCSR_DDAT_AMODE_A16;
  1318. break;
  1319. case VME_A24:
  1320. val |= TSI148_LCSR_DDAT_AMODE_A24;
  1321. break;
  1322. case VME_A32:
  1323. val |= TSI148_LCSR_DDAT_AMODE_A32;
  1324. break;
  1325. case VME_A64:
  1326. val |= TSI148_LCSR_DDAT_AMODE_A64;
  1327. break;
  1328. case VME_CRCSR:
  1329. val |= TSI148_LCSR_DDAT_AMODE_CRCSR;
  1330. break;
  1331. case VME_USER1:
  1332. val |= TSI148_LCSR_DDAT_AMODE_USER1;
  1333. break;
  1334. case VME_USER2:
  1335. val |= TSI148_LCSR_DDAT_AMODE_USER2;
  1336. break;
  1337. case VME_USER3:
  1338. val |= TSI148_LCSR_DDAT_AMODE_USER3;
  1339. break;
  1340. case VME_USER4:
  1341. val |= TSI148_LCSR_DDAT_AMODE_USER4;
  1342. break;
  1343. default:
  1344. dev_err(dev, "Invalid address space\n");
  1345. return -EINVAL;
  1346. break;
  1347. }
  1348. if (cycle & VME_SUPER)
  1349. val |= TSI148_LCSR_DDAT_SUP;
  1350. if (cycle & VME_PROG)
  1351. val |= TSI148_LCSR_DDAT_PGM;
  1352. *attr = cpu_to_be32(val);
  1353. return 0;
  1354. }
  1355. /*
  1356. * Add a link list descriptor to the list
  1357. *
  1358. * Note: DMA engine expects the DMA descriptor to be big endian.
  1359. */
  1360. static int tsi148_dma_list_add(struct vme_dma_list *list,
  1361. struct vme_dma_attr *src, struct vme_dma_attr *dest, size_t count)
  1362. {
  1363. struct tsi148_dma_entry *entry, *prev;
  1364. u32 address_high, address_low, val;
  1365. struct vme_dma_pattern *pattern_attr;
  1366. struct vme_dma_pci *pci_attr;
  1367. struct vme_dma_vme *vme_attr;
  1368. int retval = 0;
  1369. struct vme_bridge *tsi148_bridge;
  1370. tsi148_bridge = list->parent->parent;
  1371. /* Descriptor must be aligned on 64-bit boundaries */
  1372. entry = kmalloc(sizeof(struct tsi148_dma_entry), GFP_KERNEL);
  1373. if (entry == NULL) {
  1374. dev_err(tsi148_bridge->parent, "Failed to allocate memory for "
  1375. "dma resource structure\n");
  1376. retval = -ENOMEM;
  1377. goto err_mem;
  1378. }
  1379. /* Test descriptor alignment */
  1380. if ((unsigned long)&entry->descriptor & 0x7) {
  1381. dev_err(tsi148_bridge->parent, "Descriptor not aligned to 8 "
  1382. "byte boundary as required: %p\n",
  1383. &entry->descriptor);
  1384. retval = -EINVAL;
  1385. goto err_align;
  1386. }
  1387. /* Given we are going to fill out the structure, we probably don't
  1388. * need to zero it, but better safe than sorry for now.
  1389. */
  1390. memset(&entry->descriptor, 0, sizeof(struct tsi148_dma_descriptor));
  1391. /* Fill out source part */
  1392. switch (src->type) {
  1393. case VME_DMA_PATTERN:
  1394. pattern_attr = src->private;
  1395. entry->descriptor.dsal = cpu_to_be32(pattern_attr->pattern);
  1396. val = TSI148_LCSR_DSAT_TYP_PAT;
  1397. /* Default behaviour is 32 bit pattern */
  1398. if (pattern_attr->type & VME_DMA_PATTERN_BYTE)
  1399. val |= TSI148_LCSR_DSAT_PSZ;
  1400. /* It seems that the default behaviour is to increment */
  1401. if ((pattern_attr->type & VME_DMA_PATTERN_INCREMENT) == 0)
  1402. val |= TSI148_LCSR_DSAT_NIN;
  1403. entry->descriptor.dsat = cpu_to_be32(val);
  1404. break;
  1405. case VME_DMA_PCI:
  1406. pci_attr = src->private;
  1407. reg_split((unsigned long long)pci_attr->address, &address_high,
  1408. &address_low);
  1409. entry->descriptor.dsau = cpu_to_be32(address_high);
  1410. entry->descriptor.dsal = cpu_to_be32(address_low);
  1411. entry->descriptor.dsat = cpu_to_be32(TSI148_LCSR_DSAT_TYP_PCI);
  1412. break;
  1413. case VME_DMA_VME:
  1414. vme_attr = src->private;
  1415. reg_split((unsigned long long)vme_attr->address, &address_high,
  1416. &address_low);
  1417. entry->descriptor.dsau = cpu_to_be32(address_high);
  1418. entry->descriptor.dsal = cpu_to_be32(address_low);
  1419. entry->descriptor.dsat = cpu_to_be32(TSI148_LCSR_DSAT_TYP_VME);
  1420. retval = tsi148_dma_set_vme_src_attributes(
  1421. tsi148_bridge->parent, &entry->descriptor.dsat,
  1422. vme_attr->aspace, vme_attr->cycle, vme_attr->dwidth);
  1423. if (retval < 0)
  1424. goto err_source;
  1425. break;
  1426. default:
  1427. dev_err(tsi148_bridge->parent, "Invalid source type\n");
  1428. retval = -EINVAL;
  1429. goto err_source;
  1430. break;
  1431. }
  1432. /* Assume last link - this will be over-written by adding another */
  1433. entry->descriptor.dnlau = cpu_to_be32(0);
  1434. entry->descriptor.dnlal = cpu_to_be32(TSI148_LCSR_DNLAL_LLA);
  1435. /* Fill out destination part */
  1436. switch (dest->type) {
  1437. case VME_DMA_PCI:
  1438. pci_attr = dest->private;
  1439. reg_split((unsigned long long)pci_attr->address, &address_high,
  1440. &address_low);
  1441. entry->descriptor.ddau = cpu_to_be32(address_high);
  1442. entry->descriptor.ddal = cpu_to_be32(address_low);
  1443. entry->descriptor.ddat = cpu_to_be32(TSI148_LCSR_DDAT_TYP_PCI);
  1444. break;
  1445. case VME_DMA_VME:
  1446. vme_attr = dest->private;
  1447. reg_split((unsigned long long)vme_attr->address, &address_high,
  1448. &address_low);
  1449. entry->descriptor.ddau = cpu_to_be32(address_high);
  1450. entry->descriptor.ddal = cpu_to_be32(address_low);
  1451. entry->descriptor.ddat = cpu_to_be32(TSI148_LCSR_DDAT_TYP_VME);
  1452. retval = tsi148_dma_set_vme_dest_attributes(
  1453. tsi148_bridge->parent, &entry->descriptor.ddat,
  1454. vme_attr->aspace, vme_attr->cycle, vme_attr->dwidth);
  1455. if (retval < 0)
  1456. goto err_dest;
  1457. break;
  1458. default:
  1459. dev_err(tsi148_bridge->parent, "Invalid destination type\n");
  1460. retval = -EINVAL;
  1461. goto err_dest;
  1462. break;
  1463. }
  1464. /* Fill out count */
  1465. entry->descriptor.dcnt = cpu_to_be32((u32)count);
  1466. /* Add to list */
  1467. list_add_tail(&entry->list, &list->entries);
  1468. /* Fill out previous descriptors "Next Address" */
  1469. if (entry->list.prev != &list->entries) {
  1470. prev = list_entry(entry->list.prev, struct tsi148_dma_entry,
  1471. list);
  1472. /* We need the bus address for the pointer */
  1473. entry->dma_handle = dma_map_single(tsi148_bridge->parent,
  1474. &entry->descriptor,
  1475. sizeof(struct tsi148_dma_descriptor), DMA_TO_DEVICE);
  1476. reg_split((unsigned long long)entry->dma_handle, &address_high,
  1477. &address_low);
  1478. entry->descriptor.dnlau = cpu_to_be32(address_high);
  1479. entry->descriptor.dnlal = cpu_to_be32(address_low);
  1480. }
  1481. return 0;
  1482. err_dest:
  1483. err_source:
  1484. err_align:
  1485. kfree(entry);
  1486. err_mem:
  1487. return retval;
  1488. }
  1489. /*
  1490. * Check to see if the provided DMA channel is busy.
  1491. */
  1492. static int tsi148_dma_busy(struct vme_bridge *tsi148_bridge, int channel)
  1493. {
  1494. u32 tmp;
  1495. struct tsi148_driver *bridge;
  1496. bridge = tsi148_bridge->driver_priv;
  1497. tmp = ioread32be(bridge->base + TSI148_LCSR_DMA[channel] +
  1498. TSI148_LCSR_OFFSET_DSTA);
  1499. if (tmp & TSI148_LCSR_DSTA_BSY)
  1500. return 0;
  1501. else
  1502. return 1;
  1503. }
  1504. /*
  1505. * Execute a previously generated link list
  1506. *
  1507. * XXX Need to provide control register configuration.
  1508. */
  1509. static int tsi148_dma_list_exec(struct vme_dma_list *list)
  1510. {
  1511. struct vme_dma_resource *ctrlr;
  1512. int channel, retval = 0;
  1513. struct tsi148_dma_entry *entry;
  1514. u32 bus_addr_high, bus_addr_low;
  1515. u32 val, dctlreg = 0;
  1516. struct vme_bridge *tsi148_bridge;
  1517. struct tsi148_driver *bridge;
  1518. ctrlr = list->parent;
  1519. tsi148_bridge = ctrlr->parent;
  1520. bridge = tsi148_bridge->driver_priv;
  1521. mutex_lock(&ctrlr->mtx);
  1522. channel = ctrlr->number;
  1523. if (!list_empty(&ctrlr->running)) {
  1524. /*
  1525. * XXX We have an active DMA transfer and currently haven't
  1526. * sorted out the mechanism for "pending" DMA transfers.
  1527. * Return busy.
  1528. */
  1529. /* Need to add to pending here */
  1530. mutex_unlock(&ctrlr->mtx);
  1531. return -EBUSY;
  1532. } else {
  1533. list_add(&list->list, &ctrlr->running);
  1534. }
  1535. /* Get first bus address and write into registers */
  1536. entry = list_first_entry(&list->entries, struct tsi148_dma_entry,
  1537. list);
  1538. entry->dma_handle = dma_map_single(tsi148_bridge->parent,
  1539. &entry->descriptor,
  1540. sizeof(struct tsi148_dma_descriptor), DMA_TO_DEVICE);
  1541. mutex_unlock(&ctrlr->mtx);
  1542. reg_split(entry->dma_handle, &bus_addr_high, &bus_addr_low);
  1543. iowrite32be(bus_addr_high, bridge->base +
  1544. TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DNLAU);
  1545. iowrite32be(bus_addr_low, bridge->base +
  1546. TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DNLAL);
  1547. dctlreg = ioread32be(bridge->base + TSI148_LCSR_DMA[channel] +
  1548. TSI148_LCSR_OFFSET_DCTL);
  1549. /* Start the operation */
  1550. iowrite32be(dctlreg | TSI148_LCSR_DCTL_DGO, bridge->base +
  1551. TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DCTL);
  1552. wait_event_interruptible(bridge->dma_queue[channel],
  1553. tsi148_dma_busy(ctrlr->parent, channel));
  1554. /*
  1555. * Read status register, this register is valid until we kick off a
  1556. * new transfer.
  1557. */
  1558. val = ioread32be(bridge->base + TSI148_LCSR_DMA[channel] +
  1559. TSI148_LCSR_OFFSET_DSTA);
  1560. if (val & TSI148_LCSR_DSTA_VBE) {
  1561. dev_err(tsi148_bridge->parent, "DMA Error. DSTA=%08X\n", val);
  1562. retval = -EIO;
  1563. }
  1564. /* Remove list from running list */
  1565. mutex_lock(&ctrlr->mtx);
  1566. list_del(&list->list);
  1567. mutex_unlock(&ctrlr->mtx);
  1568. return retval;
  1569. }
  1570. /*
  1571. * Clean up a previously generated link list
  1572. *
  1573. * We have a separate function, don't assume that the chain can't be reused.
  1574. */
  1575. static int tsi148_dma_list_empty(struct vme_dma_list *list)
  1576. {
  1577. struct list_head *pos, *temp;
  1578. struct tsi148_dma_entry *entry;
  1579. struct vme_bridge *tsi148_bridge = list->parent->parent;
  1580. /* detach and free each entry */
  1581. list_for_each_safe(pos, temp, &list->entries) {
  1582. list_del(pos);
  1583. entry = list_entry(pos, struct tsi148_dma_entry, list);
  1584. dma_unmap_single(tsi148_bridge->parent, entry->dma_handle,
  1585. sizeof(struct tsi148_dma_descriptor), DMA_TO_DEVICE);
  1586. kfree(entry);
  1587. }
  1588. return 0;
  1589. }
  1590. /*
  1591. * All 4 location monitors reside at the same base - this is therefore a
  1592. * system wide configuration.
  1593. *
  1594. * This does not enable the LM monitor - that should be done when the first
  1595. * callback is attached and disabled when the last callback is removed.
  1596. */
  1597. static int tsi148_lm_set(struct vme_lm_resource *lm, unsigned long long lm_base,
  1598. u32 aspace, u32 cycle)
  1599. {
  1600. u32 lm_base_high, lm_base_low, lm_ctl = 0;
  1601. int i;
  1602. struct vme_bridge *tsi148_bridge;
  1603. struct tsi148_driver *bridge;
  1604. tsi148_bridge = lm->parent;
  1605. bridge = tsi148_bridge->driver_priv;
  1606. mutex_lock(&lm->mtx);
  1607. /* If we already have a callback attached, we can't move it! */
  1608. for (i = 0; i < lm->monitors; i++) {
  1609. if (bridge->lm_callback[i] != NULL) {
  1610. mutex_unlock(&lm->mtx);
  1611. dev_err(tsi148_bridge->parent, "Location monitor "
  1612. "callback attached, can't reset\n");
  1613. return -EBUSY;
  1614. }
  1615. }
  1616. switch (aspace) {
  1617. case VME_A16:
  1618. lm_ctl |= TSI148_LCSR_LMAT_AS_A16;
  1619. break;
  1620. case VME_A24:
  1621. lm_ctl |= TSI148_LCSR_LMAT_AS_A24;
  1622. break;
  1623. case VME_A32:
  1624. lm_ctl |= TSI148_LCSR_LMAT_AS_A32;
  1625. break;
  1626. case VME_A64:
  1627. lm_ctl |= TSI148_LCSR_LMAT_AS_A64;
  1628. break;
  1629. default:
  1630. mutex_unlock(&lm->mtx);
  1631. dev_err(tsi148_bridge->parent, "Invalid address space\n");
  1632. return -EINVAL;
  1633. break;
  1634. }
  1635. if (cycle & VME_SUPER)
  1636. lm_ctl |= TSI148_LCSR_LMAT_SUPR ;
  1637. if (cycle & VME_USER)
  1638. lm_ctl |= TSI148_LCSR_LMAT_NPRIV;
  1639. if (cycle & VME_PROG)
  1640. lm_ctl |= TSI148_LCSR_LMAT_PGM;
  1641. if (cycle & VME_DATA)
  1642. lm_ctl |= TSI148_LCSR_LMAT_DATA;
  1643. reg_split(lm_base, &lm_base_high, &lm_base_low);
  1644. iowrite32be(lm_base_high, bridge->base + TSI148_LCSR_LMBAU);
  1645. iowrite32be(lm_base_low, bridge->base + TSI148_LCSR_LMBAL);
  1646. iowrite32be(lm_ctl, bridge->base + TSI148_LCSR_LMAT);
  1647. mutex_unlock(&lm->mtx);
  1648. return 0;
  1649. }
  1650. /* Get configuration of the callback monitor and return whether it is enabled
  1651. * or disabled.
  1652. */
  1653. static int tsi148_lm_get(struct vme_lm_resource *lm,
  1654. unsigned long long *lm_base, u32 *aspace, u32 *cycle)
  1655. {
  1656. u32 lm_base_high, lm_base_low, lm_ctl, enabled = 0;
  1657. struct tsi148_driver *bridge;
  1658. bridge = lm->parent->driver_priv;
  1659. mutex_lock(&lm->mtx);
  1660. lm_base_high = ioread32be(bridge->base + TSI148_LCSR_LMBAU);
  1661. lm_base_low = ioread32be(bridge->base + TSI148_LCSR_LMBAL);
  1662. lm_ctl = ioread32be(bridge->base + TSI148_LCSR_LMAT);
  1663. reg_join(lm_base_high, lm_base_low, lm_base);
  1664. if (lm_ctl & TSI148_LCSR_LMAT_EN)
  1665. enabled = 1;
  1666. if ((lm_ctl & TSI148_LCSR_LMAT_AS_M) == TSI148_LCSR_LMAT_AS_A16)
  1667. *aspace |= VME_A16;
  1668. if ((lm_ctl & TSI148_LCSR_LMAT_AS_M) == TSI148_LCSR_LMAT_AS_A24)
  1669. *aspace |= VME_A24;
  1670. if ((lm_ctl & TSI148_LCSR_LMAT_AS_M) == TSI148_LCSR_LMAT_AS_A32)
  1671. *aspace |= VME_A32;
  1672. if ((lm_ctl & TSI148_LCSR_LMAT_AS_M) == TSI148_LCSR_LMAT_AS_A64)
  1673. *aspace |= VME_A64;
  1674. if (lm_ctl & TSI148_LCSR_LMAT_SUPR)
  1675. *cycle |= VME_SUPER;
  1676. if (lm_ctl & TSI148_LCSR_LMAT_NPRIV)
  1677. *cycle |= VME_USER;
  1678. if (lm_ctl & TSI148_LCSR_LMAT_PGM)
  1679. *cycle |= VME_PROG;
  1680. if (lm_ctl & TSI148_LCSR_LMAT_DATA)
  1681. *cycle |= VME_DATA;
  1682. mutex_unlock(&lm->mtx);
  1683. return enabled;
  1684. }
  1685. /*
  1686. * Attach a callback to a specific location monitor.
  1687. *
  1688. * Callback will be passed the monitor triggered.
  1689. */
  1690. static int tsi148_lm_attach(struct vme_lm_resource *lm, int monitor,
  1691. void (*callback)(int))
  1692. {
  1693. u32 lm_ctl, tmp;
  1694. struct vme_bridge *tsi148_bridge;
  1695. struct tsi148_driver *bridge;
  1696. tsi148_bridge = lm->parent;
  1697. bridge = tsi148_bridge->driver_priv;
  1698. mutex_lock(&lm->mtx);
  1699. /* Ensure that the location monitor is configured - need PGM or DATA */
  1700. lm_ctl = ioread32be(bridge->base + TSI148_LCSR_LMAT);
  1701. if ((lm_ctl & (TSI148_LCSR_LMAT_PGM | TSI148_LCSR_LMAT_DATA)) == 0) {
  1702. mutex_unlock(&lm->mtx);
  1703. dev_err(tsi148_bridge->parent, "Location monitor not properly "
  1704. "configured\n");
  1705. return -EINVAL;
  1706. }
  1707. /* Check that a callback isn't already attached */
  1708. if (bridge->lm_callback[monitor] != NULL) {
  1709. mutex_unlock(&lm->mtx);
  1710. dev_err(tsi148_bridge->parent, "Existing callback attached\n");
  1711. return -EBUSY;
  1712. }
  1713. /* Attach callback */
  1714. bridge->lm_callback[monitor] = callback;
  1715. /* Enable Location Monitor interrupt */
  1716. tmp = ioread32be(bridge->base + TSI148_LCSR_INTEN);
  1717. tmp |= TSI148_LCSR_INTEN_LMEN[monitor];
  1718. iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN);
  1719. tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO);
  1720. tmp |= TSI148_LCSR_INTEO_LMEO[monitor];
  1721. iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO);
  1722. /* Ensure that global Location Monitor Enable set */
  1723. if ((lm_ctl & TSI148_LCSR_LMAT_EN) == 0) {
  1724. lm_ctl |= TSI148_LCSR_LMAT_EN;
  1725. iowrite32be(lm_ctl, bridge->base + TSI148_LCSR_LMAT);
  1726. }
  1727. mutex_unlock(&lm->mtx);
  1728. return 0;
  1729. }
  1730. /*
  1731. * Detach a callback function forn a specific location monitor.
  1732. */
  1733. static int tsi148_lm_detach(struct vme_lm_resource *lm, int monitor)
  1734. {
  1735. u32 lm_en, tmp;
  1736. struct tsi148_driver *bridge;
  1737. bridge = lm->parent->driver_priv;
  1738. mutex_lock(&lm->mtx);
  1739. /* Disable Location Monitor and ensure previous interrupts are clear */
  1740. lm_en = ioread32be(bridge->base + TSI148_LCSR_INTEN);
  1741. lm_en &= ~TSI148_LCSR_INTEN_LMEN[monitor];
  1742. iowrite32be(lm_en, bridge->base + TSI148_LCSR_INTEN);
  1743. tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO);
  1744. tmp &= ~TSI148_LCSR_INTEO_LMEO[monitor];
  1745. iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO);
  1746. iowrite32be(TSI148_LCSR_INTC_LMC[monitor],
  1747. bridge->base + TSI148_LCSR_INTC);
  1748. /* Detach callback */
  1749. bridge->lm_callback[monitor] = NULL;
  1750. /* If all location monitors disabled, disable global Location Monitor */
  1751. if ((lm_en & (TSI148_LCSR_INTS_LM0S | TSI148_LCSR_INTS_LM1S |
  1752. TSI148_LCSR_INTS_LM2S | TSI148_LCSR_INTS_LM3S)) == 0) {
  1753. tmp = ioread32be(bridge->base + TSI148_LCSR_LMAT);
  1754. tmp &= ~TSI148_LCSR_LMAT_EN;
  1755. iowrite32be(tmp, bridge->base + TSI148_LCSR_LMAT);
  1756. }
  1757. mutex_unlock(&lm->mtx);
  1758. return 0;
  1759. }
  1760. /*
  1761. * Determine Geographical Addressing
  1762. */
  1763. static int tsi148_slot_get(struct vme_bridge *tsi148_bridge)
  1764. {
  1765. u32 slot = 0;
  1766. struct tsi148_driver *bridge;
  1767. bridge = tsi148_bridge->driver_priv;
  1768. if (!geoid) {
  1769. slot = ioread32be(bridge->base + TSI148_LCSR_VSTAT);
  1770. slot = slot & TSI148_LCSR_VSTAT_GA_M;
  1771. } else
  1772. slot = geoid;
  1773. return (int)slot;
  1774. }
  1775. static void *tsi148_alloc_consistent(struct device *parent, size_t size,
  1776. dma_addr_t *dma)
  1777. {
  1778. struct pci_dev *pdev;
  1779. /* Find pci_dev container of dev */
  1780. pdev = container_of(parent, struct pci_dev, dev);
  1781. return pci_alloc_consistent(pdev, size, dma);
  1782. }
  1783. static void tsi148_free_consistent(struct device *parent, size_t size,
  1784. void *vaddr, dma_addr_t dma)
  1785. {
  1786. struct pci_dev *pdev;
  1787. /* Find pci_dev container of dev */
  1788. pdev = container_of(parent, struct pci_dev, dev);
  1789. pci_free_consistent(pdev, size, vaddr, dma);
  1790. }
  1791. static int __init tsi148_init(void)
  1792. {
  1793. return pci_register_driver(&tsi148_driver);
  1794. }
  1795. /*
  1796. * Configure CR/CSR space
  1797. *
  1798. * Access to the CR/CSR can be configured at power-up. The location of the
  1799. * CR/CSR registers in the CR/CSR address space is determined by the boards
  1800. * Auto-ID or Geographic address. This function ensures that the window is
  1801. * enabled at an offset consistent with the boards geopgraphic address.
  1802. *
  1803. * Each board has a 512kB window, with the highest 4kB being used for the
  1804. * boards registers, this means there is a fix length 508kB window which must
  1805. * be mapped onto PCI memory.
  1806. */
  1807. static int tsi148_crcsr_init(struct vme_bridge *tsi148_bridge,
  1808. struct pci_dev *pdev)
  1809. {
  1810. u32 cbar, crat, vstat;
  1811. u32 crcsr_bus_high, crcsr_bus_low;
  1812. int retval;
  1813. struct tsi148_driver *bridge;
  1814. bridge = tsi148_bridge->driver_priv;
  1815. /* Allocate mem for CR/CSR image */
  1816. bridge->crcsr_kernel = pci_alloc_consistent(pdev, VME_CRCSR_BUF_SIZE,
  1817. &bridge->crcsr_bus);
  1818. if (bridge->crcsr_kernel == NULL) {
  1819. dev_err(tsi148_bridge->parent, "Failed to allocate memory for "
  1820. "CR/CSR image\n");
  1821. return -ENOMEM;
  1822. }
  1823. memset(bridge->crcsr_kernel, 0, VME_CRCSR_BUF_SIZE);
  1824. reg_split(bridge->crcsr_bus, &crcsr_bus_high, &crcsr_bus_low);
  1825. iowrite32be(crcsr_bus_high, bridge->base + TSI148_LCSR_CROU);
  1826. iowrite32be(crcsr_bus_low, bridge->base + TSI148_LCSR_CROL);
  1827. /* Ensure that the CR/CSR is configured at the correct offset */
  1828. cbar = ioread32be(bridge->base + TSI148_CBAR);
  1829. cbar = (cbar & TSI148_CRCSR_CBAR_M)>>3;
  1830. vstat = tsi148_slot_get(tsi148_bridge);
  1831. if (cbar != vstat) {
  1832. cbar = vstat;
  1833. dev_info(tsi148_bridge->parent, "Setting CR/CSR offset\n");
  1834. iowrite32be(cbar<<3, bridge->base + TSI148_CBAR);
  1835. }
  1836. dev_info(tsi148_bridge->parent, "CR/CSR Offset: %d\n", cbar);
  1837. crat = ioread32be(bridge->base + TSI148_LCSR_CRAT);
  1838. if (crat & TSI148_LCSR_CRAT_EN) {
  1839. dev_info(tsi148_bridge->parent, "Enabling CR/CSR space\n");
  1840. iowrite32be(crat | TSI148_LCSR_CRAT_EN,
  1841. bridge->base + TSI148_LCSR_CRAT);
  1842. } else
  1843. dev_info(tsi148_bridge->parent, "CR/CSR already enabled\n");
  1844. /* If we want flushed, error-checked writes, set up a window
  1845. * over the CR/CSR registers. We read from here to safely flush
  1846. * through VME writes.
  1847. */
  1848. if (err_chk) {
  1849. retval = tsi148_master_set(bridge->flush_image, 1,
  1850. (vstat * 0x80000), 0x80000, VME_CRCSR, VME_SCT,
  1851. VME_D16);
  1852. if (retval)
  1853. dev_err(tsi148_bridge->parent, "Configuring flush image"
  1854. " failed\n");
  1855. }
  1856. return 0;
  1857. }
  1858. static void tsi148_crcsr_exit(struct vme_bridge *tsi148_bridge,
  1859. struct pci_dev *pdev)
  1860. {
  1861. u32 crat;
  1862. struct tsi148_driver *bridge;
  1863. bridge = tsi148_bridge->driver_priv;
  1864. /* Turn off CR/CSR space */
  1865. crat = ioread32be(bridge->base + TSI148_LCSR_CRAT);
  1866. iowrite32be(crat & ~TSI148_LCSR_CRAT_EN,
  1867. bridge->base + TSI148_LCSR_CRAT);
  1868. /* Free image */
  1869. iowrite32be(0, bridge->base + TSI148_LCSR_CROU);
  1870. iowrite32be(0, bridge->base + TSI148_LCSR_CROL);
  1871. pci_free_consistent(pdev, VME_CRCSR_BUF_SIZE, bridge->crcsr_kernel,
  1872. bridge->crcsr_bus);
  1873. }
  1874. static int tsi148_probe(struct pci_dev *pdev, const struct pci_device_id *id)
  1875. {
  1876. int retval, i, master_num;
  1877. u32 data;
  1878. struct list_head *pos = NULL;
  1879. struct vme_bridge *tsi148_bridge;
  1880. struct tsi148_driver *tsi148_device;
  1881. struct vme_master_resource *master_image;
  1882. struct vme_slave_resource *slave_image;
  1883. struct vme_dma_resource *dma_ctrlr;
  1884. struct vme_lm_resource *lm;
  1885. /* If we want to support more than one of each bridge, we need to
  1886. * dynamically generate this so we get one per device
  1887. */
  1888. tsi148_bridge = kzalloc(sizeof(struct vme_bridge), GFP_KERNEL);
  1889. if (tsi148_bridge == NULL) {
  1890. dev_err(&pdev->dev, "Failed to allocate memory for device "
  1891. "structure\n");
  1892. retval = -ENOMEM;
  1893. goto err_struct;
  1894. }
  1895. tsi148_device = kzalloc(sizeof(struct tsi148_driver), GFP_KERNEL);
  1896. if (tsi148_device == NULL) {
  1897. dev_err(&pdev->dev, "Failed to allocate memory for device "
  1898. "structure\n");
  1899. retval = -ENOMEM;
  1900. goto err_driver;
  1901. }
  1902. tsi148_bridge->driver_priv = tsi148_device;
  1903. /* Enable the device */
  1904. retval = pci_enable_device(pdev);
  1905. if (retval) {
  1906. dev_err(&pdev->dev, "Unable to enable device\n");
  1907. goto err_enable;
  1908. }
  1909. /* Map Registers */
  1910. retval = pci_request_regions(pdev, driver_name);
  1911. if (retval) {
  1912. dev_err(&pdev->dev, "Unable to reserve resources\n");
  1913. goto err_resource;
  1914. }
  1915. /* map registers in BAR 0 */
  1916. tsi148_device->base = ioremap_nocache(pci_resource_start(pdev, 0),
  1917. 4096);
  1918. if (!tsi148_device->base) {
  1919. dev_err(&pdev->dev, "Unable to remap CRG region\n");
  1920. retval = -EIO;
  1921. goto err_remap;
  1922. }
  1923. /* Check to see if the mapping worked out */
  1924. data = ioread32(tsi148_device->base + TSI148_PCFS_ID) & 0x0000FFFF;
  1925. if (data != PCI_VENDOR_ID_TUNDRA) {
  1926. dev_err(&pdev->dev, "CRG region check failed\n");
  1927. retval = -EIO;
  1928. goto err_test;
  1929. }
  1930. /* Initialize wait queues & mutual exclusion flags */
  1931. init_waitqueue_head(&tsi148_device->dma_queue[0]);
  1932. init_waitqueue_head(&tsi148_device->dma_queue[1]);
  1933. init_waitqueue_head(&tsi148_device->iack_queue);
  1934. mutex_init(&tsi148_device->vme_int);
  1935. mutex_init(&tsi148_device->vme_rmw);
  1936. tsi148_bridge->parent = &pdev->dev;
  1937. strcpy(tsi148_bridge->name, driver_name);
  1938. /* Setup IRQ */
  1939. retval = tsi148_irq_init(tsi148_bridge);
  1940. if (retval != 0) {
  1941. dev_err(&pdev->dev, "Chip Initialization failed.\n");
  1942. goto err_irq;
  1943. }
  1944. /* If we are going to flush writes, we need to read from the VME bus.
  1945. * We need to do this safely, thus we read the devices own CR/CSR
  1946. * register. To do this we must set up a window in CR/CSR space and
  1947. * hence have one less master window resource available.
  1948. */
  1949. master_num = TSI148_MAX_MASTER;
  1950. if (err_chk) {
  1951. master_num--;
  1952. tsi148_device->flush_image =
  1953. kmalloc(sizeof(struct vme_master_resource), GFP_KERNEL);
  1954. if (tsi148_device->flush_image == NULL) {
  1955. dev_err(&pdev->dev, "Failed to allocate memory for "
  1956. "flush resource structure\n");
  1957. retval = -ENOMEM;
  1958. goto err_master;
  1959. }
  1960. tsi148_device->flush_image->parent = tsi148_bridge;
  1961. spin_lock_init(&tsi148_device->flush_image->lock);
  1962. tsi148_device->flush_image->locked = 1;
  1963. tsi148_device->flush_image->number = master_num;
  1964. tsi148_device->flush_image->address_attr = VME_A16 | VME_A24 |
  1965. VME_A32 | VME_A64;
  1966. tsi148_device->flush_image->cycle_attr = VME_SCT | VME_BLT |
  1967. VME_MBLT | VME_2eVME | VME_2eSST | VME_2eSSTB |
  1968. VME_2eSST160 | VME_2eSST267 | VME_2eSST320 | VME_SUPER |
  1969. VME_USER | VME_PROG | VME_DATA;
  1970. tsi148_device->flush_image->width_attr = VME_D16 | VME_D32;
  1971. memset(&tsi148_device->flush_image->bus_resource, 0,
  1972. sizeof(struct resource));
  1973. tsi148_device->flush_image->kern_base = NULL;
  1974. }
  1975. /* Add master windows to list */
  1976. INIT_LIST_HEAD(&tsi148_bridge->master_resources);
  1977. for (i = 0; i < master_num; i++) {
  1978. master_image = kmalloc(sizeof(struct vme_master_resource),
  1979. GFP_KERNEL);
  1980. if (master_image == NULL) {
  1981. dev_err(&pdev->dev, "Failed to allocate memory for "
  1982. "master resource structure\n");
  1983. retval = -ENOMEM;
  1984. goto err_master;
  1985. }
  1986. master_image->parent = tsi148_bridge;
  1987. spin_lock_init(&master_image->lock);
  1988. master_image->locked = 0;
  1989. master_image->number = i;
  1990. master_image->address_attr = VME_A16 | VME_A24 | VME_A32 |
  1991. VME_A64;
  1992. master_image->cycle_attr = VME_SCT | VME_BLT | VME_MBLT |
  1993. VME_2eVME | VME_2eSST | VME_2eSSTB | VME_2eSST160 |
  1994. VME_2eSST267 | VME_2eSST320 | VME_SUPER | VME_USER |
  1995. VME_PROG | VME_DATA;
  1996. master_image->width_attr = VME_D16 | VME_D32;
  1997. memset(&master_image->bus_resource, 0,
  1998. sizeof(struct resource));
  1999. master_image->kern_base = NULL;
  2000. list_add_tail(&master_image->list,
  2001. &tsi148_bridge->master_resources);
  2002. }
  2003. /* Add slave windows to list */
  2004. INIT_LIST_HEAD(&tsi148_bridge->slave_resources);
  2005. for (i = 0; i < TSI148_MAX_SLAVE; i++) {
  2006. slave_image = kmalloc(sizeof(struct vme_slave_resource),
  2007. GFP_KERNEL);
  2008. if (slave_image == NULL) {
  2009. dev_err(&pdev->dev, "Failed to allocate memory for "
  2010. "slave resource structure\n");
  2011. retval = -ENOMEM;
  2012. goto err_slave;
  2013. }
  2014. slave_image->parent = tsi148_bridge;
  2015. mutex_init(&slave_image->mtx);
  2016. slave_image->locked = 0;
  2017. slave_image->number = i;
  2018. slave_image->address_attr = VME_A16 | VME_A24 | VME_A32 |
  2019. VME_A64 | VME_CRCSR | VME_USER1 | VME_USER2 |
  2020. VME_USER3 | VME_USER4;
  2021. slave_image->cycle_attr = VME_SCT | VME_BLT | VME_MBLT |
  2022. VME_2eVME | VME_2eSST | VME_2eSSTB | VME_2eSST160 |
  2023. VME_2eSST267 | VME_2eSST320 | VME_SUPER | VME_USER |
  2024. VME_PROG | VME_DATA;
  2025. list_add_tail(&slave_image->list,
  2026. &tsi148_bridge->slave_resources);
  2027. }
  2028. /* Add dma engines to list */
  2029. INIT_LIST_HEAD(&tsi148_bridge->dma_resources);
  2030. for (i = 0; i < TSI148_MAX_DMA; i++) {
  2031. dma_ctrlr = kmalloc(sizeof(struct vme_dma_resource),
  2032. GFP_KERNEL);
  2033. if (dma_ctrlr == NULL) {
  2034. dev_err(&pdev->dev, "Failed to allocate memory for "
  2035. "dma resource structure\n");
  2036. retval = -ENOMEM;
  2037. goto err_dma;
  2038. }
  2039. dma_ctrlr->parent = tsi148_bridge;
  2040. mutex_init(&dma_ctrlr->mtx);
  2041. dma_ctrlr->locked = 0;
  2042. dma_ctrlr->number = i;
  2043. dma_ctrlr->route_attr = VME_DMA_VME_TO_MEM |
  2044. VME_DMA_MEM_TO_VME | VME_DMA_VME_TO_VME |
  2045. VME_DMA_MEM_TO_MEM | VME_DMA_PATTERN_TO_VME |
  2046. VME_DMA_PATTERN_TO_MEM;
  2047. INIT_LIST_HEAD(&dma_ctrlr->pending);
  2048. INIT_LIST_HEAD(&dma_ctrlr->running);
  2049. list_add_tail(&dma_ctrlr->list,
  2050. &tsi148_bridge->dma_resources);
  2051. }
  2052. /* Add location monitor to list */
  2053. INIT_LIST_HEAD(&tsi148_bridge->lm_resources);
  2054. lm = kmalloc(sizeof(struct vme_lm_resource), GFP_KERNEL);
  2055. if (lm == NULL) {
  2056. dev_err(&pdev->dev, "Failed to allocate memory for "
  2057. "location monitor resource structure\n");
  2058. retval = -ENOMEM;
  2059. goto err_lm;
  2060. }
  2061. lm->parent = tsi148_bridge;
  2062. mutex_init(&lm->mtx);
  2063. lm->locked = 0;
  2064. lm->number = 1;
  2065. lm->monitors = 4;
  2066. list_add_tail(&lm->list, &tsi148_bridge->lm_resources);
  2067. tsi148_bridge->slave_get = tsi148_slave_get;
  2068. tsi148_bridge->slave_set = tsi148_slave_set;
  2069. tsi148_bridge->master_get = tsi148_master_get;
  2070. tsi148_bridge->master_set = tsi148_master_set;
  2071. tsi148_bridge->master_read = tsi148_master_read;
  2072. tsi148_bridge->master_write = tsi148_master_write;
  2073. tsi148_bridge->master_rmw = tsi148_master_rmw;
  2074. tsi148_bridge->dma_list_add = tsi148_dma_list_add;
  2075. tsi148_bridge->dma_list_exec = tsi148_dma_list_exec;
  2076. tsi148_bridge->dma_list_empty = tsi148_dma_list_empty;
  2077. tsi148_bridge->irq_set = tsi148_irq_set;
  2078. tsi148_bridge->irq_generate = tsi148_irq_generate;
  2079. tsi148_bridge->lm_set = tsi148_lm_set;
  2080. tsi148_bridge->lm_get = tsi148_lm_get;
  2081. tsi148_bridge->lm_attach = tsi148_lm_attach;
  2082. tsi148_bridge->lm_detach = tsi148_lm_detach;
  2083. tsi148_bridge->slot_get = tsi148_slot_get;
  2084. tsi148_bridge->alloc_consistent = tsi148_alloc_consistent;
  2085. tsi148_bridge->free_consistent = tsi148_free_consistent;
  2086. data = ioread32be(tsi148_device->base + TSI148_LCSR_VSTAT);
  2087. dev_info(&pdev->dev, "Board is%s the VME system controller\n",
  2088. (data & TSI148_LCSR_VSTAT_SCONS) ? "" : " not");
  2089. if (!geoid)
  2090. dev_info(&pdev->dev, "VME geographical address is %d\n",
  2091. data & TSI148_LCSR_VSTAT_GA_M);
  2092. else
  2093. dev_info(&pdev->dev, "VME geographical address is set to %d\n",
  2094. geoid);
  2095. dev_info(&pdev->dev, "VME Write and flush and error check is %s\n",
  2096. err_chk ? "enabled" : "disabled");
  2097. if (tsi148_crcsr_init(tsi148_bridge, pdev)) {
  2098. dev_err(&pdev->dev, "CR/CSR configuration failed.\n");
  2099. goto err_crcsr;
  2100. }
  2101. retval = vme_register_bridge(tsi148_bridge);
  2102. if (retval != 0) {
  2103. dev_err(&pdev->dev, "Chip Registration failed.\n");
  2104. goto err_reg;
  2105. }
  2106. pci_set_drvdata(pdev, tsi148_bridge);
  2107. /* Clear VME bus "board fail", and "power-up reset" lines */
  2108. data = ioread32be(tsi148_device->base + TSI148_LCSR_VSTAT);
  2109. data &= ~TSI148_LCSR_VSTAT_BRDFL;
  2110. data |= TSI148_LCSR_VSTAT_CPURST;
  2111. iowrite32be(data, tsi148_device->base + TSI148_LCSR_VSTAT);
  2112. return 0;
  2113. err_reg:
  2114. tsi148_crcsr_exit(tsi148_bridge, pdev);
  2115. err_crcsr:
  2116. err_lm:
  2117. /* resources are stored in link list */
  2118. list_for_each(pos, &tsi148_bridge->lm_resources) {
  2119. lm = list_entry(pos, struct vme_lm_resource, list);
  2120. list_del(pos);
  2121. kfree(lm);
  2122. }
  2123. err_dma:
  2124. /* resources are stored in link list */
  2125. list_for_each(pos, &tsi148_bridge->dma_resources) {
  2126. dma_ctrlr = list_entry(pos, struct vme_dma_resource, list);
  2127. list_del(pos);
  2128. kfree(dma_ctrlr);
  2129. }
  2130. err_slave:
  2131. /* resources are stored in link list */
  2132. list_for_each(pos, &tsi148_bridge->slave_resources) {
  2133. slave_image = list_entry(pos, struct vme_slave_resource, list);
  2134. list_del(pos);
  2135. kfree(slave_image);
  2136. }
  2137. err_master:
  2138. /* resources are stored in link list */
  2139. list_for_each(pos, &tsi148_bridge->master_resources) {
  2140. master_image = list_entry(pos, struct vme_master_resource,
  2141. list);
  2142. list_del(pos);
  2143. kfree(master_image);
  2144. }
  2145. tsi148_irq_exit(tsi148_bridge, pdev);
  2146. err_irq:
  2147. err_test:
  2148. iounmap(tsi148_device->base);
  2149. err_remap:
  2150. pci_release_regions(pdev);
  2151. err_resource:
  2152. pci_disable_device(pdev);
  2153. err_enable:
  2154. kfree(tsi148_device);
  2155. err_driver:
  2156. kfree(tsi148_bridge);
  2157. err_struct:
  2158. return retval;
  2159. }
  2160. static void tsi148_remove(struct pci_dev *pdev)
  2161. {
  2162. struct list_head *pos = NULL;
  2163. struct list_head *tmplist;
  2164. struct vme_master_resource *master_image;
  2165. struct vme_slave_resource *slave_image;
  2166. struct vme_dma_resource *dma_ctrlr;
  2167. int i;
  2168. struct tsi148_driver *bridge;
  2169. struct vme_bridge *tsi148_bridge = pci_get_drvdata(pdev);
  2170. bridge = tsi148_bridge->driver_priv;
  2171. dev_dbg(&pdev->dev, "Driver is being unloaded.\n");
  2172. /*
  2173. * Shutdown all inbound and outbound windows.
  2174. */
  2175. for (i = 0; i < 8; i++) {
  2176. iowrite32be(0, bridge->base + TSI148_LCSR_IT[i] +
  2177. TSI148_LCSR_OFFSET_ITAT);
  2178. iowrite32be(0, bridge->base + TSI148_LCSR_OT[i] +
  2179. TSI148_LCSR_OFFSET_OTAT);
  2180. }
  2181. /*
  2182. * Shutdown Location monitor.
  2183. */
  2184. iowrite32be(0, bridge->base + TSI148_LCSR_LMAT);
  2185. /*
  2186. * Shutdown CRG map.
  2187. */
  2188. iowrite32be(0, bridge->base + TSI148_LCSR_CSRAT);
  2189. /*
  2190. * Clear error status.
  2191. */
  2192. iowrite32be(0xFFFFFFFF, bridge->base + TSI148_LCSR_EDPAT);
  2193. iowrite32be(0xFFFFFFFF, bridge->base + TSI148_LCSR_VEAT);
  2194. iowrite32be(0x07000700, bridge->base + TSI148_LCSR_PSTAT);
  2195. /*
  2196. * Remove VIRQ interrupt (if any)
  2197. */
  2198. if (ioread32be(bridge->base + TSI148_LCSR_VICR) & 0x800)
  2199. iowrite32be(0x8000, bridge->base + TSI148_LCSR_VICR);
  2200. /*
  2201. * Map all Interrupts to PCI INTA
  2202. */
  2203. iowrite32be(0x0, bridge->base + TSI148_LCSR_INTM1);
  2204. iowrite32be(0x0, bridge->base + TSI148_LCSR_INTM2);
  2205. tsi148_irq_exit(tsi148_bridge, pdev);
  2206. vme_unregister_bridge(tsi148_bridge);
  2207. tsi148_crcsr_exit(tsi148_bridge, pdev);
  2208. /* resources are stored in link list */
  2209. list_for_each_safe(pos, tmplist, &tsi148_bridge->dma_resources) {
  2210. dma_ctrlr = list_entry(pos, struct vme_dma_resource, list);
  2211. list_del(pos);
  2212. kfree(dma_ctrlr);
  2213. }
  2214. /* resources are stored in link list */
  2215. list_for_each_safe(pos, tmplist, &tsi148_bridge->slave_resources) {
  2216. slave_image = list_entry(pos, struct vme_slave_resource, list);
  2217. list_del(pos);
  2218. kfree(slave_image);
  2219. }
  2220. /* resources are stored in link list */
  2221. list_for_each_safe(pos, tmplist, &tsi148_bridge->master_resources) {
  2222. master_image = list_entry(pos, struct vme_master_resource,
  2223. list);
  2224. list_del(pos);
  2225. kfree(master_image);
  2226. }
  2227. iounmap(bridge->base);
  2228. pci_release_regions(pdev);
  2229. pci_disable_device(pdev);
  2230. kfree(tsi148_bridge->driver_priv);
  2231. kfree(tsi148_bridge);
  2232. }
  2233. static void __exit tsi148_exit(void)
  2234. {
  2235. pci_unregister_driver(&tsi148_driver);
  2236. }
  2237. MODULE_PARM_DESC(err_chk, "Check for VME errors on reads and writes");
  2238. module_param(err_chk, bool, 0);
  2239. MODULE_PARM_DESC(geoid, "Override geographical addressing");
  2240. module_param(geoid, int, 0);
  2241. MODULE_DESCRIPTION("VME driver for the Tundra Tempe VME bridge");
  2242. MODULE_LICENSE("GPL");
  2243. module_init(tsi148_init);
  2244. module_exit(tsi148_exit);