dispc.h 16 KB

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  1. /*
  2. * linux/drivers/video/omap2/dss/dispc.h
  3. *
  4. * Copyright (C) 2011 Texas Instruments
  5. * Author: Archit Taneja <archit@ti.com>
  6. *
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of the GNU General Public License version 2 as published by
  10. * the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15. * more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along with
  18. * this program. If not, see <http://www.gnu.org/licenses/>.
  19. */
  20. #ifndef __OMAP2_DISPC_REG_H
  21. #define __OMAP2_DISPC_REG_H
  22. /* DISPC common registers */
  23. #define DISPC_REVISION 0x0000
  24. #define DISPC_SYSCONFIG 0x0010
  25. #define DISPC_SYSSTATUS 0x0014
  26. #define DISPC_IRQSTATUS 0x0018
  27. #define DISPC_IRQENABLE 0x001C
  28. #define DISPC_CONTROL 0x0040
  29. #define DISPC_CONFIG 0x0044
  30. #define DISPC_CAPABLE 0x0048
  31. #define DISPC_LINE_STATUS 0x005C
  32. #define DISPC_LINE_NUMBER 0x0060
  33. #define DISPC_GLOBAL_ALPHA 0x0074
  34. #define DISPC_CONTROL2 0x0238
  35. #define DISPC_CONFIG2 0x0620
  36. #define DISPC_DIVISOR 0x0804
  37. /* DISPC overlay registers */
  38. #define DISPC_OVL_BA0(n) (DISPC_OVL_BASE(n) + \
  39. DISPC_BA0_OFFSET(n))
  40. #define DISPC_OVL_BA1(n) (DISPC_OVL_BASE(n) + \
  41. DISPC_BA1_OFFSET(n))
  42. #define DISPC_OVL_BA0_UV(n) (DISPC_OVL_BASE(n) + \
  43. DISPC_BA0_UV_OFFSET(n))
  44. #define DISPC_OVL_BA1_UV(n) (DISPC_OVL_BASE(n) + \
  45. DISPC_BA1_UV_OFFSET(n))
  46. #define DISPC_OVL_POSITION(n) (DISPC_OVL_BASE(n) + \
  47. DISPC_POS_OFFSET(n))
  48. #define DISPC_OVL_SIZE(n) (DISPC_OVL_BASE(n) + \
  49. DISPC_SIZE_OFFSET(n))
  50. #define DISPC_OVL_ATTRIBUTES(n) (DISPC_OVL_BASE(n) + \
  51. DISPC_ATTR_OFFSET(n))
  52. #define DISPC_OVL_ATTRIBUTES2(n) (DISPC_OVL_BASE(n) + \
  53. DISPC_ATTR2_OFFSET(n))
  54. #define DISPC_OVL_FIFO_THRESHOLD(n) (DISPC_OVL_BASE(n) + \
  55. DISPC_FIFO_THRESH_OFFSET(n))
  56. #define DISPC_OVL_FIFO_SIZE_STATUS(n) (DISPC_OVL_BASE(n) + \
  57. DISPC_FIFO_SIZE_STATUS_OFFSET(n))
  58. #define DISPC_OVL_ROW_INC(n) (DISPC_OVL_BASE(n) + \
  59. DISPC_ROW_INC_OFFSET(n))
  60. #define DISPC_OVL_PIXEL_INC(n) (DISPC_OVL_BASE(n) + \
  61. DISPC_PIX_INC_OFFSET(n))
  62. #define DISPC_OVL_WINDOW_SKIP(n) (DISPC_OVL_BASE(n) + \
  63. DISPC_WINDOW_SKIP_OFFSET(n))
  64. #define DISPC_OVL_TABLE_BA(n) (DISPC_OVL_BASE(n) + \
  65. DISPC_TABLE_BA_OFFSET(n))
  66. #define DISPC_OVL_FIR(n) (DISPC_OVL_BASE(n) + \
  67. DISPC_FIR_OFFSET(n))
  68. #define DISPC_OVL_FIR2(n) (DISPC_OVL_BASE(n) + \
  69. DISPC_FIR2_OFFSET(n))
  70. #define DISPC_OVL_PICTURE_SIZE(n) (DISPC_OVL_BASE(n) + \
  71. DISPC_PIC_SIZE_OFFSET(n))
  72. #define DISPC_OVL_ACCU0(n) (DISPC_OVL_BASE(n) + \
  73. DISPC_ACCU0_OFFSET(n))
  74. #define DISPC_OVL_ACCU1(n) (DISPC_OVL_BASE(n) + \
  75. DISPC_ACCU1_OFFSET(n))
  76. #define DISPC_OVL_ACCU2_0(n) (DISPC_OVL_BASE(n) + \
  77. DISPC_ACCU2_0_OFFSET(n))
  78. #define DISPC_OVL_ACCU2_1(n) (DISPC_OVL_BASE(n) + \
  79. DISPC_ACCU2_1_OFFSET(n))
  80. #define DISPC_OVL_FIR_COEF_H(n, i) (DISPC_OVL_BASE(n) + \
  81. DISPC_FIR_COEF_H_OFFSET(n, i))
  82. #define DISPC_OVL_FIR_COEF_HV(n, i) (DISPC_OVL_BASE(n) + \
  83. DISPC_FIR_COEF_HV_OFFSET(n, i))
  84. #define DISPC_OVL_FIR_COEF_H2(n, i) (DISPC_OVL_BASE(n) + \
  85. DISPC_FIR_COEF_H2_OFFSET(n, i))
  86. #define DISPC_OVL_FIR_COEF_HV2(n, i) (DISPC_OVL_BASE(n) + \
  87. DISPC_FIR_COEF_HV2_OFFSET(n, i))
  88. #define DISPC_OVL_CONV_COEF(n, i) (DISPC_OVL_BASE(n) + \
  89. DISPC_CONV_COEF_OFFSET(n, i))
  90. #define DISPC_OVL_FIR_COEF_V(n, i) (DISPC_OVL_BASE(n) + \
  91. DISPC_FIR_COEF_V_OFFSET(n, i))
  92. #define DISPC_OVL_FIR_COEF_V2(n, i) (DISPC_OVL_BASE(n) + \
  93. DISPC_FIR_COEF_V2_OFFSET(n, i))
  94. #define DISPC_OVL_PRELOAD(n) (DISPC_OVL_BASE(n) + \
  95. DISPC_PRELOAD_OFFSET(n))
  96. /* DISPC up/downsampling FIR filter coefficient structure */
  97. struct dispc_coef {
  98. s8 hc4_vc22;
  99. s8 hc3_vc2;
  100. u8 hc2_vc1;
  101. s8 hc1_vc0;
  102. s8 hc0_vc00;
  103. };
  104. const struct dispc_coef *dispc_ovl_get_scale_coef(int inc, int five_taps);
  105. /* DISPC manager/channel specific registers */
  106. static inline u16 DISPC_DEFAULT_COLOR(enum omap_channel channel)
  107. {
  108. switch (channel) {
  109. case OMAP_DSS_CHANNEL_LCD:
  110. return 0x004C;
  111. case OMAP_DSS_CHANNEL_DIGIT:
  112. return 0x0050;
  113. case OMAP_DSS_CHANNEL_LCD2:
  114. return 0x03AC;
  115. default:
  116. BUG();
  117. return 0;
  118. }
  119. }
  120. static inline u16 DISPC_TRANS_COLOR(enum omap_channel channel)
  121. {
  122. switch (channel) {
  123. case OMAP_DSS_CHANNEL_LCD:
  124. return 0x0054;
  125. case OMAP_DSS_CHANNEL_DIGIT:
  126. return 0x0058;
  127. case OMAP_DSS_CHANNEL_LCD2:
  128. return 0x03B0;
  129. default:
  130. BUG();
  131. return 0;
  132. }
  133. }
  134. static inline u16 DISPC_TIMING_H(enum omap_channel channel)
  135. {
  136. switch (channel) {
  137. case OMAP_DSS_CHANNEL_LCD:
  138. return 0x0064;
  139. case OMAP_DSS_CHANNEL_DIGIT:
  140. BUG();
  141. return 0;
  142. case OMAP_DSS_CHANNEL_LCD2:
  143. return 0x0400;
  144. default:
  145. BUG();
  146. return 0;
  147. }
  148. }
  149. static inline u16 DISPC_TIMING_V(enum omap_channel channel)
  150. {
  151. switch (channel) {
  152. case OMAP_DSS_CHANNEL_LCD:
  153. return 0x0068;
  154. case OMAP_DSS_CHANNEL_DIGIT:
  155. BUG();
  156. return 0;
  157. case OMAP_DSS_CHANNEL_LCD2:
  158. return 0x0404;
  159. default:
  160. BUG();
  161. return 0;
  162. }
  163. }
  164. static inline u16 DISPC_POL_FREQ(enum omap_channel channel)
  165. {
  166. switch (channel) {
  167. case OMAP_DSS_CHANNEL_LCD:
  168. return 0x006C;
  169. case OMAP_DSS_CHANNEL_DIGIT:
  170. BUG();
  171. return 0;
  172. case OMAP_DSS_CHANNEL_LCD2:
  173. return 0x0408;
  174. default:
  175. BUG();
  176. return 0;
  177. }
  178. }
  179. static inline u16 DISPC_DIVISORo(enum omap_channel channel)
  180. {
  181. switch (channel) {
  182. case OMAP_DSS_CHANNEL_LCD:
  183. return 0x0070;
  184. case OMAP_DSS_CHANNEL_DIGIT:
  185. BUG();
  186. return 0;
  187. case OMAP_DSS_CHANNEL_LCD2:
  188. return 0x040C;
  189. default:
  190. BUG();
  191. return 0;
  192. }
  193. }
  194. /* Named as DISPC_SIZE_LCD, DISPC_SIZE_DIGIT and DISPC_SIZE_LCD2 in TRM */
  195. static inline u16 DISPC_SIZE_MGR(enum omap_channel channel)
  196. {
  197. switch (channel) {
  198. case OMAP_DSS_CHANNEL_LCD:
  199. return 0x007C;
  200. case OMAP_DSS_CHANNEL_DIGIT:
  201. return 0x0078;
  202. case OMAP_DSS_CHANNEL_LCD2:
  203. return 0x03CC;
  204. default:
  205. BUG();
  206. return 0;
  207. }
  208. }
  209. static inline u16 DISPC_DATA_CYCLE1(enum omap_channel channel)
  210. {
  211. switch (channel) {
  212. case OMAP_DSS_CHANNEL_LCD:
  213. return 0x01D4;
  214. case OMAP_DSS_CHANNEL_DIGIT:
  215. BUG();
  216. return 0;
  217. case OMAP_DSS_CHANNEL_LCD2:
  218. return 0x03C0;
  219. default:
  220. BUG();
  221. return 0;
  222. }
  223. }
  224. static inline u16 DISPC_DATA_CYCLE2(enum omap_channel channel)
  225. {
  226. switch (channel) {
  227. case OMAP_DSS_CHANNEL_LCD:
  228. return 0x01D8;
  229. case OMAP_DSS_CHANNEL_DIGIT:
  230. BUG();
  231. return 0;
  232. case OMAP_DSS_CHANNEL_LCD2:
  233. return 0x03C4;
  234. default:
  235. BUG();
  236. return 0;
  237. }
  238. }
  239. static inline u16 DISPC_DATA_CYCLE3(enum omap_channel channel)
  240. {
  241. switch (channel) {
  242. case OMAP_DSS_CHANNEL_LCD:
  243. return 0x01DC;
  244. case OMAP_DSS_CHANNEL_DIGIT:
  245. BUG();
  246. return 0;
  247. case OMAP_DSS_CHANNEL_LCD2:
  248. return 0x03C8;
  249. default:
  250. BUG();
  251. return 0;
  252. }
  253. }
  254. static inline u16 DISPC_CPR_COEF_R(enum omap_channel channel)
  255. {
  256. switch (channel) {
  257. case OMAP_DSS_CHANNEL_LCD:
  258. return 0x0220;
  259. case OMAP_DSS_CHANNEL_DIGIT:
  260. BUG();
  261. return 0;
  262. case OMAP_DSS_CHANNEL_LCD2:
  263. return 0x03BC;
  264. default:
  265. BUG();
  266. return 0;
  267. }
  268. }
  269. static inline u16 DISPC_CPR_COEF_G(enum omap_channel channel)
  270. {
  271. switch (channel) {
  272. case OMAP_DSS_CHANNEL_LCD:
  273. return 0x0224;
  274. case OMAP_DSS_CHANNEL_DIGIT:
  275. BUG();
  276. return 0;
  277. case OMAP_DSS_CHANNEL_LCD2:
  278. return 0x03B8;
  279. default:
  280. BUG();
  281. return 0;
  282. }
  283. }
  284. static inline u16 DISPC_CPR_COEF_B(enum omap_channel channel)
  285. {
  286. switch (channel) {
  287. case OMAP_DSS_CHANNEL_LCD:
  288. return 0x0228;
  289. case OMAP_DSS_CHANNEL_DIGIT:
  290. BUG();
  291. return 0;
  292. case OMAP_DSS_CHANNEL_LCD2:
  293. return 0x03B4;
  294. default:
  295. BUG();
  296. return 0;
  297. }
  298. }
  299. /* DISPC overlay register base addresses */
  300. static inline u16 DISPC_OVL_BASE(enum omap_plane plane)
  301. {
  302. switch (plane) {
  303. case OMAP_DSS_GFX:
  304. return 0x0080;
  305. case OMAP_DSS_VIDEO1:
  306. return 0x00BC;
  307. case OMAP_DSS_VIDEO2:
  308. return 0x014C;
  309. case OMAP_DSS_VIDEO3:
  310. return 0x0300;
  311. default:
  312. BUG();
  313. return 0;
  314. }
  315. }
  316. /* DISPC overlay register offsets */
  317. static inline u16 DISPC_BA0_OFFSET(enum omap_plane plane)
  318. {
  319. switch (plane) {
  320. case OMAP_DSS_GFX:
  321. case OMAP_DSS_VIDEO1:
  322. case OMAP_DSS_VIDEO2:
  323. return 0x0000;
  324. case OMAP_DSS_VIDEO3:
  325. return 0x0008;
  326. default:
  327. BUG();
  328. return 0;
  329. }
  330. }
  331. static inline u16 DISPC_BA1_OFFSET(enum omap_plane plane)
  332. {
  333. switch (plane) {
  334. case OMAP_DSS_GFX:
  335. case OMAP_DSS_VIDEO1:
  336. case OMAP_DSS_VIDEO2:
  337. return 0x0004;
  338. case OMAP_DSS_VIDEO3:
  339. return 0x000C;
  340. default:
  341. BUG();
  342. return 0;
  343. }
  344. }
  345. static inline u16 DISPC_BA0_UV_OFFSET(enum omap_plane plane)
  346. {
  347. switch (plane) {
  348. case OMAP_DSS_GFX:
  349. BUG();
  350. return 0;
  351. case OMAP_DSS_VIDEO1:
  352. return 0x0544;
  353. case OMAP_DSS_VIDEO2:
  354. return 0x04BC;
  355. case OMAP_DSS_VIDEO3:
  356. return 0x0310;
  357. default:
  358. BUG();
  359. return 0;
  360. }
  361. }
  362. static inline u16 DISPC_BA1_UV_OFFSET(enum omap_plane plane)
  363. {
  364. switch (plane) {
  365. case OMAP_DSS_GFX:
  366. BUG();
  367. return 0;
  368. case OMAP_DSS_VIDEO1:
  369. return 0x0548;
  370. case OMAP_DSS_VIDEO2:
  371. return 0x04C0;
  372. case OMAP_DSS_VIDEO3:
  373. return 0x0314;
  374. default:
  375. BUG();
  376. return 0;
  377. }
  378. }
  379. static inline u16 DISPC_POS_OFFSET(enum omap_plane plane)
  380. {
  381. switch (plane) {
  382. case OMAP_DSS_GFX:
  383. case OMAP_DSS_VIDEO1:
  384. case OMAP_DSS_VIDEO2:
  385. return 0x0008;
  386. case OMAP_DSS_VIDEO3:
  387. return 0x009C;
  388. default:
  389. BUG();
  390. return 0;
  391. }
  392. }
  393. static inline u16 DISPC_SIZE_OFFSET(enum omap_plane plane)
  394. {
  395. switch (plane) {
  396. case OMAP_DSS_GFX:
  397. case OMAP_DSS_VIDEO1:
  398. case OMAP_DSS_VIDEO2:
  399. return 0x000C;
  400. case OMAP_DSS_VIDEO3:
  401. return 0x00A8;
  402. default:
  403. BUG();
  404. return 0;
  405. }
  406. }
  407. static inline u16 DISPC_ATTR_OFFSET(enum omap_plane plane)
  408. {
  409. switch (plane) {
  410. case OMAP_DSS_GFX:
  411. return 0x0020;
  412. case OMAP_DSS_VIDEO1:
  413. case OMAP_DSS_VIDEO2:
  414. return 0x0010;
  415. case OMAP_DSS_VIDEO3:
  416. return 0x0070;
  417. default:
  418. BUG();
  419. return 0;
  420. }
  421. }
  422. static inline u16 DISPC_ATTR2_OFFSET(enum omap_plane plane)
  423. {
  424. switch (plane) {
  425. case OMAP_DSS_GFX:
  426. BUG();
  427. return 0;
  428. case OMAP_DSS_VIDEO1:
  429. return 0x0568;
  430. case OMAP_DSS_VIDEO2:
  431. return 0x04DC;
  432. case OMAP_DSS_VIDEO3:
  433. return 0x032C;
  434. default:
  435. BUG();
  436. return 0;
  437. }
  438. }
  439. static inline u16 DISPC_FIFO_THRESH_OFFSET(enum omap_plane plane)
  440. {
  441. switch (plane) {
  442. case OMAP_DSS_GFX:
  443. return 0x0024;
  444. case OMAP_DSS_VIDEO1:
  445. case OMAP_DSS_VIDEO2:
  446. return 0x0014;
  447. case OMAP_DSS_VIDEO3:
  448. return 0x008C;
  449. default:
  450. BUG();
  451. return 0;
  452. }
  453. }
  454. static inline u16 DISPC_FIFO_SIZE_STATUS_OFFSET(enum omap_plane plane)
  455. {
  456. switch (plane) {
  457. case OMAP_DSS_GFX:
  458. return 0x0028;
  459. case OMAP_DSS_VIDEO1:
  460. case OMAP_DSS_VIDEO2:
  461. return 0x0018;
  462. case OMAP_DSS_VIDEO3:
  463. return 0x0088;
  464. default:
  465. BUG();
  466. return 0;
  467. }
  468. }
  469. static inline u16 DISPC_ROW_INC_OFFSET(enum omap_plane plane)
  470. {
  471. switch (plane) {
  472. case OMAP_DSS_GFX:
  473. return 0x002C;
  474. case OMAP_DSS_VIDEO1:
  475. case OMAP_DSS_VIDEO2:
  476. return 0x001C;
  477. case OMAP_DSS_VIDEO3:
  478. return 0x00A4;
  479. default:
  480. BUG();
  481. return 0;
  482. }
  483. }
  484. static inline u16 DISPC_PIX_INC_OFFSET(enum omap_plane plane)
  485. {
  486. switch (plane) {
  487. case OMAP_DSS_GFX:
  488. return 0x0030;
  489. case OMAP_DSS_VIDEO1:
  490. case OMAP_DSS_VIDEO2:
  491. return 0x0020;
  492. case OMAP_DSS_VIDEO3:
  493. return 0x0098;
  494. default:
  495. BUG();
  496. return 0;
  497. }
  498. }
  499. static inline u16 DISPC_WINDOW_SKIP_OFFSET(enum omap_plane plane)
  500. {
  501. switch (plane) {
  502. case OMAP_DSS_GFX:
  503. return 0x0034;
  504. case OMAP_DSS_VIDEO1:
  505. case OMAP_DSS_VIDEO2:
  506. case OMAP_DSS_VIDEO3:
  507. BUG();
  508. return 0;
  509. default:
  510. BUG();
  511. return 0;
  512. }
  513. }
  514. static inline u16 DISPC_TABLE_BA_OFFSET(enum omap_plane plane)
  515. {
  516. switch (plane) {
  517. case OMAP_DSS_GFX:
  518. return 0x0038;
  519. case OMAP_DSS_VIDEO1:
  520. case OMAP_DSS_VIDEO2:
  521. case OMAP_DSS_VIDEO3:
  522. BUG();
  523. return 0;
  524. default:
  525. BUG();
  526. return 0;
  527. }
  528. }
  529. static inline u16 DISPC_FIR_OFFSET(enum omap_plane plane)
  530. {
  531. switch (plane) {
  532. case OMAP_DSS_GFX:
  533. BUG();
  534. return 0;
  535. case OMAP_DSS_VIDEO1:
  536. case OMAP_DSS_VIDEO2:
  537. return 0x0024;
  538. case OMAP_DSS_VIDEO3:
  539. return 0x0090;
  540. default:
  541. BUG();
  542. return 0;
  543. }
  544. }
  545. static inline u16 DISPC_FIR2_OFFSET(enum omap_plane plane)
  546. {
  547. switch (plane) {
  548. case OMAP_DSS_GFX:
  549. BUG();
  550. return 0;
  551. case OMAP_DSS_VIDEO1:
  552. return 0x0580;
  553. case OMAP_DSS_VIDEO2:
  554. return 0x055C;
  555. case OMAP_DSS_VIDEO3:
  556. return 0x0424;
  557. default:
  558. BUG();
  559. return 0;
  560. }
  561. }
  562. static inline u16 DISPC_PIC_SIZE_OFFSET(enum omap_plane plane)
  563. {
  564. switch (plane) {
  565. case OMAP_DSS_GFX:
  566. BUG();
  567. return 0;
  568. case OMAP_DSS_VIDEO1:
  569. case OMAP_DSS_VIDEO2:
  570. return 0x0028;
  571. case OMAP_DSS_VIDEO3:
  572. return 0x0094;
  573. default:
  574. BUG();
  575. return 0;
  576. }
  577. }
  578. static inline u16 DISPC_ACCU0_OFFSET(enum omap_plane plane)
  579. {
  580. switch (plane) {
  581. case OMAP_DSS_GFX:
  582. BUG();
  583. return 0;
  584. case OMAP_DSS_VIDEO1:
  585. case OMAP_DSS_VIDEO2:
  586. return 0x002C;
  587. case OMAP_DSS_VIDEO3:
  588. return 0x0000;
  589. default:
  590. BUG();
  591. return 0;
  592. }
  593. }
  594. static inline u16 DISPC_ACCU2_0_OFFSET(enum omap_plane plane)
  595. {
  596. switch (plane) {
  597. case OMAP_DSS_GFX:
  598. BUG();
  599. return 0;
  600. case OMAP_DSS_VIDEO1:
  601. return 0x0584;
  602. case OMAP_DSS_VIDEO2:
  603. return 0x0560;
  604. case OMAP_DSS_VIDEO3:
  605. return 0x0428;
  606. default:
  607. BUG();
  608. return 0;
  609. }
  610. }
  611. static inline u16 DISPC_ACCU1_OFFSET(enum omap_plane plane)
  612. {
  613. switch (plane) {
  614. case OMAP_DSS_GFX:
  615. BUG();
  616. return 0;
  617. case OMAP_DSS_VIDEO1:
  618. case OMAP_DSS_VIDEO2:
  619. return 0x0030;
  620. case OMAP_DSS_VIDEO3:
  621. return 0x0004;
  622. default:
  623. BUG();
  624. return 0;
  625. }
  626. }
  627. static inline u16 DISPC_ACCU2_1_OFFSET(enum omap_plane plane)
  628. {
  629. switch (plane) {
  630. case OMAP_DSS_GFX:
  631. BUG();
  632. return 0;
  633. case OMAP_DSS_VIDEO1:
  634. return 0x0588;
  635. case OMAP_DSS_VIDEO2:
  636. return 0x0564;
  637. case OMAP_DSS_VIDEO3:
  638. return 0x042C;
  639. default:
  640. BUG();
  641. return 0;
  642. }
  643. }
  644. /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
  645. static inline u16 DISPC_FIR_COEF_H_OFFSET(enum omap_plane plane, u16 i)
  646. {
  647. switch (plane) {
  648. case OMAP_DSS_GFX:
  649. BUG();
  650. return 0;
  651. case OMAP_DSS_VIDEO1:
  652. case OMAP_DSS_VIDEO2:
  653. return 0x0034 + i * 0x8;
  654. case OMAP_DSS_VIDEO3:
  655. return 0x0010 + i * 0x8;
  656. default:
  657. BUG();
  658. return 0;
  659. }
  660. }
  661. /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
  662. static inline u16 DISPC_FIR_COEF_H2_OFFSET(enum omap_plane plane, u16 i)
  663. {
  664. switch (plane) {
  665. case OMAP_DSS_GFX:
  666. BUG();
  667. return 0;
  668. case OMAP_DSS_VIDEO1:
  669. return 0x058C + i * 0x8;
  670. case OMAP_DSS_VIDEO2:
  671. return 0x0568 + i * 0x8;
  672. case OMAP_DSS_VIDEO3:
  673. return 0x0430 + i * 0x8;
  674. default:
  675. BUG();
  676. return 0;
  677. }
  678. }
  679. /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
  680. static inline u16 DISPC_FIR_COEF_HV_OFFSET(enum omap_plane plane, u16 i)
  681. {
  682. switch (plane) {
  683. case OMAP_DSS_GFX:
  684. BUG();
  685. return 0;
  686. case OMAP_DSS_VIDEO1:
  687. case OMAP_DSS_VIDEO2:
  688. return 0x0038 + i * 0x8;
  689. case OMAP_DSS_VIDEO3:
  690. return 0x0014 + i * 0x8;
  691. default:
  692. BUG();
  693. return 0;
  694. }
  695. }
  696. /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
  697. static inline u16 DISPC_FIR_COEF_HV2_OFFSET(enum omap_plane plane, u16 i)
  698. {
  699. switch (plane) {
  700. case OMAP_DSS_GFX:
  701. BUG();
  702. return 0;
  703. case OMAP_DSS_VIDEO1:
  704. return 0x0590 + i * 8;
  705. case OMAP_DSS_VIDEO2:
  706. return 0x056C + i * 0x8;
  707. case OMAP_DSS_VIDEO3:
  708. return 0x0434 + i * 0x8;
  709. default:
  710. BUG();
  711. return 0;
  712. }
  713. }
  714. /* coef index i = {0, 1, 2, 3, 4,} */
  715. static inline u16 DISPC_CONV_COEF_OFFSET(enum omap_plane plane, u16 i)
  716. {
  717. switch (plane) {
  718. case OMAP_DSS_GFX:
  719. BUG();
  720. return 0;
  721. case OMAP_DSS_VIDEO1:
  722. case OMAP_DSS_VIDEO2:
  723. case OMAP_DSS_VIDEO3:
  724. return 0x0074 + i * 0x4;
  725. default:
  726. BUG();
  727. return 0;
  728. }
  729. }
  730. /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
  731. static inline u16 DISPC_FIR_COEF_V_OFFSET(enum omap_plane plane, u16 i)
  732. {
  733. switch (plane) {
  734. case OMAP_DSS_GFX:
  735. BUG();
  736. return 0;
  737. case OMAP_DSS_VIDEO1:
  738. return 0x0124 + i * 0x4;
  739. case OMAP_DSS_VIDEO2:
  740. return 0x00B4 + i * 0x4;
  741. case OMAP_DSS_VIDEO3:
  742. return 0x0050 + i * 0x4;
  743. default:
  744. BUG();
  745. return 0;
  746. }
  747. }
  748. /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
  749. static inline u16 DISPC_FIR_COEF_V2_OFFSET(enum omap_plane plane, u16 i)
  750. {
  751. switch (plane) {
  752. case OMAP_DSS_GFX:
  753. BUG();
  754. return 0;
  755. case OMAP_DSS_VIDEO1:
  756. return 0x05CC + i * 0x4;
  757. case OMAP_DSS_VIDEO2:
  758. return 0x05A8 + i * 0x4;
  759. case OMAP_DSS_VIDEO3:
  760. return 0x0470 + i * 0x4;
  761. default:
  762. BUG();
  763. return 0;
  764. }
  765. }
  766. static inline u16 DISPC_PRELOAD_OFFSET(enum omap_plane plane)
  767. {
  768. switch (plane) {
  769. case OMAP_DSS_GFX:
  770. return 0x01AC;
  771. case OMAP_DSS_VIDEO1:
  772. return 0x0174;
  773. case OMAP_DSS_VIDEO2:
  774. return 0x00E8;
  775. case OMAP_DSS_VIDEO3:
  776. return 0x00A0;
  777. default:
  778. BUG();
  779. return 0;
  780. }
  781. }
  782. #endif