xhci-hub.c 31 KB

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  1. /*
  2. * xHCI host controller driver
  3. *
  4. * Copyright (C) 2008 Intel Corp.
  5. *
  6. * Author: Sarah Sharp
  7. * Some code borrowed from the Linux EHCI driver.
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License version 2 as
  11. * published by the Free Software Foundation.
  12. *
  13. * This program is distributed in the hope that it will be useful, but
  14. * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15. * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  16. * for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software Foundation,
  20. * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21. */
  22. #include <linux/gfp.h>
  23. #include <asm/unaligned.h>
  24. #include "xhci.h"
  25. #define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
  26. #define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \
  27. PORT_RC | PORT_PLC | PORT_PE)
  28. /* usb 1.1 root hub device descriptor */
  29. static u8 usb_bos_descriptor [] = {
  30. USB_DT_BOS_SIZE, /* __u8 bLength, 5 bytes */
  31. USB_DT_BOS, /* __u8 bDescriptorType */
  32. 0x0F, 0x00, /* __le16 wTotalLength, 15 bytes */
  33. 0x1, /* __u8 bNumDeviceCaps */
  34. /* First device capability */
  35. USB_DT_USB_SS_CAP_SIZE, /* __u8 bLength, 10 bytes */
  36. USB_DT_DEVICE_CAPABILITY, /* Device Capability */
  37. USB_SS_CAP_TYPE, /* bDevCapabilityType, SUPERSPEED_USB */
  38. 0x00, /* bmAttributes, LTM off by default */
  39. USB_5GBPS_OPERATION, 0x00, /* wSpeedsSupported, 5Gbps only */
  40. 0x03, /* bFunctionalitySupport,
  41. USB 3.0 speed only */
  42. 0x00, /* bU1DevExitLat, set later. */
  43. 0x00, 0x00 /* __le16 bU2DevExitLat, set later. */
  44. };
  45. static void xhci_common_hub_descriptor(struct xhci_hcd *xhci,
  46. struct usb_hub_descriptor *desc, int ports)
  47. {
  48. u16 temp;
  49. desc->bPwrOn2PwrGood = 10; /* xhci section 5.4.9 says 20ms max */
  50. desc->bHubContrCurrent = 0;
  51. desc->bNbrPorts = ports;
  52. temp = 0;
  53. /* Bits 1:0 - support per-port power switching, or power always on */
  54. if (HCC_PPC(xhci->hcc_params))
  55. temp |= HUB_CHAR_INDV_PORT_LPSM;
  56. else
  57. temp |= HUB_CHAR_NO_LPSM;
  58. /* Bit 2 - root hubs are not part of a compound device */
  59. /* Bits 4:3 - individual port over current protection */
  60. temp |= HUB_CHAR_INDV_PORT_OCPM;
  61. /* Bits 6:5 - no TTs in root ports */
  62. /* Bit 7 - no port indicators */
  63. desc->wHubCharacteristics = cpu_to_le16(temp);
  64. }
  65. /* Fill in the USB 2.0 roothub descriptor */
  66. static void xhci_usb2_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
  67. struct usb_hub_descriptor *desc)
  68. {
  69. int ports;
  70. u16 temp;
  71. __u8 port_removable[(USB_MAXCHILDREN + 1 + 7) / 8];
  72. u32 portsc;
  73. unsigned int i;
  74. ports = xhci->num_usb2_ports;
  75. xhci_common_hub_descriptor(xhci, desc, ports);
  76. desc->bDescriptorType = USB_DT_HUB;
  77. temp = 1 + (ports / 8);
  78. desc->bDescLength = USB_DT_HUB_NONVAR_SIZE + 2 * temp;
  79. /* The Device Removable bits are reported on a byte granularity.
  80. * If the port doesn't exist within that byte, the bit is set to 0.
  81. */
  82. memset(port_removable, 0, sizeof(port_removable));
  83. for (i = 0; i < ports; i++) {
  84. portsc = xhci_readl(xhci, xhci->usb2_ports[i]);
  85. /* If a device is removable, PORTSC reports a 0, same as in the
  86. * hub descriptor DeviceRemovable bits.
  87. */
  88. if (portsc & PORT_DEV_REMOVE)
  89. /* This math is hairy because bit 0 of DeviceRemovable
  90. * is reserved, and bit 1 is for port 1, etc.
  91. */
  92. port_removable[(i + 1) / 8] |= 1 << ((i + 1) % 8);
  93. }
  94. /* ch11.h defines a hub descriptor that has room for USB_MAXCHILDREN
  95. * ports on it. The USB 2.0 specification says that there are two
  96. * variable length fields at the end of the hub descriptor:
  97. * DeviceRemovable and PortPwrCtrlMask. But since we can have less than
  98. * USB_MAXCHILDREN ports, we may need to use the DeviceRemovable array
  99. * to set PortPwrCtrlMask bits. PortPwrCtrlMask must always be set to
  100. * 0xFF, so we initialize the both arrays (DeviceRemovable and
  101. * PortPwrCtrlMask) to 0xFF. Then we set the DeviceRemovable for each
  102. * set of ports that actually exist.
  103. */
  104. memset(desc->u.hs.DeviceRemovable, 0xff,
  105. sizeof(desc->u.hs.DeviceRemovable));
  106. memset(desc->u.hs.PortPwrCtrlMask, 0xff,
  107. sizeof(desc->u.hs.PortPwrCtrlMask));
  108. for (i = 0; i < (ports + 1 + 7) / 8; i++)
  109. memset(&desc->u.hs.DeviceRemovable[i], port_removable[i],
  110. sizeof(__u8));
  111. }
  112. /* Fill in the USB 3.0 roothub descriptor */
  113. static void xhci_usb3_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
  114. struct usb_hub_descriptor *desc)
  115. {
  116. int ports;
  117. u16 port_removable;
  118. u32 portsc;
  119. unsigned int i;
  120. ports = xhci->num_usb3_ports;
  121. xhci_common_hub_descriptor(xhci, desc, ports);
  122. desc->bDescriptorType = USB_DT_SS_HUB;
  123. desc->bDescLength = USB_DT_SS_HUB_SIZE;
  124. /* header decode latency should be zero for roothubs,
  125. * see section 4.23.5.2.
  126. */
  127. desc->u.ss.bHubHdrDecLat = 0;
  128. desc->u.ss.wHubDelay = 0;
  129. port_removable = 0;
  130. /* bit 0 is reserved, bit 1 is for port 1, etc. */
  131. for (i = 0; i < ports; i++) {
  132. portsc = xhci_readl(xhci, xhci->usb3_ports[i]);
  133. if (portsc & PORT_DEV_REMOVE)
  134. port_removable |= 1 << (i + 1);
  135. }
  136. memset(&desc->u.ss.DeviceRemovable,
  137. (__force __u16) cpu_to_le16(port_removable),
  138. sizeof(__u16));
  139. }
  140. static void xhci_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
  141. struct usb_hub_descriptor *desc)
  142. {
  143. if (hcd->speed == HCD_USB3)
  144. xhci_usb3_hub_descriptor(hcd, xhci, desc);
  145. else
  146. xhci_usb2_hub_descriptor(hcd, xhci, desc);
  147. }
  148. static unsigned int xhci_port_speed(unsigned int port_status)
  149. {
  150. if (DEV_LOWSPEED(port_status))
  151. return USB_PORT_STAT_LOW_SPEED;
  152. if (DEV_HIGHSPEED(port_status))
  153. return USB_PORT_STAT_HIGH_SPEED;
  154. /*
  155. * FIXME: Yes, we should check for full speed, but the core uses that as
  156. * a default in portspeed() in usb/core/hub.c (which is the only place
  157. * USB_PORT_STAT_*_SPEED is used).
  158. */
  159. return 0;
  160. }
  161. /*
  162. * These bits are Read Only (RO) and should be saved and written to the
  163. * registers: 0, 3, 10:13, 30
  164. * connect status, over-current status, port speed, and device removable.
  165. * connect status and port speed are also sticky - meaning they're in
  166. * the AUX well and they aren't changed by a hot, warm, or cold reset.
  167. */
  168. #define XHCI_PORT_RO ((1<<0) | (1<<3) | (0xf<<10) | (1<<30))
  169. /*
  170. * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit:
  171. * bits 5:8, 9, 14:15, 25:27
  172. * link state, port power, port indicator state, "wake on" enable state
  173. */
  174. #define XHCI_PORT_RWS ((0xf<<5) | (1<<9) | (0x3<<14) | (0x7<<25))
  175. /*
  176. * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect:
  177. * bit 4 (port reset)
  178. */
  179. #define XHCI_PORT_RW1S ((1<<4))
  180. /*
  181. * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect:
  182. * bits 1, 17, 18, 19, 20, 21, 22, 23
  183. * port enable/disable, and
  184. * change bits: connect, PED, warm port reset changed (reserved zero for USB 2.0 ports),
  185. * over-current, reset, link state, and L1 change
  186. */
  187. #define XHCI_PORT_RW1CS ((1<<1) | (0x7f<<17))
  188. /*
  189. * Bit 16 is RW, and writing a '1' to it causes the link state control to be
  190. * latched in
  191. */
  192. #define XHCI_PORT_RW ((1<<16))
  193. /*
  194. * These bits are Reserved Zero (RsvdZ) and zero should be written to them:
  195. * bits 2, 24, 28:31
  196. */
  197. #define XHCI_PORT_RZ ((1<<2) | (1<<24) | (0xf<<28))
  198. /*
  199. * Given a port state, this function returns a value that would result in the
  200. * port being in the same state, if the value was written to the port status
  201. * control register.
  202. * Save Read Only (RO) bits and save read/write bits where
  203. * writing a 0 clears the bit and writing a 1 sets the bit (RWS).
  204. * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect.
  205. */
  206. u32 xhci_port_state_to_neutral(u32 state)
  207. {
  208. /* Save read-only status and port state */
  209. return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS);
  210. }
  211. /*
  212. * find slot id based on port number.
  213. * @port: The one-based port number from one of the two split roothubs.
  214. */
  215. int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
  216. u16 port)
  217. {
  218. int slot_id;
  219. int i;
  220. enum usb_device_speed speed;
  221. slot_id = 0;
  222. for (i = 0; i < MAX_HC_SLOTS; i++) {
  223. if (!xhci->devs[i])
  224. continue;
  225. speed = xhci->devs[i]->udev->speed;
  226. if (((speed == USB_SPEED_SUPER) == (hcd->speed == HCD_USB3))
  227. && xhci->devs[i]->fake_port == port) {
  228. slot_id = i;
  229. break;
  230. }
  231. }
  232. return slot_id;
  233. }
  234. /*
  235. * Stop device
  236. * It issues stop endpoint command for EP 0 to 30. And wait the last command
  237. * to complete.
  238. * suspend will set to 1, if suspend bit need to set in command.
  239. */
  240. static int xhci_stop_device(struct xhci_hcd *xhci, int slot_id, int suspend)
  241. {
  242. struct xhci_virt_device *virt_dev;
  243. struct xhci_command *cmd;
  244. unsigned long flags;
  245. int timeleft;
  246. int ret;
  247. int i;
  248. ret = 0;
  249. virt_dev = xhci->devs[slot_id];
  250. cmd = xhci_alloc_command(xhci, false, true, GFP_NOIO);
  251. if (!cmd) {
  252. xhci_dbg(xhci, "Couldn't allocate command structure.\n");
  253. return -ENOMEM;
  254. }
  255. spin_lock_irqsave(&xhci->lock, flags);
  256. for (i = LAST_EP_INDEX; i > 0; i--) {
  257. if (virt_dev->eps[i].ring && virt_dev->eps[i].ring->dequeue)
  258. xhci_queue_stop_endpoint(xhci, slot_id, i, suspend);
  259. }
  260. cmd->command_trb = xhci->cmd_ring->enqueue;
  261. list_add_tail(&cmd->cmd_list, &virt_dev->cmd_list);
  262. xhci_queue_stop_endpoint(xhci, slot_id, 0, suspend);
  263. xhci_ring_cmd_db(xhci);
  264. spin_unlock_irqrestore(&xhci->lock, flags);
  265. /* Wait for last stop endpoint command to finish */
  266. timeleft = wait_for_completion_interruptible_timeout(
  267. cmd->completion,
  268. USB_CTRL_SET_TIMEOUT);
  269. if (timeleft <= 0) {
  270. xhci_warn(xhci, "%s while waiting for stop endpoint command\n",
  271. timeleft == 0 ? "Timeout" : "Signal");
  272. spin_lock_irqsave(&xhci->lock, flags);
  273. /* The timeout might have raced with the event ring handler, so
  274. * only delete from the list if the item isn't poisoned.
  275. */
  276. if (cmd->cmd_list.next != LIST_POISON1)
  277. list_del(&cmd->cmd_list);
  278. spin_unlock_irqrestore(&xhci->lock, flags);
  279. ret = -ETIME;
  280. goto command_cleanup;
  281. }
  282. command_cleanup:
  283. xhci_free_command(xhci, cmd);
  284. return ret;
  285. }
  286. /*
  287. * Ring device, it rings the all doorbells unconditionally.
  288. */
  289. void xhci_ring_device(struct xhci_hcd *xhci, int slot_id)
  290. {
  291. int i;
  292. for (i = 0; i < LAST_EP_INDEX + 1; i++)
  293. if (xhci->devs[slot_id]->eps[i].ring &&
  294. xhci->devs[slot_id]->eps[i].ring->dequeue)
  295. xhci_ring_ep_doorbell(xhci, slot_id, i, 0);
  296. return;
  297. }
  298. static void xhci_disable_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
  299. u16 wIndex, __le32 __iomem *addr, u32 port_status)
  300. {
  301. /* Don't allow the USB core to disable SuperSpeed ports. */
  302. if (hcd->speed == HCD_USB3) {
  303. xhci_dbg(xhci, "Ignoring request to disable "
  304. "SuperSpeed port.\n");
  305. return;
  306. }
  307. /* Write 1 to disable the port */
  308. xhci_writel(xhci, port_status | PORT_PE, addr);
  309. port_status = xhci_readl(xhci, addr);
  310. xhci_dbg(xhci, "disable port, actual port %d status = 0x%x\n",
  311. wIndex, port_status);
  312. }
  313. static void xhci_clear_port_change_bit(struct xhci_hcd *xhci, u16 wValue,
  314. u16 wIndex, __le32 __iomem *addr, u32 port_status)
  315. {
  316. char *port_change_bit;
  317. u32 status;
  318. switch (wValue) {
  319. case USB_PORT_FEAT_C_RESET:
  320. status = PORT_RC;
  321. port_change_bit = "reset";
  322. break;
  323. case USB_PORT_FEAT_C_BH_PORT_RESET:
  324. status = PORT_WRC;
  325. port_change_bit = "warm(BH) reset";
  326. break;
  327. case USB_PORT_FEAT_C_CONNECTION:
  328. status = PORT_CSC;
  329. port_change_bit = "connect";
  330. break;
  331. case USB_PORT_FEAT_C_OVER_CURRENT:
  332. status = PORT_OCC;
  333. port_change_bit = "over-current";
  334. break;
  335. case USB_PORT_FEAT_C_ENABLE:
  336. status = PORT_PEC;
  337. port_change_bit = "enable/disable";
  338. break;
  339. case USB_PORT_FEAT_C_SUSPEND:
  340. status = PORT_PLC;
  341. port_change_bit = "suspend/resume";
  342. break;
  343. case USB_PORT_FEAT_C_PORT_LINK_STATE:
  344. status = PORT_PLC;
  345. port_change_bit = "link state";
  346. break;
  347. default:
  348. /* Should never happen */
  349. return;
  350. }
  351. /* Change bits are all write 1 to clear */
  352. xhci_writel(xhci, port_status | status, addr);
  353. port_status = xhci_readl(xhci, addr);
  354. xhci_dbg(xhci, "clear port %s change, actual port %d status = 0x%x\n",
  355. port_change_bit, wIndex, port_status);
  356. }
  357. static int xhci_get_ports(struct usb_hcd *hcd, __le32 __iomem ***port_array)
  358. {
  359. int max_ports;
  360. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  361. if (hcd->speed == HCD_USB3) {
  362. max_ports = xhci->num_usb3_ports;
  363. *port_array = xhci->usb3_ports;
  364. } else {
  365. max_ports = xhci->num_usb2_ports;
  366. *port_array = xhci->usb2_ports;
  367. }
  368. return max_ports;
  369. }
  370. void xhci_set_link_state(struct xhci_hcd *xhci, __le32 __iomem **port_array,
  371. int port_id, u32 link_state)
  372. {
  373. u32 temp;
  374. temp = xhci_readl(xhci, port_array[port_id]);
  375. temp = xhci_port_state_to_neutral(temp);
  376. temp &= ~PORT_PLS_MASK;
  377. temp |= PORT_LINK_STROBE | link_state;
  378. xhci_writel(xhci, temp, port_array[port_id]);
  379. }
  380. void xhci_set_remote_wake_mask(struct xhci_hcd *xhci,
  381. __le32 __iomem **port_array, int port_id, u16 wake_mask)
  382. {
  383. u32 temp;
  384. temp = xhci_readl(xhci, port_array[port_id]);
  385. temp = xhci_port_state_to_neutral(temp);
  386. if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_CONNECT)
  387. temp |= PORT_WKCONN_E;
  388. else
  389. temp &= ~PORT_WKCONN_E;
  390. if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_DISCONNECT)
  391. temp |= PORT_WKDISC_E;
  392. else
  393. temp &= ~PORT_WKDISC_E;
  394. if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_OVER_CURRENT)
  395. temp |= PORT_WKOC_E;
  396. else
  397. temp &= ~PORT_WKOC_E;
  398. xhci_writel(xhci, temp, port_array[port_id]);
  399. }
  400. /* Test and clear port RWC bit */
  401. void xhci_test_and_clear_bit(struct xhci_hcd *xhci, __le32 __iomem **port_array,
  402. int port_id, u32 port_bit)
  403. {
  404. u32 temp;
  405. temp = xhci_readl(xhci, port_array[port_id]);
  406. if (temp & port_bit) {
  407. temp = xhci_port_state_to_neutral(temp);
  408. temp |= port_bit;
  409. xhci_writel(xhci, temp, port_array[port_id]);
  410. }
  411. }
  412. int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
  413. u16 wIndex, char *buf, u16 wLength)
  414. {
  415. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  416. int max_ports;
  417. unsigned long flags;
  418. u32 temp, status;
  419. int retval = 0;
  420. __le32 __iomem **port_array;
  421. int slot_id;
  422. struct xhci_bus_state *bus_state;
  423. u16 link_state = 0;
  424. u16 wake_mask = 0;
  425. u16 timeout = 0;
  426. max_ports = xhci_get_ports(hcd, &port_array);
  427. bus_state = &xhci->bus_state[hcd_index(hcd)];
  428. spin_lock_irqsave(&xhci->lock, flags);
  429. switch (typeReq) {
  430. case GetHubStatus:
  431. /* No power source, over-current reported per port */
  432. memset(buf, 0, 4);
  433. break;
  434. case GetHubDescriptor:
  435. /* Check to make sure userspace is asking for the USB 3.0 hub
  436. * descriptor for the USB 3.0 roothub. If not, we stall the
  437. * endpoint, like external hubs do.
  438. */
  439. if (hcd->speed == HCD_USB3 &&
  440. (wLength < USB_DT_SS_HUB_SIZE ||
  441. wValue != (USB_DT_SS_HUB << 8))) {
  442. xhci_dbg(xhci, "Wrong hub descriptor type for "
  443. "USB 3.0 roothub.\n");
  444. goto error;
  445. }
  446. xhci_hub_descriptor(hcd, xhci,
  447. (struct usb_hub_descriptor *) buf);
  448. break;
  449. case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
  450. if ((wValue & 0xff00) != (USB_DT_BOS << 8))
  451. goto error;
  452. if (hcd->speed != HCD_USB3)
  453. goto error;
  454. memcpy(buf, &usb_bos_descriptor,
  455. USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE);
  456. temp = xhci_readl(xhci, &xhci->cap_regs->hcs_params3);
  457. buf[12] = HCS_U1_LATENCY(temp);
  458. put_unaligned_le16(HCS_U2_LATENCY(temp), &buf[13]);
  459. spin_unlock_irqrestore(&xhci->lock, flags);
  460. return USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE;
  461. case GetPortStatus:
  462. if (!wIndex || wIndex > max_ports)
  463. goto error;
  464. wIndex--;
  465. status = 0;
  466. temp = xhci_readl(xhci, port_array[wIndex]);
  467. if (temp == 0xffffffff) {
  468. retval = -ENODEV;
  469. break;
  470. }
  471. xhci_dbg(xhci, "get port status, actual port %d status = 0x%x\n", wIndex, temp);
  472. /* wPortChange bits */
  473. if (temp & PORT_CSC)
  474. status |= USB_PORT_STAT_C_CONNECTION << 16;
  475. if (temp & PORT_PEC)
  476. status |= USB_PORT_STAT_C_ENABLE << 16;
  477. if ((temp & PORT_OCC))
  478. status |= USB_PORT_STAT_C_OVERCURRENT << 16;
  479. if ((temp & PORT_RC))
  480. status |= USB_PORT_STAT_C_RESET << 16;
  481. /* USB3.0 only */
  482. if (hcd->speed == HCD_USB3) {
  483. if ((temp & PORT_PLC))
  484. status |= USB_PORT_STAT_C_LINK_STATE << 16;
  485. if ((temp & PORT_WRC))
  486. status |= USB_PORT_STAT_C_BH_RESET << 16;
  487. }
  488. if (hcd->speed != HCD_USB3) {
  489. if ((temp & PORT_PLS_MASK) == XDEV_U3
  490. && (temp & PORT_POWER))
  491. status |= USB_PORT_STAT_SUSPEND;
  492. }
  493. if ((temp & PORT_PLS_MASK) == XDEV_RESUME &&
  494. !DEV_SUPERSPEED(temp)) {
  495. if ((temp & PORT_RESET) || !(temp & PORT_PE))
  496. goto error;
  497. if (time_after_eq(jiffies,
  498. bus_state->resume_done[wIndex])) {
  499. xhci_dbg(xhci, "Resume USB2 port %d\n",
  500. wIndex + 1);
  501. bus_state->resume_done[wIndex] = 0;
  502. clear_bit(wIndex, &bus_state->resuming_ports);
  503. xhci_set_link_state(xhci, port_array, wIndex,
  504. XDEV_U0);
  505. xhci_dbg(xhci, "set port %d resume\n",
  506. wIndex + 1);
  507. slot_id = xhci_find_slot_id_by_port(hcd, xhci,
  508. wIndex + 1);
  509. if (!slot_id) {
  510. xhci_dbg(xhci, "slot_id is zero\n");
  511. goto error;
  512. }
  513. xhci_ring_device(xhci, slot_id);
  514. bus_state->port_c_suspend |= 1 << wIndex;
  515. bus_state->suspended_ports &= ~(1 << wIndex);
  516. } else {
  517. /*
  518. * The resume has been signaling for less than
  519. * 20ms. Report the port status as SUSPEND,
  520. * let the usbcore check port status again
  521. * and clear resume signaling later.
  522. */
  523. status |= USB_PORT_STAT_SUSPEND;
  524. }
  525. }
  526. if ((temp & PORT_PLS_MASK) == XDEV_U0
  527. && (temp & PORT_POWER)
  528. && (bus_state->suspended_ports & (1 << wIndex))) {
  529. bus_state->suspended_ports &= ~(1 << wIndex);
  530. if (hcd->speed != HCD_USB3)
  531. bus_state->port_c_suspend |= 1 << wIndex;
  532. }
  533. if (temp & PORT_CONNECT) {
  534. status |= USB_PORT_STAT_CONNECTION;
  535. status |= xhci_port_speed(temp);
  536. }
  537. if (temp & PORT_PE)
  538. status |= USB_PORT_STAT_ENABLE;
  539. if (temp & PORT_OC)
  540. status |= USB_PORT_STAT_OVERCURRENT;
  541. if (temp & PORT_RESET)
  542. status |= USB_PORT_STAT_RESET;
  543. if (temp & PORT_POWER) {
  544. if (hcd->speed == HCD_USB3)
  545. status |= USB_SS_PORT_STAT_POWER;
  546. else
  547. status |= USB_PORT_STAT_POWER;
  548. }
  549. /* Port Link State */
  550. if (hcd->speed == HCD_USB3) {
  551. /* resume state is a xHCI internal state.
  552. * Do not report it to usb core.
  553. */
  554. if ((temp & PORT_PLS_MASK) != XDEV_RESUME)
  555. status |= (temp & PORT_PLS_MASK);
  556. }
  557. if (bus_state->port_c_suspend & (1 << wIndex))
  558. status |= 1 << USB_PORT_FEAT_C_SUSPEND;
  559. xhci_dbg(xhci, "Get port status returned 0x%x\n", status);
  560. put_unaligned(cpu_to_le32(status), (__le32 *) buf);
  561. break;
  562. case SetPortFeature:
  563. if (wValue == USB_PORT_FEAT_LINK_STATE)
  564. link_state = (wIndex & 0xff00) >> 3;
  565. if (wValue == USB_PORT_FEAT_REMOTE_WAKE_MASK)
  566. wake_mask = wIndex & 0xff00;
  567. /* The MSB of wIndex is the U1/U2 timeout */
  568. timeout = (wIndex & 0xff00) >> 8;
  569. wIndex &= 0xff;
  570. if (!wIndex || wIndex > max_ports)
  571. goto error;
  572. wIndex--;
  573. temp = xhci_readl(xhci, port_array[wIndex]);
  574. if (temp == 0xffffffff) {
  575. retval = -ENODEV;
  576. break;
  577. }
  578. temp = xhci_port_state_to_neutral(temp);
  579. /* FIXME: What new port features do we need to support? */
  580. switch (wValue) {
  581. case USB_PORT_FEAT_SUSPEND:
  582. temp = xhci_readl(xhci, port_array[wIndex]);
  583. if ((temp & PORT_PLS_MASK) != XDEV_U0) {
  584. /* Resume the port to U0 first */
  585. xhci_set_link_state(xhci, port_array, wIndex,
  586. XDEV_U0);
  587. spin_unlock_irqrestore(&xhci->lock, flags);
  588. msleep(10);
  589. spin_lock_irqsave(&xhci->lock, flags);
  590. }
  591. /* In spec software should not attempt to suspend
  592. * a port unless the port reports that it is in the
  593. * enabled (PED = ‘1’,PLS < ‘3’) state.
  594. */
  595. temp = xhci_readl(xhci, port_array[wIndex]);
  596. if ((temp & PORT_PE) == 0 || (temp & PORT_RESET)
  597. || (temp & PORT_PLS_MASK) >= XDEV_U3) {
  598. xhci_warn(xhci, "USB core suspending device "
  599. "not in U0/U1/U2.\n");
  600. goto error;
  601. }
  602. slot_id = xhci_find_slot_id_by_port(hcd, xhci,
  603. wIndex + 1);
  604. if (!slot_id) {
  605. xhci_warn(xhci, "slot_id is zero\n");
  606. goto error;
  607. }
  608. /* unlock to execute stop endpoint commands */
  609. spin_unlock_irqrestore(&xhci->lock, flags);
  610. xhci_stop_device(xhci, slot_id, 1);
  611. spin_lock_irqsave(&xhci->lock, flags);
  612. xhci_set_link_state(xhci, port_array, wIndex, XDEV_U3);
  613. spin_unlock_irqrestore(&xhci->lock, flags);
  614. msleep(10); /* wait device to enter */
  615. spin_lock_irqsave(&xhci->lock, flags);
  616. temp = xhci_readl(xhci, port_array[wIndex]);
  617. bus_state->suspended_ports |= 1 << wIndex;
  618. break;
  619. case USB_PORT_FEAT_LINK_STATE:
  620. temp = xhci_readl(xhci, port_array[wIndex]);
  621. /* Software should not attempt to set
  622. * port link state above '5' (Rx.Detect) and the port
  623. * must be enabled.
  624. */
  625. if ((temp & PORT_PE) == 0 ||
  626. (link_state > USB_SS_PORT_LS_RX_DETECT)) {
  627. xhci_warn(xhci, "Cannot set link state.\n");
  628. goto error;
  629. }
  630. if (link_state == USB_SS_PORT_LS_U3) {
  631. slot_id = xhci_find_slot_id_by_port(hcd, xhci,
  632. wIndex + 1);
  633. if (slot_id) {
  634. /* unlock to execute stop endpoint
  635. * commands */
  636. spin_unlock_irqrestore(&xhci->lock,
  637. flags);
  638. xhci_stop_device(xhci, slot_id, 1);
  639. spin_lock_irqsave(&xhci->lock, flags);
  640. }
  641. }
  642. xhci_set_link_state(xhci, port_array, wIndex,
  643. link_state);
  644. spin_unlock_irqrestore(&xhci->lock, flags);
  645. msleep(20); /* wait device to enter */
  646. spin_lock_irqsave(&xhci->lock, flags);
  647. temp = xhci_readl(xhci, port_array[wIndex]);
  648. if (link_state == USB_SS_PORT_LS_U3)
  649. bus_state->suspended_ports |= 1 << wIndex;
  650. break;
  651. case USB_PORT_FEAT_POWER:
  652. /*
  653. * Turn on ports, even if there isn't per-port switching.
  654. * HC will report connect events even before this is set.
  655. * However, khubd will ignore the roothub events until
  656. * the roothub is registered.
  657. */
  658. xhci_writel(xhci, temp | PORT_POWER,
  659. port_array[wIndex]);
  660. temp = xhci_readl(xhci, port_array[wIndex]);
  661. xhci_dbg(xhci, "set port power, actual port %d status = 0x%x\n", wIndex, temp);
  662. break;
  663. case USB_PORT_FEAT_RESET:
  664. temp = (temp | PORT_RESET);
  665. xhci_writel(xhci, temp, port_array[wIndex]);
  666. temp = xhci_readl(xhci, port_array[wIndex]);
  667. xhci_dbg(xhci, "set port reset, actual port %d status = 0x%x\n", wIndex, temp);
  668. break;
  669. case USB_PORT_FEAT_REMOTE_WAKE_MASK:
  670. xhci_set_remote_wake_mask(xhci, port_array,
  671. wIndex, wake_mask);
  672. temp = xhci_readl(xhci, port_array[wIndex]);
  673. xhci_dbg(xhci, "set port remote wake mask, "
  674. "actual port %d status = 0x%x\n",
  675. wIndex, temp);
  676. break;
  677. case USB_PORT_FEAT_BH_PORT_RESET:
  678. temp |= PORT_WR;
  679. xhci_writel(xhci, temp, port_array[wIndex]);
  680. temp = xhci_readl(xhci, port_array[wIndex]);
  681. break;
  682. case USB_PORT_FEAT_U1_TIMEOUT:
  683. if (hcd->speed != HCD_USB3)
  684. goto error;
  685. temp = xhci_readl(xhci, port_array[wIndex] + 1);
  686. temp &= ~PORT_U1_TIMEOUT_MASK;
  687. temp |= PORT_U1_TIMEOUT(timeout);
  688. xhci_writel(xhci, temp, port_array[wIndex] + 1);
  689. break;
  690. case USB_PORT_FEAT_U2_TIMEOUT:
  691. if (hcd->speed != HCD_USB3)
  692. goto error;
  693. temp = xhci_readl(xhci, port_array[wIndex] + 1);
  694. temp &= ~PORT_U2_TIMEOUT_MASK;
  695. temp |= PORT_U2_TIMEOUT(timeout);
  696. xhci_writel(xhci, temp, port_array[wIndex] + 1);
  697. break;
  698. default:
  699. goto error;
  700. }
  701. /* unblock any posted writes */
  702. temp = xhci_readl(xhci, port_array[wIndex]);
  703. break;
  704. case ClearPortFeature:
  705. if (!wIndex || wIndex > max_ports)
  706. goto error;
  707. wIndex--;
  708. temp = xhci_readl(xhci, port_array[wIndex]);
  709. if (temp == 0xffffffff) {
  710. retval = -ENODEV;
  711. break;
  712. }
  713. /* FIXME: What new port features do we need to support? */
  714. temp = xhci_port_state_to_neutral(temp);
  715. switch (wValue) {
  716. case USB_PORT_FEAT_SUSPEND:
  717. temp = xhci_readl(xhci, port_array[wIndex]);
  718. xhci_dbg(xhci, "clear USB_PORT_FEAT_SUSPEND\n");
  719. xhci_dbg(xhci, "PORTSC %04x\n", temp);
  720. if (temp & PORT_RESET)
  721. goto error;
  722. if ((temp & PORT_PLS_MASK) == XDEV_U3) {
  723. if ((temp & PORT_PE) == 0)
  724. goto error;
  725. xhci_set_link_state(xhci, port_array, wIndex,
  726. XDEV_RESUME);
  727. spin_unlock_irqrestore(&xhci->lock, flags);
  728. msleep(20);
  729. spin_lock_irqsave(&xhci->lock, flags);
  730. xhci_set_link_state(xhci, port_array, wIndex,
  731. XDEV_U0);
  732. }
  733. bus_state->port_c_suspend |= 1 << wIndex;
  734. slot_id = xhci_find_slot_id_by_port(hcd, xhci,
  735. wIndex + 1);
  736. if (!slot_id) {
  737. xhci_dbg(xhci, "slot_id is zero\n");
  738. goto error;
  739. }
  740. xhci_ring_device(xhci, slot_id);
  741. break;
  742. case USB_PORT_FEAT_C_SUSPEND:
  743. bus_state->port_c_suspend &= ~(1 << wIndex);
  744. case USB_PORT_FEAT_C_RESET:
  745. case USB_PORT_FEAT_C_BH_PORT_RESET:
  746. case USB_PORT_FEAT_C_CONNECTION:
  747. case USB_PORT_FEAT_C_OVER_CURRENT:
  748. case USB_PORT_FEAT_C_ENABLE:
  749. case USB_PORT_FEAT_C_PORT_LINK_STATE:
  750. xhci_clear_port_change_bit(xhci, wValue, wIndex,
  751. port_array[wIndex], temp);
  752. break;
  753. case USB_PORT_FEAT_ENABLE:
  754. xhci_disable_port(hcd, xhci, wIndex,
  755. port_array[wIndex], temp);
  756. break;
  757. default:
  758. goto error;
  759. }
  760. break;
  761. default:
  762. error:
  763. /* "stall" on error */
  764. retval = -EPIPE;
  765. }
  766. spin_unlock_irqrestore(&xhci->lock, flags);
  767. return retval;
  768. }
  769. /*
  770. * Returns 0 if the status hasn't changed, or the number of bytes in buf.
  771. * Ports are 0-indexed from the HCD point of view,
  772. * and 1-indexed from the USB core pointer of view.
  773. *
  774. * Note that the status change bits will be cleared as soon as a port status
  775. * change event is generated, so we use the saved status from that event.
  776. */
  777. int xhci_hub_status_data(struct usb_hcd *hcd, char *buf)
  778. {
  779. unsigned long flags;
  780. u32 temp, status;
  781. u32 mask;
  782. int i, retval;
  783. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  784. int max_ports;
  785. __le32 __iomem **port_array;
  786. struct xhci_bus_state *bus_state;
  787. max_ports = xhci_get_ports(hcd, &port_array);
  788. bus_state = &xhci->bus_state[hcd_index(hcd)];
  789. /* Initial status is no changes */
  790. retval = (max_ports + 8) / 8;
  791. memset(buf, 0, retval);
  792. /*
  793. * Inform the usbcore about resume-in-progress by returning
  794. * a non-zero value even if there are no status changes.
  795. */
  796. status = bus_state->resuming_ports;
  797. mask = PORT_CSC | PORT_PEC | PORT_OCC | PORT_PLC | PORT_WRC;
  798. spin_lock_irqsave(&xhci->lock, flags);
  799. /* For each port, did anything change? If so, set that bit in buf. */
  800. for (i = 0; i < max_ports; i++) {
  801. temp = xhci_readl(xhci, port_array[i]);
  802. if (temp == 0xffffffff) {
  803. retval = -ENODEV;
  804. break;
  805. }
  806. if ((temp & mask) != 0 ||
  807. (bus_state->port_c_suspend & 1 << i) ||
  808. (bus_state->resume_done[i] && time_after_eq(
  809. jiffies, bus_state->resume_done[i]))) {
  810. buf[(i + 1) / 8] |= 1 << (i + 1) % 8;
  811. status = 1;
  812. }
  813. }
  814. spin_unlock_irqrestore(&xhci->lock, flags);
  815. return status ? retval : 0;
  816. }
  817. #ifdef CONFIG_PM
  818. int xhci_bus_suspend(struct usb_hcd *hcd)
  819. {
  820. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  821. int max_ports, port_index;
  822. __le32 __iomem **port_array;
  823. struct xhci_bus_state *bus_state;
  824. unsigned long flags;
  825. max_ports = xhci_get_ports(hcd, &port_array);
  826. bus_state = &xhci->bus_state[hcd_index(hcd)];
  827. spin_lock_irqsave(&xhci->lock, flags);
  828. if (hcd->self.root_hub->do_remote_wakeup) {
  829. if (bus_state->resuming_ports) {
  830. spin_unlock_irqrestore(&xhci->lock, flags);
  831. xhci_dbg(xhci, "suspend failed because "
  832. "a port is resuming\n");
  833. return -EBUSY;
  834. }
  835. }
  836. port_index = max_ports;
  837. bus_state->bus_suspended = 0;
  838. while (port_index--) {
  839. /* suspend the port if the port is not suspended */
  840. u32 t1, t2;
  841. int slot_id;
  842. t1 = xhci_readl(xhci, port_array[port_index]);
  843. t2 = xhci_port_state_to_neutral(t1);
  844. if ((t1 & PORT_PE) && !(t1 & PORT_PLS_MASK)) {
  845. xhci_dbg(xhci, "port %d not suspended\n", port_index);
  846. slot_id = xhci_find_slot_id_by_port(hcd, xhci,
  847. port_index + 1);
  848. if (slot_id) {
  849. spin_unlock_irqrestore(&xhci->lock, flags);
  850. xhci_stop_device(xhci, slot_id, 1);
  851. spin_lock_irqsave(&xhci->lock, flags);
  852. }
  853. t2 &= ~PORT_PLS_MASK;
  854. t2 |= PORT_LINK_STROBE | XDEV_U3;
  855. set_bit(port_index, &bus_state->bus_suspended);
  856. }
  857. /* USB core sets remote wake mask for USB 3.0 hubs,
  858. * including the USB 3.0 roothub, but only if CONFIG_USB_SUSPEND
  859. * is enabled, so also enable remote wake here.
  860. */
  861. if (hcd->self.root_hub->do_remote_wakeup) {
  862. if (t1 & PORT_CONNECT) {
  863. t2 |= PORT_WKOC_E | PORT_WKDISC_E;
  864. t2 &= ~PORT_WKCONN_E;
  865. } else {
  866. t2 |= PORT_WKOC_E | PORT_WKCONN_E;
  867. t2 &= ~PORT_WKDISC_E;
  868. }
  869. } else
  870. t2 &= ~PORT_WAKE_BITS;
  871. t1 = xhci_port_state_to_neutral(t1);
  872. if (t1 != t2)
  873. xhci_writel(xhci, t2, port_array[port_index]);
  874. if (hcd->speed != HCD_USB3) {
  875. /* enable remote wake up for USB 2.0 */
  876. __le32 __iomem *addr;
  877. u32 tmp;
  878. /* Add one to the port status register address to get
  879. * the port power control register address.
  880. */
  881. addr = port_array[port_index] + 1;
  882. tmp = xhci_readl(xhci, addr);
  883. tmp |= PORT_RWE;
  884. xhci_writel(xhci, tmp, addr);
  885. }
  886. }
  887. hcd->state = HC_STATE_SUSPENDED;
  888. bus_state->next_statechange = jiffies + msecs_to_jiffies(10);
  889. spin_unlock_irqrestore(&xhci->lock, flags);
  890. return 0;
  891. }
  892. int xhci_bus_resume(struct usb_hcd *hcd)
  893. {
  894. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  895. int max_ports, port_index;
  896. __le32 __iomem **port_array;
  897. struct xhci_bus_state *bus_state;
  898. u32 temp;
  899. unsigned long flags;
  900. max_ports = xhci_get_ports(hcd, &port_array);
  901. bus_state = &xhci->bus_state[hcd_index(hcd)];
  902. if (time_before(jiffies, bus_state->next_statechange))
  903. msleep(5);
  904. spin_lock_irqsave(&xhci->lock, flags);
  905. if (!HCD_HW_ACCESSIBLE(hcd)) {
  906. spin_unlock_irqrestore(&xhci->lock, flags);
  907. return -ESHUTDOWN;
  908. }
  909. /* delay the irqs */
  910. temp = xhci_readl(xhci, &xhci->op_regs->command);
  911. temp &= ~CMD_EIE;
  912. xhci_writel(xhci, temp, &xhci->op_regs->command);
  913. port_index = max_ports;
  914. while (port_index--) {
  915. /* Check whether need resume ports. If needed
  916. resume port and disable remote wakeup */
  917. u32 temp;
  918. int slot_id;
  919. temp = xhci_readl(xhci, port_array[port_index]);
  920. if (DEV_SUPERSPEED(temp))
  921. temp &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
  922. else
  923. temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS);
  924. if (test_bit(port_index, &bus_state->bus_suspended) &&
  925. (temp & PORT_PLS_MASK)) {
  926. if (DEV_SUPERSPEED(temp)) {
  927. xhci_set_link_state(xhci, port_array,
  928. port_index, XDEV_U0);
  929. } else {
  930. xhci_set_link_state(xhci, port_array,
  931. port_index, XDEV_RESUME);
  932. spin_unlock_irqrestore(&xhci->lock, flags);
  933. msleep(20);
  934. spin_lock_irqsave(&xhci->lock, flags);
  935. xhci_set_link_state(xhci, port_array,
  936. port_index, XDEV_U0);
  937. }
  938. /* wait for the port to enter U0 and report port link
  939. * state change.
  940. */
  941. spin_unlock_irqrestore(&xhci->lock, flags);
  942. msleep(20);
  943. spin_lock_irqsave(&xhci->lock, flags);
  944. /* Clear PLC */
  945. xhci_test_and_clear_bit(xhci, port_array, port_index,
  946. PORT_PLC);
  947. slot_id = xhci_find_slot_id_by_port(hcd,
  948. xhci, port_index + 1);
  949. if (slot_id)
  950. xhci_ring_device(xhci, slot_id);
  951. } else
  952. xhci_writel(xhci, temp, port_array[port_index]);
  953. if (hcd->speed != HCD_USB3) {
  954. /* disable remote wake up for USB 2.0 */
  955. __le32 __iomem *addr;
  956. u32 tmp;
  957. /* Add one to the port status register address to get
  958. * the port power control register address.
  959. */
  960. addr = port_array[port_index] + 1;
  961. tmp = xhci_readl(xhci, addr);
  962. tmp &= ~PORT_RWE;
  963. xhci_writel(xhci, tmp, addr);
  964. }
  965. }
  966. (void) xhci_readl(xhci, &xhci->op_regs->command);
  967. bus_state->next_statechange = jiffies + msecs_to_jiffies(5);
  968. /* re-enable irqs */
  969. temp = xhci_readl(xhci, &xhci->op_regs->command);
  970. temp |= CMD_EIE;
  971. xhci_writel(xhci, temp, &xhci->op_regs->command);
  972. temp = xhci_readl(xhci, &xhci->op_regs->command);
  973. spin_unlock_irqrestore(&xhci->lock, flags);
  974. return 0;
  975. }
  976. #endif /* CONFIG_PM */