ohci-nxp.c 12 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455
  1. /*
  2. * driver for NXP USB Host devices
  3. *
  4. * Currently supported OHCI host devices:
  5. * - Philips PNX4008
  6. * - NXP LPC32xx
  7. *
  8. * Authors: Dmitry Chigirev <source@mvista.com>
  9. * Vitaly Wool <vitalywool@gmail.com>
  10. *
  11. * register initialization is based on code examples provided by Philips
  12. * Copyright (c) 2005 Koninklijke Philips Electronics N.V.
  13. *
  14. * NOTE: This driver does not have suspend/resume functionality
  15. * This driver is intended for engineering development purposes only
  16. *
  17. * 2005-2006 (c) MontaVista Software, Inc. This file is licensed under
  18. * the terms of the GNU General Public License version 2. This program
  19. * is licensed "as is" without any warranty of any kind, whether express
  20. * or implied.
  21. */
  22. #include <linux/clk.h>
  23. #include <linux/platform_device.h>
  24. #include <linux/i2c.h>
  25. #include <linux/of.h>
  26. #include <linux/usb/isp1301.h>
  27. #include <mach/hardware.h>
  28. #include <asm/mach-types.h>
  29. #include <asm/io.h>
  30. #include <mach/platform.h>
  31. #include <mach/irqs.h>
  32. #define USB_CONFIG_BASE 0x31020000
  33. #define PWRMAN_BASE 0x40004000
  34. #define USB_CTRL IO_ADDRESS(PWRMAN_BASE + 0x64)
  35. /* USB_CTRL bit defines */
  36. #define USB_SLAVE_HCLK_EN (1 << 24)
  37. #define USB_DEV_NEED_CLK_EN (1 << 22)
  38. #define USB_HOST_NEED_CLK_EN (1 << 21)
  39. #define PAD_CONTROL_LAST_DRIVEN (1 << 19)
  40. #define USB_OTG_CLK_CTRL IO_ADDRESS(USB_CONFIG_BASE + 0xFF4)
  41. #define USB_OTG_CLK_STAT IO_ADDRESS(USB_CONFIG_BASE + 0xFF8)
  42. /* USB_OTG_CLK_CTRL bit defines */
  43. #define AHB_M_CLOCK_ON (1 << 4)
  44. #define OTG_CLOCK_ON (1 << 3)
  45. #define I2C_CLOCK_ON (1 << 2)
  46. #define DEV_CLOCK_ON (1 << 1)
  47. #define HOST_CLOCK_ON (1 << 0)
  48. #define USB_OTG_STAT_CONTROL IO_ADDRESS(USB_CONFIG_BASE + 0x110)
  49. /* USB_OTG_STAT_CONTROL bit defines */
  50. #define TRANSPARENT_I2C_EN (1 << 7)
  51. #define HOST_EN (1 << 0)
  52. /* On LPC32xx, those are undefined */
  53. #ifndef start_int_set_falling_edge
  54. #define start_int_set_falling_edge(irq)
  55. #define start_int_set_rising_edge(irq)
  56. #define start_int_ack(irq)
  57. #define start_int_mask(irq)
  58. #define start_int_umask(irq)
  59. #endif
  60. static struct i2c_client *isp1301_i2c_client;
  61. extern int usb_disabled(void);
  62. static struct clk *usb_clk;
  63. static void isp1301_configure_pnx4008(void)
  64. {
  65. /* PNX4008 only supports DAT_SE0 USB mode */
  66. /* PNX4008 R2A requires setting the MAX603 to output 3.6V */
  67. /* Power up externel charge-pump */
  68. i2c_smbus_write_byte_data(isp1301_i2c_client,
  69. ISP1301_I2C_MODE_CONTROL_1, MC1_DAT_SE0 | MC1_SPEED_REG);
  70. i2c_smbus_write_byte_data(isp1301_i2c_client,
  71. ISP1301_I2C_MODE_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR,
  72. ~(MC1_DAT_SE0 | MC1_SPEED_REG));
  73. i2c_smbus_write_byte_data(isp1301_i2c_client,
  74. ISP1301_I2C_MODE_CONTROL_2,
  75. MC2_BI_DI | MC2_PSW_EN | MC2_SPD_SUSP_CTRL);
  76. i2c_smbus_write_byte_data(isp1301_i2c_client,
  77. ISP1301_I2C_MODE_CONTROL_2 | ISP1301_I2C_REG_CLEAR_ADDR,
  78. ~(MC2_BI_DI | MC2_PSW_EN | MC2_SPD_SUSP_CTRL));
  79. i2c_smbus_write_byte_data(isp1301_i2c_client,
  80. ISP1301_I2C_OTG_CONTROL_1, OTG1_DM_PULLDOWN | OTG1_DP_PULLDOWN);
  81. i2c_smbus_write_byte_data(isp1301_i2c_client,
  82. ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR,
  83. ~(OTG1_DM_PULLDOWN | OTG1_DP_PULLDOWN));
  84. i2c_smbus_write_byte_data(isp1301_i2c_client,
  85. ISP1301_I2C_INTERRUPT_LATCH | ISP1301_I2C_REG_CLEAR_ADDR, 0xFF);
  86. i2c_smbus_write_byte_data(isp1301_i2c_client,
  87. ISP1301_I2C_INTERRUPT_FALLING | ISP1301_I2C_REG_CLEAR_ADDR,
  88. 0xFF);
  89. i2c_smbus_write_byte_data(isp1301_i2c_client,
  90. ISP1301_I2C_INTERRUPT_RISING | ISP1301_I2C_REG_CLEAR_ADDR,
  91. 0xFF);
  92. }
  93. static void isp1301_configure_lpc32xx(void)
  94. {
  95. /* LPC32XX only supports DAT_SE0 USB mode */
  96. /* This sequence is important */
  97. /* Disable transparent UART mode first */
  98. i2c_smbus_write_byte_data(isp1301_i2c_client,
  99. (ISP1301_I2C_MODE_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR),
  100. MC1_UART_EN);
  101. i2c_smbus_write_byte_data(isp1301_i2c_client,
  102. (ISP1301_I2C_MODE_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR),
  103. ~MC1_SPEED_REG);
  104. i2c_smbus_write_byte_data(isp1301_i2c_client,
  105. ISP1301_I2C_MODE_CONTROL_1, MC1_SPEED_REG);
  106. i2c_smbus_write_byte_data(isp1301_i2c_client,
  107. (ISP1301_I2C_MODE_CONTROL_2 | ISP1301_I2C_REG_CLEAR_ADDR),
  108. ~0);
  109. i2c_smbus_write_byte_data(isp1301_i2c_client,
  110. ISP1301_I2C_MODE_CONTROL_2,
  111. (MC2_BI_DI | MC2_PSW_EN | MC2_SPD_SUSP_CTRL));
  112. i2c_smbus_write_byte_data(isp1301_i2c_client,
  113. (ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR), ~0);
  114. i2c_smbus_write_byte_data(isp1301_i2c_client,
  115. ISP1301_I2C_MODE_CONTROL_1, MC1_DAT_SE0);
  116. i2c_smbus_write_byte_data(isp1301_i2c_client,
  117. ISP1301_I2C_OTG_CONTROL_1,
  118. (OTG1_DM_PULLDOWN | OTG1_DP_PULLDOWN));
  119. i2c_smbus_write_byte_data(isp1301_i2c_client,
  120. (ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR),
  121. (OTG1_DM_PULLUP | OTG1_DP_PULLUP));
  122. i2c_smbus_write_byte_data(isp1301_i2c_client,
  123. ISP1301_I2C_INTERRUPT_LATCH | ISP1301_I2C_REG_CLEAR_ADDR, ~0);
  124. i2c_smbus_write_byte_data(isp1301_i2c_client,
  125. ISP1301_I2C_INTERRUPT_FALLING | ISP1301_I2C_REG_CLEAR_ADDR,
  126. ~0);
  127. i2c_smbus_write_byte_data(isp1301_i2c_client,
  128. ISP1301_I2C_INTERRUPT_RISING | ISP1301_I2C_REG_CLEAR_ADDR, ~0);
  129. /* Enable usb_need_clk clock after transceiver is initialized */
  130. __raw_writel(__raw_readl(USB_CTRL) | USB_HOST_NEED_CLK_EN, USB_CTRL);
  131. printk(KERN_INFO "ISP1301 Vendor ID : 0x%04x\n",
  132. i2c_smbus_read_word_data(isp1301_i2c_client, 0x00));
  133. printk(KERN_INFO "ISP1301 Product ID : 0x%04x\n",
  134. i2c_smbus_read_word_data(isp1301_i2c_client, 0x02));
  135. printk(KERN_INFO "ISP1301 Version ID : 0x%04x\n",
  136. i2c_smbus_read_word_data(isp1301_i2c_client, 0x14));
  137. }
  138. static void isp1301_configure(void)
  139. {
  140. if (machine_is_pnx4008())
  141. isp1301_configure_pnx4008();
  142. else
  143. isp1301_configure_lpc32xx();
  144. }
  145. static inline void isp1301_vbus_on(void)
  146. {
  147. i2c_smbus_write_byte_data(isp1301_i2c_client, ISP1301_I2C_OTG_CONTROL_1,
  148. OTG1_VBUS_DRV);
  149. }
  150. static inline void isp1301_vbus_off(void)
  151. {
  152. i2c_smbus_write_byte_data(isp1301_i2c_client,
  153. ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR,
  154. OTG1_VBUS_DRV);
  155. }
  156. static void nxp_start_hc(void)
  157. {
  158. unsigned long tmp = __raw_readl(USB_OTG_STAT_CONTROL) | HOST_EN;
  159. __raw_writel(tmp, USB_OTG_STAT_CONTROL);
  160. isp1301_vbus_on();
  161. }
  162. static void nxp_stop_hc(void)
  163. {
  164. unsigned long tmp;
  165. isp1301_vbus_off();
  166. tmp = __raw_readl(USB_OTG_STAT_CONTROL) & ~HOST_EN;
  167. __raw_writel(tmp, USB_OTG_STAT_CONTROL);
  168. }
  169. static int __devinit ohci_nxp_start(struct usb_hcd *hcd)
  170. {
  171. struct ohci_hcd *ohci = hcd_to_ohci(hcd);
  172. int ret;
  173. if ((ret = ohci_init(ohci)) < 0)
  174. return ret;
  175. if ((ret = ohci_run(ohci)) < 0) {
  176. dev_err(hcd->self.controller, "can't start\n");
  177. ohci_stop(hcd);
  178. return ret;
  179. }
  180. return 0;
  181. }
  182. static const struct hc_driver ohci_nxp_hc_driver = {
  183. .description = hcd_name,
  184. .product_desc = "nxp OHCI",
  185. /*
  186. * generic hardware linkage
  187. */
  188. .irq = ohci_irq,
  189. .flags = HCD_USB11 | HCD_MEMORY,
  190. .hcd_priv_size = sizeof(struct ohci_hcd),
  191. /*
  192. * basic lifecycle operations
  193. */
  194. .start = ohci_nxp_start,
  195. .stop = ohci_stop,
  196. .shutdown = ohci_shutdown,
  197. /*
  198. * managing i/o requests and associated device resources
  199. */
  200. .urb_enqueue = ohci_urb_enqueue,
  201. .urb_dequeue = ohci_urb_dequeue,
  202. .endpoint_disable = ohci_endpoint_disable,
  203. /*
  204. * scheduling support
  205. */
  206. .get_frame_number = ohci_get_frame,
  207. /*
  208. * root hub support
  209. */
  210. .hub_status_data = ohci_hub_status_data,
  211. .hub_control = ohci_hub_control,
  212. #ifdef CONFIG_PM
  213. .bus_suspend = ohci_bus_suspend,
  214. .bus_resume = ohci_bus_resume,
  215. #endif
  216. .start_port_reset = ohci_start_port_reset,
  217. };
  218. #define USB_CLOCK_MASK (AHB_M_CLOCK_ON| OTG_CLOCK_ON | HOST_CLOCK_ON | I2C_CLOCK_ON)
  219. static void nxp_set_usb_bits(void)
  220. {
  221. if (machine_is_pnx4008()) {
  222. start_int_set_falling_edge(SE_USB_OTG_ATX_INT_N);
  223. start_int_ack(SE_USB_OTG_ATX_INT_N);
  224. start_int_umask(SE_USB_OTG_ATX_INT_N);
  225. start_int_set_rising_edge(SE_USB_OTG_TIMER_INT);
  226. start_int_ack(SE_USB_OTG_TIMER_INT);
  227. start_int_umask(SE_USB_OTG_TIMER_INT);
  228. start_int_set_rising_edge(SE_USB_I2C_INT);
  229. start_int_ack(SE_USB_I2C_INT);
  230. start_int_umask(SE_USB_I2C_INT);
  231. start_int_set_rising_edge(SE_USB_INT);
  232. start_int_ack(SE_USB_INT);
  233. start_int_umask(SE_USB_INT);
  234. start_int_set_rising_edge(SE_USB_NEED_CLK_INT);
  235. start_int_ack(SE_USB_NEED_CLK_INT);
  236. start_int_umask(SE_USB_NEED_CLK_INT);
  237. start_int_set_rising_edge(SE_USB_AHB_NEED_CLK_INT);
  238. start_int_ack(SE_USB_AHB_NEED_CLK_INT);
  239. start_int_umask(SE_USB_AHB_NEED_CLK_INT);
  240. }
  241. }
  242. static void nxp_unset_usb_bits(void)
  243. {
  244. if (machine_is_pnx4008()) {
  245. start_int_mask(SE_USB_OTG_ATX_INT_N);
  246. start_int_mask(SE_USB_OTG_TIMER_INT);
  247. start_int_mask(SE_USB_I2C_INT);
  248. start_int_mask(SE_USB_INT);
  249. start_int_mask(SE_USB_NEED_CLK_INT);
  250. start_int_mask(SE_USB_AHB_NEED_CLK_INT);
  251. }
  252. }
  253. static int __devinit usb_hcd_nxp_probe(struct platform_device *pdev)
  254. {
  255. struct usb_hcd *hcd = 0;
  256. struct ohci_hcd *ohci;
  257. const struct hc_driver *driver = &ohci_nxp_hc_driver;
  258. struct resource *res;
  259. int ret = 0, irq;
  260. struct device_node *isp1301_node;
  261. if (pdev->dev.of_node) {
  262. isp1301_node = of_parse_phandle(pdev->dev.of_node,
  263. "transceiver", 0);
  264. } else {
  265. isp1301_node = NULL;
  266. }
  267. isp1301_i2c_client = isp1301_get_client(isp1301_node);
  268. if (!isp1301_i2c_client) {
  269. ret = -EPROBE_DEFER;
  270. goto out;
  271. }
  272. pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
  273. pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
  274. dev_dbg(&pdev->dev, "%s: " DRIVER_DESC " (nxp)\n", hcd_name);
  275. if (usb_disabled()) {
  276. dev_err(&pdev->dev, "USB is disabled\n");
  277. ret = -ENODEV;
  278. goto out;
  279. }
  280. /* Enable AHB slave USB clock, needed for further USB clock control */
  281. __raw_writel(USB_SLAVE_HCLK_EN | PAD_CONTROL_LAST_DRIVEN, USB_CTRL);
  282. isp1301_configure();
  283. /* Enable USB PLL */
  284. usb_clk = clk_get(&pdev->dev, "ck_pll5");
  285. if (IS_ERR(usb_clk)) {
  286. dev_err(&pdev->dev, "failed to acquire USB PLL\n");
  287. ret = PTR_ERR(usb_clk);
  288. goto out1;
  289. }
  290. ret = clk_enable(usb_clk);
  291. if (ret < 0) {
  292. dev_err(&pdev->dev, "failed to start USB PLL\n");
  293. goto out2;
  294. }
  295. ret = clk_set_rate(usb_clk, 48000);
  296. if (ret < 0) {
  297. dev_err(&pdev->dev, "failed to set USB clock rate\n");
  298. goto out3;
  299. }
  300. __raw_writel(__raw_readl(USB_CTRL) | USB_HOST_NEED_CLK_EN, USB_CTRL);
  301. /* Set to enable all needed USB clocks */
  302. __raw_writel(USB_CLOCK_MASK, USB_OTG_CLK_CTRL);
  303. while ((__raw_readl(USB_OTG_CLK_STAT) & USB_CLOCK_MASK) !=
  304. USB_CLOCK_MASK) ;
  305. hcd = usb_create_hcd(driver, &pdev->dev, dev_name(&pdev->dev));
  306. if (!hcd) {
  307. dev_err(&pdev->dev, "Failed to allocate HC buffer\n");
  308. ret = -ENOMEM;
  309. goto out3;
  310. }
  311. /* Set all USB bits in the Start Enable register */
  312. nxp_set_usb_bits();
  313. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  314. if (!res) {
  315. dev_err(&pdev->dev, "Failed to get MEM resource\n");
  316. ret = -ENOMEM;
  317. goto out4;
  318. }
  319. hcd->regs = devm_request_and_ioremap(&pdev->dev, res);
  320. if (!hcd->regs) {
  321. dev_err(&pdev->dev, "Failed to devm_request_and_ioremap\n");
  322. ret = -ENOMEM;
  323. goto out4;
  324. }
  325. hcd->rsrc_start = res->start;
  326. hcd->rsrc_len = resource_size(res);
  327. irq = platform_get_irq(pdev, 0);
  328. if (irq < 0) {
  329. ret = -ENXIO;
  330. goto out4;
  331. }
  332. nxp_start_hc();
  333. platform_set_drvdata(pdev, hcd);
  334. ohci = hcd_to_ohci(hcd);
  335. ohci_hcd_init(ohci);
  336. dev_info(&pdev->dev, "at 0x%p, irq %d\n", hcd->regs, hcd->irq);
  337. ret = usb_add_hcd(hcd, irq, 0);
  338. if (ret == 0)
  339. return ret;
  340. nxp_stop_hc();
  341. out4:
  342. nxp_unset_usb_bits();
  343. usb_put_hcd(hcd);
  344. out3:
  345. clk_disable(usb_clk);
  346. out2:
  347. clk_put(usb_clk);
  348. out1:
  349. isp1301_i2c_client = NULL;
  350. out:
  351. return ret;
  352. }
  353. static int usb_hcd_nxp_remove(struct platform_device *pdev)
  354. {
  355. struct usb_hcd *hcd = platform_get_drvdata(pdev);
  356. usb_remove_hcd(hcd);
  357. nxp_stop_hc();
  358. release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
  359. usb_put_hcd(hcd);
  360. nxp_unset_usb_bits();
  361. clk_disable(usb_clk);
  362. clk_put(usb_clk);
  363. i2c_unregister_device(isp1301_i2c_client);
  364. isp1301_i2c_client = NULL;
  365. platform_set_drvdata(pdev, NULL);
  366. return 0;
  367. }
  368. /* work with hotplug and coldplug */
  369. MODULE_ALIAS("platform:usb-ohci");
  370. #ifdef CONFIG_OF
  371. static const struct of_device_id usb_hcd_nxp_match[] = {
  372. { .compatible = "nxp,ohci-nxp" },
  373. {},
  374. };
  375. MODULE_DEVICE_TABLE(of, usb_hcd_nxp_match);
  376. #endif
  377. static struct platform_driver usb_hcd_nxp_driver = {
  378. .driver = {
  379. .name = "usb-ohci",
  380. .owner = THIS_MODULE,
  381. .of_match_table = of_match_ptr(usb_hcd_nxp_match),
  382. },
  383. .probe = usb_hcd_nxp_probe,
  384. .remove = usb_hcd_nxp_remove,
  385. };