ehci-fsl.c 19 KB

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  1. /*
  2. * Copyright 2005-2009 MontaVista Software, Inc.
  3. * Copyright 2008,2012 Freescale Semiconductor, Inc.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of the GNU General Public License as published by the
  7. * Free Software Foundation; either version 2 of the License, or (at your
  8. * option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  12. * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  13. * for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software Foundation,
  17. * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  18. *
  19. * Ported to 834x by Randy Vinson <rvinson@mvista.com> using code provided
  20. * by Hunter Wu.
  21. * Power Management support by Dave Liu <daveliu@freescale.com>,
  22. * Jerry Huang <Chang-Ming.Huang@freescale.com> and
  23. * Anton Vorontsov <avorontsov@ru.mvista.com>.
  24. */
  25. #include <linux/kernel.h>
  26. #include <linux/types.h>
  27. #include <linux/delay.h>
  28. #include <linux/pm.h>
  29. #include <linux/platform_device.h>
  30. #include <linux/fsl_devices.h>
  31. #include "ehci-fsl.h"
  32. /* configure so an HC device and id are always provided */
  33. /* always called with process context; sleeping is OK */
  34. /**
  35. * usb_hcd_fsl_probe - initialize FSL-based HCDs
  36. * @drvier: Driver to be used for this HCD
  37. * @pdev: USB Host Controller being probed
  38. * Context: !in_interrupt()
  39. *
  40. * Allocates basic resources for this USB host controller.
  41. *
  42. */
  43. static int usb_hcd_fsl_probe(const struct hc_driver *driver,
  44. struct platform_device *pdev)
  45. {
  46. struct fsl_usb2_platform_data *pdata;
  47. struct usb_hcd *hcd;
  48. struct resource *res;
  49. int irq;
  50. int retval;
  51. pr_debug("initializing FSL-SOC USB Controller\n");
  52. /* Need platform data for setup */
  53. pdata = (struct fsl_usb2_platform_data *)pdev->dev.platform_data;
  54. if (!pdata) {
  55. dev_err(&pdev->dev,
  56. "No platform data for %s.\n", dev_name(&pdev->dev));
  57. return -ENODEV;
  58. }
  59. /*
  60. * This is a host mode driver, verify that we're supposed to be
  61. * in host mode.
  62. */
  63. if (!((pdata->operating_mode == FSL_USB2_DR_HOST) ||
  64. (pdata->operating_mode == FSL_USB2_MPH_HOST) ||
  65. (pdata->operating_mode == FSL_USB2_DR_OTG))) {
  66. dev_err(&pdev->dev,
  67. "Non Host Mode configured for %s. Wrong driver linked.\n",
  68. dev_name(&pdev->dev));
  69. return -ENODEV;
  70. }
  71. res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  72. if (!res) {
  73. dev_err(&pdev->dev,
  74. "Found HC with no IRQ. Check %s setup!\n",
  75. dev_name(&pdev->dev));
  76. return -ENODEV;
  77. }
  78. irq = res->start;
  79. hcd = usb_create_hcd(driver, &pdev->dev, dev_name(&pdev->dev));
  80. if (!hcd) {
  81. retval = -ENOMEM;
  82. goto err1;
  83. }
  84. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  85. if (!res) {
  86. dev_err(&pdev->dev,
  87. "Found HC with no register addr. Check %s setup!\n",
  88. dev_name(&pdev->dev));
  89. retval = -ENODEV;
  90. goto err2;
  91. }
  92. hcd->rsrc_start = res->start;
  93. hcd->rsrc_len = resource_size(res);
  94. if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len,
  95. driver->description)) {
  96. dev_dbg(&pdev->dev, "controller already in use\n");
  97. retval = -EBUSY;
  98. goto err2;
  99. }
  100. hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len);
  101. if (hcd->regs == NULL) {
  102. dev_dbg(&pdev->dev, "error mapping memory\n");
  103. retval = -EFAULT;
  104. goto err3;
  105. }
  106. pdata->regs = hcd->regs;
  107. if (pdata->power_budget)
  108. hcd->power_budget = pdata->power_budget;
  109. /*
  110. * do platform specific init: check the clock, grab/config pins, etc.
  111. */
  112. if (pdata->init && pdata->init(pdev)) {
  113. retval = -ENODEV;
  114. goto err4;
  115. }
  116. /* Enable USB controller, 83xx or 8536 */
  117. if (pdata->have_sysif_regs)
  118. setbits32(hcd->regs + FSL_SOC_USB_CTRL, 0x4);
  119. /* Don't need to set host mode here. It will be done by tdi_reset() */
  120. retval = usb_add_hcd(hcd, irq, IRQF_SHARED);
  121. if (retval != 0)
  122. goto err4;
  123. #ifdef CONFIG_USB_OTG
  124. if (pdata->operating_mode == FSL_USB2_DR_OTG) {
  125. struct ehci_hcd *ehci = hcd_to_ehci(hcd);
  126. ehci->transceiver = usb_get_transceiver();
  127. dev_dbg(&pdev->dev, "hcd=0x%p ehci=0x%p, transceiver=0x%p\n",
  128. hcd, ehci, ehci->transceiver);
  129. if (ehci->transceiver) {
  130. retval = otg_set_host(ehci->transceiver->otg,
  131. &ehci_to_hcd(ehci)->self);
  132. if (retval) {
  133. usb_put_transceiver(ehci->transceiver);
  134. goto err4;
  135. }
  136. } else {
  137. dev_err(&pdev->dev, "can't find transceiver\n");
  138. retval = -ENODEV;
  139. goto err4;
  140. }
  141. }
  142. #endif
  143. return retval;
  144. err4:
  145. iounmap(hcd->regs);
  146. err3:
  147. release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
  148. err2:
  149. usb_put_hcd(hcd);
  150. err1:
  151. dev_err(&pdev->dev, "init %s fail, %d\n", dev_name(&pdev->dev), retval);
  152. if (pdata->exit)
  153. pdata->exit(pdev);
  154. return retval;
  155. }
  156. /* may be called without controller electrically present */
  157. /* may be called with controller, bus, and devices active */
  158. /**
  159. * usb_hcd_fsl_remove - shutdown processing for FSL-based HCDs
  160. * @dev: USB Host Controller being removed
  161. * Context: !in_interrupt()
  162. *
  163. * Reverses the effect of usb_hcd_fsl_probe().
  164. *
  165. */
  166. static void usb_hcd_fsl_remove(struct usb_hcd *hcd,
  167. struct platform_device *pdev)
  168. {
  169. struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
  170. struct ehci_hcd *ehci = hcd_to_ehci(hcd);
  171. if (ehci->transceiver) {
  172. otg_set_host(ehci->transceiver->otg, NULL);
  173. usb_put_transceiver(ehci->transceiver);
  174. }
  175. usb_remove_hcd(hcd);
  176. /*
  177. * do platform specific un-initialization:
  178. * release iomux pins, disable clock, etc.
  179. */
  180. if (pdata->exit)
  181. pdata->exit(pdev);
  182. iounmap(hcd->regs);
  183. release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
  184. usb_put_hcd(hcd);
  185. }
  186. static void ehci_fsl_setup_phy(struct usb_hcd *hcd,
  187. enum fsl_usb2_phy_modes phy_mode,
  188. unsigned int port_offset)
  189. {
  190. u32 portsc, temp;
  191. struct ehci_hcd *ehci = hcd_to_ehci(hcd);
  192. void __iomem *non_ehci = hcd->regs;
  193. struct device *dev = hcd->self.controller;
  194. struct fsl_usb2_platform_data *pdata = dev->platform_data;
  195. if (pdata->controller_ver < 0) {
  196. dev_warn(hcd->self.controller, "Could not get controller version\n");
  197. return;
  198. }
  199. portsc = ehci_readl(ehci, &ehci->regs->port_status[port_offset]);
  200. portsc &= ~(PORT_PTS_MSK | PORT_PTS_PTW);
  201. switch (phy_mode) {
  202. case FSL_USB2_PHY_ULPI:
  203. if (pdata->controller_ver) {
  204. /* controller version 1.6 or above */
  205. temp = in_be32(non_ehci + FSL_SOC_USB_CTRL);
  206. out_be32(non_ehci + FSL_SOC_USB_CTRL, temp |
  207. USB_CTRL_USB_EN | ULPI_PHY_CLK_SEL);
  208. }
  209. portsc |= PORT_PTS_ULPI;
  210. break;
  211. case FSL_USB2_PHY_SERIAL:
  212. portsc |= PORT_PTS_SERIAL;
  213. break;
  214. case FSL_USB2_PHY_UTMI_WIDE:
  215. portsc |= PORT_PTS_PTW;
  216. /* fall through */
  217. case FSL_USB2_PHY_UTMI:
  218. if (pdata->controller_ver) {
  219. /* controller version 1.6 or above */
  220. temp = in_be32(non_ehci + FSL_SOC_USB_CTRL);
  221. out_be32(non_ehci + FSL_SOC_USB_CTRL, temp |
  222. UTMI_PHY_EN | USB_CTRL_USB_EN);
  223. mdelay(FSL_UTMI_PHY_DLY); /* Delay for UTMI PHY CLK to
  224. become stable - 10ms*/
  225. }
  226. /* enable UTMI PHY */
  227. if (pdata->have_sysif_regs)
  228. setbits32(non_ehci + FSL_SOC_USB_CTRL,
  229. CTRL_UTMI_PHY_EN);
  230. portsc |= PORT_PTS_UTMI;
  231. break;
  232. case FSL_USB2_PHY_NONE:
  233. break;
  234. }
  235. ehci_writel(ehci, portsc, &ehci->regs->port_status[port_offset]);
  236. }
  237. static void ehci_fsl_usb_setup(struct ehci_hcd *ehci)
  238. {
  239. struct usb_hcd *hcd = ehci_to_hcd(ehci);
  240. struct fsl_usb2_platform_data *pdata;
  241. void __iomem *non_ehci = hcd->regs;
  242. u32 temp;
  243. pdata = hcd->self.controller->platform_data;
  244. /* Enable PHY interface in the control reg. */
  245. if (pdata->have_sysif_regs) {
  246. temp = in_be32(non_ehci + FSL_SOC_USB_CTRL);
  247. out_be32(non_ehci + FSL_SOC_USB_CTRL, temp | 0x00000004);
  248. /*
  249. * Turn on cache snooping hardware, since some PowerPC platforms
  250. * wholly rely on hardware to deal with cache coherent
  251. */
  252. /* Setup Snooping for all the 4GB space */
  253. /* SNOOP1 starts from 0x0, size 2G */
  254. out_be32(non_ehci + FSL_SOC_USB_SNOOP1, 0x0 | SNOOP_SIZE_2GB);
  255. /* SNOOP2 starts from 0x80000000, size 2G */
  256. out_be32(non_ehci + FSL_SOC_USB_SNOOP2, 0x80000000 | SNOOP_SIZE_2GB);
  257. }
  258. if ((pdata->operating_mode == FSL_USB2_DR_HOST) ||
  259. (pdata->operating_mode == FSL_USB2_DR_OTG))
  260. ehci_fsl_setup_phy(hcd, pdata->phy_mode, 0);
  261. if (pdata->operating_mode == FSL_USB2_MPH_HOST) {
  262. unsigned int chip, rev, svr;
  263. svr = mfspr(SPRN_SVR);
  264. chip = svr >> 16;
  265. rev = (svr >> 4) & 0xf;
  266. /* Deal with USB Erratum #14 on MPC834x Rev 1.0 & 1.1 chips */
  267. if ((rev == 1) && (chip >= 0x8050) && (chip <= 0x8055))
  268. ehci->has_fsl_port_bug = 1;
  269. if (pdata->port_enables & FSL_USB2_PORT0_ENABLED)
  270. ehci_fsl_setup_phy(hcd, pdata->phy_mode, 0);
  271. if (pdata->port_enables & FSL_USB2_PORT1_ENABLED)
  272. ehci_fsl_setup_phy(hcd, pdata->phy_mode, 1);
  273. }
  274. if (pdata->have_sysif_regs) {
  275. #ifdef CONFIG_PPC_85xx
  276. out_be32(non_ehci + FSL_SOC_USB_PRICTRL, 0x00000008);
  277. out_be32(non_ehci + FSL_SOC_USB_AGECNTTHRSH, 0x00000080);
  278. #else
  279. out_be32(non_ehci + FSL_SOC_USB_PRICTRL, 0x0000000c);
  280. out_be32(non_ehci + FSL_SOC_USB_AGECNTTHRSH, 0x00000040);
  281. #endif
  282. out_be32(non_ehci + FSL_SOC_USB_SICTRL, 0x00000001);
  283. }
  284. }
  285. /* called after powerup, by probe or system-pm "wakeup" */
  286. static int ehci_fsl_reinit(struct ehci_hcd *ehci)
  287. {
  288. ehci_fsl_usb_setup(ehci);
  289. ehci_port_power(ehci, 0);
  290. return 0;
  291. }
  292. /* called during probe() after chip reset completes */
  293. static int ehci_fsl_setup(struct usb_hcd *hcd)
  294. {
  295. struct ehci_hcd *ehci = hcd_to_ehci(hcd);
  296. int retval;
  297. struct fsl_usb2_platform_data *pdata;
  298. struct device *dev;
  299. dev = hcd->self.controller;
  300. pdata = hcd->self.controller->platform_data;
  301. ehci->big_endian_desc = pdata->big_endian_desc;
  302. ehci->big_endian_mmio = pdata->big_endian_mmio;
  303. /* EHCI registers start at offset 0x100 */
  304. ehci->caps = hcd->regs + 0x100;
  305. ehci->regs = hcd->regs + 0x100 +
  306. HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase));
  307. dbg_hcs_params(ehci, "reset");
  308. dbg_hcc_params(ehci, "reset");
  309. /* cache this readonly data; minimize chip reads */
  310. ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);
  311. hcd->has_tt = 1;
  312. retval = ehci_halt(ehci);
  313. if (retval)
  314. return retval;
  315. /* data structure init */
  316. retval = ehci_init(hcd);
  317. if (retval)
  318. return retval;
  319. ehci->sbrn = 0x20;
  320. ehci_reset(ehci);
  321. if (of_device_is_compatible(dev->parent->of_node,
  322. "fsl,mpc5121-usb2-dr")) {
  323. /*
  324. * set SBUSCFG:AHBBRST so that control msgs don't
  325. * fail when doing heavy PATA writes.
  326. */
  327. ehci_writel(ehci, SBUSCFG_INCR8,
  328. hcd->regs + FSL_SOC_USB_SBUSCFG);
  329. }
  330. retval = ehci_fsl_reinit(ehci);
  331. return retval;
  332. }
  333. struct ehci_fsl {
  334. struct ehci_hcd ehci;
  335. #ifdef CONFIG_PM
  336. /* Saved USB PHY settings, need to restore after deep sleep. */
  337. u32 usb_ctrl;
  338. #endif
  339. };
  340. #ifdef CONFIG_PM
  341. #ifdef CONFIG_PPC_MPC512x
  342. static int ehci_fsl_mpc512x_drv_suspend(struct device *dev)
  343. {
  344. struct usb_hcd *hcd = dev_get_drvdata(dev);
  345. struct ehci_hcd *ehci = hcd_to_ehci(hcd);
  346. struct fsl_usb2_platform_data *pdata = dev->platform_data;
  347. u32 tmp;
  348. #ifdef DEBUG
  349. u32 mode = ehci_readl(ehci, hcd->regs + FSL_SOC_USB_USBMODE);
  350. mode &= USBMODE_CM_MASK;
  351. tmp = ehci_readl(ehci, hcd->regs + 0x140); /* usbcmd */
  352. dev_dbg(dev, "suspend=%d already_suspended=%d "
  353. "mode=%d usbcmd %08x\n", pdata->suspended,
  354. pdata->already_suspended, mode, tmp);
  355. #endif
  356. /*
  357. * If the controller is already suspended, then this must be a
  358. * PM suspend. Remember this fact, so that we will leave the
  359. * controller suspended at PM resume time.
  360. */
  361. if (pdata->suspended) {
  362. dev_dbg(dev, "already suspended, leaving early\n");
  363. pdata->already_suspended = 1;
  364. return 0;
  365. }
  366. dev_dbg(dev, "suspending...\n");
  367. ehci->rh_state = EHCI_RH_SUSPENDED;
  368. dev->power.power_state = PMSG_SUSPEND;
  369. /* ignore non-host interrupts */
  370. clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
  371. /* stop the controller */
  372. tmp = ehci_readl(ehci, &ehci->regs->command);
  373. tmp &= ~CMD_RUN;
  374. ehci_writel(ehci, tmp, &ehci->regs->command);
  375. /* save EHCI registers */
  376. pdata->pm_command = ehci_readl(ehci, &ehci->regs->command);
  377. pdata->pm_command &= ~CMD_RUN;
  378. pdata->pm_status = ehci_readl(ehci, &ehci->regs->status);
  379. pdata->pm_intr_enable = ehci_readl(ehci, &ehci->regs->intr_enable);
  380. pdata->pm_frame_index = ehci_readl(ehci, &ehci->regs->frame_index);
  381. pdata->pm_segment = ehci_readl(ehci, &ehci->regs->segment);
  382. pdata->pm_frame_list = ehci_readl(ehci, &ehci->regs->frame_list);
  383. pdata->pm_async_next = ehci_readl(ehci, &ehci->regs->async_next);
  384. pdata->pm_configured_flag =
  385. ehci_readl(ehci, &ehci->regs->configured_flag);
  386. pdata->pm_portsc = ehci_readl(ehci, &ehci->regs->port_status[0]);
  387. pdata->pm_usbgenctrl = ehci_readl(ehci,
  388. hcd->regs + FSL_SOC_USB_USBGENCTRL);
  389. /* clear the W1C bits */
  390. pdata->pm_portsc &= cpu_to_hc32(ehci, ~PORT_RWC_BITS);
  391. pdata->suspended = 1;
  392. /* clear PP to cut power to the port */
  393. tmp = ehci_readl(ehci, &ehci->regs->port_status[0]);
  394. tmp &= ~PORT_POWER;
  395. ehci_writel(ehci, tmp, &ehci->regs->port_status[0]);
  396. return 0;
  397. }
  398. static int ehci_fsl_mpc512x_drv_resume(struct device *dev)
  399. {
  400. struct usb_hcd *hcd = dev_get_drvdata(dev);
  401. struct ehci_hcd *ehci = hcd_to_ehci(hcd);
  402. struct fsl_usb2_platform_data *pdata = dev->platform_data;
  403. u32 tmp;
  404. dev_dbg(dev, "suspend=%d already_suspended=%d\n",
  405. pdata->suspended, pdata->already_suspended);
  406. /*
  407. * If the controller was already suspended at suspend time,
  408. * then don't resume it now.
  409. */
  410. if (pdata->already_suspended) {
  411. dev_dbg(dev, "already suspended, leaving early\n");
  412. pdata->already_suspended = 0;
  413. return 0;
  414. }
  415. if (!pdata->suspended) {
  416. dev_dbg(dev, "not suspended, leaving early\n");
  417. return 0;
  418. }
  419. pdata->suspended = 0;
  420. dev_dbg(dev, "resuming...\n");
  421. /* set host mode */
  422. tmp = USBMODE_CM_HOST | (pdata->es ? USBMODE_ES : 0);
  423. ehci_writel(ehci, tmp, hcd->regs + FSL_SOC_USB_USBMODE);
  424. ehci_writel(ehci, pdata->pm_usbgenctrl,
  425. hcd->regs + FSL_SOC_USB_USBGENCTRL);
  426. ehci_writel(ehci, ISIPHYCTRL_PXE | ISIPHYCTRL_PHYE,
  427. hcd->regs + FSL_SOC_USB_ISIPHYCTRL);
  428. ehci_writel(ehci, SBUSCFG_INCR8, hcd->regs + FSL_SOC_USB_SBUSCFG);
  429. /* restore EHCI registers */
  430. ehci_writel(ehci, pdata->pm_command, &ehci->regs->command);
  431. ehci_writel(ehci, pdata->pm_intr_enable, &ehci->regs->intr_enable);
  432. ehci_writel(ehci, pdata->pm_frame_index, &ehci->regs->frame_index);
  433. ehci_writel(ehci, pdata->pm_segment, &ehci->regs->segment);
  434. ehci_writel(ehci, pdata->pm_frame_list, &ehci->regs->frame_list);
  435. ehci_writel(ehci, pdata->pm_async_next, &ehci->regs->async_next);
  436. ehci_writel(ehci, pdata->pm_configured_flag,
  437. &ehci->regs->configured_flag);
  438. ehci_writel(ehci, pdata->pm_portsc, &ehci->regs->port_status[0]);
  439. set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
  440. ehci->rh_state = EHCI_RH_RUNNING;
  441. dev->power.power_state = PMSG_ON;
  442. tmp = ehci_readl(ehci, &ehci->regs->command);
  443. tmp |= CMD_RUN;
  444. ehci_writel(ehci, tmp, &ehci->regs->command);
  445. usb_hcd_resume_root_hub(hcd);
  446. return 0;
  447. }
  448. #else
  449. static inline int ehci_fsl_mpc512x_drv_suspend(struct device *dev)
  450. {
  451. return 0;
  452. }
  453. static inline int ehci_fsl_mpc512x_drv_resume(struct device *dev)
  454. {
  455. return 0;
  456. }
  457. #endif /* CONFIG_PPC_MPC512x */
  458. static struct ehci_fsl *hcd_to_ehci_fsl(struct usb_hcd *hcd)
  459. {
  460. struct ehci_hcd *ehci = hcd_to_ehci(hcd);
  461. return container_of(ehci, struct ehci_fsl, ehci);
  462. }
  463. static int ehci_fsl_drv_suspend(struct device *dev)
  464. {
  465. struct usb_hcd *hcd = dev_get_drvdata(dev);
  466. struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd);
  467. void __iomem *non_ehci = hcd->regs;
  468. if (of_device_is_compatible(dev->parent->of_node,
  469. "fsl,mpc5121-usb2-dr")) {
  470. return ehci_fsl_mpc512x_drv_suspend(dev);
  471. }
  472. ehci_prepare_ports_for_controller_suspend(hcd_to_ehci(hcd),
  473. device_may_wakeup(dev));
  474. if (!fsl_deep_sleep())
  475. return 0;
  476. ehci_fsl->usb_ctrl = in_be32(non_ehci + FSL_SOC_USB_CTRL);
  477. return 0;
  478. }
  479. static int ehci_fsl_drv_resume(struct device *dev)
  480. {
  481. struct usb_hcd *hcd = dev_get_drvdata(dev);
  482. struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd);
  483. struct ehci_hcd *ehci = hcd_to_ehci(hcd);
  484. void __iomem *non_ehci = hcd->regs;
  485. if (of_device_is_compatible(dev->parent->of_node,
  486. "fsl,mpc5121-usb2-dr")) {
  487. return ehci_fsl_mpc512x_drv_resume(dev);
  488. }
  489. ehci_prepare_ports_for_controller_resume(ehci);
  490. if (!fsl_deep_sleep())
  491. return 0;
  492. usb_root_hub_lost_power(hcd->self.root_hub);
  493. /* Restore USB PHY settings and enable the controller. */
  494. out_be32(non_ehci + FSL_SOC_USB_CTRL, ehci_fsl->usb_ctrl);
  495. ehci_reset(ehci);
  496. ehci_fsl_reinit(ehci);
  497. return 0;
  498. }
  499. static int ehci_fsl_drv_restore(struct device *dev)
  500. {
  501. struct usb_hcd *hcd = dev_get_drvdata(dev);
  502. usb_root_hub_lost_power(hcd->self.root_hub);
  503. return 0;
  504. }
  505. static struct dev_pm_ops ehci_fsl_pm_ops = {
  506. .suspend = ehci_fsl_drv_suspend,
  507. .resume = ehci_fsl_drv_resume,
  508. .restore = ehci_fsl_drv_restore,
  509. };
  510. #define EHCI_FSL_PM_OPS (&ehci_fsl_pm_ops)
  511. #else
  512. #define EHCI_FSL_PM_OPS NULL
  513. #endif /* CONFIG_PM */
  514. #ifdef CONFIG_USB_OTG
  515. static int ehci_start_port_reset(struct usb_hcd *hcd, unsigned port)
  516. {
  517. struct ehci_hcd *ehci = hcd_to_ehci(hcd);
  518. u32 status;
  519. if (!port)
  520. return -EINVAL;
  521. port--;
  522. /* start port reset before HNP protocol time out */
  523. status = readl(&ehci->regs->port_status[port]);
  524. if (!(status & PORT_CONNECT))
  525. return -ENODEV;
  526. /* khubd will finish the reset later */
  527. if (ehci_is_TDI(ehci)) {
  528. writel(PORT_RESET |
  529. (status & ~(PORT_CSC | PORT_PEC | PORT_OCC)),
  530. &ehci->regs->port_status[port]);
  531. } else {
  532. writel(PORT_RESET, &ehci->regs->port_status[port]);
  533. }
  534. return 0;
  535. }
  536. #else
  537. #define ehci_start_port_reset NULL
  538. #endif /* CONFIG_USB_OTG */
  539. static const struct hc_driver ehci_fsl_hc_driver = {
  540. .description = hcd_name,
  541. .product_desc = "Freescale On-Chip EHCI Host Controller",
  542. .hcd_priv_size = sizeof(struct ehci_fsl),
  543. /*
  544. * generic hardware linkage
  545. */
  546. .irq = ehci_irq,
  547. .flags = HCD_USB2 | HCD_MEMORY,
  548. /*
  549. * basic lifecycle operations
  550. */
  551. .reset = ehci_fsl_setup,
  552. .start = ehci_run,
  553. .stop = ehci_stop,
  554. .shutdown = ehci_shutdown,
  555. /*
  556. * managing i/o requests and associated device resources
  557. */
  558. .urb_enqueue = ehci_urb_enqueue,
  559. .urb_dequeue = ehci_urb_dequeue,
  560. .endpoint_disable = ehci_endpoint_disable,
  561. .endpoint_reset = ehci_endpoint_reset,
  562. /*
  563. * scheduling support
  564. */
  565. .get_frame_number = ehci_get_frame,
  566. /*
  567. * root hub support
  568. */
  569. .hub_status_data = ehci_hub_status_data,
  570. .hub_control = ehci_hub_control,
  571. .bus_suspend = ehci_bus_suspend,
  572. .bus_resume = ehci_bus_resume,
  573. .start_port_reset = ehci_start_port_reset,
  574. .relinquish_port = ehci_relinquish_port,
  575. .port_handed_over = ehci_port_handed_over,
  576. .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete,
  577. };
  578. static int ehci_fsl_drv_probe(struct platform_device *pdev)
  579. {
  580. if (usb_disabled())
  581. return -ENODEV;
  582. /* FIXME we only want one one probe() not two */
  583. return usb_hcd_fsl_probe(&ehci_fsl_hc_driver, pdev);
  584. }
  585. static int ehci_fsl_drv_remove(struct platform_device *pdev)
  586. {
  587. struct usb_hcd *hcd = platform_get_drvdata(pdev);
  588. /* FIXME we only want one one remove() not two */
  589. usb_hcd_fsl_remove(hcd, pdev);
  590. return 0;
  591. }
  592. MODULE_ALIAS("platform:fsl-ehci");
  593. static struct platform_driver ehci_fsl_driver = {
  594. .probe = ehci_fsl_drv_probe,
  595. .remove = ehci_fsl_drv_remove,
  596. .shutdown = usb_hcd_platform_shutdown,
  597. .driver = {
  598. .name = "fsl-ehci",
  599. .pm = EHCI_FSL_PM_OPS,
  600. },
  601. };