ufshcd.c 51 KB

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  1. /*
  2. * Universal Flash Storage Host controller driver
  3. *
  4. * This code is based on drivers/scsi/ufs/ufshcd.c
  5. * Copyright (C) 2011-2012 Samsung India Software Operations
  6. *
  7. * Santosh Yaraganavi <santosh.sy@samsung.com>
  8. * Vinayak Holikatti <h.vinayak@samsung.com>
  9. *
  10. * This program is free software; you can redistribute it and/or
  11. * modify it under the terms of the GNU General Public License
  12. * as published by the Free Software Foundation; either version 2
  13. * of the License, or (at your option) any later version.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. * GNU General Public License for more details.
  19. *
  20. * NO WARRANTY
  21. * THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR
  22. * CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT
  23. * LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
  24. * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is
  25. * solely responsible for determining the appropriateness of using and
  26. * distributing the Program and assumes all risks associated with its
  27. * exercise of rights under this Agreement, including but not limited to
  28. * the risks and costs of program errors, damage to or loss of data,
  29. * programs or equipment, and unavailability or interruption of operations.
  30. * DISCLAIMER OF LIABILITY
  31. * NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY
  32. * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  33. * DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND
  34. * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
  35. * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
  36. * USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED
  37. * HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES
  38. * You should have received a copy of the GNU General Public License
  39. * along with this program; if not, write to the Free Software
  40. * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301,
  41. * USA.
  42. */
  43. #include <linux/module.h>
  44. #include <linux/kernel.h>
  45. #include <linux/init.h>
  46. #include <linux/pci.h>
  47. #include <linux/interrupt.h>
  48. #include <linux/io.h>
  49. #include <linux/delay.h>
  50. #include <linux/slab.h>
  51. #include <linux/spinlock.h>
  52. #include <linux/workqueue.h>
  53. #include <linux/errno.h>
  54. #include <linux/types.h>
  55. #include <linux/wait.h>
  56. #include <linux/bitops.h>
  57. #include <asm/irq.h>
  58. #include <asm/byteorder.h>
  59. #include <scsi/scsi.h>
  60. #include <scsi/scsi_cmnd.h>
  61. #include <scsi/scsi_host.h>
  62. #include <scsi/scsi_tcq.h>
  63. #include <scsi/scsi_dbg.h>
  64. #include <scsi/scsi_eh.h>
  65. #include "ufs.h"
  66. #include "ufshci.h"
  67. #define UFSHCD "ufshcd"
  68. #define UFSHCD_DRIVER_VERSION "0.1"
  69. enum {
  70. UFSHCD_MAX_CHANNEL = 0,
  71. UFSHCD_MAX_ID = 1,
  72. UFSHCD_MAX_LUNS = 8,
  73. UFSHCD_CMD_PER_LUN = 32,
  74. UFSHCD_CAN_QUEUE = 32,
  75. };
  76. /* UFSHCD states */
  77. enum {
  78. UFSHCD_STATE_OPERATIONAL,
  79. UFSHCD_STATE_RESET,
  80. UFSHCD_STATE_ERROR,
  81. };
  82. /* Interrupt configuration options */
  83. enum {
  84. UFSHCD_INT_DISABLE,
  85. UFSHCD_INT_ENABLE,
  86. UFSHCD_INT_CLEAR,
  87. };
  88. /* Interrupt aggregation options */
  89. enum {
  90. INT_AGGR_RESET,
  91. INT_AGGR_CONFIG,
  92. };
  93. /**
  94. * struct uic_command - UIC command structure
  95. * @command: UIC command
  96. * @argument1: UIC command argument 1
  97. * @argument2: UIC command argument 2
  98. * @argument3: UIC command argument 3
  99. * @cmd_active: Indicate if UIC command is outstanding
  100. * @result: UIC command result
  101. */
  102. struct uic_command {
  103. u32 command;
  104. u32 argument1;
  105. u32 argument2;
  106. u32 argument3;
  107. int cmd_active;
  108. int result;
  109. };
  110. /**
  111. * struct ufs_hba - per adapter private structure
  112. * @mmio_base: UFSHCI base register address
  113. * @ucdl_base_addr: UFS Command Descriptor base address
  114. * @utrdl_base_addr: UTP Transfer Request Descriptor base address
  115. * @utmrdl_base_addr: UTP Task Management Descriptor base address
  116. * @ucdl_dma_addr: UFS Command Descriptor DMA address
  117. * @utrdl_dma_addr: UTRDL DMA address
  118. * @utmrdl_dma_addr: UTMRDL DMA address
  119. * @host: Scsi_Host instance of the driver
  120. * @pdev: PCI device handle
  121. * @lrb: local reference block
  122. * @outstanding_tasks: Bits representing outstanding task requests
  123. * @outstanding_reqs: Bits representing outstanding transfer requests
  124. * @capabilities: UFS Controller Capabilities
  125. * @nutrs: Transfer Request Queue depth supported by controller
  126. * @nutmrs: Task Management Queue depth supported by controller
  127. * @active_uic_cmd: handle of active UIC command
  128. * @ufshcd_tm_wait_queue: wait queue for task management
  129. * @tm_condition: condition variable for task management
  130. * @ufshcd_state: UFSHCD states
  131. * @int_enable_mask: Interrupt Mask Bits
  132. * @uic_workq: Work queue for UIC completion handling
  133. * @feh_workq: Work queue for fatal controller error handling
  134. * @errors: HBA errors
  135. */
  136. struct ufs_hba {
  137. void __iomem *mmio_base;
  138. /* Virtual memory reference */
  139. struct utp_transfer_cmd_desc *ucdl_base_addr;
  140. struct utp_transfer_req_desc *utrdl_base_addr;
  141. struct utp_task_req_desc *utmrdl_base_addr;
  142. /* DMA memory reference */
  143. dma_addr_t ucdl_dma_addr;
  144. dma_addr_t utrdl_dma_addr;
  145. dma_addr_t utmrdl_dma_addr;
  146. struct Scsi_Host *host;
  147. struct pci_dev *pdev;
  148. struct ufshcd_lrb *lrb;
  149. unsigned long outstanding_tasks;
  150. unsigned long outstanding_reqs;
  151. u32 capabilities;
  152. int nutrs;
  153. int nutmrs;
  154. u32 ufs_version;
  155. struct uic_command active_uic_cmd;
  156. wait_queue_head_t ufshcd_tm_wait_queue;
  157. unsigned long tm_condition;
  158. u32 ufshcd_state;
  159. u32 int_enable_mask;
  160. /* Work Queues */
  161. struct work_struct uic_workq;
  162. struct work_struct feh_workq;
  163. /* HBA Errors */
  164. u32 errors;
  165. };
  166. /**
  167. * struct ufshcd_lrb - local reference block
  168. * @utr_descriptor_ptr: UTRD address of the command
  169. * @ucd_cmd_ptr: UCD address of the command
  170. * @ucd_rsp_ptr: Response UPIU address for this command
  171. * @ucd_prdt_ptr: PRDT address of the command
  172. * @cmd: pointer to SCSI command
  173. * @sense_buffer: pointer to sense buffer address of the SCSI command
  174. * @sense_bufflen: Length of the sense buffer
  175. * @scsi_status: SCSI status of the command
  176. * @command_type: SCSI, UFS, Query.
  177. * @task_tag: Task tag of the command
  178. * @lun: LUN of the command
  179. */
  180. struct ufshcd_lrb {
  181. struct utp_transfer_req_desc *utr_descriptor_ptr;
  182. struct utp_upiu_cmd *ucd_cmd_ptr;
  183. struct utp_upiu_rsp *ucd_rsp_ptr;
  184. struct ufshcd_sg_entry *ucd_prdt_ptr;
  185. struct scsi_cmnd *cmd;
  186. u8 *sense_buffer;
  187. unsigned int sense_bufflen;
  188. int scsi_status;
  189. int command_type;
  190. int task_tag;
  191. unsigned int lun;
  192. };
  193. /**
  194. * ufshcd_get_ufs_version - Get the UFS version supported by the HBA
  195. * @hba - Pointer to adapter instance
  196. *
  197. * Returns UFSHCI version supported by the controller
  198. */
  199. static inline u32 ufshcd_get_ufs_version(struct ufs_hba *hba)
  200. {
  201. return readl(hba->mmio_base + REG_UFS_VERSION);
  202. }
  203. /**
  204. * ufshcd_is_device_present - Check if any device connected to
  205. * the host controller
  206. * @reg_hcs - host controller status register value
  207. *
  208. * Returns 0 if device present, non-zero if no device detected
  209. */
  210. static inline int ufshcd_is_device_present(u32 reg_hcs)
  211. {
  212. return (DEVICE_PRESENT & reg_hcs) ? 0 : -1;
  213. }
  214. /**
  215. * ufshcd_get_tr_ocs - Get the UTRD Overall Command Status
  216. * @lrb: pointer to local command reference block
  217. *
  218. * This function is used to get the OCS field from UTRD
  219. * Returns the OCS field in the UTRD
  220. */
  221. static inline int ufshcd_get_tr_ocs(struct ufshcd_lrb *lrbp)
  222. {
  223. return lrbp->utr_descriptor_ptr->header.dword_2 & MASK_OCS;
  224. }
  225. /**
  226. * ufshcd_get_tmr_ocs - Get the UTMRD Overall Command Status
  227. * @task_req_descp: pointer to utp_task_req_desc structure
  228. *
  229. * This function is used to get the OCS field from UTMRD
  230. * Returns the OCS field in the UTMRD
  231. */
  232. static inline int
  233. ufshcd_get_tmr_ocs(struct utp_task_req_desc *task_req_descp)
  234. {
  235. return task_req_descp->header.dword_2 & MASK_OCS;
  236. }
  237. /**
  238. * ufshcd_get_tm_free_slot - get a free slot for task management request
  239. * @hba: per adapter instance
  240. *
  241. * Returns maximum number of task management request slots in case of
  242. * task management queue full or returns the free slot number
  243. */
  244. static inline int ufshcd_get_tm_free_slot(struct ufs_hba *hba)
  245. {
  246. return find_first_zero_bit(&hba->outstanding_tasks, hba->nutmrs);
  247. }
  248. /**
  249. * ufshcd_utrl_clear - Clear a bit in UTRLCLR register
  250. * @hba: per adapter instance
  251. * @pos: position of the bit to be cleared
  252. */
  253. static inline void ufshcd_utrl_clear(struct ufs_hba *hba, u32 pos)
  254. {
  255. writel(~(1 << pos),
  256. (hba->mmio_base + REG_UTP_TRANSFER_REQ_LIST_CLEAR));
  257. }
  258. /**
  259. * ufshcd_get_lists_status - Check UCRDY, UTRLRDY and UTMRLRDY
  260. * @reg: Register value of host controller status
  261. *
  262. * Returns integer, 0 on Success and positive value if failed
  263. */
  264. static inline int ufshcd_get_lists_status(u32 reg)
  265. {
  266. /*
  267. * The mask 0xFF is for the following HCS register bits
  268. * Bit Description
  269. * 0 Device Present
  270. * 1 UTRLRDY
  271. * 2 UTMRLRDY
  272. * 3 UCRDY
  273. * 4 HEI
  274. * 5 DEI
  275. * 6-7 reserved
  276. */
  277. return (((reg) & (0xFF)) >> 1) ^ (0x07);
  278. }
  279. /**
  280. * ufshcd_get_uic_cmd_result - Get the UIC command result
  281. * @hba: Pointer to adapter instance
  282. *
  283. * This function gets the result of UIC command completion
  284. * Returns 0 on success, non zero value on error
  285. */
  286. static inline int ufshcd_get_uic_cmd_result(struct ufs_hba *hba)
  287. {
  288. return readl(hba->mmio_base + REG_UIC_COMMAND_ARG_2) &
  289. MASK_UIC_COMMAND_RESULT;
  290. }
  291. /**
  292. * ufshcd_free_hba_memory - Free allocated memory for LRB, request
  293. * and task lists
  294. * @hba: Pointer to adapter instance
  295. */
  296. static inline void ufshcd_free_hba_memory(struct ufs_hba *hba)
  297. {
  298. size_t utmrdl_size, utrdl_size, ucdl_size;
  299. kfree(hba->lrb);
  300. if (hba->utmrdl_base_addr) {
  301. utmrdl_size = sizeof(struct utp_task_req_desc) * hba->nutmrs;
  302. dma_free_coherent(&hba->pdev->dev, utmrdl_size,
  303. hba->utmrdl_base_addr, hba->utmrdl_dma_addr);
  304. }
  305. if (hba->utrdl_base_addr) {
  306. utrdl_size =
  307. (sizeof(struct utp_transfer_req_desc) * hba->nutrs);
  308. dma_free_coherent(&hba->pdev->dev, utrdl_size,
  309. hba->utrdl_base_addr, hba->utrdl_dma_addr);
  310. }
  311. if (hba->ucdl_base_addr) {
  312. ucdl_size =
  313. (sizeof(struct utp_transfer_cmd_desc) * hba->nutrs);
  314. dma_free_coherent(&hba->pdev->dev, ucdl_size,
  315. hba->ucdl_base_addr, hba->ucdl_dma_addr);
  316. }
  317. }
  318. /**
  319. * ufshcd_is_valid_req_rsp - checks if controller TR response is valid
  320. * @ucd_rsp_ptr: pointer to response UPIU
  321. *
  322. * This function checks the response UPIU for valid transaction type in
  323. * response field
  324. * Returns 0 on success, non-zero on failure
  325. */
  326. static inline int
  327. ufshcd_is_valid_req_rsp(struct utp_upiu_rsp *ucd_rsp_ptr)
  328. {
  329. return ((be32_to_cpu(ucd_rsp_ptr->header.dword_0) >> 24) ==
  330. UPIU_TRANSACTION_RESPONSE) ? 0 : DID_ERROR << 16;
  331. }
  332. /**
  333. * ufshcd_get_rsp_upiu_result - Get the result from response UPIU
  334. * @ucd_rsp_ptr: pointer to response UPIU
  335. *
  336. * This function gets the response status and scsi_status from response UPIU
  337. * Returns the response result code.
  338. */
  339. static inline int
  340. ufshcd_get_rsp_upiu_result(struct utp_upiu_rsp *ucd_rsp_ptr)
  341. {
  342. return be32_to_cpu(ucd_rsp_ptr->header.dword_1) & MASK_RSP_UPIU_RESULT;
  343. }
  344. /**
  345. * ufshcd_config_int_aggr - Configure interrupt aggregation values.
  346. * Currently there is no use case where we want to configure
  347. * interrupt aggregation dynamically. So to configure interrupt
  348. * aggregation, #define INT_AGGR_COUNTER_THRESHOLD_VALUE and
  349. * INT_AGGR_TIMEOUT_VALUE are used.
  350. * @hba: per adapter instance
  351. * @option: Interrupt aggregation option
  352. */
  353. static inline void
  354. ufshcd_config_int_aggr(struct ufs_hba *hba, int option)
  355. {
  356. switch (option) {
  357. case INT_AGGR_RESET:
  358. writel((INT_AGGR_ENABLE |
  359. INT_AGGR_COUNTER_AND_TIMER_RESET),
  360. (hba->mmio_base +
  361. REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL));
  362. break;
  363. case INT_AGGR_CONFIG:
  364. writel((INT_AGGR_ENABLE |
  365. INT_AGGR_PARAM_WRITE |
  366. INT_AGGR_COUNTER_THRESHOLD_VALUE |
  367. INT_AGGR_TIMEOUT_VALUE),
  368. (hba->mmio_base +
  369. REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL));
  370. break;
  371. }
  372. }
  373. /**
  374. * ufshcd_enable_run_stop_reg - Enable run-stop registers,
  375. * When run-stop registers are set to 1, it indicates the
  376. * host controller that it can process the requests
  377. * @hba: per adapter instance
  378. */
  379. static void ufshcd_enable_run_stop_reg(struct ufs_hba *hba)
  380. {
  381. writel(UTP_TASK_REQ_LIST_RUN_STOP_BIT,
  382. (hba->mmio_base +
  383. REG_UTP_TASK_REQ_LIST_RUN_STOP));
  384. writel(UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT,
  385. (hba->mmio_base +
  386. REG_UTP_TRANSFER_REQ_LIST_RUN_STOP));
  387. }
  388. /**
  389. * ufshcd_hba_stop - Send controller to reset state
  390. * @hba: per adapter instance
  391. */
  392. static inline void ufshcd_hba_stop(struct ufs_hba *hba)
  393. {
  394. writel(CONTROLLER_DISABLE, (hba->mmio_base + REG_CONTROLLER_ENABLE));
  395. }
  396. /**
  397. * ufshcd_hba_start - Start controller initialization sequence
  398. * @hba: per adapter instance
  399. */
  400. static inline void ufshcd_hba_start(struct ufs_hba *hba)
  401. {
  402. writel(CONTROLLER_ENABLE , (hba->mmio_base + REG_CONTROLLER_ENABLE));
  403. }
  404. /**
  405. * ufshcd_is_hba_active - Get controller state
  406. * @hba: per adapter instance
  407. *
  408. * Returns zero if controller is active, 1 otherwise
  409. */
  410. static inline int ufshcd_is_hba_active(struct ufs_hba *hba)
  411. {
  412. return (readl(hba->mmio_base + REG_CONTROLLER_ENABLE) & 0x1) ? 0 : 1;
  413. }
  414. /**
  415. * ufshcd_send_command - Send SCSI or device management commands
  416. * @hba: per adapter instance
  417. * @task_tag: Task tag of the command
  418. */
  419. static inline
  420. void ufshcd_send_command(struct ufs_hba *hba, unsigned int task_tag)
  421. {
  422. __set_bit(task_tag, &hba->outstanding_reqs);
  423. writel((1 << task_tag),
  424. (hba->mmio_base + REG_UTP_TRANSFER_REQ_DOOR_BELL));
  425. }
  426. /**
  427. * ufshcd_copy_sense_data - Copy sense data in case of check condition
  428. * @lrb - pointer to local reference block
  429. */
  430. static inline void ufshcd_copy_sense_data(struct ufshcd_lrb *lrbp)
  431. {
  432. int len;
  433. if (lrbp->sense_buffer) {
  434. len = be16_to_cpu(lrbp->ucd_rsp_ptr->sense_data_len);
  435. memcpy(lrbp->sense_buffer,
  436. lrbp->ucd_rsp_ptr->sense_data,
  437. min_t(int, len, SCSI_SENSE_BUFFERSIZE));
  438. }
  439. }
  440. /**
  441. * ufshcd_hba_capabilities - Read controller capabilities
  442. * @hba: per adapter instance
  443. */
  444. static inline void ufshcd_hba_capabilities(struct ufs_hba *hba)
  445. {
  446. hba->capabilities =
  447. readl(hba->mmio_base + REG_CONTROLLER_CAPABILITIES);
  448. /* nutrs and nutmrs are 0 based values */
  449. hba->nutrs = (hba->capabilities & MASK_TRANSFER_REQUESTS_SLOTS) + 1;
  450. hba->nutmrs =
  451. ((hba->capabilities & MASK_TASK_MANAGEMENT_REQUEST_SLOTS) >> 16) + 1;
  452. }
  453. /**
  454. * ufshcd_send_uic_command - Send UIC commands to unipro layers
  455. * @hba: per adapter instance
  456. * @uic_command: UIC command
  457. */
  458. static inline void
  459. ufshcd_send_uic_command(struct ufs_hba *hba, struct uic_command *uic_cmnd)
  460. {
  461. /* Write Args */
  462. writel(uic_cmnd->argument1,
  463. (hba->mmio_base + REG_UIC_COMMAND_ARG_1));
  464. writel(uic_cmnd->argument2,
  465. (hba->mmio_base + REG_UIC_COMMAND_ARG_2));
  466. writel(uic_cmnd->argument3,
  467. (hba->mmio_base + REG_UIC_COMMAND_ARG_3));
  468. /* Write UIC Cmd */
  469. writel((uic_cmnd->command & COMMAND_OPCODE_MASK),
  470. (hba->mmio_base + REG_UIC_COMMAND));
  471. }
  472. /**
  473. * ufshcd_map_sg - Map scatter-gather list to prdt
  474. * @lrbp - pointer to local reference block
  475. *
  476. * Returns 0 in case of success, non-zero value in case of failure
  477. */
  478. static int ufshcd_map_sg(struct ufshcd_lrb *lrbp)
  479. {
  480. struct ufshcd_sg_entry *prd_table;
  481. struct scatterlist *sg;
  482. struct scsi_cmnd *cmd;
  483. int sg_segments;
  484. int i;
  485. cmd = lrbp->cmd;
  486. sg_segments = scsi_dma_map(cmd);
  487. if (sg_segments < 0)
  488. return sg_segments;
  489. if (sg_segments) {
  490. lrbp->utr_descriptor_ptr->prd_table_length =
  491. cpu_to_le16((u16) (sg_segments));
  492. prd_table = (struct ufshcd_sg_entry *)lrbp->ucd_prdt_ptr;
  493. scsi_for_each_sg(cmd, sg, sg_segments, i) {
  494. prd_table[i].size =
  495. cpu_to_le32(((u32) sg_dma_len(sg))-1);
  496. prd_table[i].base_addr =
  497. cpu_to_le32(lower_32_bits(sg->dma_address));
  498. prd_table[i].upper_addr =
  499. cpu_to_le32(upper_32_bits(sg->dma_address));
  500. }
  501. } else {
  502. lrbp->utr_descriptor_ptr->prd_table_length = 0;
  503. }
  504. return 0;
  505. }
  506. /**
  507. * ufshcd_int_config - enable/disable interrupts
  508. * @hba: per adapter instance
  509. * @option: interrupt option
  510. */
  511. static void ufshcd_int_config(struct ufs_hba *hba, u32 option)
  512. {
  513. switch (option) {
  514. case UFSHCD_INT_ENABLE:
  515. writel(hba->int_enable_mask,
  516. (hba->mmio_base + REG_INTERRUPT_ENABLE));
  517. break;
  518. case UFSHCD_INT_DISABLE:
  519. if (hba->ufs_version == UFSHCI_VERSION_10)
  520. writel(INTERRUPT_DISABLE_MASK_10,
  521. (hba->mmio_base + REG_INTERRUPT_ENABLE));
  522. else
  523. writel(INTERRUPT_DISABLE_MASK_11,
  524. (hba->mmio_base + REG_INTERRUPT_ENABLE));
  525. break;
  526. }
  527. }
  528. /**
  529. * ufshcd_compose_upiu - form UFS Protocol Information Unit(UPIU)
  530. * @lrb - pointer to local reference block
  531. */
  532. static void ufshcd_compose_upiu(struct ufshcd_lrb *lrbp)
  533. {
  534. struct utp_transfer_req_desc *req_desc;
  535. struct utp_upiu_cmd *ucd_cmd_ptr;
  536. u32 data_direction;
  537. u32 upiu_flags;
  538. ucd_cmd_ptr = lrbp->ucd_cmd_ptr;
  539. req_desc = lrbp->utr_descriptor_ptr;
  540. switch (lrbp->command_type) {
  541. case UTP_CMD_TYPE_SCSI:
  542. if (lrbp->cmd->sc_data_direction == DMA_FROM_DEVICE) {
  543. data_direction = UTP_DEVICE_TO_HOST;
  544. upiu_flags = UPIU_CMD_FLAGS_READ;
  545. } else if (lrbp->cmd->sc_data_direction == DMA_TO_DEVICE) {
  546. data_direction = UTP_HOST_TO_DEVICE;
  547. upiu_flags = UPIU_CMD_FLAGS_WRITE;
  548. } else {
  549. data_direction = UTP_NO_DATA_TRANSFER;
  550. upiu_flags = UPIU_CMD_FLAGS_NONE;
  551. }
  552. /* Transfer request descriptor header fields */
  553. req_desc->header.dword_0 =
  554. cpu_to_le32(data_direction | UTP_SCSI_COMMAND);
  555. /*
  556. * assigning invalid value for command status. Controller
  557. * updates OCS on command completion, with the command
  558. * status
  559. */
  560. req_desc->header.dword_2 =
  561. cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
  562. /* command descriptor fields */
  563. ucd_cmd_ptr->header.dword_0 =
  564. cpu_to_be32(UPIU_HEADER_DWORD(UPIU_TRANSACTION_COMMAND,
  565. upiu_flags,
  566. lrbp->lun,
  567. lrbp->task_tag));
  568. ucd_cmd_ptr->header.dword_1 =
  569. cpu_to_be32(
  570. UPIU_HEADER_DWORD(UPIU_COMMAND_SET_TYPE_SCSI,
  571. 0,
  572. 0,
  573. 0));
  574. /* Total EHS length and Data segment length will be zero */
  575. ucd_cmd_ptr->header.dword_2 = 0;
  576. ucd_cmd_ptr->exp_data_transfer_len =
  577. cpu_to_be32(lrbp->cmd->transfersize);
  578. memcpy(ucd_cmd_ptr->cdb,
  579. lrbp->cmd->cmnd,
  580. (min_t(unsigned short,
  581. lrbp->cmd->cmd_len,
  582. MAX_CDB_SIZE)));
  583. break;
  584. case UTP_CMD_TYPE_DEV_MANAGE:
  585. /* For query function implementation */
  586. break;
  587. case UTP_CMD_TYPE_UFS:
  588. /* For UFS native command implementation */
  589. break;
  590. } /* end of switch */
  591. }
  592. /**
  593. * ufshcd_queuecommand - main entry point for SCSI requests
  594. * @cmd: command from SCSI Midlayer
  595. * @done: call back function
  596. *
  597. * Returns 0 for success, non-zero in case of failure
  598. */
  599. static int ufshcd_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
  600. {
  601. struct ufshcd_lrb *lrbp;
  602. struct ufs_hba *hba;
  603. unsigned long flags;
  604. int tag;
  605. int err = 0;
  606. hba = shost_priv(host);
  607. tag = cmd->request->tag;
  608. if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL) {
  609. err = SCSI_MLQUEUE_HOST_BUSY;
  610. goto out;
  611. }
  612. lrbp = &hba->lrb[tag];
  613. lrbp->cmd = cmd;
  614. lrbp->sense_bufflen = SCSI_SENSE_BUFFERSIZE;
  615. lrbp->sense_buffer = cmd->sense_buffer;
  616. lrbp->task_tag = tag;
  617. lrbp->lun = cmd->device->lun;
  618. lrbp->command_type = UTP_CMD_TYPE_SCSI;
  619. /* form UPIU before issuing the command */
  620. ufshcd_compose_upiu(lrbp);
  621. err = ufshcd_map_sg(lrbp);
  622. if (err)
  623. goto out;
  624. /* issue command to the controller */
  625. spin_lock_irqsave(hba->host->host_lock, flags);
  626. ufshcd_send_command(hba, tag);
  627. spin_unlock_irqrestore(hba->host->host_lock, flags);
  628. out:
  629. return err;
  630. }
  631. /**
  632. * ufshcd_memory_alloc - allocate memory for host memory space data structures
  633. * @hba: per adapter instance
  634. *
  635. * 1. Allocate DMA memory for Command Descriptor array
  636. * Each command descriptor consist of Command UPIU, Response UPIU and PRDT
  637. * 2. Allocate DMA memory for UTP Transfer Request Descriptor List (UTRDL).
  638. * 3. Allocate DMA memory for UTP Task Management Request Descriptor List
  639. * (UTMRDL)
  640. * 4. Allocate memory for local reference block(lrb).
  641. *
  642. * Returns 0 for success, non-zero in case of failure
  643. */
  644. static int ufshcd_memory_alloc(struct ufs_hba *hba)
  645. {
  646. size_t utmrdl_size, utrdl_size, ucdl_size;
  647. /* Allocate memory for UTP command descriptors */
  648. ucdl_size = (sizeof(struct utp_transfer_cmd_desc) * hba->nutrs);
  649. hba->ucdl_base_addr = dma_alloc_coherent(&hba->pdev->dev,
  650. ucdl_size,
  651. &hba->ucdl_dma_addr,
  652. GFP_KERNEL);
  653. /*
  654. * UFSHCI requires UTP command descriptor to be 128 byte aligned.
  655. * make sure hba->ucdl_dma_addr is aligned to PAGE_SIZE
  656. * if hba->ucdl_dma_addr is aligned to PAGE_SIZE, then it will
  657. * be aligned to 128 bytes as well
  658. */
  659. if (!hba->ucdl_base_addr ||
  660. WARN_ON(hba->ucdl_dma_addr & (PAGE_SIZE - 1))) {
  661. dev_err(&hba->pdev->dev,
  662. "Command Descriptor Memory allocation failed\n");
  663. goto out;
  664. }
  665. /*
  666. * Allocate memory for UTP Transfer descriptors
  667. * UFSHCI requires 1024 byte alignment of UTRD
  668. */
  669. utrdl_size = (sizeof(struct utp_transfer_req_desc) * hba->nutrs);
  670. hba->utrdl_base_addr = dma_alloc_coherent(&hba->pdev->dev,
  671. utrdl_size,
  672. &hba->utrdl_dma_addr,
  673. GFP_KERNEL);
  674. if (!hba->utrdl_base_addr ||
  675. WARN_ON(hba->utrdl_dma_addr & (PAGE_SIZE - 1))) {
  676. dev_err(&hba->pdev->dev,
  677. "Transfer Descriptor Memory allocation failed\n");
  678. goto out;
  679. }
  680. /*
  681. * Allocate memory for UTP Task Management descriptors
  682. * UFSHCI requires 1024 byte alignment of UTMRD
  683. */
  684. utmrdl_size = sizeof(struct utp_task_req_desc) * hba->nutmrs;
  685. hba->utmrdl_base_addr = dma_alloc_coherent(&hba->pdev->dev,
  686. utmrdl_size,
  687. &hba->utmrdl_dma_addr,
  688. GFP_KERNEL);
  689. if (!hba->utmrdl_base_addr ||
  690. WARN_ON(hba->utmrdl_dma_addr & (PAGE_SIZE - 1))) {
  691. dev_err(&hba->pdev->dev,
  692. "Task Management Descriptor Memory allocation failed\n");
  693. goto out;
  694. }
  695. /* Allocate memory for local reference block */
  696. hba->lrb = kcalloc(hba->nutrs, sizeof(struct ufshcd_lrb), GFP_KERNEL);
  697. if (!hba->lrb) {
  698. dev_err(&hba->pdev->dev, "LRB Memory allocation failed\n");
  699. goto out;
  700. }
  701. return 0;
  702. out:
  703. ufshcd_free_hba_memory(hba);
  704. return -ENOMEM;
  705. }
  706. /**
  707. * ufshcd_host_memory_configure - configure local reference block with
  708. * memory offsets
  709. * @hba: per adapter instance
  710. *
  711. * Configure Host memory space
  712. * 1. Update Corresponding UTRD.UCDBA and UTRD.UCDBAU with UCD DMA
  713. * address.
  714. * 2. Update each UTRD with Response UPIU offset, Response UPIU length
  715. * and PRDT offset.
  716. * 3. Save the corresponding addresses of UTRD, UCD.CMD, UCD.RSP and UCD.PRDT
  717. * into local reference block.
  718. */
  719. static void ufshcd_host_memory_configure(struct ufs_hba *hba)
  720. {
  721. struct utp_transfer_cmd_desc *cmd_descp;
  722. struct utp_transfer_req_desc *utrdlp;
  723. dma_addr_t cmd_desc_dma_addr;
  724. dma_addr_t cmd_desc_element_addr;
  725. u16 response_offset;
  726. u16 prdt_offset;
  727. int cmd_desc_size;
  728. int i;
  729. utrdlp = hba->utrdl_base_addr;
  730. cmd_descp = hba->ucdl_base_addr;
  731. response_offset =
  732. offsetof(struct utp_transfer_cmd_desc, response_upiu);
  733. prdt_offset =
  734. offsetof(struct utp_transfer_cmd_desc, prd_table);
  735. cmd_desc_size = sizeof(struct utp_transfer_cmd_desc);
  736. cmd_desc_dma_addr = hba->ucdl_dma_addr;
  737. for (i = 0; i < hba->nutrs; i++) {
  738. /* Configure UTRD with command descriptor base address */
  739. cmd_desc_element_addr =
  740. (cmd_desc_dma_addr + (cmd_desc_size * i));
  741. utrdlp[i].command_desc_base_addr_lo =
  742. cpu_to_le32(lower_32_bits(cmd_desc_element_addr));
  743. utrdlp[i].command_desc_base_addr_hi =
  744. cpu_to_le32(upper_32_bits(cmd_desc_element_addr));
  745. /* Response upiu and prdt offset should be in double words */
  746. utrdlp[i].response_upiu_offset =
  747. cpu_to_le16((response_offset >> 2));
  748. utrdlp[i].prd_table_offset =
  749. cpu_to_le16((prdt_offset >> 2));
  750. utrdlp[i].response_upiu_length =
  751. cpu_to_le16(ALIGNED_UPIU_SIZE);
  752. hba->lrb[i].utr_descriptor_ptr = (utrdlp + i);
  753. hba->lrb[i].ucd_cmd_ptr =
  754. (struct utp_upiu_cmd *)(cmd_descp + i);
  755. hba->lrb[i].ucd_rsp_ptr =
  756. (struct utp_upiu_rsp *)cmd_descp[i].response_upiu;
  757. hba->lrb[i].ucd_prdt_ptr =
  758. (struct ufshcd_sg_entry *)cmd_descp[i].prd_table;
  759. }
  760. }
  761. /**
  762. * ufshcd_dme_link_startup - Notify Unipro to perform link startup
  763. * @hba: per adapter instance
  764. *
  765. * UIC_CMD_DME_LINK_STARTUP command must be issued to Unipro layer,
  766. * in order to initialize the Unipro link startup procedure.
  767. * Once the Unipro links are up, the device connected to the controller
  768. * is detected.
  769. *
  770. * Returns 0 on success, non-zero value on failure
  771. */
  772. static int ufshcd_dme_link_startup(struct ufs_hba *hba)
  773. {
  774. struct uic_command *uic_cmd;
  775. unsigned long flags;
  776. /* check if controller is ready to accept UIC commands */
  777. if (((readl(hba->mmio_base + REG_CONTROLLER_STATUS)) &
  778. UIC_COMMAND_READY) == 0x0) {
  779. dev_err(&hba->pdev->dev,
  780. "Controller not ready"
  781. " to accept UIC commands\n");
  782. return -EIO;
  783. }
  784. spin_lock_irqsave(hba->host->host_lock, flags);
  785. /* form UIC command */
  786. uic_cmd = &hba->active_uic_cmd;
  787. uic_cmd->command = UIC_CMD_DME_LINK_STARTUP;
  788. uic_cmd->argument1 = 0;
  789. uic_cmd->argument2 = 0;
  790. uic_cmd->argument3 = 0;
  791. /* enable UIC related interrupts */
  792. hba->int_enable_mask |= UIC_COMMAND_COMPL;
  793. ufshcd_int_config(hba, UFSHCD_INT_ENABLE);
  794. /* sending UIC commands to controller */
  795. ufshcd_send_uic_command(hba, uic_cmd);
  796. spin_unlock_irqrestore(hba->host->host_lock, flags);
  797. return 0;
  798. }
  799. /**
  800. * ufshcd_make_hba_operational - Make UFS controller operational
  801. * @hba: per adapter instance
  802. *
  803. * To bring UFS host controller to operational state,
  804. * 1. Check if device is present
  805. * 2. Configure run-stop-registers
  806. * 3. Enable required interrupts
  807. * 4. Configure interrupt aggregation
  808. *
  809. * Returns 0 on success, non-zero value on failure
  810. */
  811. static int ufshcd_make_hba_operational(struct ufs_hba *hba)
  812. {
  813. int err = 0;
  814. u32 reg;
  815. /* check if device present */
  816. reg = readl((hba->mmio_base + REG_CONTROLLER_STATUS));
  817. if (ufshcd_is_device_present(reg)) {
  818. dev_err(&hba->pdev->dev, "cc: Device not present\n");
  819. err = -ENXIO;
  820. goto out;
  821. }
  822. /*
  823. * UCRDY, UTMRLDY and UTRLRDY bits must be 1
  824. * DEI, HEI bits must be 0
  825. */
  826. if (!(ufshcd_get_lists_status(reg))) {
  827. ufshcd_enable_run_stop_reg(hba);
  828. } else {
  829. dev_err(&hba->pdev->dev,
  830. "Host controller not ready to process requests");
  831. err = -EIO;
  832. goto out;
  833. }
  834. /* Enable required interrupts */
  835. hba->int_enable_mask |= (UTP_TRANSFER_REQ_COMPL |
  836. UIC_ERROR |
  837. UTP_TASK_REQ_COMPL |
  838. DEVICE_FATAL_ERROR |
  839. CONTROLLER_FATAL_ERROR |
  840. SYSTEM_BUS_FATAL_ERROR);
  841. ufshcd_int_config(hba, UFSHCD_INT_ENABLE);
  842. /* Configure interrupt aggregation */
  843. ufshcd_config_int_aggr(hba, INT_AGGR_CONFIG);
  844. if (hba->ufshcd_state == UFSHCD_STATE_RESET)
  845. scsi_unblock_requests(hba->host);
  846. hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
  847. scsi_scan_host(hba->host);
  848. out:
  849. return err;
  850. }
  851. /**
  852. * ufshcd_hba_enable - initialize the controller
  853. * @hba: per adapter instance
  854. *
  855. * The controller resets itself and controller firmware initialization
  856. * sequence kicks off. When controller is ready it will set
  857. * the Host Controller Enable bit to 1.
  858. *
  859. * Returns 0 on success, non-zero value on failure
  860. */
  861. static int ufshcd_hba_enable(struct ufs_hba *hba)
  862. {
  863. int retry;
  864. /*
  865. * msleep of 1 and 5 used in this function might result in msleep(20),
  866. * but it was necessary to send the UFS FPGA to reset mode during
  867. * development and testing of this driver. msleep can be changed to
  868. * mdelay and retry count can be reduced based on the controller.
  869. */
  870. if (!ufshcd_is_hba_active(hba)) {
  871. /* change controller state to "reset state" */
  872. ufshcd_hba_stop(hba);
  873. /*
  874. * This delay is based on the testing done with UFS host
  875. * controller FPGA. The delay can be changed based on the
  876. * host controller used.
  877. */
  878. msleep(5);
  879. }
  880. /* start controller initialization sequence */
  881. ufshcd_hba_start(hba);
  882. /*
  883. * To initialize a UFS host controller HCE bit must be set to 1.
  884. * During initialization the HCE bit value changes from 1->0->1.
  885. * When the host controller completes initialization sequence
  886. * it sets the value of HCE bit to 1. The same HCE bit is read back
  887. * to check if the controller has completed initialization sequence.
  888. * So without this delay the value HCE = 1, set in the previous
  889. * instruction might be read back.
  890. * This delay can be changed based on the controller.
  891. */
  892. msleep(1);
  893. /* wait for the host controller to complete initialization */
  894. retry = 10;
  895. while (ufshcd_is_hba_active(hba)) {
  896. if (retry) {
  897. retry--;
  898. } else {
  899. dev_err(&hba->pdev->dev,
  900. "Controller enable failed\n");
  901. return -EIO;
  902. }
  903. msleep(5);
  904. }
  905. return 0;
  906. }
  907. /**
  908. * ufshcd_initialize_hba - start the initialization process
  909. * @hba: per adapter instance
  910. *
  911. * 1. Enable the controller via ufshcd_hba_enable.
  912. * 2. Program the Transfer Request List Address with the starting address of
  913. * UTRDL.
  914. * 3. Program the Task Management Request List Address with starting address
  915. * of UTMRDL.
  916. *
  917. * Returns 0 on success, non-zero value on failure.
  918. */
  919. static int ufshcd_initialize_hba(struct ufs_hba *hba)
  920. {
  921. if (ufshcd_hba_enable(hba))
  922. return -EIO;
  923. /* Configure UTRL and UTMRL base address registers */
  924. writel(lower_32_bits(hba->utrdl_dma_addr),
  925. (hba->mmio_base + REG_UTP_TRANSFER_REQ_LIST_BASE_L));
  926. writel(upper_32_bits(hba->utrdl_dma_addr),
  927. (hba->mmio_base + REG_UTP_TRANSFER_REQ_LIST_BASE_H));
  928. writel(lower_32_bits(hba->utmrdl_dma_addr),
  929. (hba->mmio_base + REG_UTP_TASK_REQ_LIST_BASE_L));
  930. writel(upper_32_bits(hba->utmrdl_dma_addr),
  931. (hba->mmio_base + REG_UTP_TASK_REQ_LIST_BASE_H));
  932. /* Initialize unipro link startup procedure */
  933. return ufshcd_dme_link_startup(hba);
  934. }
  935. /**
  936. * ufshcd_do_reset - reset the host controller
  937. * @hba: per adapter instance
  938. *
  939. * Returns SUCCESS/FAILED
  940. */
  941. static int ufshcd_do_reset(struct ufs_hba *hba)
  942. {
  943. struct ufshcd_lrb *lrbp;
  944. unsigned long flags;
  945. int tag;
  946. /* block commands from midlayer */
  947. scsi_block_requests(hba->host);
  948. spin_lock_irqsave(hba->host->host_lock, flags);
  949. hba->ufshcd_state = UFSHCD_STATE_RESET;
  950. /* send controller to reset state */
  951. ufshcd_hba_stop(hba);
  952. spin_unlock_irqrestore(hba->host->host_lock, flags);
  953. /* abort outstanding commands */
  954. for (tag = 0; tag < hba->nutrs; tag++) {
  955. if (test_bit(tag, &hba->outstanding_reqs)) {
  956. lrbp = &hba->lrb[tag];
  957. scsi_dma_unmap(lrbp->cmd);
  958. lrbp->cmd->result = DID_RESET << 16;
  959. lrbp->cmd->scsi_done(lrbp->cmd);
  960. lrbp->cmd = NULL;
  961. }
  962. }
  963. /* clear outstanding request/task bit maps */
  964. hba->outstanding_reqs = 0;
  965. hba->outstanding_tasks = 0;
  966. /* start the initialization process */
  967. if (ufshcd_initialize_hba(hba)) {
  968. dev_err(&hba->pdev->dev,
  969. "Reset: Controller initialization failed\n");
  970. return FAILED;
  971. }
  972. return SUCCESS;
  973. }
  974. /**
  975. * ufshcd_slave_alloc - handle initial SCSI device configurations
  976. * @sdev: pointer to SCSI device
  977. *
  978. * Returns success
  979. */
  980. static int ufshcd_slave_alloc(struct scsi_device *sdev)
  981. {
  982. struct ufs_hba *hba;
  983. hba = shost_priv(sdev->host);
  984. sdev->tagged_supported = 1;
  985. /* Mode sense(6) is not supported by UFS, so use Mode sense(10) */
  986. sdev->use_10_for_ms = 1;
  987. scsi_set_tag_type(sdev, MSG_SIMPLE_TAG);
  988. /*
  989. * Inform SCSI Midlayer that the LUN queue depth is same as the
  990. * controller queue depth. If a LUN queue depth is less than the
  991. * controller queue depth and if the LUN reports
  992. * SAM_STAT_TASK_SET_FULL, the LUN queue depth will be adjusted
  993. * with scsi_adjust_queue_depth.
  994. */
  995. scsi_activate_tcq(sdev, hba->nutrs);
  996. return 0;
  997. }
  998. /**
  999. * ufshcd_slave_destroy - remove SCSI device configurations
  1000. * @sdev: pointer to SCSI device
  1001. */
  1002. static void ufshcd_slave_destroy(struct scsi_device *sdev)
  1003. {
  1004. struct ufs_hba *hba;
  1005. hba = shost_priv(sdev->host);
  1006. scsi_deactivate_tcq(sdev, hba->nutrs);
  1007. }
  1008. /**
  1009. * ufshcd_task_req_compl - handle task management request completion
  1010. * @hba: per adapter instance
  1011. * @index: index of the completed request
  1012. *
  1013. * Returns SUCCESS/FAILED
  1014. */
  1015. static int ufshcd_task_req_compl(struct ufs_hba *hba, u32 index)
  1016. {
  1017. struct utp_task_req_desc *task_req_descp;
  1018. struct utp_upiu_task_rsp *task_rsp_upiup;
  1019. unsigned long flags;
  1020. int ocs_value;
  1021. int task_result;
  1022. spin_lock_irqsave(hba->host->host_lock, flags);
  1023. /* Clear completed tasks from outstanding_tasks */
  1024. __clear_bit(index, &hba->outstanding_tasks);
  1025. task_req_descp = hba->utmrdl_base_addr;
  1026. ocs_value = ufshcd_get_tmr_ocs(&task_req_descp[index]);
  1027. if (ocs_value == OCS_SUCCESS) {
  1028. task_rsp_upiup = (struct utp_upiu_task_rsp *)
  1029. task_req_descp[index].task_rsp_upiu;
  1030. task_result = be32_to_cpu(task_rsp_upiup->header.dword_1);
  1031. task_result = ((task_result & MASK_TASK_RESPONSE) >> 8);
  1032. if (task_result != UPIU_TASK_MANAGEMENT_FUNC_COMPL &&
  1033. task_result != UPIU_TASK_MANAGEMENT_FUNC_SUCCEEDED)
  1034. task_result = FAILED;
  1035. } else {
  1036. task_result = FAILED;
  1037. dev_err(&hba->pdev->dev,
  1038. "trc: Invalid ocs = %x\n", ocs_value);
  1039. }
  1040. spin_unlock_irqrestore(hba->host->host_lock, flags);
  1041. return task_result;
  1042. }
  1043. /**
  1044. * ufshcd_adjust_lun_qdepth - Update LUN queue depth if device responds with
  1045. * SAM_STAT_TASK_SET_FULL SCSI command status.
  1046. * @cmd: pointer to SCSI command
  1047. */
  1048. static void ufshcd_adjust_lun_qdepth(struct scsi_cmnd *cmd)
  1049. {
  1050. struct ufs_hba *hba;
  1051. int i;
  1052. int lun_qdepth = 0;
  1053. hba = shost_priv(cmd->device->host);
  1054. /*
  1055. * LUN queue depth can be obtained by counting outstanding commands
  1056. * on the LUN.
  1057. */
  1058. for (i = 0; i < hba->nutrs; i++) {
  1059. if (test_bit(i, &hba->outstanding_reqs)) {
  1060. /*
  1061. * Check if the outstanding command belongs
  1062. * to the LUN which reported SAM_STAT_TASK_SET_FULL.
  1063. */
  1064. if (cmd->device->lun == hba->lrb[i].lun)
  1065. lun_qdepth++;
  1066. }
  1067. }
  1068. /*
  1069. * LUN queue depth will be total outstanding commands, except the
  1070. * command for which the LUN reported SAM_STAT_TASK_SET_FULL.
  1071. */
  1072. scsi_adjust_queue_depth(cmd->device, MSG_SIMPLE_TAG, lun_qdepth - 1);
  1073. }
  1074. /**
  1075. * ufshcd_scsi_cmd_status - Update SCSI command result based on SCSI status
  1076. * @lrb: pointer to local reference block of completed command
  1077. * @scsi_status: SCSI command status
  1078. *
  1079. * Returns value base on SCSI command status
  1080. */
  1081. static inline int
  1082. ufshcd_scsi_cmd_status(struct ufshcd_lrb *lrbp, int scsi_status)
  1083. {
  1084. int result = 0;
  1085. switch (scsi_status) {
  1086. case SAM_STAT_GOOD:
  1087. result |= DID_OK << 16 |
  1088. COMMAND_COMPLETE << 8 |
  1089. SAM_STAT_GOOD;
  1090. break;
  1091. case SAM_STAT_CHECK_CONDITION:
  1092. result |= DID_OK << 16 |
  1093. COMMAND_COMPLETE << 8 |
  1094. SAM_STAT_CHECK_CONDITION;
  1095. ufshcd_copy_sense_data(lrbp);
  1096. break;
  1097. case SAM_STAT_BUSY:
  1098. result |= SAM_STAT_BUSY;
  1099. break;
  1100. case SAM_STAT_TASK_SET_FULL:
  1101. /*
  1102. * If a LUN reports SAM_STAT_TASK_SET_FULL, then the LUN queue
  1103. * depth needs to be adjusted to the exact number of
  1104. * outstanding commands the LUN can handle at any given time.
  1105. */
  1106. ufshcd_adjust_lun_qdepth(lrbp->cmd);
  1107. result |= SAM_STAT_TASK_SET_FULL;
  1108. break;
  1109. case SAM_STAT_TASK_ABORTED:
  1110. result |= SAM_STAT_TASK_ABORTED;
  1111. break;
  1112. default:
  1113. result |= DID_ERROR << 16;
  1114. break;
  1115. } /* end of switch */
  1116. return result;
  1117. }
  1118. /**
  1119. * ufshcd_transfer_rsp_status - Get overall status of the response
  1120. * @hba: per adapter instance
  1121. * @lrb: pointer to local reference block of completed command
  1122. *
  1123. * Returns result of the command to notify SCSI midlayer
  1124. */
  1125. static inline int
  1126. ufshcd_transfer_rsp_status(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
  1127. {
  1128. int result = 0;
  1129. int scsi_status;
  1130. int ocs;
  1131. /* overall command status of utrd */
  1132. ocs = ufshcd_get_tr_ocs(lrbp);
  1133. switch (ocs) {
  1134. case OCS_SUCCESS:
  1135. /* check if the returned transfer response is valid */
  1136. result = ufshcd_is_valid_req_rsp(lrbp->ucd_rsp_ptr);
  1137. if (result) {
  1138. dev_err(&hba->pdev->dev,
  1139. "Invalid response = %x\n", result);
  1140. break;
  1141. }
  1142. /*
  1143. * get the response UPIU result to extract
  1144. * the SCSI command status
  1145. */
  1146. result = ufshcd_get_rsp_upiu_result(lrbp->ucd_rsp_ptr);
  1147. /*
  1148. * get the result based on SCSI status response
  1149. * to notify the SCSI midlayer of the command status
  1150. */
  1151. scsi_status = result & MASK_SCSI_STATUS;
  1152. result = ufshcd_scsi_cmd_status(lrbp, scsi_status);
  1153. break;
  1154. case OCS_ABORTED:
  1155. result |= DID_ABORT << 16;
  1156. break;
  1157. case OCS_INVALID_CMD_TABLE_ATTR:
  1158. case OCS_INVALID_PRDT_ATTR:
  1159. case OCS_MISMATCH_DATA_BUF_SIZE:
  1160. case OCS_MISMATCH_RESP_UPIU_SIZE:
  1161. case OCS_PEER_COMM_FAILURE:
  1162. case OCS_FATAL_ERROR:
  1163. default:
  1164. result |= DID_ERROR << 16;
  1165. dev_err(&hba->pdev->dev,
  1166. "OCS error from controller = %x\n", ocs);
  1167. break;
  1168. } /* end of switch */
  1169. return result;
  1170. }
  1171. /**
  1172. * ufshcd_transfer_req_compl - handle SCSI and query command completion
  1173. * @hba: per adapter instance
  1174. */
  1175. static void ufshcd_transfer_req_compl(struct ufs_hba *hba)
  1176. {
  1177. struct ufshcd_lrb *lrb;
  1178. unsigned long completed_reqs;
  1179. u32 tr_doorbell;
  1180. int result;
  1181. int index;
  1182. lrb = hba->lrb;
  1183. tr_doorbell =
  1184. readl(hba->mmio_base + REG_UTP_TRANSFER_REQ_DOOR_BELL);
  1185. completed_reqs = tr_doorbell ^ hba->outstanding_reqs;
  1186. for (index = 0; index < hba->nutrs; index++) {
  1187. if (test_bit(index, &completed_reqs)) {
  1188. result = ufshcd_transfer_rsp_status(hba, &lrb[index]);
  1189. if (lrb[index].cmd) {
  1190. scsi_dma_unmap(lrb[index].cmd);
  1191. lrb[index].cmd->result = result;
  1192. lrb[index].cmd->scsi_done(lrb[index].cmd);
  1193. /* Mark completed command as NULL in LRB */
  1194. lrb[index].cmd = NULL;
  1195. }
  1196. } /* end of if */
  1197. } /* end of for */
  1198. /* clear corresponding bits of completed commands */
  1199. hba->outstanding_reqs ^= completed_reqs;
  1200. /* Reset interrupt aggregation counters */
  1201. ufshcd_config_int_aggr(hba, INT_AGGR_RESET);
  1202. }
  1203. /**
  1204. * ufshcd_uic_cc_handler - handle UIC command completion
  1205. * @work: pointer to a work queue structure
  1206. *
  1207. * Returns 0 on success, non-zero value on failure
  1208. */
  1209. static void ufshcd_uic_cc_handler (struct work_struct *work)
  1210. {
  1211. struct ufs_hba *hba;
  1212. hba = container_of(work, struct ufs_hba, uic_workq);
  1213. if ((hba->active_uic_cmd.command == UIC_CMD_DME_LINK_STARTUP) &&
  1214. !(ufshcd_get_uic_cmd_result(hba))) {
  1215. if (ufshcd_make_hba_operational(hba))
  1216. dev_err(&hba->pdev->dev,
  1217. "cc: hba not operational state\n");
  1218. return;
  1219. }
  1220. }
  1221. /**
  1222. * ufshcd_fatal_err_handler - handle fatal errors
  1223. * @hba: per adapter instance
  1224. */
  1225. static void ufshcd_fatal_err_handler(struct work_struct *work)
  1226. {
  1227. struct ufs_hba *hba;
  1228. hba = container_of(work, struct ufs_hba, feh_workq);
  1229. /* check if reset is already in progress */
  1230. if (hba->ufshcd_state != UFSHCD_STATE_RESET)
  1231. ufshcd_do_reset(hba);
  1232. }
  1233. /**
  1234. * ufshcd_err_handler - Check for fatal errors
  1235. * @work: pointer to a work queue structure
  1236. */
  1237. static void ufshcd_err_handler(struct ufs_hba *hba)
  1238. {
  1239. u32 reg;
  1240. if (hba->errors & INT_FATAL_ERRORS)
  1241. goto fatal_eh;
  1242. if (hba->errors & UIC_ERROR) {
  1243. reg = readl(hba->mmio_base +
  1244. REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER);
  1245. if (reg & UIC_DATA_LINK_LAYER_ERROR_PA_INIT)
  1246. goto fatal_eh;
  1247. }
  1248. return;
  1249. fatal_eh:
  1250. hba->ufshcd_state = UFSHCD_STATE_ERROR;
  1251. schedule_work(&hba->feh_workq);
  1252. }
  1253. /**
  1254. * ufshcd_tmc_handler - handle task management function completion
  1255. * @hba: per adapter instance
  1256. */
  1257. static void ufshcd_tmc_handler(struct ufs_hba *hba)
  1258. {
  1259. u32 tm_doorbell;
  1260. tm_doorbell = readl(hba->mmio_base + REG_UTP_TASK_REQ_DOOR_BELL);
  1261. hba->tm_condition = tm_doorbell ^ hba->outstanding_tasks;
  1262. wake_up_interruptible(&hba->ufshcd_tm_wait_queue);
  1263. }
  1264. /**
  1265. * ufshcd_sl_intr - Interrupt service routine
  1266. * @hba: per adapter instance
  1267. * @intr_status: contains interrupts generated by the controller
  1268. */
  1269. static void ufshcd_sl_intr(struct ufs_hba *hba, u32 intr_status)
  1270. {
  1271. hba->errors = UFSHCD_ERROR_MASK & intr_status;
  1272. if (hba->errors)
  1273. ufshcd_err_handler(hba);
  1274. if (intr_status & UIC_COMMAND_COMPL)
  1275. schedule_work(&hba->uic_workq);
  1276. if (intr_status & UTP_TASK_REQ_COMPL)
  1277. ufshcd_tmc_handler(hba);
  1278. if (intr_status & UTP_TRANSFER_REQ_COMPL)
  1279. ufshcd_transfer_req_compl(hba);
  1280. }
  1281. /**
  1282. * ufshcd_intr - Main interrupt service routine
  1283. * @irq: irq number
  1284. * @__hba: pointer to adapter instance
  1285. *
  1286. * Returns IRQ_HANDLED - If interrupt is valid
  1287. * IRQ_NONE - If invalid interrupt
  1288. */
  1289. static irqreturn_t ufshcd_intr(int irq, void *__hba)
  1290. {
  1291. u32 intr_status;
  1292. irqreturn_t retval = IRQ_NONE;
  1293. struct ufs_hba *hba = __hba;
  1294. spin_lock(hba->host->host_lock);
  1295. intr_status = readl(hba->mmio_base + REG_INTERRUPT_STATUS);
  1296. if (intr_status) {
  1297. ufshcd_sl_intr(hba, intr_status);
  1298. /* If UFSHCI 1.0 then clear interrupt status register */
  1299. if (hba->ufs_version == UFSHCI_VERSION_10)
  1300. writel(intr_status,
  1301. (hba->mmio_base + REG_INTERRUPT_STATUS));
  1302. retval = IRQ_HANDLED;
  1303. }
  1304. spin_unlock(hba->host->host_lock);
  1305. return retval;
  1306. }
  1307. /**
  1308. * ufshcd_issue_tm_cmd - issues task management commands to controller
  1309. * @hba: per adapter instance
  1310. * @lrbp: pointer to local reference block
  1311. *
  1312. * Returns SUCCESS/FAILED
  1313. */
  1314. static int
  1315. ufshcd_issue_tm_cmd(struct ufs_hba *hba,
  1316. struct ufshcd_lrb *lrbp,
  1317. u8 tm_function)
  1318. {
  1319. struct utp_task_req_desc *task_req_descp;
  1320. struct utp_upiu_task_req *task_req_upiup;
  1321. struct Scsi_Host *host;
  1322. unsigned long flags;
  1323. int free_slot = 0;
  1324. int err;
  1325. host = hba->host;
  1326. spin_lock_irqsave(host->host_lock, flags);
  1327. /* If task management queue is full */
  1328. free_slot = ufshcd_get_tm_free_slot(hba);
  1329. if (free_slot >= hba->nutmrs) {
  1330. spin_unlock_irqrestore(host->host_lock, flags);
  1331. dev_err(&hba->pdev->dev, "Task management queue full\n");
  1332. err = FAILED;
  1333. goto out;
  1334. }
  1335. task_req_descp = hba->utmrdl_base_addr;
  1336. task_req_descp += free_slot;
  1337. /* Configure task request descriptor */
  1338. task_req_descp->header.dword_0 = cpu_to_le32(UTP_REQ_DESC_INT_CMD);
  1339. task_req_descp->header.dword_2 =
  1340. cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
  1341. /* Configure task request UPIU */
  1342. task_req_upiup =
  1343. (struct utp_upiu_task_req *) task_req_descp->task_req_upiu;
  1344. task_req_upiup->header.dword_0 =
  1345. cpu_to_be32(UPIU_HEADER_DWORD(UPIU_TRANSACTION_TASK_REQ, 0,
  1346. lrbp->lun, lrbp->task_tag));
  1347. task_req_upiup->header.dword_1 =
  1348. cpu_to_be32(UPIU_HEADER_DWORD(0, tm_function, 0, 0));
  1349. task_req_upiup->input_param1 = lrbp->lun;
  1350. task_req_upiup->input_param1 =
  1351. cpu_to_be32(task_req_upiup->input_param1);
  1352. task_req_upiup->input_param2 = lrbp->task_tag;
  1353. task_req_upiup->input_param2 =
  1354. cpu_to_be32(task_req_upiup->input_param2);
  1355. /* send command to the controller */
  1356. __set_bit(free_slot, &hba->outstanding_tasks);
  1357. writel((1 << free_slot),
  1358. (hba->mmio_base + REG_UTP_TASK_REQ_DOOR_BELL));
  1359. spin_unlock_irqrestore(host->host_lock, flags);
  1360. /* wait until the task management command is completed */
  1361. err =
  1362. wait_event_interruptible_timeout(hba->ufshcd_tm_wait_queue,
  1363. (test_bit(free_slot,
  1364. &hba->tm_condition) != 0),
  1365. 60 * HZ);
  1366. if (!err) {
  1367. dev_err(&hba->pdev->dev,
  1368. "Task management command timed-out\n");
  1369. err = FAILED;
  1370. goto out;
  1371. }
  1372. clear_bit(free_slot, &hba->tm_condition);
  1373. return ufshcd_task_req_compl(hba, free_slot);
  1374. out:
  1375. return err;
  1376. }
  1377. /**
  1378. * ufshcd_device_reset - reset device and abort all the pending commands
  1379. * @cmd: SCSI command pointer
  1380. *
  1381. * Returns SUCCESS/FAILED
  1382. */
  1383. static int ufshcd_device_reset(struct scsi_cmnd *cmd)
  1384. {
  1385. struct Scsi_Host *host;
  1386. struct ufs_hba *hba;
  1387. unsigned int tag;
  1388. u32 pos;
  1389. int err;
  1390. host = cmd->device->host;
  1391. hba = shost_priv(host);
  1392. tag = cmd->request->tag;
  1393. err = ufshcd_issue_tm_cmd(hba, &hba->lrb[tag], UFS_LOGICAL_RESET);
  1394. if (err)
  1395. goto out;
  1396. for (pos = 0; pos < hba->nutrs; pos++) {
  1397. if (test_bit(pos, &hba->outstanding_reqs) &&
  1398. (hba->lrb[tag].lun == hba->lrb[pos].lun)) {
  1399. /* clear the respective UTRLCLR register bit */
  1400. ufshcd_utrl_clear(hba, pos);
  1401. clear_bit(pos, &hba->outstanding_reqs);
  1402. if (hba->lrb[pos].cmd) {
  1403. scsi_dma_unmap(hba->lrb[pos].cmd);
  1404. hba->lrb[pos].cmd->result =
  1405. DID_ABORT << 16;
  1406. hba->lrb[pos].cmd->scsi_done(cmd);
  1407. hba->lrb[pos].cmd = NULL;
  1408. }
  1409. }
  1410. } /* end of for */
  1411. out:
  1412. return err;
  1413. }
  1414. /**
  1415. * ufshcd_host_reset - Main reset function registered with scsi layer
  1416. * @cmd: SCSI command pointer
  1417. *
  1418. * Returns SUCCESS/FAILED
  1419. */
  1420. static int ufshcd_host_reset(struct scsi_cmnd *cmd)
  1421. {
  1422. struct ufs_hba *hba;
  1423. hba = shost_priv(cmd->device->host);
  1424. if (hba->ufshcd_state == UFSHCD_STATE_RESET)
  1425. return SUCCESS;
  1426. return (ufshcd_do_reset(hba) == SUCCESS) ? SUCCESS : FAILED;
  1427. }
  1428. /**
  1429. * ufshcd_abort - abort a specific command
  1430. * @cmd: SCSI command pointer
  1431. *
  1432. * Returns SUCCESS/FAILED
  1433. */
  1434. static int ufshcd_abort(struct scsi_cmnd *cmd)
  1435. {
  1436. struct Scsi_Host *host;
  1437. struct ufs_hba *hba;
  1438. unsigned long flags;
  1439. unsigned int tag;
  1440. int err;
  1441. host = cmd->device->host;
  1442. hba = shost_priv(host);
  1443. tag = cmd->request->tag;
  1444. spin_lock_irqsave(host->host_lock, flags);
  1445. /* check if command is still pending */
  1446. if (!(test_bit(tag, &hba->outstanding_reqs))) {
  1447. err = FAILED;
  1448. spin_unlock_irqrestore(host->host_lock, flags);
  1449. goto out;
  1450. }
  1451. spin_unlock_irqrestore(host->host_lock, flags);
  1452. err = ufshcd_issue_tm_cmd(hba, &hba->lrb[tag], UFS_ABORT_TASK);
  1453. if (err)
  1454. goto out;
  1455. scsi_dma_unmap(cmd);
  1456. spin_lock_irqsave(host->host_lock, flags);
  1457. /* clear the respective UTRLCLR register bit */
  1458. ufshcd_utrl_clear(hba, tag);
  1459. __clear_bit(tag, &hba->outstanding_reqs);
  1460. hba->lrb[tag].cmd = NULL;
  1461. spin_unlock_irqrestore(host->host_lock, flags);
  1462. out:
  1463. return err;
  1464. }
  1465. static struct scsi_host_template ufshcd_driver_template = {
  1466. .module = THIS_MODULE,
  1467. .name = UFSHCD,
  1468. .proc_name = UFSHCD,
  1469. .queuecommand = ufshcd_queuecommand,
  1470. .slave_alloc = ufshcd_slave_alloc,
  1471. .slave_destroy = ufshcd_slave_destroy,
  1472. .eh_abort_handler = ufshcd_abort,
  1473. .eh_device_reset_handler = ufshcd_device_reset,
  1474. .eh_host_reset_handler = ufshcd_host_reset,
  1475. .this_id = -1,
  1476. .sg_tablesize = SG_ALL,
  1477. .cmd_per_lun = UFSHCD_CMD_PER_LUN,
  1478. .can_queue = UFSHCD_CAN_QUEUE,
  1479. };
  1480. /**
  1481. * ufshcd_shutdown - main function to put the controller in reset state
  1482. * @pdev: pointer to PCI device handle
  1483. */
  1484. static void ufshcd_shutdown(struct pci_dev *pdev)
  1485. {
  1486. ufshcd_hba_stop((struct ufs_hba *)pci_get_drvdata(pdev));
  1487. }
  1488. #ifdef CONFIG_PM
  1489. /**
  1490. * ufshcd_suspend - suspend power management function
  1491. * @pdev: pointer to PCI device handle
  1492. * @state: power state
  1493. *
  1494. * Returns -ENOSYS
  1495. */
  1496. static int ufshcd_suspend(struct pci_dev *pdev, pm_message_t state)
  1497. {
  1498. /*
  1499. * TODO:
  1500. * 1. Block SCSI requests from SCSI midlayer
  1501. * 2. Change the internal driver state to non operational
  1502. * 3. Set UTRLRSR and UTMRLRSR bits to zero
  1503. * 4. Wait until outstanding commands are completed
  1504. * 5. Set HCE to zero to send the UFS host controller to reset state
  1505. */
  1506. return -ENOSYS;
  1507. }
  1508. /**
  1509. * ufshcd_resume - resume power management function
  1510. * @pdev: pointer to PCI device handle
  1511. *
  1512. * Returns -ENOSYS
  1513. */
  1514. static int ufshcd_resume(struct pci_dev *pdev)
  1515. {
  1516. /*
  1517. * TODO:
  1518. * 1. Set HCE to 1, to start the UFS host controller
  1519. * initialization process
  1520. * 2. Set UTRLRSR and UTMRLRSR bits to 1
  1521. * 3. Change the internal driver state to operational
  1522. * 4. Unblock SCSI requests from SCSI midlayer
  1523. */
  1524. return -ENOSYS;
  1525. }
  1526. #endif /* CONFIG_PM */
  1527. /**
  1528. * ufshcd_hba_free - free allocated memory for
  1529. * host memory space data structures
  1530. * @hba: per adapter instance
  1531. */
  1532. static void ufshcd_hba_free(struct ufs_hba *hba)
  1533. {
  1534. iounmap(hba->mmio_base);
  1535. ufshcd_free_hba_memory(hba);
  1536. pci_release_regions(hba->pdev);
  1537. }
  1538. /**
  1539. * ufshcd_remove - de-allocate PCI/SCSI host and host memory space
  1540. * data structure memory
  1541. * @pdev - pointer to PCI handle
  1542. */
  1543. static void ufshcd_remove(struct pci_dev *pdev)
  1544. {
  1545. struct ufs_hba *hba = pci_get_drvdata(pdev);
  1546. /* disable interrupts */
  1547. ufshcd_int_config(hba, UFSHCD_INT_DISABLE);
  1548. free_irq(pdev->irq, hba);
  1549. ufshcd_hba_stop(hba);
  1550. ufshcd_hba_free(hba);
  1551. scsi_remove_host(hba->host);
  1552. scsi_host_put(hba->host);
  1553. pci_set_drvdata(pdev, NULL);
  1554. pci_clear_master(pdev);
  1555. pci_disable_device(pdev);
  1556. }
  1557. /**
  1558. * ufshcd_set_dma_mask - Set dma mask based on the controller
  1559. * addressing capability
  1560. * @pdev: PCI device structure
  1561. *
  1562. * Returns 0 for success, non-zero for failure
  1563. */
  1564. static int ufshcd_set_dma_mask(struct ufs_hba *hba)
  1565. {
  1566. int err;
  1567. u64 dma_mask;
  1568. /*
  1569. * If controller supports 64 bit addressing mode, then set the DMA
  1570. * mask to 64-bit, else set the DMA mask to 32-bit
  1571. */
  1572. if (hba->capabilities & MASK_64_ADDRESSING_SUPPORT)
  1573. dma_mask = DMA_BIT_MASK(64);
  1574. else
  1575. dma_mask = DMA_BIT_MASK(32);
  1576. err = pci_set_dma_mask(hba->pdev, dma_mask);
  1577. if (err)
  1578. return err;
  1579. err = pci_set_consistent_dma_mask(hba->pdev, dma_mask);
  1580. return err;
  1581. }
  1582. /**
  1583. * ufshcd_probe - probe routine of the driver
  1584. * @pdev: pointer to PCI device handle
  1585. * @id: PCI device id
  1586. *
  1587. * Returns 0 on success, non-zero value on failure
  1588. */
  1589. static int __devinit
  1590. ufshcd_probe(struct pci_dev *pdev, const struct pci_device_id *id)
  1591. {
  1592. struct Scsi_Host *host;
  1593. struct ufs_hba *hba;
  1594. int err;
  1595. err = pci_enable_device(pdev);
  1596. if (err) {
  1597. dev_err(&pdev->dev, "pci_enable_device failed\n");
  1598. goto out_error;
  1599. }
  1600. pci_set_master(pdev);
  1601. host = scsi_host_alloc(&ufshcd_driver_template,
  1602. sizeof(struct ufs_hba));
  1603. if (!host) {
  1604. dev_err(&pdev->dev, "scsi_host_alloc failed\n");
  1605. err = -ENOMEM;
  1606. goto out_disable;
  1607. }
  1608. hba = shost_priv(host);
  1609. err = pci_request_regions(pdev, UFSHCD);
  1610. if (err < 0) {
  1611. dev_err(&pdev->dev, "request regions failed\n");
  1612. goto out_host_put;
  1613. }
  1614. hba->mmio_base = pci_ioremap_bar(pdev, 0);
  1615. if (!hba->mmio_base) {
  1616. dev_err(&pdev->dev, "memory map failed\n");
  1617. err = -ENOMEM;
  1618. goto out_release_regions;
  1619. }
  1620. hba->host = host;
  1621. hba->pdev = pdev;
  1622. /* Read capabilities registers */
  1623. ufshcd_hba_capabilities(hba);
  1624. /* Get UFS version supported by the controller */
  1625. hba->ufs_version = ufshcd_get_ufs_version(hba);
  1626. err = ufshcd_set_dma_mask(hba);
  1627. if (err) {
  1628. dev_err(&pdev->dev, "set dma mask failed\n");
  1629. goto out_iounmap;
  1630. }
  1631. /* Allocate memory for host memory space */
  1632. err = ufshcd_memory_alloc(hba);
  1633. if (err) {
  1634. dev_err(&pdev->dev, "Memory allocation failed\n");
  1635. goto out_iounmap;
  1636. }
  1637. /* Configure LRB */
  1638. ufshcd_host_memory_configure(hba);
  1639. host->can_queue = hba->nutrs;
  1640. host->cmd_per_lun = hba->nutrs;
  1641. host->max_id = UFSHCD_MAX_ID;
  1642. host->max_lun = UFSHCD_MAX_LUNS;
  1643. host->max_channel = UFSHCD_MAX_CHANNEL;
  1644. host->unique_id = host->host_no;
  1645. host->max_cmd_len = MAX_CDB_SIZE;
  1646. /* Initailize wait queue for task management */
  1647. init_waitqueue_head(&hba->ufshcd_tm_wait_queue);
  1648. /* Initialize work queues */
  1649. INIT_WORK(&hba->uic_workq, ufshcd_uic_cc_handler);
  1650. INIT_WORK(&hba->feh_workq, ufshcd_fatal_err_handler);
  1651. /* IRQ registration */
  1652. err = request_irq(pdev->irq, ufshcd_intr, IRQF_SHARED, UFSHCD, hba);
  1653. if (err) {
  1654. dev_err(&pdev->dev, "request irq failed\n");
  1655. goto out_lrb_free;
  1656. }
  1657. /* Enable SCSI tag mapping */
  1658. err = scsi_init_shared_tag_map(host, host->can_queue);
  1659. if (err) {
  1660. dev_err(&pdev->dev, "init shared queue failed\n");
  1661. goto out_free_irq;
  1662. }
  1663. pci_set_drvdata(pdev, hba);
  1664. err = scsi_add_host(host, &pdev->dev);
  1665. if (err) {
  1666. dev_err(&pdev->dev, "scsi_add_host failed\n");
  1667. goto out_free_irq;
  1668. }
  1669. /* Initialization routine */
  1670. err = ufshcd_initialize_hba(hba);
  1671. if (err) {
  1672. dev_err(&pdev->dev, "Initialization failed\n");
  1673. goto out_free_irq;
  1674. }
  1675. return 0;
  1676. out_free_irq:
  1677. free_irq(pdev->irq, hba);
  1678. out_lrb_free:
  1679. ufshcd_free_hba_memory(hba);
  1680. out_iounmap:
  1681. iounmap(hba->mmio_base);
  1682. out_release_regions:
  1683. pci_release_regions(pdev);
  1684. out_host_put:
  1685. scsi_host_put(host);
  1686. out_disable:
  1687. pci_clear_master(pdev);
  1688. pci_disable_device(pdev);
  1689. out_error:
  1690. return err;
  1691. }
  1692. static DEFINE_PCI_DEVICE_TABLE(ufshcd_pci_tbl) = {
  1693. { PCI_VENDOR_ID_SAMSUNG, 0xC00C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
  1694. { } /* terminate list */
  1695. };
  1696. MODULE_DEVICE_TABLE(pci, ufshcd_pci_tbl);
  1697. static struct pci_driver ufshcd_pci_driver = {
  1698. .name = UFSHCD,
  1699. .id_table = ufshcd_pci_tbl,
  1700. .probe = ufshcd_probe,
  1701. .remove = __devexit_p(ufshcd_remove),
  1702. .shutdown = ufshcd_shutdown,
  1703. #ifdef CONFIG_PM
  1704. .suspend = ufshcd_suspend,
  1705. .resume = ufshcd_resume,
  1706. #endif
  1707. };
  1708. /**
  1709. * ufshcd_init - Driver registration routine
  1710. */
  1711. static int __init ufshcd_init(void)
  1712. {
  1713. return pci_register_driver(&ufshcd_pci_driver);
  1714. }
  1715. module_init(ufshcd_init);
  1716. /**
  1717. * ufshcd_exit - Driver exit clean-up routine
  1718. */
  1719. static void __exit ufshcd_exit(void)
  1720. {
  1721. pci_unregister_driver(&ufshcd_pci_driver);
  1722. }
  1723. module_exit(ufshcd_exit);
  1724. MODULE_AUTHOR("Santosh Yaragnavi <santosh.sy@samsung.com>, "
  1725. "Vinayak Holikatti <h.vinayak@samsung.com>");
  1726. MODULE_DESCRIPTION("Generic UFS host controller driver");
  1727. MODULE_LICENSE("GPL");
  1728. MODULE_VERSION(UFSHCD_DRIVER_VERSION);