ql4_def.h 24 KB

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  1. /*
  2. * QLogic iSCSI HBA Driver
  3. * Copyright (c) 2003-2010 QLogic Corporation
  4. *
  5. * See LICENSE.qla4xxx for copyright and licensing details.
  6. */
  7. #ifndef __QL4_DEF_H
  8. #define __QL4_DEF_H
  9. #include <linux/kernel.h>
  10. #include <linux/init.h>
  11. #include <linux/types.h>
  12. #include <linux/module.h>
  13. #include <linux/list.h>
  14. #include <linux/pci.h>
  15. #include <linux/dma-mapping.h>
  16. #include <linux/sched.h>
  17. #include <linux/slab.h>
  18. #include <linux/dmapool.h>
  19. #include <linux/mempool.h>
  20. #include <linux/spinlock.h>
  21. #include <linux/workqueue.h>
  22. #include <linux/delay.h>
  23. #include <linux/interrupt.h>
  24. #include <linux/mutex.h>
  25. #include <linux/aer.h>
  26. #include <linux/bsg-lib.h>
  27. #include <net/tcp.h>
  28. #include <scsi/scsi.h>
  29. #include <scsi/scsi_host.h>
  30. #include <scsi/scsi_device.h>
  31. #include <scsi/scsi_cmnd.h>
  32. #include <scsi/scsi_transport.h>
  33. #include <scsi/scsi_transport_iscsi.h>
  34. #include <scsi/scsi_bsg_iscsi.h>
  35. #include <scsi/scsi_netlink.h>
  36. #include <scsi/libiscsi.h>
  37. #include "ql4_dbg.h"
  38. #include "ql4_nx.h"
  39. #include "ql4_fw.h"
  40. #include "ql4_nvram.h"
  41. #ifndef PCI_DEVICE_ID_QLOGIC_ISP4010
  42. #define PCI_DEVICE_ID_QLOGIC_ISP4010 0x4010
  43. #endif
  44. #ifndef PCI_DEVICE_ID_QLOGIC_ISP4022
  45. #define PCI_DEVICE_ID_QLOGIC_ISP4022 0x4022
  46. #endif
  47. #ifndef PCI_DEVICE_ID_QLOGIC_ISP4032
  48. #define PCI_DEVICE_ID_QLOGIC_ISP4032 0x4032
  49. #endif
  50. #ifndef PCI_DEVICE_ID_QLOGIC_ISP8022
  51. #define PCI_DEVICE_ID_QLOGIC_ISP8022 0x8022
  52. #endif
  53. #define ISP4XXX_PCI_FN_1 0x1
  54. #define ISP4XXX_PCI_FN_2 0x3
  55. #define QLA_SUCCESS 0
  56. #define QLA_ERROR 1
  57. /*
  58. * Data bit definitions
  59. */
  60. #define BIT_0 0x1
  61. #define BIT_1 0x2
  62. #define BIT_2 0x4
  63. #define BIT_3 0x8
  64. #define BIT_4 0x10
  65. #define BIT_5 0x20
  66. #define BIT_6 0x40
  67. #define BIT_7 0x80
  68. #define BIT_8 0x100
  69. #define BIT_9 0x200
  70. #define BIT_10 0x400
  71. #define BIT_11 0x800
  72. #define BIT_12 0x1000
  73. #define BIT_13 0x2000
  74. #define BIT_14 0x4000
  75. #define BIT_15 0x8000
  76. #define BIT_16 0x10000
  77. #define BIT_17 0x20000
  78. #define BIT_18 0x40000
  79. #define BIT_19 0x80000
  80. #define BIT_20 0x100000
  81. #define BIT_21 0x200000
  82. #define BIT_22 0x400000
  83. #define BIT_23 0x800000
  84. #define BIT_24 0x1000000
  85. #define BIT_25 0x2000000
  86. #define BIT_26 0x4000000
  87. #define BIT_27 0x8000000
  88. #define BIT_28 0x10000000
  89. #define BIT_29 0x20000000
  90. #define BIT_30 0x40000000
  91. #define BIT_31 0x80000000
  92. /**
  93. * Macros to help code, maintain, etc.
  94. **/
  95. #define ql4_printk(level, ha, format, arg...) \
  96. dev_printk(level , &((ha)->pdev->dev) , format , ## arg)
  97. /*
  98. * Host adapter default definitions
  99. ***********************************/
  100. #define MAX_HBAS 16
  101. #define MAX_BUSES 1
  102. #define MAX_TARGETS MAX_DEV_DB_ENTRIES
  103. #define MAX_LUNS 0xffff
  104. #define MAX_AEN_ENTRIES MAX_DEV_DB_ENTRIES
  105. #define MAX_DDB_ENTRIES MAX_DEV_DB_ENTRIES
  106. #define MAX_PDU_ENTRIES 32
  107. #define INVALID_ENTRY 0xFFFF
  108. #define MAX_CMDS_TO_RISC 1024
  109. #define MAX_SRBS MAX_CMDS_TO_RISC
  110. #define MBOX_AEN_REG_COUNT 8
  111. #define MAX_INIT_RETRIES 5
  112. /*
  113. * Buffer sizes
  114. */
  115. #define REQUEST_QUEUE_DEPTH MAX_CMDS_TO_RISC
  116. #define RESPONSE_QUEUE_DEPTH 64
  117. #define QUEUE_SIZE 64
  118. #define DMA_BUFFER_SIZE 512
  119. /*
  120. * Misc
  121. */
  122. #define MAC_ADDR_LEN 6 /* in bytes */
  123. #define IP_ADDR_LEN 4 /* in bytes */
  124. #define IPv6_ADDR_LEN 16 /* IPv6 address size */
  125. #define DRIVER_NAME "qla4xxx"
  126. #define MAX_LINKED_CMDS_PER_LUN 3
  127. #define MAX_REQS_SERVICED_PER_INTR 1
  128. #define ISCSI_IPADDR_SIZE 4 /* IP address size */
  129. #define ISCSI_ALIAS_SIZE 32 /* ISCSI Alias name size */
  130. #define ISCSI_NAME_SIZE 0xE0 /* ISCSI Name size */
  131. #define QL4_SESS_RECOVERY_TMO 120 /* iSCSI session */
  132. /* recovery timeout */
  133. #define LSDW(x) ((u32)((u64)(x)))
  134. #define MSDW(x) ((u32)((((u64)(x)) >> 16) >> 16))
  135. /*
  136. * Retry & Timeout Values
  137. */
  138. #define MBOX_TOV 60
  139. #define SOFT_RESET_TOV 30
  140. #define RESET_INTR_TOV 3
  141. #define SEMAPHORE_TOV 10
  142. #define ADAPTER_INIT_TOV 30
  143. #define ADAPTER_RESET_TOV 180
  144. #define EXTEND_CMD_TOV 60
  145. #define WAIT_CMD_TOV 30
  146. #define EH_WAIT_CMD_TOV 120
  147. #define FIRMWARE_UP_TOV 60
  148. #define RESET_FIRMWARE_TOV 30
  149. #define LOGOUT_TOV 10
  150. #define IOCB_TOV_MARGIN 10
  151. #define RELOGIN_TOV 18
  152. #define ISNS_DEREG_TOV 5
  153. #define HBA_ONLINE_TOV 30
  154. #define DISABLE_ACB_TOV 30
  155. #define IP_CONFIG_TOV 30
  156. #define LOGIN_TOV 12
  157. #define MAX_RESET_HA_RETRIES 2
  158. #define FW_ALIVE_WAIT_TOV 3
  159. #define CMD_SP(Cmnd) ((Cmnd)->SCp.ptr)
  160. /*
  161. * SCSI Request Block structure (srb) that is placed
  162. * on cmd->SCp location of every I/O [We have 22 bytes available]
  163. */
  164. struct srb {
  165. struct list_head list; /* (8) */
  166. struct scsi_qla_host *ha; /* HA the SP is queued on */
  167. struct ddb_entry *ddb;
  168. uint16_t flags; /* (1) Status flags. */
  169. #define SRB_DMA_VALID BIT_3 /* DMA Buffer mapped. */
  170. #define SRB_GOT_SENSE BIT_4 /* sense data received. */
  171. uint8_t state; /* (1) Status flags. */
  172. #define SRB_NO_QUEUE_STATE 0 /* Request is in between states */
  173. #define SRB_FREE_STATE 1
  174. #define SRB_ACTIVE_STATE 3
  175. #define SRB_ACTIVE_TIMEOUT_STATE 4
  176. #define SRB_SUSPENDED_STATE 7 /* Request in suspended state */
  177. struct scsi_cmnd *cmd; /* (4) SCSI command block */
  178. dma_addr_t dma_handle; /* (4) for unmap of single transfers */
  179. struct kref srb_ref; /* reference count for this srb */
  180. uint8_t err_id; /* error id */
  181. #define SRB_ERR_PORT 1 /* Request failed because "port down" */
  182. #define SRB_ERR_LOOP 2 /* Request failed because "loop down" */
  183. #define SRB_ERR_DEVICE 3 /* Request failed because "device error" */
  184. #define SRB_ERR_OTHER 4
  185. uint16_t reserved;
  186. uint16_t iocb_tov;
  187. uint16_t iocb_cnt; /* Number of used iocbs */
  188. uint16_t cc_stat;
  189. /* Used for extended sense / status continuation */
  190. uint8_t *req_sense_ptr;
  191. uint16_t req_sense_len;
  192. uint16_t reserved2;
  193. };
  194. /* Mailbox request block structure */
  195. struct mrb {
  196. struct scsi_qla_host *ha;
  197. struct mbox_cmd_iocb *mbox;
  198. uint32_t mbox_cmd;
  199. uint16_t iocb_cnt; /* Number of used iocbs */
  200. uint32_t pid;
  201. };
  202. /*
  203. * Asynchronous Event Queue structure
  204. */
  205. struct aen {
  206. uint32_t mbox_sts[MBOX_AEN_REG_COUNT];
  207. };
  208. struct ql4_aen_log {
  209. int count;
  210. struct aen entry[MAX_AEN_ENTRIES];
  211. };
  212. /*
  213. * Device Database (DDB) structure
  214. */
  215. struct ddb_entry {
  216. struct scsi_qla_host *ha;
  217. struct iscsi_cls_session *sess;
  218. struct iscsi_cls_conn *conn;
  219. uint16_t fw_ddb_index; /* DDB firmware index */
  220. uint32_t fw_ddb_device_state; /* F/W Device State -- see ql4_fw.h */
  221. uint16_t ddb_type;
  222. #define FLASH_DDB 0x01
  223. struct dev_db_entry fw_ddb_entry;
  224. int (*unblock_sess)(struct iscsi_cls_session *cls_session);
  225. int (*ddb_change)(struct scsi_qla_host *ha, uint32_t fw_ddb_index,
  226. struct ddb_entry *ddb_entry, uint32_t state);
  227. /* Driver Re-login */
  228. unsigned long flags; /* DDB Flags */
  229. uint16_t default_relogin_timeout; /* Max time to wait for
  230. * relogin to complete */
  231. atomic_t retry_relogin_timer; /* Min Time between relogins
  232. * (4000 only) */
  233. atomic_t relogin_timer; /* Max Time to wait for
  234. * relogin to complete */
  235. atomic_t relogin_retry_count; /* Num of times relogin has been
  236. * retried */
  237. uint32_t default_time2wait; /* Default Min time between
  238. * relogins (+aens) */
  239. uint16_t chap_tbl_idx;
  240. };
  241. struct qla_ddb_index {
  242. struct list_head list;
  243. uint16_t fw_ddb_idx;
  244. struct dev_db_entry fw_ddb;
  245. };
  246. #define DDB_IPADDR_LEN 64
  247. struct ql4_tuple_ddb {
  248. int port;
  249. int tpgt;
  250. char ip_addr[DDB_IPADDR_LEN];
  251. char iscsi_name[ISCSI_NAME_SIZE];
  252. uint16_t options;
  253. #define DDB_OPT_IPV6 0x0e0e
  254. #define DDB_OPT_IPV4 0x0f0f
  255. uint8_t isid[6];
  256. };
  257. /*
  258. * DDB states.
  259. */
  260. #define DDB_STATE_DEAD 0 /* We can no longer talk to
  261. * this device */
  262. #define DDB_STATE_ONLINE 1 /* Device ready to accept
  263. * commands */
  264. #define DDB_STATE_MISSING 2 /* Device logged off, trying
  265. * to re-login */
  266. /*
  267. * DDB flags.
  268. */
  269. #define DF_RELOGIN 0 /* Relogin to device */
  270. #define DF_ISNS_DISCOVERED 2 /* Device was discovered via iSNS */
  271. #define DF_FO_MASKED 3
  272. enum qla4_work_type {
  273. QLA4_EVENT_AEN,
  274. QLA4_EVENT_PING_STATUS,
  275. };
  276. struct qla4_work_evt {
  277. struct list_head list;
  278. enum qla4_work_type type;
  279. union {
  280. struct {
  281. enum iscsi_host_event_code code;
  282. uint32_t data_size;
  283. uint8_t data[0];
  284. } aen;
  285. struct {
  286. uint32_t status;
  287. uint32_t pid;
  288. uint32_t data_size;
  289. uint8_t data[0];
  290. } ping;
  291. } u;
  292. };
  293. struct ql82xx_hw_data {
  294. /* Offsets for flash/nvram access (set to ~0 if not used). */
  295. uint32_t flash_conf_off;
  296. uint32_t flash_data_off;
  297. uint32_t fdt_wrt_disable;
  298. uint32_t fdt_erase_cmd;
  299. uint32_t fdt_block_size;
  300. uint32_t fdt_unprotect_sec_cmd;
  301. uint32_t fdt_protect_sec_cmd;
  302. uint32_t flt_region_flt;
  303. uint32_t flt_region_fdt;
  304. uint32_t flt_region_boot;
  305. uint32_t flt_region_bootload;
  306. uint32_t flt_region_fw;
  307. uint32_t flt_iscsi_param;
  308. uint32_t flt_region_chap;
  309. uint32_t flt_chap_size;
  310. };
  311. struct qla4_8xxx_legacy_intr_set {
  312. uint32_t int_vec_bit;
  313. uint32_t tgt_status_reg;
  314. uint32_t tgt_mask_reg;
  315. uint32_t pci_int_reg;
  316. };
  317. /* MSI-X Support */
  318. #define QLA_MSIX_DEFAULT 0x00
  319. #define QLA_MSIX_RSP_Q 0x01
  320. #define QLA_MSIX_ENTRIES 2
  321. #define QLA_MIDX_DEFAULT 0
  322. #define QLA_MIDX_RSP_Q 1
  323. struct ql4_msix_entry {
  324. int have_irq;
  325. uint16_t msix_vector;
  326. uint16_t msix_entry;
  327. };
  328. /*
  329. * ISP Operations
  330. */
  331. struct isp_operations {
  332. int (*iospace_config) (struct scsi_qla_host *ha);
  333. void (*pci_config) (struct scsi_qla_host *);
  334. void (*disable_intrs) (struct scsi_qla_host *);
  335. void (*enable_intrs) (struct scsi_qla_host *);
  336. int (*start_firmware) (struct scsi_qla_host *);
  337. irqreturn_t (*intr_handler) (int , void *);
  338. void (*interrupt_service_routine) (struct scsi_qla_host *, uint32_t);
  339. int (*reset_chip) (struct scsi_qla_host *);
  340. int (*reset_firmware) (struct scsi_qla_host *);
  341. void (*queue_iocb) (struct scsi_qla_host *);
  342. void (*complete_iocb) (struct scsi_qla_host *);
  343. uint16_t (*rd_shdw_req_q_out) (struct scsi_qla_host *);
  344. uint16_t (*rd_shdw_rsp_q_in) (struct scsi_qla_host *);
  345. int (*get_sys_info) (struct scsi_qla_host *);
  346. };
  347. struct ql4_mdump_size_table {
  348. uint32_t size;
  349. uint32_t size_cmask_02;
  350. uint32_t size_cmask_04;
  351. uint32_t size_cmask_08;
  352. uint32_t size_cmask_10;
  353. uint32_t size_cmask_FF;
  354. uint32_t version;
  355. };
  356. /*qla4xxx ipaddress configuration details */
  357. struct ipaddress_config {
  358. uint16_t ipv4_options;
  359. uint16_t tcp_options;
  360. uint16_t ipv4_vlan_tag;
  361. uint8_t ipv4_addr_state;
  362. uint8_t ip_address[IP_ADDR_LEN];
  363. uint8_t subnet_mask[IP_ADDR_LEN];
  364. uint8_t gateway[IP_ADDR_LEN];
  365. uint32_t ipv6_options;
  366. uint32_t ipv6_addl_options;
  367. uint8_t ipv6_link_local_state;
  368. uint8_t ipv6_addr0_state;
  369. uint8_t ipv6_addr1_state;
  370. uint8_t ipv6_default_router_state;
  371. uint16_t ipv6_vlan_tag;
  372. struct in6_addr ipv6_link_local_addr;
  373. struct in6_addr ipv6_addr0;
  374. struct in6_addr ipv6_addr1;
  375. struct in6_addr ipv6_default_router_addr;
  376. uint16_t eth_mtu_size;
  377. uint16_t ipv4_port;
  378. uint16_t ipv6_port;
  379. };
  380. #define QL4_CHAP_MAX_NAME_LEN 256
  381. #define QL4_CHAP_MAX_SECRET_LEN 100
  382. #define LOCAL_CHAP 0
  383. #define BIDI_CHAP 1
  384. struct ql4_chap_format {
  385. u8 intr_chap_name[QL4_CHAP_MAX_NAME_LEN];
  386. u8 intr_secret[QL4_CHAP_MAX_SECRET_LEN];
  387. u8 target_chap_name[QL4_CHAP_MAX_NAME_LEN];
  388. u8 target_secret[QL4_CHAP_MAX_SECRET_LEN];
  389. u16 intr_chap_name_length;
  390. u16 intr_secret_length;
  391. u16 target_chap_name_length;
  392. u16 target_secret_length;
  393. };
  394. struct ip_address_format {
  395. u8 ip_type;
  396. u8 ip_address[16];
  397. };
  398. struct ql4_conn_info {
  399. u16 dest_port;
  400. struct ip_address_format dest_ipaddr;
  401. struct ql4_chap_format chap;
  402. };
  403. struct ql4_boot_session_info {
  404. u8 target_name[224];
  405. struct ql4_conn_info conn_list[1];
  406. };
  407. struct ql4_boot_tgt_info {
  408. struct ql4_boot_session_info boot_pri_sess;
  409. struct ql4_boot_session_info boot_sec_sess;
  410. };
  411. /*
  412. * Linux Host Adapter structure
  413. */
  414. struct scsi_qla_host {
  415. /* Linux adapter configuration data */
  416. unsigned long flags;
  417. #define AF_ONLINE 0 /* 0x00000001 */
  418. #define AF_INIT_DONE 1 /* 0x00000002 */
  419. #define AF_MBOX_COMMAND 2 /* 0x00000004 */
  420. #define AF_MBOX_COMMAND_DONE 3 /* 0x00000008 */
  421. #define AF_INTERRUPTS_ON 6 /* 0x00000040 */
  422. #define AF_GET_CRASH_RECORD 7 /* 0x00000080 */
  423. #define AF_LINK_UP 8 /* 0x00000100 */
  424. #define AF_IRQ_ATTACHED 10 /* 0x00000400 */
  425. #define AF_DISABLE_ACB_COMPLETE 11 /* 0x00000800 */
  426. #define AF_HA_REMOVAL 12 /* 0x00001000 */
  427. #define AF_INTx_ENABLED 15 /* 0x00008000 */
  428. #define AF_MSI_ENABLED 16 /* 0x00010000 */
  429. #define AF_MSIX_ENABLED 17 /* 0x00020000 */
  430. #define AF_MBOX_COMMAND_NOPOLL 18 /* 0x00040000 */
  431. #define AF_FW_RECOVERY 19 /* 0x00080000 */
  432. #define AF_EEH_BUSY 20 /* 0x00100000 */
  433. #define AF_PCI_CHANNEL_IO_PERM_FAILURE 21 /* 0x00200000 */
  434. #define AF_BUILD_DDB_LIST 22 /* 0x00400000 */
  435. #define AF_82XX_FW_DUMPED 24 /* 0x01000000 */
  436. #define AF_82XX_RST_OWNER 25 /* 0x02000000 */
  437. #define AF_82XX_DUMP_READING 26 /* 0x04000000 */
  438. unsigned long dpc_flags;
  439. #define DPC_RESET_HA 1 /* 0x00000002 */
  440. #define DPC_RETRY_RESET_HA 2 /* 0x00000004 */
  441. #define DPC_RELOGIN_DEVICE 3 /* 0x00000008 */
  442. #define DPC_RESET_HA_FW_CONTEXT 4 /* 0x00000010 */
  443. #define DPC_RESET_HA_INTR 5 /* 0x00000020 */
  444. #define DPC_ISNS_RESTART 7 /* 0x00000080 */
  445. #define DPC_AEN 9 /* 0x00000200 */
  446. #define DPC_GET_DHCP_IP_ADDR 15 /* 0x00008000 */
  447. #define DPC_LINK_CHANGED 18 /* 0x00040000 */
  448. #define DPC_RESET_ACTIVE 20 /* 0x00040000 */
  449. #define DPC_HA_UNRECOVERABLE 21 /* 0x00080000 ISP-82xx only*/
  450. #define DPC_HA_NEED_QUIESCENT 22 /* 0x00100000 ISP-82xx only*/
  451. struct Scsi_Host *host; /* pointer to host data */
  452. uint32_t tot_ddbs;
  453. uint16_t iocb_cnt;
  454. /* SRB cache. */
  455. #define SRB_MIN_REQ 128
  456. mempool_t *srb_mempool;
  457. /* pci information */
  458. struct pci_dev *pdev;
  459. struct isp_reg __iomem *reg; /* Base I/O address */
  460. unsigned long pio_address;
  461. unsigned long pio_length;
  462. #define MIN_IOBASE_LEN 0x100
  463. uint16_t req_q_count;
  464. unsigned long host_no;
  465. /* NVRAM registers */
  466. struct eeprom_data *nvram;
  467. spinlock_t hardware_lock ____cacheline_aligned;
  468. uint32_t eeprom_cmd_data;
  469. /* Counters for general statistics */
  470. uint64_t isr_count;
  471. uint64_t adapter_error_count;
  472. uint64_t device_error_count;
  473. uint64_t total_io_count;
  474. uint64_t total_mbytes_xferred;
  475. uint64_t link_failure_count;
  476. uint64_t invalid_crc_count;
  477. uint32_t bytes_xfered;
  478. uint32_t spurious_int_count;
  479. uint32_t aborted_io_count;
  480. uint32_t io_timeout_count;
  481. uint32_t mailbox_timeout_count;
  482. uint32_t seconds_since_last_intr;
  483. uint32_t seconds_since_last_heartbeat;
  484. uint32_t mac_index;
  485. /* Info Needed for Management App */
  486. /* --- From GetFwVersion --- */
  487. uint32_t firmware_version[2];
  488. uint32_t patch_number;
  489. uint32_t build_number;
  490. uint32_t board_id;
  491. /* --- From Init_FW --- */
  492. /* init_cb_t *init_cb; */
  493. uint16_t firmware_options;
  494. uint8_t alias[32];
  495. uint8_t name_string[256];
  496. uint8_t heartbeat_interval;
  497. /* --- From FlashSysInfo --- */
  498. uint8_t my_mac[MAC_ADDR_LEN];
  499. uint8_t serial_number[16];
  500. uint16_t port_num;
  501. /* --- From GetFwState --- */
  502. uint32_t firmware_state;
  503. uint32_t addl_fw_state;
  504. /* Linux kernel thread */
  505. struct workqueue_struct *dpc_thread;
  506. struct work_struct dpc_work;
  507. /* Linux timer thread */
  508. struct timer_list timer;
  509. uint32_t timer_active;
  510. /* Recovery Timers */
  511. atomic_t check_relogin_timeouts;
  512. uint32_t retry_reset_ha_cnt;
  513. uint32_t isp_reset_timer; /* reset test timer */
  514. uint32_t nic_reset_timer; /* simulated nic reset test timer */
  515. int eh_start;
  516. struct list_head free_srb_q;
  517. uint16_t free_srb_q_count;
  518. uint16_t num_srbs_allocated;
  519. /* DMA Memory Block */
  520. void *queues;
  521. dma_addr_t queues_dma;
  522. unsigned long queues_len;
  523. #define MEM_ALIGN_VALUE \
  524. ((max(REQUEST_QUEUE_DEPTH, RESPONSE_QUEUE_DEPTH)) * \
  525. sizeof(struct queue_entry))
  526. /* request and response queue variables */
  527. dma_addr_t request_dma;
  528. struct queue_entry *request_ring;
  529. struct queue_entry *request_ptr;
  530. dma_addr_t response_dma;
  531. struct queue_entry *response_ring;
  532. struct queue_entry *response_ptr;
  533. dma_addr_t shadow_regs_dma;
  534. struct shadow_regs *shadow_regs;
  535. uint16_t request_in; /* Current indexes. */
  536. uint16_t request_out;
  537. uint16_t response_in;
  538. uint16_t response_out;
  539. /* aen queue variables */
  540. uint16_t aen_q_count; /* Number of available aen_q entries */
  541. uint16_t aen_in; /* Current indexes */
  542. uint16_t aen_out;
  543. struct aen aen_q[MAX_AEN_ENTRIES];
  544. struct ql4_aen_log aen_log;/* tracks all aens */
  545. /* This mutex protects several threads to do mailbox commands
  546. * concurrently.
  547. */
  548. struct mutex mbox_sem;
  549. /* temporary mailbox status registers */
  550. volatile uint8_t mbox_status_count;
  551. volatile uint32_t mbox_status[MBOX_REG_COUNT];
  552. /* FW ddb index map */
  553. struct ddb_entry *fw_ddb_index_map[MAX_DDB_ENTRIES];
  554. /* Saved srb for status continuation entry processing */
  555. struct srb *status_srb;
  556. uint8_t acb_version;
  557. /* qla82xx specific fields */
  558. struct device_reg_82xx __iomem *qla4_8xxx_reg; /* Base I/O address */
  559. unsigned long nx_pcibase; /* Base I/O address */
  560. uint8_t *nx_db_rd_ptr; /* Doorbell read pointer */
  561. unsigned long nx_db_wr_ptr; /* Door bell write pointer */
  562. unsigned long first_page_group_start;
  563. unsigned long first_page_group_end;
  564. uint32_t crb_win;
  565. uint32_t curr_window;
  566. uint32_t ddr_mn_window;
  567. unsigned long mn_win_crb;
  568. unsigned long ms_win_crb;
  569. int qdr_sn_window;
  570. rwlock_t hw_lock;
  571. uint16_t func_num;
  572. int link_width;
  573. struct qla4_8xxx_legacy_intr_set nx_legacy_intr;
  574. u32 nx_crb_mask;
  575. uint8_t revision_id;
  576. uint32_t fw_heartbeat_counter;
  577. struct isp_operations *isp_ops;
  578. struct ql82xx_hw_data hw;
  579. struct ql4_msix_entry msix_entries[QLA_MSIX_ENTRIES];
  580. uint32_t nx_dev_init_timeout;
  581. uint32_t nx_reset_timeout;
  582. void *fw_dump;
  583. uint32_t fw_dump_size;
  584. uint32_t fw_dump_capture_mask;
  585. void *fw_dump_tmplt_hdr;
  586. uint32_t fw_dump_tmplt_size;
  587. struct completion mbx_intr_comp;
  588. struct ipaddress_config ip_config;
  589. struct iscsi_iface *iface_ipv4;
  590. struct iscsi_iface *iface_ipv6_0;
  591. struct iscsi_iface *iface_ipv6_1;
  592. /* --- From About Firmware --- */
  593. uint16_t iscsi_major;
  594. uint16_t iscsi_minor;
  595. uint16_t bootload_major;
  596. uint16_t bootload_minor;
  597. uint16_t bootload_patch;
  598. uint16_t bootload_build;
  599. uint16_t def_timeout; /* Default login timeout */
  600. uint32_t flash_state;
  601. #define QLFLASH_WAITING 0
  602. #define QLFLASH_READING 1
  603. #define QLFLASH_WRITING 2
  604. struct dma_pool *chap_dma_pool;
  605. uint8_t *chap_list; /* CHAP table cache */
  606. struct mutex chap_sem;
  607. #define CHAP_DMA_BLOCK_SIZE 512
  608. struct workqueue_struct *task_wq;
  609. unsigned long ddb_idx_map[MAX_DDB_ENTRIES / BITS_PER_LONG];
  610. #define SYSFS_FLAG_FW_SEL_BOOT 2
  611. struct iscsi_boot_kset *boot_kset;
  612. struct ql4_boot_tgt_info boot_tgt;
  613. uint16_t phy_port_num;
  614. uint16_t phy_port_cnt;
  615. uint16_t iscsi_pci_func_cnt;
  616. uint8_t model_name[16];
  617. struct completion disable_acb_comp;
  618. struct dma_pool *fw_ddb_dma_pool;
  619. #define DDB_DMA_BLOCK_SIZE 512
  620. uint16_t pri_ddb_idx;
  621. uint16_t sec_ddb_idx;
  622. int is_reset;
  623. uint16_t temperature;
  624. /* event work list */
  625. struct list_head work_list;
  626. spinlock_t work_lock;
  627. /* mbox iocb */
  628. #define MAX_MRB 128
  629. struct mrb *active_mrb_array[MAX_MRB];
  630. uint32_t mrb_index;
  631. };
  632. struct ql4_task_data {
  633. struct scsi_qla_host *ha;
  634. uint8_t iocb_req_cnt;
  635. dma_addr_t data_dma;
  636. void *req_buffer;
  637. dma_addr_t req_dma;
  638. uint32_t req_len;
  639. void *resp_buffer;
  640. dma_addr_t resp_dma;
  641. uint32_t resp_len;
  642. struct iscsi_task *task;
  643. struct passthru_status sts;
  644. struct work_struct task_work;
  645. };
  646. struct qla_endpoint {
  647. struct Scsi_Host *host;
  648. struct sockaddr dst_addr;
  649. };
  650. struct qla_conn {
  651. struct qla_endpoint *qla_ep;
  652. };
  653. static inline int is_ipv4_enabled(struct scsi_qla_host *ha)
  654. {
  655. return ((ha->ip_config.ipv4_options & IPOPT_IPV4_PROTOCOL_ENABLE) != 0);
  656. }
  657. static inline int is_ipv6_enabled(struct scsi_qla_host *ha)
  658. {
  659. return ((ha->ip_config.ipv6_options &
  660. IPV6_OPT_IPV6_PROTOCOL_ENABLE) != 0);
  661. }
  662. static inline int is_qla4010(struct scsi_qla_host *ha)
  663. {
  664. return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP4010;
  665. }
  666. static inline int is_qla4022(struct scsi_qla_host *ha)
  667. {
  668. return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP4022;
  669. }
  670. static inline int is_qla4032(struct scsi_qla_host *ha)
  671. {
  672. return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP4032;
  673. }
  674. static inline int is_qla40XX(struct scsi_qla_host *ha)
  675. {
  676. return is_qla4032(ha) || is_qla4022(ha) || is_qla4010(ha);
  677. }
  678. static inline int is_qla8022(struct scsi_qla_host *ha)
  679. {
  680. return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8022;
  681. }
  682. /* Note: Currently AER/EEH is now supported only for 8022 cards
  683. * This function needs to be updated when AER/EEH is enabled
  684. * for other cards.
  685. */
  686. static inline int is_aer_supported(struct scsi_qla_host *ha)
  687. {
  688. return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8022;
  689. }
  690. static inline int adapter_up(struct scsi_qla_host *ha)
  691. {
  692. return (test_bit(AF_ONLINE, &ha->flags) != 0) &&
  693. (test_bit(AF_LINK_UP, &ha->flags) != 0);
  694. }
  695. static inline struct scsi_qla_host* to_qla_host(struct Scsi_Host *shost)
  696. {
  697. return (struct scsi_qla_host *)iscsi_host_priv(shost);
  698. }
  699. static inline void __iomem* isp_semaphore(struct scsi_qla_host *ha)
  700. {
  701. return (is_qla4010(ha) ?
  702. &ha->reg->u1.isp4010.nvram :
  703. &ha->reg->u1.isp4022.semaphore);
  704. }
  705. static inline void __iomem* isp_nvram(struct scsi_qla_host *ha)
  706. {
  707. return (is_qla4010(ha) ?
  708. &ha->reg->u1.isp4010.nvram :
  709. &ha->reg->u1.isp4022.nvram);
  710. }
  711. static inline void __iomem* isp_ext_hw_conf(struct scsi_qla_host *ha)
  712. {
  713. return (is_qla4010(ha) ?
  714. &ha->reg->u2.isp4010.ext_hw_conf :
  715. &ha->reg->u2.isp4022.p0.ext_hw_conf);
  716. }
  717. static inline void __iomem* isp_port_status(struct scsi_qla_host *ha)
  718. {
  719. return (is_qla4010(ha) ?
  720. &ha->reg->u2.isp4010.port_status :
  721. &ha->reg->u2.isp4022.p0.port_status);
  722. }
  723. static inline void __iomem* isp_port_ctrl(struct scsi_qla_host *ha)
  724. {
  725. return (is_qla4010(ha) ?
  726. &ha->reg->u2.isp4010.port_ctrl :
  727. &ha->reg->u2.isp4022.p0.port_ctrl);
  728. }
  729. static inline void __iomem* isp_port_error_status(struct scsi_qla_host *ha)
  730. {
  731. return (is_qla4010(ha) ?
  732. &ha->reg->u2.isp4010.port_err_status :
  733. &ha->reg->u2.isp4022.p0.port_err_status);
  734. }
  735. static inline void __iomem * isp_gp_out(struct scsi_qla_host *ha)
  736. {
  737. return (is_qla4010(ha) ?
  738. &ha->reg->u2.isp4010.gp_out :
  739. &ha->reg->u2.isp4022.p0.gp_out);
  740. }
  741. static inline int eeprom_ext_hw_conf_offset(struct scsi_qla_host *ha)
  742. {
  743. return (is_qla4010(ha) ?
  744. offsetof(struct eeprom_data, isp4010.ext_hw_conf) / 2 :
  745. offsetof(struct eeprom_data, isp4022.ext_hw_conf) / 2);
  746. }
  747. int ql4xxx_sem_spinlock(struct scsi_qla_host * ha, u32 sem_mask, u32 sem_bits);
  748. void ql4xxx_sem_unlock(struct scsi_qla_host * ha, u32 sem_mask);
  749. int ql4xxx_sem_lock(struct scsi_qla_host * ha, u32 sem_mask, u32 sem_bits);
  750. static inline int ql4xxx_lock_flash(struct scsi_qla_host *a)
  751. {
  752. if (is_qla4010(a))
  753. return ql4xxx_sem_spinlock(a, QL4010_FLASH_SEM_MASK,
  754. QL4010_FLASH_SEM_BITS);
  755. else
  756. return ql4xxx_sem_spinlock(a, QL4022_FLASH_SEM_MASK,
  757. (QL4022_RESOURCE_BITS_BASE_CODE |
  758. (a->mac_index)) << 13);
  759. }
  760. static inline void ql4xxx_unlock_flash(struct scsi_qla_host *a)
  761. {
  762. if (is_qla4010(a))
  763. ql4xxx_sem_unlock(a, QL4010_FLASH_SEM_MASK);
  764. else
  765. ql4xxx_sem_unlock(a, QL4022_FLASH_SEM_MASK);
  766. }
  767. static inline int ql4xxx_lock_nvram(struct scsi_qla_host *a)
  768. {
  769. if (is_qla4010(a))
  770. return ql4xxx_sem_spinlock(a, QL4010_NVRAM_SEM_MASK,
  771. QL4010_NVRAM_SEM_BITS);
  772. else
  773. return ql4xxx_sem_spinlock(a, QL4022_NVRAM_SEM_MASK,
  774. (QL4022_RESOURCE_BITS_BASE_CODE |
  775. (a->mac_index)) << 10);
  776. }
  777. static inline void ql4xxx_unlock_nvram(struct scsi_qla_host *a)
  778. {
  779. if (is_qla4010(a))
  780. ql4xxx_sem_unlock(a, QL4010_NVRAM_SEM_MASK);
  781. else
  782. ql4xxx_sem_unlock(a, QL4022_NVRAM_SEM_MASK);
  783. }
  784. static inline int ql4xxx_lock_drvr(struct scsi_qla_host *a)
  785. {
  786. if (is_qla4010(a))
  787. return ql4xxx_sem_lock(a, QL4010_DRVR_SEM_MASK,
  788. QL4010_DRVR_SEM_BITS);
  789. else
  790. return ql4xxx_sem_lock(a, QL4022_DRVR_SEM_MASK,
  791. (QL4022_RESOURCE_BITS_BASE_CODE |
  792. (a->mac_index)) << 1);
  793. }
  794. static inline void ql4xxx_unlock_drvr(struct scsi_qla_host *a)
  795. {
  796. if (is_qla4010(a))
  797. ql4xxx_sem_unlock(a, QL4010_DRVR_SEM_MASK);
  798. else
  799. ql4xxx_sem_unlock(a, QL4022_DRVR_SEM_MASK);
  800. }
  801. static inline int ql4xxx_reset_active(struct scsi_qla_host *ha)
  802. {
  803. return test_bit(DPC_RESET_ACTIVE, &ha->dpc_flags) ||
  804. test_bit(DPC_RESET_HA, &ha->dpc_flags) ||
  805. test_bit(DPC_RETRY_RESET_HA, &ha->dpc_flags) ||
  806. test_bit(DPC_RESET_HA_INTR, &ha->dpc_flags) ||
  807. test_bit(DPC_RESET_HA_FW_CONTEXT, &ha->dpc_flags) ||
  808. test_bit(DPC_HA_UNRECOVERABLE, &ha->dpc_flags);
  809. }
  810. /*---------------------------------------------------------------------------*/
  811. /* Defines for qla4xxx_initialize_adapter() and qla4xxx_recover_adapter() */
  812. #define INIT_ADAPTER 0
  813. #define RESET_ADAPTER 1
  814. #define PRESERVE_DDB_LIST 0
  815. #define REBUILD_DDB_LIST 1
  816. /* Defines for process_aen() */
  817. #define PROCESS_ALL_AENS 0
  818. #define FLUSH_DDB_CHANGED_AENS 1
  819. /* Defines for udev events */
  820. #define QL4_UEVENT_CODE_FW_DUMP 0
  821. #endif /*_QLA4XXX_H */