qla_mbx.c 118 KB

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  1. /*
  2. * QLogic Fibre Channel HBA Driver
  3. * Copyright (c) 2003-2011 QLogic Corporation
  4. *
  5. * See LICENSE.qla2xxx for copyright and licensing details.
  6. */
  7. #include "qla_def.h"
  8. #include "qla_target.h"
  9. #include <linux/delay.h>
  10. #include <linux/gfp.h>
  11. /*
  12. * qla2x00_mailbox_command
  13. * Issue mailbox command and waits for completion.
  14. *
  15. * Input:
  16. * ha = adapter block pointer.
  17. * mcp = driver internal mbx struct pointer.
  18. *
  19. * Output:
  20. * mb[MAX_MAILBOX_REGISTER_COUNT] = returned mailbox data.
  21. *
  22. * Returns:
  23. * 0 : QLA_SUCCESS = cmd performed success
  24. * 1 : QLA_FUNCTION_FAILED (error encountered)
  25. * 6 : QLA_FUNCTION_TIMEOUT (timeout condition encountered)
  26. *
  27. * Context:
  28. * Kernel context.
  29. */
  30. static int
  31. qla2x00_mailbox_command(scsi_qla_host_t *vha, mbx_cmd_t *mcp)
  32. {
  33. int rval;
  34. unsigned long flags = 0;
  35. device_reg_t __iomem *reg;
  36. uint8_t abort_active;
  37. uint8_t io_lock_on;
  38. uint16_t command = 0;
  39. uint16_t *iptr;
  40. uint16_t __iomem *optr;
  41. uint32_t cnt;
  42. uint32_t mboxes;
  43. unsigned long wait_time;
  44. struct qla_hw_data *ha = vha->hw;
  45. scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
  46. ql_dbg(ql_dbg_mbx, vha, 0x1000, "Entered %s.\n", __func__);
  47. if (ha->pdev->error_state > pci_channel_io_frozen) {
  48. ql_log(ql_log_warn, vha, 0x1001,
  49. "error_state is greater than pci_channel_io_frozen, "
  50. "exiting.\n");
  51. return QLA_FUNCTION_TIMEOUT;
  52. }
  53. if (vha->device_flags & DFLG_DEV_FAILED) {
  54. ql_log(ql_log_warn, vha, 0x1002,
  55. "Device in failed state, exiting.\n");
  56. return QLA_FUNCTION_TIMEOUT;
  57. }
  58. reg = ha->iobase;
  59. io_lock_on = base_vha->flags.init_done;
  60. rval = QLA_SUCCESS;
  61. abort_active = test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
  62. if (ha->flags.pci_channel_io_perm_failure) {
  63. ql_log(ql_log_warn, vha, 0x1003,
  64. "Perm failure on EEH timeout MBX, exiting.\n");
  65. return QLA_FUNCTION_TIMEOUT;
  66. }
  67. if (ha->flags.isp82xx_fw_hung) {
  68. /* Setting Link-Down error */
  69. mcp->mb[0] = MBS_LINK_DOWN_ERROR;
  70. ql_log(ql_log_warn, vha, 0x1004,
  71. "FW hung = %d.\n", ha->flags.isp82xx_fw_hung);
  72. return QLA_FUNCTION_TIMEOUT;
  73. }
  74. /*
  75. * Wait for active mailbox commands to finish by waiting at most tov
  76. * seconds. This is to serialize actual issuing of mailbox cmds during
  77. * non ISP abort time.
  78. */
  79. if (!wait_for_completion_timeout(&ha->mbx_cmd_comp, mcp->tov * HZ)) {
  80. /* Timeout occurred. Return error. */
  81. ql_log(ql_log_warn, vha, 0x1005,
  82. "Cmd access timeout, cmd=0x%x, Exiting.\n",
  83. mcp->mb[0]);
  84. return QLA_FUNCTION_TIMEOUT;
  85. }
  86. ha->flags.mbox_busy = 1;
  87. /* Save mailbox command for debug */
  88. ha->mcp = mcp;
  89. ql_dbg(ql_dbg_mbx, vha, 0x1006,
  90. "Prepare to issue mbox cmd=0x%x.\n", mcp->mb[0]);
  91. spin_lock_irqsave(&ha->hardware_lock, flags);
  92. /* Load mailbox registers. */
  93. if (IS_QLA82XX(ha))
  94. optr = (uint16_t __iomem *)&reg->isp82.mailbox_in[0];
  95. else if (IS_FWI2_CAPABLE(ha) && !IS_QLA82XX(ha))
  96. optr = (uint16_t __iomem *)&reg->isp24.mailbox0;
  97. else
  98. optr = (uint16_t __iomem *)MAILBOX_REG(ha, &reg->isp, 0);
  99. iptr = mcp->mb;
  100. command = mcp->mb[0];
  101. mboxes = mcp->out_mb;
  102. for (cnt = 0; cnt < ha->mbx_count; cnt++) {
  103. if (IS_QLA2200(ha) && cnt == 8)
  104. optr =
  105. (uint16_t __iomem *)MAILBOX_REG(ha, &reg->isp, 8);
  106. if (mboxes & BIT_0)
  107. WRT_REG_WORD(optr, *iptr);
  108. mboxes >>= 1;
  109. optr++;
  110. iptr++;
  111. }
  112. ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1111,
  113. "Loaded MBX registers (displayed in bytes) =.\n");
  114. ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1112,
  115. (uint8_t *)mcp->mb, 16);
  116. ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1113,
  117. ".\n");
  118. ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1114,
  119. ((uint8_t *)mcp->mb + 0x10), 16);
  120. ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1115,
  121. ".\n");
  122. ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1116,
  123. ((uint8_t *)mcp->mb + 0x20), 8);
  124. ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1117,
  125. "I/O Address = %p.\n", optr);
  126. ql_dump_regs(ql_dbg_mbx + ql_dbg_buffer, vha, 0x100e);
  127. /* Issue set host interrupt command to send cmd out. */
  128. ha->flags.mbox_int = 0;
  129. clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
  130. /* Unlock mbx registers and wait for interrupt */
  131. ql_dbg(ql_dbg_mbx, vha, 0x100f,
  132. "Going to unlock irq & waiting for interrupts. "
  133. "jiffies=%lx.\n", jiffies);
  134. /* Wait for mbx cmd completion until timeout */
  135. if ((!abort_active && io_lock_on) || IS_NOPOLLING_TYPE(ha)) {
  136. set_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags);
  137. if (IS_QLA82XX(ha)) {
  138. if (RD_REG_DWORD(&reg->isp82.hint) &
  139. HINT_MBX_INT_PENDING) {
  140. spin_unlock_irqrestore(&ha->hardware_lock,
  141. flags);
  142. ha->flags.mbox_busy = 0;
  143. ql_dbg(ql_dbg_mbx, vha, 0x1010,
  144. "Pending mailbox timeout, exiting.\n");
  145. rval = QLA_FUNCTION_TIMEOUT;
  146. goto premature_exit;
  147. }
  148. WRT_REG_DWORD(&reg->isp82.hint, HINT_MBX_INT_PENDING);
  149. } else if (IS_FWI2_CAPABLE(ha))
  150. WRT_REG_DWORD(&reg->isp24.hccr, HCCRX_SET_HOST_INT);
  151. else
  152. WRT_REG_WORD(&reg->isp.hccr, HCCR_SET_HOST_INT);
  153. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  154. wait_for_completion_timeout(&ha->mbx_intr_comp, mcp->tov * HZ);
  155. clear_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags);
  156. } else {
  157. ql_dbg(ql_dbg_mbx, vha, 0x1011,
  158. "Cmd=%x Polling Mode.\n", command);
  159. if (IS_QLA82XX(ha)) {
  160. if (RD_REG_DWORD(&reg->isp82.hint) &
  161. HINT_MBX_INT_PENDING) {
  162. spin_unlock_irqrestore(&ha->hardware_lock,
  163. flags);
  164. ha->flags.mbox_busy = 0;
  165. ql_dbg(ql_dbg_mbx, vha, 0x1012,
  166. "Pending mailbox timeout, exiting.\n");
  167. rval = QLA_FUNCTION_TIMEOUT;
  168. goto premature_exit;
  169. }
  170. WRT_REG_DWORD(&reg->isp82.hint, HINT_MBX_INT_PENDING);
  171. } else if (IS_FWI2_CAPABLE(ha))
  172. WRT_REG_DWORD(&reg->isp24.hccr, HCCRX_SET_HOST_INT);
  173. else
  174. WRT_REG_WORD(&reg->isp.hccr, HCCR_SET_HOST_INT);
  175. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  176. wait_time = jiffies + mcp->tov * HZ; /* wait at most tov secs */
  177. while (!ha->flags.mbox_int) {
  178. if (time_after(jiffies, wait_time))
  179. break;
  180. /* Check for pending interrupts. */
  181. qla2x00_poll(ha->rsp_q_map[0]);
  182. if (!ha->flags.mbox_int &&
  183. !(IS_QLA2200(ha) &&
  184. command == MBC_LOAD_RISC_RAM_EXTENDED))
  185. msleep(10);
  186. } /* while */
  187. ql_dbg(ql_dbg_mbx, vha, 0x1013,
  188. "Waited %d sec.\n",
  189. (uint)((jiffies - (wait_time - (mcp->tov * HZ)))/HZ));
  190. }
  191. /* Check whether we timed out */
  192. if (ha->flags.mbox_int) {
  193. uint16_t *iptr2;
  194. ql_dbg(ql_dbg_mbx, vha, 0x1014,
  195. "Cmd=%x completed.\n", command);
  196. /* Got interrupt. Clear the flag. */
  197. ha->flags.mbox_int = 0;
  198. clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
  199. if (ha->flags.isp82xx_fw_hung) {
  200. ha->flags.mbox_busy = 0;
  201. /* Setting Link-Down error */
  202. mcp->mb[0] = MBS_LINK_DOWN_ERROR;
  203. ha->mcp = NULL;
  204. rval = QLA_FUNCTION_FAILED;
  205. ql_log(ql_log_warn, vha, 0x1015,
  206. "FW hung = %d.\n", ha->flags.isp82xx_fw_hung);
  207. goto premature_exit;
  208. }
  209. if (ha->mailbox_out[0] != MBS_COMMAND_COMPLETE)
  210. rval = QLA_FUNCTION_FAILED;
  211. /* Load return mailbox registers. */
  212. iptr2 = mcp->mb;
  213. iptr = (uint16_t *)&ha->mailbox_out[0];
  214. mboxes = mcp->in_mb;
  215. for (cnt = 0; cnt < ha->mbx_count; cnt++) {
  216. if (mboxes & BIT_0)
  217. *iptr2 = *iptr;
  218. mboxes >>= 1;
  219. iptr2++;
  220. iptr++;
  221. }
  222. } else {
  223. uint16_t mb0;
  224. uint32_t ictrl;
  225. if (IS_FWI2_CAPABLE(ha)) {
  226. mb0 = RD_REG_WORD(&reg->isp24.mailbox0);
  227. ictrl = RD_REG_DWORD(&reg->isp24.ictrl);
  228. } else {
  229. mb0 = RD_MAILBOX_REG(ha, &reg->isp, 0);
  230. ictrl = RD_REG_WORD(&reg->isp.ictrl);
  231. }
  232. ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1119,
  233. "MBX Command timeout for cmd %x, iocontrol=%x jiffies=%lx "
  234. "mb[0]=0x%x\n", command, ictrl, jiffies, mb0);
  235. ql_dump_regs(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1019);
  236. /*
  237. * Attempt to capture a firmware dump for further analysis
  238. * of the current firmware state
  239. */
  240. ha->isp_ops->fw_dump(vha, 0);
  241. rval = QLA_FUNCTION_TIMEOUT;
  242. }
  243. ha->flags.mbox_busy = 0;
  244. /* Clean up */
  245. ha->mcp = NULL;
  246. if ((abort_active || !io_lock_on) && !IS_NOPOLLING_TYPE(ha)) {
  247. ql_dbg(ql_dbg_mbx, vha, 0x101a,
  248. "Checking for additional resp interrupt.\n");
  249. /* polling mode for non isp_abort commands. */
  250. qla2x00_poll(ha->rsp_q_map[0]);
  251. }
  252. if (rval == QLA_FUNCTION_TIMEOUT &&
  253. mcp->mb[0] != MBC_GEN_SYSTEM_ERROR) {
  254. if (!io_lock_on || (mcp->flags & IOCTL_CMD) ||
  255. ha->flags.eeh_busy) {
  256. /* not in dpc. schedule it for dpc to take over. */
  257. ql_dbg(ql_dbg_mbx, vha, 0x101b,
  258. "Timeout, schedule isp_abort_needed.\n");
  259. if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) &&
  260. !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
  261. !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
  262. if (IS_QLA82XX(ha)) {
  263. ql_dbg(ql_dbg_mbx, vha, 0x112a,
  264. "disabling pause transmit on port "
  265. "0 & 1.\n");
  266. qla82xx_wr_32(ha,
  267. QLA82XX_CRB_NIU + 0x98,
  268. CRB_NIU_XG_PAUSE_CTL_P0|
  269. CRB_NIU_XG_PAUSE_CTL_P1);
  270. }
  271. ql_log(ql_log_info, base_vha, 0x101c,
  272. "Mailbox cmd timeout occurred, cmd=0x%x, "
  273. "mb[0]=0x%x, eeh_busy=0x%x. Scheduling ISP "
  274. "abort.\n", command, mcp->mb[0],
  275. ha->flags.eeh_busy);
  276. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  277. qla2xxx_wake_dpc(vha);
  278. }
  279. } else if (!abort_active) {
  280. /* call abort directly since we are in the DPC thread */
  281. ql_dbg(ql_dbg_mbx, vha, 0x101d,
  282. "Timeout, calling abort_isp.\n");
  283. if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) &&
  284. !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
  285. !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
  286. if (IS_QLA82XX(ha)) {
  287. ql_dbg(ql_dbg_mbx, vha, 0x112b,
  288. "disabling pause transmit on port "
  289. "0 & 1.\n");
  290. qla82xx_wr_32(ha,
  291. QLA82XX_CRB_NIU + 0x98,
  292. CRB_NIU_XG_PAUSE_CTL_P0|
  293. CRB_NIU_XG_PAUSE_CTL_P1);
  294. }
  295. ql_log(ql_log_info, base_vha, 0x101e,
  296. "Mailbox cmd timeout occurred, cmd=0x%x, "
  297. "mb[0]=0x%x. Scheduling ISP abort ",
  298. command, mcp->mb[0]);
  299. set_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags);
  300. clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  301. /* Allow next mbx cmd to come in. */
  302. complete(&ha->mbx_cmd_comp);
  303. if (ha->isp_ops->abort_isp(vha)) {
  304. /* Failed. retry later. */
  305. set_bit(ISP_ABORT_NEEDED,
  306. &vha->dpc_flags);
  307. }
  308. clear_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags);
  309. ql_dbg(ql_dbg_mbx, vha, 0x101f,
  310. "Finished abort_isp.\n");
  311. goto mbx_done;
  312. }
  313. }
  314. }
  315. premature_exit:
  316. /* Allow next mbx cmd to come in. */
  317. complete(&ha->mbx_cmd_comp);
  318. mbx_done:
  319. if (rval) {
  320. ql_dbg(ql_dbg_mbx, base_vha, 0x1020,
  321. "**** Failed mbx[0]=%x, mb[1]=%x, mb[2]=%x, mb[3]=%x, cmd=%x ****.\n",
  322. mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3], command);
  323. } else {
  324. ql_dbg(ql_dbg_mbx, base_vha, 0x1021, "Done %s.\n", __func__);
  325. }
  326. return rval;
  327. }
  328. int
  329. qla2x00_load_ram(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t risc_addr,
  330. uint32_t risc_code_size)
  331. {
  332. int rval;
  333. struct qla_hw_data *ha = vha->hw;
  334. mbx_cmd_t mc;
  335. mbx_cmd_t *mcp = &mc;
  336. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1022,
  337. "Entered %s.\n", __func__);
  338. if (MSW(risc_addr) || IS_FWI2_CAPABLE(ha)) {
  339. mcp->mb[0] = MBC_LOAD_RISC_RAM_EXTENDED;
  340. mcp->mb[8] = MSW(risc_addr);
  341. mcp->out_mb = MBX_8|MBX_0;
  342. } else {
  343. mcp->mb[0] = MBC_LOAD_RISC_RAM;
  344. mcp->out_mb = MBX_0;
  345. }
  346. mcp->mb[1] = LSW(risc_addr);
  347. mcp->mb[2] = MSW(req_dma);
  348. mcp->mb[3] = LSW(req_dma);
  349. mcp->mb[6] = MSW(MSD(req_dma));
  350. mcp->mb[7] = LSW(MSD(req_dma));
  351. mcp->out_mb |= MBX_7|MBX_6|MBX_3|MBX_2|MBX_1;
  352. if (IS_FWI2_CAPABLE(ha)) {
  353. mcp->mb[4] = MSW(risc_code_size);
  354. mcp->mb[5] = LSW(risc_code_size);
  355. mcp->out_mb |= MBX_5|MBX_4;
  356. } else {
  357. mcp->mb[4] = LSW(risc_code_size);
  358. mcp->out_mb |= MBX_4;
  359. }
  360. mcp->in_mb = MBX_0;
  361. mcp->tov = MBX_TOV_SECONDS;
  362. mcp->flags = 0;
  363. rval = qla2x00_mailbox_command(vha, mcp);
  364. if (rval != QLA_SUCCESS) {
  365. ql_dbg(ql_dbg_mbx, vha, 0x1023,
  366. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  367. } else {
  368. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1024,
  369. "Done %s.\n", __func__);
  370. }
  371. return rval;
  372. }
  373. #define EXTENDED_BB_CREDITS BIT_0
  374. /*
  375. * qla2x00_execute_fw
  376. * Start adapter firmware.
  377. *
  378. * Input:
  379. * ha = adapter block pointer.
  380. * TARGET_QUEUE_LOCK must be released.
  381. * ADAPTER_STATE_LOCK must be released.
  382. *
  383. * Returns:
  384. * qla2x00 local function return status code.
  385. *
  386. * Context:
  387. * Kernel context.
  388. */
  389. int
  390. qla2x00_execute_fw(scsi_qla_host_t *vha, uint32_t risc_addr)
  391. {
  392. int rval;
  393. struct qla_hw_data *ha = vha->hw;
  394. mbx_cmd_t mc;
  395. mbx_cmd_t *mcp = &mc;
  396. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1025,
  397. "Entered %s.\n", __func__);
  398. mcp->mb[0] = MBC_EXECUTE_FIRMWARE;
  399. mcp->out_mb = MBX_0;
  400. mcp->in_mb = MBX_0;
  401. if (IS_FWI2_CAPABLE(ha)) {
  402. mcp->mb[1] = MSW(risc_addr);
  403. mcp->mb[2] = LSW(risc_addr);
  404. mcp->mb[3] = 0;
  405. if (IS_QLA81XX(ha) || IS_QLA83XX(ha)) {
  406. struct nvram_81xx *nv = ha->nvram;
  407. mcp->mb[4] = (nv->enhanced_features &
  408. EXTENDED_BB_CREDITS);
  409. } else
  410. mcp->mb[4] = 0;
  411. mcp->out_mb |= MBX_4|MBX_3|MBX_2|MBX_1;
  412. mcp->in_mb |= MBX_1;
  413. } else {
  414. mcp->mb[1] = LSW(risc_addr);
  415. mcp->out_mb |= MBX_1;
  416. if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
  417. mcp->mb[2] = 0;
  418. mcp->out_mb |= MBX_2;
  419. }
  420. }
  421. mcp->tov = MBX_TOV_SECONDS;
  422. mcp->flags = 0;
  423. rval = qla2x00_mailbox_command(vha, mcp);
  424. if (rval != QLA_SUCCESS) {
  425. ql_dbg(ql_dbg_mbx, vha, 0x1026,
  426. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  427. } else {
  428. if (IS_FWI2_CAPABLE(ha)) {
  429. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1027,
  430. "Done exchanges=%x.\n", mcp->mb[1]);
  431. } else {
  432. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1028,
  433. "Done %s.\n", __func__);
  434. }
  435. }
  436. return rval;
  437. }
  438. /*
  439. * qla2x00_get_fw_version
  440. * Get firmware version.
  441. *
  442. * Input:
  443. * ha: adapter state pointer.
  444. * major: pointer for major number.
  445. * minor: pointer for minor number.
  446. * subminor: pointer for subminor number.
  447. *
  448. * Returns:
  449. * qla2x00 local function return status code.
  450. *
  451. * Context:
  452. * Kernel context.
  453. */
  454. int
  455. qla2x00_get_fw_version(scsi_qla_host_t *vha)
  456. {
  457. int rval;
  458. mbx_cmd_t mc;
  459. mbx_cmd_t *mcp = &mc;
  460. struct qla_hw_data *ha = vha->hw;
  461. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1029,
  462. "Entered %s.\n", __func__);
  463. mcp->mb[0] = MBC_GET_FIRMWARE_VERSION;
  464. mcp->out_mb = MBX_0;
  465. mcp->in_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  466. if (IS_QLA81XX(vha->hw) || IS_QLA8031(ha))
  467. mcp->in_mb |= MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8;
  468. if (IS_QLA83XX(vha->hw))
  469. mcp->in_mb |= MBX_17|MBX_16|MBX_15;
  470. mcp->flags = 0;
  471. mcp->tov = MBX_TOV_SECONDS;
  472. rval = qla2x00_mailbox_command(vha, mcp);
  473. if (rval != QLA_SUCCESS)
  474. goto failed;
  475. /* Return mailbox data. */
  476. ha->fw_major_version = mcp->mb[1];
  477. ha->fw_minor_version = mcp->mb[2];
  478. ha->fw_subminor_version = mcp->mb[3];
  479. ha->fw_attributes = mcp->mb[6];
  480. if (IS_QLA2100(vha->hw) || IS_QLA2200(vha->hw))
  481. ha->fw_memory_size = 0x1FFFF; /* Defaults to 128KB. */
  482. else
  483. ha->fw_memory_size = (mcp->mb[5] << 16) | mcp->mb[4];
  484. if (IS_QLA81XX(vha->hw) || IS_QLA8031(vha->hw)) {
  485. ha->mpi_version[0] = mcp->mb[10] & 0xff;
  486. ha->mpi_version[1] = mcp->mb[11] >> 8;
  487. ha->mpi_version[2] = mcp->mb[11] & 0xff;
  488. ha->mpi_capabilities = (mcp->mb[12] << 16) | mcp->mb[13];
  489. ha->phy_version[0] = mcp->mb[8] & 0xff;
  490. ha->phy_version[1] = mcp->mb[9] >> 8;
  491. ha->phy_version[2] = mcp->mb[9] & 0xff;
  492. }
  493. if (IS_QLA83XX(ha)) {
  494. if (mcp->mb[6] & BIT_15) {
  495. ha->fw_attributes_h = mcp->mb[15];
  496. ha->fw_attributes_ext[0] = mcp->mb[16];
  497. ha->fw_attributes_ext[1] = mcp->mb[17];
  498. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1139,
  499. "%s: FW_attributes Upper: 0x%x, Lower: 0x%x.\n",
  500. __func__, mcp->mb[15], mcp->mb[6]);
  501. } else
  502. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x112f,
  503. "%s: FwAttributes [Upper] invalid, MB6:%04x\n",
  504. __func__, mcp->mb[6]);
  505. }
  506. failed:
  507. if (rval != QLA_SUCCESS) {
  508. /*EMPTY*/
  509. ql_dbg(ql_dbg_mbx, vha, 0x102a, "Failed=%x.\n", rval);
  510. } else {
  511. /*EMPTY*/
  512. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102b,
  513. "Done %s.\n", __func__);
  514. }
  515. return rval;
  516. }
  517. /*
  518. * qla2x00_get_fw_options
  519. * Set firmware options.
  520. *
  521. * Input:
  522. * ha = adapter block pointer.
  523. * fwopt = pointer for firmware options.
  524. *
  525. * Returns:
  526. * qla2x00 local function return status code.
  527. *
  528. * Context:
  529. * Kernel context.
  530. */
  531. int
  532. qla2x00_get_fw_options(scsi_qla_host_t *vha, uint16_t *fwopts)
  533. {
  534. int rval;
  535. mbx_cmd_t mc;
  536. mbx_cmd_t *mcp = &mc;
  537. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102c,
  538. "Entered %s.\n", __func__);
  539. mcp->mb[0] = MBC_GET_FIRMWARE_OPTION;
  540. mcp->out_mb = MBX_0;
  541. mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
  542. mcp->tov = MBX_TOV_SECONDS;
  543. mcp->flags = 0;
  544. rval = qla2x00_mailbox_command(vha, mcp);
  545. if (rval != QLA_SUCCESS) {
  546. /*EMPTY*/
  547. ql_dbg(ql_dbg_mbx, vha, 0x102d, "Failed=%x.\n", rval);
  548. } else {
  549. fwopts[0] = mcp->mb[0];
  550. fwopts[1] = mcp->mb[1];
  551. fwopts[2] = mcp->mb[2];
  552. fwopts[3] = mcp->mb[3];
  553. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102e,
  554. "Done %s.\n", __func__);
  555. }
  556. return rval;
  557. }
  558. /*
  559. * qla2x00_set_fw_options
  560. * Set firmware options.
  561. *
  562. * Input:
  563. * ha = adapter block pointer.
  564. * fwopt = pointer for firmware options.
  565. *
  566. * Returns:
  567. * qla2x00 local function return status code.
  568. *
  569. * Context:
  570. * Kernel context.
  571. */
  572. int
  573. qla2x00_set_fw_options(scsi_qla_host_t *vha, uint16_t *fwopts)
  574. {
  575. int rval;
  576. mbx_cmd_t mc;
  577. mbx_cmd_t *mcp = &mc;
  578. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102f,
  579. "Entered %s.\n", __func__);
  580. mcp->mb[0] = MBC_SET_FIRMWARE_OPTION;
  581. mcp->mb[1] = fwopts[1];
  582. mcp->mb[2] = fwopts[2];
  583. mcp->mb[3] = fwopts[3];
  584. mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
  585. mcp->in_mb = MBX_0;
  586. if (IS_FWI2_CAPABLE(vha->hw)) {
  587. mcp->in_mb |= MBX_1;
  588. } else {
  589. mcp->mb[10] = fwopts[10];
  590. mcp->mb[11] = fwopts[11];
  591. mcp->mb[12] = 0; /* Undocumented, but used */
  592. mcp->out_mb |= MBX_12|MBX_11|MBX_10;
  593. }
  594. mcp->tov = MBX_TOV_SECONDS;
  595. mcp->flags = 0;
  596. rval = qla2x00_mailbox_command(vha, mcp);
  597. fwopts[0] = mcp->mb[0];
  598. if (rval != QLA_SUCCESS) {
  599. /*EMPTY*/
  600. ql_dbg(ql_dbg_mbx, vha, 0x1030,
  601. "Failed=%x (%x/%x).\n", rval, mcp->mb[0], mcp->mb[1]);
  602. } else {
  603. /*EMPTY*/
  604. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1031,
  605. "Done %s.\n", __func__);
  606. }
  607. return rval;
  608. }
  609. /*
  610. * qla2x00_mbx_reg_test
  611. * Mailbox register wrap test.
  612. *
  613. * Input:
  614. * ha = adapter block pointer.
  615. * TARGET_QUEUE_LOCK must be released.
  616. * ADAPTER_STATE_LOCK must be released.
  617. *
  618. * Returns:
  619. * qla2x00 local function return status code.
  620. *
  621. * Context:
  622. * Kernel context.
  623. */
  624. int
  625. qla2x00_mbx_reg_test(scsi_qla_host_t *vha)
  626. {
  627. int rval;
  628. mbx_cmd_t mc;
  629. mbx_cmd_t *mcp = &mc;
  630. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1032,
  631. "Entered %s.\n", __func__);
  632. mcp->mb[0] = MBC_MAILBOX_REGISTER_TEST;
  633. mcp->mb[1] = 0xAAAA;
  634. mcp->mb[2] = 0x5555;
  635. mcp->mb[3] = 0xAA55;
  636. mcp->mb[4] = 0x55AA;
  637. mcp->mb[5] = 0xA5A5;
  638. mcp->mb[6] = 0x5A5A;
  639. mcp->mb[7] = 0x2525;
  640. mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  641. mcp->in_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  642. mcp->tov = MBX_TOV_SECONDS;
  643. mcp->flags = 0;
  644. rval = qla2x00_mailbox_command(vha, mcp);
  645. if (rval == QLA_SUCCESS) {
  646. if (mcp->mb[1] != 0xAAAA || mcp->mb[2] != 0x5555 ||
  647. mcp->mb[3] != 0xAA55 || mcp->mb[4] != 0x55AA)
  648. rval = QLA_FUNCTION_FAILED;
  649. if (mcp->mb[5] != 0xA5A5 || mcp->mb[6] != 0x5A5A ||
  650. mcp->mb[7] != 0x2525)
  651. rval = QLA_FUNCTION_FAILED;
  652. }
  653. if (rval != QLA_SUCCESS) {
  654. /*EMPTY*/
  655. ql_dbg(ql_dbg_mbx, vha, 0x1033, "Failed=%x.\n", rval);
  656. } else {
  657. /*EMPTY*/
  658. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1034,
  659. "Done %s.\n", __func__);
  660. }
  661. return rval;
  662. }
  663. /*
  664. * qla2x00_verify_checksum
  665. * Verify firmware checksum.
  666. *
  667. * Input:
  668. * ha = adapter block pointer.
  669. * TARGET_QUEUE_LOCK must be released.
  670. * ADAPTER_STATE_LOCK must be released.
  671. *
  672. * Returns:
  673. * qla2x00 local function return status code.
  674. *
  675. * Context:
  676. * Kernel context.
  677. */
  678. int
  679. qla2x00_verify_checksum(scsi_qla_host_t *vha, uint32_t risc_addr)
  680. {
  681. int rval;
  682. mbx_cmd_t mc;
  683. mbx_cmd_t *mcp = &mc;
  684. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1035,
  685. "Entered %s.\n", __func__);
  686. mcp->mb[0] = MBC_VERIFY_CHECKSUM;
  687. mcp->out_mb = MBX_0;
  688. mcp->in_mb = MBX_0;
  689. if (IS_FWI2_CAPABLE(vha->hw)) {
  690. mcp->mb[1] = MSW(risc_addr);
  691. mcp->mb[2] = LSW(risc_addr);
  692. mcp->out_mb |= MBX_2|MBX_1;
  693. mcp->in_mb |= MBX_2|MBX_1;
  694. } else {
  695. mcp->mb[1] = LSW(risc_addr);
  696. mcp->out_mb |= MBX_1;
  697. mcp->in_mb |= MBX_1;
  698. }
  699. mcp->tov = MBX_TOV_SECONDS;
  700. mcp->flags = 0;
  701. rval = qla2x00_mailbox_command(vha, mcp);
  702. if (rval != QLA_SUCCESS) {
  703. ql_dbg(ql_dbg_mbx, vha, 0x1036,
  704. "Failed=%x chm sum=%x.\n", rval, IS_FWI2_CAPABLE(vha->hw) ?
  705. (mcp->mb[2] << 16) | mcp->mb[1] : mcp->mb[1]);
  706. } else {
  707. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1037,
  708. "Done %s.\n", __func__);
  709. }
  710. return rval;
  711. }
  712. /*
  713. * qla2x00_issue_iocb
  714. * Issue IOCB using mailbox command
  715. *
  716. * Input:
  717. * ha = adapter state pointer.
  718. * buffer = buffer pointer.
  719. * phys_addr = physical address of buffer.
  720. * size = size of buffer.
  721. * TARGET_QUEUE_LOCK must be released.
  722. * ADAPTER_STATE_LOCK must be released.
  723. *
  724. * Returns:
  725. * qla2x00 local function return status code.
  726. *
  727. * Context:
  728. * Kernel context.
  729. */
  730. int
  731. qla2x00_issue_iocb_timeout(scsi_qla_host_t *vha, void *buffer,
  732. dma_addr_t phys_addr, size_t size, uint32_t tov)
  733. {
  734. int rval;
  735. mbx_cmd_t mc;
  736. mbx_cmd_t *mcp = &mc;
  737. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1038,
  738. "Entered %s.\n", __func__);
  739. mcp->mb[0] = MBC_IOCB_COMMAND_A64;
  740. mcp->mb[1] = 0;
  741. mcp->mb[2] = MSW(phys_addr);
  742. mcp->mb[3] = LSW(phys_addr);
  743. mcp->mb[6] = MSW(MSD(phys_addr));
  744. mcp->mb[7] = LSW(MSD(phys_addr));
  745. mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
  746. mcp->in_mb = MBX_2|MBX_0;
  747. mcp->tov = tov;
  748. mcp->flags = 0;
  749. rval = qla2x00_mailbox_command(vha, mcp);
  750. if (rval != QLA_SUCCESS) {
  751. /*EMPTY*/
  752. ql_dbg(ql_dbg_mbx, vha, 0x1039, "Failed=%x.\n", rval);
  753. } else {
  754. sts_entry_t *sts_entry = (sts_entry_t *) buffer;
  755. /* Mask reserved bits. */
  756. sts_entry->entry_status &=
  757. IS_FWI2_CAPABLE(vha->hw) ? RF_MASK_24XX : RF_MASK;
  758. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103a,
  759. "Done %s.\n", __func__);
  760. }
  761. return rval;
  762. }
  763. int
  764. qla2x00_issue_iocb(scsi_qla_host_t *vha, void *buffer, dma_addr_t phys_addr,
  765. size_t size)
  766. {
  767. return qla2x00_issue_iocb_timeout(vha, buffer, phys_addr, size,
  768. MBX_TOV_SECONDS);
  769. }
  770. /*
  771. * qla2x00_abort_command
  772. * Abort command aborts a specified IOCB.
  773. *
  774. * Input:
  775. * ha = adapter block pointer.
  776. * sp = SB structure pointer.
  777. *
  778. * Returns:
  779. * qla2x00 local function return status code.
  780. *
  781. * Context:
  782. * Kernel context.
  783. */
  784. int
  785. qla2x00_abort_command(srb_t *sp)
  786. {
  787. unsigned long flags = 0;
  788. int rval;
  789. uint32_t handle = 0;
  790. mbx_cmd_t mc;
  791. mbx_cmd_t *mcp = &mc;
  792. fc_port_t *fcport = sp->fcport;
  793. scsi_qla_host_t *vha = fcport->vha;
  794. struct qla_hw_data *ha = vha->hw;
  795. struct req_que *req = vha->req;
  796. struct scsi_cmnd *cmd = GET_CMD_SP(sp);
  797. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103b,
  798. "Entered %s.\n", __func__);
  799. spin_lock_irqsave(&ha->hardware_lock, flags);
  800. for (handle = 1; handle < MAX_OUTSTANDING_COMMANDS; handle++) {
  801. if (req->outstanding_cmds[handle] == sp)
  802. break;
  803. }
  804. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  805. if (handle == MAX_OUTSTANDING_COMMANDS) {
  806. /* command not found */
  807. return QLA_FUNCTION_FAILED;
  808. }
  809. mcp->mb[0] = MBC_ABORT_COMMAND;
  810. if (HAS_EXTENDED_IDS(ha))
  811. mcp->mb[1] = fcport->loop_id;
  812. else
  813. mcp->mb[1] = fcport->loop_id << 8;
  814. mcp->mb[2] = (uint16_t)handle;
  815. mcp->mb[3] = (uint16_t)(handle >> 16);
  816. mcp->mb[6] = (uint16_t)cmd->device->lun;
  817. mcp->out_mb = MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
  818. mcp->in_mb = MBX_0;
  819. mcp->tov = MBX_TOV_SECONDS;
  820. mcp->flags = 0;
  821. rval = qla2x00_mailbox_command(vha, mcp);
  822. if (rval != QLA_SUCCESS) {
  823. ql_dbg(ql_dbg_mbx, vha, 0x103c, "Failed=%x.\n", rval);
  824. } else {
  825. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103d,
  826. "Done %s.\n", __func__);
  827. }
  828. return rval;
  829. }
  830. int
  831. qla2x00_abort_target(struct fc_port *fcport, unsigned int l, int tag)
  832. {
  833. int rval, rval2;
  834. mbx_cmd_t mc;
  835. mbx_cmd_t *mcp = &mc;
  836. scsi_qla_host_t *vha;
  837. struct req_que *req;
  838. struct rsp_que *rsp;
  839. l = l;
  840. vha = fcport->vha;
  841. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103e,
  842. "Entered %s.\n", __func__);
  843. req = vha->hw->req_q_map[0];
  844. rsp = req->rsp;
  845. mcp->mb[0] = MBC_ABORT_TARGET;
  846. mcp->out_mb = MBX_9|MBX_2|MBX_1|MBX_0;
  847. if (HAS_EXTENDED_IDS(vha->hw)) {
  848. mcp->mb[1] = fcport->loop_id;
  849. mcp->mb[10] = 0;
  850. mcp->out_mb |= MBX_10;
  851. } else {
  852. mcp->mb[1] = fcport->loop_id << 8;
  853. }
  854. mcp->mb[2] = vha->hw->loop_reset_delay;
  855. mcp->mb[9] = vha->vp_idx;
  856. mcp->in_mb = MBX_0;
  857. mcp->tov = MBX_TOV_SECONDS;
  858. mcp->flags = 0;
  859. rval = qla2x00_mailbox_command(vha, mcp);
  860. if (rval != QLA_SUCCESS) {
  861. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103f,
  862. "Failed=%x.\n", rval);
  863. }
  864. /* Issue marker IOCB. */
  865. rval2 = qla2x00_marker(vha, req, rsp, fcport->loop_id, 0,
  866. MK_SYNC_ID);
  867. if (rval2 != QLA_SUCCESS) {
  868. ql_dbg(ql_dbg_mbx, vha, 0x1040,
  869. "Failed to issue marker IOCB (%x).\n", rval2);
  870. } else {
  871. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1041,
  872. "Done %s.\n", __func__);
  873. }
  874. return rval;
  875. }
  876. int
  877. qla2x00_lun_reset(struct fc_port *fcport, unsigned int l, int tag)
  878. {
  879. int rval, rval2;
  880. mbx_cmd_t mc;
  881. mbx_cmd_t *mcp = &mc;
  882. scsi_qla_host_t *vha;
  883. struct req_que *req;
  884. struct rsp_que *rsp;
  885. vha = fcport->vha;
  886. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1042,
  887. "Entered %s.\n", __func__);
  888. req = vha->hw->req_q_map[0];
  889. rsp = req->rsp;
  890. mcp->mb[0] = MBC_LUN_RESET;
  891. mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0;
  892. if (HAS_EXTENDED_IDS(vha->hw))
  893. mcp->mb[1] = fcport->loop_id;
  894. else
  895. mcp->mb[1] = fcport->loop_id << 8;
  896. mcp->mb[2] = l;
  897. mcp->mb[3] = 0;
  898. mcp->mb[9] = vha->vp_idx;
  899. mcp->in_mb = MBX_0;
  900. mcp->tov = MBX_TOV_SECONDS;
  901. mcp->flags = 0;
  902. rval = qla2x00_mailbox_command(vha, mcp);
  903. if (rval != QLA_SUCCESS) {
  904. ql_dbg(ql_dbg_mbx, vha, 0x1043, "Failed=%x.\n", rval);
  905. }
  906. /* Issue marker IOCB. */
  907. rval2 = qla2x00_marker(vha, req, rsp, fcport->loop_id, l,
  908. MK_SYNC_ID_LUN);
  909. if (rval2 != QLA_SUCCESS) {
  910. ql_dbg(ql_dbg_mbx, vha, 0x1044,
  911. "Failed to issue marker IOCB (%x).\n", rval2);
  912. } else {
  913. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1045,
  914. "Done %s.\n", __func__);
  915. }
  916. return rval;
  917. }
  918. /*
  919. * qla2x00_get_adapter_id
  920. * Get adapter ID and topology.
  921. *
  922. * Input:
  923. * ha = adapter block pointer.
  924. * id = pointer for loop ID.
  925. * al_pa = pointer for AL_PA.
  926. * area = pointer for area.
  927. * domain = pointer for domain.
  928. * top = pointer for topology.
  929. * TARGET_QUEUE_LOCK must be released.
  930. * ADAPTER_STATE_LOCK must be released.
  931. *
  932. * Returns:
  933. * qla2x00 local function return status code.
  934. *
  935. * Context:
  936. * Kernel context.
  937. */
  938. int
  939. qla2x00_get_adapter_id(scsi_qla_host_t *vha, uint16_t *id, uint8_t *al_pa,
  940. uint8_t *area, uint8_t *domain, uint16_t *top, uint16_t *sw_cap)
  941. {
  942. int rval;
  943. mbx_cmd_t mc;
  944. mbx_cmd_t *mcp = &mc;
  945. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1046,
  946. "Entered %s.\n", __func__);
  947. mcp->mb[0] = MBC_GET_ADAPTER_LOOP_ID;
  948. mcp->mb[9] = vha->vp_idx;
  949. mcp->out_mb = MBX_9|MBX_0;
  950. mcp->in_mb = MBX_9|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
  951. if (IS_CNA_CAPABLE(vha->hw))
  952. mcp->in_mb |= MBX_13|MBX_12|MBX_11|MBX_10;
  953. mcp->tov = MBX_TOV_SECONDS;
  954. mcp->flags = 0;
  955. rval = qla2x00_mailbox_command(vha, mcp);
  956. if (mcp->mb[0] == MBS_COMMAND_ERROR)
  957. rval = QLA_COMMAND_ERROR;
  958. else if (mcp->mb[0] == MBS_INVALID_COMMAND)
  959. rval = QLA_INVALID_COMMAND;
  960. /* Return data. */
  961. *id = mcp->mb[1];
  962. *al_pa = LSB(mcp->mb[2]);
  963. *area = MSB(mcp->mb[2]);
  964. *domain = LSB(mcp->mb[3]);
  965. *top = mcp->mb[6];
  966. *sw_cap = mcp->mb[7];
  967. if (rval != QLA_SUCCESS) {
  968. /*EMPTY*/
  969. ql_dbg(ql_dbg_mbx, vha, 0x1047, "Failed=%x.\n", rval);
  970. } else {
  971. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1048,
  972. "Done %s.\n", __func__);
  973. if (IS_CNA_CAPABLE(vha->hw)) {
  974. vha->fcoe_vlan_id = mcp->mb[9] & 0xfff;
  975. vha->fcoe_fcf_idx = mcp->mb[10];
  976. vha->fcoe_vn_port_mac[5] = mcp->mb[11] >> 8;
  977. vha->fcoe_vn_port_mac[4] = mcp->mb[11] & 0xff;
  978. vha->fcoe_vn_port_mac[3] = mcp->mb[12] >> 8;
  979. vha->fcoe_vn_port_mac[2] = mcp->mb[12] & 0xff;
  980. vha->fcoe_vn_port_mac[1] = mcp->mb[13] >> 8;
  981. vha->fcoe_vn_port_mac[0] = mcp->mb[13] & 0xff;
  982. }
  983. }
  984. return rval;
  985. }
  986. /*
  987. * qla2x00_get_retry_cnt
  988. * Get current firmware login retry count and delay.
  989. *
  990. * Input:
  991. * ha = adapter block pointer.
  992. * retry_cnt = pointer to login retry count.
  993. * tov = pointer to login timeout value.
  994. *
  995. * Returns:
  996. * qla2x00 local function return status code.
  997. *
  998. * Context:
  999. * Kernel context.
  1000. */
  1001. int
  1002. qla2x00_get_retry_cnt(scsi_qla_host_t *vha, uint8_t *retry_cnt, uint8_t *tov,
  1003. uint16_t *r_a_tov)
  1004. {
  1005. int rval;
  1006. uint16_t ratov;
  1007. mbx_cmd_t mc;
  1008. mbx_cmd_t *mcp = &mc;
  1009. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1049,
  1010. "Entered %s.\n", __func__);
  1011. mcp->mb[0] = MBC_GET_RETRY_COUNT;
  1012. mcp->out_mb = MBX_0;
  1013. mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
  1014. mcp->tov = MBX_TOV_SECONDS;
  1015. mcp->flags = 0;
  1016. rval = qla2x00_mailbox_command(vha, mcp);
  1017. if (rval != QLA_SUCCESS) {
  1018. /*EMPTY*/
  1019. ql_dbg(ql_dbg_mbx, vha, 0x104a,
  1020. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  1021. } else {
  1022. /* Convert returned data and check our values. */
  1023. *r_a_tov = mcp->mb[3] / 2;
  1024. ratov = (mcp->mb[3]/2) / 10; /* mb[3] value is in 100ms */
  1025. if (mcp->mb[1] * ratov > (*retry_cnt) * (*tov)) {
  1026. /* Update to the larger values */
  1027. *retry_cnt = (uint8_t)mcp->mb[1];
  1028. *tov = ratov;
  1029. }
  1030. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104b,
  1031. "Done %s mb3=%d ratov=%d.\n", __func__, mcp->mb[3], ratov);
  1032. }
  1033. return rval;
  1034. }
  1035. /*
  1036. * qla2x00_init_firmware
  1037. * Initialize adapter firmware.
  1038. *
  1039. * Input:
  1040. * ha = adapter block pointer.
  1041. * dptr = Initialization control block pointer.
  1042. * size = size of initialization control block.
  1043. * TARGET_QUEUE_LOCK must be released.
  1044. * ADAPTER_STATE_LOCK must be released.
  1045. *
  1046. * Returns:
  1047. * qla2x00 local function return status code.
  1048. *
  1049. * Context:
  1050. * Kernel context.
  1051. */
  1052. int
  1053. qla2x00_init_firmware(scsi_qla_host_t *vha, uint16_t size)
  1054. {
  1055. int rval;
  1056. mbx_cmd_t mc;
  1057. mbx_cmd_t *mcp = &mc;
  1058. struct qla_hw_data *ha = vha->hw;
  1059. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104c,
  1060. "Entered %s.\n", __func__);
  1061. if (IS_QLA82XX(ha) && ql2xdbwr)
  1062. qla82xx_wr_32(ha, ha->nxdb_wr_ptr,
  1063. (0x04 | (ha->portnum << 5) | (0 << 8) | (0 << 16)));
  1064. if (ha->flags.npiv_supported)
  1065. mcp->mb[0] = MBC_MID_INITIALIZE_FIRMWARE;
  1066. else
  1067. mcp->mb[0] = MBC_INITIALIZE_FIRMWARE;
  1068. mcp->mb[1] = 0;
  1069. mcp->mb[2] = MSW(ha->init_cb_dma);
  1070. mcp->mb[3] = LSW(ha->init_cb_dma);
  1071. mcp->mb[6] = MSW(MSD(ha->init_cb_dma));
  1072. mcp->mb[7] = LSW(MSD(ha->init_cb_dma));
  1073. mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
  1074. if ((IS_QLA81XX(ha) || IS_QLA83XX(ha)) && ha->ex_init_cb->ex_version) {
  1075. mcp->mb[1] = BIT_0;
  1076. mcp->mb[10] = MSW(ha->ex_init_cb_dma);
  1077. mcp->mb[11] = LSW(ha->ex_init_cb_dma);
  1078. mcp->mb[12] = MSW(MSD(ha->ex_init_cb_dma));
  1079. mcp->mb[13] = LSW(MSD(ha->ex_init_cb_dma));
  1080. mcp->mb[14] = sizeof(*ha->ex_init_cb);
  1081. mcp->out_mb |= MBX_14|MBX_13|MBX_12|MBX_11|MBX_10;
  1082. }
  1083. /* 1 and 2 should normally be captured. */
  1084. mcp->in_mb = MBX_2|MBX_1|MBX_0;
  1085. if (IS_QLA83XX(ha))
  1086. /* mb3 is additional info about the installed SFP. */
  1087. mcp->in_mb |= MBX_3;
  1088. mcp->buf_size = size;
  1089. mcp->flags = MBX_DMA_OUT;
  1090. mcp->tov = MBX_TOV_SECONDS;
  1091. rval = qla2x00_mailbox_command(vha, mcp);
  1092. if (rval != QLA_SUCCESS) {
  1093. /*EMPTY*/
  1094. ql_dbg(ql_dbg_mbx, vha, 0x104d,
  1095. "Failed=%x mb[0]=%x, mb[1]=%x, mb[2]=%x, mb[3]=%x,.\n",
  1096. rval, mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3]);
  1097. } else {
  1098. /*EMPTY*/
  1099. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104e,
  1100. "Done %s.\n", __func__);
  1101. }
  1102. return rval;
  1103. }
  1104. /*
  1105. * qla2x00_get_node_name_list
  1106. * Issue get node name list mailbox command, kmalloc()
  1107. * and return the resulting list. Caller must kfree() it!
  1108. *
  1109. * Input:
  1110. * ha = adapter state pointer.
  1111. * out_data = resulting list
  1112. * out_len = length of the resulting list
  1113. *
  1114. * Returns:
  1115. * qla2x00 local function return status code.
  1116. *
  1117. * Context:
  1118. * Kernel context.
  1119. */
  1120. int
  1121. qla2x00_get_node_name_list(scsi_qla_host_t *vha, void **out_data, int *out_len)
  1122. {
  1123. struct qla_hw_data *ha = vha->hw;
  1124. struct qla_port_24xx_data *list = NULL;
  1125. void *pmap;
  1126. mbx_cmd_t mc;
  1127. dma_addr_t pmap_dma;
  1128. ulong dma_size;
  1129. int rval, left;
  1130. left = 1;
  1131. while (left > 0) {
  1132. dma_size = left * sizeof(*list);
  1133. pmap = dma_alloc_coherent(&ha->pdev->dev, dma_size,
  1134. &pmap_dma, GFP_KERNEL);
  1135. if (!pmap) {
  1136. ql_log(ql_log_warn, vha, 0x113f,
  1137. "%s(%ld): DMA Alloc failed of %ld\n",
  1138. __func__, vha->host_no, dma_size);
  1139. rval = QLA_MEMORY_ALLOC_FAILED;
  1140. goto out;
  1141. }
  1142. mc.mb[0] = MBC_PORT_NODE_NAME_LIST;
  1143. mc.mb[1] = BIT_1 | BIT_3;
  1144. mc.mb[2] = MSW(pmap_dma);
  1145. mc.mb[3] = LSW(pmap_dma);
  1146. mc.mb[6] = MSW(MSD(pmap_dma));
  1147. mc.mb[7] = LSW(MSD(pmap_dma));
  1148. mc.mb[8] = dma_size;
  1149. mc.out_mb = MBX_0|MBX_1|MBX_2|MBX_3|MBX_6|MBX_7|MBX_8;
  1150. mc.in_mb = MBX_0|MBX_1;
  1151. mc.tov = 30;
  1152. mc.flags = MBX_DMA_IN;
  1153. rval = qla2x00_mailbox_command(vha, &mc);
  1154. if (rval != QLA_SUCCESS) {
  1155. if ((mc.mb[0] == MBS_COMMAND_ERROR) &&
  1156. (mc.mb[1] == 0xA)) {
  1157. left += le16_to_cpu(mc.mb[2]) /
  1158. sizeof(struct qla_port_24xx_data);
  1159. goto restart;
  1160. }
  1161. goto out_free;
  1162. }
  1163. left = 0;
  1164. list = kzalloc(dma_size, GFP_KERNEL);
  1165. if (!list) {
  1166. ql_log(ql_log_warn, vha, 0x1140,
  1167. "%s(%ld): failed to allocate node names list "
  1168. "structure.\n", __func__, vha->host_no);
  1169. rval = QLA_MEMORY_ALLOC_FAILED;
  1170. goto out_free;
  1171. }
  1172. memcpy(list, pmap, dma_size);
  1173. restart:
  1174. dma_free_coherent(&ha->pdev->dev, dma_size, pmap, pmap_dma);
  1175. }
  1176. *out_data = list;
  1177. *out_len = dma_size;
  1178. out:
  1179. return rval;
  1180. out_free:
  1181. dma_free_coherent(&ha->pdev->dev, dma_size, pmap, pmap_dma);
  1182. return rval;
  1183. }
  1184. /*
  1185. * qla2x00_get_port_database
  1186. * Issue normal/enhanced get port database mailbox command
  1187. * and copy device name as necessary.
  1188. *
  1189. * Input:
  1190. * ha = adapter state pointer.
  1191. * dev = structure pointer.
  1192. * opt = enhanced cmd option byte.
  1193. *
  1194. * Returns:
  1195. * qla2x00 local function return status code.
  1196. *
  1197. * Context:
  1198. * Kernel context.
  1199. */
  1200. int
  1201. qla2x00_get_port_database(scsi_qla_host_t *vha, fc_port_t *fcport, uint8_t opt)
  1202. {
  1203. int rval;
  1204. mbx_cmd_t mc;
  1205. mbx_cmd_t *mcp = &mc;
  1206. port_database_t *pd;
  1207. struct port_database_24xx *pd24;
  1208. dma_addr_t pd_dma;
  1209. struct qla_hw_data *ha = vha->hw;
  1210. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104f,
  1211. "Entered %s.\n", __func__);
  1212. pd24 = NULL;
  1213. pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &pd_dma);
  1214. if (pd == NULL) {
  1215. ql_log(ql_log_warn, vha, 0x1050,
  1216. "Failed to allocate port database structure.\n");
  1217. return QLA_MEMORY_ALLOC_FAILED;
  1218. }
  1219. memset(pd, 0, max(PORT_DATABASE_SIZE, PORT_DATABASE_24XX_SIZE));
  1220. mcp->mb[0] = MBC_GET_PORT_DATABASE;
  1221. if (opt != 0 && !IS_FWI2_CAPABLE(ha))
  1222. mcp->mb[0] = MBC_ENHANCED_GET_PORT_DATABASE;
  1223. mcp->mb[2] = MSW(pd_dma);
  1224. mcp->mb[3] = LSW(pd_dma);
  1225. mcp->mb[6] = MSW(MSD(pd_dma));
  1226. mcp->mb[7] = LSW(MSD(pd_dma));
  1227. mcp->mb[9] = vha->vp_idx;
  1228. mcp->out_mb = MBX_9|MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
  1229. mcp->in_mb = MBX_0;
  1230. if (IS_FWI2_CAPABLE(ha)) {
  1231. mcp->mb[1] = fcport->loop_id;
  1232. mcp->mb[10] = opt;
  1233. mcp->out_mb |= MBX_10|MBX_1;
  1234. mcp->in_mb |= MBX_1;
  1235. } else if (HAS_EXTENDED_IDS(ha)) {
  1236. mcp->mb[1] = fcport->loop_id;
  1237. mcp->mb[10] = opt;
  1238. mcp->out_mb |= MBX_10|MBX_1;
  1239. } else {
  1240. mcp->mb[1] = fcport->loop_id << 8 | opt;
  1241. mcp->out_mb |= MBX_1;
  1242. }
  1243. mcp->buf_size = IS_FWI2_CAPABLE(ha) ?
  1244. PORT_DATABASE_24XX_SIZE : PORT_DATABASE_SIZE;
  1245. mcp->flags = MBX_DMA_IN;
  1246. mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
  1247. rval = qla2x00_mailbox_command(vha, mcp);
  1248. if (rval != QLA_SUCCESS)
  1249. goto gpd_error_out;
  1250. if (IS_FWI2_CAPABLE(ha)) {
  1251. uint64_t zero = 0;
  1252. pd24 = (struct port_database_24xx *) pd;
  1253. /* Check for logged in state. */
  1254. if (pd24->current_login_state != PDS_PRLI_COMPLETE &&
  1255. pd24->last_login_state != PDS_PRLI_COMPLETE) {
  1256. ql_dbg(ql_dbg_mbx, vha, 0x1051,
  1257. "Unable to verify login-state (%x/%x) for "
  1258. "loop_id %x.\n", pd24->current_login_state,
  1259. pd24->last_login_state, fcport->loop_id);
  1260. rval = QLA_FUNCTION_FAILED;
  1261. goto gpd_error_out;
  1262. }
  1263. if (fcport->loop_id == FC_NO_LOOP_ID ||
  1264. (memcmp(fcport->port_name, (uint8_t *)&zero, 8) &&
  1265. memcmp(fcport->port_name, pd24->port_name, 8))) {
  1266. /* We lost the device mid way. */
  1267. rval = QLA_NOT_LOGGED_IN;
  1268. goto gpd_error_out;
  1269. }
  1270. /* Names are little-endian. */
  1271. memcpy(fcport->node_name, pd24->node_name, WWN_SIZE);
  1272. memcpy(fcport->port_name, pd24->port_name, WWN_SIZE);
  1273. /* Get port_id of device. */
  1274. fcport->d_id.b.domain = pd24->port_id[0];
  1275. fcport->d_id.b.area = pd24->port_id[1];
  1276. fcport->d_id.b.al_pa = pd24->port_id[2];
  1277. fcport->d_id.b.rsvd_1 = 0;
  1278. /* If not target must be initiator or unknown type. */
  1279. if ((pd24->prli_svc_param_word_3[0] & BIT_4) == 0)
  1280. fcport->port_type = FCT_INITIATOR;
  1281. else
  1282. fcport->port_type = FCT_TARGET;
  1283. /* Passback COS information. */
  1284. fcport->supported_classes = (pd24->flags & PDF_CLASS_2) ?
  1285. FC_COS_CLASS2 : FC_COS_CLASS3;
  1286. if (pd24->prli_svc_param_word_3[0] & BIT_7)
  1287. fcport->flags |= FCF_CONF_COMP_SUPPORTED;
  1288. } else {
  1289. uint64_t zero = 0;
  1290. /* Check for logged in state. */
  1291. if (pd->master_state != PD_STATE_PORT_LOGGED_IN &&
  1292. pd->slave_state != PD_STATE_PORT_LOGGED_IN) {
  1293. ql_dbg(ql_dbg_mbx, vha, 0x100a,
  1294. "Unable to verify login-state (%x/%x) - "
  1295. "portid=%02x%02x%02x.\n", pd->master_state,
  1296. pd->slave_state, fcport->d_id.b.domain,
  1297. fcport->d_id.b.area, fcport->d_id.b.al_pa);
  1298. rval = QLA_FUNCTION_FAILED;
  1299. goto gpd_error_out;
  1300. }
  1301. if (fcport->loop_id == FC_NO_LOOP_ID ||
  1302. (memcmp(fcport->port_name, (uint8_t *)&zero, 8) &&
  1303. memcmp(fcport->port_name, pd->port_name, 8))) {
  1304. /* We lost the device mid way. */
  1305. rval = QLA_NOT_LOGGED_IN;
  1306. goto gpd_error_out;
  1307. }
  1308. /* Names are little-endian. */
  1309. memcpy(fcport->node_name, pd->node_name, WWN_SIZE);
  1310. memcpy(fcport->port_name, pd->port_name, WWN_SIZE);
  1311. /* Get port_id of device. */
  1312. fcport->d_id.b.domain = pd->port_id[0];
  1313. fcport->d_id.b.area = pd->port_id[3];
  1314. fcport->d_id.b.al_pa = pd->port_id[2];
  1315. fcport->d_id.b.rsvd_1 = 0;
  1316. /* If not target must be initiator or unknown type. */
  1317. if ((pd->prli_svc_param_word_3[0] & BIT_4) == 0)
  1318. fcport->port_type = FCT_INITIATOR;
  1319. else
  1320. fcport->port_type = FCT_TARGET;
  1321. /* Passback COS information. */
  1322. fcport->supported_classes = (pd->options & BIT_4) ?
  1323. FC_COS_CLASS2: FC_COS_CLASS3;
  1324. }
  1325. gpd_error_out:
  1326. dma_pool_free(ha->s_dma_pool, pd, pd_dma);
  1327. if (rval != QLA_SUCCESS) {
  1328. ql_dbg(ql_dbg_mbx, vha, 0x1052,
  1329. "Failed=%x mb[0]=%x mb[1]=%x.\n", rval,
  1330. mcp->mb[0], mcp->mb[1]);
  1331. } else {
  1332. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1053,
  1333. "Done %s.\n", __func__);
  1334. }
  1335. return rval;
  1336. }
  1337. /*
  1338. * qla2x00_get_firmware_state
  1339. * Get adapter firmware state.
  1340. *
  1341. * Input:
  1342. * ha = adapter block pointer.
  1343. * dptr = pointer for firmware state.
  1344. * TARGET_QUEUE_LOCK must be released.
  1345. * ADAPTER_STATE_LOCK must be released.
  1346. *
  1347. * Returns:
  1348. * qla2x00 local function return status code.
  1349. *
  1350. * Context:
  1351. * Kernel context.
  1352. */
  1353. int
  1354. qla2x00_get_firmware_state(scsi_qla_host_t *vha, uint16_t *states)
  1355. {
  1356. int rval;
  1357. mbx_cmd_t mc;
  1358. mbx_cmd_t *mcp = &mc;
  1359. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1054,
  1360. "Entered %s.\n", __func__);
  1361. mcp->mb[0] = MBC_GET_FIRMWARE_STATE;
  1362. mcp->out_mb = MBX_0;
  1363. if (IS_FWI2_CAPABLE(vha->hw))
  1364. mcp->in_mb = MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  1365. else
  1366. mcp->in_mb = MBX_1|MBX_0;
  1367. mcp->tov = MBX_TOV_SECONDS;
  1368. mcp->flags = 0;
  1369. rval = qla2x00_mailbox_command(vha, mcp);
  1370. /* Return firmware states. */
  1371. states[0] = mcp->mb[1];
  1372. if (IS_FWI2_CAPABLE(vha->hw)) {
  1373. states[1] = mcp->mb[2];
  1374. states[2] = mcp->mb[3];
  1375. states[3] = mcp->mb[4];
  1376. states[4] = mcp->mb[5];
  1377. }
  1378. if (rval != QLA_SUCCESS) {
  1379. /*EMPTY*/
  1380. ql_dbg(ql_dbg_mbx, vha, 0x1055, "Failed=%x.\n", rval);
  1381. } else {
  1382. /*EMPTY*/
  1383. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1056,
  1384. "Done %s.\n", __func__);
  1385. }
  1386. return rval;
  1387. }
  1388. /*
  1389. * qla2x00_get_port_name
  1390. * Issue get port name mailbox command.
  1391. * Returned name is in big endian format.
  1392. *
  1393. * Input:
  1394. * ha = adapter block pointer.
  1395. * loop_id = loop ID of device.
  1396. * name = pointer for name.
  1397. * TARGET_QUEUE_LOCK must be released.
  1398. * ADAPTER_STATE_LOCK must be released.
  1399. *
  1400. * Returns:
  1401. * qla2x00 local function return status code.
  1402. *
  1403. * Context:
  1404. * Kernel context.
  1405. */
  1406. int
  1407. qla2x00_get_port_name(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t *name,
  1408. uint8_t opt)
  1409. {
  1410. int rval;
  1411. mbx_cmd_t mc;
  1412. mbx_cmd_t *mcp = &mc;
  1413. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1057,
  1414. "Entered %s.\n", __func__);
  1415. mcp->mb[0] = MBC_GET_PORT_NAME;
  1416. mcp->mb[9] = vha->vp_idx;
  1417. mcp->out_mb = MBX_9|MBX_1|MBX_0;
  1418. if (HAS_EXTENDED_IDS(vha->hw)) {
  1419. mcp->mb[1] = loop_id;
  1420. mcp->mb[10] = opt;
  1421. mcp->out_mb |= MBX_10;
  1422. } else {
  1423. mcp->mb[1] = loop_id << 8 | opt;
  1424. }
  1425. mcp->in_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
  1426. mcp->tov = MBX_TOV_SECONDS;
  1427. mcp->flags = 0;
  1428. rval = qla2x00_mailbox_command(vha, mcp);
  1429. if (rval != QLA_SUCCESS) {
  1430. /*EMPTY*/
  1431. ql_dbg(ql_dbg_mbx, vha, 0x1058, "Failed=%x.\n", rval);
  1432. } else {
  1433. if (name != NULL) {
  1434. /* This function returns name in big endian. */
  1435. name[0] = MSB(mcp->mb[2]);
  1436. name[1] = LSB(mcp->mb[2]);
  1437. name[2] = MSB(mcp->mb[3]);
  1438. name[3] = LSB(mcp->mb[3]);
  1439. name[4] = MSB(mcp->mb[6]);
  1440. name[5] = LSB(mcp->mb[6]);
  1441. name[6] = MSB(mcp->mb[7]);
  1442. name[7] = LSB(mcp->mb[7]);
  1443. }
  1444. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1059,
  1445. "Done %s.\n", __func__);
  1446. }
  1447. return rval;
  1448. }
  1449. /*
  1450. * qla2x00_lip_reset
  1451. * Issue LIP reset mailbox command.
  1452. *
  1453. * Input:
  1454. * ha = adapter block pointer.
  1455. * TARGET_QUEUE_LOCK must be released.
  1456. * ADAPTER_STATE_LOCK must be released.
  1457. *
  1458. * Returns:
  1459. * qla2x00 local function return status code.
  1460. *
  1461. * Context:
  1462. * Kernel context.
  1463. */
  1464. int
  1465. qla2x00_lip_reset(scsi_qla_host_t *vha)
  1466. {
  1467. int rval;
  1468. mbx_cmd_t mc;
  1469. mbx_cmd_t *mcp = &mc;
  1470. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105a,
  1471. "Entered %s.\n", __func__);
  1472. if (IS_CNA_CAPABLE(vha->hw)) {
  1473. /* Logout across all FCFs. */
  1474. mcp->mb[0] = MBC_LIP_FULL_LOGIN;
  1475. mcp->mb[1] = BIT_1;
  1476. mcp->mb[2] = 0;
  1477. mcp->out_mb = MBX_2|MBX_1|MBX_0;
  1478. } else if (IS_FWI2_CAPABLE(vha->hw)) {
  1479. mcp->mb[0] = MBC_LIP_FULL_LOGIN;
  1480. mcp->mb[1] = BIT_6;
  1481. mcp->mb[2] = 0;
  1482. mcp->mb[3] = vha->hw->loop_reset_delay;
  1483. mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
  1484. } else {
  1485. mcp->mb[0] = MBC_LIP_RESET;
  1486. mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
  1487. if (HAS_EXTENDED_IDS(vha->hw)) {
  1488. mcp->mb[1] = 0x00ff;
  1489. mcp->mb[10] = 0;
  1490. mcp->out_mb |= MBX_10;
  1491. } else {
  1492. mcp->mb[1] = 0xff00;
  1493. }
  1494. mcp->mb[2] = vha->hw->loop_reset_delay;
  1495. mcp->mb[3] = 0;
  1496. }
  1497. mcp->in_mb = MBX_0;
  1498. mcp->tov = MBX_TOV_SECONDS;
  1499. mcp->flags = 0;
  1500. rval = qla2x00_mailbox_command(vha, mcp);
  1501. if (rval != QLA_SUCCESS) {
  1502. /*EMPTY*/
  1503. ql_dbg(ql_dbg_mbx, vha, 0x105b, "Failed=%x.\n", rval);
  1504. } else {
  1505. /*EMPTY*/
  1506. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105c,
  1507. "Done %s.\n", __func__);
  1508. }
  1509. return rval;
  1510. }
  1511. /*
  1512. * qla2x00_send_sns
  1513. * Send SNS command.
  1514. *
  1515. * Input:
  1516. * ha = adapter block pointer.
  1517. * sns = pointer for command.
  1518. * cmd_size = command size.
  1519. * buf_size = response/command size.
  1520. * TARGET_QUEUE_LOCK must be released.
  1521. * ADAPTER_STATE_LOCK must be released.
  1522. *
  1523. * Returns:
  1524. * qla2x00 local function return status code.
  1525. *
  1526. * Context:
  1527. * Kernel context.
  1528. */
  1529. int
  1530. qla2x00_send_sns(scsi_qla_host_t *vha, dma_addr_t sns_phys_address,
  1531. uint16_t cmd_size, size_t buf_size)
  1532. {
  1533. int rval;
  1534. mbx_cmd_t mc;
  1535. mbx_cmd_t *mcp = &mc;
  1536. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105d,
  1537. "Entered %s.\n", __func__);
  1538. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105e,
  1539. "Retry cnt=%d ratov=%d total tov=%d.\n",
  1540. vha->hw->retry_count, vha->hw->login_timeout, mcp->tov);
  1541. mcp->mb[0] = MBC_SEND_SNS_COMMAND;
  1542. mcp->mb[1] = cmd_size;
  1543. mcp->mb[2] = MSW(sns_phys_address);
  1544. mcp->mb[3] = LSW(sns_phys_address);
  1545. mcp->mb[6] = MSW(MSD(sns_phys_address));
  1546. mcp->mb[7] = LSW(MSD(sns_phys_address));
  1547. mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
  1548. mcp->in_mb = MBX_0|MBX_1;
  1549. mcp->buf_size = buf_size;
  1550. mcp->flags = MBX_DMA_OUT|MBX_DMA_IN;
  1551. mcp->tov = (vha->hw->login_timeout * 2) + (vha->hw->login_timeout / 2);
  1552. rval = qla2x00_mailbox_command(vha, mcp);
  1553. if (rval != QLA_SUCCESS) {
  1554. /*EMPTY*/
  1555. ql_dbg(ql_dbg_mbx, vha, 0x105f,
  1556. "Failed=%x mb[0]=%x mb[1]=%x.\n",
  1557. rval, mcp->mb[0], mcp->mb[1]);
  1558. } else {
  1559. /*EMPTY*/
  1560. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1060,
  1561. "Done %s.\n", __func__);
  1562. }
  1563. return rval;
  1564. }
  1565. int
  1566. qla24xx_login_fabric(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
  1567. uint8_t area, uint8_t al_pa, uint16_t *mb, uint8_t opt)
  1568. {
  1569. int rval;
  1570. struct logio_entry_24xx *lg;
  1571. dma_addr_t lg_dma;
  1572. uint32_t iop[2];
  1573. struct qla_hw_data *ha = vha->hw;
  1574. struct req_que *req;
  1575. struct rsp_que *rsp;
  1576. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1061,
  1577. "Entered %s.\n", __func__);
  1578. if (ha->flags.cpu_affinity_enabled)
  1579. req = ha->req_q_map[0];
  1580. else
  1581. req = vha->req;
  1582. rsp = req->rsp;
  1583. lg = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &lg_dma);
  1584. if (lg == NULL) {
  1585. ql_log(ql_log_warn, vha, 0x1062,
  1586. "Failed to allocate login IOCB.\n");
  1587. return QLA_MEMORY_ALLOC_FAILED;
  1588. }
  1589. memset(lg, 0, sizeof(struct logio_entry_24xx));
  1590. lg->entry_type = LOGINOUT_PORT_IOCB_TYPE;
  1591. lg->entry_count = 1;
  1592. lg->handle = MAKE_HANDLE(req->id, lg->handle);
  1593. lg->nport_handle = cpu_to_le16(loop_id);
  1594. lg->control_flags = __constant_cpu_to_le16(LCF_COMMAND_PLOGI);
  1595. if (opt & BIT_0)
  1596. lg->control_flags |= __constant_cpu_to_le16(LCF_COND_PLOGI);
  1597. if (opt & BIT_1)
  1598. lg->control_flags |= __constant_cpu_to_le16(LCF_SKIP_PRLI);
  1599. lg->port_id[0] = al_pa;
  1600. lg->port_id[1] = area;
  1601. lg->port_id[2] = domain;
  1602. lg->vp_index = vha->vp_idx;
  1603. rval = qla2x00_issue_iocb_timeout(vha, lg, lg_dma, 0,
  1604. (ha->r_a_tov / 10 * 2) + 2);
  1605. if (rval != QLA_SUCCESS) {
  1606. ql_dbg(ql_dbg_mbx, vha, 0x1063,
  1607. "Failed to issue login IOCB (%x).\n", rval);
  1608. } else if (lg->entry_status != 0) {
  1609. ql_dbg(ql_dbg_mbx, vha, 0x1064,
  1610. "Failed to complete IOCB -- error status (%x).\n",
  1611. lg->entry_status);
  1612. rval = QLA_FUNCTION_FAILED;
  1613. } else if (lg->comp_status != __constant_cpu_to_le16(CS_COMPLETE)) {
  1614. iop[0] = le32_to_cpu(lg->io_parameter[0]);
  1615. iop[1] = le32_to_cpu(lg->io_parameter[1]);
  1616. ql_dbg(ql_dbg_mbx, vha, 0x1065,
  1617. "Failed to complete IOCB -- completion status (%x) "
  1618. "ioparam=%x/%x.\n", le16_to_cpu(lg->comp_status),
  1619. iop[0], iop[1]);
  1620. switch (iop[0]) {
  1621. case LSC_SCODE_PORTID_USED:
  1622. mb[0] = MBS_PORT_ID_USED;
  1623. mb[1] = LSW(iop[1]);
  1624. break;
  1625. case LSC_SCODE_NPORT_USED:
  1626. mb[0] = MBS_LOOP_ID_USED;
  1627. break;
  1628. case LSC_SCODE_NOLINK:
  1629. case LSC_SCODE_NOIOCB:
  1630. case LSC_SCODE_NOXCB:
  1631. case LSC_SCODE_CMD_FAILED:
  1632. case LSC_SCODE_NOFABRIC:
  1633. case LSC_SCODE_FW_NOT_READY:
  1634. case LSC_SCODE_NOT_LOGGED_IN:
  1635. case LSC_SCODE_NOPCB:
  1636. case LSC_SCODE_ELS_REJECT:
  1637. case LSC_SCODE_CMD_PARAM_ERR:
  1638. case LSC_SCODE_NONPORT:
  1639. case LSC_SCODE_LOGGED_IN:
  1640. case LSC_SCODE_NOFLOGI_ACC:
  1641. default:
  1642. mb[0] = MBS_COMMAND_ERROR;
  1643. break;
  1644. }
  1645. } else {
  1646. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1066,
  1647. "Done %s.\n", __func__);
  1648. iop[0] = le32_to_cpu(lg->io_parameter[0]);
  1649. mb[0] = MBS_COMMAND_COMPLETE;
  1650. mb[1] = 0;
  1651. if (iop[0] & BIT_4) {
  1652. if (iop[0] & BIT_8)
  1653. mb[1] |= BIT_1;
  1654. } else
  1655. mb[1] = BIT_0;
  1656. /* Passback COS information. */
  1657. mb[10] = 0;
  1658. if (lg->io_parameter[7] || lg->io_parameter[8])
  1659. mb[10] |= BIT_0; /* Class 2. */
  1660. if (lg->io_parameter[9] || lg->io_parameter[10])
  1661. mb[10] |= BIT_1; /* Class 3. */
  1662. if (lg->io_parameter[0] & __constant_cpu_to_le32(BIT_7))
  1663. mb[10] |= BIT_7; /* Confirmed Completion
  1664. * Allowed
  1665. */
  1666. }
  1667. dma_pool_free(ha->s_dma_pool, lg, lg_dma);
  1668. return rval;
  1669. }
  1670. /*
  1671. * qla2x00_login_fabric
  1672. * Issue login fabric port mailbox command.
  1673. *
  1674. * Input:
  1675. * ha = adapter block pointer.
  1676. * loop_id = device loop ID.
  1677. * domain = device domain.
  1678. * area = device area.
  1679. * al_pa = device AL_PA.
  1680. * status = pointer for return status.
  1681. * opt = command options.
  1682. * TARGET_QUEUE_LOCK must be released.
  1683. * ADAPTER_STATE_LOCK must be released.
  1684. *
  1685. * Returns:
  1686. * qla2x00 local function return status code.
  1687. *
  1688. * Context:
  1689. * Kernel context.
  1690. */
  1691. int
  1692. qla2x00_login_fabric(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
  1693. uint8_t area, uint8_t al_pa, uint16_t *mb, uint8_t opt)
  1694. {
  1695. int rval;
  1696. mbx_cmd_t mc;
  1697. mbx_cmd_t *mcp = &mc;
  1698. struct qla_hw_data *ha = vha->hw;
  1699. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1067,
  1700. "Entered %s.\n", __func__);
  1701. mcp->mb[0] = MBC_LOGIN_FABRIC_PORT;
  1702. mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
  1703. if (HAS_EXTENDED_IDS(ha)) {
  1704. mcp->mb[1] = loop_id;
  1705. mcp->mb[10] = opt;
  1706. mcp->out_mb |= MBX_10;
  1707. } else {
  1708. mcp->mb[1] = (loop_id << 8) | opt;
  1709. }
  1710. mcp->mb[2] = domain;
  1711. mcp->mb[3] = area << 8 | al_pa;
  1712. mcp->in_mb = MBX_7|MBX_6|MBX_2|MBX_1|MBX_0;
  1713. mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
  1714. mcp->flags = 0;
  1715. rval = qla2x00_mailbox_command(vha, mcp);
  1716. /* Return mailbox statuses. */
  1717. if (mb != NULL) {
  1718. mb[0] = mcp->mb[0];
  1719. mb[1] = mcp->mb[1];
  1720. mb[2] = mcp->mb[2];
  1721. mb[6] = mcp->mb[6];
  1722. mb[7] = mcp->mb[7];
  1723. /* COS retrieved from Get-Port-Database mailbox command. */
  1724. mb[10] = 0;
  1725. }
  1726. if (rval != QLA_SUCCESS) {
  1727. /* RLU tmp code: need to change main mailbox_command function to
  1728. * return ok even when the mailbox completion value is not
  1729. * SUCCESS. The caller needs to be responsible to interpret
  1730. * the return values of this mailbox command if we're not
  1731. * to change too much of the existing code.
  1732. */
  1733. if (mcp->mb[0] == 0x4001 || mcp->mb[0] == 0x4002 ||
  1734. mcp->mb[0] == 0x4003 || mcp->mb[0] == 0x4005 ||
  1735. mcp->mb[0] == 0x4006)
  1736. rval = QLA_SUCCESS;
  1737. /*EMPTY*/
  1738. ql_dbg(ql_dbg_mbx, vha, 0x1068,
  1739. "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
  1740. rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
  1741. } else {
  1742. /*EMPTY*/
  1743. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1069,
  1744. "Done %s.\n", __func__);
  1745. }
  1746. return rval;
  1747. }
  1748. /*
  1749. * qla2x00_login_local_device
  1750. * Issue login loop port mailbox command.
  1751. *
  1752. * Input:
  1753. * ha = adapter block pointer.
  1754. * loop_id = device loop ID.
  1755. * opt = command options.
  1756. *
  1757. * Returns:
  1758. * Return status code.
  1759. *
  1760. * Context:
  1761. * Kernel context.
  1762. *
  1763. */
  1764. int
  1765. qla2x00_login_local_device(scsi_qla_host_t *vha, fc_port_t *fcport,
  1766. uint16_t *mb_ret, uint8_t opt)
  1767. {
  1768. int rval;
  1769. mbx_cmd_t mc;
  1770. mbx_cmd_t *mcp = &mc;
  1771. struct qla_hw_data *ha = vha->hw;
  1772. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x106a,
  1773. "Entered %s.\n", __func__);
  1774. if (IS_FWI2_CAPABLE(ha))
  1775. return qla24xx_login_fabric(vha, fcport->loop_id,
  1776. fcport->d_id.b.domain, fcport->d_id.b.area,
  1777. fcport->d_id.b.al_pa, mb_ret, opt);
  1778. mcp->mb[0] = MBC_LOGIN_LOOP_PORT;
  1779. if (HAS_EXTENDED_IDS(ha))
  1780. mcp->mb[1] = fcport->loop_id;
  1781. else
  1782. mcp->mb[1] = fcport->loop_id << 8;
  1783. mcp->mb[2] = opt;
  1784. mcp->out_mb = MBX_2|MBX_1|MBX_0;
  1785. mcp->in_mb = MBX_7|MBX_6|MBX_1|MBX_0;
  1786. mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
  1787. mcp->flags = 0;
  1788. rval = qla2x00_mailbox_command(vha, mcp);
  1789. /* Return mailbox statuses. */
  1790. if (mb_ret != NULL) {
  1791. mb_ret[0] = mcp->mb[0];
  1792. mb_ret[1] = mcp->mb[1];
  1793. mb_ret[6] = mcp->mb[6];
  1794. mb_ret[7] = mcp->mb[7];
  1795. }
  1796. if (rval != QLA_SUCCESS) {
  1797. /* AV tmp code: need to change main mailbox_command function to
  1798. * return ok even when the mailbox completion value is not
  1799. * SUCCESS. The caller needs to be responsible to interpret
  1800. * the return values of this mailbox command if we're not
  1801. * to change too much of the existing code.
  1802. */
  1803. if (mcp->mb[0] == 0x4005 || mcp->mb[0] == 0x4006)
  1804. rval = QLA_SUCCESS;
  1805. ql_dbg(ql_dbg_mbx, vha, 0x106b,
  1806. "Failed=%x mb[0]=%x mb[1]=%x mb[6]=%x mb[7]=%x.\n",
  1807. rval, mcp->mb[0], mcp->mb[1], mcp->mb[6], mcp->mb[7]);
  1808. } else {
  1809. /*EMPTY*/
  1810. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x106c,
  1811. "Done %s.\n", __func__);
  1812. }
  1813. return (rval);
  1814. }
  1815. int
  1816. qla24xx_fabric_logout(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
  1817. uint8_t area, uint8_t al_pa)
  1818. {
  1819. int rval;
  1820. struct logio_entry_24xx *lg;
  1821. dma_addr_t lg_dma;
  1822. struct qla_hw_data *ha = vha->hw;
  1823. struct req_que *req;
  1824. struct rsp_que *rsp;
  1825. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x106d,
  1826. "Entered %s.\n", __func__);
  1827. lg = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &lg_dma);
  1828. if (lg == NULL) {
  1829. ql_log(ql_log_warn, vha, 0x106e,
  1830. "Failed to allocate logout IOCB.\n");
  1831. return QLA_MEMORY_ALLOC_FAILED;
  1832. }
  1833. memset(lg, 0, sizeof(struct logio_entry_24xx));
  1834. if (ql2xmaxqueues > 1)
  1835. req = ha->req_q_map[0];
  1836. else
  1837. req = vha->req;
  1838. rsp = req->rsp;
  1839. lg->entry_type = LOGINOUT_PORT_IOCB_TYPE;
  1840. lg->entry_count = 1;
  1841. lg->handle = MAKE_HANDLE(req->id, lg->handle);
  1842. lg->nport_handle = cpu_to_le16(loop_id);
  1843. lg->control_flags =
  1844. __constant_cpu_to_le16(LCF_COMMAND_LOGO|LCF_IMPL_LOGO|
  1845. LCF_FREE_NPORT);
  1846. lg->port_id[0] = al_pa;
  1847. lg->port_id[1] = area;
  1848. lg->port_id[2] = domain;
  1849. lg->vp_index = vha->vp_idx;
  1850. rval = qla2x00_issue_iocb_timeout(vha, lg, lg_dma, 0,
  1851. (ha->r_a_tov / 10 * 2) + 2);
  1852. if (rval != QLA_SUCCESS) {
  1853. ql_dbg(ql_dbg_mbx, vha, 0x106f,
  1854. "Failed to issue logout IOCB (%x).\n", rval);
  1855. } else if (lg->entry_status != 0) {
  1856. ql_dbg(ql_dbg_mbx, vha, 0x1070,
  1857. "Failed to complete IOCB -- error status (%x).\n",
  1858. lg->entry_status);
  1859. rval = QLA_FUNCTION_FAILED;
  1860. } else if (lg->comp_status != __constant_cpu_to_le16(CS_COMPLETE)) {
  1861. ql_dbg(ql_dbg_mbx, vha, 0x1071,
  1862. "Failed to complete IOCB -- completion status (%x) "
  1863. "ioparam=%x/%x.\n", le16_to_cpu(lg->comp_status),
  1864. le32_to_cpu(lg->io_parameter[0]),
  1865. le32_to_cpu(lg->io_parameter[1]));
  1866. } else {
  1867. /*EMPTY*/
  1868. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1072,
  1869. "Done %s.\n", __func__);
  1870. }
  1871. dma_pool_free(ha->s_dma_pool, lg, lg_dma);
  1872. return rval;
  1873. }
  1874. /*
  1875. * qla2x00_fabric_logout
  1876. * Issue logout fabric port mailbox command.
  1877. *
  1878. * Input:
  1879. * ha = adapter block pointer.
  1880. * loop_id = device loop ID.
  1881. * TARGET_QUEUE_LOCK must be released.
  1882. * ADAPTER_STATE_LOCK must be released.
  1883. *
  1884. * Returns:
  1885. * qla2x00 local function return status code.
  1886. *
  1887. * Context:
  1888. * Kernel context.
  1889. */
  1890. int
  1891. qla2x00_fabric_logout(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
  1892. uint8_t area, uint8_t al_pa)
  1893. {
  1894. int rval;
  1895. mbx_cmd_t mc;
  1896. mbx_cmd_t *mcp = &mc;
  1897. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1073,
  1898. "Entered %s.\n", __func__);
  1899. mcp->mb[0] = MBC_LOGOUT_FABRIC_PORT;
  1900. mcp->out_mb = MBX_1|MBX_0;
  1901. if (HAS_EXTENDED_IDS(vha->hw)) {
  1902. mcp->mb[1] = loop_id;
  1903. mcp->mb[10] = 0;
  1904. mcp->out_mb |= MBX_10;
  1905. } else {
  1906. mcp->mb[1] = loop_id << 8;
  1907. }
  1908. mcp->in_mb = MBX_1|MBX_0;
  1909. mcp->tov = MBX_TOV_SECONDS;
  1910. mcp->flags = 0;
  1911. rval = qla2x00_mailbox_command(vha, mcp);
  1912. if (rval != QLA_SUCCESS) {
  1913. /*EMPTY*/
  1914. ql_dbg(ql_dbg_mbx, vha, 0x1074,
  1915. "Failed=%x mb[1]=%x.\n", rval, mcp->mb[1]);
  1916. } else {
  1917. /*EMPTY*/
  1918. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1075,
  1919. "Done %s.\n", __func__);
  1920. }
  1921. return rval;
  1922. }
  1923. /*
  1924. * qla2x00_full_login_lip
  1925. * Issue full login LIP mailbox command.
  1926. *
  1927. * Input:
  1928. * ha = adapter block pointer.
  1929. * TARGET_QUEUE_LOCK must be released.
  1930. * ADAPTER_STATE_LOCK must be released.
  1931. *
  1932. * Returns:
  1933. * qla2x00 local function return status code.
  1934. *
  1935. * Context:
  1936. * Kernel context.
  1937. */
  1938. int
  1939. qla2x00_full_login_lip(scsi_qla_host_t *vha)
  1940. {
  1941. int rval;
  1942. mbx_cmd_t mc;
  1943. mbx_cmd_t *mcp = &mc;
  1944. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1076,
  1945. "Entered %s.\n", __func__);
  1946. mcp->mb[0] = MBC_LIP_FULL_LOGIN;
  1947. mcp->mb[1] = IS_FWI2_CAPABLE(vha->hw) ? BIT_3 : 0;
  1948. mcp->mb[2] = 0;
  1949. mcp->mb[3] = 0;
  1950. mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
  1951. mcp->in_mb = MBX_0;
  1952. mcp->tov = MBX_TOV_SECONDS;
  1953. mcp->flags = 0;
  1954. rval = qla2x00_mailbox_command(vha, mcp);
  1955. if (rval != QLA_SUCCESS) {
  1956. /*EMPTY*/
  1957. ql_dbg(ql_dbg_mbx, vha, 0x1077, "Failed=%x.\n", rval);
  1958. } else {
  1959. /*EMPTY*/
  1960. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1078,
  1961. "Done %s.\n", __func__);
  1962. }
  1963. return rval;
  1964. }
  1965. /*
  1966. * qla2x00_get_id_list
  1967. *
  1968. * Input:
  1969. * ha = adapter block pointer.
  1970. *
  1971. * Returns:
  1972. * qla2x00 local function return status code.
  1973. *
  1974. * Context:
  1975. * Kernel context.
  1976. */
  1977. int
  1978. qla2x00_get_id_list(scsi_qla_host_t *vha, void *id_list, dma_addr_t id_list_dma,
  1979. uint16_t *entries)
  1980. {
  1981. int rval;
  1982. mbx_cmd_t mc;
  1983. mbx_cmd_t *mcp = &mc;
  1984. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1079,
  1985. "Entered %s.\n", __func__);
  1986. if (id_list == NULL)
  1987. return QLA_FUNCTION_FAILED;
  1988. mcp->mb[0] = MBC_GET_ID_LIST;
  1989. mcp->out_mb = MBX_0;
  1990. if (IS_FWI2_CAPABLE(vha->hw)) {
  1991. mcp->mb[2] = MSW(id_list_dma);
  1992. mcp->mb[3] = LSW(id_list_dma);
  1993. mcp->mb[6] = MSW(MSD(id_list_dma));
  1994. mcp->mb[7] = LSW(MSD(id_list_dma));
  1995. mcp->mb[8] = 0;
  1996. mcp->mb[9] = vha->vp_idx;
  1997. mcp->out_mb |= MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2;
  1998. } else {
  1999. mcp->mb[1] = MSW(id_list_dma);
  2000. mcp->mb[2] = LSW(id_list_dma);
  2001. mcp->mb[3] = MSW(MSD(id_list_dma));
  2002. mcp->mb[6] = LSW(MSD(id_list_dma));
  2003. mcp->out_mb |= MBX_6|MBX_3|MBX_2|MBX_1;
  2004. }
  2005. mcp->in_mb = MBX_1|MBX_0;
  2006. mcp->tov = MBX_TOV_SECONDS;
  2007. mcp->flags = 0;
  2008. rval = qla2x00_mailbox_command(vha, mcp);
  2009. if (rval != QLA_SUCCESS) {
  2010. /*EMPTY*/
  2011. ql_dbg(ql_dbg_mbx, vha, 0x107a, "Failed=%x.\n", rval);
  2012. } else {
  2013. *entries = mcp->mb[1];
  2014. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107b,
  2015. "Done %s.\n", __func__);
  2016. }
  2017. return rval;
  2018. }
  2019. /*
  2020. * qla2x00_get_resource_cnts
  2021. * Get current firmware resource counts.
  2022. *
  2023. * Input:
  2024. * ha = adapter block pointer.
  2025. *
  2026. * Returns:
  2027. * qla2x00 local function return status code.
  2028. *
  2029. * Context:
  2030. * Kernel context.
  2031. */
  2032. int
  2033. qla2x00_get_resource_cnts(scsi_qla_host_t *vha, uint16_t *cur_xchg_cnt,
  2034. uint16_t *orig_xchg_cnt, uint16_t *cur_iocb_cnt,
  2035. uint16_t *orig_iocb_cnt, uint16_t *max_npiv_vports, uint16_t *max_fcfs)
  2036. {
  2037. int rval;
  2038. mbx_cmd_t mc;
  2039. mbx_cmd_t *mcp = &mc;
  2040. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107c,
  2041. "Entered %s.\n", __func__);
  2042. mcp->mb[0] = MBC_GET_RESOURCE_COUNTS;
  2043. mcp->out_mb = MBX_0;
  2044. mcp->in_mb = MBX_11|MBX_10|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
  2045. if (IS_QLA81XX(vha->hw) || IS_QLA83XX(vha->hw))
  2046. mcp->in_mb |= MBX_12;
  2047. mcp->tov = MBX_TOV_SECONDS;
  2048. mcp->flags = 0;
  2049. rval = qla2x00_mailbox_command(vha, mcp);
  2050. if (rval != QLA_SUCCESS) {
  2051. /*EMPTY*/
  2052. ql_dbg(ql_dbg_mbx, vha, 0x107d,
  2053. "Failed mb[0]=%x.\n", mcp->mb[0]);
  2054. } else {
  2055. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107e,
  2056. "Done %s mb1=%x mb2=%x mb3=%x mb6=%x mb7=%x mb10=%x "
  2057. "mb11=%x mb12=%x.\n", __func__, mcp->mb[1], mcp->mb[2],
  2058. mcp->mb[3], mcp->mb[6], mcp->mb[7], mcp->mb[10],
  2059. mcp->mb[11], mcp->mb[12]);
  2060. if (cur_xchg_cnt)
  2061. *cur_xchg_cnt = mcp->mb[3];
  2062. if (orig_xchg_cnt)
  2063. *orig_xchg_cnt = mcp->mb[6];
  2064. if (cur_iocb_cnt)
  2065. *cur_iocb_cnt = mcp->mb[7];
  2066. if (orig_iocb_cnt)
  2067. *orig_iocb_cnt = mcp->mb[10];
  2068. if (vha->hw->flags.npiv_supported && max_npiv_vports)
  2069. *max_npiv_vports = mcp->mb[11];
  2070. if ((IS_QLA81XX(vha->hw) || IS_QLA83XX(vha->hw)) && max_fcfs)
  2071. *max_fcfs = mcp->mb[12];
  2072. }
  2073. return (rval);
  2074. }
  2075. /*
  2076. * qla2x00_get_fcal_position_map
  2077. * Get FCAL (LILP) position map using mailbox command
  2078. *
  2079. * Input:
  2080. * ha = adapter state pointer.
  2081. * pos_map = buffer pointer (can be NULL).
  2082. *
  2083. * Returns:
  2084. * qla2x00 local function return status code.
  2085. *
  2086. * Context:
  2087. * Kernel context.
  2088. */
  2089. int
  2090. qla2x00_get_fcal_position_map(scsi_qla_host_t *vha, char *pos_map)
  2091. {
  2092. int rval;
  2093. mbx_cmd_t mc;
  2094. mbx_cmd_t *mcp = &mc;
  2095. char *pmap;
  2096. dma_addr_t pmap_dma;
  2097. struct qla_hw_data *ha = vha->hw;
  2098. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107f,
  2099. "Entered %s.\n", __func__);
  2100. pmap = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &pmap_dma);
  2101. if (pmap == NULL) {
  2102. ql_log(ql_log_warn, vha, 0x1080,
  2103. "Memory alloc failed.\n");
  2104. return QLA_MEMORY_ALLOC_FAILED;
  2105. }
  2106. memset(pmap, 0, FCAL_MAP_SIZE);
  2107. mcp->mb[0] = MBC_GET_FC_AL_POSITION_MAP;
  2108. mcp->mb[2] = MSW(pmap_dma);
  2109. mcp->mb[3] = LSW(pmap_dma);
  2110. mcp->mb[6] = MSW(MSD(pmap_dma));
  2111. mcp->mb[7] = LSW(MSD(pmap_dma));
  2112. mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
  2113. mcp->in_mb = MBX_1|MBX_0;
  2114. mcp->buf_size = FCAL_MAP_SIZE;
  2115. mcp->flags = MBX_DMA_IN;
  2116. mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
  2117. rval = qla2x00_mailbox_command(vha, mcp);
  2118. if (rval == QLA_SUCCESS) {
  2119. ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1081,
  2120. "mb0/mb1=%x/%X FC/AL position map size (%x).\n",
  2121. mcp->mb[0], mcp->mb[1], (unsigned)pmap[0]);
  2122. ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111d,
  2123. pmap, pmap[0] + 1);
  2124. if (pos_map)
  2125. memcpy(pos_map, pmap, FCAL_MAP_SIZE);
  2126. }
  2127. dma_pool_free(ha->s_dma_pool, pmap, pmap_dma);
  2128. if (rval != QLA_SUCCESS) {
  2129. ql_dbg(ql_dbg_mbx, vha, 0x1082, "Failed=%x.\n", rval);
  2130. } else {
  2131. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1083,
  2132. "Done %s.\n", __func__);
  2133. }
  2134. return rval;
  2135. }
  2136. /*
  2137. * qla2x00_get_link_status
  2138. *
  2139. * Input:
  2140. * ha = adapter block pointer.
  2141. * loop_id = device loop ID.
  2142. * ret_buf = pointer to link status return buffer.
  2143. *
  2144. * Returns:
  2145. * 0 = success.
  2146. * BIT_0 = mem alloc error.
  2147. * BIT_1 = mailbox error.
  2148. */
  2149. int
  2150. qla2x00_get_link_status(scsi_qla_host_t *vha, uint16_t loop_id,
  2151. struct link_statistics *stats, dma_addr_t stats_dma)
  2152. {
  2153. int rval;
  2154. mbx_cmd_t mc;
  2155. mbx_cmd_t *mcp = &mc;
  2156. uint32_t *siter, *diter, dwords;
  2157. struct qla_hw_data *ha = vha->hw;
  2158. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1084,
  2159. "Entered %s.\n", __func__);
  2160. mcp->mb[0] = MBC_GET_LINK_STATUS;
  2161. mcp->mb[2] = MSW(stats_dma);
  2162. mcp->mb[3] = LSW(stats_dma);
  2163. mcp->mb[6] = MSW(MSD(stats_dma));
  2164. mcp->mb[7] = LSW(MSD(stats_dma));
  2165. mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
  2166. mcp->in_mb = MBX_0;
  2167. if (IS_FWI2_CAPABLE(ha)) {
  2168. mcp->mb[1] = loop_id;
  2169. mcp->mb[4] = 0;
  2170. mcp->mb[10] = 0;
  2171. mcp->out_mb |= MBX_10|MBX_4|MBX_1;
  2172. mcp->in_mb |= MBX_1;
  2173. } else if (HAS_EXTENDED_IDS(ha)) {
  2174. mcp->mb[1] = loop_id;
  2175. mcp->mb[10] = 0;
  2176. mcp->out_mb |= MBX_10|MBX_1;
  2177. } else {
  2178. mcp->mb[1] = loop_id << 8;
  2179. mcp->out_mb |= MBX_1;
  2180. }
  2181. mcp->tov = MBX_TOV_SECONDS;
  2182. mcp->flags = IOCTL_CMD;
  2183. rval = qla2x00_mailbox_command(vha, mcp);
  2184. if (rval == QLA_SUCCESS) {
  2185. if (mcp->mb[0] != MBS_COMMAND_COMPLETE) {
  2186. ql_dbg(ql_dbg_mbx, vha, 0x1085,
  2187. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  2188. rval = QLA_FUNCTION_FAILED;
  2189. } else {
  2190. /* Copy over data -- firmware data is LE. */
  2191. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1086,
  2192. "Done %s.\n", __func__);
  2193. dwords = offsetof(struct link_statistics, unused1) / 4;
  2194. siter = diter = &stats->link_fail_cnt;
  2195. while (dwords--)
  2196. *diter++ = le32_to_cpu(*siter++);
  2197. }
  2198. } else {
  2199. /* Failed. */
  2200. ql_dbg(ql_dbg_mbx, vha, 0x1087, "Failed=%x.\n", rval);
  2201. }
  2202. return rval;
  2203. }
  2204. int
  2205. qla24xx_get_isp_stats(scsi_qla_host_t *vha, struct link_statistics *stats,
  2206. dma_addr_t stats_dma)
  2207. {
  2208. int rval;
  2209. mbx_cmd_t mc;
  2210. mbx_cmd_t *mcp = &mc;
  2211. uint32_t *siter, *diter, dwords;
  2212. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1088,
  2213. "Entered %s.\n", __func__);
  2214. mcp->mb[0] = MBC_GET_LINK_PRIV_STATS;
  2215. mcp->mb[2] = MSW(stats_dma);
  2216. mcp->mb[3] = LSW(stats_dma);
  2217. mcp->mb[6] = MSW(MSD(stats_dma));
  2218. mcp->mb[7] = LSW(MSD(stats_dma));
  2219. mcp->mb[8] = sizeof(struct link_statistics) / 4;
  2220. mcp->mb[9] = vha->vp_idx;
  2221. mcp->mb[10] = 0;
  2222. mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
  2223. mcp->in_mb = MBX_2|MBX_1|MBX_0;
  2224. mcp->tov = MBX_TOV_SECONDS;
  2225. mcp->flags = IOCTL_CMD;
  2226. rval = qla2x00_mailbox_command(vha, mcp);
  2227. if (rval == QLA_SUCCESS) {
  2228. if (mcp->mb[0] != MBS_COMMAND_COMPLETE) {
  2229. ql_dbg(ql_dbg_mbx, vha, 0x1089,
  2230. "Failed mb[0]=%x.\n", mcp->mb[0]);
  2231. rval = QLA_FUNCTION_FAILED;
  2232. } else {
  2233. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x108a,
  2234. "Done %s.\n", __func__);
  2235. /* Copy over data -- firmware data is LE. */
  2236. dwords = sizeof(struct link_statistics) / 4;
  2237. siter = diter = &stats->link_fail_cnt;
  2238. while (dwords--)
  2239. *diter++ = le32_to_cpu(*siter++);
  2240. }
  2241. } else {
  2242. /* Failed. */
  2243. ql_dbg(ql_dbg_mbx, vha, 0x108b, "Failed=%x.\n", rval);
  2244. }
  2245. return rval;
  2246. }
  2247. int
  2248. qla24xx_abort_command(srb_t *sp)
  2249. {
  2250. int rval;
  2251. unsigned long flags = 0;
  2252. struct abort_entry_24xx *abt;
  2253. dma_addr_t abt_dma;
  2254. uint32_t handle;
  2255. fc_port_t *fcport = sp->fcport;
  2256. struct scsi_qla_host *vha = fcport->vha;
  2257. struct qla_hw_data *ha = vha->hw;
  2258. struct req_que *req = vha->req;
  2259. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x108c,
  2260. "Entered %s.\n", __func__);
  2261. spin_lock_irqsave(&ha->hardware_lock, flags);
  2262. for (handle = 1; handle < MAX_OUTSTANDING_COMMANDS; handle++) {
  2263. if (req->outstanding_cmds[handle] == sp)
  2264. break;
  2265. }
  2266. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  2267. if (handle == MAX_OUTSTANDING_COMMANDS) {
  2268. /* Command not found. */
  2269. return QLA_FUNCTION_FAILED;
  2270. }
  2271. abt = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &abt_dma);
  2272. if (abt == NULL) {
  2273. ql_log(ql_log_warn, vha, 0x108d,
  2274. "Failed to allocate abort IOCB.\n");
  2275. return QLA_MEMORY_ALLOC_FAILED;
  2276. }
  2277. memset(abt, 0, sizeof(struct abort_entry_24xx));
  2278. abt->entry_type = ABORT_IOCB_TYPE;
  2279. abt->entry_count = 1;
  2280. abt->handle = MAKE_HANDLE(req->id, abt->handle);
  2281. abt->nport_handle = cpu_to_le16(fcport->loop_id);
  2282. abt->handle_to_abort = MAKE_HANDLE(req->id, handle);
  2283. abt->port_id[0] = fcport->d_id.b.al_pa;
  2284. abt->port_id[1] = fcport->d_id.b.area;
  2285. abt->port_id[2] = fcport->d_id.b.domain;
  2286. abt->vp_index = fcport->vha->vp_idx;
  2287. abt->req_que_no = cpu_to_le16(req->id);
  2288. rval = qla2x00_issue_iocb(vha, abt, abt_dma, 0);
  2289. if (rval != QLA_SUCCESS) {
  2290. ql_dbg(ql_dbg_mbx, vha, 0x108e,
  2291. "Failed to issue IOCB (%x).\n", rval);
  2292. } else if (abt->entry_status != 0) {
  2293. ql_dbg(ql_dbg_mbx, vha, 0x108f,
  2294. "Failed to complete IOCB -- error status (%x).\n",
  2295. abt->entry_status);
  2296. rval = QLA_FUNCTION_FAILED;
  2297. } else if (abt->nport_handle != __constant_cpu_to_le16(0)) {
  2298. ql_dbg(ql_dbg_mbx, vha, 0x1090,
  2299. "Failed to complete IOCB -- completion status (%x).\n",
  2300. le16_to_cpu(abt->nport_handle));
  2301. rval = QLA_FUNCTION_FAILED;
  2302. } else {
  2303. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1091,
  2304. "Done %s.\n", __func__);
  2305. }
  2306. dma_pool_free(ha->s_dma_pool, abt, abt_dma);
  2307. return rval;
  2308. }
  2309. struct tsk_mgmt_cmd {
  2310. union {
  2311. struct tsk_mgmt_entry tsk;
  2312. struct sts_entry_24xx sts;
  2313. } p;
  2314. };
  2315. static int
  2316. __qla24xx_issue_tmf(char *name, uint32_t type, struct fc_port *fcport,
  2317. unsigned int l, int tag)
  2318. {
  2319. int rval, rval2;
  2320. struct tsk_mgmt_cmd *tsk;
  2321. struct sts_entry_24xx *sts;
  2322. dma_addr_t tsk_dma;
  2323. scsi_qla_host_t *vha;
  2324. struct qla_hw_data *ha;
  2325. struct req_que *req;
  2326. struct rsp_que *rsp;
  2327. vha = fcport->vha;
  2328. ha = vha->hw;
  2329. req = vha->req;
  2330. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1092,
  2331. "Entered %s.\n", __func__);
  2332. if (ha->flags.cpu_affinity_enabled)
  2333. rsp = ha->rsp_q_map[tag + 1];
  2334. else
  2335. rsp = req->rsp;
  2336. tsk = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &tsk_dma);
  2337. if (tsk == NULL) {
  2338. ql_log(ql_log_warn, vha, 0x1093,
  2339. "Failed to allocate task management IOCB.\n");
  2340. return QLA_MEMORY_ALLOC_FAILED;
  2341. }
  2342. memset(tsk, 0, sizeof(struct tsk_mgmt_cmd));
  2343. tsk->p.tsk.entry_type = TSK_MGMT_IOCB_TYPE;
  2344. tsk->p.tsk.entry_count = 1;
  2345. tsk->p.tsk.handle = MAKE_HANDLE(req->id, tsk->p.tsk.handle);
  2346. tsk->p.tsk.nport_handle = cpu_to_le16(fcport->loop_id);
  2347. tsk->p.tsk.timeout = cpu_to_le16(ha->r_a_tov / 10 * 2);
  2348. tsk->p.tsk.control_flags = cpu_to_le32(type);
  2349. tsk->p.tsk.port_id[0] = fcport->d_id.b.al_pa;
  2350. tsk->p.tsk.port_id[1] = fcport->d_id.b.area;
  2351. tsk->p.tsk.port_id[2] = fcport->d_id.b.domain;
  2352. tsk->p.tsk.vp_index = fcport->vha->vp_idx;
  2353. if (type == TCF_LUN_RESET) {
  2354. int_to_scsilun(l, &tsk->p.tsk.lun);
  2355. host_to_fcp_swap((uint8_t *)&tsk->p.tsk.lun,
  2356. sizeof(tsk->p.tsk.lun));
  2357. }
  2358. sts = &tsk->p.sts;
  2359. rval = qla2x00_issue_iocb(vha, tsk, tsk_dma, 0);
  2360. if (rval != QLA_SUCCESS) {
  2361. ql_dbg(ql_dbg_mbx, vha, 0x1094,
  2362. "Failed to issue %s reset IOCB (%x).\n", name, rval);
  2363. } else if (sts->entry_status != 0) {
  2364. ql_dbg(ql_dbg_mbx, vha, 0x1095,
  2365. "Failed to complete IOCB -- error status (%x).\n",
  2366. sts->entry_status);
  2367. rval = QLA_FUNCTION_FAILED;
  2368. } else if (sts->comp_status !=
  2369. __constant_cpu_to_le16(CS_COMPLETE)) {
  2370. ql_dbg(ql_dbg_mbx, vha, 0x1096,
  2371. "Failed to complete IOCB -- completion status (%x).\n",
  2372. le16_to_cpu(sts->comp_status));
  2373. rval = QLA_FUNCTION_FAILED;
  2374. } else if (le16_to_cpu(sts->scsi_status) &
  2375. SS_RESPONSE_INFO_LEN_VALID) {
  2376. if (le32_to_cpu(sts->rsp_data_len) < 4) {
  2377. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1097,
  2378. "Ignoring inconsistent data length -- not enough "
  2379. "response info (%d).\n",
  2380. le32_to_cpu(sts->rsp_data_len));
  2381. } else if (sts->data[3]) {
  2382. ql_dbg(ql_dbg_mbx, vha, 0x1098,
  2383. "Failed to complete IOCB -- response (%x).\n",
  2384. sts->data[3]);
  2385. rval = QLA_FUNCTION_FAILED;
  2386. }
  2387. }
  2388. /* Issue marker IOCB. */
  2389. rval2 = qla2x00_marker(vha, req, rsp, fcport->loop_id, l,
  2390. type == TCF_LUN_RESET ? MK_SYNC_ID_LUN: MK_SYNC_ID);
  2391. if (rval2 != QLA_SUCCESS) {
  2392. ql_dbg(ql_dbg_mbx, vha, 0x1099,
  2393. "Failed to issue marker IOCB (%x).\n", rval2);
  2394. } else {
  2395. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109a,
  2396. "Done %s.\n", __func__);
  2397. }
  2398. dma_pool_free(ha->s_dma_pool, tsk, tsk_dma);
  2399. return rval;
  2400. }
  2401. int
  2402. qla24xx_abort_target(struct fc_port *fcport, unsigned int l, int tag)
  2403. {
  2404. struct qla_hw_data *ha = fcport->vha->hw;
  2405. if ((ql2xasynctmfenable) && IS_FWI2_CAPABLE(ha))
  2406. return qla2x00_async_tm_cmd(fcport, TCF_TARGET_RESET, l, tag);
  2407. return __qla24xx_issue_tmf("Target", TCF_TARGET_RESET, fcport, l, tag);
  2408. }
  2409. int
  2410. qla24xx_lun_reset(struct fc_port *fcport, unsigned int l, int tag)
  2411. {
  2412. struct qla_hw_data *ha = fcport->vha->hw;
  2413. if ((ql2xasynctmfenable) && IS_FWI2_CAPABLE(ha))
  2414. return qla2x00_async_tm_cmd(fcport, TCF_LUN_RESET, l, tag);
  2415. return __qla24xx_issue_tmf("Lun", TCF_LUN_RESET, fcport, l, tag);
  2416. }
  2417. int
  2418. qla2x00_system_error(scsi_qla_host_t *vha)
  2419. {
  2420. int rval;
  2421. mbx_cmd_t mc;
  2422. mbx_cmd_t *mcp = &mc;
  2423. struct qla_hw_data *ha = vha->hw;
  2424. if (!IS_QLA23XX(ha) && !IS_FWI2_CAPABLE(ha))
  2425. return QLA_FUNCTION_FAILED;
  2426. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109b,
  2427. "Entered %s.\n", __func__);
  2428. mcp->mb[0] = MBC_GEN_SYSTEM_ERROR;
  2429. mcp->out_mb = MBX_0;
  2430. mcp->in_mb = MBX_0;
  2431. mcp->tov = 5;
  2432. mcp->flags = 0;
  2433. rval = qla2x00_mailbox_command(vha, mcp);
  2434. if (rval != QLA_SUCCESS) {
  2435. ql_dbg(ql_dbg_mbx, vha, 0x109c, "Failed=%x.\n", rval);
  2436. } else {
  2437. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109d,
  2438. "Done %s.\n", __func__);
  2439. }
  2440. return rval;
  2441. }
  2442. /**
  2443. * qla2x00_set_serdes_params() -
  2444. * @ha: HA context
  2445. *
  2446. * Returns
  2447. */
  2448. int
  2449. qla2x00_set_serdes_params(scsi_qla_host_t *vha, uint16_t sw_em_1g,
  2450. uint16_t sw_em_2g, uint16_t sw_em_4g)
  2451. {
  2452. int rval;
  2453. mbx_cmd_t mc;
  2454. mbx_cmd_t *mcp = &mc;
  2455. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109e,
  2456. "Entered %s.\n", __func__);
  2457. mcp->mb[0] = MBC_SERDES_PARAMS;
  2458. mcp->mb[1] = BIT_0;
  2459. mcp->mb[2] = sw_em_1g | BIT_15;
  2460. mcp->mb[3] = sw_em_2g | BIT_15;
  2461. mcp->mb[4] = sw_em_4g | BIT_15;
  2462. mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  2463. mcp->in_mb = MBX_0;
  2464. mcp->tov = MBX_TOV_SECONDS;
  2465. mcp->flags = 0;
  2466. rval = qla2x00_mailbox_command(vha, mcp);
  2467. if (rval != QLA_SUCCESS) {
  2468. /*EMPTY*/
  2469. ql_dbg(ql_dbg_mbx, vha, 0x109f,
  2470. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  2471. } else {
  2472. /*EMPTY*/
  2473. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a0,
  2474. "Done %s.\n", __func__);
  2475. }
  2476. return rval;
  2477. }
  2478. int
  2479. qla2x00_stop_firmware(scsi_qla_host_t *vha)
  2480. {
  2481. int rval;
  2482. mbx_cmd_t mc;
  2483. mbx_cmd_t *mcp = &mc;
  2484. if (!IS_FWI2_CAPABLE(vha->hw))
  2485. return QLA_FUNCTION_FAILED;
  2486. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a1,
  2487. "Entered %s.\n", __func__);
  2488. mcp->mb[0] = MBC_STOP_FIRMWARE;
  2489. mcp->mb[1] = 0;
  2490. mcp->out_mb = MBX_1|MBX_0;
  2491. mcp->in_mb = MBX_0;
  2492. mcp->tov = 5;
  2493. mcp->flags = 0;
  2494. rval = qla2x00_mailbox_command(vha, mcp);
  2495. if (rval != QLA_SUCCESS) {
  2496. ql_dbg(ql_dbg_mbx, vha, 0x10a2, "Failed=%x.\n", rval);
  2497. if (mcp->mb[0] == MBS_INVALID_COMMAND)
  2498. rval = QLA_INVALID_COMMAND;
  2499. } else {
  2500. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a3,
  2501. "Done %s.\n", __func__);
  2502. }
  2503. return rval;
  2504. }
  2505. int
  2506. qla2x00_enable_eft_trace(scsi_qla_host_t *vha, dma_addr_t eft_dma,
  2507. uint16_t buffers)
  2508. {
  2509. int rval;
  2510. mbx_cmd_t mc;
  2511. mbx_cmd_t *mcp = &mc;
  2512. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a4,
  2513. "Entered %s.\n", __func__);
  2514. if (!IS_FWI2_CAPABLE(vha->hw))
  2515. return QLA_FUNCTION_FAILED;
  2516. if (unlikely(pci_channel_offline(vha->hw->pdev)))
  2517. return QLA_FUNCTION_FAILED;
  2518. mcp->mb[0] = MBC_TRACE_CONTROL;
  2519. mcp->mb[1] = TC_EFT_ENABLE;
  2520. mcp->mb[2] = LSW(eft_dma);
  2521. mcp->mb[3] = MSW(eft_dma);
  2522. mcp->mb[4] = LSW(MSD(eft_dma));
  2523. mcp->mb[5] = MSW(MSD(eft_dma));
  2524. mcp->mb[6] = buffers;
  2525. mcp->mb[7] = TC_AEN_DISABLE;
  2526. mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  2527. mcp->in_mb = MBX_1|MBX_0;
  2528. mcp->tov = MBX_TOV_SECONDS;
  2529. mcp->flags = 0;
  2530. rval = qla2x00_mailbox_command(vha, mcp);
  2531. if (rval != QLA_SUCCESS) {
  2532. ql_dbg(ql_dbg_mbx, vha, 0x10a5,
  2533. "Failed=%x mb[0]=%x mb[1]=%x.\n",
  2534. rval, mcp->mb[0], mcp->mb[1]);
  2535. } else {
  2536. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a6,
  2537. "Done %s.\n", __func__);
  2538. }
  2539. return rval;
  2540. }
  2541. int
  2542. qla2x00_disable_eft_trace(scsi_qla_host_t *vha)
  2543. {
  2544. int rval;
  2545. mbx_cmd_t mc;
  2546. mbx_cmd_t *mcp = &mc;
  2547. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a7,
  2548. "Entered %s.\n", __func__);
  2549. if (!IS_FWI2_CAPABLE(vha->hw))
  2550. return QLA_FUNCTION_FAILED;
  2551. if (unlikely(pci_channel_offline(vha->hw->pdev)))
  2552. return QLA_FUNCTION_FAILED;
  2553. mcp->mb[0] = MBC_TRACE_CONTROL;
  2554. mcp->mb[1] = TC_EFT_DISABLE;
  2555. mcp->out_mb = MBX_1|MBX_0;
  2556. mcp->in_mb = MBX_1|MBX_0;
  2557. mcp->tov = MBX_TOV_SECONDS;
  2558. mcp->flags = 0;
  2559. rval = qla2x00_mailbox_command(vha, mcp);
  2560. if (rval != QLA_SUCCESS) {
  2561. ql_dbg(ql_dbg_mbx, vha, 0x10a8,
  2562. "Failed=%x mb[0]=%x mb[1]=%x.\n",
  2563. rval, mcp->mb[0], mcp->mb[1]);
  2564. } else {
  2565. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a9,
  2566. "Done %s.\n", __func__);
  2567. }
  2568. return rval;
  2569. }
  2570. int
  2571. qla2x00_enable_fce_trace(scsi_qla_host_t *vha, dma_addr_t fce_dma,
  2572. uint16_t buffers, uint16_t *mb, uint32_t *dwords)
  2573. {
  2574. int rval;
  2575. mbx_cmd_t mc;
  2576. mbx_cmd_t *mcp = &mc;
  2577. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10aa,
  2578. "Entered %s.\n", __func__);
  2579. if (!IS_QLA25XX(vha->hw) && !IS_QLA81XX(vha->hw) &&
  2580. !IS_QLA83XX(vha->hw))
  2581. return QLA_FUNCTION_FAILED;
  2582. if (unlikely(pci_channel_offline(vha->hw->pdev)))
  2583. return QLA_FUNCTION_FAILED;
  2584. mcp->mb[0] = MBC_TRACE_CONTROL;
  2585. mcp->mb[1] = TC_FCE_ENABLE;
  2586. mcp->mb[2] = LSW(fce_dma);
  2587. mcp->mb[3] = MSW(fce_dma);
  2588. mcp->mb[4] = LSW(MSD(fce_dma));
  2589. mcp->mb[5] = MSW(MSD(fce_dma));
  2590. mcp->mb[6] = buffers;
  2591. mcp->mb[7] = TC_AEN_DISABLE;
  2592. mcp->mb[8] = 0;
  2593. mcp->mb[9] = TC_FCE_DEFAULT_RX_SIZE;
  2594. mcp->mb[10] = TC_FCE_DEFAULT_TX_SIZE;
  2595. mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|
  2596. MBX_1|MBX_0;
  2597. mcp->in_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  2598. mcp->tov = MBX_TOV_SECONDS;
  2599. mcp->flags = 0;
  2600. rval = qla2x00_mailbox_command(vha, mcp);
  2601. if (rval != QLA_SUCCESS) {
  2602. ql_dbg(ql_dbg_mbx, vha, 0x10ab,
  2603. "Failed=%x mb[0]=%x mb[1]=%x.\n",
  2604. rval, mcp->mb[0], mcp->mb[1]);
  2605. } else {
  2606. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ac,
  2607. "Done %s.\n", __func__);
  2608. if (mb)
  2609. memcpy(mb, mcp->mb, 8 * sizeof(*mb));
  2610. if (dwords)
  2611. *dwords = buffers;
  2612. }
  2613. return rval;
  2614. }
  2615. int
  2616. qla2x00_disable_fce_trace(scsi_qla_host_t *vha, uint64_t *wr, uint64_t *rd)
  2617. {
  2618. int rval;
  2619. mbx_cmd_t mc;
  2620. mbx_cmd_t *mcp = &mc;
  2621. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ad,
  2622. "Entered %s.\n", __func__);
  2623. if (!IS_FWI2_CAPABLE(vha->hw))
  2624. return QLA_FUNCTION_FAILED;
  2625. if (unlikely(pci_channel_offline(vha->hw->pdev)))
  2626. return QLA_FUNCTION_FAILED;
  2627. mcp->mb[0] = MBC_TRACE_CONTROL;
  2628. mcp->mb[1] = TC_FCE_DISABLE;
  2629. mcp->mb[2] = TC_FCE_DISABLE_TRACE;
  2630. mcp->out_mb = MBX_2|MBX_1|MBX_0;
  2631. mcp->in_mb = MBX_9|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|
  2632. MBX_1|MBX_0;
  2633. mcp->tov = MBX_TOV_SECONDS;
  2634. mcp->flags = 0;
  2635. rval = qla2x00_mailbox_command(vha, mcp);
  2636. if (rval != QLA_SUCCESS) {
  2637. ql_dbg(ql_dbg_mbx, vha, 0x10ae,
  2638. "Failed=%x mb[0]=%x mb[1]=%x.\n",
  2639. rval, mcp->mb[0], mcp->mb[1]);
  2640. } else {
  2641. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10af,
  2642. "Done %s.\n", __func__);
  2643. if (wr)
  2644. *wr = (uint64_t) mcp->mb[5] << 48 |
  2645. (uint64_t) mcp->mb[4] << 32 |
  2646. (uint64_t) mcp->mb[3] << 16 |
  2647. (uint64_t) mcp->mb[2];
  2648. if (rd)
  2649. *rd = (uint64_t) mcp->mb[9] << 48 |
  2650. (uint64_t) mcp->mb[8] << 32 |
  2651. (uint64_t) mcp->mb[7] << 16 |
  2652. (uint64_t) mcp->mb[6];
  2653. }
  2654. return rval;
  2655. }
  2656. int
  2657. qla2x00_get_idma_speed(scsi_qla_host_t *vha, uint16_t loop_id,
  2658. uint16_t *port_speed, uint16_t *mb)
  2659. {
  2660. int rval;
  2661. mbx_cmd_t mc;
  2662. mbx_cmd_t *mcp = &mc;
  2663. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b0,
  2664. "Entered %s.\n", __func__);
  2665. if (!IS_IIDMA_CAPABLE(vha->hw))
  2666. return QLA_FUNCTION_FAILED;
  2667. mcp->mb[0] = MBC_PORT_PARAMS;
  2668. mcp->mb[1] = loop_id;
  2669. mcp->mb[2] = mcp->mb[3] = 0;
  2670. mcp->mb[9] = vha->vp_idx;
  2671. mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0;
  2672. mcp->in_mb = MBX_3|MBX_1|MBX_0;
  2673. mcp->tov = MBX_TOV_SECONDS;
  2674. mcp->flags = 0;
  2675. rval = qla2x00_mailbox_command(vha, mcp);
  2676. /* Return mailbox statuses. */
  2677. if (mb != NULL) {
  2678. mb[0] = mcp->mb[0];
  2679. mb[1] = mcp->mb[1];
  2680. mb[3] = mcp->mb[3];
  2681. }
  2682. if (rval != QLA_SUCCESS) {
  2683. ql_dbg(ql_dbg_mbx, vha, 0x10b1, "Failed=%x.\n", rval);
  2684. } else {
  2685. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b2,
  2686. "Done %s.\n", __func__);
  2687. if (port_speed)
  2688. *port_speed = mcp->mb[3];
  2689. }
  2690. return rval;
  2691. }
  2692. int
  2693. qla2x00_set_idma_speed(scsi_qla_host_t *vha, uint16_t loop_id,
  2694. uint16_t port_speed, uint16_t *mb)
  2695. {
  2696. int rval;
  2697. mbx_cmd_t mc;
  2698. mbx_cmd_t *mcp = &mc;
  2699. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b3,
  2700. "Entered %s.\n", __func__);
  2701. if (!IS_IIDMA_CAPABLE(vha->hw))
  2702. return QLA_FUNCTION_FAILED;
  2703. mcp->mb[0] = MBC_PORT_PARAMS;
  2704. mcp->mb[1] = loop_id;
  2705. mcp->mb[2] = BIT_0;
  2706. if (IS_CNA_CAPABLE(vha->hw))
  2707. mcp->mb[3] = port_speed & (BIT_5|BIT_4|BIT_3|BIT_2|BIT_1|BIT_0);
  2708. else
  2709. mcp->mb[3] = port_speed & (BIT_2|BIT_1|BIT_0);
  2710. mcp->mb[9] = vha->vp_idx;
  2711. mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0;
  2712. mcp->in_mb = MBX_3|MBX_1|MBX_0;
  2713. mcp->tov = MBX_TOV_SECONDS;
  2714. mcp->flags = 0;
  2715. rval = qla2x00_mailbox_command(vha, mcp);
  2716. /* Return mailbox statuses. */
  2717. if (mb != NULL) {
  2718. mb[0] = mcp->mb[0];
  2719. mb[1] = mcp->mb[1];
  2720. mb[3] = mcp->mb[3];
  2721. }
  2722. if (rval != QLA_SUCCESS) {
  2723. ql_dbg(ql_dbg_mbx, vha, 0x10b4,
  2724. "Failed=%x.\n", rval);
  2725. } else {
  2726. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b5,
  2727. "Done %s.\n", __func__);
  2728. }
  2729. return rval;
  2730. }
  2731. void
  2732. qla24xx_report_id_acquisition(scsi_qla_host_t *vha,
  2733. struct vp_rpt_id_entry_24xx *rptid_entry)
  2734. {
  2735. uint8_t vp_idx;
  2736. uint16_t stat = le16_to_cpu(rptid_entry->vp_idx);
  2737. struct qla_hw_data *ha = vha->hw;
  2738. scsi_qla_host_t *vp;
  2739. unsigned long flags;
  2740. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b6,
  2741. "Entered %s.\n", __func__);
  2742. if (rptid_entry->entry_status != 0)
  2743. return;
  2744. if (rptid_entry->format == 0) {
  2745. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b7,
  2746. "Format 0 : Number of VPs setup %d, number of "
  2747. "VPs acquired %d.\n",
  2748. MSB(le16_to_cpu(rptid_entry->vp_count)),
  2749. LSB(le16_to_cpu(rptid_entry->vp_count)));
  2750. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b8,
  2751. "Primary port id %02x%02x%02x.\n",
  2752. rptid_entry->port_id[2], rptid_entry->port_id[1],
  2753. rptid_entry->port_id[0]);
  2754. } else if (rptid_entry->format == 1) {
  2755. vp_idx = LSB(stat);
  2756. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b9,
  2757. "Format 1: VP[%d] enabled - status %d - with "
  2758. "port id %02x%02x%02x.\n", vp_idx, MSB(stat),
  2759. rptid_entry->port_id[2], rptid_entry->port_id[1],
  2760. rptid_entry->port_id[0]);
  2761. vp = vha;
  2762. if (vp_idx == 0 && (MSB(stat) != 1))
  2763. goto reg_needed;
  2764. if (MSB(stat) != 0) {
  2765. ql_dbg(ql_dbg_mbx, vha, 0x10ba,
  2766. "Could not acquire ID for VP[%d].\n", vp_idx);
  2767. return;
  2768. }
  2769. spin_lock_irqsave(&ha->vport_slock, flags);
  2770. list_for_each_entry(vp, &ha->vp_list, list)
  2771. if (vp_idx == vp->vp_idx)
  2772. break;
  2773. spin_unlock_irqrestore(&ha->vport_slock, flags);
  2774. if (!vp)
  2775. return;
  2776. vp->d_id.b.domain = rptid_entry->port_id[2];
  2777. vp->d_id.b.area = rptid_entry->port_id[1];
  2778. vp->d_id.b.al_pa = rptid_entry->port_id[0];
  2779. /*
  2780. * Cannot configure here as we are still sitting on the
  2781. * response queue. Handle it in dpc context.
  2782. */
  2783. set_bit(VP_IDX_ACQUIRED, &vp->vp_flags);
  2784. reg_needed:
  2785. set_bit(REGISTER_FC4_NEEDED, &vp->dpc_flags);
  2786. set_bit(REGISTER_FDMI_NEEDED, &vp->dpc_flags);
  2787. set_bit(VP_DPC_NEEDED, &vha->dpc_flags);
  2788. qla2xxx_wake_dpc(vha);
  2789. }
  2790. }
  2791. /*
  2792. * qla24xx_modify_vp_config
  2793. * Change VP configuration for vha
  2794. *
  2795. * Input:
  2796. * vha = adapter block pointer.
  2797. *
  2798. * Returns:
  2799. * qla2xxx local function return status code.
  2800. *
  2801. * Context:
  2802. * Kernel context.
  2803. */
  2804. int
  2805. qla24xx_modify_vp_config(scsi_qla_host_t *vha)
  2806. {
  2807. int rval;
  2808. struct vp_config_entry_24xx *vpmod;
  2809. dma_addr_t vpmod_dma;
  2810. struct qla_hw_data *ha = vha->hw;
  2811. struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
  2812. /* This can be called by the parent */
  2813. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10bb,
  2814. "Entered %s.\n", __func__);
  2815. vpmod = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &vpmod_dma);
  2816. if (!vpmod) {
  2817. ql_log(ql_log_warn, vha, 0x10bc,
  2818. "Failed to allocate modify VP IOCB.\n");
  2819. return QLA_MEMORY_ALLOC_FAILED;
  2820. }
  2821. memset(vpmod, 0, sizeof(struct vp_config_entry_24xx));
  2822. vpmod->entry_type = VP_CONFIG_IOCB_TYPE;
  2823. vpmod->entry_count = 1;
  2824. vpmod->command = VCT_COMMAND_MOD_ENABLE_VPS;
  2825. vpmod->vp_count = 1;
  2826. vpmod->vp_index1 = vha->vp_idx;
  2827. vpmod->options_idx1 = BIT_3|BIT_4|BIT_5;
  2828. qlt_modify_vp_config(vha, vpmod);
  2829. memcpy(vpmod->node_name_idx1, vha->node_name, WWN_SIZE);
  2830. memcpy(vpmod->port_name_idx1, vha->port_name, WWN_SIZE);
  2831. vpmod->entry_count = 1;
  2832. rval = qla2x00_issue_iocb(base_vha, vpmod, vpmod_dma, 0);
  2833. if (rval != QLA_SUCCESS) {
  2834. ql_dbg(ql_dbg_mbx, vha, 0x10bd,
  2835. "Failed to issue VP config IOCB (%x).\n", rval);
  2836. } else if (vpmod->comp_status != 0) {
  2837. ql_dbg(ql_dbg_mbx, vha, 0x10be,
  2838. "Failed to complete IOCB -- error status (%x).\n",
  2839. vpmod->comp_status);
  2840. rval = QLA_FUNCTION_FAILED;
  2841. } else if (vpmod->comp_status != __constant_cpu_to_le16(CS_COMPLETE)) {
  2842. ql_dbg(ql_dbg_mbx, vha, 0x10bf,
  2843. "Failed to complete IOCB -- completion status (%x).\n",
  2844. le16_to_cpu(vpmod->comp_status));
  2845. rval = QLA_FUNCTION_FAILED;
  2846. } else {
  2847. /* EMPTY */
  2848. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c0,
  2849. "Done %s.\n", __func__);
  2850. fc_vport_set_state(vha->fc_vport, FC_VPORT_INITIALIZING);
  2851. }
  2852. dma_pool_free(ha->s_dma_pool, vpmod, vpmod_dma);
  2853. return rval;
  2854. }
  2855. /*
  2856. * qla24xx_control_vp
  2857. * Enable a virtual port for given host
  2858. *
  2859. * Input:
  2860. * ha = adapter block pointer.
  2861. * vhba = virtual adapter (unused)
  2862. * index = index number for enabled VP
  2863. *
  2864. * Returns:
  2865. * qla2xxx local function return status code.
  2866. *
  2867. * Context:
  2868. * Kernel context.
  2869. */
  2870. int
  2871. qla24xx_control_vp(scsi_qla_host_t *vha, int cmd)
  2872. {
  2873. int rval;
  2874. int map, pos;
  2875. struct vp_ctrl_entry_24xx *vce;
  2876. dma_addr_t vce_dma;
  2877. struct qla_hw_data *ha = vha->hw;
  2878. int vp_index = vha->vp_idx;
  2879. struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
  2880. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c1,
  2881. "Entered %s enabling index %d.\n", __func__, vp_index);
  2882. if (vp_index == 0 || vp_index >= ha->max_npiv_vports)
  2883. return QLA_PARAMETER_ERROR;
  2884. vce = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &vce_dma);
  2885. if (!vce) {
  2886. ql_log(ql_log_warn, vha, 0x10c2,
  2887. "Failed to allocate VP control IOCB.\n");
  2888. return QLA_MEMORY_ALLOC_FAILED;
  2889. }
  2890. memset(vce, 0, sizeof(struct vp_ctrl_entry_24xx));
  2891. vce->entry_type = VP_CTRL_IOCB_TYPE;
  2892. vce->entry_count = 1;
  2893. vce->command = cpu_to_le16(cmd);
  2894. vce->vp_count = __constant_cpu_to_le16(1);
  2895. /* index map in firmware starts with 1; decrement index
  2896. * this is ok as we never use index 0
  2897. */
  2898. map = (vp_index - 1) / 8;
  2899. pos = (vp_index - 1) & 7;
  2900. mutex_lock(&ha->vport_lock);
  2901. vce->vp_idx_map[map] |= 1 << pos;
  2902. mutex_unlock(&ha->vport_lock);
  2903. rval = qla2x00_issue_iocb(base_vha, vce, vce_dma, 0);
  2904. if (rval != QLA_SUCCESS) {
  2905. ql_dbg(ql_dbg_mbx, vha, 0x10c3,
  2906. "Failed to issue VP control IOCB (%x).\n", rval);
  2907. } else if (vce->entry_status != 0) {
  2908. ql_dbg(ql_dbg_mbx, vha, 0x10c4,
  2909. "Failed to complete IOCB -- error status (%x).\n",
  2910. vce->entry_status);
  2911. rval = QLA_FUNCTION_FAILED;
  2912. } else if (vce->comp_status != __constant_cpu_to_le16(CS_COMPLETE)) {
  2913. ql_dbg(ql_dbg_mbx, vha, 0x10c5,
  2914. "Failed to complet IOCB -- completion status (%x).\n",
  2915. le16_to_cpu(vce->comp_status));
  2916. rval = QLA_FUNCTION_FAILED;
  2917. } else {
  2918. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c6,
  2919. "Done %s.\n", __func__);
  2920. }
  2921. dma_pool_free(ha->s_dma_pool, vce, vce_dma);
  2922. return rval;
  2923. }
  2924. /*
  2925. * qla2x00_send_change_request
  2926. * Receive or disable RSCN request from fabric controller
  2927. *
  2928. * Input:
  2929. * ha = adapter block pointer
  2930. * format = registration format:
  2931. * 0 - Reserved
  2932. * 1 - Fabric detected registration
  2933. * 2 - N_port detected registration
  2934. * 3 - Full registration
  2935. * FF - clear registration
  2936. * vp_idx = Virtual port index
  2937. *
  2938. * Returns:
  2939. * qla2x00 local function return status code.
  2940. *
  2941. * Context:
  2942. * Kernel Context
  2943. */
  2944. int
  2945. qla2x00_send_change_request(scsi_qla_host_t *vha, uint16_t format,
  2946. uint16_t vp_idx)
  2947. {
  2948. int rval;
  2949. mbx_cmd_t mc;
  2950. mbx_cmd_t *mcp = &mc;
  2951. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c7,
  2952. "Entered %s.\n", __func__);
  2953. mcp->mb[0] = MBC_SEND_CHANGE_REQUEST;
  2954. mcp->mb[1] = format;
  2955. mcp->mb[9] = vp_idx;
  2956. mcp->out_mb = MBX_9|MBX_1|MBX_0;
  2957. mcp->in_mb = MBX_0|MBX_1;
  2958. mcp->tov = MBX_TOV_SECONDS;
  2959. mcp->flags = 0;
  2960. rval = qla2x00_mailbox_command(vha, mcp);
  2961. if (rval == QLA_SUCCESS) {
  2962. if (mcp->mb[0] != MBS_COMMAND_COMPLETE) {
  2963. rval = BIT_1;
  2964. }
  2965. } else
  2966. rval = BIT_1;
  2967. return rval;
  2968. }
  2969. int
  2970. qla2x00_dump_ram(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t addr,
  2971. uint32_t size)
  2972. {
  2973. int rval;
  2974. mbx_cmd_t mc;
  2975. mbx_cmd_t *mcp = &mc;
  2976. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1009,
  2977. "Entered %s.\n", __func__);
  2978. if (MSW(addr) || IS_FWI2_CAPABLE(vha->hw)) {
  2979. mcp->mb[0] = MBC_DUMP_RISC_RAM_EXTENDED;
  2980. mcp->mb[8] = MSW(addr);
  2981. mcp->out_mb = MBX_8|MBX_0;
  2982. } else {
  2983. mcp->mb[0] = MBC_DUMP_RISC_RAM;
  2984. mcp->out_mb = MBX_0;
  2985. }
  2986. mcp->mb[1] = LSW(addr);
  2987. mcp->mb[2] = MSW(req_dma);
  2988. mcp->mb[3] = LSW(req_dma);
  2989. mcp->mb[6] = MSW(MSD(req_dma));
  2990. mcp->mb[7] = LSW(MSD(req_dma));
  2991. mcp->out_mb |= MBX_7|MBX_6|MBX_3|MBX_2|MBX_1;
  2992. if (IS_FWI2_CAPABLE(vha->hw)) {
  2993. mcp->mb[4] = MSW(size);
  2994. mcp->mb[5] = LSW(size);
  2995. mcp->out_mb |= MBX_5|MBX_4;
  2996. } else {
  2997. mcp->mb[4] = LSW(size);
  2998. mcp->out_mb |= MBX_4;
  2999. }
  3000. mcp->in_mb = MBX_0;
  3001. mcp->tov = MBX_TOV_SECONDS;
  3002. mcp->flags = 0;
  3003. rval = qla2x00_mailbox_command(vha, mcp);
  3004. if (rval != QLA_SUCCESS) {
  3005. ql_dbg(ql_dbg_mbx, vha, 0x1008,
  3006. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  3007. } else {
  3008. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1007,
  3009. "Done %s.\n", __func__);
  3010. }
  3011. return rval;
  3012. }
  3013. /* 84XX Support **************************************************************/
  3014. struct cs84xx_mgmt_cmd {
  3015. union {
  3016. struct verify_chip_entry_84xx req;
  3017. struct verify_chip_rsp_84xx rsp;
  3018. } p;
  3019. };
  3020. int
  3021. qla84xx_verify_chip(struct scsi_qla_host *vha, uint16_t *status)
  3022. {
  3023. int rval, retry;
  3024. struct cs84xx_mgmt_cmd *mn;
  3025. dma_addr_t mn_dma;
  3026. uint16_t options;
  3027. unsigned long flags;
  3028. struct qla_hw_data *ha = vha->hw;
  3029. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c8,
  3030. "Entered %s.\n", __func__);
  3031. mn = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &mn_dma);
  3032. if (mn == NULL) {
  3033. return QLA_MEMORY_ALLOC_FAILED;
  3034. }
  3035. /* Force Update? */
  3036. options = ha->cs84xx->fw_update ? VCO_FORCE_UPDATE : 0;
  3037. /* Diagnostic firmware? */
  3038. /* options |= MENLO_DIAG_FW; */
  3039. /* We update the firmware with only one data sequence. */
  3040. options |= VCO_END_OF_DATA;
  3041. do {
  3042. retry = 0;
  3043. memset(mn, 0, sizeof(*mn));
  3044. mn->p.req.entry_type = VERIFY_CHIP_IOCB_TYPE;
  3045. mn->p.req.entry_count = 1;
  3046. mn->p.req.options = cpu_to_le16(options);
  3047. ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111c,
  3048. "Dump of Verify Request.\n");
  3049. ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111e,
  3050. (uint8_t *)mn, sizeof(*mn));
  3051. rval = qla2x00_issue_iocb_timeout(vha, mn, mn_dma, 0, 120);
  3052. if (rval != QLA_SUCCESS) {
  3053. ql_dbg(ql_dbg_mbx, vha, 0x10cb,
  3054. "Failed to issue verify IOCB (%x).\n", rval);
  3055. goto verify_done;
  3056. }
  3057. ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1110,
  3058. "Dump of Verify Response.\n");
  3059. ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1118,
  3060. (uint8_t *)mn, sizeof(*mn));
  3061. status[0] = le16_to_cpu(mn->p.rsp.comp_status);
  3062. status[1] = status[0] == CS_VCS_CHIP_FAILURE ?
  3063. le16_to_cpu(mn->p.rsp.failure_code) : 0;
  3064. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ce,
  3065. "cs=%x fc=%x.\n", status[0], status[1]);
  3066. if (status[0] != CS_COMPLETE) {
  3067. rval = QLA_FUNCTION_FAILED;
  3068. if (!(options & VCO_DONT_UPDATE_FW)) {
  3069. ql_dbg(ql_dbg_mbx, vha, 0x10cf,
  3070. "Firmware update failed. Retrying "
  3071. "without update firmware.\n");
  3072. options |= VCO_DONT_UPDATE_FW;
  3073. options &= ~VCO_FORCE_UPDATE;
  3074. retry = 1;
  3075. }
  3076. } else {
  3077. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d0,
  3078. "Firmware updated to %x.\n",
  3079. le32_to_cpu(mn->p.rsp.fw_ver));
  3080. /* NOTE: we only update OP firmware. */
  3081. spin_lock_irqsave(&ha->cs84xx->access_lock, flags);
  3082. ha->cs84xx->op_fw_version =
  3083. le32_to_cpu(mn->p.rsp.fw_ver);
  3084. spin_unlock_irqrestore(&ha->cs84xx->access_lock,
  3085. flags);
  3086. }
  3087. } while (retry);
  3088. verify_done:
  3089. dma_pool_free(ha->s_dma_pool, mn, mn_dma);
  3090. if (rval != QLA_SUCCESS) {
  3091. ql_dbg(ql_dbg_mbx, vha, 0x10d1,
  3092. "Failed=%x.\n", rval);
  3093. } else {
  3094. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d2,
  3095. "Done %s.\n", __func__);
  3096. }
  3097. return rval;
  3098. }
  3099. int
  3100. qla25xx_init_req_que(struct scsi_qla_host *vha, struct req_que *req)
  3101. {
  3102. int rval;
  3103. unsigned long flags;
  3104. mbx_cmd_t mc;
  3105. mbx_cmd_t *mcp = &mc;
  3106. struct device_reg_25xxmq __iomem *reg;
  3107. struct qla_hw_data *ha = vha->hw;
  3108. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d3,
  3109. "Entered %s.\n", __func__);
  3110. mcp->mb[0] = MBC_INITIALIZE_MULTIQ;
  3111. mcp->mb[1] = req->options;
  3112. mcp->mb[2] = MSW(LSD(req->dma));
  3113. mcp->mb[3] = LSW(LSD(req->dma));
  3114. mcp->mb[6] = MSW(MSD(req->dma));
  3115. mcp->mb[7] = LSW(MSD(req->dma));
  3116. mcp->mb[5] = req->length;
  3117. if (req->rsp)
  3118. mcp->mb[10] = req->rsp->id;
  3119. mcp->mb[12] = req->qos;
  3120. mcp->mb[11] = req->vp_idx;
  3121. mcp->mb[13] = req->rid;
  3122. if (IS_QLA83XX(ha))
  3123. mcp->mb[15] = 0;
  3124. reg = (struct device_reg_25xxmq *)((void *)(ha->mqiobase) +
  3125. QLA_QUE_PAGE * req->id);
  3126. mcp->mb[4] = req->id;
  3127. /* que in ptr index */
  3128. mcp->mb[8] = 0;
  3129. /* que out ptr index */
  3130. mcp->mb[9] = 0;
  3131. mcp->out_mb = MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8|MBX_7|
  3132. MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  3133. mcp->in_mb = MBX_0;
  3134. mcp->flags = MBX_DMA_OUT;
  3135. mcp->tov = MBX_TOV_SECONDS * 2;
  3136. if (IS_QLA81XX(ha) || IS_QLA83XX(ha))
  3137. mcp->in_mb |= MBX_1;
  3138. if (IS_QLA83XX(ha)) {
  3139. mcp->out_mb |= MBX_15;
  3140. /* debug q create issue in SR-IOV */
  3141. mcp->in_mb |= MBX_9 | MBX_8 | MBX_7;
  3142. }
  3143. spin_lock_irqsave(&ha->hardware_lock, flags);
  3144. if (!(req->options & BIT_0)) {
  3145. WRT_REG_DWORD(&reg->req_q_in, 0);
  3146. if (!IS_QLA83XX(ha))
  3147. WRT_REG_DWORD(&reg->req_q_out, 0);
  3148. }
  3149. req->req_q_in = &reg->req_q_in;
  3150. req->req_q_out = &reg->req_q_out;
  3151. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  3152. rval = qla2x00_mailbox_command(vha, mcp);
  3153. if (rval != QLA_SUCCESS) {
  3154. ql_dbg(ql_dbg_mbx, vha, 0x10d4,
  3155. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  3156. } else {
  3157. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d5,
  3158. "Done %s.\n", __func__);
  3159. }
  3160. return rval;
  3161. }
  3162. int
  3163. qla25xx_init_rsp_que(struct scsi_qla_host *vha, struct rsp_que *rsp)
  3164. {
  3165. int rval;
  3166. unsigned long flags;
  3167. mbx_cmd_t mc;
  3168. mbx_cmd_t *mcp = &mc;
  3169. struct device_reg_25xxmq __iomem *reg;
  3170. struct qla_hw_data *ha = vha->hw;
  3171. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d6,
  3172. "Entered %s.\n", __func__);
  3173. mcp->mb[0] = MBC_INITIALIZE_MULTIQ;
  3174. mcp->mb[1] = rsp->options;
  3175. mcp->mb[2] = MSW(LSD(rsp->dma));
  3176. mcp->mb[3] = LSW(LSD(rsp->dma));
  3177. mcp->mb[6] = MSW(MSD(rsp->dma));
  3178. mcp->mb[7] = LSW(MSD(rsp->dma));
  3179. mcp->mb[5] = rsp->length;
  3180. mcp->mb[14] = rsp->msix->entry;
  3181. mcp->mb[13] = rsp->rid;
  3182. if (IS_QLA83XX(ha))
  3183. mcp->mb[15] = 0;
  3184. reg = (struct device_reg_25xxmq *)((void *)(ha->mqiobase) +
  3185. QLA_QUE_PAGE * rsp->id);
  3186. mcp->mb[4] = rsp->id;
  3187. /* que in ptr index */
  3188. mcp->mb[8] = 0;
  3189. /* que out ptr index */
  3190. mcp->mb[9] = 0;
  3191. mcp->out_mb = MBX_14|MBX_13|MBX_9|MBX_8|MBX_7
  3192. |MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  3193. mcp->in_mb = MBX_0;
  3194. mcp->flags = MBX_DMA_OUT;
  3195. mcp->tov = MBX_TOV_SECONDS * 2;
  3196. if (IS_QLA81XX(ha)) {
  3197. mcp->out_mb |= MBX_12|MBX_11|MBX_10;
  3198. mcp->in_mb |= MBX_1;
  3199. } else if (IS_QLA83XX(ha)) {
  3200. mcp->out_mb |= MBX_15|MBX_12|MBX_11|MBX_10;
  3201. mcp->in_mb |= MBX_1;
  3202. /* debug q create issue in SR-IOV */
  3203. mcp->in_mb |= MBX_9 | MBX_8 | MBX_7;
  3204. }
  3205. spin_lock_irqsave(&ha->hardware_lock, flags);
  3206. if (!(rsp->options & BIT_0)) {
  3207. WRT_REG_DWORD(&reg->rsp_q_out, 0);
  3208. if (!IS_QLA83XX(ha))
  3209. WRT_REG_DWORD(&reg->rsp_q_in, 0);
  3210. }
  3211. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  3212. rval = qla2x00_mailbox_command(vha, mcp);
  3213. if (rval != QLA_SUCCESS) {
  3214. ql_dbg(ql_dbg_mbx, vha, 0x10d7,
  3215. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  3216. } else {
  3217. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d8,
  3218. "Done %s.\n", __func__);
  3219. }
  3220. return rval;
  3221. }
  3222. int
  3223. qla81xx_idc_ack(scsi_qla_host_t *vha, uint16_t *mb)
  3224. {
  3225. int rval;
  3226. mbx_cmd_t mc;
  3227. mbx_cmd_t *mcp = &mc;
  3228. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d9,
  3229. "Entered %s.\n", __func__);
  3230. mcp->mb[0] = MBC_IDC_ACK;
  3231. memcpy(&mcp->mb[1], mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
  3232. mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  3233. mcp->in_mb = MBX_0;
  3234. mcp->tov = MBX_TOV_SECONDS;
  3235. mcp->flags = 0;
  3236. rval = qla2x00_mailbox_command(vha, mcp);
  3237. if (rval != QLA_SUCCESS) {
  3238. ql_dbg(ql_dbg_mbx, vha, 0x10da,
  3239. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  3240. } else {
  3241. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10db,
  3242. "Done %s.\n", __func__);
  3243. }
  3244. return rval;
  3245. }
  3246. int
  3247. qla81xx_fac_get_sector_size(scsi_qla_host_t *vha, uint32_t *sector_size)
  3248. {
  3249. int rval;
  3250. mbx_cmd_t mc;
  3251. mbx_cmd_t *mcp = &mc;
  3252. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10dc,
  3253. "Entered %s.\n", __func__);
  3254. if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw))
  3255. return QLA_FUNCTION_FAILED;
  3256. mcp->mb[0] = MBC_FLASH_ACCESS_CTRL;
  3257. mcp->mb[1] = FAC_OPT_CMD_GET_SECTOR_SIZE;
  3258. mcp->out_mb = MBX_1|MBX_0;
  3259. mcp->in_mb = MBX_1|MBX_0;
  3260. mcp->tov = MBX_TOV_SECONDS;
  3261. mcp->flags = 0;
  3262. rval = qla2x00_mailbox_command(vha, mcp);
  3263. if (rval != QLA_SUCCESS) {
  3264. ql_dbg(ql_dbg_mbx, vha, 0x10dd,
  3265. "Failed=%x mb[0]=%x mb[1]=%x.\n",
  3266. rval, mcp->mb[0], mcp->mb[1]);
  3267. } else {
  3268. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10de,
  3269. "Done %s.\n", __func__);
  3270. *sector_size = mcp->mb[1];
  3271. }
  3272. return rval;
  3273. }
  3274. int
  3275. qla81xx_fac_do_write_enable(scsi_qla_host_t *vha, int enable)
  3276. {
  3277. int rval;
  3278. mbx_cmd_t mc;
  3279. mbx_cmd_t *mcp = &mc;
  3280. if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw))
  3281. return QLA_FUNCTION_FAILED;
  3282. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10df,
  3283. "Entered %s.\n", __func__);
  3284. mcp->mb[0] = MBC_FLASH_ACCESS_CTRL;
  3285. mcp->mb[1] = enable ? FAC_OPT_CMD_WRITE_ENABLE :
  3286. FAC_OPT_CMD_WRITE_PROTECT;
  3287. mcp->out_mb = MBX_1|MBX_0;
  3288. mcp->in_mb = MBX_1|MBX_0;
  3289. mcp->tov = MBX_TOV_SECONDS;
  3290. mcp->flags = 0;
  3291. rval = qla2x00_mailbox_command(vha, mcp);
  3292. if (rval != QLA_SUCCESS) {
  3293. ql_dbg(ql_dbg_mbx, vha, 0x10e0,
  3294. "Failed=%x mb[0]=%x mb[1]=%x.\n",
  3295. rval, mcp->mb[0], mcp->mb[1]);
  3296. } else {
  3297. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e1,
  3298. "Done %s.\n", __func__);
  3299. }
  3300. return rval;
  3301. }
  3302. int
  3303. qla81xx_fac_erase_sector(scsi_qla_host_t *vha, uint32_t start, uint32_t finish)
  3304. {
  3305. int rval;
  3306. mbx_cmd_t mc;
  3307. mbx_cmd_t *mcp = &mc;
  3308. if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw))
  3309. return QLA_FUNCTION_FAILED;
  3310. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e2,
  3311. "Entered %s.\n", __func__);
  3312. mcp->mb[0] = MBC_FLASH_ACCESS_CTRL;
  3313. mcp->mb[1] = FAC_OPT_CMD_ERASE_SECTOR;
  3314. mcp->mb[2] = LSW(start);
  3315. mcp->mb[3] = MSW(start);
  3316. mcp->mb[4] = LSW(finish);
  3317. mcp->mb[5] = MSW(finish);
  3318. mcp->out_mb = MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  3319. mcp->in_mb = MBX_2|MBX_1|MBX_0;
  3320. mcp->tov = MBX_TOV_SECONDS;
  3321. mcp->flags = 0;
  3322. rval = qla2x00_mailbox_command(vha, mcp);
  3323. if (rval != QLA_SUCCESS) {
  3324. ql_dbg(ql_dbg_mbx, vha, 0x10e3,
  3325. "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
  3326. rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
  3327. } else {
  3328. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e4,
  3329. "Done %s.\n", __func__);
  3330. }
  3331. return rval;
  3332. }
  3333. int
  3334. qla81xx_restart_mpi_firmware(scsi_qla_host_t *vha)
  3335. {
  3336. int rval = 0;
  3337. mbx_cmd_t mc;
  3338. mbx_cmd_t *mcp = &mc;
  3339. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e5,
  3340. "Entered %s.\n", __func__);
  3341. mcp->mb[0] = MBC_RESTART_MPI_FW;
  3342. mcp->out_mb = MBX_0;
  3343. mcp->in_mb = MBX_0|MBX_1;
  3344. mcp->tov = MBX_TOV_SECONDS;
  3345. mcp->flags = 0;
  3346. rval = qla2x00_mailbox_command(vha, mcp);
  3347. if (rval != QLA_SUCCESS) {
  3348. ql_dbg(ql_dbg_mbx, vha, 0x10e6,
  3349. "Failed=%x mb[0]=%x mb[1]=%x.\n",
  3350. rval, mcp->mb[0], mcp->mb[1]);
  3351. } else {
  3352. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e7,
  3353. "Done %s.\n", __func__);
  3354. }
  3355. return rval;
  3356. }
  3357. int
  3358. qla2x00_read_sfp(scsi_qla_host_t *vha, dma_addr_t sfp_dma, uint8_t *sfp,
  3359. uint16_t dev, uint16_t off, uint16_t len, uint16_t opt)
  3360. {
  3361. int rval;
  3362. mbx_cmd_t mc;
  3363. mbx_cmd_t *mcp = &mc;
  3364. struct qla_hw_data *ha = vha->hw;
  3365. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e8,
  3366. "Entered %s.\n", __func__);
  3367. if (!IS_FWI2_CAPABLE(ha))
  3368. return QLA_FUNCTION_FAILED;
  3369. if (len == 1)
  3370. opt |= BIT_0;
  3371. mcp->mb[0] = MBC_READ_SFP;
  3372. mcp->mb[1] = dev;
  3373. mcp->mb[2] = MSW(sfp_dma);
  3374. mcp->mb[3] = LSW(sfp_dma);
  3375. mcp->mb[6] = MSW(MSD(sfp_dma));
  3376. mcp->mb[7] = LSW(MSD(sfp_dma));
  3377. mcp->mb[8] = len;
  3378. mcp->mb[9] = off;
  3379. mcp->mb[10] = opt;
  3380. mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
  3381. mcp->in_mb = MBX_1|MBX_0;
  3382. mcp->tov = MBX_TOV_SECONDS;
  3383. mcp->flags = 0;
  3384. rval = qla2x00_mailbox_command(vha, mcp);
  3385. if (opt & BIT_0)
  3386. *sfp = mcp->mb[1];
  3387. if (rval != QLA_SUCCESS) {
  3388. ql_dbg(ql_dbg_mbx, vha, 0x10e9,
  3389. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  3390. } else {
  3391. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ea,
  3392. "Done %s.\n", __func__);
  3393. }
  3394. return rval;
  3395. }
  3396. int
  3397. qla2x00_write_sfp(scsi_qla_host_t *vha, dma_addr_t sfp_dma, uint8_t *sfp,
  3398. uint16_t dev, uint16_t off, uint16_t len, uint16_t opt)
  3399. {
  3400. int rval;
  3401. mbx_cmd_t mc;
  3402. mbx_cmd_t *mcp = &mc;
  3403. struct qla_hw_data *ha = vha->hw;
  3404. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10eb,
  3405. "Entered %s.\n", __func__);
  3406. if (!IS_FWI2_CAPABLE(ha))
  3407. return QLA_FUNCTION_FAILED;
  3408. if (len == 1)
  3409. opt |= BIT_0;
  3410. if (opt & BIT_0)
  3411. len = *sfp;
  3412. mcp->mb[0] = MBC_WRITE_SFP;
  3413. mcp->mb[1] = dev;
  3414. mcp->mb[2] = MSW(sfp_dma);
  3415. mcp->mb[3] = LSW(sfp_dma);
  3416. mcp->mb[6] = MSW(MSD(sfp_dma));
  3417. mcp->mb[7] = LSW(MSD(sfp_dma));
  3418. mcp->mb[8] = len;
  3419. mcp->mb[9] = off;
  3420. mcp->mb[10] = opt;
  3421. mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
  3422. mcp->in_mb = MBX_1|MBX_0;
  3423. mcp->tov = MBX_TOV_SECONDS;
  3424. mcp->flags = 0;
  3425. rval = qla2x00_mailbox_command(vha, mcp);
  3426. if (rval != QLA_SUCCESS) {
  3427. ql_dbg(ql_dbg_mbx, vha, 0x10ec,
  3428. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  3429. } else {
  3430. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ed,
  3431. "Done %s.\n", __func__);
  3432. }
  3433. return rval;
  3434. }
  3435. int
  3436. qla2x00_get_xgmac_stats(scsi_qla_host_t *vha, dma_addr_t stats_dma,
  3437. uint16_t size_in_bytes, uint16_t *actual_size)
  3438. {
  3439. int rval;
  3440. mbx_cmd_t mc;
  3441. mbx_cmd_t *mcp = &mc;
  3442. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ee,
  3443. "Entered %s.\n", __func__);
  3444. if (!IS_CNA_CAPABLE(vha->hw))
  3445. return QLA_FUNCTION_FAILED;
  3446. mcp->mb[0] = MBC_GET_XGMAC_STATS;
  3447. mcp->mb[2] = MSW(stats_dma);
  3448. mcp->mb[3] = LSW(stats_dma);
  3449. mcp->mb[6] = MSW(MSD(stats_dma));
  3450. mcp->mb[7] = LSW(MSD(stats_dma));
  3451. mcp->mb[8] = size_in_bytes >> 2;
  3452. mcp->out_mb = MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
  3453. mcp->in_mb = MBX_2|MBX_1|MBX_0;
  3454. mcp->tov = MBX_TOV_SECONDS;
  3455. mcp->flags = 0;
  3456. rval = qla2x00_mailbox_command(vha, mcp);
  3457. if (rval != QLA_SUCCESS) {
  3458. ql_dbg(ql_dbg_mbx, vha, 0x10ef,
  3459. "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
  3460. rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
  3461. } else {
  3462. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f0,
  3463. "Done %s.\n", __func__);
  3464. *actual_size = mcp->mb[2] << 2;
  3465. }
  3466. return rval;
  3467. }
  3468. int
  3469. qla2x00_get_dcbx_params(scsi_qla_host_t *vha, dma_addr_t tlv_dma,
  3470. uint16_t size)
  3471. {
  3472. int rval;
  3473. mbx_cmd_t mc;
  3474. mbx_cmd_t *mcp = &mc;
  3475. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f1,
  3476. "Entered %s.\n", __func__);
  3477. if (!IS_CNA_CAPABLE(vha->hw))
  3478. return QLA_FUNCTION_FAILED;
  3479. mcp->mb[0] = MBC_GET_DCBX_PARAMS;
  3480. mcp->mb[1] = 0;
  3481. mcp->mb[2] = MSW(tlv_dma);
  3482. mcp->mb[3] = LSW(tlv_dma);
  3483. mcp->mb[6] = MSW(MSD(tlv_dma));
  3484. mcp->mb[7] = LSW(MSD(tlv_dma));
  3485. mcp->mb[8] = size;
  3486. mcp->out_mb = MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
  3487. mcp->in_mb = MBX_2|MBX_1|MBX_0;
  3488. mcp->tov = MBX_TOV_SECONDS;
  3489. mcp->flags = 0;
  3490. rval = qla2x00_mailbox_command(vha, mcp);
  3491. if (rval != QLA_SUCCESS) {
  3492. ql_dbg(ql_dbg_mbx, vha, 0x10f2,
  3493. "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
  3494. rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
  3495. } else {
  3496. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f3,
  3497. "Done %s.\n", __func__);
  3498. }
  3499. return rval;
  3500. }
  3501. int
  3502. qla2x00_read_ram_word(scsi_qla_host_t *vha, uint32_t risc_addr, uint32_t *data)
  3503. {
  3504. int rval;
  3505. mbx_cmd_t mc;
  3506. mbx_cmd_t *mcp = &mc;
  3507. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f4,
  3508. "Entered %s.\n", __func__);
  3509. if (!IS_FWI2_CAPABLE(vha->hw))
  3510. return QLA_FUNCTION_FAILED;
  3511. mcp->mb[0] = MBC_READ_RAM_EXTENDED;
  3512. mcp->mb[1] = LSW(risc_addr);
  3513. mcp->mb[8] = MSW(risc_addr);
  3514. mcp->out_mb = MBX_8|MBX_1|MBX_0;
  3515. mcp->in_mb = MBX_3|MBX_2|MBX_0;
  3516. mcp->tov = 30;
  3517. mcp->flags = 0;
  3518. rval = qla2x00_mailbox_command(vha, mcp);
  3519. if (rval != QLA_SUCCESS) {
  3520. ql_dbg(ql_dbg_mbx, vha, 0x10f5,
  3521. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  3522. } else {
  3523. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f6,
  3524. "Done %s.\n", __func__);
  3525. *data = mcp->mb[3] << 16 | mcp->mb[2];
  3526. }
  3527. return rval;
  3528. }
  3529. int
  3530. qla2x00_loopback_test(scsi_qla_host_t *vha, struct msg_echo_lb *mreq,
  3531. uint16_t *mresp)
  3532. {
  3533. int rval;
  3534. mbx_cmd_t mc;
  3535. mbx_cmd_t *mcp = &mc;
  3536. uint32_t iter_cnt = 0x1;
  3537. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f7,
  3538. "Entered %s.\n", __func__);
  3539. memset(mcp->mb, 0 , sizeof(mcp->mb));
  3540. mcp->mb[0] = MBC_DIAGNOSTIC_LOOP_BACK;
  3541. mcp->mb[1] = mreq->options | BIT_6; // BIT_6 specifies 64 bit addressing
  3542. /* transfer count */
  3543. mcp->mb[10] = LSW(mreq->transfer_size);
  3544. mcp->mb[11] = MSW(mreq->transfer_size);
  3545. /* send data address */
  3546. mcp->mb[14] = LSW(mreq->send_dma);
  3547. mcp->mb[15] = MSW(mreq->send_dma);
  3548. mcp->mb[20] = LSW(MSD(mreq->send_dma));
  3549. mcp->mb[21] = MSW(MSD(mreq->send_dma));
  3550. /* receive data address */
  3551. mcp->mb[16] = LSW(mreq->rcv_dma);
  3552. mcp->mb[17] = MSW(mreq->rcv_dma);
  3553. mcp->mb[6] = LSW(MSD(mreq->rcv_dma));
  3554. mcp->mb[7] = MSW(MSD(mreq->rcv_dma));
  3555. /* Iteration count */
  3556. mcp->mb[18] = LSW(iter_cnt);
  3557. mcp->mb[19] = MSW(iter_cnt);
  3558. mcp->out_mb = MBX_21|MBX_20|MBX_19|MBX_18|MBX_17|MBX_16|MBX_15|
  3559. MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_7|MBX_6|MBX_1|MBX_0;
  3560. if (IS_CNA_CAPABLE(vha->hw))
  3561. mcp->out_mb |= MBX_2;
  3562. mcp->in_mb = MBX_19|MBX_18|MBX_3|MBX_2|MBX_1|MBX_0;
  3563. mcp->buf_size = mreq->transfer_size;
  3564. mcp->tov = MBX_TOV_SECONDS;
  3565. mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
  3566. rval = qla2x00_mailbox_command(vha, mcp);
  3567. if (rval != QLA_SUCCESS) {
  3568. ql_dbg(ql_dbg_mbx, vha, 0x10f8,
  3569. "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x mb[3]=%x mb[18]=%x "
  3570. "mb[19]=%x.\n", rval, mcp->mb[0], mcp->mb[1], mcp->mb[2],
  3571. mcp->mb[3], mcp->mb[18], mcp->mb[19]);
  3572. } else {
  3573. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f9,
  3574. "Done %s.\n", __func__);
  3575. }
  3576. /* Copy mailbox information */
  3577. memcpy( mresp, mcp->mb, 64);
  3578. return rval;
  3579. }
  3580. int
  3581. qla2x00_echo_test(scsi_qla_host_t *vha, struct msg_echo_lb *mreq,
  3582. uint16_t *mresp)
  3583. {
  3584. int rval;
  3585. mbx_cmd_t mc;
  3586. mbx_cmd_t *mcp = &mc;
  3587. struct qla_hw_data *ha = vha->hw;
  3588. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10fa,
  3589. "Entered %s.\n", __func__);
  3590. memset(mcp->mb, 0 , sizeof(mcp->mb));
  3591. mcp->mb[0] = MBC_DIAGNOSTIC_ECHO;
  3592. mcp->mb[1] = mreq->options | BIT_6; /* BIT_6 specifies 64bit address */
  3593. if (IS_CNA_CAPABLE(ha)) {
  3594. mcp->mb[1] |= BIT_15;
  3595. mcp->mb[2] = vha->fcoe_fcf_idx;
  3596. }
  3597. mcp->mb[16] = LSW(mreq->rcv_dma);
  3598. mcp->mb[17] = MSW(mreq->rcv_dma);
  3599. mcp->mb[6] = LSW(MSD(mreq->rcv_dma));
  3600. mcp->mb[7] = MSW(MSD(mreq->rcv_dma));
  3601. mcp->mb[10] = LSW(mreq->transfer_size);
  3602. mcp->mb[14] = LSW(mreq->send_dma);
  3603. mcp->mb[15] = MSW(mreq->send_dma);
  3604. mcp->mb[20] = LSW(MSD(mreq->send_dma));
  3605. mcp->mb[21] = MSW(MSD(mreq->send_dma));
  3606. mcp->out_mb = MBX_21|MBX_20|MBX_17|MBX_16|MBX_15|
  3607. MBX_14|MBX_10|MBX_7|MBX_6|MBX_1|MBX_0;
  3608. if (IS_CNA_CAPABLE(ha))
  3609. mcp->out_mb |= MBX_2;
  3610. mcp->in_mb = MBX_0;
  3611. if (IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha) ||
  3612. IS_CNA_CAPABLE(ha) || IS_QLA2031(ha))
  3613. mcp->in_mb |= MBX_1;
  3614. if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha))
  3615. mcp->in_mb |= MBX_3;
  3616. mcp->tov = MBX_TOV_SECONDS;
  3617. mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
  3618. mcp->buf_size = mreq->transfer_size;
  3619. rval = qla2x00_mailbox_command(vha, mcp);
  3620. if (rval != QLA_SUCCESS) {
  3621. ql_dbg(ql_dbg_mbx, vha, 0x10fb,
  3622. "Failed=%x mb[0]=%x mb[1]=%x.\n",
  3623. rval, mcp->mb[0], mcp->mb[1]);
  3624. } else {
  3625. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10fc,
  3626. "Done %s.\n", __func__);
  3627. }
  3628. /* Copy mailbox information */
  3629. memcpy(mresp, mcp->mb, 64);
  3630. return rval;
  3631. }
  3632. int
  3633. qla84xx_reset_chip(scsi_qla_host_t *vha, uint16_t enable_diagnostic)
  3634. {
  3635. int rval;
  3636. mbx_cmd_t mc;
  3637. mbx_cmd_t *mcp = &mc;
  3638. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10fd,
  3639. "Entered %s enable_diag=%d.\n", __func__, enable_diagnostic);
  3640. mcp->mb[0] = MBC_ISP84XX_RESET;
  3641. mcp->mb[1] = enable_diagnostic;
  3642. mcp->out_mb = MBX_1|MBX_0;
  3643. mcp->in_mb = MBX_1|MBX_0;
  3644. mcp->tov = MBX_TOV_SECONDS;
  3645. mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
  3646. rval = qla2x00_mailbox_command(vha, mcp);
  3647. if (rval != QLA_SUCCESS)
  3648. ql_dbg(ql_dbg_mbx, vha, 0x10fe, "Failed=%x.\n", rval);
  3649. else
  3650. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ff,
  3651. "Done %s.\n", __func__);
  3652. return rval;
  3653. }
  3654. int
  3655. qla2x00_write_ram_word(scsi_qla_host_t *vha, uint32_t risc_addr, uint32_t data)
  3656. {
  3657. int rval;
  3658. mbx_cmd_t mc;
  3659. mbx_cmd_t *mcp = &mc;
  3660. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1100,
  3661. "Entered %s.\n", __func__);
  3662. if (!IS_FWI2_CAPABLE(vha->hw))
  3663. return QLA_FUNCTION_FAILED;
  3664. mcp->mb[0] = MBC_WRITE_RAM_WORD_EXTENDED;
  3665. mcp->mb[1] = LSW(risc_addr);
  3666. mcp->mb[2] = LSW(data);
  3667. mcp->mb[3] = MSW(data);
  3668. mcp->mb[8] = MSW(risc_addr);
  3669. mcp->out_mb = MBX_8|MBX_3|MBX_2|MBX_1|MBX_0;
  3670. mcp->in_mb = MBX_0;
  3671. mcp->tov = 30;
  3672. mcp->flags = 0;
  3673. rval = qla2x00_mailbox_command(vha, mcp);
  3674. if (rval != QLA_SUCCESS) {
  3675. ql_dbg(ql_dbg_mbx, vha, 0x1101,
  3676. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  3677. } else {
  3678. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1102,
  3679. "Done %s.\n", __func__);
  3680. }
  3681. return rval;
  3682. }
  3683. int
  3684. qla81xx_write_mpi_register(scsi_qla_host_t *vha, uint16_t *mb)
  3685. {
  3686. int rval;
  3687. uint32_t stat, timer;
  3688. uint16_t mb0 = 0;
  3689. struct qla_hw_data *ha = vha->hw;
  3690. struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
  3691. rval = QLA_SUCCESS;
  3692. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1103,
  3693. "Entered %s.\n", __func__);
  3694. clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
  3695. /* Write the MBC data to the registers */
  3696. WRT_REG_WORD(&reg->mailbox0, MBC_WRITE_MPI_REGISTER);
  3697. WRT_REG_WORD(&reg->mailbox1, mb[0]);
  3698. WRT_REG_WORD(&reg->mailbox2, mb[1]);
  3699. WRT_REG_WORD(&reg->mailbox3, mb[2]);
  3700. WRT_REG_WORD(&reg->mailbox4, mb[3]);
  3701. WRT_REG_DWORD(&reg->hccr, HCCRX_SET_HOST_INT);
  3702. /* Poll for MBC interrupt */
  3703. for (timer = 6000000; timer; timer--) {
  3704. /* Check for pending interrupts. */
  3705. stat = RD_REG_DWORD(&reg->host_status);
  3706. if (stat & HSRX_RISC_INT) {
  3707. stat &= 0xff;
  3708. if (stat == 0x1 || stat == 0x2 ||
  3709. stat == 0x10 || stat == 0x11) {
  3710. set_bit(MBX_INTERRUPT,
  3711. &ha->mbx_cmd_flags);
  3712. mb0 = RD_REG_WORD(&reg->mailbox0);
  3713. WRT_REG_DWORD(&reg->hccr,
  3714. HCCRX_CLR_RISC_INT);
  3715. RD_REG_DWORD(&reg->hccr);
  3716. break;
  3717. }
  3718. }
  3719. udelay(5);
  3720. }
  3721. if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags))
  3722. rval = mb0 & MBS_MASK;
  3723. else
  3724. rval = QLA_FUNCTION_FAILED;
  3725. if (rval != QLA_SUCCESS) {
  3726. ql_dbg(ql_dbg_mbx, vha, 0x1104,
  3727. "Failed=%x mb[0]=%x.\n", rval, mb[0]);
  3728. } else {
  3729. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1105,
  3730. "Done %s.\n", __func__);
  3731. }
  3732. return rval;
  3733. }
  3734. int
  3735. qla2x00_get_data_rate(scsi_qla_host_t *vha)
  3736. {
  3737. int rval;
  3738. mbx_cmd_t mc;
  3739. mbx_cmd_t *mcp = &mc;
  3740. struct qla_hw_data *ha = vha->hw;
  3741. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1106,
  3742. "Entered %s.\n", __func__);
  3743. if (!IS_FWI2_CAPABLE(ha))
  3744. return QLA_FUNCTION_FAILED;
  3745. mcp->mb[0] = MBC_DATA_RATE;
  3746. mcp->mb[1] = 0;
  3747. mcp->out_mb = MBX_1|MBX_0;
  3748. mcp->in_mb = MBX_2|MBX_1|MBX_0;
  3749. if (IS_QLA83XX(ha))
  3750. mcp->in_mb |= MBX_3;
  3751. mcp->tov = MBX_TOV_SECONDS;
  3752. mcp->flags = 0;
  3753. rval = qla2x00_mailbox_command(vha, mcp);
  3754. if (rval != QLA_SUCCESS) {
  3755. ql_dbg(ql_dbg_mbx, vha, 0x1107,
  3756. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  3757. } else {
  3758. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1108,
  3759. "Done %s.\n", __func__);
  3760. if (mcp->mb[1] != 0x7)
  3761. ha->link_data_rate = mcp->mb[1];
  3762. }
  3763. return rval;
  3764. }
  3765. int
  3766. qla81xx_get_port_config(scsi_qla_host_t *vha, uint16_t *mb)
  3767. {
  3768. int rval;
  3769. mbx_cmd_t mc;
  3770. mbx_cmd_t *mcp = &mc;
  3771. struct qla_hw_data *ha = vha->hw;
  3772. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1109,
  3773. "Entered %s.\n", __func__);
  3774. if (!IS_QLA81XX(ha) && !IS_QLA83XX(ha))
  3775. return QLA_FUNCTION_FAILED;
  3776. mcp->mb[0] = MBC_GET_PORT_CONFIG;
  3777. mcp->out_mb = MBX_0;
  3778. mcp->in_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  3779. mcp->tov = MBX_TOV_SECONDS;
  3780. mcp->flags = 0;
  3781. rval = qla2x00_mailbox_command(vha, mcp);
  3782. if (rval != QLA_SUCCESS) {
  3783. ql_dbg(ql_dbg_mbx, vha, 0x110a,
  3784. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  3785. } else {
  3786. /* Copy all bits to preserve original value */
  3787. memcpy(mb, &mcp->mb[1], sizeof(uint16_t) * 4);
  3788. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110b,
  3789. "Done %s.\n", __func__);
  3790. }
  3791. return rval;
  3792. }
  3793. int
  3794. qla81xx_set_port_config(scsi_qla_host_t *vha, uint16_t *mb)
  3795. {
  3796. int rval;
  3797. mbx_cmd_t mc;
  3798. mbx_cmd_t *mcp = &mc;
  3799. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110c,
  3800. "Entered %s.\n", __func__);
  3801. mcp->mb[0] = MBC_SET_PORT_CONFIG;
  3802. /* Copy all bits to preserve original setting */
  3803. memcpy(&mcp->mb[1], mb, sizeof(uint16_t) * 4);
  3804. mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  3805. mcp->in_mb = MBX_0;
  3806. mcp->tov = MBX_TOV_SECONDS;
  3807. mcp->flags = 0;
  3808. rval = qla2x00_mailbox_command(vha, mcp);
  3809. if (rval != QLA_SUCCESS) {
  3810. ql_dbg(ql_dbg_mbx, vha, 0x110d,
  3811. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  3812. } else
  3813. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110e,
  3814. "Done %s.\n", __func__);
  3815. return rval;
  3816. }
  3817. int
  3818. qla24xx_set_fcp_prio(scsi_qla_host_t *vha, uint16_t loop_id, uint16_t priority,
  3819. uint16_t *mb)
  3820. {
  3821. int rval;
  3822. mbx_cmd_t mc;
  3823. mbx_cmd_t *mcp = &mc;
  3824. struct qla_hw_data *ha = vha->hw;
  3825. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110f,
  3826. "Entered %s.\n", __func__);
  3827. if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha))
  3828. return QLA_FUNCTION_FAILED;
  3829. mcp->mb[0] = MBC_PORT_PARAMS;
  3830. mcp->mb[1] = loop_id;
  3831. if (ha->flags.fcp_prio_enabled)
  3832. mcp->mb[2] = BIT_1;
  3833. else
  3834. mcp->mb[2] = BIT_2;
  3835. mcp->mb[4] = priority & 0xf;
  3836. mcp->mb[9] = vha->vp_idx;
  3837. mcp->out_mb = MBX_9|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  3838. mcp->in_mb = MBX_4|MBX_3|MBX_1|MBX_0;
  3839. mcp->tov = 30;
  3840. mcp->flags = 0;
  3841. rval = qla2x00_mailbox_command(vha, mcp);
  3842. if (mb != NULL) {
  3843. mb[0] = mcp->mb[0];
  3844. mb[1] = mcp->mb[1];
  3845. mb[3] = mcp->mb[3];
  3846. mb[4] = mcp->mb[4];
  3847. }
  3848. if (rval != QLA_SUCCESS) {
  3849. ql_dbg(ql_dbg_mbx, vha, 0x10cd, "Failed=%x.\n", rval);
  3850. } else {
  3851. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10cc,
  3852. "Done %s.\n", __func__);
  3853. }
  3854. return rval;
  3855. }
  3856. int
  3857. qla2x00_get_thermal_temp(scsi_qla_host_t *vha, uint16_t *temp, uint16_t *frac)
  3858. {
  3859. int rval;
  3860. uint8_t byte;
  3861. struct qla_hw_data *ha = vha->hw;
  3862. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ca,
  3863. "Entered %s.\n", __func__);
  3864. /* Integer part */
  3865. rval = qla2x00_read_sfp(vha, 0, &byte, 0x98, 0x01, 1, BIT_13|BIT_0);
  3866. if (rval != QLA_SUCCESS) {
  3867. ql_dbg(ql_dbg_mbx, vha, 0x10c9, "Failed=%x.\n", rval);
  3868. ha->flags.thermal_supported = 0;
  3869. goto fail;
  3870. }
  3871. *temp = byte;
  3872. /* Fraction part */
  3873. rval = qla2x00_read_sfp(vha, 0, &byte, 0x98, 0x10, 1, BIT_13|BIT_0);
  3874. if (rval != QLA_SUCCESS) {
  3875. ql_dbg(ql_dbg_mbx, vha, 0x1019, "Failed=%x.\n", rval);
  3876. ha->flags.thermal_supported = 0;
  3877. goto fail;
  3878. }
  3879. *frac = (byte >> 6) * 25;
  3880. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1018,
  3881. "Done %s.\n", __func__);
  3882. fail:
  3883. return rval;
  3884. }
  3885. int
  3886. qla82xx_mbx_intr_enable(scsi_qla_host_t *vha)
  3887. {
  3888. int rval;
  3889. struct qla_hw_data *ha = vha->hw;
  3890. mbx_cmd_t mc;
  3891. mbx_cmd_t *mcp = &mc;
  3892. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1017,
  3893. "Entered %s.\n", __func__);
  3894. if (!IS_FWI2_CAPABLE(ha))
  3895. return QLA_FUNCTION_FAILED;
  3896. memset(mcp, 0, sizeof(mbx_cmd_t));
  3897. mcp->mb[0] = MBC_TOGGLE_INTERRUPT;
  3898. mcp->mb[1] = 1;
  3899. mcp->out_mb = MBX_1|MBX_0;
  3900. mcp->in_mb = MBX_0;
  3901. mcp->tov = 30;
  3902. mcp->flags = 0;
  3903. rval = qla2x00_mailbox_command(vha, mcp);
  3904. if (rval != QLA_SUCCESS) {
  3905. ql_dbg(ql_dbg_mbx, vha, 0x1016,
  3906. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  3907. } else {
  3908. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x100e,
  3909. "Done %s.\n", __func__);
  3910. }
  3911. return rval;
  3912. }
  3913. int
  3914. qla82xx_mbx_intr_disable(scsi_qla_host_t *vha)
  3915. {
  3916. int rval;
  3917. struct qla_hw_data *ha = vha->hw;
  3918. mbx_cmd_t mc;
  3919. mbx_cmd_t *mcp = &mc;
  3920. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x100d,
  3921. "Entered %s.\n", __func__);
  3922. if (!IS_QLA82XX(ha))
  3923. return QLA_FUNCTION_FAILED;
  3924. memset(mcp, 0, sizeof(mbx_cmd_t));
  3925. mcp->mb[0] = MBC_TOGGLE_INTERRUPT;
  3926. mcp->mb[1] = 0;
  3927. mcp->out_mb = MBX_1|MBX_0;
  3928. mcp->in_mb = MBX_0;
  3929. mcp->tov = 30;
  3930. mcp->flags = 0;
  3931. rval = qla2x00_mailbox_command(vha, mcp);
  3932. if (rval != QLA_SUCCESS) {
  3933. ql_dbg(ql_dbg_mbx, vha, 0x100c,
  3934. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  3935. } else {
  3936. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x100b,
  3937. "Done %s.\n", __func__);
  3938. }
  3939. return rval;
  3940. }
  3941. int
  3942. qla82xx_md_get_template_size(scsi_qla_host_t *vha)
  3943. {
  3944. struct qla_hw_data *ha = vha->hw;
  3945. mbx_cmd_t mc;
  3946. mbx_cmd_t *mcp = &mc;
  3947. int rval = QLA_FUNCTION_FAILED;
  3948. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x111f,
  3949. "Entered %s.\n", __func__);
  3950. memset(mcp->mb, 0 , sizeof(mcp->mb));
  3951. mcp->mb[0] = LSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
  3952. mcp->mb[1] = MSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
  3953. mcp->mb[2] = LSW(RQST_TMPLT_SIZE);
  3954. mcp->mb[3] = MSW(RQST_TMPLT_SIZE);
  3955. mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
  3956. mcp->in_mb = MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8|
  3957. MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  3958. mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
  3959. mcp->tov = MBX_TOV_SECONDS;
  3960. rval = qla2x00_mailbox_command(vha, mcp);
  3961. /* Always copy back return mailbox values. */
  3962. if (rval != QLA_SUCCESS) {
  3963. ql_dbg(ql_dbg_mbx, vha, 0x1120,
  3964. "mailbox command FAILED=0x%x, subcode=%x.\n",
  3965. (mcp->mb[1] << 16) | mcp->mb[0],
  3966. (mcp->mb[3] << 16) | mcp->mb[2]);
  3967. } else {
  3968. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1121,
  3969. "Done %s.\n", __func__);
  3970. ha->md_template_size = ((mcp->mb[3] << 16) | mcp->mb[2]);
  3971. if (!ha->md_template_size) {
  3972. ql_dbg(ql_dbg_mbx, vha, 0x1122,
  3973. "Null template size obtained.\n");
  3974. rval = QLA_FUNCTION_FAILED;
  3975. }
  3976. }
  3977. return rval;
  3978. }
  3979. int
  3980. qla82xx_md_get_template(scsi_qla_host_t *vha)
  3981. {
  3982. struct qla_hw_data *ha = vha->hw;
  3983. mbx_cmd_t mc;
  3984. mbx_cmd_t *mcp = &mc;
  3985. int rval = QLA_FUNCTION_FAILED;
  3986. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1123,
  3987. "Entered %s.\n", __func__);
  3988. ha->md_tmplt_hdr = dma_alloc_coherent(&ha->pdev->dev,
  3989. ha->md_template_size, &ha->md_tmplt_hdr_dma, GFP_KERNEL);
  3990. if (!ha->md_tmplt_hdr) {
  3991. ql_log(ql_log_warn, vha, 0x1124,
  3992. "Unable to allocate memory for Minidump template.\n");
  3993. return rval;
  3994. }
  3995. memset(mcp->mb, 0 , sizeof(mcp->mb));
  3996. mcp->mb[0] = LSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
  3997. mcp->mb[1] = MSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
  3998. mcp->mb[2] = LSW(RQST_TMPLT);
  3999. mcp->mb[3] = MSW(RQST_TMPLT);
  4000. mcp->mb[4] = LSW(LSD(ha->md_tmplt_hdr_dma));
  4001. mcp->mb[5] = MSW(LSD(ha->md_tmplt_hdr_dma));
  4002. mcp->mb[6] = LSW(MSD(ha->md_tmplt_hdr_dma));
  4003. mcp->mb[7] = MSW(MSD(ha->md_tmplt_hdr_dma));
  4004. mcp->mb[8] = LSW(ha->md_template_size);
  4005. mcp->mb[9] = MSW(ha->md_template_size);
  4006. mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
  4007. mcp->tov = MBX_TOV_SECONDS;
  4008. mcp->out_mb = MBX_11|MBX_10|MBX_9|MBX_8|
  4009. MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  4010. mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
  4011. rval = qla2x00_mailbox_command(vha, mcp);
  4012. if (rval != QLA_SUCCESS) {
  4013. ql_dbg(ql_dbg_mbx, vha, 0x1125,
  4014. "mailbox command FAILED=0x%x, subcode=%x.\n",
  4015. ((mcp->mb[1] << 16) | mcp->mb[0]),
  4016. ((mcp->mb[3] << 16) | mcp->mb[2]));
  4017. } else
  4018. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1126,
  4019. "Done %s.\n", __func__);
  4020. return rval;
  4021. }
  4022. int
  4023. qla81xx_set_led_config(scsi_qla_host_t *vha, uint16_t *led_cfg)
  4024. {
  4025. int rval;
  4026. struct qla_hw_data *ha = vha->hw;
  4027. mbx_cmd_t mc;
  4028. mbx_cmd_t *mcp = &mc;
  4029. if (!IS_QLA81XX(ha) && !IS_QLA8031(ha))
  4030. return QLA_FUNCTION_FAILED;
  4031. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1133,
  4032. "Entered %s.\n", __func__);
  4033. memset(mcp, 0, sizeof(mbx_cmd_t));
  4034. mcp->mb[0] = MBC_SET_LED_CONFIG;
  4035. mcp->mb[1] = led_cfg[0];
  4036. mcp->mb[2] = led_cfg[1];
  4037. if (IS_QLA8031(ha)) {
  4038. mcp->mb[3] = led_cfg[2];
  4039. mcp->mb[4] = led_cfg[3];
  4040. mcp->mb[5] = led_cfg[4];
  4041. mcp->mb[6] = led_cfg[5];
  4042. }
  4043. mcp->out_mb = MBX_2|MBX_1|MBX_0;
  4044. if (IS_QLA8031(ha))
  4045. mcp->out_mb |= MBX_6|MBX_5|MBX_4|MBX_3;
  4046. mcp->in_mb = MBX_0;
  4047. mcp->tov = 30;
  4048. mcp->flags = 0;
  4049. rval = qla2x00_mailbox_command(vha, mcp);
  4050. if (rval != QLA_SUCCESS) {
  4051. ql_dbg(ql_dbg_mbx, vha, 0x1134,
  4052. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  4053. } else {
  4054. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1135,
  4055. "Done %s.\n", __func__);
  4056. }
  4057. return rval;
  4058. }
  4059. int
  4060. qla81xx_get_led_config(scsi_qla_host_t *vha, uint16_t *led_cfg)
  4061. {
  4062. int rval;
  4063. struct qla_hw_data *ha = vha->hw;
  4064. mbx_cmd_t mc;
  4065. mbx_cmd_t *mcp = &mc;
  4066. if (!IS_QLA81XX(ha) && !IS_QLA8031(ha))
  4067. return QLA_FUNCTION_FAILED;
  4068. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1136,
  4069. "Entered %s.\n", __func__);
  4070. memset(mcp, 0, sizeof(mbx_cmd_t));
  4071. mcp->mb[0] = MBC_GET_LED_CONFIG;
  4072. mcp->out_mb = MBX_0;
  4073. mcp->in_mb = MBX_2|MBX_1|MBX_0;
  4074. if (IS_QLA8031(ha))
  4075. mcp->in_mb |= MBX_6|MBX_5|MBX_4|MBX_3;
  4076. mcp->tov = 30;
  4077. mcp->flags = 0;
  4078. rval = qla2x00_mailbox_command(vha, mcp);
  4079. if (rval != QLA_SUCCESS) {
  4080. ql_dbg(ql_dbg_mbx, vha, 0x1137,
  4081. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  4082. } else {
  4083. led_cfg[0] = mcp->mb[1];
  4084. led_cfg[1] = mcp->mb[2];
  4085. if (IS_QLA8031(ha)) {
  4086. led_cfg[2] = mcp->mb[3];
  4087. led_cfg[3] = mcp->mb[4];
  4088. led_cfg[4] = mcp->mb[5];
  4089. led_cfg[5] = mcp->mb[6];
  4090. }
  4091. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1138,
  4092. "Done %s.\n", __func__);
  4093. }
  4094. return rval;
  4095. }
  4096. int
  4097. qla82xx_mbx_beacon_ctl(scsi_qla_host_t *vha, int enable)
  4098. {
  4099. int rval;
  4100. struct qla_hw_data *ha = vha->hw;
  4101. mbx_cmd_t mc;
  4102. mbx_cmd_t *mcp = &mc;
  4103. if (!IS_QLA82XX(ha))
  4104. return QLA_FUNCTION_FAILED;
  4105. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1127,
  4106. "Entered %s.\n", __func__);
  4107. memset(mcp, 0, sizeof(mbx_cmd_t));
  4108. mcp->mb[0] = MBC_SET_LED_CONFIG;
  4109. if (enable)
  4110. mcp->mb[7] = 0xE;
  4111. else
  4112. mcp->mb[7] = 0xD;
  4113. mcp->out_mb = MBX_7|MBX_0;
  4114. mcp->in_mb = MBX_0;
  4115. mcp->tov = MBX_TOV_SECONDS;
  4116. mcp->flags = 0;
  4117. rval = qla2x00_mailbox_command(vha, mcp);
  4118. if (rval != QLA_SUCCESS) {
  4119. ql_dbg(ql_dbg_mbx, vha, 0x1128,
  4120. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  4121. } else {
  4122. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1129,
  4123. "Done %s.\n", __func__);
  4124. }
  4125. return rval;
  4126. }
  4127. int
  4128. qla83xx_write_remote_reg(scsi_qla_host_t *vha, uint32_t reg, uint32_t data)
  4129. {
  4130. int rval;
  4131. struct qla_hw_data *ha = vha->hw;
  4132. mbx_cmd_t mc;
  4133. mbx_cmd_t *mcp = &mc;
  4134. if (!IS_QLA83XX(ha))
  4135. return QLA_FUNCTION_FAILED;
  4136. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1130,
  4137. "Entered %s.\n", __func__);
  4138. mcp->mb[0] = MBC_WRITE_REMOTE_REG;
  4139. mcp->mb[1] = LSW(reg);
  4140. mcp->mb[2] = MSW(reg);
  4141. mcp->mb[3] = LSW(data);
  4142. mcp->mb[4] = MSW(data);
  4143. mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  4144. mcp->in_mb = MBX_1|MBX_0;
  4145. mcp->tov = MBX_TOV_SECONDS;
  4146. mcp->flags = 0;
  4147. rval = qla2x00_mailbox_command(vha, mcp);
  4148. if (rval != QLA_SUCCESS) {
  4149. ql_dbg(ql_dbg_mbx, vha, 0x1131,
  4150. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  4151. } else {
  4152. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1132,
  4153. "Done %s.\n", __func__);
  4154. }
  4155. return rval;
  4156. }
  4157. int
  4158. qla2x00_port_logout(scsi_qla_host_t *vha, struct fc_port *fcport)
  4159. {
  4160. int rval;
  4161. struct qla_hw_data *ha = vha->hw;
  4162. mbx_cmd_t mc;
  4163. mbx_cmd_t *mcp = &mc;
  4164. if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
  4165. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x113b,
  4166. "Implicit LOGO Unsupported.\n");
  4167. return QLA_FUNCTION_FAILED;
  4168. }
  4169. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x113c,
  4170. "Entering %s.\n", __func__);
  4171. /* Perform Implicit LOGO. */
  4172. mcp->mb[0] = MBC_PORT_LOGOUT;
  4173. mcp->mb[1] = fcport->loop_id;
  4174. mcp->mb[10] = BIT_15;
  4175. mcp->out_mb = MBX_10|MBX_1|MBX_0;
  4176. mcp->in_mb = MBX_0;
  4177. mcp->tov = MBX_TOV_SECONDS;
  4178. mcp->flags = 0;
  4179. rval = qla2x00_mailbox_command(vha, mcp);
  4180. if (rval != QLA_SUCCESS)
  4181. ql_dbg(ql_dbg_mbx, vha, 0x113d,
  4182. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  4183. else
  4184. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x113e,
  4185. "Done %s.\n", __func__);
  4186. return rval;
  4187. }