qla_init.c 144 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457145814591460146114621463146414651466146714681469147014711472147314741475147614771478147914801481148214831484148514861487148814891490149114921493149414951496149714981499150015011502150315041505150615071508150915101511151215131514151515161517151815191520152115221523152415251526152715281529153015311532153315341535153615371538153915401541154215431544154515461547154815491550155115521553155415551556155715581559156015611562156315641565156615671568156915701571157215731574157515761577157815791580158115821583158415851586158715881589159015911592159315941595159615971598159916001601160216031604160516061607160816091610161116121613161416151616161716181619162016211622162316241625162616271628162916301631163216331634163516361637163816391640164116421643164416451646164716481649165016511652165316541655165616571658165916601661166216631664166516661667166816691670167116721673167416751676167716781679168016811682168316841685168616871688168916901691169216931694169516961697169816991700170117021703170417051706170717081709171017111712171317141715171617171718171917201721172217231724172517261727172817291730173117321733173417351736173717381739174017411742174317441745174617471748174917501751175217531754175517561757175817591760176117621763176417651766176717681769177017711772177317741775177617771778177917801781178217831784178517861787178817891790179117921793179417951796179717981799180018011802180318041805180618071808180918101811181218131814181518161817181818191820182118221823182418251826182718281829183018311832183318341835183618371838183918401841184218431844184518461847184818491850185118521853185418551856185718581859186018611862186318641865186618671868186918701871187218731874187518761877187818791880188118821883188418851886188718881889189018911892189318941895189618971898189919001901190219031904190519061907190819091910191119121913191419151916191719181919192019211922192319241925192619271928192919301931193219331934193519361937193819391940194119421943194419451946194719481949195019511952195319541955195619571958195919601961196219631964196519661967196819691970197119721973197419751976197719781979198019811982198319841985198619871988198919901991199219931994199519961997199819992000200120022003200420052006200720082009201020112012201320142015201620172018201920202021202220232024202520262027202820292030203120322033203420352036203720382039204020412042204320442045204620472048204920502051205220532054205520562057205820592060206120622063206420652066206720682069207020712072207320742075207620772078207920802081208220832084208520862087208820892090209120922093209420952096209720982099210021012102210321042105210621072108210921102111211221132114211521162117211821192120212121222123212421252126212721282129213021312132213321342135213621372138213921402141214221432144214521462147214821492150215121522153215421552156215721582159216021612162216321642165216621672168216921702171217221732174217521762177217821792180218121822183218421852186218721882189219021912192219321942195219621972198219922002201220222032204220522062207220822092210221122122213221422152216221722182219222022212222222322242225222622272228222922302231223222332234223522362237223822392240224122422243224422452246224722482249225022512252225322542255225622572258225922602261226222632264226522662267226822692270227122722273227422752276227722782279228022812282228322842285228622872288228922902291229222932294229522962297229822992300230123022303230423052306230723082309231023112312231323142315231623172318231923202321232223232324232523262327232823292330233123322333233423352336233723382339234023412342234323442345234623472348234923502351235223532354235523562357235823592360236123622363236423652366236723682369237023712372237323742375237623772378237923802381238223832384238523862387238823892390239123922393239423952396239723982399240024012402240324042405240624072408240924102411241224132414241524162417241824192420242124222423242424252426242724282429243024312432243324342435243624372438243924402441244224432444244524462447244824492450245124522453245424552456245724582459246024612462246324642465246624672468246924702471247224732474247524762477247824792480248124822483248424852486248724882489249024912492249324942495249624972498249925002501250225032504250525062507250825092510251125122513251425152516251725182519252025212522252325242525252625272528252925302531253225332534253525362537253825392540254125422543254425452546254725482549255025512552255325542555255625572558255925602561256225632564256525662567256825692570257125722573257425752576257725782579258025812582258325842585258625872588258925902591259225932594259525962597259825992600260126022603260426052606260726082609261026112612261326142615261626172618261926202621262226232624262526262627262826292630263126322633263426352636263726382639264026412642264326442645264626472648264926502651265226532654265526562657265826592660266126622663266426652666266726682669267026712672267326742675267626772678267926802681268226832684268526862687268826892690269126922693269426952696269726982699270027012702270327042705270627072708270927102711271227132714271527162717271827192720272127222723272427252726272727282729273027312732273327342735273627372738273927402741274227432744274527462747274827492750275127522753275427552756275727582759276027612762276327642765276627672768276927702771277227732774277527762777277827792780278127822783278427852786278727882789279027912792279327942795279627972798279928002801280228032804280528062807280828092810281128122813281428152816281728182819282028212822282328242825282628272828282928302831283228332834283528362837283828392840284128422843284428452846284728482849285028512852285328542855285628572858285928602861286228632864286528662867286828692870287128722873287428752876287728782879288028812882288328842885288628872888288928902891289228932894289528962897289828992900290129022903290429052906290729082909291029112912291329142915291629172918291929202921292229232924292529262927292829292930293129322933293429352936293729382939294029412942294329442945294629472948294929502951295229532954295529562957295829592960296129622963296429652966296729682969297029712972297329742975297629772978297929802981298229832984298529862987298829892990299129922993299429952996299729982999300030013002300330043005300630073008300930103011301230133014301530163017301830193020302130223023302430253026302730283029303030313032303330343035303630373038303930403041304230433044304530463047304830493050305130523053305430553056305730583059306030613062306330643065306630673068306930703071307230733074307530763077307830793080308130823083308430853086308730883089309030913092309330943095309630973098309931003101310231033104310531063107310831093110311131123113311431153116311731183119312031213122312331243125312631273128312931303131313231333134313531363137313831393140314131423143314431453146314731483149315031513152315331543155315631573158315931603161316231633164316531663167316831693170317131723173317431753176317731783179318031813182318331843185318631873188318931903191319231933194319531963197319831993200320132023203320432053206320732083209321032113212321332143215321632173218321932203221322232233224322532263227322832293230323132323233323432353236323732383239324032413242324332443245324632473248324932503251325232533254325532563257325832593260326132623263326432653266326732683269327032713272327332743275327632773278327932803281328232833284328532863287328832893290329132923293329432953296329732983299330033013302330333043305330633073308330933103311331233133314331533163317331833193320332133223323332433253326332733283329333033313332333333343335333633373338333933403341334233433344334533463347334833493350335133523353335433553356335733583359336033613362336333643365336633673368336933703371337233733374337533763377337833793380338133823383338433853386338733883389339033913392339333943395339633973398339934003401340234033404340534063407340834093410341134123413341434153416341734183419342034213422342334243425342634273428342934303431343234333434343534363437343834393440344134423443344434453446344734483449345034513452345334543455345634573458345934603461346234633464346534663467346834693470347134723473347434753476347734783479348034813482348334843485348634873488348934903491349234933494349534963497349834993500350135023503350435053506350735083509351035113512351335143515351635173518351935203521352235233524352535263527352835293530353135323533353435353536353735383539354035413542354335443545354635473548354935503551355235533554355535563557355835593560356135623563356435653566356735683569357035713572357335743575357635773578357935803581358235833584358535863587358835893590359135923593359435953596359735983599360036013602360336043605360636073608360936103611361236133614361536163617361836193620362136223623362436253626362736283629363036313632363336343635363636373638363936403641364236433644364536463647364836493650365136523653365436553656365736583659366036613662366336643665366636673668366936703671367236733674367536763677367836793680368136823683368436853686368736883689369036913692369336943695369636973698369937003701370237033704370537063707370837093710371137123713371437153716371737183719372037213722372337243725372637273728372937303731373237333734373537363737373837393740374137423743374437453746374737483749375037513752375337543755375637573758375937603761376237633764376537663767376837693770377137723773377437753776377737783779378037813782378337843785378637873788378937903791379237933794379537963797379837993800380138023803380438053806380738083809381038113812381338143815381638173818381938203821382238233824382538263827382838293830383138323833383438353836383738383839384038413842384338443845384638473848384938503851385238533854385538563857385838593860386138623863386438653866386738683869387038713872387338743875387638773878387938803881388238833884388538863887388838893890389138923893389438953896389738983899390039013902390339043905390639073908390939103911391239133914391539163917391839193920392139223923392439253926392739283929393039313932393339343935393639373938393939403941394239433944394539463947394839493950395139523953395439553956395739583959396039613962396339643965396639673968396939703971397239733974397539763977397839793980398139823983398439853986398739883989399039913992399339943995399639973998399940004001400240034004400540064007400840094010401140124013401440154016401740184019402040214022402340244025402640274028402940304031403240334034403540364037403840394040404140424043404440454046404740484049405040514052405340544055405640574058405940604061406240634064406540664067406840694070407140724073407440754076407740784079408040814082408340844085408640874088408940904091409240934094409540964097409840994100410141024103410441054106410741084109411041114112411341144115411641174118411941204121412241234124412541264127412841294130413141324133413441354136413741384139414041414142414341444145414641474148414941504151415241534154415541564157415841594160416141624163416441654166416741684169417041714172417341744175417641774178417941804181418241834184418541864187418841894190419141924193419441954196419741984199420042014202420342044205420642074208420942104211421242134214421542164217421842194220422142224223422442254226422742284229423042314232423342344235423642374238423942404241424242434244424542464247424842494250425142524253425442554256425742584259426042614262426342644265426642674268426942704271427242734274427542764277427842794280428142824283428442854286428742884289429042914292429342944295429642974298429943004301430243034304430543064307430843094310431143124313431443154316431743184319432043214322432343244325432643274328432943304331433243334334433543364337433843394340434143424343434443454346434743484349435043514352435343544355435643574358435943604361436243634364436543664367436843694370437143724373437443754376437743784379438043814382438343844385438643874388438943904391439243934394439543964397439843994400440144024403440444054406440744084409441044114412441344144415441644174418441944204421442244234424442544264427442844294430443144324433443444354436443744384439444044414442444344444445444644474448444944504451445244534454445544564457445844594460446144624463446444654466446744684469447044714472447344744475447644774478447944804481448244834484448544864487448844894490449144924493449444954496449744984499450045014502450345044505450645074508450945104511451245134514451545164517451845194520452145224523452445254526452745284529453045314532453345344535453645374538453945404541454245434544454545464547454845494550455145524553455445554556455745584559456045614562456345644565456645674568456945704571457245734574457545764577457845794580458145824583458445854586458745884589459045914592459345944595459645974598459946004601460246034604460546064607460846094610461146124613461446154616461746184619462046214622462346244625462646274628462946304631463246334634463546364637463846394640464146424643464446454646464746484649465046514652465346544655465646574658465946604661466246634664466546664667466846694670467146724673467446754676467746784679468046814682468346844685468646874688468946904691469246934694469546964697469846994700470147024703470447054706470747084709471047114712471347144715471647174718471947204721472247234724472547264727472847294730473147324733473447354736473747384739474047414742474347444745474647474748474947504751475247534754475547564757475847594760476147624763476447654766476747684769477047714772477347744775477647774778477947804781478247834784478547864787478847894790479147924793479447954796479747984799480048014802480348044805480648074808480948104811481248134814481548164817481848194820482148224823482448254826482748284829483048314832483348344835483648374838483948404841484248434844484548464847484848494850485148524853485448554856485748584859486048614862486348644865486648674868486948704871487248734874487548764877487848794880488148824883488448854886488748884889489048914892489348944895489648974898489949004901490249034904490549064907490849094910491149124913491449154916491749184919492049214922492349244925492649274928492949304931493249334934493549364937493849394940494149424943494449454946494749484949495049514952495349544955495649574958495949604961496249634964496549664967496849694970497149724973497449754976497749784979498049814982498349844985498649874988498949904991499249934994499549964997499849995000500150025003500450055006500750085009501050115012501350145015501650175018501950205021502250235024502550265027502850295030503150325033503450355036503750385039504050415042504350445045504650475048504950505051505250535054505550565057505850595060506150625063506450655066506750685069507050715072507350745075507650775078507950805081508250835084508550865087508850895090509150925093509450955096509750985099510051015102510351045105510651075108510951105111511251135114511551165117511851195120512151225123512451255126512751285129513051315132513351345135513651375138513951405141514251435144514551465147514851495150515151525153515451555156515751585159516051615162516351645165516651675168516951705171517251735174517551765177517851795180518151825183518451855186518751885189519051915192519351945195519651975198519952005201520252035204520552065207520852095210521152125213521452155216521752185219522052215222522352245225522652275228522952305231523252335234523552365237523852395240524152425243524452455246524752485249525052515252525352545255525652575258525952605261526252635264526552665267526852695270527152725273527452755276527752785279528052815282528352845285528652875288528952905291529252935294529552965297529852995300530153025303530453055306530753085309531053115312531353145315531653175318531953205321532253235324532553265327532853295330533153325333533453355336533753385339534053415342534353445345534653475348534953505351535253535354535553565357535853595360536153625363536453655366536753685369537053715372537353745375537653775378537953805381538253835384538553865387538853895390539153925393539453955396539753985399540054015402540354045405540654075408540954105411541254135414541554165417541854195420542154225423542454255426542754285429543054315432543354345435543654375438543954405441544254435444544554465447544854495450545154525453545454555456545754585459546054615462546354645465546654675468546954705471547254735474547554765477547854795480548154825483548454855486548754885489549054915492549354945495549654975498549955005501550255035504550555065507550855095510551155125513551455155516551755185519552055215522552355245525552655275528552955305531553255335534553555365537553855395540554155425543554455455546554755485549555055515552555355545555555655575558555955605561
  1. /*
  2. * QLogic Fibre Channel HBA Driver
  3. * Copyright (c) 2003-2011 QLogic Corporation
  4. *
  5. * See LICENSE.qla2xxx for copyright and licensing details.
  6. */
  7. #include "qla_def.h"
  8. #include "qla_gbl.h"
  9. #include <linux/delay.h>
  10. #include <linux/slab.h>
  11. #include <linux/vmalloc.h>
  12. #include "qla_devtbl.h"
  13. #ifdef CONFIG_SPARC
  14. #include <asm/prom.h>
  15. #endif
  16. #include <target/target_core_base.h>
  17. #include "qla_target.h"
  18. /*
  19. * QLogic ISP2x00 Hardware Support Function Prototypes.
  20. */
  21. static int qla2x00_isp_firmware(scsi_qla_host_t *);
  22. static int qla2x00_setup_chip(scsi_qla_host_t *);
  23. static int qla2x00_init_rings(scsi_qla_host_t *);
  24. static int qla2x00_fw_ready(scsi_qla_host_t *);
  25. static int qla2x00_configure_hba(scsi_qla_host_t *);
  26. static int qla2x00_configure_loop(scsi_qla_host_t *);
  27. static int qla2x00_configure_local_loop(scsi_qla_host_t *);
  28. static int qla2x00_configure_fabric(scsi_qla_host_t *);
  29. static int qla2x00_find_all_fabric_devs(scsi_qla_host_t *, struct list_head *);
  30. static int qla2x00_fabric_dev_login(scsi_qla_host_t *, fc_port_t *,
  31. uint16_t *);
  32. static int qla2x00_restart_isp(scsi_qla_host_t *);
  33. static struct qla_chip_state_84xx *qla84xx_get_chip(struct scsi_qla_host *);
  34. static int qla84xx_init_chip(scsi_qla_host_t *);
  35. static int qla25xx_init_queues(struct qla_hw_data *);
  36. /* SRB Extensions ---------------------------------------------------------- */
  37. void
  38. qla2x00_sp_timeout(unsigned long __data)
  39. {
  40. srb_t *sp = (srb_t *)__data;
  41. struct srb_iocb *iocb;
  42. fc_port_t *fcport = sp->fcport;
  43. struct qla_hw_data *ha = fcport->vha->hw;
  44. struct req_que *req;
  45. unsigned long flags;
  46. spin_lock_irqsave(&ha->hardware_lock, flags);
  47. req = ha->req_q_map[0];
  48. req->outstanding_cmds[sp->handle] = NULL;
  49. iocb = &sp->u.iocb_cmd;
  50. iocb->timeout(sp);
  51. sp->free(fcport->vha, sp);
  52. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  53. }
  54. void
  55. qla2x00_sp_free(void *data, void *ptr)
  56. {
  57. srb_t *sp = (srb_t *)ptr;
  58. struct srb_iocb *iocb = &sp->u.iocb_cmd;
  59. struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
  60. del_timer(&iocb->timer);
  61. mempool_free(sp, vha->hw->srb_mempool);
  62. QLA_VHA_MARK_NOT_BUSY(vha);
  63. }
  64. /* Asynchronous Login/Logout Routines -------------------------------------- */
  65. static inline unsigned long
  66. qla2x00_get_async_timeout(struct scsi_qla_host *vha)
  67. {
  68. unsigned long tmo;
  69. struct qla_hw_data *ha = vha->hw;
  70. /* Firmware should use switch negotiated r_a_tov for timeout. */
  71. tmo = ha->r_a_tov / 10 * 2;
  72. if (!IS_FWI2_CAPABLE(ha)) {
  73. /*
  74. * Except for earlier ISPs where the timeout is seeded from the
  75. * initialization control block.
  76. */
  77. tmo = ha->login_timeout;
  78. }
  79. return tmo;
  80. }
  81. static void
  82. qla2x00_async_iocb_timeout(void *data)
  83. {
  84. srb_t *sp = (srb_t *)data;
  85. fc_port_t *fcport = sp->fcport;
  86. ql_dbg(ql_dbg_disc, fcport->vha, 0x2071,
  87. "Async-%s timeout - hdl=%x portid=%02x%02x%02x.\n",
  88. sp->name, sp->handle, fcport->d_id.b.domain, fcport->d_id.b.area,
  89. fcport->d_id.b.al_pa);
  90. fcport->flags &= ~FCF_ASYNC_SENT;
  91. if (sp->type == SRB_LOGIN_CMD) {
  92. struct srb_iocb *lio = &sp->u.iocb_cmd;
  93. qla2x00_post_async_logout_work(fcport->vha, fcport, NULL);
  94. /* Retry as needed. */
  95. lio->u.logio.data[0] = MBS_COMMAND_ERROR;
  96. lio->u.logio.data[1] = lio->u.logio.flags & SRB_LOGIN_RETRIED ?
  97. QLA_LOGIO_LOGIN_RETRIED : 0;
  98. qla2x00_post_async_login_done_work(fcport->vha, fcport,
  99. lio->u.logio.data);
  100. }
  101. }
  102. static void
  103. qla2x00_async_login_sp_done(void *data, void *ptr, int res)
  104. {
  105. srb_t *sp = (srb_t *)ptr;
  106. struct srb_iocb *lio = &sp->u.iocb_cmd;
  107. struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
  108. if (!test_bit(UNLOADING, &vha->dpc_flags))
  109. qla2x00_post_async_login_done_work(sp->fcport->vha, sp->fcport,
  110. lio->u.logio.data);
  111. sp->free(sp->fcport->vha, sp);
  112. }
  113. int
  114. qla2x00_async_login(struct scsi_qla_host *vha, fc_port_t *fcport,
  115. uint16_t *data)
  116. {
  117. srb_t *sp;
  118. struct srb_iocb *lio;
  119. int rval;
  120. rval = QLA_FUNCTION_FAILED;
  121. sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
  122. if (!sp)
  123. goto done;
  124. sp->type = SRB_LOGIN_CMD;
  125. sp->name = "login";
  126. qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
  127. lio = &sp->u.iocb_cmd;
  128. lio->timeout = qla2x00_async_iocb_timeout;
  129. sp->done = qla2x00_async_login_sp_done;
  130. lio->u.logio.flags |= SRB_LOGIN_COND_PLOGI;
  131. if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
  132. lio->u.logio.flags |= SRB_LOGIN_RETRIED;
  133. rval = qla2x00_start_sp(sp);
  134. if (rval != QLA_SUCCESS)
  135. goto done_free_sp;
  136. ql_dbg(ql_dbg_disc, vha, 0x2072,
  137. "Async-login - hdl=%x, loopid=%x portid=%02x%02x%02x "
  138. "retries=%d.\n", sp->handle, fcport->loop_id,
  139. fcport->d_id.b.domain, fcport->d_id.b.area, fcport->d_id.b.al_pa,
  140. fcport->login_retry);
  141. return rval;
  142. done_free_sp:
  143. sp->free(fcport->vha, sp);
  144. done:
  145. return rval;
  146. }
  147. static void
  148. qla2x00_async_logout_sp_done(void *data, void *ptr, int res)
  149. {
  150. srb_t *sp = (srb_t *)ptr;
  151. struct srb_iocb *lio = &sp->u.iocb_cmd;
  152. struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
  153. if (!test_bit(UNLOADING, &vha->dpc_flags))
  154. qla2x00_post_async_logout_done_work(sp->fcport->vha, sp->fcport,
  155. lio->u.logio.data);
  156. sp->free(sp->fcport->vha, sp);
  157. }
  158. int
  159. qla2x00_async_logout(struct scsi_qla_host *vha, fc_port_t *fcport)
  160. {
  161. srb_t *sp;
  162. struct srb_iocb *lio;
  163. int rval;
  164. rval = QLA_FUNCTION_FAILED;
  165. sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
  166. if (!sp)
  167. goto done;
  168. sp->type = SRB_LOGOUT_CMD;
  169. sp->name = "logout";
  170. qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
  171. lio = &sp->u.iocb_cmd;
  172. lio->timeout = qla2x00_async_iocb_timeout;
  173. sp->done = qla2x00_async_logout_sp_done;
  174. rval = qla2x00_start_sp(sp);
  175. if (rval != QLA_SUCCESS)
  176. goto done_free_sp;
  177. ql_dbg(ql_dbg_disc, vha, 0x2070,
  178. "Async-logout - hdl=%x loop-id=%x portid=%02x%02x%02x.\n",
  179. sp->handle, fcport->loop_id, fcport->d_id.b.domain,
  180. fcport->d_id.b.area, fcport->d_id.b.al_pa);
  181. return rval;
  182. done_free_sp:
  183. sp->free(fcport->vha, sp);
  184. done:
  185. return rval;
  186. }
  187. static void
  188. qla2x00_async_adisc_sp_done(void *data, void *ptr, int res)
  189. {
  190. srb_t *sp = (srb_t *)ptr;
  191. struct srb_iocb *lio = &sp->u.iocb_cmd;
  192. struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
  193. if (!test_bit(UNLOADING, &vha->dpc_flags))
  194. qla2x00_post_async_adisc_done_work(sp->fcport->vha, sp->fcport,
  195. lio->u.logio.data);
  196. sp->free(sp->fcport->vha, sp);
  197. }
  198. int
  199. qla2x00_async_adisc(struct scsi_qla_host *vha, fc_port_t *fcport,
  200. uint16_t *data)
  201. {
  202. srb_t *sp;
  203. struct srb_iocb *lio;
  204. int rval;
  205. rval = QLA_FUNCTION_FAILED;
  206. sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
  207. if (!sp)
  208. goto done;
  209. sp->type = SRB_ADISC_CMD;
  210. sp->name = "adisc";
  211. qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
  212. lio = &sp->u.iocb_cmd;
  213. lio->timeout = qla2x00_async_iocb_timeout;
  214. sp->done = qla2x00_async_adisc_sp_done;
  215. if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
  216. lio->u.logio.flags |= SRB_LOGIN_RETRIED;
  217. rval = qla2x00_start_sp(sp);
  218. if (rval != QLA_SUCCESS)
  219. goto done_free_sp;
  220. ql_dbg(ql_dbg_disc, vha, 0x206f,
  221. "Async-adisc - hdl=%x loopid=%x portid=%02x%02x%02x.\n",
  222. sp->handle, fcport->loop_id, fcport->d_id.b.domain,
  223. fcport->d_id.b.area, fcport->d_id.b.al_pa);
  224. return rval;
  225. done_free_sp:
  226. sp->free(fcport->vha, sp);
  227. done:
  228. return rval;
  229. }
  230. static void
  231. qla2x00_async_tm_cmd_done(void *data, void *ptr, int res)
  232. {
  233. srb_t *sp = (srb_t *)ptr;
  234. struct srb_iocb *iocb = &sp->u.iocb_cmd;
  235. struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
  236. uint32_t flags;
  237. uint16_t lun;
  238. int rval;
  239. if (!test_bit(UNLOADING, &vha->dpc_flags)) {
  240. flags = iocb->u.tmf.flags;
  241. lun = (uint16_t)iocb->u.tmf.lun;
  242. /* Issue Marker IOCB */
  243. rval = qla2x00_marker(vha, vha->hw->req_q_map[0],
  244. vha->hw->rsp_q_map[0], sp->fcport->loop_id, lun,
  245. flags == TCF_LUN_RESET ? MK_SYNC_ID_LUN : MK_SYNC_ID);
  246. if ((rval != QLA_SUCCESS) || iocb->u.tmf.data) {
  247. ql_dbg(ql_dbg_taskm, vha, 0x8030,
  248. "TM IOCB failed (%x).\n", rval);
  249. }
  250. }
  251. sp->free(sp->fcport->vha, sp);
  252. }
  253. int
  254. qla2x00_async_tm_cmd(fc_port_t *fcport, uint32_t tm_flags, uint32_t lun,
  255. uint32_t tag)
  256. {
  257. struct scsi_qla_host *vha = fcport->vha;
  258. srb_t *sp;
  259. struct srb_iocb *tcf;
  260. int rval;
  261. rval = QLA_FUNCTION_FAILED;
  262. sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
  263. if (!sp)
  264. goto done;
  265. sp->type = SRB_TM_CMD;
  266. sp->name = "tmf";
  267. qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
  268. tcf = &sp->u.iocb_cmd;
  269. tcf->u.tmf.flags = tm_flags;
  270. tcf->u.tmf.lun = lun;
  271. tcf->u.tmf.data = tag;
  272. tcf->timeout = qla2x00_async_iocb_timeout;
  273. sp->done = qla2x00_async_tm_cmd_done;
  274. rval = qla2x00_start_sp(sp);
  275. if (rval != QLA_SUCCESS)
  276. goto done_free_sp;
  277. ql_dbg(ql_dbg_taskm, vha, 0x802f,
  278. "Async-tmf hdl=%x loop-id=%x portid=%02x%02x%02x.\n",
  279. sp->handle, fcport->loop_id, fcport->d_id.b.domain,
  280. fcport->d_id.b.area, fcport->d_id.b.al_pa);
  281. return rval;
  282. done_free_sp:
  283. sp->free(fcport->vha, sp);
  284. done:
  285. return rval;
  286. }
  287. void
  288. qla2x00_async_login_done(struct scsi_qla_host *vha, fc_port_t *fcport,
  289. uint16_t *data)
  290. {
  291. int rval;
  292. switch (data[0]) {
  293. case MBS_COMMAND_COMPLETE:
  294. /*
  295. * Driver must validate login state - If PRLI not complete,
  296. * force a relogin attempt via implicit LOGO, PLOGI, and PRLI
  297. * requests.
  298. */
  299. rval = qla2x00_get_port_database(vha, fcport, 0);
  300. if (rval == QLA_NOT_LOGGED_IN) {
  301. fcport->flags &= ~FCF_ASYNC_SENT;
  302. fcport->flags |= FCF_LOGIN_NEEDED;
  303. set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
  304. break;
  305. }
  306. if (rval != QLA_SUCCESS) {
  307. qla2x00_post_async_logout_work(vha, fcport, NULL);
  308. qla2x00_post_async_login_work(vha, fcport, NULL);
  309. break;
  310. }
  311. if (fcport->flags & FCF_FCP2_DEVICE) {
  312. qla2x00_post_async_adisc_work(vha, fcport, data);
  313. break;
  314. }
  315. qla2x00_update_fcport(vha, fcport);
  316. break;
  317. case MBS_COMMAND_ERROR:
  318. fcport->flags &= ~FCF_ASYNC_SENT;
  319. if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
  320. set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
  321. else
  322. qla2x00_mark_device_lost(vha, fcport, 1, 0);
  323. break;
  324. case MBS_PORT_ID_USED:
  325. fcport->loop_id = data[1];
  326. qla2x00_post_async_logout_work(vha, fcport, NULL);
  327. qla2x00_post_async_login_work(vha, fcport, NULL);
  328. break;
  329. case MBS_LOOP_ID_USED:
  330. fcport->loop_id++;
  331. rval = qla2x00_find_new_loop_id(vha, fcport);
  332. if (rval != QLA_SUCCESS) {
  333. fcport->flags &= ~FCF_ASYNC_SENT;
  334. qla2x00_mark_device_lost(vha, fcport, 1, 0);
  335. break;
  336. }
  337. qla2x00_post_async_login_work(vha, fcport, NULL);
  338. break;
  339. }
  340. return;
  341. }
  342. void
  343. qla2x00_async_logout_done(struct scsi_qla_host *vha, fc_port_t *fcport,
  344. uint16_t *data)
  345. {
  346. qla2x00_mark_device_lost(vha, fcport, 1, 0);
  347. return;
  348. }
  349. void
  350. qla2x00_async_adisc_done(struct scsi_qla_host *vha, fc_port_t *fcport,
  351. uint16_t *data)
  352. {
  353. if (data[0] == MBS_COMMAND_COMPLETE) {
  354. qla2x00_update_fcport(vha, fcport);
  355. return;
  356. }
  357. /* Retry login. */
  358. fcport->flags &= ~FCF_ASYNC_SENT;
  359. if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
  360. set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
  361. else
  362. qla2x00_mark_device_lost(vha, fcport, 1, 0);
  363. return;
  364. }
  365. /****************************************************************************/
  366. /* QLogic ISP2x00 Hardware Support Functions. */
  367. /****************************************************************************/
  368. /*
  369. * qla2x00_initialize_adapter
  370. * Initialize board.
  371. *
  372. * Input:
  373. * ha = adapter block pointer.
  374. *
  375. * Returns:
  376. * 0 = success
  377. */
  378. int
  379. qla2x00_initialize_adapter(scsi_qla_host_t *vha)
  380. {
  381. int rval;
  382. struct qla_hw_data *ha = vha->hw;
  383. struct req_que *req = ha->req_q_map[0];
  384. /* Clear adapter flags. */
  385. vha->flags.online = 0;
  386. ha->flags.chip_reset_done = 0;
  387. vha->flags.reset_active = 0;
  388. ha->flags.pci_channel_io_perm_failure = 0;
  389. ha->flags.eeh_busy = 0;
  390. ha->flags.thermal_supported = 1;
  391. atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
  392. atomic_set(&vha->loop_state, LOOP_DOWN);
  393. vha->device_flags = DFLG_NO_CABLE;
  394. vha->dpc_flags = 0;
  395. vha->flags.management_server_logged_in = 0;
  396. vha->marker_needed = 0;
  397. ha->isp_abort_cnt = 0;
  398. ha->beacon_blink_led = 0;
  399. set_bit(0, ha->req_qid_map);
  400. set_bit(0, ha->rsp_qid_map);
  401. ql_dbg(ql_dbg_init, vha, 0x0040,
  402. "Configuring PCI space...\n");
  403. rval = ha->isp_ops->pci_config(vha);
  404. if (rval) {
  405. ql_log(ql_log_warn, vha, 0x0044,
  406. "Unable to configure PCI space.\n");
  407. return (rval);
  408. }
  409. ha->isp_ops->reset_chip(vha);
  410. rval = qla2xxx_get_flash_info(vha);
  411. if (rval) {
  412. ql_log(ql_log_fatal, vha, 0x004f,
  413. "Unable to validate FLASH data.\n");
  414. return (rval);
  415. }
  416. ha->isp_ops->get_flash_version(vha, req->ring);
  417. ql_dbg(ql_dbg_init, vha, 0x0061,
  418. "Configure NVRAM parameters...\n");
  419. ha->isp_ops->nvram_config(vha);
  420. if (ha->flags.disable_serdes) {
  421. /* Mask HBA via NVRAM settings? */
  422. ql_log(ql_log_info, vha, 0x0077,
  423. "Masking HBA WWPN "
  424. "%02x%02x%02x%02x%02x%02x%02x%02x (via NVRAM).\n",
  425. vha->port_name[0], vha->port_name[1],
  426. vha->port_name[2], vha->port_name[3],
  427. vha->port_name[4], vha->port_name[5],
  428. vha->port_name[6], vha->port_name[7]);
  429. return QLA_FUNCTION_FAILED;
  430. }
  431. ql_dbg(ql_dbg_init, vha, 0x0078,
  432. "Verifying loaded RISC code...\n");
  433. if (qla2x00_isp_firmware(vha) != QLA_SUCCESS) {
  434. rval = ha->isp_ops->chip_diag(vha);
  435. if (rval)
  436. return (rval);
  437. rval = qla2x00_setup_chip(vha);
  438. if (rval)
  439. return (rval);
  440. }
  441. if (IS_QLA84XX(ha)) {
  442. ha->cs84xx = qla84xx_get_chip(vha);
  443. if (!ha->cs84xx) {
  444. ql_log(ql_log_warn, vha, 0x00d0,
  445. "Unable to configure ISP84XX.\n");
  446. return QLA_FUNCTION_FAILED;
  447. }
  448. }
  449. if (qla_ini_mode_enabled(vha))
  450. rval = qla2x00_init_rings(vha);
  451. ha->flags.chip_reset_done = 1;
  452. if (rval == QLA_SUCCESS && IS_QLA84XX(ha)) {
  453. /* Issue verify 84xx FW IOCB to complete 84xx initialization */
  454. rval = qla84xx_init_chip(vha);
  455. if (rval != QLA_SUCCESS) {
  456. ql_log(ql_log_warn, vha, 0x00d4,
  457. "Unable to initialize ISP84XX.\n");
  458. qla84xx_put_chip(vha);
  459. }
  460. }
  461. if (IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha))
  462. qla24xx_read_fcp_prio_cfg(vha);
  463. return (rval);
  464. }
  465. /**
  466. * qla2100_pci_config() - Setup ISP21xx PCI configuration registers.
  467. * @ha: HA context
  468. *
  469. * Returns 0 on success.
  470. */
  471. int
  472. qla2100_pci_config(scsi_qla_host_t *vha)
  473. {
  474. uint16_t w;
  475. unsigned long flags;
  476. struct qla_hw_data *ha = vha->hw;
  477. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  478. pci_set_master(ha->pdev);
  479. pci_try_set_mwi(ha->pdev);
  480. pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
  481. w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
  482. pci_write_config_word(ha->pdev, PCI_COMMAND, w);
  483. pci_disable_rom(ha->pdev);
  484. /* Get PCI bus information. */
  485. spin_lock_irqsave(&ha->hardware_lock, flags);
  486. ha->pci_attr = RD_REG_WORD(&reg->ctrl_status);
  487. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  488. return QLA_SUCCESS;
  489. }
  490. /**
  491. * qla2300_pci_config() - Setup ISP23xx PCI configuration registers.
  492. * @ha: HA context
  493. *
  494. * Returns 0 on success.
  495. */
  496. int
  497. qla2300_pci_config(scsi_qla_host_t *vha)
  498. {
  499. uint16_t w;
  500. unsigned long flags = 0;
  501. uint32_t cnt;
  502. struct qla_hw_data *ha = vha->hw;
  503. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  504. pci_set_master(ha->pdev);
  505. pci_try_set_mwi(ha->pdev);
  506. pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
  507. w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
  508. if (IS_QLA2322(ha) || IS_QLA6322(ha))
  509. w &= ~PCI_COMMAND_INTX_DISABLE;
  510. pci_write_config_word(ha->pdev, PCI_COMMAND, w);
  511. /*
  512. * If this is a 2300 card and not 2312, reset the
  513. * COMMAND_INVALIDATE due to a bug in the 2300. Unfortunately,
  514. * the 2310 also reports itself as a 2300 so we need to get the
  515. * fb revision level -- a 6 indicates it really is a 2300 and
  516. * not a 2310.
  517. */
  518. if (IS_QLA2300(ha)) {
  519. spin_lock_irqsave(&ha->hardware_lock, flags);
  520. /* Pause RISC. */
  521. WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
  522. for (cnt = 0; cnt < 30000; cnt++) {
  523. if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) != 0)
  524. break;
  525. udelay(10);
  526. }
  527. /* Select FPM registers. */
  528. WRT_REG_WORD(&reg->ctrl_status, 0x20);
  529. RD_REG_WORD(&reg->ctrl_status);
  530. /* Get the fb rev level */
  531. ha->fb_rev = RD_FB_CMD_REG(ha, reg);
  532. if (ha->fb_rev == FPM_2300)
  533. pci_clear_mwi(ha->pdev);
  534. /* Deselect FPM registers. */
  535. WRT_REG_WORD(&reg->ctrl_status, 0x0);
  536. RD_REG_WORD(&reg->ctrl_status);
  537. /* Release RISC module. */
  538. WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
  539. for (cnt = 0; cnt < 30000; cnt++) {
  540. if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0)
  541. break;
  542. udelay(10);
  543. }
  544. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  545. }
  546. pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);
  547. pci_disable_rom(ha->pdev);
  548. /* Get PCI bus information. */
  549. spin_lock_irqsave(&ha->hardware_lock, flags);
  550. ha->pci_attr = RD_REG_WORD(&reg->ctrl_status);
  551. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  552. return QLA_SUCCESS;
  553. }
  554. /**
  555. * qla24xx_pci_config() - Setup ISP24xx PCI configuration registers.
  556. * @ha: HA context
  557. *
  558. * Returns 0 on success.
  559. */
  560. int
  561. qla24xx_pci_config(scsi_qla_host_t *vha)
  562. {
  563. uint16_t w;
  564. unsigned long flags = 0;
  565. struct qla_hw_data *ha = vha->hw;
  566. struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
  567. pci_set_master(ha->pdev);
  568. pci_try_set_mwi(ha->pdev);
  569. pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
  570. w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
  571. w &= ~PCI_COMMAND_INTX_DISABLE;
  572. pci_write_config_word(ha->pdev, PCI_COMMAND, w);
  573. pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);
  574. /* PCI-X -- adjust Maximum Memory Read Byte Count (2048). */
  575. if (pci_find_capability(ha->pdev, PCI_CAP_ID_PCIX))
  576. pcix_set_mmrbc(ha->pdev, 2048);
  577. /* PCIe -- adjust Maximum Read Request Size (2048). */
  578. if (pci_find_capability(ha->pdev, PCI_CAP_ID_EXP))
  579. pcie_set_readrq(ha->pdev, 2048);
  580. pci_disable_rom(ha->pdev);
  581. ha->chip_revision = ha->pdev->revision;
  582. /* Get PCI bus information. */
  583. spin_lock_irqsave(&ha->hardware_lock, flags);
  584. ha->pci_attr = RD_REG_DWORD(&reg->ctrl_status);
  585. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  586. return QLA_SUCCESS;
  587. }
  588. /**
  589. * qla25xx_pci_config() - Setup ISP25xx PCI configuration registers.
  590. * @ha: HA context
  591. *
  592. * Returns 0 on success.
  593. */
  594. int
  595. qla25xx_pci_config(scsi_qla_host_t *vha)
  596. {
  597. uint16_t w;
  598. struct qla_hw_data *ha = vha->hw;
  599. pci_set_master(ha->pdev);
  600. pci_try_set_mwi(ha->pdev);
  601. pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
  602. w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
  603. w &= ~PCI_COMMAND_INTX_DISABLE;
  604. pci_write_config_word(ha->pdev, PCI_COMMAND, w);
  605. /* PCIe -- adjust Maximum Read Request Size (2048). */
  606. if (pci_find_capability(ha->pdev, PCI_CAP_ID_EXP))
  607. pcie_set_readrq(ha->pdev, 2048);
  608. pci_disable_rom(ha->pdev);
  609. ha->chip_revision = ha->pdev->revision;
  610. return QLA_SUCCESS;
  611. }
  612. /**
  613. * qla2x00_isp_firmware() - Choose firmware image.
  614. * @ha: HA context
  615. *
  616. * Returns 0 on success.
  617. */
  618. static int
  619. qla2x00_isp_firmware(scsi_qla_host_t *vha)
  620. {
  621. int rval;
  622. uint16_t loop_id, topo, sw_cap;
  623. uint8_t domain, area, al_pa;
  624. struct qla_hw_data *ha = vha->hw;
  625. /* Assume loading risc code */
  626. rval = QLA_FUNCTION_FAILED;
  627. if (ha->flags.disable_risc_code_load) {
  628. ql_log(ql_log_info, vha, 0x0079, "RISC CODE NOT loaded.\n");
  629. /* Verify checksum of loaded RISC code. */
  630. rval = qla2x00_verify_checksum(vha, ha->fw_srisc_address);
  631. if (rval == QLA_SUCCESS) {
  632. /* And, verify we are not in ROM code. */
  633. rval = qla2x00_get_adapter_id(vha, &loop_id, &al_pa,
  634. &area, &domain, &topo, &sw_cap);
  635. }
  636. }
  637. if (rval)
  638. ql_dbg(ql_dbg_init, vha, 0x007a,
  639. "**** Load RISC code ****.\n");
  640. return (rval);
  641. }
  642. /**
  643. * qla2x00_reset_chip() - Reset ISP chip.
  644. * @ha: HA context
  645. *
  646. * Returns 0 on success.
  647. */
  648. void
  649. qla2x00_reset_chip(scsi_qla_host_t *vha)
  650. {
  651. unsigned long flags = 0;
  652. struct qla_hw_data *ha = vha->hw;
  653. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  654. uint32_t cnt;
  655. uint16_t cmd;
  656. if (unlikely(pci_channel_offline(ha->pdev)))
  657. return;
  658. ha->isp_ops->disable_intrs(ha);
  659. spin_lock_irqsave(&ha->hardware_lock, flags);
  660. /* Turn off master enable */
  661. cmd = 0;
  662. pci_read_config_word(ha->pdev, PCI_COMMAND, &cmd);
  663. cmd &= ~PCI_COMMAND_MASTER;
  664. pci_write_config_word(ha->pdev, PCI_COMMAND, cmd);
  665. if (!IS_QLA2100(ha)) {
  666. /* Pause RISC. */
  667. WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
  668. if (IS_QLA2200(ha) || IS_QLA2300(ha)) {
  669. for (cnt = 0; cnt < 30000; cnt++) {
  670. if ((RD_REG_WORD(&reg->hccr) &
  671. HCCR_RISC_PAUSE) != 0)
  672. break;
  673. udelay(100);
  674. }
  675. } else {
  676. RD_REG_WORD(&reg->hccr); /* PCI Posting. */
  677. udelay(10);
  678. }
  679. /* Select FPM registers. */
  680. WRT_REG_WORD(&reg->ctrl_status, 0x20);
  681. RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
  682. /* FPM Soft Reset. */
  683. WRT_REG_WORD(&reg->fpm_diag_config, 0x100);
  684. RD_REG_WORD(&reg->fpm_diag_config); /* PCI Posting. */
  685. /* Toggle Fpm Reset. */
  686. if (!IS_QLA2200(ha)) {
  687. WRT_REG_WORD(&reg->fpm_diag_config, 0x0);
  688. RD_REG_WORD(&reg->fpm_diag_config); /* PCI Posting. */
  689. }
  690. /* Select frame buffer registers. */
  691. WRT_REG_WORD(&reg->ctrl_status, 0x10);
  692. RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
  693. /* Reset frame buffer FIFOs. */
  694. if (IS_QLA2200(ha)) {
  695. WRT_FB_CMD_REG(ha, reg, 0xa000);
  696. RD_FB_CMD_REG(ha, reg); /* PCI Posting. */
  697. } else {
  698. WRT_FB_CMD_REG(ha, reg, 0x00fc);
  699. /* Read back fb_cmd until zero or 3 seconds max */
  700. for (cnt = 0; cnt < 3000; cnt++) {
  701. if ((RD_FB_CMD_REG(ha, reg) & 0xff) == 0)
  702. break;
  703. udelay(100);
  704. }
  705. }
  706. /* Select RISC module registers. */
  707. WRT_REG_WORD(&reg->ctrl_status, 0);
  708. RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
  709. /* Reset RISC processor. */
  710. WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
  711. RD_REG_WORD(&reg->hccr); /* PCI Posting. */
  712. /* Release RISC processor. */
  713. WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
  714. RD_REG_WORD(&reg->hccr); /* PCI Posting. */
  715. }
  716. WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
  717. WRT_REG_WORD(&reg->hccr, HCCR_CLR_HOST_INT);
  718. /* Reset ISP chip. */
  719. WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
  720. /* Wait for RISC to recover from reset. */
  721. if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
  722. /*
  723. * It is necessary to for a delay here since the card doesn't
  724. * respond to PCI reads during a reset. On some architectures
  725. * this will result in an MCA.
  726. */
  727. udelay(20);
  728. for (cnt = 30000; cnt; cnt--) {
  729. if ((RD_REG_WORD(&reg->ctrl_status) &
  730. CSR_ISP_SOFT_RESET) == 0)
  731. break;
  732. udelay(100);
  733. }
  734. } else
  735. udelay(10);
  736. /* Reset RISC processor. */
  737. WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
  738. WRT_REG_WORD(&reg->semaphore, 0);
  739. /* Release RISC processor. */
  740. WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
  741. RD_REG_WORD(&reg->hccr); /* PCI Posting. */
  742. if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
  743. for (cnt = 0; cnt < 30000; cnt++) {
  744. if (RD_MAILBOX_REG(ha, reg, 0) != MBS_BUSY)
  745. break;
  746. udelay(100);
  747. }
  748. } else
  749. udelay(100);
  750. /* Turn on master enable */
  751. cmd |= PCI_COMMAND_MASTER;
  752. pci_write_config_word(ha->pdev, PCI_COMMAND, cmd);
  753. /* Disable RISC pause on FPM parity error. */
  754. if (!IS_QLA2100(ha)) {
  755. WRT_REG_WORD(&reg->hccr, HCCR_DISABLE_PARITY_PAUSE);
  756. RD_REG_WORD(&reg->hccr); /* PCI Posting. */
  757. }
  758. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  759. }
  760. /**
  761. * qla81xx_reset_mpi() - Reset's MPI FW via Write MPI Register MBC.
  762. *
  763. * Returns 0 on success.
  764. */
  765. int
  766. qla81xx_reset_mpi(scsi_qla_host_t *vha)
  767. {
  768. uint16_t mb[4] = {0x1010, 0, 1, 0};
  769. if (!IS_QLA81XX(vha->hw))
  770. return QLA_SUCCESS;
  771. return qla81xx_write_mpi_register(vha, mb);
  772. }
  773. /**
  774. * qla24xx_reset_risc() - Perform full reset of ISP24xx RISC.
  775. * @ha: HA context
  776. *
  777. * Returns 0 on success.
  778. */
  779. static inline void
  780. qla24xx_reset_risc(scsi_qla_host_t *vha)
  781. {
  782. unsigned long flags = 0;
  783. struct qla_hw_data *ha = vha->hw;
  784. struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
  785. uint32_t cnt, d2;
  786. uint16_t wd;
  787. static int abts_cnt; /* ISP abort retry counts */
  788. spin_lock_irqsave(&ha->hardware_lock, flags);
  789. /* Reset RISC. */
  790. WRT_REG_DWORD(&reg->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
  791. for (cnt = 0; cnt < 30000; cnt++) {
  792. if ((RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE) == 0)
  793. break;
  794. udelay(10);
  795. }
  796. WRT_REG_DWORD(&reg->ctrl_status,
  797. CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
  798. pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
  799. udelay(100);
  800. /* Wait for firmware to complete NVRAM accesses. */
  801. d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
  802. for (cnt = 10000 ; cnt && d2; cnt--) {
  803. udelay(5);
  804. d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
  805. barrier();
  806. }
  807. /* Wait for soft-reset to complete. */
  808. d2 = RD_REG_DWORD(&reg->ctrl_status);
  809. for (cnt = 6000000 ; cnt && (d2 & CSRX_ISP_SOFT_RESET); cnt--) {
  810. udelay(5);
  811. d2 = RD_REG_DWORD(&reg->ctrl_status);
  812. barrier();
  813. }
  814. /* If required, do an MPI FW reset now */
  815. if (test_and_clear_bit(MPI_RESET_NEEDED, &vha->dpc_flags)) {
  816. if (qla81xx_reset_mpi(vha) != QLA_SUCCESS) {
  817. if (++abts_cnt < 5) {
  818. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  819. set_bit(MPI_RESET_NEEDED, &vha->dpc_flags);
  820. } else {
  821. /*
  822. * We exhausted the ISP abort retries. We have to
  823. * set the board offline.
  824. */
  825. abts_cnt = 0;
  826. vha->flags.online = 0;
  827. }
  828. }
  829. }
  830. WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
  831. RD_REG_DWORD(&reg->hccr);
  832. WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
  833. RD_REG_DWORD(&reg->hccr);
  834. WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_RESET);
  835. RD_REG_DWORD(&reg->hccr);
  836. d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
  837. for (cnt = 6000000 ; cnt && d2; cnt--) {
  838. udelay(5);
  839. d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
  840. barrier();
  841. }
  842. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  843. if (IS_NOPOLLING_TYPE(ha))
  844. ha->isp_ops->enable_intrs(ha);
  845. }
  846. /**
  847. * qla24xx_reset_chip() - Reset ISP24xx chip.
  848. * @ha: HA context
  849. *
  850. * Returns 0 on success.
  851. */
  852. void
  853. qla24xx_reset_chip(scsi_qla_host_t *vha)
  854. {
  855. struct qla_hw_data *ha = vha->hw;
  856. if (pci_channel_offline(ha->pdev) &&
  857. ha->flags.pci_channel_io_perm_failure) {
  858. return;
  859. }
  860. ha->isp_ops->disable_intrs(ha);
  861. /* Perform RISC reset. */
  862. qla24xx_reset_risc(vha);
  863. }
  864. /**
  865. * qla2x00_chip_diag() - Test chip for proper operation.
  866. * @ha: HA context
  867. *
  868. * Returns 0 on success.
  869. */
  870. int
  871. qla2x00_chip_diag(scsi_qla_host_t *vha)
  872. {
  873. int rval;
  874. struct qla_hw_data *ha = vha->hw;
  875. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  876. unsigned long flags = 0;
  877. uint16_t data;
  878. uint32_t cnt;
  879. uint16_t mb[5];
  880. struct req_que *req = ha->req_q_map[0];
  881. /* Assume a failed state */
  882. rval = QLA_FUNCTION_FAILED;
  883. ql_dbg(ql_dbg_init, vha, 0x007b,
  884. "Testing device at %lx.\n", (u_long)&reg->flash_address);
  885. spin_lock_irqsave(&ha->hardware_lock, flags);
  886. /* Reset ISP chip. */
  887. WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
  888. /*
  889. * We need to have a delay here since the card will not respond while
  890. * in reset causing an MCA on some architectures.
  891. */
  892. udelay(20);
  893. data = qla2x00_debounce_register(&reg->ctrl_status);
  894. for (cnt = 6000000 ; cnt && (data & CSR_ISP_SOFT_RESET); cnt--) {
  895. udelay(5);
  896. data = RD_REG_WORD(&reg->ctrl_status);
  897. barrier();
  898. }
  899. if (!cnt)
  900. goto chip_diag_failed;
  901. ql_dbg(ql_dbg_init, vha, 0x007c,
  902. "Reset register cleared by chip reset.\n");
  903. /* Reset RISC processor. */
  904. WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
  905. WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
  906. /* Workaround for QLA2312 PCI parity error */
  907. if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
  908. data = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 0));
  909. for (cnt = 6000000; cnt && (data == MBS_BUSY); cnt--) {
  910. udelay(5);
  911. data = RD_MAILBOX_REG(ha, reg, 0);
  912. barrier();
  913. }
  914. } else
  915. udelay(10);
  916. if (!cnt)
  917. goto chip_diag_failed;
  918. /* Check product ID of chip */
  919. ql_dbg(ql_dbg_init, vha, 0x007d, "Checking product Id of chip.\n");
  920. mb[1] = RD_MAILBOX_REG(ha, reg, 1);
  921. mb[2] = RD_MAILBOX_REG(ha, reg, 2);
  922. mb[3] = RD_MAILBOX_REG(ha, reg, 3);
  923. mb[4] = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 4));
  924. if (mb[1] != PROD_ID_1 || (mb[2] != PROD_ID_2 && mb[2] != PROD_ID_2a) ||
  925. mb[3] != PROD_ID_3) {
  926. ql_log(ql_log_warn, vha, 0x0062,
  927. "Wrong product ID = 0x%x,0x%x,0x%x.\n",
  928. mb[1], mb[2], mb[3]);
  929. goto chip_diag_failed;
  930. }
  931. ha->product_id[0] = mb[1];
  932. ha->product_id[1] = mb[2];
  933. ha->product_id[2] = mb[3];
  934. ha->product_id[3] = mb[4];
  935. /* Adjust fw RISC transfer size */
  936. if (req->length > 1024)
  937. ha->fw_transfer_size = REQUEST_ENTRY_SIZE * 1024;
  938. else
  939. ha->fw_transfer_size = REQUEST_ENTRY_SIZE *
  940. req->length;
  941. if (IS_QLA2200(ha) &&
  942. RD_MAILBOX_REG(ha, reg, 7) == QLA2200A_RISC_ROM_VER) {
  943. /* Limit firmware transfer size with a 2200A */
  944. ql_dbg(ql_dbg_init, vha, 0x007e, "Found QLA2200A Chip.\n");
  945. ha->device_type |= DT_ISP2200A;
  946. ha->fw_transfer_size = 128;
  947. }
  948. /* Wrap Incoming Mailboxes Test. */
  949. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  950. ql_dbg(ql_dbg_init, vha, 0x007f, "Checking mailboxes.\n");
  951. rval = qla2x00_mbx_reg_test(vha);
  952. if (rval)
  953. ql_log(ql_log_warn, vha, 0x0080,
  954. "Failed mailbox send register test.\n");
  955. else
  956. /* Flag a successful rval */
  957. rval = QLA_SUCCESS;
  958. spin_lock_irqsave(&ha->hardware_lock, flags);
  959. chip_diag_failed:
  960. if (rval)
  961. ql_log(ql_log_info, vha, 0x0081,
  962. "Chip diagnostics **** FAILED ****.\n");
  963. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  964. return (rval);
  965. }
  966. /**
  967. * qla24xx_chip_diag() - Test ISP24xx for proper operation.
  968. * @ha: HA context
  969. *
  970. * Returns 0 on success.
  971. */
  972. int
  973. qla24xx_chip_diag(scsi_qla_host_t *vha)
  974. {
  975. int rval;
  976. struct qla_hw_data *ha = vha->hw;
  977. struct req_que *req = ha->req_q_map[0];
  978. if (IS_QLA82XX(ha))
  979. return QLA_SUCCESS;
  980. ha->fw_transfer_size = REQUEST_ENTRY_SIZE * req->length;
  981. rval = qla2x00_mbx_reg_test(vha);
  982. if (rval) {
  983. ql_log(ql_log_warn, vha, 0x0082,
  984. "Failed mailbox send register test.\n");
  985. } else {
  986. /* Flag a successful rval */
  987. rval = QLA_SUCCESS;
  988. }
  989. return rval;
  990. }
  991. void
  992. qla2x00_alloc_fw_dump(scsi_qla_host_t *vha)
  993. {
  994. int rval;
  995. uint32_t dump_size, fixed_size, mem_size, req_q_size, rsp_q_size,
  996. eft_size, fce_size, mq_size;
  997. dma_addr_t tc_dma;
  998. void *tc;
  999. struct qla_hw_data *ha = vha->hw;
  1000. struct req_que *req = ha->req_q_map[0];
  1001. struct rsp_que *rsp = ha->rsp_q_map[0];
  1002. if (ha->fw_dump) {
  1003. ql_dbg(ql_dbg_init, vha, 0x00bd,
  1004. "Firmware dump already allocated.\n");
  1005. return;
  1006. }
  1007. ha->fw_dumped = 0;
  1008. fixed_size = mem_size = eft_size = fce_size = mq_size = 0;
  1009. if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
  1010. fixed_size = sizeof(struct qla2100_fw_dump);
  1011. } else if (IS_QLA23XX(ha)) {
  1012. fixed_size = offsetof(struct qla2300_fw_dump, data_ram);
  1013. mem_size = (ha->fw_memory_size - 0x11000 + 1) *
  1014. sizeof(uint16_t);
  1015. } else if (IS_FWI2_CAPABLE(ha)) {
  1016. if (IS_QLA83XX(ha))
  1017. fixed_size = offsetof(struct qla83xx_fw_dump, ext_mem);
  1018. else if (IS_QLA81XX(ha))
  1019. fixed_size = offsetof(struct qla81xx_fw_dump, ext_mem);
  1020. else if (IS_QLA25XX(ha))
  1021. fixed_size = offsetof(struct qla25xx_fw_dump, ext_mem);
  1022. else
  1023. fixed_size = offsetof(struct qla24xx_fw_dump, ext_mem);
  1024. mem_size = (ha->fw_memory_size - 0x100000 + 1) *
  1025. sizeof(uint32_t);
  1026. if (ha->mqenable) {
  1027. if (!IS_QLA83XX(ha))
  1028. mq_size = sizeof(struct qla2xxx_mq_chain);
  1029. /*
  1030. * Allocate maximum buffer size for all queues.
  1031. * Resizing must be done at end-of-dump processing.
  1032. */
  1033. mq_size += ha->max_req_queues *
  1034. (req->length * sizeof(request_t));
  1035. mq_size += ha->max_rsp_queues *
  1036. (rsp->length * sizeof(response_t));
  1037. }
  1038. if (ha->tgt.atio_q_length)
  1039. mq_size += ha->tgt.atio_q_length * sizeof(request_t);
  1040. /* Allocate memory for Fibre Channel Event Buffer. */
  1041. if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha) && !IS_QLA83XX(ha))
  1042. goto try_eft;
  1043. tc = dma_alloc_coherent(&ha->pdev->dev, FCE_SIZE, &tc_dma,
  1044. GFP_KERNEL);
  1045. if (!tc) {
  1046. ql_log(ql_log_warn, vha, 0x00be,
  1047. "Unable to allocate (%d KB) for FCE.\n",
  1048. FCE_SIZE / 1024);
  1049. goto try_eft;
  1050. }
  1051. memset(tc, 0, FCE_SIZE);
  1052. rval = qla2x00_enable_fce_trace(vha, tc_dma, FCE_NUM_BUFFERS,
  1053. ha->fce_mb, &ha->fce_bufs);
  1054. if (rval) {
  1055. ql_log(ql_log_warn, vha, 0x00bf,
  1056. "Unable to initialize FCE (%d).\n", rval);
  1057. dma_free_coherent(&ha->pdev->dev, FCE_SIZE, tc,
  1058. tc_dma);
  1059. ha->flags.fce_enabled = 0;
  1060. goto try_eft;
  1061. }
  1062. ql_dbg(ql_dbg_init, vha, 0x00c0,
  1063. "Allocate (%d KB) for FCE...\n", FCE_SIZE / 1024);
  1064. fce_size = sizeof(struct qla2xxx_fce_chain) + FCE_SIZE;
  1065. ha->flags.fce_enabled = 1;
  1066. ha->fce_dma = tc_dma;
  1067. ha->fce = tc;
  1068. try_eft:
  1069. /* Allocate memory for Extended Trace Buffer. */
  1070. tc = dma_alloc_coherent(&ha->pdev->dev, EFT_SIZE, &tc_dma,
  1071. GFP_KERNEL);
  1072. if (!tc) {
  1073. ql_log(ql_log_warn, vha, 0x00c1,
  1074. "Unable to allocate (%d KB) for EFT.\n",
  1075. EFT_SIZE / 1024);
  1076. goto cont_alloc;
  1077. }
  1078. memset(tc, 0, EFT_SIZE);
  1079. rval = qla2x00_enable_eft_trace(vha, tc_dma, EFT_NUM_BUFFERS);
  1080. if (rval) {
  1081. ql_log(ql_log_warn, vha, 0x00c2,
  1082. "Unable to initialize EFT (%d).\n", rval);
  1083. dma_free_coherent(&ha->pdev->dev, EFT_SIZE, tc,
  1084. tc_dma);
  1085. goto cont_alloc;
  1086. }
  1087. ql_dbg(ql_dbg_init, vha, 0x00c3,
  1088. "Allocated (%d KB) EFT ...\n", EFT_SIZE / 1024);
  1089. eft_size = EFT_SIZE;
  1090. ha->eft_dma = tc_dma;
  1091. ha->eft = tc;
  1092. }
  1093. cont_alloc:
  1094. req_q_size = req->length * sizeof(request_t);
  1095. rsp_q_size = rsp->length * sizeof(response_t);
  1096. dump_size = offsetof(struct qla2xxx_fw_dump, isp);
  1097. dump_size += fixed_size + mem_size + req_q_size + rsp_q_size + eft_size;
  1098. ha->chain_offset = dump_size;
  1099. dump_size += mq_size + fce_size;
  1100. ha->fw_dump = vmalloc(dump_size);
  1101. if (!ha->fw_dump) {
  1102. ql_log(ql_log_warn, vha, 0x00c4,
  1103. "Unable to allocate (%d KB) for firmware dump.\n",
  1104. dump_size / 1024);
  1105. if (ha->fce) {
  1106. dma_free_coherent(&ha->pdev->dev, FCE_SIZE, ha->fce,
  1107. ha->fce_dma);
  1108. ha->fce = NULL;
  1109. ha->fce_dma = 0;
  1110. }
  1111. if (ha->eft) {
  1112. dma_free_coherent(&ha->pdev->dev, eft_size, ha->eft,
  1113. ha->eft_dma);
  1114. ha->eft = NULL;
  1115. ha->eft_dma = 0;
  1116. }
  1117. return;
  1118. }
  1119. ql_dbg(ql_dbg_init, vha, 0x00c5,
  1120. "Allocated (%d KB) for firmware dump.\n", dump_size / 1024);
  1121. ha->fw_dump_len = dump_size;
  1122. ha->fw_dump->signature[0] = 'Q';
  1123. ha->fw_dump->signature[1] = 'L';
  1124. ha->fw_dump->signature[2] = 'G';
  1125. ha->fw_dump->signature[3] = 'C';
  1126. ha->fw_dump->version = __constant_htonl(1);
  1127. ha->fw_dump->fixed_size = htonl(fixed_size);
  1128. ha->fw_dump->mem_size = htonl(mem_size);
  1129. ha->fw_dump->req_q_size = htonl(req_q_size);
  1130. ha->fw_dump->rsp_q_size = htonl(rsp_q_size);
  1131. ha->fw_dump->eft_size = htonl(eft_size);
  1132. ha->fw_dump->eft_addr_l = htonl(LSD(ha->eft_dma));
  1133. ha->fw_dump->eft_addr_h = htonl(MSD(ha->eft_dma));
  1134. ha->fw_dump->header_size =
  1135. htonl(offsetof(struct qla2xxx_fw_dump, isp));
  1136. }
  1137. static int
  1138. qla81xx_mpi_sync(scsi_qla_host_t *vha)
  1139. {
  1140. #define MPS_MASK 0xe0
  1141. int rval;
  1142. uint16_t dc;
  1143. uint32_t dw;
  1144. if (!IS_QLA81XX(vha->hw))
  1145. return QLA_SUCCESS;
  1146. rval = qla2x00_write_ram_word(vha, 0x7c00, 1);
  1147. if (rval != QLA_SUCCESS) {
  1148. ql_log(ql_log_warn, vha, 0x0105,
  1149. "Unable to acquire semaphore.\n");
  1150. goto done;
  1151. }
  1152. pci_read_config_word(vha->hw->pdev, 0x54, &dc);
  1153. rval = qla2x00_read_ram_word(vha, 0x7a15, &dw);
  1154. if (rval != QLA_SUCCESS) {
  1155. ql_log(ql_log_warn, vha, 0x0067, "Unable to read sync.\n");
  1156. goto done_release;
  1157. }
  1158. dc &= MPS_MASK;
  1159. if (dc == (dw & MPS_MASK))
  1160. goto done_release;
  1161. dw &= ~MPS_MASK;
  1162. dw |= dc;
  1163. rval = qla2x00_write_ram_word(vha, 0x7a15, dw);
  1164. if (rval != QLA_SUCCESS) {
  1165. ql_log(ql_log_warn, vha, 0x0114, "Unable to gain sync.\n");
  1166. }
  1167. done_release:
  1168. rval = qla2x00_write_ram_word(vha, 0x7c00, 0);
  1169. if (rval != QLA_SUCCESS) {
  1170. ql_log(ql_log_warn, vha, 0x006d,
  1171. "Unable to release semaphore.\n");
  1172. }
  1173. done:
  1174. return rval;
  1175. }
  1176. /**
  1177. * qla2x00_setup_chip() - Load and start RISC firmware.
  1178. * @ha: HA context
  1179. *
  1180. * Returns 0 on success.
  1181. */
  1182. static int
  1183. qla2x00_setup_chip(scsi_qla_host_t *vha)
  1184. {
  1185. int rval;
  1186. uint32_t srisc_address = 0;
  1187. struct qla_hw_data *ha = vha->hw;
  1188. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  1189. unsigned long flags;
  1190. uint16_t fw_major_version;
  1191. if (IS_QLA82XX(ha)) {
  1192. rval = ha->isp_ops->load_risc(vha, &srisc_address);
  1193. if (rval == QLA_SUCCESS) {
  1194. qla2x00_stop_firmware(vha);
  1195. goto enable_82xx_npiv;
  1196. } else
  1197. goto failed;
  1198. }
  1199. if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) {
  1200. /* Disable SRAM, Instruction RAM and GP RAM parity. */
  1201. spin_lock_irqsave(&ha->hardware_lock, flags);
  1202. WRT_REG_WORD(&reg->hccr, (HCCR_ENABLE_PARITY + 0x0));
  1203. RD_REG_WORD(&reg->hccr);
  1204. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  1205. }
  1206. qla81xx_mpi_sync(vha);
  1207. /* Load firmware sequences */
  1208. rval = ha->isp_ops->load_risc(vha, &srisc_address);
  1209. if (rval == QLA_SUCCESS) {
  1210. ql_dbg(ql_dbg_init, vha, 0x00c9,
  1211. "Verifying Checksum of loaded RISC code.\n");
  1212. rval = qla2x00_verify_checksum(vha, srisc_address);
  1213. if (rval == QLA_SUCCESS) {
  1214. /* Start firmware execution. */
  1215. ql_dbg(ql_dbg_init, vha, 0x00ca,
  1216. "Starting firmware.\n");
  1217. rval = qla2x00_execute_fw(vha, srisc_address);
  1218. /* Retrieve firmware information. */
  1219. if (rval == QLA_SUCCESS) {
  1220. enable_82xx_npiv:
  1221. fw_major_version = ha->fw_major_version;
  1222. if (IS_QLA82XX(ha))
  1223. qla82xx_check_md_needed(vha);
  1224. else
  1225. rval = qla2x00_get_fw_version(vha);
  1226. if (rval != QLA_SUCCESS)
  1227. goto failed;
  1228. ha->flags.npiv_supported = 0;
  1229. if (IS_QLA2XXX_MIDTYPE(ha) &&
  1230. (ha->fw_attributes & BIT_2)) {
  1231. ha->flags.npiv_supported = 1;
  1232. if ((!ha->max_npiv_vports) ||
  1233. ((ha->max_npiv_vports + 1) %
  1234. MIN_MULTI_ID_FABRIC))
  1235. ha->max_npiv_vports =
  1236. MIN_MULTI_ID_FABRIC - 1;
  1237. }
  1238. qla2x00_get_resource_cnts(vha, NULL,
  1239. &ha->fw_xcb_count, NULL, NULL,
  1240. &ha->max_npiv_vports, NULL);
  1241. if (!fw_major_version && ql2xallocfwdump
  1242. && !IS_QLA82XX(ha))
  1243. qla2x00_alloc_fw_dump(vha);
  1244. }
  1245. } else {
  1246. ql_log(ql_log_fatal, vha, 0x00cd,
  1247. "ISP Firmware failed checksum.\n");
  1248. goto failed;
  1249. }
  1250. }
  1251. if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) {
  1252. /* Enable proper parity. */
  1253. spin_lock_irqsave(&ha->hardware_lock, flags);
  1254. if (IS_QLA2300(ha))
  1255. /* SRAM parity */
  1256. WRT_REG_WORD(&reg->hccr, HCCR_ENABLE_PARITY + 0x1);
  1257. else
  1258. /* SRAM, Instruction RAM and GP RAM parity */
  1259. WRT_REG_WORD(&reg->hccr, HCCR_ENABLE_PARITY + 0x7);
  1260. RD_REG_WORD(&reg->hccr);
  1261. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  1262. }
  1263. if (IS_QLA83XX(ha))
  1264. goto skip_fac_check;
  1265. if (rval == QLA_SUCCESS && IS_FAC_REQUIRED(ha)) {
  1266. uint32_t size;
  1267. rval = qla81xx_fac_get_sector_size(vha, &size);
  1268. if (rval == QLA_SUCCESS) {
  1269. ha->flags.fac_supported = 1;
  1270. ha->fdt_block_size = size << 2;
  1271. } else {
  1272. ql_log(ql_log_warn, vha, 0x00ce,
  1273. "Unsupported FAC firmware (%d.%02d.%02d).\n",
  1274. ha->fw_major_version, ha->fw_minor_version,
  1275. ha->fw_subminor_version);
  1276. skip_fac_check:
  1277. if (IS_QLA83XX(ha)) {
  1278. ha->flags.fac_supported = 0;
  1279. rval = QLA_SUCCESS;
  1280. }
  1281. }
  1282. }
  1283. failed:
  1284. if (rval) {
  1285. ql_log(ql_log_fatal, vha, 0x00cf,
  1286. "Setup chip ****FAILED****.\n");
  1287. }
  1288. return (rval);
  1289. }
  1290. /**
  1291. * qla2x00_init_response_q_entries() - Initializes response queue entries.
  1292. * @ha: HA context
  1293. *
  1294. * Beginning of request ring has initialization control block already built
  1295. * by nvram config routine.
  1296. *
  1297. * Returns 0 on success.
  1298. */
  1299. void
  1300. qla2x00_init_response_q_entries(struct rsp_que *rsp)
  1301. {
  1302. uint16_t cnt;
  1303. response_t *pkt;
  1304. rsp->ring_ptr = rsp->ring;
  1305. rsp->ring_index = 0;
  1306. rsp->status_srb = NULL;
  1307. pkt = rsp->ring_ptr;
  1308. for (cnt = 0; cnt < rsp->length; cnt++) {
  1309. pkt->signature = RESPONSE_PROCESSED;
  1310. pkt++;
  1311. }
  1312. }
  1313. /**
  1314. * qla2x00_update_fw_options() - Read and process firmware options.
  1315. * @ha: HA context
  1316. *
  1317. * Returns 0 on success.
  1318. */
  1319. void
  1320. qla2x00_update_fw_options(scsi_qla_host_t *vha)
  1321. {
  1322. uint16_t swing, emphasis, tx_sens, rx_sens;
  1323. struct qla_hw_data *ha = vha->hw;
  1324. memset(ha->fw_options, 0, sizeof(ha->fw_options));
  1325. qla2x00_get_fw_options(vha, ha->fw_options);
  1326. if (IS_QLA2100(ha) || IS_QLA2200(ha))
  1327. return;
  1328. /* Serial Link options. */
  1329. ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0115,
  1330. "Serial link options.\n");
  1331. ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0109,
  1332. (uint8_t *)&ha->fw_seriallink_options,
  1333. sizeof(ha->fw_seriallink_options));
  1334. ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
  1335. if (ha->fw_seriallink_options[3] & BIT_2) {
  1336. ha->fw_options[1] |= FO1_SET_EMPHASIS_SWING;
  1337. /* 1G settings */
  1338. swing = ha->fw_seriallink_options[2] & (BIT_2 | BIT_1 | BIT_0);
  1339. emphasis = (ha->fw_seriallink_options[2] &
  1340. (BIT_4 | BIT_3)) >> 3;
  1341. tx_sens = ha->fw_seriallink_options[0] &
  1342. (BIT_3 | BIT_2 | BIT_1 | BIT_0);
  1343. rx_sens = (ha->fw_seriallink_options[0] &
  1344. (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4;
  1345. ha->fw_options[10] = (emphasis << 14) | (swing << 8);
  1346. if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
  1347. if (rx_sens == 0x0)
  1348. rx_sens = 0x3;
  1349. ha->fw_options[10] |= (tx_sens << 4) | rx_sens;
  1350. } else if (IS_QLA2322(ha) || IS_QLA6322(ha))
  1351. ha->fw_options[10] |= BIT_5 |
  1352. ((rx_sens & (BIT_1 | BIT_0)) << 2) |
  1353. (tx_sens & (BIT_1 | BIT_0));
  1354. /* 2G settings */
  1355. swing = (ha->fw_seriallink_options[2] &
  1356. (BIT_7 | BIT_6 | BIT_5)) >> 5;
  1357. emphasis = ha->fw_seriallink_options[3] & (BIT_1 | BIT_0);
  1358. tx_sens = ha->fw_seriallink_options[1] &
  1359. (BIT_3 | BIT_2 | BIT_1 | BIT_0);
  1360. rx_sens = (ha->fw_seriallink_options[1] &
  1361. (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4;
  1362. ha->fw_options[11] = (emphasis << 14) | (swing << 8);
  1363. if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
  1364. if (rx_sens == 0x0)
  1365. rx_sens = 0x3;
  1366. ha->fw_options[11] |= (tx_sens << 4) | rx_sens;
  1367. } else if (IS_QLA2322(ha) || IS_QLA6322(ha))
  1368. ha->fw_options[11] |= BIT_5 |
  1369. ((rx_sens & (BIT_1 | BIT_0)) << 2) |
  1370. (tx_sens & (BIT_1 | BIT_0));
  1371. }
  1372. /* FCP2 options. */
  1373. /* Return command IOCBs without waiting for an ABTS to complete. */
  1374. ha->fw_options[3] |= BIT_13;
  1375. /* LED scheme. */
  1376. if (ha->flags.enable_led_scheme)
  1377. ha->fw_options[2] |= BIT_12;
  1378. /* Detect ISP6312. */
  1379. if (IS_QLA6312(ha))
  1380. ha->fw_options[2] |= BIT_13;
  1381. /* Update firmware options. */
  1382. qla2x00_set_fw_options(vha, ha->fw_options);
  1383. }
  1384. void
  1385. qla24xx_update_fw_options(scsi_qla_host_t *vha)
  1386. {
  1387. int rval;
  1388. struct qla_hw_data *ha = vha->hw;
  1389. if (IS_QLA82XX(ha))
  1390. return;
  1391. /* Update Serial Link options. */
  1392. if ((le16_to_cpu(ha->fw_seriallink_options24[0]) & BIT_0) == 0)
  1393. return;
  1394. rval = qla2x00_set_serdes_params(vha,
  1395. le16_to_cpu(ha->fw_seriallink_options24[1]),
  1396. le16_to_cpu(ha->fw_seriallink_options24[2]),
  1397. le16_to_cpu(ha->fw_seriallink_options24[3]));
  1398. if (rval != QLA_SUCCESS) {
  1399. ql_log(ql_log_warn, vha, 0x0104,
  1400. "Unable to update Serial Link options (%x).\n", rval);
  1401. }
  1402. }
  1403. void
  1404. qla2x00_config_rings(struct scsi_qla_host *vha)
  1405. {
  1406. struct qla_hw_data *ha = vha->hw;
  1407. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  1408. struct req_que *req = ha->req_q_map[0];
  1409. struct rsp_que *rsp = ha->rsp_q_map[0];
  1410. /* Setup ring parameters in initialization control block. */
  1411. ha->init_cb->request_q_outpointer = __constant_cpu_to_le16(0);
  1412. ha->init_cb->response_q_inpointer = __constant_cpu_to_le16(0);
  1413. ha->init_cb->request_q_length = cpu_to_le16(req->length);
  1414. ha->init_cb->response_q_length = cpu_to_le16(rsp->length);
  1415. ha->init_cb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
  1416. ha->init_cb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
  1417. ha->init_cb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
  1418. ha->init_cb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
  1419. WRT_REG_WORD(ISP_REQ_Q_IN(ha, reg), 0);
  1420. WRT_REG_WORD(ISP_REQ_Q_OUT(ha, reg), 0);
  1421. WRT_REG_WORD(ISP_RSP_Q_IN(ha, reg), 0);
  1422. WRT_REG_WORD(ISP_RSP_Q_OUT(ha, reg), 0);
  1423. RD_REG_WORD(ISP_RSP_Q_OUT(ha, reg)); /* PCI Posting. */
  1424. }
  1425. void
  1426. qla24xx_config_rings(struct scsi_qla_host *vha)
  1427. {
  1428. struct qla_hw_data *ha = vha->hw;
  1429. device_reg_t __iomem *reg = ISP_QUE_REG(ha, 0);
  1430. struct device_reg_2xxx __iomem *ioreg = &ha->iobase->isp;
  1431. struct qla_msix_entry *msix;
  1432. struct init_cb_24xx *icb;
  1433. uint16_t rid = 0;
  1434. struct req_que *req = ha->req_q_map[0];
  1435. struct rsp_que *rsp = ha->rsp_q_map[0];
  1436. /* Setup ring parameters in initialization control block. */
  1437. icb = (struct init_cb_24xx *)ha->init_cb;
  1438. icb->request_q_outpointer = __constant_cpu_to_le16(0);
  1439. icb->response_q_inpointer = __constant_cpu_to_le16(0);
  1440. icb->request_q_length = cpu_to_le16(req->length);
  1441. icb->response_q_length = cpu_to_le16(rsp->length);
  1442. icb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
  1443. icb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
  1444. icb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
  1445. icb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
  1446. /* Setup ATIO queue dma pointers for target mode */
  1447. icb->atio_q_inpointer = __constant_cpu_to_le16(0);
  1448. icb->atio_q_length = cpu_to_le16(ha->tgt.atio_q_length);
  1449. icb->atio_q_address[0] = cpu_to_le32(LSD(ha->tgt.atio_dma));
  1450. icb->atio_q_address[1] = cpu_to_le32(MSD(ha->tgt.atio_dma));
  1451. if (ha->mqenable || IS_QLA83XX(ha)) {
  1452. icb->qos = __constant_cpu_to_le16(QLA_DEFAULT_QUE_QOS);
  1453. icb->rid = __constant_cpu_to_le16(rid);
  1454. if (ha->flags.msix_enabled) {
  1455. msix = &ha->msix_entries[1];
  1456. ql_dbg(ql_dbg_init, vha, 0x00fd,
  1457. "Registering vector 0x%x for base que.\n",
  1458. msix->entry);
  1459. icb->msix = cpu_to_le16(msix->entry);
  1460. }
  1461. /* Use alternate PCI bus number */
  1462. if (MSB(rid))
  1463. icb->firmware_options_2 |=
  1464. __constant_cpu_to_le32(BIT_19);
  1465. /* Use alternate PCI devfn */
  1466. if (LSB(rid))
  1467. icb->firmware_options_2 |=
  1468. __constant_cpu_to_le32(BIT_18);
  1469. /* Use Disable MSIX Handshake mode for capable adapters */
  1470. if ((ha->fw_attributes & BIT_6) && (IS_MSIX_NACK_CAPABLE(ha)) &&
  1471. (ha->flags.msix_enabled)) {
  1472. icb->firmware_options_2 &=
  1473. __constant_cpu_to_le32(~BIT_22);
  1474. ha->flags.disable_msix_handshake = 1;
  1475. ql_dbg(ql_dbg_init, vha, 0x00fe,
  1476. "MSIX Handshake Disable Mode turned on.\n");
  1477. } else {
  1478. icb->firmware_options_2 |=
  1479. __constant_cpu_to_le32(BIT_22);
  1480. }
  1481. icb->firmware_options_2 |= __constant_cpu_to_le32(BIT_23);
  1482. WRT_REG_DWORD(&reg->isp25mq.req_q_in, 0);
  1483. WRT_REG_DWORD(&reg->isp25mq.req_q_out, 0);
  1484. WRT_REG_DWORD(&reg->isp25mq.rsp_q_in, 0);
  1485. WRT_REG_DWORD(&reg->isp25mq.rsp_q_out, 0);
  1486. } else {
  1487. WRT_REG_DWORD(&reg->isp24.req_q_in, 0);
  1488. WRT_REG_DWORD(&reg->isp24.req_q_out, 0);
  1489. WRT_REG_DWORD(&reg->isp24.rsp_q_in, 0);
  1490. WRT_REG_DWORD(&reg->isp24.rsp_q_out, 0);
  1491. }
  1492. qlt_24xx_config_rings(vha, reg);
  1493. /* PCI posting */
  1494. RD_REG_DWORD(&ioreg->hccr);
  1495. }
  1496. /**
  1497. * qla2x00_init_rings() - Initializes firmware.
  1498. * @ha: HA context
  1499. *
  1500. * Beginning of request ring has initialization control block already built
  1501. * by nvram config routine.
  1502. *
  1503. * Returns 0 on success.
  1504. */
  1505. static int
  1506. qla2x00_init_rings(scsi_qla_host_t *vha)
  1507. {
  1508. int rval;
  1509. unsigned long flags = 0;
  1510. int cnt, que;
  1511. struct qla_hw_data *ha = vha->hw;
  1512. struct req_que *req;
  1513. struct rsp_que *rsp;
  1514. struct mid_init_cb_24xx *mid_init_cb =
  1515. (struct mid_init_cb_24xx *) ha->init_cb;
  1516. spin_lock_irqsave(&ha->hardware_lock, flags);
  1517. /* Clear outstanding commands array. */
  1518. for (que = 0; que < ha->max_req_queues; que++) {
  1519. req = ha->req_q_map[que];
  1520. if (!req)
  1521. continue;
  1522. for (cnt = 1; cnt < MAX_OUTSTANDING_COMMANDS; cnt++)
  1523. req->outstanding_cmds[cnt] = NULL;
  1524. req->current_outstanding_cmd = 1;
  1525. /* Initialize firmware. */
  1526. req->ring_ptr = req->ring;
  1527. req->ring_index = 0;
  1528. req->cnt = req->length;
  1529. }
  1530. for (que = 0; que < ha->max_rsp_queues; que++) {
  1531. rsp = ha->rsp_q_map[que];
  1532. if (!rsp)
  1533. continue;
  1534. /* Initialize response queue entries */
  1535. qla2x00_init_response_q_entries(rsp);
  1536. }
  1537. spin_lock(&ha->vport_slock);
  1538. spin_unlock(&ha->vport_slock);
  1539. ha->tgt.atio_ring_ptr = ha->tgt.atio_ring;
  1540. ha->tgt.atio_ring_index = 0;
  1541. /* Initialize ATIO queue entries */
  1542. qlt_init_atio_q_entries(vha);
  1543. ha->isp_ops->config_rings(vha);
  1544. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  1545. /* Update any ISP specific firmware options before initialization. */
  1546. ha->isp_ops->update_fw_options(vha);
  1547. ql_dbg(ql_dbg_init, vha, 0x00d1, "Issue init firmware.\n");
  1548. if (ha->flags.npiv_supported) {
  1549. if (ha->operating_mode == LOOP)
  1550. ha->max_npiv_vports = MIN_MULTI_ID_FABRIC - 1;
  1551. mid_init_cb->count = cpu_to_le16(ha->max_npiv_vports);
  1552. }
  1553. if (IS_FWI2_CAPABLE(ha)) {
  1554. mid_init_cb->options = __constant_cpu_to_le16(BIT_1);
  1555. mid_init_cb->init_cb.execution_throttle =
  1556. cpu_to_le16(ha->fw_xcb_count);
  1557. }
  1558. rval = qla2x00_init_firmware(vha, ha->init_cb_size);
  1559. if (rval) {
  1560. ql_log(ql_log_fatal, vha, 0x00d2,
  1561. "Init Firmware **** FAILED ****.\n");
  1562. } else {
  1563. ql_dbg(ql_dbg_init, vha, 0x00d3,
  1564. "Init Firmware -- success.\n");
  1565. }
  1566. return (rval);
  1567. }
  1568. /**
  1569. * qla2x00_fw_ready() - Waits for firmware ready.
  1570. * @ha: HA context
  1571. *
  1572. * Returns 0 on success.
  1573. */
  1574. static int
  1575. qla2x00_fw_ready(scsi_qla_host_t *vha)
  1576. {
  1577. int rval;
  1578. unsigned long wtime, mtime, cs84xx_time;
  1579. uint16_t min_wait; /* Minimum wait time if loop is down */
  1580. uint16_t wait_time; /* Wait time if loop is coming ready */
  1581. uint16_t state[5];
  1582. struct qla_hw_data *ha = vha->hw;
  1583. rval = QLA_SUCCESS;
  1584. /* 20 seconds for loop down. */
  1585. min_wait = 20;
  1586. /*
  1587. * Firmware should take at most one RATOV to login, plus 5 seconds for
  1588. * our own processing.
  1589. */
  1590. if ((wait_time = (ha->retry_count*ha->login_timeout) + 5) < min_wait) {
  1591. wait_time = min_wait;
  1592. }
  1593. /* Min wait time if loop down */
  1594. mtime = jiffies + (min_wait * HZ);
  1595. /* wait time before firmware ready */
  1596. wtime = jiffies + (wait_time * HZ);
  1597. /* Wait for ISP to finish LIP */
  1598. if (!vha->flags.init_done)
  1599. ql_log(ql_log_info, vha, 0x801e,
  1600. "Waiting for LIP to complete.\n");
  1601. do {
  1602. rval = qla2x00_get_firmware_state(vha, state);
  1603. if (rval == QLA_SUCCESS) {
  1604. if (state[0] < FSTATE_LOSS_OF_SYNC) {
  1605. vha->device_flags &= ~DFLG_NO_CABLE;
  1606. }
  1607. if (IS_QLA84XX(ha) && state[0] != FSTATE_READY) {
  1608. ql_dbg(ql_dbg_taskm, vha, 0x801f,
  1609. "fw_state=%x 84xx=%x.\n", state[0],
  1610. state[2]);
  1611. if ((state[2] & FSTATE_LOGGED_IN) &&
  1612. (state[2] & FSTATE_WAITING_FOR_VERIFY)) {
  1613. ql_dbg(ql_dbg_taskm, vha, 0x8028,
  1614. "Sending verify iocb.\n");
  1615. cs84xx_time = jiffies;
  1616. rval = qla84xx_init_chip(vha);
  1617. if (rval != QLA_SUCCESS) {
  1618. ql_log(ql_log_warn,
  1619. vha, 0x8007,
  1620. "Init chip failed.\n");
  1621. break;
  1622. }
  1623. /* Add time taken to initialize. */
  1624. cs84xx_time = jiffies - cs84xx_time;
  1625. wtime += cs84xx_time;
  1626. mtime += cs84xx_time;
  1627. ql_dbg(ql_dbg_taskm, vha, 0x8008,
  1628. "Increasing wait time by %ld. "
  1629. "New time %ld.\n", cs84xx_time,
  1630. wtime);
  1631. }
  1632. } else if (state[0] == FSTATE_READY) {
  1633. ql_dbg(ql_dbg_taskm, vha, 0x8037,
  1634. "F/W Ready - OK.\n");
  1635. qla2x00_get_retry_cnt(vha, &ha->retry_count,
  1636. &ha->login_timeout, &ha->r_a_tov);
  1637. rval = QLA_SUCCESS;
  1638. break;
  1639. }
  1640. rval = QLA_FUNCTION_FAILED;
  1641. if (atomic_read(&vha->loop_down_timer) &&
  1642. state[0] != FSTATE_READY) {
  1643. /* Loop down. Timeout on min_wait for states
  1644. * other than Wait for Login.
  1645. */
  1646. if (time_after_eq(jiffies, mtime)) {
  1647. ql_log(ql_log_info, vha, 0x8038,
  1648. "Cable is unplugged...\n");
  1649. vha->device_flags |= DFLG_NO_CABLE;
  1650. break;
  1651. }
  1652. }
  1653. } else {
  1654. /* Mailbox cmd failed. Timeout on min_wait. */
  1655. if (time_after_eq(jiffies, mtime) ||
  1656. ha->flags.isp82xx_fw_hung)
  1657. break;
  1658. }
  1659. if (time_after_eq(jiffies, wtime))
  1660. break;
  1661. /* Delay for a while */
  1662. msleep(500);
  1663. } while (1);
  1664. ql_dbg(ql_dbg_taskm, vha, 0x803a,
  1665. "fw_state=%x (%x, %x, %x, %x) " "curr time=%lx.\n", state[0],
  1666. state[1], state[2], state[3], state[4], jiffies);
  1667. if (rval && !(vha->device_flags & DFLG_NO_CABLE)) {
  1668. ql_log(ql_log_warn, vha, 0x803b,
  1669. "Firmware ready **** FAILED ****.\n");
  1670. }
  1671. return (rval);
  1672. }
  1673. /*
  1674. * qla2x00_configure_hba
  1675. * Setup adapter context.
  1676. *
  1677. * Input:
  1678. * ha = adapter state pointer.
  1679. *
  1680. * Returns:
  1681. * 0 = success
  1682. *
  1683. * Context:
  1684. * Kernel context.
  1685. */
  1686. static int
  1687. qla2x00_configure_hba(scsi_qla_host_t *vha)
  1688. {
  1689. int rval;
  1690. uint16_t loop_id;
  1691. uint16_t topo;
  1692. uint16_t sw_cap;
  1693. uint8_t al_pa;
  1694. uint8_t area;
  1695. uint8_t domain;
  1696. char connect_type[22];
  1697. struct qla_hw_data *ha = vha->hw;
  1698. /* Get host addresses. */
  1699. rval = qla2x00_get_adapter_id(vha,
  1700. &loop_id, &al_pa, &area, &domain, &topo, &sw_cap);
  1701. if (rval != QLA_SUCCESS) {
  1702. if (LOOP_TRANSITION(vha) || atomic_read(&ha->loop_down_timer) ||
  1703. IS_CNA_CAPABLE(ha) ||
  1704. (rval == QLA_COMMAND_ERROR && loop_id == 0x7)) {
  1705. ql_dbg(ql_dbg_disc, vha, 0x2008,
  1706. "Loop is in a transition state.\n");
  1707. } else {
  1708. ql_log(ql_log_warn, vha, 0x2009,
  1709. "Unable to get host loop ID.\n");
  1710. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  1711. }
  1712. return (rval);
  1713. }
  1714. if (topo == 4) {
  1715. ql_log(ql_log_info, vha, 0x200a,
  1716. "Cannot get topology - retrying.\n");
  1717. return (QLA_FUNCTION_FAILED);
  1718. }
  1719. vha->loop_id = loop_id;
  1720. /* initialize */
  1721. ha->min_external_loopid = SNS_FIRST_LOOP_ID;
  1722. ha->operating_mode = LOOP;
  1723. ha->switch_cap = 0;
  1724. switch (topo) {
  1725. case 0:
  1726. ql_dbg(ql_dbg_disc, vha, 0x200b, "HBA in NL topology.\n");
  1727. ha->current_topology = ISP_CFG_NL;
  1728. strcpy(connect_type, "(Loop)");
  1729. break;
  1730. case 1:
  1731. ql_dbg(ql_dbg_disc, vha, 0x200c, "HBA in FL topology.\n");
  1732. ha->switch_cap = sw_cap;
  1733. ha->current_topology = ISP_CFG_FL;
  1734. strcpy(connect_type, "(FL_Port)");
  1735. break;
  1736. case 2:
  1737. ql_dbg(ql_dbg_disc, vha, 0x200d, "HBA in N P2P topology.\n");
  1738. ha->operating_mode = P2P;
  1739. ha->current_topology = ISP_CFG_N;
  1740. strcpy(connect_type, "(N_Port-to-N_Port)");
  1741. break;
  1742. case 3:
  1743. ql_dbg(ql_dbg_disc, vha, 0x200e, "HBA in F P2P topology.\n");
  1744. ha->switch_cap = sw_cap;
  1745. ha->operating_mode = P2P;
  1746. ha->current_topology = ISP_CFG_F;
  1747. strcpy(connect_type, "(F_Port)");
  1748. break;
  1749. default:
  1750. ql_dbg(ql_dbg_disc, vha, 0x200f,
  1751. "HBA in unknown topology %x, using NL.\n", topo);
  1752. ha->current_topology = ISP_CFG_NL;
  1753. strcpy(connect_type, "(Loop)");
  1754. break;
  1755. }
  1756. /* Save Host port and loop ID. */
  1757. /* byte order - Big Endian */
  1758. vha->d_id.b.domain = domain;
  1759. vha->d_id.b.area = area;
  1760. vha->d_id.b.al_pa = al_pa;
  1761. spin_lock(&ha->vport_slock);
  1762. qlt_update_vp_map(vha, SET_AL_PA);
  1763. spin_unlock(&ha->vport_slock);
  1764. if (!vha->flags.init_done)
  1765. ql_log(ql_log_info, vha, 0x2010,
  1766. "Topology - %s, Host Loop address 0x%x.\n",
  1767. connect_type, vha->loop_id);
  1768. if (rval) {
  1769. ql_log(ql_log_warn, vha, 0x2011,
  1770. "%s FAILED\n", __func__);
  1771. } else {
  1772. ql_dbg(ql_dbg_disc, vha, 0x2012,
  1773. "%s success\n", __func__);
  1774. }
  1775. return(rval);
  1776. }
  1777. inline void
  1778. qla2x00_set_model_info(scsi_qla_host_t *vha, uint8_t *model, size_t len,
  1779. char *def)
  1780. {
  1781. char *st, *en;
  1782. uint16_t index;
  1783. struct qla_hw_data *ha = vha->hw;
  1784. int use_tbl = !IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) &&
  1785. !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha);
  1786. if (memcmp(model, BINZERO, len) != 0) {
  1787. strncpy(ha->model_number, model, len);
  1788. st = en = ha->model_number;
  1789. en += len - 1;
  1790. while (en > st) {
  1791. if (*en != 0x20 && *en != 0x00)
  1792. break;
  1793. *en-- = '\0';
  1794. }
  1795. index = (ha->pdev->subsystem_device & 0xff);
  1796. if (use_tbl &&
  1797. ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
  1798. index < QLA_MODEL_NAMES)
  1799. strncpy(ha->model_desc,
  1800. qla2x00_model_name[index * 2 + 1],
  1801. sizeof(ha->model_desc) - 1);
  1802. } else {
  1803. index = (ha->pdev->subsystem_device & 0xff);
  1804. if (use_tbl &&
  1805. ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
  1806. index < QLA_MODEL_NAMES) {
  1807. strcpy(ha->model_number,
  1808. qla2x00_model_name[index * 2]);
  1809. strncpy(ha->model_desc,
  1810. qla2x00_model_name[index * 2 + 1],
  1811. sizeof(ha->model_desc) - 1);
  1812. } else {
  1813. strcpy(ha->model_number, def);
  1814. }
  1815. }
  1816. if (IS_FWI2_CAPABLE(ha))
  1817. qla2xxx_get_vpd_field(vha, "\x82", ha->model_desc,
  1818. sizeof(ha->model_desc));
  1819. }
  1820. /* On sparc systems, obtain port and node WWN from firmware
  1821. * properties.
  1822. */
  1823. static void qla2xxx_nvram_wwn_from_ofw(scsi_qla_host_t *vha, nvram_t *nv)
  1824. {
  1825. #ifdef CONFIG_SPARC
  1826. struct qla_hw_data *ha = vha->hw;
  1827. struct pci_dev *pdev = ha->pdev;
  1828. struct device_node *dp = pci_device_to_OF_node(pdev);
  1829. const u8 *val;
  1830. int len;
  1831. val = of_get_property(dp, "port-wwn", &len);
  1832. if (val && len >= WWN_SIZE)
  1833. memcpy(nv->port_name, val, WWN_SIZE);
  1834. val = of_get_property(dp, "node-wwn", &len);
  1835. if (val && len >= WWN_SIZE)
  1836. memcpy(nv->node_name, val, WWN_SIZE);
  1837. #endif
  1838. }
  1839. /*
  1840. * NVRAM configuration for ISP 2xxx
  1841. *
  1842. * Input:
  1843. * ha = adapter block pointer.
  1844. *
  1845. * Output:
  1846. * initialization control block in response_ring
  1847. * host adapters parameters in host adapter block
  1848. *
  1849. * Returns:
  1850. * 0 = success.
  1851. */
  1852. int
  1853. qla2x00_nvram_config(scsi_qla_host_t *vha)
  1854. {
  1855. int rval;
  1856. uint8_t chksum = 0;
  1857. uint16_t cnt;
  1858. uint8_t *dptr1, *dptr2;
  1859. struct qla_hw_data *ha = vha->hw;
  1860. init_cb_t *icb = ha->init_cb;
  1861. nvram_t *nv = ha->nvram;
  1862. uint8_t *ptr = ha->nvram;
  1863. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  1864. rval = QLA_SUCCESS;
  1865. /* Determine NVRAM starting address. */
  1866. ha->nvram_size = sizeof(nvram_t);
  1867. ha->nvram_base = 0;
  1868. if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha))
  1869. if ((RD_REG_WORD(&reg->ctrl_status) >> 14) == 1)
  1870. ha->nvram_base = 0x80;
  1871. /* Get NVRAM data and calculate checksum. */
  1872. ha->isp_ops->read_nvram(vha, ptr, ha->nvram_base, ha->nvram_size);
  1873. for (cnt = 0, chksum = 0; cnt < ha->nvram_size; cnt++)
  1874. chksum += *ptr++;
  1875. ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x010f,
  1876. "Contents of NVRAM.\n");
  1877. ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0110,
  1878. (uint8_t *)nv, ha->nvram_size);
  1879. /* Bad NVRAM data, set defaults parameters. */
  1880. if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' ||
  1881. nv->id[2] != 'P' || nv->id[3] != ' ' || nv->nvram_version < 1) {
  1882. /* Reset NVRAM data. */
  1883. ql_log(ql_log_warn, vha, 0x0064,
  1884. "Inconsistent NVRAM "
  1885. "detected: checksum=0x%x id=%c version=0x%x.\n",
  1886. chksum, nv->id[0], nv->nvram_version);
  1887. ql_log(ql_log_warn, vha, 0x0065,
  1888. "Falling back to "
  1889. "functioning (yet invalid -- WWPN) defaults.\n");
  1890. /*
  1891. * Set default initialization control block.
  1892. */
  1893. memset(nv, 0, ha->nvram_size);
  1894. nv->parameter_block_version = ICB_VERSION;
  1895. if (IS_QLA23XX(ha)) {
  1896. nv->firmware_options[0] = BIT_2 | BIT_1;
  1897. nv->firmware_options[1] = BIT_7 | BIT_5;
  1898. nv->add_firmware_options[0] = BIT_5;
  1899. nv->add_firmware_options[1] = BIT_5 | BIT_4;
  1900. nv->frame_payload_size = __constant_cpu_to_le16(2048);
  1901. nv->special_options[1] = BIT_7;
  1902. } else if (IS_QLA2200(ha)) {
  1903. nv->firmware_options[0] = BIT_2 | BIT_1;
  1904. nv->firmware_options[1] = BIT_7 | BIT_5;
  1905. nv->add_firmware_options[0] = BIT_5;
  1906. nv->add_firmware_options[1] = BIT_5 | BIT_4;
  1907. nv->frame_payload_size = __constant_cpu_to_le16(1024);
  1908. } else if (IS_QLA2100(ha)) {
  1909. nv->firmware_options[0] = BIT_3 | BIT_1;
  1910. nv->firmware_options[1] = BIT_5;
  1911. nv->frame_payload_size = __constant_cpu_to_le16(1024);
  1912. }
  1913. nv->max_iocb_allocation = __constant_cpu_to_le16(256);
  1914. nv->execution_throttle = __constant_cpu_to_le16(16);
  1915. nv->retry_count = 8;
  1916. nv->retry_delay = 1;
  1917. nv->port_name[0] = 33;
  1918. nv->port_name[3] = 224;
  1919. nv->port_name[4] = 139;
  1920. qla2xxx_nvram_wwn_from_ofw(vha, nv);
  1921. nv->login_timeout = 4;
  1922. /*
  1923. * Set default host adapter parameters
  1924. */
  1925. nv->host_p[1] = BIT_2;
  1926. nv->reset_delay = 5;
  1927. nv->port_down_retry_count = 8;
  1928. nv->max_luns_per_target = __constant_cpu_to_le16(8);
  1929. nv->link_down_timeout = 60;
  1930. rval = 1;
  1931. }
  1932. #if defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_SGI_SN2)
  1933. /*
  1934. * The SN2 does not provide BIOS emulation which means you can't change
  1935. * potentially bogus BIOS settings. Force the use of default settings
  1936. * for link rate and frame size. Hope that the rest of the settings
  1937. * are valid.
  1938. */
  1939. if (ia64_platform_is("sn2")) {
  1940. nv->frame_payload_size = __constant_cpu_to_le16(2048);
  1941. if (IS_QLA23XX(ha))
  1942. nv->special_options[1] = BIT_7;
  1943. }
  1944. #endif
  1945. /* Reset Initialization control block */
  1946. memset(icb, 0, ha->init_cb_size);
  1947. /*
  1948. * Setup driver NVRAM options.
  1949. */
  1950. nv->firmware_options[0] |= (BIT_6 | BIT_1);
  1951. nv->firmware_options[0] &= ~(BIT_5 | BIT_4);
  1952. nv->firmware_options[1] |= (BIT_5 | BIT_0);
  1953. nv->firmware_options[1] &= ~BIT_4;
  1954. if (IS_QLA23XX(ha)) {
  1955. nv->firmware_options[0] |= BIT_2;
  1956. nv->firmware_options[0] &= ~BIT_3;
  1957. nv->special_options[0] &= ~BIT_6;
  1958. nv->add_firmware_options[1] |= BIT_5 | BIT_4;
  1959. if (IS_QLA2300(ha)) {
  1960. if (ha->fb_rev == FPM_2310) {
  1961. strcpy(ha->model_number, "QLA2310");
  1962. } else {
  1963. strcpy(ha->model_number, "QLA2300");
  1964. }
  1965. } else {
  1966. qla2x00_set_model_info(vha, nv->model_number,
  1967. sizeof(nv->model_number), "QLA23xx");
  1968. }
  1969. } else if (IS_QLA2200(ha)) {
  1970. nv->firmware_options[0] |= BIT_2;
  1971. /*
  1972. * 'Point-to-point preferred, else loop' is not a safe
  1973. * connection mode setting.
  1974. */
  1975. if ((nv->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) ==
  1976. (BIT_5 | BIT_4)) {
  1977. /* Force 'loop preferred, else point-to-point'. */
  1978. nv->add_firmware_options[0] &= ~(BIT_6 | BIT_5 | BIT_4);
  1979. nv->add_firmware_options[0] |= BIT_5;
  1980. }
  1981. strcpy(ha->model_number, "QLA22xx");
  1982. } else /*if (IS_QLA2100(ha))*/ {
  1983. strcpy(ha->model_number, "QLA2100");
  1984. }
  1985. /*
  1986. * Copy over NVRAM RISC parameter block to initialization control block.
  1987. */
  1988. dptr1 = (uint8_t *)icb;
  1989. dptr2 = (uint8_t *)&nv->parameter_block_version;
  1990. cnt = (uint8_t *)&icb->request_q_outpointer - (uint8_t *)&icb->version;
  1991. while (cnt--)
  1992. *dptr1++ = *dptr2++;
  1993. /* Copy 2nd half. */
  1994. dptr1 = (uint8_t *)icb->add_firmware_options;
  1995. cnt = (uint8_t *)icb->reserved_3 - (uint8_t *)icb->add_firmware_options;
  1996. while (cnt--)
  1997. *dptr1++ = *dptr2++;
  1998. /* Use alternate WWN? */
  1999. if (nv->host_p[1] & BIT_7) {
  2000. memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
  2001. memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
  2002. }
  2003. /* Prepare nodename */
  2004. if ((icb->firmware_options[1] & BIT_6) == 0) {
  2005. /*
  2006. * Firmware will apply the following mask if the nodename was
  2007. * not provided.
  2008. */
  2009. memcpy(icb->node_name, icb->port_name, WWN_SIZE);
  2010. icb->node_name[0] &= 0xF0;
  2011. }
  2012. /*
  2013. * Set host adapter parameters.
  2014. */
  2015. /*
  2016. * BIT_7 in the host-parameters section allows for modification to
  2017. * internal driver logging.
  2018. */
  2019. if (nv->host_p[0] & BIT_7)
  2020. ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
  2021. ha->flags.disable_risc_code_load = ((nv->host_p[0] & BIT_4) ? 1 : 0);
  2022. /* Always load RISC code on non ISP2[12]00 chips. */
  2023. if (!IS_QLA2100(ha) && !IS_QLA2200(ha))
  2024. ha->flags.disable_risc_code_load = 0;
  2025. ha->flags.enable_lip_reset = ((nv->host_p[1] & BIT_1) ? 1 : 0);
  2026. ha->flags.enable_lip_full_login = ((nv->host_p[1] & BIT_2) ? 1 : 0);
  2027. ha->flags.enable_target_reset = ((nv->host_p[1] & BIT_3) ? 1 : 0);
  2028. ha->flags.enable_led_scheme = (nv->special_options[1] & BIT_4) ? 1 : 0;
  2029. ha->flags.disable_serdes = 0;
  2030. ha->operating_mode =
  2031. (icb->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) >> 4;
  2032. memcpy(ha->fw_seriallink_options, nv->seriallink_options,
  2033. sizeof(ha->fw_seriallink_options));
  2034. /* save HBA serial number */
  2035. ha->serial0 = icb->port_name[5];
  2036. ha->serial1 = icb->port_name[6];
  2037. ha->serial2 = icb->port_name[7];
  2038. memcpy(vha->node_name, icb->node_name, WWN_SIZE);
  2039. memcpy(vha->port_name, icb->port_name, WWN_SIZE);
  2040. icb->execution_throttle = __constant_cpu_to_le16(0xFFFF);
  2041. ha->retry_count = nv->retry_count;
  2042. /* Set minimum login_timeout to 4 seconds. */
  2043. if (nv->login_timeout != ql2xlogintimeout)
  2044. nv->login_timeout = ql2xlogintimeout;
  2045. if (nv->login_timeout < 4)
  2046. nv->login_timeout = 4;
  2047. ha->login_timeout = nv->login_timeout;
  2048. icb->login_timeout = nv->login_timeout;
  2049. /* Set minimum RATOV to 100 tenths of a second. */
  2050. ha->r_a_tov = 100;
  2051. ha->loop_reset_delay = nv->reset_delay;
  2052. /* Link Down Timeout = 0:
  2053. *
  2054. * When Port Down timer expires we will start returning
  2055. * I/O's to OS with "DID_NO_CONNECT".
  2056. *
  2057. * Link Down Timeout != 0:
  2058. *
  2059. * The driver waits for the link to come up after link down
  2060. * before returning I/Os to OS with "DID_NO_CONNECT".
  2061. */
  2062. if (nv->link_down_timeout == 0) {
  2063. ha->loop_down_abort_time =
  2064. (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
  2065. } else {
  2066. ha->link_down_timeout = nv->link_down_timeout;
  2067. ha->loop_down_abort_time =
  2068. (LOOP_DOWN_TIME - ha->link_down_timeout);
  2069. }
  2070. /*
  2071. * Need enough time to try and get the port back.
  2072. */
  2073. ha->port_down_retry_count = nv->port_down_retry_count;
  2074. if (qlport_down_retry)
  2075. ha->port_down_retry_count = qlport_down_retry;
  2076. /* Set login_retry_count */
  2077. ha->login_retry_count = nv->retry_count;
  2078. if (ha->port_down_retry_count == nv->port_down_retry_count &&
  2079. ha->port_down_retry_count > 3)
  2080. ha->login_retry_count = ha->port_down_retry_count;
  2081. else if (ha->port_down_retry_count > (int)ha->login_retry_count)
  2082. ha->login_retry_count = ha->port_down_retry_count;
  2083. if (ql2xloginretrycount)
  2084. ha->login_retry_count = ql2xloginretrycount;
  2085. icb->lun_enables = __constant_cpu_to_le16(0);
  2086. icb->command_resource_count = 0;
  2087. icb->immediate_notify_resource_count = 0;
  2088. icb->timeout = __constant_cpu_to_le16(0);
  2089. if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
  2090. /* Enable RIO */
  2091. icb->firmware_options[0] &= ~BIT_3;
  2092. icb->add_firmware_options[0] &=
  2093. ~(BIT_3 | BIT_2 | BIT_1 | BIT_0);
  2094. icb->add_firmware_options[0] |= BIT_2;
  2095. icb->response_accumulation_timer = 3;
  2096. icb->interrupt_delay_timer = 5;
  2097. vha->flags.process_response_queue = 1;
  2098. } else {
  2099. /* Enable ZIO. */
  2100. if (!vha->flags.init_done) {
  2101. ha->zio_mode = icb->add_firmware_options[0] &
  2102. (BIT_3 | BIT_2 | BIT_1 | BIT_0);
  2103. ha->zio_timer = icb->interrupt_delay_timer ?
  2104. icb->interrupt_delay_timer: 2;
  2105. }
  2106. icb->add_firmware_options[0] &=
  2107. ~(BIT_3 | BIT_2 | BIT_1 | BIT_0);
  2108. vha->flags.process_response_queue = 0;
  2109. if (ha->zio_mode != QLA_ZIO_DISABLED) {
  2110. ha->zio_mode = QLA_ZIO_MODE_6;
  2111. ql_log(ql_log_info, vha, 0x0068,
  2112. "ZIO mode %d enabled; timer delay (%d us).\n",
  2113. ha->zio_mode, ha->zio_timer * 100);
  2114. icb->add_firmware_options[0] |= (uint8_t)ha->zio_mode;
  2115. icb->interrupt_delay_timer = (uint8_t)ha->zio_timer;
  2116. vha->flags.process_response_queue = 1;
  2117. }
  2118. }
  2119. if (rval) {
  2120. ql_log(ql_log_warn, vha, 0x0069,
  2121. "NVRAM configuration failed.\n");
  2122. }
  2123. return (rval);
  2124. }
  2125. static void
  2126. qla2x00_rport_del(void *data)
  2127. {
  2128. fc_port_t *fcport = data;
  2129. struct fc_rport *rport;
  2130. scsi_qla_host_t *vha = fcport->vha;
  2131. unsigned long flags;
  2132. spin_lock_irqsave(fcport->vha->host->host_lock, flags);
  2133. rport = fcport->drport ? fcport->drport: fcport->rport;
  2134. fcport->drport = NULL;
  2135. spin_unlock_irqrestore(fcport->vha->host->host_lock, flags);
  2136. if (rport) {
  2137. fc_remote_port_delete(rport);
  2138. /*
  2139. * Release the target mode FC NEXUS in qla_target.c code
  2140. * if target mod is enabled.
  2141. */
  2142. qlt_fc_port_deleted(vha, fcport);
  2143. }
  2144. }
  2145. /**
  2146. * qla2x00_alloc_fcport() - Allocate a generic fcport.
  2147. * @ha: HA context
  2148. * @flags: allocation flags
  2149. *
  2150. * Returns a pointer to the allocated fcport, or NULL, if none available.
  2151. */
  2152. fc_port_t *
  2153. qla2x00_alloc_fcport(scsi_qla_host_t *vha, gfp_t flags)
  2154. {
  2155. fc_port_t *fcport;
  2156. fcport = kzalloc(sizeof(fc_port_t), flags);
  2157. if (!fcport)
  2158. return NULL;
  2159. /* Setup fcport template structure. */
  2160. fcport->vha = vha;
  2161. fcport->port_type = FCT_UNKNOWN;
  2162. fcport->loop_id = FC_NO_LOOP_ID;
  2163. qla2x00_set_fcport_state(fcport, FCS_UNCONFIGURED);
  2164. fcport->supported_classes = FC_COS_UNSPECIFIED;
  2165. fcport->scan_state = QLA_FCPORT_SCAN_NONE;
  2166. return fcport;
  2167. }
  2168. /*
  2169. * qla2x00_configure_loop
  2170. * Updates Fibre Channel Device Database with what is actually on loop.
  2171. *
  2172. * Input:
  2173. * ha = adapter block pointer.
  2174. *
  2175. * Returns:
  2176. * 0 = success.
  2177. * 1 = error.
  2178. * 2 = database was full and device was not configured.
  2179. */
  2180. static int
  2181. qla2x00_configure_loop(scsi_qla_host_t *vha)
  2182. {
  2183. int rval;
  2184. unsigned long flags, save_flags;
  2185. struct qla_hw_data *ha = vha->hw;
  2186. rval = QLA_SUCCESS;
  2187. /* Get Initiator ID */
  2188. if (test_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags)) {
  2189. rval = qla2x00_configure_hba(vha);
  2190. if (rval != QLA_SUCCESS) {
  2191. ql_dbg(ql_dbg_disc, vha, 0x2013,
  2192. "Unable to configure HBA.\n");
  2193. return (rval);
  2194. }
  2195. }
  2196. save_flags = flags = vha->dpc_flags;
  2197. ql_dbg(ql_dbg_disc, vha, 0x2014,
  2198. "Configure loop -- dpc flags = 0x%lx.\n", flags);
  2199. /*
  2200. * If we have both an RSCN and PORT UPDATE pending then handle them
  2201. * both at the same time.
  2202. */
  2203. clear_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
  2204. clear_bit(RSCN_UPDATE, &vha->dpc_flags);
  2205. qla2x00_get_data_rate(vha);
  2206. /* Determine what we need to do */
  2207. if (ha->current_topology == ISP_CFG_FL &&
  2208. (test_bit(LOCAL_LOOP_UPDATE, &flags))) {
  2209. set_bit(RSCN_UPDATE, &flags);
  2210. } else if (ha->current_topology == ISP_CFG_F &&
  2211. (test_bit(LOCAL_LOOP_UPDATE, &flags))) {
  2212. set_bit(RSCN_UPDATE, &flags);
  2213. clear_bit(LOCAL_LOOP_UPDATE, &flags);
  2214. } else if (ha->current_topology == ISP_CFG_N) {
  2215. clear_bit(RSCN_UPDATE, &flags);
  2216. } else if (!vha->flags.online ||
  2217. (test_bit(ABORT_ISP_ACTIVE, &flags))) {
  2218. set_bit(RSCN_UPDATE, &flags);
  2219. set_bit(LOCAL_LOOP_UPDATE, &flags);
  2220. }
  2221. if (test_bit(LOCAL_LOOP_UPDATE, &flags)) {
  2222. if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
  2223. ql_dbg(ql_dbg_disc, vha, 0x2015,
  2224. "Loop resync needed, failing.\n");
  2225. rval = QLA_FUNCTION_FAILED;
  2226. } else
  2227. rval = qla2x00_configure_local_loop(vha);
  2228. }
  2229. if (rval == QLA_SUCCESS && test_bit(RSCN_UPDATE, &flags)) {
  2230. if (LOOP_TRANSITION(vha)) {
  2231. ql_dbg(ql_dbg_disc, vha, 0x201e,
  2232. "Needs RSCN update and loop transition.\n");
  2233. rval = QLA_FUNCTION_FAILED;
  2234. }
  2235. else
  2236. rval = qla2x00_configure_fabric(vha);
  2237. }
  2238. if (rval == QLA_SUCCESS) {
  2239. if (atomic_read(&vha->loop_down_timer) ||
  2240. test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
  2241. rval = QLA_FUNCTION_FAILED;
  2242. } else {
  2243. atomic_set(&vha->loop_state, LOOP_READY);
  2244. ql_dbg(ql_dbg_disc, vha, 0x2069,
  2245. "LOOP READY.\n");
  2246. }
  2247. }
  2248. if (rval) {
  2249. ql_dbg(ql_dbg_disc, vha, 0x206a,
  2250. "%s *** FAILED ***.\n", __func__);
  2251. } else {
  2252. ql_dbg(ql_dbg_disc, vha, 0x206b,
  2253. "%s: exiting normally.\n", __func__);
  2254. }
  2255. /* Restore state if a resync event occurred during processing */
  2256. if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
  2257. if (test_bit(LOCAL_LOOP_UPDATE, &save_flags))
  2258. set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
  2259. if (test_bit(RSCN_UPDATE, &save_flags)) {
  2260. set_bit(RSCN_UPDATE, &vha->dpc_flags);
  2261. }
  2262. }
  2263. return (rval);
  2264. }
  2265. /*
  2266. * qla2x00_configure_local_loop
  2267. * Updates Fibre Channel Device Database with local loop devices.
  2268. *
  2269. * Input:
  2270. * ha = adapter block pointer.
  2271. *
  2272. * Returns:
  2273. * 0 = success.
  2274. */
  2275. static int
  2276. qla2x00_configure_local_loop(scsi_qla_host_t *vha)
  2277. {
  2278. int rval, rval2;
  2279. int found_devs;
  2280. int found;
  2281. fc_port_t *fcport, *new_fcport;
  2282. uint16_t index;
  2283. uint16_t entries;
  2284. char *id_iter;
  2285. uint16_t loop_id;
  2286. uint8_t domain, area, al_pa;
  2287. struct qla_hw_data *ha = vha->hw;
  2288. found_devs = 0;
  2289. new_fcport = NULL;
  2290. entries = MAX_FIBRE_DEVICES_LOOP;
  2291. ql_dbg(ql_dbg_disc, vha, 0x2016,
  2292. "Getting FCAL position map.\n");
  2293. if (ql2xextended_error_logging & ql_dbg_disc)
  2294. qla2x00_get_fcal_position_map(vha, NULL);
  2295. /* Get list of logged in devices. */
  2296. memset(ha->gid_list, 0, qla2x00_gid_list_size(ha));
  2297. rval = qla2x00_get_id_list(vha, ha->gid_list, ha->gid_list_dma,
  2298. &entries);
  2299. if (rval != QLA_SUCCESS)
  2300. goto cleanup_allocation;
  2301. ql_dbg(ql_dbg_disc, vha, 0x2017,
  2302. "Entries in ID list (%d).\n", entries);
  2303. ql_dump_buffer(ql_dbg_disc + ql_dbg_buffer, vha, 0x2075,
  2304. (uint8_t *)ha->gid_list,
  2305. entries * sizeof(struct gid_list_info));
  2306. /* Allocate temporary fcport for any new fcports discovered. */
  2307. new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
  2308. if (new_fcport == NULL) {
  2309. ql_log(ql_log_warn, vha, 0x2018,
  2310. "Memory allocation failed for fcport.\n");
  2311. rval = QLA_MEMORY_ALLOC_FAILED;
  2312. goto cleanup_allocation;
  2313. }
  2314. new_fcport->flags &= ~FCF_FABRIC_DEVICE;
  2315. /*
  2316. * Mark local devices that were present with FCF_DEVICE_LOST for now.
  2317. */
  2318. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  2319. if (atomic_read(&fcport->state) == FCS_ONLINE &&
  2320. fcport->port_type != FCT_BROADCAST &&
  2321. (fcport->flags & FCF_FABRIC_DEVICE) == 0) {
  2322. ql_dbg(ql_dbg_disc, vha, 0x2019,
  2323. "Marking port lost loop_id=0x%04x.\n",
  2324. fcport->loop_id);
  2325. qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
  2326. }
  2327. }
  2328. /* Add devices to port list. */
  2329. id_iter = (char *)ha->gid_list;
  2330. for (index = 0; index < entries; index++) {
  2331. domain = ((struct gid_list_info *)id_iter)->domain;
  2332. area = ((struct gid_list_info *)id_iter)->area;
  2333. al_pa = ((struct gid_list_info *)id_iter)->al_pa;
  2334. if (IS_QLA2100(ha) || IS_QLA2200(ha))
  2335. loop_id = (uint16_t)
  2336. ((struct gid_list_info *)id_iter)->loop_id_2100;
  2337. else
  2338. loop_id = le16_to_cpu(
  2339. ((struct gid_list_info *)id_iter)->loop_id);
  2340. id_iter += ha->gid_list_info_size;
  2341. /* Bypass reserved domain fields. */
  2342. if ((domain & 0xf0) == 0xf0)
  2343. continue;
  2344. /* Bypass if not same domain and area of adapter. */
  2345. if (area && domain &&
  2346. (area != vha->d_id.b.area || domain != vha->d_id.b.domain))
  2347. continue;
  2348. /* Bypass invalid local loop ID. */
  2349. if (loop_id > LAST_LOCAL_LOOP_ID)
  2350. continue;
  2351. /* Fill in member data. */
  2352. new_fcport->d_id.b.domain = domain;
  2353. new_fcport->d_id.b.area = area;
  2354. new_fcport->d_id.b.al_pa = al_pa;
  2355. new_fcport->loop_id = loop_id;
  2356. rval2 = qla2x00_get_port_database(vha, new_fcport, 0);
  2357. if (rval2 != QLA_SUCCESS) {
  2358. ql_dbg(ql_dbg_disc, vha, 0x201a,
  2359. "Failed to retrieve fcport information "
  2360. "-- get_port_database=%x, loop_id=0x%04x.\n",
  2361. rval2, new_fcport->loop_id);
  2362. ql_dbg(ql_dbg_disc, vha, 0x201b,
  2363. "Scheduling resync.\n");
  2364. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  2365. continue;
  2366. }
  2367. /* Check for matching device in port list. */
  2368. found = 0;
  2369. fcport = NULL;
  2370. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  2371. if (memcmp(new_fcport->port_name, fcport->port_name,
  2372. WWN_SIZE))
  2373. continue;
  2374. fcport->flags &= ~FCF_FABRIC_DEVICE;
  2375. fcport->loop_id = new_fcport->loop_id;
  2376. fcport->port_type = new_fcport->port_type;
  2377. fcport->d_id.b24 = new_fcport->d_id.b24;
  2378. memcpy(fcport->node_name, new_fcport->node_name,
  2379. WWN_SIZE);
  2380. found++;
  2381. break;
  2382. }
  2383. if (!found) {
  2384. /* New device, add to fcports list. */
  2385. list_add_tail(&new_fcport->list, &vha->vp_fcports);
  2386. /* Allocate a new replacement fcport. */
  2387. fcport = new_fcport;
  2388. new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
  2389. if (new_fcport == NULL) {
  2390. ql_log(ql_log_warn, vha, 0x201c,
  2391. "Failed to allocate memory for fcport.\n");
  2392. rval = QLA_MEMORY_ALLOC_FAILED;
  2393. goto cleanup_allocation;
  2394. }
  2395. new_fcport->flags &= ~FCF_FABRIC_DEVICE;
  2396. }
  2397. /* Base iIDMA settings on HBA port speed. */
  2398. fcport->fp_speed = ha->link_data_rate;
  2399. qla2x00_update_fcport(vha, fcport);
  2400. found_devs++;
  2401. }
  2402. cleanup_allocation:
  2403. kfree(new_fcport);
  2404. if (rval != QLA_SUCCESS) {
  2405. ql_dbg(ql_dbg_disc, vha, 0x201d,
  2406. "Configure local loop error exit: rval=%x.\n", rval);
  2407. }
  2408. return (rval);
  2409. }
  2410. static void
  2411. qla2x00_iidma_fcport(scsi_qla_host_t *vha, fc_port_t *fcport)
  2412. {
  2413. char *link_speed;
  2414. int rval;
  2415. uint16_t mb[4];
  2416. struct qla_hw_data *ha = vha->hw;
  2417. if (!IS_IIDMA_CAPABLE(ha))
  2418. return;
  2419. if (atomic_read(&fcport->state) != FCS_ONLINE)
  2420. return;
  2421. if (fcport->fp_speed == PORT_SPEED_UNKNOWN ||
  2422. fcport->fp_speed > ha->link_data_rate)
  2423. return;
  2424. rval = qla2x00_set_idma_speed(vha, fcport->loop_id, fcport->fp_speed,
  2425. mb);
  2426. if (rval != QLA_SUCCESS) {
  2427. ql_dbg(ql_dbg_disc, vha, 0x2004,
  2428. "Unable to adjust iIDMA "
  2429. "%02x%02x%02x%02x%02x%02x%02x%02x -- %04x %x %04x "
  2430. "%04x.\n", fcport->port_name[0], fcport->port_name[1],
  2431. fcport->port_name[2], fcport->port_name[3],
  2432. fcport->port_name[4], fcport->port_name[5],
  2433. fcport->port_name[6], fcport->port_name[7], rval,
  2434. fcport->fp_speed, mb[0], mb[1]);
  2435. } else {
  2436. link_speed = qla2x00_get_link_speed_str(ha);
  2437. ql_dbg(ql_dbg_disc, vha, 0x2005,
  2438. "iIDMA adjusted to %s GB/s "
  2439. "on %02x%02x%02x%02x%02x%02x%02x%02x.\n", link_speed,
  2440. fcport->port_name[0], fcport->port_name[1],
  2441. fcport->port_name[2], fcport->port_name[3],
  2442. fcport->port_name[4], fcport->port_name[5],
  2443. fcport->port_name[6], fcport->port_name[7]);
  2444. }
  2445. }
  2446. static void
  2447. qla2x00_reg_remote_port(scsi_qla_host_t *vha, fc_port_t *fcport)
  2448. {
  2449. struct fc_rport_identifiers rport_ids;
  2450. struct fc_rport *rport;
  2451. unsigned long flags;
  2452. qla2x00_rport_del(fcport);
  2453. rport_ids.node_name = wwn_to_u64(fcport->node_name);
  2454. rport_ids.port_name = wwn_to_u64(fcport->port_name);
  2455. rport_ids.port_id = fcport->d_id.b.domain << 16 |
  2456. fcport->d_id.b.area << 8 | fcport->d_id.b.al_pa;
  2457. rport_ids.roles = FC_RPORT_ROLE_UNKNOWN;
  2458. fcport->rport = rport = fc_remote_port_add(vha->host, 0, &rport_ids);
  2459. if (!rport) {
  2460. ql_log(ql_log_warn, vha, 0x2006,
  2461. "Unable to allocate fc remote port.\n");
  2462. return;
  2463. }
  2464. /*
  2465. * Create target mode FC NEXUS in qla_target.c if target mode is
  2466. * enabled..
  2467. */
  2468. qlt_fc_port_added(vha, fcport);
  2469. spin_lock_irqsave(fcport->vha->host->host_lock, flags);
  2470. *((fc_port_t **)rport->dd_data) = fcport;
  2471. spin_unlock_irqrestore(fcport->vha->host->host_lock, flags);
  2472. rport->supported_classes = fcport->supported_classes;
  2473. rport_ids.roles = FC_RPORT_ROLE_UNKNOWN;
  2474. if (fcport->port_type == FCT_INITIATOR)
  2475. rport_ids.roles |= FC_RPORT_ROLE_FCP_INITIATOR;
  2476. if (fcport->port_type == FCT_TARGET)
  2477. rport_ids.roles |= FC_RPORT_ROLE_FCP_TARGET;
  2478. fc_remote_port_rolechg(rport, rport_ids.roles);
  2479. }
  2480. /*
  2481. * qla2x00_update_fcport
  2482. * Updates device on list.
  2483. *
  2484. * Input:
  2485. * ha = adapter block pointer.
  2486. * fcport = port structure pointer.
  2487. *
  2488. * Return:
  2489. * 0 - Success
  2490. * BIT_0 - error
  2491. *
  2492. * Context:
  2493. * Kernel context.
  2494. */
  2495. void
  2496. qla2x00_update_fcport(scsi_qla_host_t *vha, fc_port_t *fcport)
  2497. {
  2498. fcport->vha = vha;
  2499. fcport->login_retry = 0;
  2500. fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
  2501. qla2x00_iidma_fcport(vha, fcport);
  2502. qla24xx_update_fcport_fcp_prio(vha, fcport);
  2503. qla2x00_reg_remote_port(vha, fcport);
  2504. qla2x00_set_fcport_state(fcport, FCS_ONLINE);
  2505. }
  2506. /*
  2507. * qla2x00_configure_fabric
  2508. * Setup SNS devices with loop ID's.
  2509. *
  2510. * Input:
  2511. * ha = adapter block pointer.
  2512. *
  2513. * Returns:
  2514. * 0 = success.
  2515. * BIT_0 = error
  2516. */
  2517. static int
  2518. qla2x00_configure_fabric(scsi_qla_host_t *vha)
  2519. {
  2520. int rval;
  2521. fc_port_t *fcport;
  2522. uint16_t next_loopid;
  2523. uint16_t mb[MAILBOX_REGISTER_COUNT];
  2524. uint16_t loop_id;
  2525. LIST_HEAD(new_fcports);
  2526. struct qla_hw_data *ha = vha->hw;
  2527. struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
  2528. /* If FL port exists, then SNS is present */
  2529. if (IS_FWI2_CAPABLE(ha))
  2530. loop_id = NPH_F_PORT;
  2531. else
  2532. loop_id = SNS_FL_PORT;
  2533. rval = qla2x00_get_port_name(vha, loop_id, vha->fabric_node_name, 1);
  2534. if (rval != QLA_SUCCESS) {
  2535. ql_dbg(ql_dbg_disc, vha, 0x201f,
  2536. "MBX_GET_PORT_NAME failed, No FL Port.\n");
  2537. vha->device_flags &= ~SWITCH_FOUND;
  2538. return (QLA_SUCCESS);
  2539. }
  2540. vha->device_flags |= SWITCH_FOUND;
  2541. do {
  2542. /* FDMI support. */
  2543. if (ql2xfdmienable &&
  2544. test_and_clear_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags))
  2545. qla2x00_fdmi_register(vha);
  2546. /* Ensure we are logged into the SNS. */
  2547. if (IS_FWI2_CAPABLE(ha))
  2548. loop_id = NPH_SNS;
  2549. else
  2550. loop_id = SIMPLE_NAME_SERVER;
  2551. rval = ha->isp_ops->fabric_login(vha, loop_id, 0xff, 0xff,
  2552. 0xfc, mb, BIT_1|BIT_0);
  2553. if (rval != QLA_SUCCESS) {
  2554. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  2555. break;
  2556. }
  2557. if (mb[0] != MBS_COMMAND_COMPLETE) {
  2558. ql_dbg(ql_dbg_disc, vha, 0x2042,
  2559. "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x mb[2]=%x "
  2560. "mb[6]=%x mb[7]=%x.\n", loop_id, mb[0], mb[1],
  2561. mb[2], mb[6], mb[7]);
  2562. return (QLA_SUCCESS);
  2563. }
  2564. if (test_and_clear_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags)) {
  2565. if (qla2x00_rft_id(vha)) {
  2566. /* EMPTY */
  2567. ql_dbg(ql_dbg_disc, vha, 0x2045,
  2568. "Register FC-4 TYPE failed.\n");
  2569. }
  2570. if (qla2x00_rff_id(vha)) {
  2571. /* EMPTY */
  2572. ql_dbg(ql_dbg_disc, vha, 0x2049,
  2573. "Register FC-4 Features failed.\n");
  2574. }
  2575. if (qla2x00_rnn_id(vha)) {
  2576. /* EMPTY */
  2577. ql_dbg(ql_dbg_disc, vha, 0x204f,
  2578. "Register Node Name failed.\n");
  2579. } else if (qla2x00_rsnn_nn(vha)) {
  2580. /* EMPTY */
  2581. ql_dbg(ql_dbg_disc, vha, 0x2053,
  2582. "Register Symobilic Node Name failed.\n");
  2583. }
  2584. }
  2585. rval = qla2x00_find_all_fabric_devs(vha, &new_fcports);
  2586. if (rval != QLA_SUCCESS)
  2587. break;
  2588. /* Add new ports to existing port list */
  2589. list_splice_tail_init(&new_fcports, &vha->vp_fcports);
  2590. /* Starting free loop ID. */
  2591. next_loopid = ha->min_external_loopid;
  2592. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  2593. if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
  2594. break;
  2595. if ((fcport->flags & FCF_FABRIC_DEVICE) == 0)
  2596. continue;
  2597. /* Logout lost/gone fabric devices (non-FCP2) */
  2598. if (fcport->scan_state != QLA_FCPORT_SCAN_FOUND &&
  2599. atomic_read(&fcport->state) == FCS_ONLINE) {
  2600. qla2x00_mark_device_lost(vha, fcport,
  2601. ql2xplogiabsentdevice, 0);
  2602. if (fcport->loop_id != FC_NO_LOOP_ID &&
  2603. (fcport->flags & FCF_FCP2_DEVICE) == 0 &&
  2604. fcport->port_type != FCT_INITIATOR &&
  2605. fcport->port_type != FCT_BROADCAST) {
  2606. ha->isp_ops->fabric_logout(vha,
  2607. fcport->loop_id,
  2608. fcport->d_id.b.domain,
  2609. fcport->d_id.b.area,
  2610. fcport->d_id.b.al_pa);
  2611. }
  2612. continue;
  2613. }
  2614. fcport->scan_state = QLA_FCPORT_SCAN_NONE;
  2615. /* Login fabric devices that need a login */
  2616. if ((fcport->flags & FCF_LOGIN_NEEDED) != 0 &&
  2617. atomic_read(&vha->loop_down_timer) == 0) {
  2618. if (fcport->loop_id == FC_NO_LOOP_ID) {
  2619. fcport->loop_id = next_loopid;
  2620. rval = qla2x00_find_new_loop_id(
  2621. base_vha, fcport);
  2622. if (rval != QLA_SUCCESS) {
  2623. /* Ran out of IDs to use */
  2624. continue;
  2625. }
  2626. }
  2627. }
  2628. /* Login and update database */
  2629. qla2x00_fabric_dev_login(vha, fcport, &next_loopid);
  2630. }
  2631. } while (0);
  2632. if (rval) {
  2633. ql_dbg(ql_dbg_disc, vha, 0x2068,
  2634. "Configure fabric error exit rval=%d.\n", rval);
  2635. }
  2636. return (rval);
  2637. }
  2638. /*
  2639. * qla2x00_find_all_fabric_devs
  2640. *
  2641. * Input:
  2642. * ha = adapter block pointer.
  2643. * dev = database device entry pointer.
  2644. *
  2645. * Returns:
  2646. * 0 = success.
  2647. *
  2648. * Context:
  2649. * Kernel context.
  2650. */
  2651. static int
  2652. qla2x00_find_all_fabric_devs(scsi_qla_host_t *vha,
  2653. struct list_head *new_fcports)
  2654. {
  2655. int rval;
  2656. uint16_t loop_id;
  2657. fc_port_t *fcport, *new_fcport, *fcptemp;
  2658. int found;
  2659. sw_info_t *swl;
  2660. int swl_idx;
  2661. int first_dev, last_dev;
  2662. port_id_t wrap = {}, nxt_d_id;
  2663. struct qla_hw_data *ha = vha->hw;
  2664. struct scsi_qla_host *vp, *base_vha = pci_get_drvdata(ha->pdev);
  2665. struct scsi_qla_host *tvp;
  2666. rval = QLA_SUCCESS;
  2667. /* Try GID_PT to get device list, else GAN. */
  2668. if (!ha->swl)
  2669. ha->swl = kcalloc(ha->max_fibre_devices, sizeof(sw_info_t),
  2670. GFP_KERNEL);
  2671. swl = ha->swl;
  2672. if (!swl) {
  2673. /*EMPTY*/
  2674. ql_dbg(ql_dbg_disc, vha, 0x2054,
  2675. "GID_PT allocations failed, fallback on GA_NXT.\n");
  2676. } else {
  2677. memset(swl, 0, ha->max_fibre_devices * sizeof(sw_info_t));
  2678. if (qla2x00_gid_pt(vha, swl) != QLA_SUCCESS) {
  2679. swl = NULL;
  2680. } else if (qla2x00_gpn_id(vha, swl) != QLA_SUCCESS) {
  2681. swl = NULL;
  2682. } else if (qla2x00_gnn_id(vha, swl) != QLA_SUCCESS) {
  2683. swl = NULL;
  2684. } else if (ql2xiidmaenable &&
  2685. qla2x00_gfpn_id(vha, swl) == QLA_SUCCESS) {
  2686. qla2x00_gpsc(vha, swl);
  2687. }
  2688. /* If other queries succeeded probe for FC-4 type */
  2689. if (swl)
  2690. qla2x00_gff_id(vha, swl);
  2691. }
  2692. swl_idx = 0;
  2693. /* Allocate temporary fcport for any new fcports discovered. */
  2694. new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
  2695. if (new_fcport == NULL) {
  2696. ql_log(ql_log_warn, vha, 0x205e,
  2697. "Failed to allocate memory for fcport.\n");
  2698. return (QLA_MEMORY_ALLOC_FAILED);
  2699. }
  2700. new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED);
  2701. /* Set start port ID scan at adapter ID. */
  2702. first_dev = 1;
  2703. last_dev = 0;
  2704. /* Starting free loop ID. */
  2705. loop_id = ha->min_external_loopid;
  2706. for (; loop_id <= ha->max_loop_id; loop_id++) {
  2707. if (qla2x00_is_reserved_id(vha, loop_id))
  2708. continue;
  2709. if (ha->current_topology == ISP_CFG_FL &&
  2710. (atomic_read(&vha->loop_down_timer) ||
  2711. LOOP_TRANSITION(vha))) {
  2712. atomic_set(&vha->loop_down_timer, 0);
  2713. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  2714. set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
  2715. break;
  2716. }
  2717. if (swl != NULL) {
  2718. if (last_dev) {
  2719. wrap.b24 = new_fcport->d_id.b24;
  2720. } else {
  2721. new_fcport->d_id.b24 = swl[swl_idx].d_id.b24;
  2722. memcpy(new_fcport->node_name,
  2723. swl[swl_idx].node_name, WWN_SIZE);
  2724. memcpy(new_fcport->port_name,
  2725. swl[swl_idx].port_name, WWN_SIZE);
  2726. memcpy(new_fcport->fabric_port_name,
  2727. swl[swl_idx].fabric_port_name, WWN_SIZE);
  2728. new_fcport->fp_speed = swl[swl_idx].fp_speed;
  2729. new_fcport->fc4_type = swl[swl_idx].fc4_type;
  2730. if (swl[swl_idx].d_id.b.rsvd_1 != 0) {
  2731. last_dev = 1;
  2732. }
  2733. swl_idx++;
  2734. }
  2735. } else {
  2736. /* Send GA_NXT to the switch */
  2737. rval = qla2x00_ga_nxt(vha, new_fcport);
  2738. if (rval != QLA_SUCCESS) {
  2739. ql_log(ql_log_warn, vha, 0x2064,
  2740. "SNS scan failed -- assuming "
  2741. "zero-entry result.\n");
  2742. list_for_each_entry_safe(fcport, fcptemp,
  2743. new_fcports, list) {
  2744. list_del(&fcport->list);
  2745. kfree(fcport);
  2746. }
  2747. rval = QLA_SUCCESS;
  2748. break;
  2749. }
  2750. }
  2751. /* If wrap on switch device list, exit. */
  2752. if (first_dev) {
  2753. wrap.b24 = new_fcport->d_id.b24;
  2754. first_dev = 0;
  2755. } else if (new_fcport->d_id.b24 == wrap.b24) {
  2756. ql_dbg(ql_dbg_disc, vha, 0x2065,
  2757. "Device wrap (%02x%02x%02x).\n",
  2758. new_fcport->d_id.b.domain,
  2759. new_fcport->d_id.b.area,
  2760. new_fcport->d_id.b.al_pa);
  2761. break;
  2762. }
  2763. /* Bypass if same physical adapter. */
  2764. if (new_fcport->d_id.b24 == base_vha->d_id.b24)
  2765. continue;
  2766. /* Bypass virtual ports of the same host. */
  2767. found = 0;
  2768. if (ha->num_vhosts) {
  2769. unsigned long flags;
  2770. spin_lock_irqsave(&ha->vport_slock, flags);
  2771. list_for_each_entry_safe(vp, tvp, &ha->vp_list, list) {
  2772. if (new_fcport->d_id.b24 == vp->d_id.b24) {
  2773. found = 1;
  2774. break;
  2775. }
  2776. }
  2777. spin_unlock_irqrestore(&ha->vport_slock, flags);
  2778. if (found)
  2779. continue;
  2780. }
  2781. /* Bypass if same domain and area of adapter. */
  2782. if (((new_fcport->d_id.b24 & 0xffff00) ==
  2783. (vha->d_id.b24 & 0xffff00)) && ha->current_topology ==
  2784. ISP_CFG_FL)
  2785. continue;
  2786. /* Bypass reserved domain fields. */
  2787. if ((new_fcport->d_id.b.domain & 0xf0) == 0xf0)
  2788. continue;
  2789. /* Bypass ports whose FCP-4 type is not FCP_SCSI */
  2790. if (ql2xgffidenable &&
  2791. (new_fcport->fc4_type != FC4_TYPE_FCP_SCSI &&
  2792. new_fcport->fc4_type != FC4_TYPE_UNKNOWN))
  2793. continue;
  2794. /* Locate matching device in database. */
  2795. found = 0;
  2796. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  2797. if (memcmp(new_fcport->port_name, fcport->port_name,
  2798. WWN_SIZE))
  2799. continue;
  2800. fcport->scan_state = QLA_FCPORT_SCAN_FOUND;
  2801. found++;
  2802. /* Update port state. */
  2803. memcpy(fcport->fabric_port_name,
  2804. new_fcport->fabric_port_name, WWN_SIZE);
  2805. fcport->fp_speed = new_fcport->fp_speed;
  2806. /*
  2807. * If address the same and state FCS_ONLINE, nothing
  2808. * changed.
  2809. */
  2810. if (fcport->d_id.b24 == new_fcport->d_id.b24 &&
  2811. atomic_read(&fcport->state) == FCS_ONLINE) {
  2812. break;
  2813. }
  2814. /*
  2815. * If device was not a fabric device before.
  2816. */
  2817. if ((fcport->flags & FCF_FABRIC_DEVICE) == 0) {
  2818. fcport->d_id.b24 = new_fcport->d_id.b24;
  2819. fcport->loop_id = FC_NO_LOOP_ID;
  2820. fcport->flags |= (FCF_FABRIC_DEVICE |
  2821. FCF_LOGIN_NEEDED);
  2822. break;
  2823. }
  2824. /*
  2825. * Port ID changed or device was marked to be updated;
  2826. * Log it out if still logged in and mark it for
  2827. * relogin later.
  2828. */
  2829. fcport->d_id.b24 = new_fcport->d_id.b24;
  2830. fcport->flags |= FCF_LOGIN_NEEDED;
  2831. if (fcport->loop_id != FC_NO_LOOP_ID &&
  2832. (fcport->flags & FCF_FCP2_DEVICE) == 0 &&
  2833. (fcport->flags & FCF_ASYNC_SENT) == 0 &&
  2834. fcport->port_type != FCT_INITIATOR &&
  2835. fcport->port_type != FCT_BROADCAST) {
  2836. ha->isp_ops->fabric_logout(vha, fcport->loop_id,
  2837. fcport->d_id.b.domain, fcport->d_id.b.area,
  2838. fcport->d_id.b.al_pa);
  2839. fcport->loop_id = FC_NO_LOOP_ID;
  2840. }
  2841. break;
  2842. }
  2843. if (found)
  2844. continue;
  2845. /* If device was not in our fcports list, then add it. */
  2846. list_add_tail(&new_fcport->list, new_fcports);
  2847. /* Allocate a new replacement fcport. */
  2848. nxt_d_id.b24 = new_fcport->d_id.b24;
  2849. new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
  2850. if (new_fcport == NULL) {
  2851. ql_log(ql_log_warn, vha, 0x2066,
  2852. "Memory allocation failed for fcport.\n");
  2853. return (QLA_MEMORY_ALLOC_FAILED);
  2854. }
  2855. new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED);
  2856. new_fcport->d_id.b24 = nxt_d_id.b24;
  2857. }
  2858. kfree(new_fcport);
  2859. return (rval);
  2860. }
  2861. /*
  2862. * qla2x00_find_new_loop_id
  2863. * Scan through our port list and find a new usable loop ID.
  2864. *
  2865. * Input:
  2866. * ha: adapter state pointer.
  2867. * dev: port structure pointer.
  2868. *
  2869. * Returns:
  2870. * qla2x00 local function return status code.
  2871. *
  2872. * Context:
  2873. * Kernel context.
  2874. */
  2875. int
  2876. qla2x00_find_new_loop_id(scsi_qla_host_t *vha, fc_port_t *dev)
  2877. {
  2878. int rval;
  2879. int found;
  2880. fc_port_t *fcport;
  2881. uint16_t first_loop_id;
  2882. struct qla_hw_data *ha = vha->hw;
  2883. struct scsi_qla_host *vp;
  2884. struct scsi_qla_host *tvp;
  2885. unsigned long flags = 0;
  2886. rval = QLA_SUCCESS;
  2887. /* Save starting loop ID. */
  2888. first_loop_id = dev->loop_id;
  2889. for (;;) {
  2890. /* Skip loop ID if already used by adapter. */
  2891. if (dev->loop_id == vha->loop_id)
  2892. dev->loop_id++;
  2893. /* Skip reserved loop IDs. */
  2894. while (qla2x00_is_reserved_id(vha, dev->loop_id))
  2895. dev->loop_id++;
  2896. /* Reset loop ID if passed the end. */
  2897. if (dev->loop_id > ha->max_loop_id) {
  2898. /* first loop ID. */
  2899. dev->loop_id = ha->min_external_loopid;
  2900. }
  2901. /* Check for loop ID being already in use. */
  2902. found = 0;
  2903. fcport = NULL;
  2904. spin_lock_irqsave(&ha->vport_slock, flags);
  2905. list_for_each_entry_safe(vp, tvp, &ha->vp_list, list) {
  2906. list_for_each_entry(fcport, &vp->vp_fcports, list) {
  2907. if (fcport->loop_id == dev->loop_id &&
  2908. fcport != dev) {
  2909. /* ID possibly in use */
  2910. found++;
  2911. break;
  2912. }
  2913. }
  2914. if (found)
  2915. break;
  2916. }
  2917. spin_unlock_irqrestore(&ha->vport_slock, flags);
  2918. /* If not in use then it is free to use. */
  2919. if (!found) {
  2920. ql_dbg(ql_dbg_disc, dev->vha, 0x2086,
  2921. "Assigning new loopid=%x, portid=%x.\n",
  2922. dev->loop_id, dev->d_id.b24);
  2923. break;
  2924. }
  2925. /* ID in use. Try next value. */
  2926. dev->loop_id++;
  2927. /* If wrap around. No free ID to use. */
  2928. if (dev->loop_id == first_loop_id) {
  2929. dev->loop_id = FC_NO_LOOP_ID;
  2930. rval = QLA_FUNCTION_FAILED;
  2931. break;
  2932. }
  2933. }
  2934. return (rval);
  2935. }
  2936. /*
  2937. * qla2x00_fabric_dev_login
  2938. * Login fabric target device and update FC port database.
  2939. *
  2940. * Input:
  2941. * ha: adapter state pointer.
  2942. * fcport: port structure list pointer.
  2943. * next_loopid: contains value of a new loop ID that can be used
  2944. * by the next login attempt.
  2945. *
  2946. * Returns:
  2947. * qla2x00 local function return status code.
  2948. *
  2949. * Context:
  2950. * Kernel context.
  2951. */
  2952. static int
  2953. qla2x00_fabric_dev_login(scsi_qla_host_t *vha, fc_port_t *fcport,
  2954. uint16_t *next_loopid)
  2955. {
  2956. int rval;
  2957. int retry;
  2958. uint8_t opts;
  2959. struct qla_hw_data *ha = vha->hw;
  2960. rval = QLA_SUCCESS;
  2961. retry = 0;
  2962. if (IS_ALOGIO_CAPABLE(ha)) {
  2963. if (fcport->flags & FCF_ASYNC_SENT)
  2964. return rval;
  2965. fcport->flags |= FCF_ASYNC_SENT;
  2966. rval = qla2x00_post_async_login_work(vha, fcport, NULL);
  2967. if (!rval)
  2968. return rval;
  2969. }
  2970. fcport->flags &= ~FCF_ASYNC_SENT;
  2971. rval = qla2x00_fabric_login(vha, fcport, next_loopid);
  2972. if (rval == QLA_SUCCESS) {
  2973. /* Send an ADISC to FCP2 devices.*/
  2974. opts = 0;
  2975. if (fcport->flags & FCF_FCP2_DEVICE)
  2976. opts |= BIT_1;
  2977. rval = qla2x00_get_port_database(vha, fcport, opts);
  2978. if (rval != QLA_SUCCESS) {
  2979. ha->isp_ops->fabric_logout(vha, fcport->loop_id,
  2980. fcport->d_id.b.domain, fcport->d_id.b.area,
  2981. fcport->d_id.b.al_pa);
  2982. qla2x00_mark_device_lost(vha, fcport, 1, 0);
  2983. } else {
  2984. qla2x00_update_fcport(vha, fcport);
  2985. }
  2986. } else {
  2987. /* Retry Login. */
  2988. qla2x00_mark_device_lost(vha, fcport, 1, 0);
  2989. }
  2990. return (rval);
  2991. }
  2992. /*
  2993. * qla2x00_fabric_login
  2994. * Issue fabric login command.
  2995. *
  2996. * Input:
  2997. * ha = adapter block pointer.
  2998. * device = pointer to FC device type structure.
  2999. *
  3000. * Returns:
  3001. * 0 - Login successfully
  3002. * 1 - Login failed
  3003. * 2 - Initiator device
  3004. * 3 - Fatal error
  3005. */
  3006. int
  3007. qla2x00_fabric_login(scsi_qla_host_t *vha, fc_port_t *fcport,
  3008. uint16_t *next_loopid)
  3009. {
  3010. int rval;
  3011. int retry;
  3012. uint16_t tmp_loopid;
  3013. uint16_t mb[MAILBOX_REGISTER_COUNT];
  3014. struct qla_hw_data *ha = vha->hw;
  3015. retry = 0;
  3016. tmp_loopid = 0;
  3017. for (;;) {
  3018. ql_dbg(ql_dbg_disc, vha, 0x2000,
  3019. "Trying Fabric Login w/loop id 0x%04x for port "
  3020. "%02x%02x%02x.\n",
  3021. fcport->loop_id, fcport->d_id.b.domain,
  3022. fcport->d_id.b.area, fcport->d_id.b.al_pa);
  3023. /* Login fcport on switch. */
  3024. rval = ha->isp_ops->fabric_login(vha, fcport->loop_id,
  3025. fcport->d_id.b.domain, fcport->d_id.b.area,
  3026. fcport->d_id.b.al_pa, mb, BIT_0);
  3027. if (rval != QLA_SUCCESS) {
  3028. return rval;
  3029. }
  3030. if (mb[0] == MBS_PORT_ID_USED) {
  3031. /*
  3032. * Device has another loop ID. The firmware team
  3033. * recommends the driver perform an implicit login with
  3034. * the specified ID again. The ID we just used is save
  3035. * here so we return with an ID that can be tried by
  3036. * the next login.
  3037. */
  3038. retry++;
  3039. tmp_loopid = fcport->loop_id;
  3040. fcport->loop_id = mb[1];
  3041. ql_dbg(ql_dbg_disc, vha, 0x2001,
  3042. "Fabric Login: port in use - next loop "
  3043. "id=0x%04x, port id= %02x%02x%02x.\n",
  3044. fcport->loop_id, fcport->d_id.b.domain,
  3045. fcport->d_id.b.area, fcport->d_id.b.al_pa);
  3046. } else if (mb[0] == MBS_COMMAND_COMPLETE) {
  3047. /*
  3048. * Login succeeded.
  3049. */
  3050. if (retry) {
  3051. /* A retry occurred before. */
  3052. *next_loopid = tmp_loopid;
  3053. } else {
  3054. /*
  3055. * No retry occurred before. Just increment the
  3056. * ID value for next login.
  3057. */
  3058. *next_loopid = (fcport->loop_id + 1);
  3059. }
  3060. if (mb[1] & BIT_0) {
  3061. fcport->port_type = FCT_INITIATOR;
  3062. } else {
  3063. fcport->port_type = FCT_TARGET;
  3064. if (mb[1] & BIT_1) {
  3065. fcport->flags |= FCF_FCP2_DEVICE;
  3066. }
  3067. }
  3068. if (mb[10] & BIT_0)
  3069. fcport->supported_classes |= FC_COS_CLASS2;
  3070. if (mb[10] & BIT_1)
  3071. fcport->supported_classes |= FC_COS_CLASS3;
  3072. if (IS_FWI2_CAPABLE(ha)) {
  3073. if (mb[10] & BIT_7)
  3074. fcport->flags |=
  3075. FCF_CONF_COMP_SUPPORTED;
  3076. }
  3077. rval = QLA_SUCCESS;
  3078. break;
  3079. } else if (mb[0] == MBS_LOOP_ID_USED) {
  3080. /*
  3081. * Loop ID already used, try next loop ID.
  3082. */
  3083. fcport->loop_id++;
  3084. rval = qla2x00_find_new_loop_id(vha, fcport);
  3085. if (rval != QLA_SUCCESS) {
  3086. /* Ran out of loop IDs to use */
  3087. break;
  3088. }
  3089. } else if (mb[0] == MBS_COMMAND_ERROR) {
  3090. /*
  3091. * Firmware possibly timed out during login. If NO
  3092. * retries are left to do then the device is declared
  3093. * dead.
  3094. */
  3095. *next_loopid = fcport->loop_id;
  3096. ha->isp_ops->fabric_logout(vha, fcport->loop_id,
  3097. fcport->d_id.b.domain, fcport->d_id.b.area,
  3098. fcport->d_id.b.al_pa);
  3099. qla2x00_mark_device_lost(vha, fcport, 1, 0);
  3100. rval = 1;
  3101. break;
  3102. } else {
  3103. /*
  3104. * unrecoverable / not handled error
  3105. */
  3106. ql_dbg(ql_dbg_disc, vha, 0x2002,
  3107. "Failed=%x port_id=%02x%02x%02x loop_id=%x "
  3108. "jiffies=%lx.\n", mb[0], fcport->d_id.b.domain,
  3109. fcport->d_id.b.area, fcport->d_id.b.al_pa,
  3110. fcport->loop_id, jiffies);
  3111. *next_loopid = fcport->loop_id;
  3112. ha->isp_ops->fabric_logout(vha, fcport->loop_id,
  3113. fcport->d_id.b.domain, fcport->d_id.b.area,
  3114. fcport->d_id.b.al_pa);
  3115. fcport->loop_id = FC_NO_LOOP_ID;
  3116. fcport->login_retry = 0;
  3117. rval = 3;
  3118. break;
  3119. }
  3120. }
  3121. return (rval);
  3122. }
  3123. /*
  3124. * qla2x00_local_device_login
  3125. * Issue local device login command.
  3126. *
  3127. * Input:
  3128. * ha = adapter block pointer.
  3129. * loop_id = loop id of device to login to.
  3130. *
  3131. * Returns (Where's the #define!!!!):
  3132. * 0 - Login successfully
  3133. * 1 - Login failed
  3134. * 3 - Fatal error
  3135. */
  3136. int
  3137. qla2x00_local_device_login(scsi_qla_host_t *vha, fc_port_t *fcport)
  3138. {
  3139. int rval;
  3140. uint16_t mb[MAILBOX_REGISTER_COUNT];
  3141. memset(mb, 0, sizeof(mb));
  3142. rval = qla2x00_login_local_device(vha, fcport, mb, BIT_0);
  3143. if (rval == QLA_SUCCESS) {
  3144. /* Interrogate mailbox registers for any errors */
  3145. if (mb[0] == MBS_COMMAND_ERROR)
  3146. rval = 1;
  3147. else if (mb[0] == MBS_COMMAND_PARAMETER_ERROR)
  3148. /* device not in PCB table */
  3149. rval = 3;
  3150. }
  3151. return (rval);
  3152. }
  3153. /*
  3154. * qla2x00_loop_resync
  3155. * Resync with fibre channel devices.
  3156. *
  3157. * Input:
  3158. * ha = adapter block pointer.
  3159. *
  3160. * Returns:
  3161. * 0 = success
  3162. */
  3163. int
  3164. qla2x00_loop_resync(scsi_qla_host_t *vha)
  3165. {
  3166. int rval = QLA_SUCCESS;
  3167. uint32_t wait_time;
  3168. struct req_que *req;
  3169. struct rsp_que *rsp;
  3170. if (vha->hw->flags.cpu_affinity_enabled)
  3171. req = vha->hw->req_q_map[0];
  3172. else
  3173. req = vha->req;
  3174. rsp = req->rsp;
  3175. clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
  3176. if (vha->flags.online) {
  3177. if (!(rval = qla2x00_fw_ready(vha))) {
  3178. /* Wait at most MAX_TARGET RSCNs for a stable link. */
  3179. wait_time = 256;
  3180. do {
  3181. /* Issue a marker after FW becomes ready. */
  3182. qla2x00_marker(vha, req, rsp, 0, 0,
  3183. MK_SYNC_ALL);
  3184. vha->marker_needed = 0;
  3185. /* Remap devices on Loop. */
  3186. clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  3187. qla2x00_configure_loop(vha);
  3188. wait_time--;
  3189. } while (!atomic_read(&vha->loop_down_timer) &&
  3190. !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
  3191. && wait_time && (test_bit(LOOP_RESYNC_NEEDED,
  3192. &vha->dpc_flags)));
  3193. }
  3194. }
  3195. if (test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
  3196. return (QLA_FUNCTION_FAILED);
  3197. if (rval)
  3198. ql_dbg(ql_dbg_disc, vha, 0x206c,
  3199. "%s *** FAILED ***.\n", __func__);
  3200. return (rval);
  3201. }
  3202. /*
  3203. * qla2x00_perform_loop_resync
  3204. * Description: This function will set the appropriate flags and call
  3205. * qla2x00_loop_resync. If successful loop will be resynced
  3206. * Arguments : scsi_qla_host_t pointer
  3207. * returm : Success or Failure
  3208. */
  3209. int qla2x00_perform_loop_resync(scsi_qla_host_t *ha)
  3210. {
  3211. int32_t rval = 0;
  3212. if (!test_and_set_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags)) {
  3213. /*Configure the flags so that resync happens properly*/
  3214. atomic_set(&ha->loop_down_timer, 0);
  3215. if (!(ha->device_flags & DFLG_NO_CABLE)) {
  3216. atomic_set(&ha->loop_state, LOOP_UP);
  3217. set_bit(LOCAL_LOOP_UPDATE, &ha->dpc_flags);
  3218. set_bit(REGISTER_FC4_NEEDED, &ha->dpc_flags);
  3219. set_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags);
  3220. rval = qla2x00_loop_resync(ha);
  3221. } else
  3222. atomic_set(&ha->loop_state, LOOP_DEAD);
  3223. clear_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags);
  3224. }
  3225. return rval;
  3226. }
  3227. void
  3228. qla2x00_update_fcports(scsi_qla_host_t *base_vha)
  3229. {
  3230. fc_port_t *fcport;
  3231. struct scsi_qla_host *vha;
  3232. struct qla_hw_data *ha = base_vha->hw;
  3233. unsigned long flags;
  3234. spin_lock_irqsave(&ha->vport_slock, flags);
  3235. /* Go with deferred removal of rport references. */
  3236. list_for_each_entry(vha, &base_vha->hw->vp_list, list) {
  3237. atomic_inc(&vha->vref_count);
  3238. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  3239. if (fcport->drport &&
  3240. atomic_read(&fcport->state) != FCS_UNCONFIGURED) {
  3241. spin_unlock_irqrestore(&ha->vport_slock, flags);
  3242. qla2x00_rport_del(fcport);
  3243. spin_lock_irqsave(&ha->vport_slock, flags);
  3244. }
  3245. }
  3246. atomic_dec(&vha->vref_count);
  3247. }
  3248. spin_unlock_irqrestore(&ha->vport_slock, flags);
  3249. }
  3250. /*
  3251. * qla82xx_quiescent_state_cleanup
  3252. * Description: This function will block the new I/Os
  3253. * Its not aborting any I/Os as context
  3254. * is not destroyed during quiescence
  3255. * Arguments: scsi_qla_host_t
  3256. * return : void
  3257. */
  3258. void
  3259. qla82xx_quiescent_state_cleanup(scsi_qla_host_t *vha)
  3260. {
  3261. struct qla_hw_data *ha = vha->hw;
  3262. struct scsi_qla_host *vp;
  3263. ql_dbg(ql_dbg_p3p, vha, 0xb002,
  3264. "Performing ISP error recovery - ha=%p.\n", ha);
  3265. atomic_set(&ha->loop_down_timer, LOOP_DOWN_TIME);
  3266. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  3267. atomic_set(&vha->loop_state, LOOP_DOWN);
  3268. qla2x00_mark_all_devices_lost(vha, 0);
  3269. list_for_each_entry(vp, &ha->vp_list, list)
  3270. qla2x00_mark_all_devices_lost(vha, 0);
  3271. } else {
  3272. if (!atomic_read(&vha->loop_down_timer))
  3273. atomic_set(&vha->loop_down_timer,
  3274. LOOP_DOWN_TIME);
  3275. }
  3276. /* Wait for pending cmds to complete */
  3277. qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST);
  3278. }
  3279. void
  3280. qla2x00_abort_isp_cleanup(scsi_qla_host_t *vha)
  3281. {
  3282. struct qla_hw_data *ha = vha->hw;
  3283. struct scsi_qla_host *vp;
  3284. unsigned long flags;
  3285. fc_port_t *fcport;
  3286. /* For ISP82XX, driver waits for completion of the commands.
  3287. * online flag should be set.
  3288. */
  3289. if (!IS_QLA82XX(ha))
  3290. vha->flags.online = 0;
  3291. ha->flags.chip_reset_done = 0;
  3292. clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  3293. vha->qla_stats.total_isp_aborts++;
  3294. ql_log(ql_log_info, vha, 0x00af,
  3295. "Performing ISP error recovery - ha=%p.\n", ha);
  3296. /* For ISP82XX, reset_chip is just disabling interrupts.
  3297. * Driver waits for the completion of the commands.
  3298. * the interrupts need to be enabled.
  3299. */
  3300. if (!IS_QLA82XX(ha))
  3301. ha->isp_ops->reset_chip(vha);
  3302. atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
  3303. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  3304. atomic_set(&vha->loop_state, LOOP_DOWN);
  3305. qla2x00_mark_all_devices_lost(vha, 0);
  3306. spin_lock_irqsave(&ha->vport_slock, flags);
  3307. list_for_each_entry(vp, &ha->vp_list, list) {
  3308. atomic_inc(&vp->vref_count);
  3309. spin_unlock_irqrestore(&ha->vport_slock, flags);
  3310. qla2x00_mark_all_devices_lost(vp, 0);
  3311. spin_lock_irqsave(&ha->vport_slock, flags);
  3312. atomic_dec(&vp->vref_count);
  3313. }
  3314. spin_unlock_irqrestore(&ha->vport_slock, flags);
  3315. } else {
  3316. if (!atomic_read(&vha->loop_down_timer))
  3317. atomic_set(&vha->loop_down_timer,
  3318. LOOP_DOWN_TIME);
  3319. }
  3320. /* Clear all async request states across all VPs. */
  3321. list_for_each_entry(fcport, &vha->vp_fcports, list)
  3322. fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
  3323. spin_lock_irqsave(&ha->vport_slock, flags);
  3324. list_for_each_entry(vp, &ha->vp_list, list) {
  3325. atomic_inc(&vp->vref_count);
  3326. spin_unlock_irqrestore(&ha->vport_slock, flags);
  3327. list_for_each_entry(fcport, &vp->vp_fcports, list)
  3328. fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
  3329. spin_lock_irqsave(&ha->vport_slock, flags);
  3330. atomic_dec(&vp->vref_count);
  3331. }
  3332. spin_unlock_irqrestore(&ha->vport_slock, flags);
  3333. if (!ha->flags.eeh_busy) {
  3334. /* Make sure for ISP 82XX IO DMA is complete */
  3335. if (IS_QLA82XX(ha)) {
  3336. qla82xx_chip_reset_cleanup(vha);
  3337. ql_log(ql_log_info, vha, 0x00b4,
  3338. "Done chip reset cleanup.\n");
  3339. /* Done waiting for pending commands.
  3340. * Reset the online flag.
  3341. */
  3342. vha->flags.online = 0;
  3343. }
  3344. /* Requeue all commands in outstanding command list. */
  3345. qla2x00_abort_all_cmds(vha, DID_RESET << 16);
  3346. }
  3347. }
  3348. /*
  3349. * qla2x00_abort_isp
  3350. * Resets ISP and aborts all outstanding commands.
  3351. *
  3352. * Input:
  3353. * ha = adapter block pointer.
  3354. *
  3355. * Returns:
  3356. * 0 = success
  3357. */
  3358. int
  3359. qla2x00_abort_isp(scsi_qla_host_t *vha)
  3360. {
  3361. int rval;
  3362. uint8_t status = 0;
  3363. struct qla_hw_data *ha = vha->hw;
  3364. struct scsi_qla_host *vp;
  3365. struct req_que *req = ha->req_q_map[0];
  3366. unsigned long flags;
  3367. if (vha->flags.online) {
  3368. qla2x00_abort_isp_cleanup(vha);
  3369. if (unlikely(pci_channel_offline(ha->pdev) &&
  3370. ha->flags.pci_channel_io_perm_failure)) {
  3371. clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
  3372. status = 0;
  3373. return status;
  3374. }
  3375. ha->isp_ops->get_flash_version(vha, req->ring);
  3376. ha->isp_ops->nvram_config(vha);
  3377. if (!qla2x00_restart_isp(vha)) {
  3378. clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
  3379. if (!atomic_read(&vha->loop_down_timer)) {
  3380. /*
  3381. * Issue marker command only when we are going
  3382. * to start the I/O .
  3383. */
  3384. vha->marker_needed = 1;
  3385. }
  3386. vha->flags.online = 1;
  3387. ha->isp_ops->enable_intrs(ha);
  3388. ha->isp_abort_cnt = 0;
  3389. clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
  3390. if (IS_QLA81XX(ha) || IS_QLA8031(ha))
  3391. qla2x00_get_fw_version(vha);
  3392. if (ha->fce) {
  3393. ha->flags.fce_enabled = 1;
  3394. memset(ha->fce, 0,
  3395. fce_calc_size(ha->fce_bufs));
  3396. rval = qla2x00_enable_fce_trace(vha,
  3397. ha->fce_dma, ha->fce_bufs, ha->fce_mb,
  3398. &ha->fce_bufs);
  3399. if (rval) {
  3400. ql_log(ql_log_warn, vha, 0x8033,
  3401. "Unable to reinitialize FCE "
  3402. "(%d).\n", rval);
  3403. ha->flags.fce_enabled = 0;
  3404. }
  3405. }
  3406. if (ha->eft) {
  3407. memset(ha->eft, 0, EFT_SIZE);
  3408. rval = qla2x00_enable_eft_trace(vha,
  3409. ha->eft_dma, EFT_NUM_BUFFERS);
  3410. if (rval) {
  3411. ql_log(ql_log_warn, vha, 0x8034,
  3412. "Unable to reinitialize EFT "
  3413. "(%d).\n", rval);
  3414. }
  3415. }
  3416. } else { /* failed the ISP abort */
  3417. vha->flags.online = 1;
  3418. if (test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
  3419. if (ha->isp_abort_cnt == 0) {
  3420. ql_log(ql_log_fatal, vha, 0x8035,
  3421. "ISP error recover failed - "
  3422. "board disabled.\n");
  3423. /*
  3424. * The next call disables the board
  3425. * completely.
  3426. */
  3427. ha->isp_ops->reset_adapter(vha);
  3428. vha->flags.online = 0;
  3429. clear_bit(ISP_ABORT_RETRY,
  3430. &vha->dpc_flags);
  3431. status = 0;
  3432. } else { /* schedule another ISP abort */
  3433. ha->isp_abort_cnt--;
  3434. ql_dbg(ql_dbg_taskm, vha, 0x8020,
  3435. "ISP abort - retry remaining %d.\n",
  3436. ha->isp_abort_cnt);
  3437. status = 1;
  3438. }
  3439. } else {
  3440. ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT;
  3441. ql_dbg(ql_dbg_taskm, vha, 0x8021,
  3442. "ISP error recovery - retrying (%d) "
  3443. "more times.\n", ha->isp_abort_cnt);
  3444. set_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
  3445. status = 1;
  3446. }
  3447. }
  3448. }
  3449. if (!status) {
  3450. ql_dbg(ql_dbg_taskm, vha, 0x8022, "%s succeeded.\n", __func__);
  3451. spin_lock_irqsave(&ha->vport_slock, flags);
  3452. list_for_each_entry(vp, &ha->vp_list, list) {
  3453. if (vp->vp_idx) {
  3454. atomic_inc(&vp->vref_count);
  3455. spin_unlock_irqrestore(&ha->vport_slock, flags);
  3456. qla2x00_vp_abort_isp(vp);
  3457. spin_lock_irqsave(&ha->vport_slock, flags);
  3458. atomic_dec(&vp->vref_count);
  3459. }
  3460. }
  3461. spin_unlock_irqrestore(&ha->vport_slock, flags);
  3462. } else {
  3463. ql_log(ql_log_warn, vha, 0x8023, "%s **** FAILED ****.\n",
  3464. __func__);
  3465. }
  3466. return(status);
  3467. }
  3468. /*
  3469. * qla2x00_restart_isp
  3470. * restarts the ISP after a reset
  3471. *
  3472. * Input:
  3473. * ha = adapter block pointer.
  3474. *
  3475. * Returns:
  3476. * 0 = success
  3477. */
  3478. static int
  3479. qla2x00_restart_isp(scsi_qla_host_t *vha)
  3480. {
  3481. int status = 0;
  3482. uint32_t wait_time;
  3483. struct qla_hw_data *ha = vha->hw;
  3484. struct req_que *req = ha->req_q_map[0];
  3485. struct rsp_que *rsp = ha->rsp_q_map[0];
  3486. unsigned long flags;
  3487. /* If firmware needs to be loaded */
  3488. if (qla2x00_isp_firmware(vha)) {
  3489. vha->flags.online = 0;
  3490. status = ha->isp_ops->chip_diag(vha);
  3491. if (!status)
  3492. status = qla2x00_setup_chip(vha);
  3493. }
  3494. if (!status && !(status = qla2x00_init_rings(vha))) {
  3495. clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
  3496. ha->flags.chip_reset_done = 1;
  3497. /* Initialize the queues in use */
  3498. qla25xx_init_queues(ha);
  3499. status = qla2x00_fw_ready(vha);
  3500. if (!status) {
  3501. ql_dbg(ql_dbg_taskm, vha, 0x8031,
  3502. "Start configure loop status = %d.\n", status);
  3503. /* Issue a marker after FW becomes ready. */
  3504. qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
  3505. vha->flags.online = 1;
  3506. /*
  3507. * Process any ATIO queue entries that came in
  3508. * while we weren't online.
  3509. */
  3510. spin_lock_irqsave(&ha->hardware_lock, flags);
  3511. if (qla_tgt_mode_enabled(vha))
  3512. qlt_24xx_process_atio_queue(vha);
  3513. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  3514. /* Wait at most MAX_TARGET RSCNs for a stable link. */
  3515. wait_time = 256;
  3516. do {
  3517. clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  3518. qla2x00_configure_loop(vha);
  3519. wait_time--;
  3520. } while (!atomic_read(&vha->loop_down_timer) &&
  3521. !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
  3522. && wait_time && (test_bit(LOOP_RESYNC_NEEDED,
  3523. &vha->dpc_flags)));
  3524. }
  3525. /* if no cable then assume it's good */
  3526. if ((vha->device_flags & DFLG_NO_CABLE))
  3527. status = 0;
  3528. ql_dbg(ql_dbg_taskm, vha, 0x8032,
  3529. "Configure loop done, status = 0x%x.\n", status);
  3530. }
  3531. return (status);
  3532. }
  3533. static int
  3534. qla25xx_init_queues(struct qla_hw_data *ha)
  3535. {
  3536. struct rsp_que *rsp = NULL;
  3537. struct req_que *req = NULL;
  3538. struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
  3539. int ret = -1;
  3540. int i;
  3541. for (i = 1; i < ha->max_rsp_queues; i++) {
  3542. rsp = ha->rsp_q_map[i];
  3543. if (rsp) {
  3544. rsp->options &= ~BIT_0;
  3545. ret = qla25xx_init_rsp_que(base_vha, rsp);
  3546. if (ret != QLA_SUCCESS)
  3547. ql_dbg(ql_dbg_init, base_vha, 0x00ff,
  3548. "%s Rsp que: %d init failed.\n",
  3549. __func__, rsp->id);
  3550. else
  3551. ql_dbg(ql_dbg_init, base_vha, 0x0100,
  3552. "%s Rsp que: %d inited.\n",
  3553. __func__, rsp->id);
  3554. }
  3555. }
  3556. for (i = 1; i < ha->max_req_queues; i++) {
  3557. req = ha->req_q_map[i];
  3558. if (req) {
  3559. /* Clear outstanding commands array. */
  3560. req->options &= ~BIT_0;
  3561. ret = qla25xx_init_req_que(base_vha, req);
  3562. if (ret != QLA_SUCCESS)
  3563. ql_dbg(ql_dbg_init, base_vha, 0x0101,
  3564. "%s Req que: %d init failed.\n",
  3565. __func__, req->id);
  3566. else
  3567. ql_dbg(ql_dbg_init, base_vha, 0x0102,
  3568. "%s Req que: %d inited.\n",
  3569. __func__, req->id);
  3570. }
  3571. }
  3572. return ret;
  3573. }
  3574. /*
  3575. * qla2x00_reset_adapter
  3576. * Reset adapter.
  3577. *
  3578. * Input:
  3579. * ha = adapter block pointer.
  3580. */
  3581. void
  3582. qla2x00_reset_adapter(scsi_qla_host_t *vha)
  3583. {
  3584. unsigned long flags = 0;
  3585. struct qla_hw_data *ha = vha->hw;
  3586. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  3587. vha->flags.online = 0;
  3588. ha->isp_ops->disable_intrs(ha);
  3589. spin_lock_irqsave(&ha->hardware_lock, flags);
  3590. WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
  3591. RD_REG_WORD(&reg->hccr); /* PCI Posting. */
  3592. WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
  3593. RD_REG_WORD(&reg->hccr); /* PCI Posting. */
  3594. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  3595. }
  3596. void
  3597. qla24xx_reset_adapter(scsi_qla_host_t *vha)
  3598. {
  3599. unsigned long flags = 0;
  3600. struct qla_hw_data *ha = vha->hw;
  3601. struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
  3602. if (IS_QLA82XX(ha))
  3603. return;
  3604. vha->flags.online = 0;
  3605. ha->isp_ops->disable_intrs(ha);
  3606. spin_lock_irqsave(&ha->hardware_lock, flags);
  3607. WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
  3608. RD_REG_DWORD(&reg->hccr);
  3609. WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
  3610. RD_REG_DWORD(&reg->hccr);
  3611. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  3612. if (IS_NOPOLLING_TYPE(ha))
  3613. ha->isp_ops->enable_intrs(ha);
  3614. }
  3615. /* On sparc systems, obtain port and node WWN from firmware
  3616. * properties.
  3617. */
  3618. static void qla24xx_nvram_wwn_from_ofw(scsi_qla_host_t *vha,
  3619. struct nvram_24xx *nv)
  3620. {
  3621. #ifdef CONFIG_SPARC
  3622. struct qla_hw_data *ha = vha->hw;
  3623. struct pci_dev *pdev = ha->pdev;
  3624. struct device_node *dp = pci_device_to_OF_node(pdev);
  3625. const u8 *val;
  3626. int len;
  3627. val = of_get_property(dp, "port-wwn", &len);
  3628. if (val && len >= WWN_SIZE)
  3629. memcpy(nv->port_name, val, WWN_SIZE);
  3630. val = of_get_property(dp, "node-wwn", &len);
  3631. if (val && len >= WWN_SIZE)
  3632. memcpy(nv->node_name, val, WWN_SIZE);
  3633. #endif
  3634. }
  3635. int
  3636. qla24xx_nvram_config(scsi_qla_host_t *vha)
  3637. {
  3638. int rval;
  3639. struct init_cb_24xx *icb;
  3640. struct nvram_24xx *nv;
  3641. uint32_t *dptr;
  3642. uint8_t *dptr1, *dptr2;
  3643. uint32_t chksum;
  3644. uint16_t cnt;
  3645. struct qla_hw_data *ha = vha->hw;
  3646. rval = QLA_SUCCESS;
  3647. icb = (struct init_cb_24xx *)ha->init_cb;
  3648. nv = ha->nvram;
  3649. /* Determine NVRAM starting address. */
  3650. if (ha->flags.port0) {
  3651. ha->nvram_base = FA_NVRAM_FUNC0_ADDR;
  3652. ha->vpd_base = FA_NVRAM_VPD0_ADDR;
  3653. } else {
  3654. ha->nvram_base = FA_NVRAM_FUNC1_ADDR;
  3655. ha->vpd_base = FA_NVRAM_VPD1_ADDR;
  3656. }
  3657. ha->nvram_size = sizeof(struct nvram_24xx);
  3658. ha->vpd_size = FA_NVRAM_VPD_SIZE;
  3659. if (IS_QLA82XX(ha))
  3660. ha->vpd_size = FA_VPD_SIZE_82XX;
  3661. /* Get VPD data into cache */
  3662. ha->vpd = ha->nvram + VPD_OFFSET;
  3663. ha->isp_ops->read_nvram(vha, (uint8_t *)ha->vpd,
  3664. ha->nvram_base - FA_NVRAM_FUNC0_ADDR, FA_NVRAM_VPD_SIZE * 4);
  3665. /* Get NVRAM data into cache and calculate checksum. */
  3666. dptr = (uint32_t *)nv;
  3667. ha->isp_ops->read_nvram(vha, (uint8_t *)dptr, ha->nvram_base,
  3668. ha->nvram_size);
  3669. for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++)
  3670. chksum += le32_to_cpu(*dptr++);
  3671. ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x006a,
  3672. "Contents of NVRAM\n");
  3673. ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010d,
  3674. (uint8_t *)nv, ha->nvram_size);
  3675. /* Bad NVRAM data, set defaults parameters. */
  3676. if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P'
  3677. || nv->id[3] != ' ' ||
  3678. nv->nvram_version < __constant_cpu_to_le16(ICB_VERSION)) {
  3679. /* Reset NVRAM data. */
  3680. ql_log(ql_log_warn, vha, 0x006b,
  3681. "Inconsistent NVRAM detected: checksum=0x%x id=%c "
  3682. "version=0x%x.\n", chksum, nv->id[0], nv->nvram_version);
  3683. ql_log(ql_log_warn, vha, 0x006c,
  3684. "Falling back to functioning (yet invalid -- WWPN) "
  3685. "defaults.\n");
  3686. /*
  3687. * Set default initialization control block.
  3688. */
  3689. memset(nv, 0, ha->nvram_size);
  3690. nv->nvram_version = __constant_cpu_to_le16(ICB_VERSION);
  3691. nv->version = __constant_cpu_to_le16(ICB_VERSION);
  3692. nv->frame_payload_size = __constant_cpu_to_le16(2048);
  3693. nv->execution_throttle = __constant_cpu_to_le16(0xFFFF);
  3694. nv->exchange_count = __constant_cpu_to_le16(0);
  3695. nv->hard_address = __constant_cpu_to_le16(124);
  3696. nv->port_name[0] = 0x21;
  3697. nv->port_name[1] = 0x00 + ha->port_no;
  3698. nv->port_name[2] = 0x00;
  3699. nv->port_name[3] = 0xe0;
  3700. nv->port_name[4] = 0x8b;
  3701. nv->port_name[5] = 0x1c;
  3702. nv->port_name[6] = 0x55;
  3703. nv->port_name[7] = 0x86;
  3704. nv->node_name[0] = 0x20;
  3705. nv->node_name[1] = 0x00;
  3706. nv->node_name[2] = 0x00;
  3707. nv->node_name[3] = 0xe0;
  3708. nv->node_name[4] = 0x8b;
  3709. nv->node_name[5] = 0x1c;
  3710. nv->node_name[6] = 0x55;
  3711. nv->node_name[7] = 0x86;
  3712. qla24xx_nvram_wwn_from_ofw(vha, nv);
  3713. nv->login_retry_count = __constant_cpu_to_le16(8);
  3714. nv->interrupt_delay_timer = __constant_cpu_to_le16(0);
  3715. nv->login_timeout = __constant_cpu_to_le16(0);
  3716. nv->firmware_options_1 =
  3717. __constant_cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1);
  3718. nv->firmware_options_2 = __constant_cpu_to_le32(2 << 4);
  3719. nv->firmware_options_2 |= __constant_cpu_to_le32(BIT_12);
  3720. nv->firmware_options_3 = __constant_cpu_to_le32(2 << 13);
  3721. nv->host_p = __constant_cpu_to_le32(BIT_11|BIT_10);
  3722. nv->efi_parameters = __constant_cpu_to_le32(0);
  3723. nv->reset_delay = 5;
  3724. nv->max_luns_per_target = __constant_cpu_to_le16(128);
  3725. nv->port_down_retry_count = __constant_cpu_to_le16(30);
  3726. nv->link_down_timeout = __constant_cpu_to_le16(30);
  3727. rval = 1;
  3728. }
  3729. if (!qla_ini_mode_enabled(vha)) {
  3730. /* Don't enable full login after initial LIP */
  3731. nv->firmware_options_1 &= __constant_cpu_to_le32(~BIT_13);
  3732. /* Don't enable LIP full login for initiator */
  3733. nv->host_p &= __constant_cpu_to_le32(~BIT_10);
  3734. }
  3735. qlt_24xx_config_nvram_stage1(vha, nv);
  3736. /* Reset Initialization control block */
  3737. memset(icb, 0, ha->init_cb_size);
  3738. /* Copy 1st segment. */
  3739. dptr1 = (uint8_t *)icb;
  3740. dptr2 = (uint8_t *)&nv->version;
  3741. cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version;
  3742. while (cnt--)
  3743. *dptr1++ = *dptr2++;
  3744. icb->login_retry_count = nv->login_retry_count;
  3745. icb->link_down_on_nos = nv->link_down_on_nos;
  3746. /* Copy 2nd segment. */
  3747. dptr1 = (uint8_t *)&icb->interrupt_delay_timer;
  3748. dptr2 = (uint8_t *)&nv->interrupt_delay_timer;
  3749. cnt = (uint8_t *)&icb->reserved_3 -
  3750. (uint8_t *)&icb->interrupt_delay_timer;
  3751. while (cnt--)
  3752. *dptr1++ = *dptr2++;
  3753. /*
  3754. * Setup driver NVRAM options.
  3755. */
  3756. qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name),
  3757. "QLA2462");
  3758. qlt_24xx_config_nvram_stage2(vha, icb);
  3759. if (nv->host_p & __constant_cpu_to_le32(BIT_15)) {
  3760. /* Use alternate WWN? */
  3761. memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
  3762. memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
  3763. }
  3764. /* Prepare nodename */
  3765. if ((icb->firmware_options_1 & __constant_cpu_to_le32(BIT_14)) == 0) {
  3766. /*
  3767. * Firmware will apply the following mask if the nodename was
  3768. * not provided.
  3769. */
  3770. memcpy(icb->node_name, icb->port_name, WWN_SIZE);
  3771. icb->node_name[0] &= 0xF0;
  3772. }
  3773. /* Set host adapter parameters. */
  3774. ha->flags.disable_risc_code_load = 0;
  3775. ha->flags.enable_lip_reset = 0;
  3776. ha->flags.enable_lip_full_login =
  3777. le32_to_cpu(nv->host_p) & BIT_10 ? 1: 0;
  3778. ha->flags.enable_target_reset =
  3779. le32_to_cpu(nv->host_p) & BIT_11 ? 1: 0;
  3780. ha->flags.enable_led_scheme = 0;
  3781. ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1: 0;
  3782. ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) &
  3783. (BIT_6 | BIT_5 | BIT_4)) >> 4;
  3784. memcpy(ha->fw_seriallink_options24, nv->seriallink_options,
  3785. sizeof(ha->fw_seriallink_options24));
  3786. /* save HBA serial number */
  3787. ha->serial0 = icb->port_name[5];
  3788. ha->serial1 = icb->port_name[6];
  3789. ha->serial2 = icb->port_name[7];
  3790. memcpy(vha->node_name, icb->node_name, WWN_SIZE);
  3791. memcpy(vha->port_name, icb->port_name, WWN_SIZE);
  3792. icb->execution_throttle = __constant_cpu_to_le16(0xFFFF);
  3793. ha->retry_count = le16_to_cpu(nv->login_retry_count);
  3794. /* Set minimum login_timeout to 4 seconds. */
  3795. if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout)
  3796. nv->login_timeout = cpu_to_le16(ql2xlogintimeout);
  3797. if (le16_to_cpu(nv->login_timeout) < 4)
  3798. nv->login_timeout = __constant_cpu_to_le16(4);
  3799. ha->login_timeout = le16_to_cpu(nv->login_timeout);
  3800. icb->login_timeout = nv->login_timeout;
  3801. /* Set minimum RATOV to 100 tenths of a second. */
  3802. ha->r_a_tov = 100;
  3803. ha->loop_reset_delay = nv->reset_delay;
  3804. /* Link Down Timeout = 0:
  3805. *
  3806. * When Port Down timer expires we will start returning
  3807. * I/O's to OS with "DID_NO_CONNECT".
  3808. *
  3809. * Link Down Timeout != 0:
  3810. *
  3811. * The driver waits for the link to come up after link down
  3812. * before returning I/Os to OS with "DID_NO_CONNECT".
  3813. */
  3814. if (le16_to_cpu(nv->link_down_timeout) == 0) {
  3815. ha->loop_down_abort_time =
  3816. (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
  3817. } else {
  3818. ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout);
  3819. ha->loop_down_abort_time =
  3820. (LOOP_DOWN_TIME - ha->link_down_timeout);
  3821. }
  3822. /* Need enough time to try and get the port back. */
  3823. ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count);
  3824. if (qlport_down_retry)
  3825. ha->port_down_retry_count = qlport_down_retry;
  3826. /* Set login_retry_count */
  3827. ha->login_retry_count = le16_to_cpu(nv->login_retry_count);
  3828. if (ha->port_down_retry_count ==
  3829. le16_to_cpu(nv->port_down_retry_count) &&
  3830. ha->port_down_retry_count > 3)
  3831. ha->login_retry_count = ha->port_down_retry_count;
  3832. else if (ha->port_down_retry_count > (int)ha->login_retry_count)
  3833. ha->login_retry_count = ha->port_down_retry_count;
  3834. if (ql2xloginretrycount)
  3835. ha->login_retry_count = ql2xloginretrycount;
  3836. /* Enable ZIO. */
  3837. if (!vha->flags.init_done) {
  3838. ha->zio_mode = le32_to_cpu(icb->firmware_options_2) &
  3839. (BIT_3 | BIT_2 | BIT_1 | BIT_0);
  3840. ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ?
  3841. le16_to_cpu(icb->interrupt_delay_timer): 2;
  3842. }
  3843. icb->firmware_options_2 &= __constant_cpu_to_le32(
  3844. ~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
  3845. vha->flags.process_response_queue = 0;
  3846. if (ha->zio_mode != QLA_ZIO_DISABLED) {
  3847. ha->zio_mode = QLA_ZIO_MODE_6;
  3848. ql_log(ql_log_info, vha, 0x006f,
  3849. "ZIO mode %d enabled; timer delay (%d us).\n",
  3850. ha->zio_mode, ha->zio_timer * 100);
  3851. icb->firmware_options_2 |= cpu_to_le32(
  3852. (uint32_t)ha->zio_mode);
  3853. icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer);
  3854. vha->flags.process_response_queue = 1;
  3855. }
  3856. if (rval) {
  3857. ql_log(ql_log_warn, vha, 0x0070,
  3858. "NVRAM configuration failed.\n");
  3859. }
  3860. return (rval);
  3861. }
  3862. static int
  3863. qla24xx_load_risc_flash(scsi_qla_host_t *vha, uint32_t *srisc_addr,
  3864. uint32_t faddr)
  3865. {
  3866. int rval = QLA_SUCCESS;
  3867. int segments, fragment;
  3868. uint32_t *dcode, dlen;
  3869. uint32_t risc_addr;
  3870. uint32_t risc_size;
  3871. uint32_t i;
  3872. struct qla_hw_data *ha = vha->hw;
  3873. struct req_que *req = ha->req_q_map[0];
  3874. ql_dbg(ql_dbg_init, vha, 0x008b,
  3875. "FW: Loading firmware from flash (%x).\n", faddr);
  3876. rval = QLA_SUCCESS;
  3877. segments = FA_RISC_CODE_SEGMENTS;
  3878. dcode = (uint32_t *)req->ring;
  3879. *srisc_addr = 0;
  3880. /* Validate firmware image by checking version. */
  3881. qla24xx_read_flash_data(vha, dcode, faddr + 4, 4);
  3882. for (i = 0; i < 4; i++)
  3883. dcode[i] = be32_to_cpu(dcode[i]);
  3884. if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
  3885. dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
  3886. (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
  3887. dcode[3] == 0)) {
  3888. ql_log(ql_log_fatal, vha, 0x008c,
  3889. "Unable to verify the integrity of flash firmware "
  3890. "image.\n");
  3891. ql_log(ql_log_fatal, vha, 0x008d,
  3892. "Firmware data: %08x %08x %08x %08x.\n",
  3893. dcode[0], dcode[1], dcode[2], dcode[3]);
  3894. return QLA_FUNCTION_FAILED;
  3895. }
  3896. while (segments && rval == QLA_SUCCESS) {
  3897. /* Read segment's load information. */
  3898. qla24xx_read_flash_data(vha, dcode, faddr, 4);
  3899. risc_addr = be32_to_cpu(dcode[2]);
  3900. *srisc_addr = *srisc_addr == 0 ? risc_addr : *srisc_addr;
  3901. risc_size = be32_to_cpu(dcode[3]);
  3902. fragment = 0;
  3903. while (risc_size > 0 && rval == QLA_SUCCESS) {
  3904. dlen = (uint32_t)(ha->fw_transfer_size >> 2);
  3905. if (dlen > risc_size)
  3906. dlen = risc_size;
  3907. ql_dbg(ql_dbg_init, vha, 0x008e,
  3908. "Loading risc segment@ risc addr %x "
  3909. "number of dwords 0x%x offset 0x%x.\n",
  3910. risc_addr, dlen, faddr);
  3911. qla24xx_read_flash_data(vha, dcode, faddr, dlen);
  3912. for (i = 0; i < dlen; i++)
  3913. dcode[i] = swab32(dcode[i]);
  3914. rval = qla2x00_load_ram(vha, req->dma, risc_addr,
  3915. dlen);
  3916. if (rval) {
  3917. ql_log(ql_log_fatal, vha, 0x008f,
  3918. "Failed to load segment %d of firmware.\n",
  3919. fragment);
  3920. break;
  3921. }
  3922. faddr += dlen;
  3923. risc_addr += dlen;
  3924. risc_size -= dlen;
  3925. fragment++;
  3926. }
  3927. /* Next segment. */
  3928. segments--;
  3929. }
  3930. return rval;
  3931. }
  3932. #define QLA_FW_URL "ftp://ftp.qlogic.com/outgoing/linux/firmware/"
  3933. int
  3934. qla2x00_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
  3935. {
  3936. int rval;
  3937. int i, fragment;
  3938. uint16_t *wcode, *fwcode;
  3939. uint32_t risc_addr, risc_size, fwclen, wlen, *seg;
  3940. struct fw_blob *blob;
  3941. struct qla_hw_data *ha = vha->hw;
  3942. struct req_que *req = ha->req_q_map[0];
  3943. /* Load firmware blob. */
  3944. blob = qla2x00_request_firmware(vha);
  3945. if (!blob) {
  3946. ql_log(ql_log_info, vha, 0x0083,
  3947. "Fimware image unavailable.\n");
  3948. ql_log(ql_log_info, vha, 0x0084,
  3949. "Firmware images can be retrieved from: "QLA_FW_URL ".\n");
  3950. return QLA_FUNCTION_FAILED;
  3951. }
  3952. rval = QLA_SUCCESS;
  3953. wcode = (uint16_t *)req->ring;
  3954. *srisc_addr = 0;
  3955. fwcode = (uint16_t *)blob->fw->data;
  3956. fwclen = 0;
  3957. /* Validate firmware image by checking version. */
  3958. if (blob->fw->size < 8 * sizeof(uint16_t)) {
  3959. ql_log(ql_log_fatal, vha, 0x0085,
  3960. "Unable to verify integrity of firmware image (%Zd).\n",
  3961. blob->fw->size);
  3962. goto fail_fw_integrity;
  3963. }
  3964. for (i = 0; i < 4; i++)
  3965. wcode[i] = be16_to_cpu(fwcode[i + 4]);
  3966. if ((wcode[0] == 0xffff && wcode[1] == 0xffff && wcode[2] == 0xffff &&
  3967. wcode[3] == 0xffff) || (wcode[0] == 0 && wcode[1] == 0 &&
  3968. wcode[2] == 0 && wcode[3] == 0)) {
  3969. ql_log(ql_log_fatal, vha, 0x0086,
  3970. "Unable to verify integrity of firmware image.\n");
  3971. ql_log(ql_log_fatal, vha, 0x0087,
  3972. "Firmware data: %04x %04x %04x %04x.\n",
  3973. wcode[0], wcode[1], wcode[2], wcode[3]);
  3974. goto fail_fw_integrity;
  3975. }
  3976. seg = blob->segs;
  3977. while (*seg && rval == QLA_SUCCESS) {
  3978. risc_addr = *seg;
  3979. *srisc_addr = *srisc_addr == 0 ? *seg : *srisc_addr;
  3980. risc_size = be16_to_cpu(fwcode[3]);
  3981. /* Validate firmware image size. */
  3982. fwclen += risc_size * sizeof(uint16_t);
  3983. if (blob->fw->size < fwclen) {
  3984. ql_log(ql_log_fatal, vha, 0x0088,
  3985. "Unable to verify integrity of firmware image "
  3986. "(%Zd).\n", blob->fw->size);
  3987. goto fail_fw_integrity;
  3988. }
  3989. fragment = 0;
  3990. while (risc_size > 0 && rval == QLA_SUCCESS) {
  3991. wlen = (uint16_t)(ha->fw_transfer_size >> 1);
  3992. if (wlen > risc_size)
  3993. wlen = risc_size;
  3994. ql_dbg(ql_dbg_init, vha, 0x0089,
  3995. "Loading risc segment@ risc addr %x number of "
  3996. "words 0x%x.\n", risc_addr, wlen);
  3997. for (i = 0; i < wlen; i++)
  3998. wcode[i] = swab16(fwcode[i]);
  3999. rval = qla2x00_load_ram(vha, req->dma, risc_addr,
  4000. wlen);
  4001. if (rval) {
  4002. ql_log(ql_log_fatal, vha, 0x008a,
  4003. "Failed to load segment %d of firmware.\n",
  4004. fragment);
  4005. break;
  4006. }
  4007. fwcode += wlen;
  4008. risc_addr += wlen;
  4009. risc_size -= wlen;
  4010. fragment++;
  4011. }
  4012. /* Next segment. */
  4013. seg++;
  4014. }
  4015. return rval;
  4016. fail_fw_integrity:
  4017. return QLA_FUNCTION_FAILED;
  4018. }
  4019. static int
  4020. qla24xx_load_risc_blob(scsi_qla_host_t *vha, uint32_t *srisc_addr)
  4021. {
  4022. int rval;
  4023. int segments, fragment;
  4024. uint32_t *dcode, dlen;
  4025. uint32_t risc_addr;
  4026. uint32_t risc_size;
  4027. uint32_t i;
  4028. struct fw_blob *blob;
  4029. uint32_t *fwcode, fwclen;
  4030. struct qla_hw_data *ha = vha->hw;
  4031. struct req_que *req = ha->req_q_map[0];
  4032. /* Load firmware blob. */
  4033. blob = qla2x00_request_firmware(vha);
  4034. if (!blob) {
  4035. ql_log(ql_log_warn, vha, 0x0090,
  4036. "Fimware image unavailable.\n");
  4037. ql_log(ql_log_warn, vha, 0x0091,
  4038. "Firmware images can be retrieved from: "
  4039. QLA_FW_URL ".\n");
  4040. return QLA_FUNCTION_FAILED;
  4041. }
  4042. ql_dbg(ql_dbg_init, vha, 0x0092,
  4043. "FW: Loading via request-firmware.\n");
  4044. rval = QLA_SUCCESS;
  4045. segments = FA_RISC_CODE_SEGMENTS;
  4046. dcode = (uint32_t *)req->ring;
  4047. *srisc_addr = 0;
  4048. fwcode = (uint32_t *)blob->fw->data;
  4049. fwclen = 0;
  4050. /* Validate firmware image by checking version. */
  4051. if (blob->fw->size < 8 * sizeof(uint32_t)) {
  4052. ql_log(ql_log_fatal, vha, 0x0093,
  4053. "Unable to verify integrity of firmware image (%Zd).\n",
  4054. blob->fw->size);
  4055. goto fail_fw_integrity;
  4056. }
  4057. for (i = 0; i < 4; i++)
  4058. dcode[i] = be32_to_cpu(fwcode[i + 4]);
  4059. if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
  4060. dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
  4061. (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
  4062. dcode[3] == 0)) {
  4063. ql_log(ql_log_fatal, vha, 0x0094,
  4064. "Unable to verify integrity of firmware image (%Zd).\n",
  4065. blob->fw->size);
  4066. ql_log(ql_log_fatal, vha, 0x0095,
  4067. "Firmware data: %08x %08x %08x %08x.\n",
  4068. dcode[0], dcode[1], dcode[2], dcode[3]);
  4069. goto fail_fw_integrity;
  4070. }
  4071. while (segments && rval == QLA_SUCCESS) {
  4072. risc_addr = be32_to_cpu(fwcode[2]);
  4073. *srisc_addr = *srisc_addr == 0 ? risc_addr : *srisc_addr;
  4074. risc_size = be32_to_cpu(fwcode[3]);
  4075. /* Validate firmware image size. */
  4076. fwclen += risc_size * sizeof(uint32_t);
  4077. if (blob->fw->size < fwclen) {
  4078. ql_log(ql_log_fatal, vha, 0x0096,
  4079. "Unable to verify integrity of firmware image "
  4080. "(%Zd).\n", blob->fw->size);
  4081. goto fail_fw_integrity;
  4082. }
  4083. fragment = 0;
  4084. while (risc_size > 0 && rval == QLA_SUCCESS) {
  4085. dlen = (uint32_t)(ha->fw_transfer_size >> 2);
  4086. if (dlen > risc_size)
  4087. dlen = risc_size;
  4088. ql_dbg(ql_dbg_init, vha, 0x0097,
  4089. "Loading risc segment@ risc addr %x "
  4090. "number of dwords 0x%x.\n", risc_addr, dlen);
  4091. for (i = 0; i < dlen; i++)
  4092. dcode[i] = swab32(fwcode[i]);
  4093. rval = qla2x00_load_ram(vha, req->dma, risc_addr,
  4094. dlen);
  4095. if (rval) {
  4096. ql_log(ql_log_fatal, vha, 0x0098,
  4097. "Failed to load segment %d of firmware.\n",
  4098. fragment);
  4099. break;
  4100. }
  4101. fwcode += dlen;
  4102. risc_addr += dlen;
  4103. risc_size -= dlen;
  4104. fragment++;
  4105. }
  4106. /* Next segment. */
  4107. segments--;
  4108. }
  4109. return rval;
  4110. fail_fw_integrity:
  4111. return QLA_FUNCTION_FAILED;
  4112. }
  4113. int
  4114. qla24xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
  4115. {
  4116. int rval;
  4117. if (ql2xfwloadbin == 1)
  4118. return qla81xx_load_risc(vha, srisc_addr);
  4119. /*
  4120. * FW Load priority:
  4121. * 1) Firmware via request-firmware interface (.bin file).
  4122. * 2) Firmware residing in flash.
  4123. */
  4124. rval = qla24xx_load_risc_blob(vha, srisc_addr);
  4125. if (rval == QLA_SUCCESS)
  4126. return rval;
  4127. return qla24xx_load_risc_flash(vha, srisc_addr,
  4128. vha->hw->flt_region_fw);
  4129. }
  4130. int
  4131. qla81xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
  4132. {
  4133. int rval;
  4134. struct qla_hw_data *ha = vha->hw;
  4135. if (ql2xfwloadbin == 2)
  4136. goto try_blob_fw;
  4137. /*
  4138. * FW Load priority:
  4139. * 1) Firmware residing in flash.
  4140. * 2) Firmware via request-firmware interface (.bin file).
  4141. * 3) Golden-Firmware residing in flash -- limited operation.
  4142. */
  4143. rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_fw);
  4144. if (rval == QLA_SUCCESS)
  4145. return rval;
  4146. try_blob_fw:
  4147. rval = qla24xx_load_risc_blob(vha, srisc_addr);
  4148. if (rval == QLA_SUCCESS || !ha->flt_region_gold_fw)
  4149. return rval;
  4150. ql_log(ql_log_info, vha, 0x0099,
  4151. "Attempting to fallback to golden firmware.\n");
  4152. rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_gold_fw);
  4153. if (rval != QLA_SUCCESS)
  4154. return rval;
  4155. ql_log(ql_log_info, vha, 0x009a, "Update operational firmware.\n");
  4156. ha->flags.running_gold_fw = 1;
  4157. return rval;
  4158. }
  4159. void
  4160. qla2x00_try_to_stop_firmware(scsi_qla_host_t *vha)
  4161. {
  4162. int ret, retries;
  4163. struct qla_hw_data *ha = vha->hw;
  4164. if (ha->flags.pci_channel_io_perm_failure)
  4165. return;
  4166. if (!IS_FWI2_CAPABLE(ha))
  4167. return;
  4168. if (!ha->fw_major_version)
  4169. return;
  4170. ret = qla2x00_stop_firmware(vha);
  4171. for (retries = 5; ret != QLA_SUCCESS && ret != QLA_FUNCTION_TIMEOUT &&
  4172. ret != QLA_INVALID_COMMAND && retries ; retries--) {
  4173. ha->isp_ops->reset_chip(vha);
  4174. if (ha->isp_ops->chip_diag(vha) != QLA_SUCCESS)
  4175. continue;
  4176. if (qla2x00_setup_chip(vha) != QLA_SUCCESS)
  4177. continue;
  4178. ql_log(ql_log_info, vha, 0x8015,
  4179. "Attempting retry of stop-firmware command.\n");
  4180. ret = qla2x00_stop_firmware(vha);
  4181. }
  4182. }
  4183. int
  4184. qla24xx_configure_vhba(scsi_qla_host_t *vha)
  4185. {
  4186. int rval = QLA_SUCCESS;
  4187. int rval2;
  4188. uint16_t mb[MAILBOX_REGISTER_COUNT];
  4189. struct qla_hw_data *ha = vha->hw;
  4190. struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
  4191. struct req_que *req;
  4192. struct rsp_que *rsp;
  4193. if (!vha->vp_idx)
  4194. return -EINVAL;
  4195. rval = qla2x00_fw_ready(base_vha);
  4196. if (ha->flags.cpu_affinity_enabled)
  4197. req = ha->req_q_map[0];
  4198. else
  4199. req = vha->req;
  4200. rsp = req->rsp;
  4201. if (rval == QLA_SUCCESS) {
  4202. clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
  4203. qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
  4204. }
  4205. vha->flags.management_server_logged_in = 0;
  4206. /* Login to SNS first */
  4207. rval2 = ha->isp_ops->fabric_login(vha, NPH_SNS, 0xff, 0xff, 0xfc, mb,
  4208. BIT_1);
  4209. if (rval2 != QLA_SUCCESS || mb[0] != MBS_COMMAND_COMPLETE) {
  4210. if (rval2 == QLA_MEMORY_ALLOC_FAILED)
  4211. ql_dbg(ql_dbg_init, vha, 0x0120,
  4212. "Failed SNS login: loop_id=%x, rval2=%d\n",
  4213. NPH_SNS, rval2);
  4214. else
  4215. ql_dbg(ql_dbg_init, vha, 0x0103,
  4216. "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x "
  4217. "mb[2]=%x mb[6]=%x mb[7]=%x.\n",
  4218. NPH_SNS, mb[0], mb[1], mb[2], mb[6], mb[7]);
  4219. return (QLA_FUNCTION_FAILED);
  4220. }
  4221. atomic_set(&vha->loop_down_timer, 0);
  4222. atomic_set(&vha->loop_state, LOOP_UP);
  4223. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  4224. set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
  4225. rval = qla2x00_loop_resync(base_vha);
  4226. return rval;
  4227. }
  4228. /* 84XX Support **************************************************************/
  4229. static LIST_HEAD(qla_cs84xx_list);
  4230. static DEFINE_MUTEX(qla_cs84xx_mutex);
  4231. static struct qla_chip_state_84xx *
  4232. qla84xx_get_chip(struct scsi_qla_host *vha)
  4233. {
  4234. struct qla_chip_state_84xx *cs84xx;
  4235. struct qla_hw_data *ha = vha->hw;
  4236. mutex_lock(&qla_cs84xx_mutex);
  4237. /* Find any shared 84xx chip. */
  4238. list_for_each_entry(cs84xx, &qla_cs84xx_list, list) {
  4239. if (cs84xx->bus == ha->pdev->bus) {
  4240. kref_get(&cs84xx->kref);
  4241. goto done;
  4242. }
  4243. }
  4244. cs84xx = kzalloc(sizeof(*cs84xx), GFP_KERNEL);
  4245. if (!cs84xx)
  4246. goto done;
  4247. kref_init(&cs84xx->kref);
  4248. spin_lock_init(&cs84xx->access_lock);
  4249. mutex_init(&cs84xx->fw_update_mutex);
  4250. cs84xx->bus = ha->pdev->bus;
  4251. list_add_tail(&cs84xx->list, &qla_cs84xx_list);
  4252. done:
  4253. mutex_unlock(&qla_cs84xx_mutex);
  4254. return cs84xx;
  4255. }
  4256. static void
  4257. __qla84xx_chip_release(struct kref *kref)
  4258. {
  4259. struct qla_chip_state_84xx *cs84xx =
  4260. container_of(kref, struct qla_chip_state_84xx, kref);
  4261. mutex_lock(&qla_cs84xx_mutex);
  4262. list_del(&cs84xx->list);
  4263. mutex_unlock(&qla_cs84xx_mutex);
  4264. kfree(cs84xx);
  4265. }
  4266. void
  4267. qla84xx_put_chip(struct scsi_qla_host *vha)
  4268. {
  4269. struct qla_hw_data *ha = vha->hw;
  4270. if (ha->cs84xx)
  4271. kref_put(&ha->cs84xx->kref, __qla84xx_chip_release);
  4272. }
  4273. static int
  4274. qla84xx_init_chip(scsi_qla_host_t *vha)
  4275. {
  4276. int rval;
  4277. uint16_t status[2];
  4278. struct qla_hw_data *ha = vha->hw;
  4279. mutex_lock(&ha->cs84xx->fw_update_mutex);
  4280. rval = qla84xx_verify_chip(vha, status);
  4281. mutex_unlock(&ha->cs84xx->fw_update_mutex);
  4282. return rval != QLA_SUCCESS || status[0] ? QLA_FUNCTION_FAILED:
  4283. QLA_SUCCESS;
  4284. }
  4285. /* 81XX Support **************************************************************/
  4286. int
  4287. qla81xx_nvram_config(scsi_qla_host_t *vha)
  4288. {
  4289. int rval;
  4290. struct init_cb_81xx *icb;
  4291. struct nvram_81xx *nv;
  4292. uint32_t *dptr;
  4293. uint8_t *dptr1, *dptr2;
  4294. uint32_t chksum;
  4295. uint16_t cnt;
  4296. struct qla_hw_data *ha = vha->hw;
  4297. rval = QLA_SUCCESS;
  4298. icb = (struct init_cb_81xx *)ha->init_cb;
  4299. nv = ha->nvram;
  4300. /* Determine NVRAM starting address. */
  4301. ha->nvram_size = sizeof(struct nvram_81xx);
  4302. ha->vpd_size = FA_NVRAM_VPD_SIZE;
  4303. /* Get VPD data into cache */
  4304. ha->vpd = ha->nvram + VPD_OFFSET;
  4305. ha->isp_ops->read_optrom(vha, ha->vpd, ha->flt_region_vpd << 2,
  4306. ha->vpd_size);
  4307. /* Get NVRAM data into cache and calculate checksum. */
  4308. ha->isp_ops->read_optrom(vha, ha->nvram, ha->flt_region_nvram << 2,
  4309. ha->nvram_size);
  4310. dptr = (uint32_t *)nv;
  4311. for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++)
  4312. chksum += le32_to_cpu(*dptr++);
  4313. ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0111,
  4314. "Contents of NVRAM:\n");
  4315. ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0112,
  4316. (uint8_t *)nv, ha->nvram_size);
  4317. /* Bad NVRAM data, set defaults parameters. */
  4318. if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P'
  4319. || nv->id[3] != ' ' ||
  4320. nv->nvram_version < __constant_cpu_to_le16(ICB_VERSION)) {
  4321. /* Reset NVRAM data. */
  4322. ql_log(ql_log_info, vha, 0x0073,
  4323. "Inconsistent NVRAM detected: checksum=0x%x id=%c "
  4324. "version=0x%x.\n", chksum, nv->id[0],
  4325. le16_to_cpu(nv->nvram_version));
  4326. ql_log(ql_log_info, vha, 0x0074,
  4327. "Falling back to functioning (yet invalid -- WWPN) "
  4328. "defaults.\n");
  4329. /*
  4330. * Set default initialization control block.
  4331. */
  4332. memset(nv, 0, ha->nvram_size);
  4333. nv->nvram_version = __constant_cpu_to_le16(ICB_VERSION);
  4334. nv->version = __constant_cpu_to_le16(ICB_VERSION);
  4335. nv->frame_payload_size = __constant_cpu_to_le16(2048);
  4336. nv->execution_throttle = __constant_cpu_to_le16(0xFFFF);
  4337. nv->exchange_count = __constant_cpu_to_le16(0);
  4338. nv->port_name[0] = 0x21;
  4339. nv->port_name[1] = 0x00 + ha->port_no;
  4340. nv->port_name[2] = 0x00;
  4341. nv->port_name[3] = 0xe0;
  4342. nv->port_name[4] = 0x8b;
  4343. nv->port_name[5] = 0x1c;
  4344. nv->port_name[6] = 0x55;
  4345. nv->port_name[7] = 0x86;
  4346. nv->node_name[0] = 0x20;
  4347. nv->node_name[1] = 0x00;
  4348. nv->node_name[2] = 0x00;
  4349. nv->node_name[3] = 0xe0;
  4350. nv->node_name[4] = 0x8b;
  4351. nv->node_name[5] = 0x1c;
  4352. nv->node_name[6] = 0x55;
  4353. nv->node_name[7] = 0x86;
  4354. nv->login_retry_count = __constant_cpu_to_le16(8);
  4355. nv->interrupt_delay_timer = __constant_cpu_to_le16(0);
  4356. nv->login_timeout = __constant_cpu_to_le16(0);
  4357. nv->firmware_options_1 =
  4358. __constant_cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1);
  4359. nv->firmware_options_2 = __constant_cpu_to_le32(2 << 4);
  4360. nv->firmware_options_2 |= __constant_cpu_to_le32(BIT_12);
  4361. nv->firmware_options_3 = __constant_cpu_to_le32(2 << 13);
  4362. nv->host_p = __constant_cpu_to_le32(BIT_11|BIT_10);
  4363. nv->efi_parameters = __constant_cpu_to_le32(0);
  4364. nv->reset_delay = 5;
  4365. nv->max_luns_per_target = __constant_cpu_to_le16(128);
  4366. nv->port_down_retry_count = __constant_cpu_to_le16(30);
  4367. nv->link_down_timeout = __constant_cpu_to_le16(180);
  4368. nv->enode_mac[0] = 0x00;
  4369. nv->enode_mac[1] = 0xC0;
  4370. nv->enode_mac[2] = 0xDD;
  4371. nv->enode_mac[3] = 0x04;
  4372. nv->enode_mac[4] = 0x05;
  4373. nv->enode_mac[5] = 0x06 + ha->port_no;
  4374. rval = 1;
  4375. }
  4376. /* Reset Initialization control block */
  4377. memset(icb, 0, ha->init_cb_size);
  4378. /* Copy 1st segment. */
  4379. dptr1 = (uint8_t *)icb;
  4380. dptr2 = (uint8_t *)&nv->version;
  4381. cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version;
  4382. while (cnt--)
  4383. *dptr1++ = *dptr2++;
  4384. icb->login_retry_count = nv->login_retry_count;
  4385. /* Copy 2nd segment. */
  4386. dptr1 = (uint8_t *)&icb->interrupt_delay_timer;
  4387. dptr2 = (uint8_t *)&nv->interrupt_delay_timer;
  4388. cnt = (uint8_t *)&icb->reserved_5 -
  4389. (uint8_t *)&icb->interrupt_delay_timer;
  4390. while (cnt--)
  4391. *dptr1++ = *dptr2++;
  4392. memcpy(icb->enode_mac, nv->enode_mac, sizeof(icb->enode_mac));
  4393. /* Some boards (with valid NVRAMs) still have NULL enode_mac!! */
  4394. if (!memcmp(icb->enode_mac, "\0\0\0\0\0\0", sizeof(icb->enode_mac))) {
  4395. icb->enode_mac[0] = 0x00;
  4396. icb->enode_mac[1] = 0xC0;
  4397. icb->enode_mac[2] = 0xDD;
  4398. icb->enode_mac[3] = 0x04;
  4399. icb->enode_mac[4] = 0x05;
  4400. icb->enode_mac[5] = 0x06 + ha->port_no;
  4401. }
  4402. /* Use extended-initialization control block. */
  4403. memcpy(ha->ex_init_cb, &nv->ex_version, sizeof(*ha->ex_init_cb));
  4404. /*
  4405. * Setup driver NVRAM options.
  4406. */
  4407. qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name),
  4408. "QLE8XXX");
  4409. /* Use alternate WWN? */
  4410. if (nv->host_p & __constant_cpu_to_le32(BIT_15)) {
  4411. memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
  4412. memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
  4413. }
  4414. /* Prepare nodename */
  4415. if ((icb->firmware_options_1 & __constant_cpu_to_le32(BIT_14)) == 0) {
  4416. /*
  4417. * Firmware will apply the following mask if the nodename was
  4418. * not provided.
  4419. */
  4420. memcpy(icb->node_name, icb->port_name, WWN_SIZE);
  4421. icb->node_name[0] &= 0xF0;
  4422. }
  4423. /* Set host adapter parameters. */
  4424. ha->flags.disable_risc_code_load = 0;
  4425. ha->flags.enable_lip_reset = 0;
  4426. ha->flags.enable_lip_full_login =
  4427. le32_to_cpu(nv->host_p) & BIT_10 ? 1: 0;
  4428. ha->flags.enable_target_reset =
  4429. le32_to_cpu(nv->host_p) & BIT_11 ? 1: 0;
  4430. ha->flags.enable_led_scheme = 0;
  4431. ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1: 0;
  4432. ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) &
  4433. (BIT_6 | BIT_5 | BIT_4)) >> 4;
  4434. /* save HBA serial number */
  4435. ha->serial0 = icb->port_name[5];
  4436. ha->serial1 = icb->port_name[6];
  4437. ha->serial2 = icb->port_name[7];
  4438. memcpy(vha->node_name, icb->node_name, WWN_SIZE);
  4439. memcpy(vha->port_name, icb->port_name, WWN_SIZE);
  4440. icb->execution_throttle = __constant_cpu_to_le16(0xFFFF);
  4441. ha->retry_count = le16_to_cpu(nv->login_retry_count);
  4442. /* Set minimum login_timeout to 4 seconds. */
  4443. if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout)
  4444. nv->login_timeout = cpu_to_le16(ql2xlogintimeout);
  4445. if (le16_to_cpu(nv->login_timeout) < 4)
  4446. nv->login_timeout = __constant_cpu_to_le16(4);
  4447. ha->login_timeout = le16_to_cpu(nv->login_timeout);
  4448. icb->login_timeout = nv->login_timeout;
  4449. /* Set minimum RATOV to 100 tenths of a second. */
  4450. ha->r_a_tov = 100;
  4451. ha->loop_reset_delay = nv->reset_delay;
  4452. /* Link Down Timeout = 0:
  4453. *
  4454. * When Port Down timer expires we will start returning
  4455. * I/O's to OS with "DID_NO_CONNECT".
  4456. *
  4457. * Link Down Timeout != 0:
  4458. *
  4459. * The driver waits for the link to come up after link down
  4460. * before returning I/Os to OS with "DID_NO_CONNECT".
  4461. */
  4462. if (le16_to_cpu(nv->link_down_timeout) == 0) {
  4463. ha->loop_down_abort_time =
  4464. (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
  4465. } else {
  4466. ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout);
  4467. ha->loop_down_abort_time =
  4468. (LOOP_DOWN_TIME - ha->link_down_timeout);
  4469. }
  4470. /* Need enough time to try and get the port back. */
  4471. ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count);
  4472. if (qlport_down_retry)
  4473. ha->port_down_retry_count = qlport_down_retry;
  4474. /* Set login_retry_count */
  4475. ha->login_retry_count = le16_to_cpu(nv->login_retry_count);
  4476. if (ha->port_down_retry_count ==
  4477. le16_to_cpu(nv->port_down_retry_count) &&
  4478. ha->port_down_retry_count > 3)
  4479. ha->login_retry_count = ha->port_down_retry_count;
  4480. else if (ha->port_down_retry_count > (int)ha->login_retry_count)
  4481. ha->login_retry_count = ha->port_down_retry_count;
  4482. if (ql2xloginretrycount)
  4483. ha->login_retry_count = ql2xloginretrycount;
  4484. /* if not running MSI-X we need handshaking on interrupts */
  4485. if (!vha->hw->flags.msix_enabled && IS_QLA83XX(ha))
  4486. icb->firmware_options_2 |= __constant_cpu_to_le32(BIT_22);
  4487. /* Enable ZIO. */
  4488. if (!vha->flags.init_done) {
  4489. ha->zio_mode = le32_to_cpu(icb->firmware_options_2) &
  4490. (BIT_3 | BIT_2 | BIT_1 | BIT_0);
  4491. ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ?
  4492. le16_to_cpu(icb->interrupt_delay_timer): 2;
  4493. }
  4494. icb->firmware_options_2 &= __constant_cpu_to_le32(
  4495. ~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
  4496. vha->flags.process_response_queue = 0;
  4497. if (ha->zio_mode != QLA_ZIO_DISABLED) {
  4498. ha->zio_mode = QLA_ZIO_MODE_6;
  4499. ql_log(ql_log_info, vha, 0x0075,
  4500. "ZIO mode %d enabled; timer delay (%d us).\n",
  4501. ha->zio_mode,
  4502. ha->zio_timer * 100);
  4503. icb->firmware_options_2 |= cpu_to_le32(
  4504. (uint32_t)ha->zio_mode);
  4505. icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer);
  4506. vha->flags.process_response_queue = 1;
  4507. }
  4508. if (rval) {
  4509. ql_log(ql_log_warn, vha, 0x0076,
  4510. "NVRAM configuration failed.\n");
  4511. }
  4512. return (rval);
  4513. }
  4514. int
  4515. qla82xx_restart_isp(scsi_qla_host_t *vha)
  4516. {
  4517. int status, rval;
  4518. uint32_t wait_time;
  4519. struct qla_hw_data *ha = vha->hw;
  4520. struct req_que *req = ha->req_q_map[0];
  4521. struct rsp_que *rsp = ha->rsp_q_map[0];
  4522. struct scsi_qla_host *vp;
  4523. unsigned long flags;
  4524. status = qla2x00_init_rings(vha);
  4525. if (!status) {
  4526. clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
  4527. ha->flags.chip_reset_done = 1;
  4528. status = qla2x00_fw_ready(vha);
  4529. if (!status) {
  4530. ql_log(ql_log_info, vha, 0x803c,
  4531. "Start configure loop, status =%d.\n", status);
  4532. /* Issue a marker after FW becomes ready. */
  4533. qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
  4534. vha->flags.online = 1;
  4535. /* Wait at most MAX_TARGET RSCNs for a stable link. */
  4536. wait_time = 256;
  4537. do {
  4538. clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  4539. qla2x00_configure_loop(vha);
  4540. wait_time--;
  4541. } while (!atomic_read(&vha->loop_down_timer) &&
  4542. !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags)) &&
  4543. wait_time &&
  4544. (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)));
  4545. }
  4546. /* if no cable then assume it's good */
  4547. if ((vha->device_flags & DFLG_NO_CABLE))
  4548. status = 0;
  4549. ql_log(ql_log_info, vha, 0x8000,
  4550. "Configure loop done, status = 0x%x.\n", status);
  4551. }
  4552. if (!status) {
  4553. clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
  4554. if (!atomic_read(&vha->loop_down_timer)) {
  4555. /*
  4556. * Issue marker command only when we are going
  4557. * to start the I/O .
  4558. */
  4559. vha->marker_needed = 1;
  4560. }
  4561. vha->flags.online = 1;
  4562. ha->isp_ops->enable_intrs(ha);
  4563. ha->isp_abort_cnt = 0;
  4564. clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
  4565. /* Update the firmware version */
  4566. status = qla82xx_check_md_needed(vha);
  4567. if (ha->fce) {
  4568. ha->flags.fce_enabled = 1;
  4569. memset(ha->fce, 0,
  4570. fce_calc_size(ha->fce_bufs));
  4571. rval = qla2x00_enable_fce_trace(vha,
  4572. ha->fce_dma, ha->fce_bufs, ha->fce_mb,
  4573. &ha->fce_bufs);
  4574. if (rval) {
  4575. ql_log(ql_log_warn, vha, 0x8001,
  4576. "Unable to reinitialize FCE (%d).\n",
  4577. rval);
  4578. ha->flags.fce_enabled = 0;
  4579. }
  4580. }
  4581. if (ha->eft) {
  4582. memset(ha->eft, 0, EFT_SIZE);
  4583. rval = qla2x00_enable_eft_trace(vha,
  4584. ha->eft_dma, EFT_NUM_BUFFERS);
  4585. if (rval) {
  4586. ql_log(ql_log_warn, vha, 0x8010,
  4587. "Unable to reinitialize EFT (%d).\n",
  4588. rval);
  4589. }
  4590. }
  4591. }
  4592. if (!status) {
  4593. ql_dbg(ql_dbg_taskm, vha, 0x8011,
  4594. "qla82xx_restart_isp succeeded.\n");
  4595. spin_lock_irqsave(&ha->vport_slock, flags);
  4596. list_for_each_entry(vp, &ha->vp_list, list) {
  4597. if (vp->vp_idx) {
  4598. atomic_inc(&vp->vref_count);
  4599. spin_unlock_irqrestore(&ha->vport_slock, flags);
  4600. qla2x00_vp_abort_isp(vp);
  4601. spin_lock_irqsave(&ha->vport_slock, flags);
  4602. atomic_dec(&vp->vref_count);
  4603. }
  4604. }
  4605. spin_unlock_irqrestore(&ha->vport_slock, flags);
  4606. } else {
  4607. ql_log(ql_log_warn, vha, 0x8016,
  4608. "qla82xx_restart_isp **** FAILED ****.\n");
  4609. }
  4610. return status;
  4611. }
  4612. void
  4613. qla81xx_update_fw_options(scsi_qla_host_t *vha)
  4614. {
  4615. struct qla_hw_data *ha = vha->hw;
  4616. if (!ql2xetsenable)
  4617. return;
  4618. /* Enable ETS Burst. */
  4619. memset(ha->fw_options, 0, sizeof(ha->fw_options));
  4620. ha->fw_options[2] |= BIT_9;
  4621. qla2x00_set_fw_options(vha, ha->fw_options);
  4622. }
  4623. /*
  4624. * qla24xx_get_fcp_prio
  4625. * Gets the fcp cmd priority value for the logged in port.
  4626. * Looks for a match of the port descriptors within
  4627. * each of the fcp prio config entries. If a match is found,
  4628. * the tag (priority) value is returned.
  4629. *
  4630. * Input:
  4631. * vha = scsi host structure pointer.
  4632. * fcport = port structure pointer.
  4633. *
  4634. * Return:
  4635. * non-zero (if found)
  4636. * -1 (if not found)
  4637. *
  4638. * Context:
  4639. * Kernel context
  4640. */
  4641. static int
  4642. qla24xx_get_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport)
  4643. {
  4644. int i, entries;
  4645. uint8_t pid_match, wwn_match;
  4646. int priority;
  4647. uint32_t pid1, pid2;
  4648. uint64_t wwn1, wwn2;
  4649. struct qla_fcp_prio_entry *pri_entry;
  4650. struct qla_hw_data *ha = vha->hw;
  4651. if (!ha->fcp_prio_cfg || !ha->flags.fcp_prio_enabled)
  4652. return -1;
  4653. priority = -1;
  4654. entries = ha->fcp_prio_cfg->num_entries;
  4655. pri_entry = &ha->fcp_prio_cfg->entry[0];
  4656. for (i = 0; i < entries; i++) {
  4657. pid_match = wwn_match = 0;
  4658. if (!(pri_entry->flags & FCP_PRIO_ENTRY_VALID)) {
  4659. pri_entry++;
  4660. continue;
  4661. }
  4662. /* check source pid for a match */
  4663. if (pri_entry->flags & FCP_PRIO_ENTRY_SPID_VALID) {
  4664. pid1 = pri_entry->src_pid & INVALID_PORT_ID;
  4665. pid2 = vha->d_id.b24 & INVALID_PORT_ID;
  4666. if (pid1 == INVALID_PORT_ID)
  4667. pid_match++;
  4668. else if (pid1 == pid2)
  4669. pid_match++;
  4670. }
  4671. /* check destination pid for a match */
  4672. if (pri_entry->flags & FCP_PRIO_ENTRY_DPID_VALID) {
  4673. pid1 = pri_entry->dst_pid & INVALID_PORT_ID;
  4674. pid2 = fcport->d_id.b24 & INVALID_PORT_ID;
  4675. if (pid1 == INVALID_PORT_ID)
  4676. pid_match++;
  4677. else if (pid1 == pid2)
  4678. pid_match++;
  4679. }
  4680. /* check source WWN for a match */
  4681. if (pri_entry->flags & FCP_PRIO_ENTRY_SWWN_VALID) {
  4682. wwn1 = wwn_to_u64(vha->port_name);
  4683. wwn2 = wwn_to_u64(pri_entry->src_wwpn);
  4684. if (wwn2 == (uint64_t)-1)
  4685. wwn_match++;
  4686. else if (wwn1 == wwn2)
  4687. wwn_match++;
  4688. }
  4689. /* check destination WWN for a match */
  4690. if (pri_entry->flags & FCP_PRIO_ENTRY_DWWN_VALID) {
  4691. wwn1 = wwn_to_u64(fcport->port_name);
  4692. wwn2 = wwn_to_u64(pri_entry->dst_wwpn);
  4693. if (wwn2 == (uint64_t)-1)
  4694. wwn_match++;
  4695. else if (wwn1 == wwn2)
  4696. wwn_match++;
  4697. }
  4698. if (pid_match == 2 || wwn_match == 2) {
  4699. /* Found a matching entry */
  4700. if (pri_entry->flags & FCP_PRIO_ENTRY_TAG_VALID)
  4701. priority = pri_entry->tag;
  4702. break;
  4703. }
  4704. pri_entry++;
  4705. }
  4706. return priority;
  4707. }
  4708. /*
  4709. * qla24xx_update_fcport_fcp_prio
  4710. * Activates fcp priority for the logged in fc port
  4711. *
  4712. * Input:
  4713. * vha = scsi host structure pointer.
  4714. * fcp = port structure pointer.
  4715. *
  4716. * Return:
  4717. * QLA_SUCCESS or QLA_FUNCTION_FAILED
  4718. *
  4719. * Context:
  4720. * Kernel context.
  4721. */
  4722. int
  4723. qla24xx_update_fcport_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport)
  4724. {
  4725. int ret;
  4726. int priority;
  4727. uint16_t mb[5];
  4728. if (fcport->port_type != FCT_TARGET ||
  4729. fcport->loop_id == FC_NO_LOOP_ID)
  4730. return QLA_FUNCTION_FAILED;
  4731. priority = qla24xx_get_fcp_prio(vha, fcport);
  4732. if (priority < 0)
  4733. return QLA_FUNCTION_FAILED;
  4734. if (IS_QLA82XX(vha->hw)) {
  4735. fcport->fcp_prio = priority & 0xf;
  4736. return QLA_SUCCESS;
  4737. }
  4738. ret = qla24xx_set_fcp_prio(vha, fcport->loop_id, priority, mb);
  4739. if (ret == QLA_SUCCESS) {
  4740. if (fcport->fcp_prio != priority)
  4741. ql_dbg(ql_dbg_user, vha, 0x709e,
  4742. "Updated FCP_CMND priority - value=%d loop_id=%d "
  4743. "port_id=%02x%02x%02x.\n", priority,
  4744. fcport->loop_id, fcport->d_id.b.domain,
  4745. fcport->d_id.b.area, fcport->d_id.b.al_pa);
  4746. fcport->fcp_prio = priority & 0xf;
  4747. } else
  4748. ql_dbg(ql_dbg_user, vha, 0x704f,
  4749. "Unable to update FCP_CMND priority - ret=0x%x for "
  4750. "loop_id=%d port_id=%02x%02x%02x.\n", ret, fcport->loop_id,
  4751. fcport->d_id.b.domain, fcport->d_id.b.area,
  4752. fcport->d_id.b.al_pa);
  4753. return ret;
  4754. }
  4755. /*
  4756. * qla24xx_update_all_fcp_prio
  4757. * Activates fcp priority for all the logged in ports
  4758. *
  4759. * Input:
  4760. * ha = adapter block pointer.
  4761. *
  4762. * Return:
  4763. * QLA_SUCCESS or QLA_FUNCTION_FAILED
  4764. *
  4765. * Context:
  4766. * Kernel context.
  4767. */
  4768. int
  4769. qla24xx_update_all_fcp_prio(scsi_qla_host_t *vha)
  4770. {
  4771. int ret;
  4772. fc_port_t *fcport;
  4773. ret = QLA_FUNCTION_FAILED;
  4774. /* We need to set priority for all logged in ports */
  4775. list_for_each_entry(fcport, &vha->vp_fcports, list)
  4776. ret = qla24xx_update_fcport_fcp_prio(vha, fcport);
  4777. return ret;
  4778. }