qeth_core_main.c 152 KB

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  1. /*
  2. * drivers/s390/net/qeth_core_main.c
  3. *
  4. * Copyright IBM Corp. 2007, 2009
  5. * Author(s): Utz Bacher <utz.bacher@de.ibm.com>,
  6. * Frank Pavlic <fpavlic@de.ibm.com>,
  7. * Thomas Spatzier <tspat@de.ibm.com>,
  8. * Frank Blaschka <frank.blaschka@de.ibm.com>
  9. */
  10. #define KMSG_COMPONENT "qeth"
  11. #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt
  12. #include <linux/module.h>
  13. #include <linux/moduleparam.h>
  14. #include <linux/string.h>
  15. #include <linux/errno.h>
  16. #include <linux/kernel.h>
  17. #include <linux/ip.h>
  18. #include <linux/tcp.h>
  19. #include <linux/mii.h>
  20. #include <linux/kthread.h>
  21. #include <linux/slab.h>
  22. #include <net/iucv/af_iucv.h>
  23. #include <asm/ebcdic.h>
  24. #include <asm/io.h>
  25. #include <asm/sysinfo.h>
  26. #include <asm/compat.h>
  27. #include "qeth_core.h"
  28. struct qeth_dbf_info qeth_dbf[QETH_DBF_INFOS] = {
  29. /* define dbf - Name, Pages, Areas, Maxlen, Level, View, Handle */
  30. /* N P A M L V H */
  31. [QETH_DBF_SETUP] = {"qeth_setup",
  32. 8, 1, 8, 5, &debug_hex_ascii_view, NULL},
  33. [QETH_DBF_MSG] = {"qeth_msg",
  34. 8, 1, 128, 3, &debug_sprintf_view, NULL},
  35. [QETH_DBF_CTRL] = {"qeth_control",
  36. 8, 1, QETH_DBF_CTRL_LEN, 5, &debug_hex_ascii_view, NULL},
  37. };
  38. EXPORT_SYMBOL_GPL(qeth_dbf);
  39. struct qeth_card_list_struct qeth_core_card_list;
  40. EXPORT_SYMBOL_GPL(qeth_core_card_list);
  41. struct kmem_cache *qeth_core_header_cache;
  42. EXPORT_SYMBOL_GPL(qeth_core_header_cache);
  43. static struct kmem_cache *qeth_qdio_outbuf_cache;
  44. static struct device *qeth_core_root_dev;
  45. static unsigned int known_devices[][6] = QETH_MODELLIST_ARRAY;
  46. static struct lock_class_key qdio_out_skb_queue_key;
  47. static struct mutex qeth_mod_mutex;
  48. static void qeth_send_control_data_cb(struct qeth_channel *,
  49. struct qeth_cmd_buffer *);
  50. static int qeth_issue_next_read(struct qeth_card *);
  51. static struct qeth_cmd_buffer *qeth_get_buffer(struct qeth_channel *);
  52. static void qeth_setup_ccw(struct qeth_channel *, unsigned char *, __u32);
  53. static void qeth_free_buffer_pool(struct qeth_card *);
  54. static int qeth_qdio_establish(struct qeth_card *);
  55. static void qeth_free_qdio_buffers(struct qeth_card *);
  56. static void qeth_notify_skbs(struct qeth_qdio_out_q *queue,
  57. struct qeth_qdio_out_buffer *buf,
  58. enum iucv_tx_notify notification);
  59. static void qeth_release_skbs(struct qeth_qdio_out_buffer *buf);
  60. static void qeth_clear_output_buffer(struct qeth_qdio_out_q *queue,
  61. struct qeth_qdio_out_buffer *buf,
  62. enum qeth_qdio_buffer_states newbufstate);
  63. static int qeth_init_qdio_out_buf(struct qeth_qdio_out_q *, int);
  64. static inline const char *qeth_get_cardname(struct qeth_card *card)
  65. {
  66. if (card->info.guestlan) {
  67. switch (card->info.type) {
  68. case QETH_CARD_TYPE_OSD:
  69. return " Guest LAN QDIO";
  70. case QETH_CARD_TYPE_IQD:
  71. return " Guest LAN Hiper";
  72. case QETH_CARD_TYPE_OSM:
  73. return " Guest LAN QDIO - OSM";
  74. case QETH_CARD_TYPE_OSX:
  75. return " Guest LAN QDIO - OSX";
  76. default:
  77. return " unknown";
  78. }
  79. } else {
  80. switch (card->info.type) {
  81. case QETH_CARD_TYPE_OSD:
  82. return " OSD Express";
  83. case QETH_CARD_TYPE_IQD:
  84. return " HiperSockets";
  85. case QETH_CARD_TYPE_OSN:
  86. return " OSN QDIO";
  87. case QETH_CARD_TYPE_OSM:
  88. return " OSM QDIO";
  89. case QETH_CARD_TYPE_OSX:
  90. return " OSX QDIO";
  91. default:
  92. return " unknown";
  93. }
  94. }
  95. return " n/a";
  96. }
  97. /* max length to be returned: 14 */
  98. const char *qeth_get_cardname_short(struct qeth_card *card)
  99. {
  100. if (card->info.guestlan) {
  101. switch (card->info.type) {
  102. case QETH_CARD_TYPE_OSD:
  103. return "GuestLAN QDIO";
  104. case QETH_CARD_TYPE_IQD:
  105. return "GuestLAN Hiper";
  106. case QETH_CARD_TYPE_OSM:
  107. return "GuestLAN OSM";
  108. case QETH_CARD_TYPE_OSX:
  109. return "GuestLAN OSX";
  110. default:
  111. return "unknown";
  112. }
  113. } else {
  114. switch (card->info.type) {
  115. case QETH_CARD_TYPE_OSD:
  116. switch (card->info.link_type) {
  117. case QETH_LINK_TYPE_FAST_ETH:
  118. return "OSD_100";
  119. case QETH_LINK_TYPE_HSTR:
  120. return "HSTR";
  121. case QETH_LINK_TYPE_GBIT_ETH:
  122. return "OSD_1000";
  123. case QETH_LINK_TYPE_10GBIT_ETH:
  124. return "OSD_10GIG";
  125. case QETH_LINK_TYPE_LANE_ETH100:
  126. return "OSD_FE_LANE";
  127. case QETH_LINK_TYPE_LANE_TR:
  128. return "OSD_TR_LANE";
  129. case QETH_LINK_TYPE_LANE_ETH1000:
  130. return "OSD_GbE_LANE";
  131. case QETH_LINK_TYPE_LANE:
  132. return "OSD_ATM_LANE";
  133. default:
  134. return "OSD_Express";
  135. }
  136. case QETH_CARD_TYPE_IQD:
  137. return "HiperSockets";
  138. case QETH_CARD_TYPE_OSN:
  139. return "OSN";
  140. case QETH_CARD_TYPE_OSM:
  141. return "OSM_1000";
  142. case QETH_CARD_TYPE_OSX:
  143. return "OSX_10GIG";
  144. default:
  145. return "unknown";
  146. }
  147. }
  148. return "n/a";
  149. }
  150. void qeth_set_allowed_threads(struct qeth_card *card, unsigned long threads,
  151. int clear_start_mask)
  152. {
  153. unsigned long flags;
  154. spin_lock_irqsave(&card->thread_mask_lock, flags);
  155. card->thread_allowed_mask = threads;
  156. if (clear_start_mask)
  157. card->thread_start_mask &= threads;
  158. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  159. wake_up(&card->wait_q);
  160. }
  161. EXPORT_SYMBOL_GPL(qeth_set_allowed_threads);
  162. int qeth_threads_running(struct qeth_card *card, unsigned long threads)
  163. {
  164. unsigned long flags;
  165. int rc = 0;
  166. spin_lock_irqsave(&card->thread_mask_lock, flags);
  167. rc = (card->thread_running_mask & threads);
  168. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  169. return rc;
  170. }
  171. EXPORT_SYMBOL_GPL(qeth_threads_running);
  172. int qeth_wait_for_threads(struct qeth_card *card, unsigned long threads)
  173. {
  174. return wait_event_interruptible(card->wait_q,
  175. qeth_threads_running(card, threads) == 0);
  176. }
  177. EXPORT_SYMBOL_GPL(qeth_wait_for_threads);
  178. void qeth_clear_working_pool_list(struct qeth_card *card)
  179. {
  180. struct qeth_buffer_pool_entry *pool_entry, *tmp;
  181. QETH_CARD_TEXT(card, 5, "clwrklst");
  182. list_for_each_entry_safe(pool_entry, tmp,
  183. &card->qdio.in_buf_pool.entry_list, list){
  184. list_del(&pool_entry->list);
  185. }
  186. }
  187. EXPORT_SYMBOL_GPL(qeth_clear_working_pool_list);
  188. static int qeth_alloc_buffer_pool(struct qeth_card *card)
  189. {
  190. struct qeth_buffer_pool_entry *pool_entry;
  191. void *ptr;
  192. int i, j;
  193. QETH_CARD_TEXT(card, 5, "alocpool");
  194. for (i = 0; i < card->qdio.init_pool.buf_count; ++i) {
  195. pool_entry = kzalloc(sizeof(*pool_entry), GFP_KERNEL);
  196. if (!pool_entry) {
  197. qeth_free_buffer_pool(card);
  198. return -ENOMEM;
  199. }
  200. for (j = 0; j < QETH_MAX_BUFFER_ELEMENTS(card); ++j) {
  201. ptr = (void *) __get_free_page(GFP_KERNEL);
  202. if (!ptr) {
  203. while (j > 0)
  204. free_page((unsigned long)
  205. pool_entry->elements[--j]);
  206. kfree(pool_entry);
  207. qeth_free_buffer_pool(card);
  208. return -ENOMEM;
  209. }
  210. pool_entry->elements[j] = ptr;
  211. }
  212. list_add(&pool_entry->init_list,
  213. &card->qdio.init_pool.entry_list);
  214. }
  215. return 0;
  216. }
  217. int qeth_realloc_buffer_pool(struct qeth_card *card, int bufcnt)
  218. {
  219. QETH_CARD_TEXT(card, 2, "realcbp");
  220. if ((card->state != CARD_STATE_DOWN) &&
  221. (card->state != CARD_STATE_RECOVER))
  222. return -EPERM;
  223. /* TODO: steel/add buffers from/to a running card's buffer pool (?) */
  224. qeth_clear_working_pool_list(card);
  225. qeth_free_buffer_pool(card);
  226. card->qdio.in_buf_pool.buf_count = bufcnt;
  227. card->qdio.init_pool.buf_count = bufcnt;
  228. return qeth_alloc_buffer_pool(card);
  229. }
  230. EXPORT_SYMBOL_GPL(qeth_realloc_buffer_pool);
  231. static inline int qeth_cq_init(struct qeth_card *card)
  232. {
  233. int rc;
  234. if (card->options.cq == QETH_CQ_ENABLED) {
  235. QETH_DBF_TEXT(SETUP, 2, "cqinit");
  236. memset(card->qdio.c_q->qdio_bufs, 0,
  237. QDIO_MAX_BUFFERS_PER_Q * sizeof(struct qdio_buffer));
  238. card->qdio.c_q->next_buf_to_init = 127;
  239. rc = do_QDIO(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT,
  240. card->qdio.no_in_queues - 1, 0,
  241. 127);
  242. if (rc) {
  243. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  244. goto out;
  245. }
  246. }
  247. rc = 0;
  248. out:
  249. return rc;
  250. }
  251. static inline int qeth_alloc_cq(struct qeth_card *card)
  252. {
  253. int rc;
  254. if (card->options.cq == QETH_CQ_ENABLED) {
  255. int i;
  256. struct qdio_outbuf_state *outbuf_states;
  257. QETH_DBF_TEXT(SETUP, 2, "cqon");
  258. card->qdio.c_q = kzalloc(sizeof(struct qeth_qdio_q),
  259. GFP_KERNEL);
  260. if (!card->qdio.c_q) {
  261. rc = -1;
  262. goto kmsg_out;
  263. }
  264. QETH_DBF_HEX(SETUP, 2, &card->qdio.c_q, sizeof(void *));
  265. for (i = 0; i < QDIO_MAX_BUFFERS_PER_Q; ++i) {
  266. card->qdio.c_q->bufs[i].buffer =
  267. &card->qdio.c_q->qdio_bufs[i];
  268. }
  269. card->qdio.no_in_queues = 2;
  270. card->qdio.out_bufstates = (struct qdio_outbuf_state *)
  271. kzalloc(card->qdio.no_out_queues *
  272. QDIO_MAX_BUFFERS_PER_Q *
  273. sizeof(struct qdio_outbuf_state), GFP_KERNEL);
  274. outbuf_states = card->qdio.out_bufstates;
  275. if (outbuf_states == NULL) {
  276. rc = -1;
  277. goto free_cq_out;
  278. }
  279. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  280. card->qdio.out_qs[i]->bufstates = outbuf_states;
  281. outbuf_states += QDIO_MAX_BUFFERS_PER_Q;
  282. }
  283. } else {
  284. QETH_DBF_TEXT(SETUP, 2, "nocq");
  285. card->qdio.c_q = NULL;
  286. card->qdio.no_in_queues = 1;
  287. }
  288. QETH_DBF_TEXT_(SETUP, 2, "iqc%d", card->qdio.no_in_queues);
  289. rc = 0;
  290. out:
  291. return rc;
  292. free_cq_out:
  293. kfree(card->qdio.c_q);
  294. card->qdio.c_q = NULL;
  295. kmsg_out:
  296. dev_err(&card->gdev->dev, "Failed to create completion queue\n");
  297. goto out;
  298. }
  299. static inline void qeth_free_cq(struct qeth_card *card)
  300. {
  301. if (card->qdio.c_q) {
  302. --card->qdio.no_in_queues;
  303. kfree(card->qdio.c_q);
  304. card->qdio.c_q = NULL;
  305. }
  306. kfree(card->qdio.out_bufstates);
  307. card->qdio.out_bufstates = NULL;
  308. }
  309. static inline enum iucv_tx_notify qeth_compute_cq_notification(int sbalf15,
  310. int delayed) {
  311. enum iucv_tx_notify n;
  312. switch (sbalf15) {
  313. case 0:
  314. n = delayed ? TX_NOTIFY_DELAYED_OK : TX_NOTIFY_OK;
  315. break;
  316. case 4:
  317. case 16:
  318. case 17:
  319. case 18:
  320. n = delayed ? TX_NOTIFY_DELAYED_UNREACHABLE :
  321. TX_NOTIFY_UNREACHABLE;
  322. break;
  323. default:
  324. n = delayed ? TX_NOTIFY_DELAYED_GENERALERROR :
  325. TX_NOTIFY_GENERALERROR;
  326. break;
  327. }
  328. return n;
  329. }
  330. static inline void qeth_cleanup_handled_pending(struct qeth_qdio_out_q *q,
  331. int bidx, int forced_cleanup)
  332. {
  333. if (q->card->options.cq != QETH_CQ_ENABLED)
  334. return;
  335. if (q->bufs[bidx]->next_pending != NULL) {
  336. struct qeth_qdio_out_buffer *head = q->bufs[bidx];
  337. struct qeth_qdio_out_buffer *c = q->bufs[bidx]->next_pending;
  338. while (c) {
  339. if (forced_cleanup ||
  340. atomic_read(&c->state) ==
  341. QETH_QDIO_BUF_HANDLED_DELAYED) {
  342. struct qeth_qdio_out_buffer *f = c;
  343. QETH_CARD_TEXT(f->q->card, 5, "fp");
  344. QETH_CARD_TEXT_(f->q->card, 5, "%lx", (long) f);
  345. /* release here to avoid interleaving between
  346. outbound tasklet and inbound tasklet
  347. regarding notifications and lifecycle */
  348. qeth_release_skbs(c);
  349. c = f->next_pending;
  350. BUG_ON(head->next_pending != f);
  351. head->next_pending = c;
  352. kmem_cache_free(qeth_qdio_outbuf_cache, f);
  353. } else {
  354. head = c;
  355. c = c->next_pending;
  356. }
  357. }
  358. }
  359. if (forced_cleanup && (atomic_read(&(q->bufs[bidx]->state)) ==
  360. QETH_QDIO_BUF_HANDLED_DELAYED)) {
  361. /* for recovery situations */
  362. q->bufs[bidx]->aob = q->bufstates[bidx].aob;
  363. qeth_init_qdio_out_buf(q, bidx);
  364. QETH_CARD_TEXT(q->card, 2, "clprecov");
  365. }
  366. }
  367. static inline void qeth_qdio_handle_aob(struct qeth_card *card,
  368. unsigned long phys_aob_addr) {
  369. struct qaob *aob;
  370. struct qeth_qdio_out_buffer *buffer;
  371. enum iucv_tx_notify notification;
  372. aob = (struct qaob *) phys_to_virt(phys_aob_addr);
  373. QETH_CARD_TEXT(card, 5, "haob");
  374. QETH_CARD_TEXT_(card, 5, "%lx", phys_aob_addr);
  375. buffer = (struct qeth_qdio_out_buffer *) aob->user1;
  376. QETH_CARD_TEXT_(card, 5, "%lx", aob->user1);
  377. BUG_ON(buffer == NULL);
  378. if (atomic_cmpxchg(&buffer->state, QETH_QDIO_BUF_PRIMED,
  379. QETH_QDIO_BUF_IN_CQ) == QETH_QDIO_BUF_PRIMED) {
  380. notification = TX_NOTIFY_OK;
  381. } else {
  382. BUG_ON(atomic_read(&buffer->state) != QETH_QDIO_BUF_PENDING);
  383. atomic_set(&buffer->state, QETH_QDIO_BUF_IN_CQ);
  384. notification = TX_NOTIFY_DELAYED_OK;
  385. }
  386. if (aob->aorc != 0) {
  387. QETH_CARD_TEXT_(card, 2, "aorc%02X", aob->aorc);
  388. notification = qeth_compute_cq_notification(aob->aorc, 1);
  389. }
  390. qeth_notify_skbs(buffer->q, buffer, notification);
  391. buffer->aob = NULL;
  392. qeth_clear_output_buffer(buffer->q, buffer,
  393. QETH_QDIO_BUF_HANDLED_DELAYED);
  394. /* from here on: do not touch buffer anymore */
  395. qdio_release_aob(aob);
  396. }
  397. static inline int qeth_is_cq(struct qeth_card *card, unsigned int queue)
  398. {
  399. return card->options.cq == QETH_CQ_ENABLED &&
  400. card->qdio.c_q != NULL &&
  401. queue != 0 &&
  402. queue == card->qdio.no_in_queues - 1;
  403. }
  404. static int qeth_issue_next_read(struct qeth_card *card)
  405. {
  406. int rc;
  407. struct qeth_cmd_buffer *iob;
  408. QETH_CARD_TEXT(card, 5, "issnxrd");
  409. if (card->read.state != CH_STATE_UP)
  410. return -EIO;
  411. iob = qeth_get_buffer(&card->read);
  412. if (!iob) {
  413. dev_warn(&card->gdev->dev, "The qeth device driver "
  414. "failed to recover an error on the device\n");
  415. QETH_DBF_MESSAGE(2, "%s issue_next_read failed: no iob "
  416. "available\n", dev_name(&card->gdev->dev));
  417. return -ENOMEM;
  418. }
  419. qeth_setup_ccw(&card->read, iob->data, QETH_BUFSIZE);
  420. QETH_CARD_TEXT(card, 6, "noirqpnd");
  421. rc = ccw_device_start(card->read.ccwdev, &card->read.ccw,
  422. (addr_t) iob, 0, 0);
  423. if (rc) {
  424. QETH_DBF_MESSAGE(2, "%s error in starting next read ccw! "
  425. "rc=%i\n", dev_name(&card->gdev->dev), rc);
  426. atomic_set(&card->read.irq_pending, 0);
  427. card->read_or_write_problem = 1;
  428. qeth_schedule_recovery(card);
  429. wake_up(&card->wait_q);
  430. }
  431. return rc;
  432. }
  433. static struct qeth_reply *qeth_alloc_reply(struct qeth_card *card)
  434. {
  435. struct qeth_reply *reply;
  436. reply = kzalloc(sizeof(struct qeth_reply), GFP_ATOMIC);
  437. if (reply) {
  438. atomic_set(&reply->refcnt, 1);
  439. atomic_set(&reply->received, 0);
  440. reply->card = card;
  441. };
  442. return reply;
  443. }
  444. static void qeth_get_reply(struct qeth_reply *reply)
  445. {
  446. WARN_ON(atomic_read(&reply->refcnt) <= 0);
  447. atomic_inc(&reply->refcnt);
  448. }
  449. static void qeth_put_reply(struct qeth_reply *reply)
  450. {
  451. WARN_ON(atomic_read(&reply->refcnt) <= 0);
  452. if (atomic_dec_and_test(&reply->refcnt))
  453. kfree(reply);
  454. }
  455. static void qeth_issue_ipa_msg(struct qeth_ipa_cmd *cmd, int rc,
  456. struct qeth_card *card)
  457. {
  458. char *ipa_name;
  459. int com = cmd->hdr.command;
  460. ipa_name = qeth_get_ipa_cmd_name(com);
  461. if (rc)
  462. QETH_DBF_MESSAGE(2, "IPA: %s(x%X) for %s/%s returned "
  463. "x%X \"%s\"\n",
  464. ipa_name, com, dev_name(&card->gdev->dev),
  465. QETH_CARD_IFNAME(card), rc,
  466. qeth_get_ipa_msg(rc));
  467. else
  468. QETH_DBF_MESSAGE(5, "IPA: %s(x%X) for %s/%s succeeded\n",
  469. ipa_name, com, dev_name(&card->gdev->dev),
  470. QETH_CARD_IFNAME(card));
  471. }
  472. static struct qeth_ipa_cmd *qeth_check_ipa_data(struct qeth_card *card,
  473. struct qeth_cmd_buffer *iob)
  474. {
  475. struct qeth_ipa_cmd *cmd = NULL;
  476. QETH_CARD_TEXT(card, 5, "chkipad");
  477. if (IS_IPA(iob->data)) {
  478. cmd = (struct qeth_ipa_cmd *) PDU_ENCAPSULATION(iob->data);
  479. if (IS_IPA_REPLY(cmd)) {
  480. if (cmd->hdr.command != IPA_CMD_SETCCID &&
  481. cmd->hdr.command != IPA_CMD_DELCCID &&
  482. cmd->hdr.command != IPA_CMD_MODCCID &&
  483. cmd->hdr.command != IPA_CMD_SET_DIAG_ASS)
  484. qeth_issue_ipa_msg(cmd,
  485. cmd->hdr.return_code, card);
  486. return cmd;
  487. } else {
  488. switch (cmd->hdr.command) {
  489. case IPA_CMD_STOPLAN:
  490. dev_warn(&card->gdev->dev,
  491. "The link for interface %s on CHPID"
  492. " 0x%X failed\n",
  493. QETH_CARD_IFNAME(card),
  494. card->info.chpid);
  495. card->lan_online = 0;
  496. if (card->dev && netif_carrier_ok(card->dev))
  497. netif_carrier_off(card->dev);
  498. return NULL;
  499. case IPA_CMD_STARTLAN:
  500. dev_info(&card->gdev->dev,
  501. "The link for %s on CHPID 0x%X has"
  502. " been restored\n",
  503. QETH_CARD_IFNAME(card),
  504. card->info.chpid);
  505. netif_carrier_on(card->dev);
  506. card->lan_online = 1;
  507. if (card->info.hwtrap)
  508. card->info.hwtrap = 2;
  509. qeth_schedule_recovery(card);
  510. return NULL;
  511. case IPA_CMD_MODCCID:
  512. return cmd;
  513. case IPA_CMD_REGISTER_LOCAL_ADDR:
  514. QETH_CARD_TEXT(card, 3, "irla");
  515. break;
  516. case IPA_CMD_UNREGISTER_LOCAL_ADDR:
  517. QETH_CARD_TEXT(card, 3, "urla");
  518. break;
  519. default:
  520. QETH_DBF_MESSAGE(2, "Received data is IPA "
  521. "but not a reply!\n");
  522. break;
  523. }
  524. }
  525. }
  526. return cmd;
  527. }
  528. void qeth_clear_ipacmd_list(struct qeth_card *card)
  529. {
  530. struct qeth_reply *reply, *r;
  531. unsigned long flags;
  532. QETH_CARD_TEXT(card, 4, "clipalst");
  533. spin_lock_irqsave(&card->lock, flags);
  534. list_for_each_entry_safe(reply, r, &card->cmd_waiter_list, list) {
  535. qeth_get_reply(reply);
  536. reply->rc = -EIO;
  537. atomic_inc(&reply->received);
  538. list_del_init(&reply->list);
  539. wake_up(&reply->wait_q);
  540. qeth_put_reply(reply);
  541. }
  542. spin_unlock_irqrestore(&card->lock, flags);
  543. atomic_set(&card->write.irq_pending, 0);
  544. }
  545. EXPORT_SYMBOL_GPL(qeth_clear_ipacmd_list);
  546. static int qeth_check_idx_response(struct qeth_card *card,
  547. unsigned char *buffer)
  548. {
  549. if (!buffer)
  550. return 0;
  551. QETH_DBF_HEX(CTRL, 2, buffer, QETH_DBF_CTRL_LEN);
  552. if ((buffer[2] & 0xc0) == 0xc0) {
  553. QETH_DBF_MESSAGE(2, "received an IDX TERMINATE "
  554. "with cause code 0x%02x%s\n",
  555. buffer[4],
  556. ((buffer[4] == 0x22) ?
  557. " -- try another portname" : ""));
  558. QETH_CARD_TEXT(card, 2, "ckidxres");
  559. QETH_CARD_TEXT(card, 2, " idxterm");
  560. QETH_CARD_TEXT_(card, 2, " rc%d", -EIO);
  561. if (buffer[4] == 0xf6) {
  562. dev_err(&card->gdev->dev,
  563. "The qeth device is not configured "
  564. "for the OSI layer required by z/VM\n");
  565. return -EPERM;
  566. }
  567. return -EIO;
  568. }
  569. return 0;
  570. }
  571. static void qeth_setup_ccw(struct qeth_channel *channel, unsigned char *iob,
  572. __u32 len)
  573. {
  574. struct qeth_card *card;
  575. card = CARD_FROM_CDEV(channel->ccwdev);
  576. QETH_CARD_TEXT(card, 4, "setupccw");
  577. if (channel == &card->read)
  578. memcpy(&channel->ccw, READ_CCW, sizeof(struct ccw1));
  579. else
  580. memcpy(&channel->ccw, WRITE_CCW, sizeof(struct ccw1));
  581. channel->ccw.count = len;
  582. channel->ccw.cda = (__u32) __pa(iob);
  583. }
  584. static struct qeth_cmd_buffer *__qeth_get_buffer(struct qeth_channel *channel)
  585. {
  586. __u8 index;
  587. QETH_CARD_TEXT(CARD_FROM_CDEV(channel->ccwdev), 6, "getbuff");
  588. index = channel->io_buf_no;
  589. do {
  590. if (channel->iob[index].state == BUF_STATE_FREE) {
  591. channel->iob[index].state = BUF_STATE_LOCKED;
  592. channel->io_buf_no = (channel->io_buf_no + 1) %
  593. QETH_CMD_BUFFER_NO;
  594. memset(channel->iob[index].data, 0, QETH_BUFSIZE);
  595. return channel->iob + index;
  596. }
  597. index = (index + 1) % QETH_CMD_BUFFER_NO;
  598. } while (index != channel->io_buf_no);
  599. return NULL;
  600. }
  601. void qeth_release_buffer(struct qeth_channel *channel,
  602. struct qeth_cmd_buffer *iob)
  603. {
  604. unsigned long flags;
  605. QETH_CARD_TEXT(CARD_FROM_CDEV(channel->ccwdev), 6, "relbuff");
  606. spin_lock_irqsave(&channel->iob_lock, flags);
  607. memset(iob->data, 0, QETH_BUFSIZE);
  608. iob->state = BUF_STATE_FREE;
  609. iob->callback = qeth_send_control_data_cb;
  610. iob->rc = 0;
  611. spin_unlock_irqrestore(&channel->iob_lock, flags);
  612. wake_up(&channel->wait_q);
  613. }
  614. EXPORT_SYMBOL_GPL(qeth_release_buffer);
  615. static struct qeth_cmd_buffer *qeth_get_buffer(struct qeth_channel *channel)
  616. {
  617. struct qeth_cmd_buffer *buffer = NULL;
  618. unsigned long flags;
  619. spin_lock_irqsave(&channel->iob_lock, flags);
  620. buffer = __qeth_get_buffer(channel);
  621. spin_unlock_irqrestore(&channel->iob_lock, flags);
  622. return buffer;
  623. }
  624. struct qeth_cmd_buffer *qeth_wait_for_buffer(struct qeth_channel *channel)
  625. {
  626. struct qeth_cmd_buffer *buffer;
  627. wait_event(channel->wait_q,
  628. ((buffer = qeth_get_buffer(channel)) != NULL));
  629. return buffer;
  630. }
  631. EXPORT_SYMBOL_GPL(qeth_wait_for_buffer);
  632. void qeth_clear_cmd_buffers(struct qeth_channel *channel)
  633. {
  634. int cnt;
  635. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++)
  636. qeth_release_buffer(channel, &channel->iob[cnt]);
  637. channel->buf_no = 0;
  638. channel->io_buf_no = 0;
  639. }
  640. EXPORT_SYMBOL_GPL(qeth_clear_cmd_buffers);
  641. static void qeth_send_control_data_cb(struct qeth_channel *channel,
  642. struct qeth_cmd_buffer *iob)
  643. {
  644. struct qeth_card *card;
  645. struct qeth_reply *reply, *r;
  646. struct qeth_ipa_cmd *cmd;
  647. unsigned long flags;
  648. int keep_reply;
  649. int rc = 0;
  650. card = CARD_FROM_CDEV(channel->ccwdev);
  651. QETH_CARD_TEXT(card, 4, "sndctlcb");
  652. rc = qeth_check_idx_response(card, iob->data);
  653. switch (rc) {
  654. case 0:
  655. break;
  656. case -EIO:
  657. qeth_clear_ipacmd_list(card);
  658. qeth_schedule_recovery(card);
  659. /* fall through */
  660. default:
  661. goto out;
  662. }
  663. cmd = qeth_check_ipa_data(card, iob);
  664. if ((cmd == NULL) && (card->state != CARD_STATE_DOWN))
  665. goto out;
  666. /*in case of OSN : check if cmd is set */
  667. if (card->info.type == QETH_CARD_TYPE_OSN &&
  668. cmd &&
  669. cmd->hdr.command != IPA_CMD_STARTLAN &&
  670. card->osn_info.assist_cb != NULL) {
  671. card->osn_info.assist_cb(card->dev, cmd);
  672. goto out;
  673. }
  674. spin_lock_irqsave(&card->lock, flags);
  675. list_for_each_entry_safe(reply, r, &card->cmd_waiter_list, list) {
  676. if ((reply->seqno == QETH_IDX_COMMAND_SEQNO) ||
  677. ((cmd) && (reply->seqno == cmd->hdr.seqno))) {
  678. qeth_get_reply(reply);
  679. list_del_init(&reply->list);
  680. spin_unlock_irqrestore(&card->lock, flags);
  681. keep_reply = 0;
  682. if (reply->callback != NULL) {
  683. if (cmd) {
  684. reply->offset = (__u16)((char *)cmd -
  685. (char *)iob->data);
  686. keep_reply = reply->callback(card,
  687. reply,
  688. (unsigned long)cmd);
  689. } else
  690. keep_reply = reply->callback(card,
  691. reply,
  692. (unsigned long)iob);
  693. }
  694. if (cmd)
  695. reply->rc = (u16) cmd->hdr.return_code;
  696. else if (iob->rc)
  697. reply->rc = iob->rc;
  698. if (keep_reply) {
  699. spin_lock_irqsave(&card->lock, flags);
  700. list_add_tail(&reply->list,
  701. &card->cmd_waiter_list);
  702. spin_unlock_irqrestore(&card->lock, flags);
  703. } else {
  704. atomic_inc(&reply->received);
  705. wake_up(&reply->wait_q);
  706. }
  707. qeth_put_reply(reply);
  708. goto out;
  709. }
  710. }
  711. spin_unlock_irqrestore(&card->lock, flags);
  712. out:
  713. memcpy(&card->seqno.pdu_hdr_ack,
  714. QETH_PDU_HEADER_SEQ_NO(iob->data),
  715. QETH_SEQ_NO_LENGTH);
  716. qeth_release_buffer(channel, iob);
  717. }
  718. static int qeth_setup_channel(struct qeth_channel *channel)
  719. {
  720. int cnt;
  721. QETH_DBF_TEXT(SETUP, 2, "setupch");
  722. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++) {
  723. channel->iob[cnt].data =
  724. kzalloc(QETH_BUFSIZE, GFP_DMA|GFP_KERNEL);
  725. if (channel->iob[cnt].data == NULL)
  726. break;
  727. channel->iob[cnt].state = BUF_STATE_FREE;
  728. channel->iob[cnt].channel = channel;
  729. channel->iob[cnt].callback = qeth_send_control_data_cb;
  730. channel->iob[cnt].rc = 0;
  731. }
  732. if (cnt < QETH_CMD_BUFFER_NO) {
  733. while (cnt-- > 0)
  734. kfree(channel->iob[cnt].data);
  735. return -ENOMEM;
  736. }
  737. channel->buf_no = 0;
  738. channel->io_buf_no = 0;
  739. atomic_set(&channel->irq_pending, 0);
  740. spin_lock_init(&channel->iob_lock);
  741. init_waitqueue_head(&channel->wait_q);
  742. return 0;
  743. }
  744. static int qeth_set_thread_start_bit(struct qeth_card *card,
  745. unsigned long thread)
  746. {
  747. unsigned long flags;
  748. spin_lock_irqsave(&card->thread_mask_lock, flags);
  749. if (!(card->thread_allowed_mask & thread) ||
  750. (card->thread_start_mask & thread)) {
  751. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  752. return -EPERM;
  753. }
  754. card->thread_start_mask |= thread;
  755. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  756. return 0;
  757. }
  758. void qeth_clear_thread_start_bit(struct qeth_card *card, unsigned long thread)
  759. {
  760. unsigned long flags;
  761. spin_lock_irqsave(&card->thread_mask_lock, flags);
  762. card->thread_start_mask &= ~thread;
  763. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  764. wake_up(&card->wait_q);
  765. }
  766. EXPORT_SYMBOL_GPL(qeth_clear_thread_start_bit);
  767. void qeth_clear_thread_running_bit(struct qeth_card *card, unsigned long thread)
  768. {
  769. unsigned long flags;
  770. spin_lock_irqsave(&card->thread_mask_lock, flags);
  771. card->thread_running_mask &= ~thread;
  772. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  773. wake_up(&card->wait_q);
  774. }
  775. EXPORT_SYMBOL_GPL(qeth_clear_thread_running_bit);
  776. static int __qeth_do_run_thread(struct qeth_card *card, unsigned long thread)
  777. {
  778. unsigned long flags;
  779. int rc = 0;
  780. spin_lock_irqsave(&card->thread_mask_lock, flags);
  781. if (card->thread_start_mask & thread) {
  782. if ((card->thread_allowed_mask & thread) &&
  783. !(card->thread_running_mask & thread)) {
  784. rc = 1;
  785. card->thread_start_mask &= ~thread;
  786. card->thread_running_mask |= thread;
  787. } else
  788. rc = -EPERM;
  789. }
  790. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  791. return rc;
  792. }
  793. int qeth_do_run_thread(struct qeth_card *card, unsigned long thread)
  794. {
  795. int rc = 0;
  796. wait_event(card->wait_q,
  797. (rc = __qeth_do_run_thread(card, thread)) >= 0);
  798. return rc;
  799. }
  800. EXPORT_SYMBOL_GPL(qeth_do_run_thread);
  801. void qeth_schedule_recovery(struct qeth_card *card)
  802. {
  803. QETH_CARD_TEXT(card, 2, "startrec");
  804. if (qeth_set_thread_start_bit(card, QETH_RECOVER_THREAD) == 0)
  805. schedule_work(&card->kernel_thread_starter);
  806. }
  807. EXPORT_SYMBOL_GPL(qeth_schedule_recovery);
  808. static int qeth_get_problem(struct ccw_device *cdev, struct irb *irb)
  809. {
  810. int dstat, cstat;
  811. char *sense;
  812. struct qeth_card *card;
  813. sense = (char *) irb->ecw;
  814. cstat = irb->scsw.cmd.cstat;
  815. dstat = irb->scsw.cmd.dstat;
  816. card = CARD_FROM_CDEV(cdev);
  817. if (cstat & (SCHN_STAT_CHN_CTRL_CHK | SCHN_STAT_INTF_CTRL_CHK |
  818. SCHN_STAT_CHN_DATA_CHK | SCHN_STAT_CHAIN_CHECK |
  819. SCHN_STAT_PROT_CHECK | SCHN_STAT_PROG_CHECK)) {
  820. QETH_CARD_TEXT(card, 2, "CGENCHK");
  821. dev_warn(&cdev->dev, "The qeth device driver "
  822. "failed to recover an error on the device\n");
  823. QETH_DBF_MESSAGE(2, "%s check on device dstat=x%x, cstat=x%x\n",
  824. dev_name(&cdev->dev), dstat, cstat);
  825. print_hex_dump(KERN_WARNING, "qeth: irb ", DUMP_PREFIX_OFFSET,
  826. 16, 1, irb, 64, 1);
  827. return 1;
  828. }
  829. if (dstat & DEV_STAT_UNIT_CHECK) {
  830. if (sense[SENSE_RESETTING_EVENT_BYTE] &
  831. SENSE_RESETTING_EVENT_FLAG) {
  832. QETH_CARD_TEXT(card, 2, "REVIND");
  833. return 1;
  834. }
  835. if (sense[SENSE_COMMAND_REJECT_BYTE] &
  836. SENSE_COMMAND_REJECT_FLAG) {
  837. QETH_CARD_TEXT(card, 2, "CMDREJi");
  838. return 1;
  839. }
  840. if ((sense[2] == 0xaf) && (sense[3] == 0xfe)) {
  841. QETH_CARD_TEXT(card, 2, "AFFE");
  842. return 1;
  843. }
  844. if ((!sense[0]) && (!sense[1]) && (!sense[2]) && (!sense[3])) {
  845. QETH_CARD_TEXT(card, 2, "ZEROSEN");
  846. return 0;
  847. }
  848. QETH_CARD_TEXT(card, 2, "DGENCHK");
  849. return 1;
  850. }
  851. return 0;
  852. }
  853. static long __qeth_check_irb_error(struct ccw_device *cdev,
  854. unsigned long intparm, struct irb *irb)
  855. {
  856. struct qeth_card *card;
  857. card = CARD_FROM_CDEV(cdev);
  858. if (!IS_ERR(irb))
  859. return 0;
  860. switch (PTR_ERR(irb)) {
  861. case -EIO:
  862. QETH_DBF_MESSAGE(2, "%s i/o-error on device\n",
  863. dev_name(&cdev->dev));
  864. QETH_CARD_TEXT(card, 2, "ckirberr");
  865. QETH_CARD_TEXT_(card, 2, " rc%d", -EIO);
  866. break;
  867. case -ETIMEDOUT:
  868. dev_warn(&cdev->dev, "A hardware operation timed out"
  869. " on the device\n");
  870. QETH_CARD_TEXT(card, 2, "ckirberr");
  871. QETH_CARD_TEXT_(card, 2, " rc%d", -ETIMEDOUT);
  872. if (intparm == QETH_RCD_PARM) {
  873. if (card && (card->data.ccwdev == cdev)) {
  874. card->data.state = CH_STATE_DOWN;
  875. wake_up(&card->wait_q);
  876. }
  877. }
  878. break;
  879. default:
  880. QETH_DBF_MESSAGE(2, "%s unknown error %ld on device\n",
  881. dev_name(&cdev->dev), PTR_ERR(irb));
  882. QETH_CARD_TEXT(card, 2, "ckirberr");
  883. QETH_CARD_TEXT(card, 2, " rc???");
  884. }
  885. return PTR_ERR(irb);
  886. }
  887. static void qeth_irq(struct ccw_device *cdev, unsigned long intparm,
  888. struct irb *irb)
  889. {
  890. int rc;
  891. int cstat, dstat;
  892. struct qeth_cmd_buffer *buffer;
  893. struct qeth_channel *channel;
  894. struct qeth_card *card;
  895. struct qeth_cmd_buffer *iob;
  896. __u8 index;
  897. if (__qeth_check_irb_error(cdev, intparm, irb))
  898. return;
  899. cstat = irb->scsw.cmd.cstat;
  900. dstat = irb->scsw.cmd.dstat;
  901. card = CARD_FROM_CDEV(cdev);
  902. if (!card)
  903. return;
  904. QETH_CARD_TEXT(card, 5, "irq");
  905. if (card->read.ccwdev == cdev) {
  906. channel = &card->read;
  907. QETH_CARD_TEXT(card, 5, "read");
  908. } else if (card->write.ccwdev == cdev) {
  909. channel = &card->write;
  910. QETH_CARD_TEXT(card, 5, "write");
  911. } else {
  912. channel = &card->data;
  913. QETH_CARD_TEXT(card, 5, "data");
  914. }
  915. atomic_set(&channel->irq_pending, 0);
  916. if (irb->scsw.cmd.fctl & (SCSW_FCTL_CLEAR_FUNC))
  917. channel->state = CH_STATE_STOPPED;
  918. if (irb->scsw.cmd.fctl & (SCSW_FCTL_HALT_FUNC))
  919. channel->state = CH_STATE_HALTED;
  920. /*let's wake up immediately on data channel*/
  921. if ((channel == &card->data) && (intparm != 0) &&
  922. (intparm != QETH_RCD_PARM))
  923. goto out;
  924. if (intparm == QETH_CLEAR_CHANNEL_PARM) {
  925. QETH_CARD_TEXT(card, 6, "clrchpar");
  926. /* we don't have to handle this further */
  927. intparm = 0;
  928. }
  929. if (intparm == QETH_HALT_CHANNEL_PARM) {
  930. QETH_CARD_TEXT(card, 6, "hltchpar");
  931. /* we don't have to handle this further */
  932. intparm = 0;
  933. }
  934. if ((dstat & DEV_STAT_UNIT_EXCEP) ||
  935. (dstat & DEV_STAT_UNIT_CHECK) ||
  936. (cstat)) {
  937. if (irb->esw.esw0.erw.cons) {
  938. dev_warn(&channel->ccwdev->dev,
  939. "The qeth device driver failed to recover "
  940. "an error on the device\n");
  941. QETH_DBF_MESSAGE(2, "%s sense data available. cstat "
  942. "0x%X dstat 0x%X\n",
  943. dev_name(&channel->ccwdev->dev), cstat, dstat);
  944. print_hex_dump(KERN_WARNING, "qeth: irb ",
  945. DUMP_PREFIX_OFFSET, 16, 1, irb, 32, 1);
  946. print_hex_dump(KERN_WARNING, "qeth: sense data ",
  947. DUMP_PREFIX_OFFSET, 16, 1, irb->ecw, 32, 1);
  948. }
  949. if (intparm == QETH_RCD_PARM) {
  950. channel->state = CH_STATE_DOWN;
  951. goto out;
  952. }
  953. rc = qeth_get_problem(cdev, irb);
  954. if (rc) {
  955. qeth_clear_ipacmd_list(card);
  956. qeth_schedule_recovery(card);
  957. goto out;
  958. }
  959. }
  960. if (intparm == QETH_RCD_PARM) {
  961. channel->state = CH_STATE_RCD_DONE;
  962. goto out;
  963. }
  964. if (intparm) {
  965. buffer = (struct qeth_cmd_buffer *) __va((addr_t)intparm);
  966. buffer->state = BUF_STATE_PROCESSED;
  967. }
  968. if (channel == &card->data)
  969. return;
  970. if (channel == &card->read &&
  971. channel->state == CH_STATE_UP)
  972. qeth_issue_next_read(card);
  973. iob = channel->iob;
  974. index = channel->buf_no;
  975. while (iob[index].state == BUF_STATE_PROCESSED) {
  976. if (iob[index].callback != NULL)
  977. iob[index].callback(channel, iob + index);
  978. index = (index + 1) % QETH_CMD_BUFFER_NO;
  979. }
  980. channel->buf_no = index;
  981. out:
  982. wake_up(&card->wait_q);
  983. return;
  984. }
  985. static void qeth_notify_skbs(struct qeth_qdio_out_q *q,
  986. struct qeth_qdio_out_buffer *buf,
  987. enum iucv_tx_notify notification)
  988. {
  989. struct sk_buff *skb;
  990. if (skb_queue_empty(&buf->skb_list))
  991. goto out;
  992. skb = skb_peek(&buf->skb_list);
  993. while (skb) {
  994. QETH_CARD_TEXT_(q->card, 5, "skbn%d", notification);
  995. QETH_CARD_TEXT_(q->card, 5, "%lx", (long) skb);
  996. if (skb->protocol == ETH_P_AF_IUCV) {
  997. if (skb->sk) {
  998. struct iucv_sock *iucv = iucv_sk(skb->sk);
  999. iucv->sk_txnotify(skb, notification);
  1000. }
  1001. }
  1002. if (skb_queue_is_last(&buf->skb_list, skb))
  1003. skb = NULL;
  1004. else
  1005. skb = skb_queue_next(&buf->skb_list, skb);
  1006. }
  1007. out:
  1008. return;
  1009. }
  1010. static void qeth_release_skbs(struct qeth_qdio_out_buffer *buf)
  1011. {
  1012. struct sk_buff *skb;
  1013. struct iucv_sock *iucv;
  1014. int notify_general_error = 0;
  1015. if (atomic_read(&buf->state) == QETH_QDIO_BUF_PENDING)
  1016. notify_general_error = 1;
  1017. /* release may never happen from within CQ tasklet scope */
  1018. BUG_ON(atomic_read(&buf->state) == QETH_QDIO_BUF_IN_CQ);
  1019. skb = skb_dequeue(&buf->skb_list);
  1020. while (skb) {
  1021. QETH_CARD_TEXT(buf->q->card, 5, "skbr");
  1022. QETH_CARD_TEXT_(buf->q->card, 5, "%lx", (long) skb);
  1023. if (notify_general_error && skb->protocol == ETH_P_AF_IUCV) {
  1024. if (skb->sk) {
  1025. iucv = iucv_sk(skb->sk);
  1026. iucv->sk_txnotify(skb, TX_NOTIFY_GENERALERROR);
  1027. }
  1028. }
  1029. atomic_dec(&skb->users);
  1030. dev_kfree_skb_any(skb);
  1031. skb = skb_dequeue(&buf->skb_list);
  1032. }
  1033. }
  1034. static void qeth_clear_output_buffer(struct qeth_qdio_out_q *queue,
  1035. struct qeth_qdio_out_buffer *buf,
  1036. enum qeth_qdio_buffer_states newbufstate)
  1037. {
  1038. int i;
  1039. /* is PCI flag set on buffer? */
  1040. if (buf->buffer->element[0].sflags & SBAL_SFLAGS0_PCI_REQ)
  1041. atomic_dec(&queue->set_pci_flags_count);
  1042. if (newbufstate == QETH_QDIO_BUF_EMPTY) {
  1043. qeth_release_skbs(buf);
  1044. }
  1045. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(queue->card); ++i) {
  1046. if (buf->buffer->element[i].addr && buf->is_header[i])
  1047. kmem_cache_free(qeth_core_header_cache,
  1048. buf->buffer->element[i].addr);
  1049. buf->is_header[i] = 0;
  1050. buf->buffer->element[i].length = 0;
  1051. buf->buffer->element[i].addr = NULL;
  1052. buf->buffer->element[i].eflags = 0;
  1053. buf->buffer->element[i].sflags = 0;
  1054. }
  1055. buf->buffer->element[15].eflags = 0;
  1056. buf->buffer->element[15].sflags = 0;
  1057. buf->next_element_to_fill = 0;
  1058. atomic_set(&buf->state, newbufstate);
  1059. }
  1060. static void qeth_clear_outq_buffers(struct qeth_qdio_out_q *q, int free)
  1061. {
  1062. int j;
  1063. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j) {
  1064. if (!q->bufs[j])
  1065. continue;
  1066. qeth_cleanup_handled_pending(q, j, 1);
  1067. qeth_clear_output_buffer(q, q->bufs[j], QETH_QDIO_BUF_EMPTY);
  1068. if (free) {
  1069. kmem_cache_free(qeth_qdio_outbuf_cache, q->bufs[j]);
  1070. q->bufs[j] = NULL;
  1071. }
  1072. }
  1073. }
  1074. void qeth_clear_qdio_buffers(struct qeth_card *card)
  1075. {
  1076. int i;
  1077. QETH_CARD_TEXT(card, 2, "clearqdbf");
  1078. /* clear outbound buffers to free skbs */
  1079. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  1080. if (card->qdio.out_qs[i]) {
  1081. qeth_clear_outq_buffers(card->qdio.out_qs[i], 0);
  1082. }
  1083. }
  1084. }
  1085. EXPORT_SYMBOL_GPL(qeth_clear_qdio_buffers);
  1086. static void qeth_free_buffer_pool(struct qeth_card *card)
  1087. {
  1088. struct qeth_buffer_pool_entry *pool_entry, *tmp;
  1089. int i = 0;
  1090. list_for_each_entry_safe(pool_entry, tmp,
  1091. &card->qdio.init_pool.entry_list, init_list){
  1092. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i)
  1093. free_page((unsigned long)pool_entry->elements[i]);
  1094. list_del(&pool_entry->init_list);
  1095. kfree(pool_entry);
  1096. }
  1097. }
  1098. static void qeth_free_qdio_buffers(struct qeth_card *card)
  1099. {
  1100. int i, j;
  1101. if (atomic_xchg(&card->qdio.state, QETH_QDIO_UNINITIALIZED) ==
  1102. QETH_QDIO_UNINITIALIZED)
  1103. return;
  1104. qeth_free_cq(card);
  1105. cancel_delayed_work_sync(&card->buffer_reclaim_work);
  1106. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j)
  1107. dev_kfree_skb_any(card->qdio.in_q->bufs[j].rx_skb);
  1108. kfree(card->qdio.in_q);
  1109. card->qdio.in_q = NULL;
  1110. /* inbound buffer pool */
  1111. qeth_free_buffer_pool(card);
  1112. /* free outbound qdio_qs */
  1113. if (card->qdio.out_qs) {
  1114. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  1115. qeth_clear_outq_buffers(card->qdio.out_qs[i], 1);
  1116. kfree(card->qdio.out_qs[i]);
  1117. }
  1118. kfree(card->qdio.out_qs);
  1119. card->qdio.out_qs = NULL;
  1120. }
  1121. }
  1122. static void qeth_clean_channel(struct qeth_channel *channel)
  1123. {
  1124. int cnt;
  1125. QETH_DBF_TEXT(SETUP, 2, "freech");
  1126. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++)
  1127. kfree(channel->iob[cnt].data);
  1128. }
  1129. static void qeth_get_channel_path_desc(struct qeth_card *card)
  1130. {
  1131. struct ccw_device *ccwdev;
  1132. struct channelPath_dsc {
  1133. u8 flags;
  1134. u8 lsn;
  1135. u8 desc;
  1136. u8 chpid;
  1137. u8 swla;
  1138. u8 zeroes;
  1139. u8 chla;
  1140. u8 chpp;
  1141. } *chp_dsc;
  1142. QETH_DBF_TEXT(SETUP, 2, "chp_desc");
  1143. ccwdev = card->data.ccwdev;
  1144. chp_dsc = (struct channelPath_dsc *)ccw_device_get_chp_desc(ccwdev, 0);
  1145. if (chp_dsc != NULL) {
  1146. if (card->info.type != QETH_CARD_TYPE_IQD) {
  1147. /* CHPP field bit 6 == 1 -> single queue */
  1148. if ((chp_dsc->chpp & 0x02) == 0x02) {
  1149. if ((atomic_read(&card->qdio.state) !=
  1150. QETH_QDIO_UNINITIALIZED) &&
  1151. (card->qdio.no_out_queues == 4))
  1152. /* change from 4 to 1 outbound queues */
  1153. qeth_free_qdio_buffers(card);
  1154. card->qdio.no_out_queues = 1;
  1155. if (card->qdio.default_out_queue != 0)
  1156. dev_info(&card->gdev->dev,
  1157. "Priority Queueing not supported\n");
  1158. card->qdio.default_out_queue = 0;
  1159. } else {
  1160. if ((atomic_read(&card->qdio.state) !=
  1161. QETH_QDIO_UNINITIALIZED) &&
  1162. (card->qdio.no_out_queues == 1)) {
  1163. /* change from 1 to 4 outbound queues */
  1164. qeth_free_qdio_buffers(card);
  1165. card->qdio.default_out_queue = 2;
  1166. }
  1167. card->qdio.no_out_queues = 4;
  1168. }
  1169. }
  1170. card->info.func_level = 0x4100 + chp_dsc->desc;
  1171. kfree(chp_dsc);
  1172. }
  1173. QETH_DBF_TEXT_(SETUP, 2, "nr:%x", card->qdio.no_out_queues);
  1174. QETH_DBF_TEXT_(SETUP, 2, "lvl:%02x", card->info.func_level);
  1175. return;
  1176. }
  1177. static void qeth_init_qdio_info(struct qeth_card *card)
  1178. {
  1179. QETH_DBF_TEXT(SETUP, 4, "intqdinf");
  1180. atomic_set(&card->qdio.state, QETH_QDIO_UNINITIALIZED);
  1181. /* inbound */
  1182. card->qdio.in_buf_size = QETH_IN_BUF_SIZE_DEFAULT;
  1183. if (card->info.type == QETH_CARD_TYPE_IQD)
  1184. card->qdio.init_pool.buf_count = QETH_IN_BUF_COUNT_HSDEFAULT;
  1185. else
  1186. card->qdio.init_pool.buf_count = QETH_IN_BUF_COUNT_DEFAULT;
  1187. card->qdio.in_buf_pool.buf_count = card->qdio.init_pool.buf_count;
  1188. INIT_LIST_HEAD(&card->qdio.in_buf_pool.entry_list);
  1189. INIT_LIST_HEAD(&card->qdio.init_pool.entry_list);
  1190. }
  1191. static void qeth_set_intial_options(struct qeth_card *card)
  1192. {
  1193. card->options.route4.type = NO_ROUTER;
  1194. card->options.route6.type = NO_ROUTER;
  1195. card->options.fake_broadcast = 0;
  1196. card->options.add_hhlen = DEFAULT_ADD_HHLEN;
  1197. card->options.performance_stats = 0;
  1198. card->options.rx_sg_cb = QETH_RX_SG_CB;
  1199. card->options.isolation = ISOLATION_MODE_NONE;
  1200. card->options.cq = QETH_CQ_DISABLED;
  1201. }
  1202. static int qeth_do_start_thread(struct qeth_card *card, unsigned long thread)
  1203. {
  1204. unsigned long flags;
  1205. int rc = 0;
  1206. spin_lock_irqsave(&card->thread_mask_lock, flags);
  1207. QETH_CARD_TEXT_(card, 4, " %02x%02x%02x",
  1208. (u8) card->thread_start_mask,
  1209. (u8) card->thread_allowed_mask,
  1210. (u8) card->thread_running_mask);
  1211. rc = (card->thread_start_mask & thread);
  1212. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  1213. return rc;
  1214. }
  1215. static void qeth_start_kernel_thread(struct work_struct *work)
  1216. {
  1217. struct task_struct *ts;
  1218. struct qeth_card *card = container_of(work, struct qeth_card,
  1219. kernel_thread_starter);
  1220. QETH_CARD_TEXT(card , 2, "strthrd");
  1221. if (card->read.state != CH_STATE_UP &&
  1222. card->write.state != CH_STATE_UP)
  1223. return;
  1224. if (qeth_do_start_thread(card, QETH_RECOVER_THREAD)) {
  1225. ts = kthread_run(card->discipline->recover, (void *)card,
  1226. "qeth_recover");
  1227. if (IS_ERR(ts)) {
  1228. qeth_clear_thread_start_bit(card, QETH_RECOVER_THREAD);
  1229. qeth_clear_thread_running_bit(card,
  1230. QETH_RECOVER_THREAD);
  1231. }
  1232. }
  1233. }
  1234. static int qeth_setup_card(struct qeth_card *card)
  1235. {
  1236. QETH_DBF_TEXT(SETUP, 2, "setupcrd");
  1237. QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
  1238. card->read.state = CH_STATE_DOWN;
  1239. card->write.state = CH_STATE_DOWN;
  1240. card->data.state = CH_STATE_DOWN;
  1241. card->state = CARD_STATE_DOWN;
  1242. card->lan_online = 0;
  1243. card->read_or_write_problem = 0;
  1244. card->dev = NULL;
  1245. spin_lock_init(&card->vlanlock);
  1246. spin_lock_init(&card->mclock);
  1247. spin_lock_init(&card->lock);
  1248. spin_lock_init(&card->ip_lock);
  1249. spin_lock_init(&card->thread_mask_lock);
  1250. mutex_init(&card->conf_mutex);
  1251. mutex_init(&card->discipline_mutex);
  1252. card->thread_start_mask = 0;
  1253. card->thread_allowed_mask = 0;
  1254. card->thread_running_mask = 0;
  1255. INIT_WORK(&card->kernel_thread_starter, qeth_start_kernel_thread);
  1256. INIT_LIST_HEAD(&card->ip_list);
  1257. INIT_LIST_HEAD(card->ip_tbd_list);
  1258. INIT_LIST_HEAD(&card->cmd_waiter_list);
  1259. init_waitqueue_head(&card->wait_q);
  1260. /* initial options */
  1261. qeth_set_intial_options(card);
  1262. /* IP address takeover */
  1263. INIT_LIST_HEAD(&card->ipato.entries);
  1264. card->ipato.enabled = 0;
  1265. card->ipato.invert4 = 0;
  1266. card->ipato.invert6 = 0;
  1267. /* init QDIO stuff */
  1268. qeth_init_qdio_info(card);
  1269. INIT_DELAYED_WORK(&card->buffer_reclaim_work, qeth_buffer_reclaim_work);
  1270. return 0;
  1271. }
  1272. static void qeth_core_sl_print(struct seq_file *m, struct service_level *slr)
  1273. {
  1274. struct qeth_card *card = container_of(slr, struct qeth_card,
  1275. qeth_service_level);
  1276. if (card->info.mcl_level[0])
  1277. seq_printf(m, "qeth: %s firmware level %s\n",
  1278. CARD_BUS_ID(card), card->info.mcl_level);
  1279. }
  1280. static struct qeth_card *qeth_alloc_card(void)
  1281. {
  1282. struct qeth_card *card;
  1283. QETH_DBF_TEXT(SETUP, 2, "alloccrd");
  1284. card = kzalloc(sizeof(struct qeth_card), GFP_DMA|GFP_KERNEL);
  1285. if (!card)
  1286. goto out;
  1287. QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
  1288. card->ip_tbd_list = kzalloc(sizeof(struct list_head), GFP_KERNEL);
  1289. if (!card->ip_tbd_list) {
  1290. QETH_DBF_TEXT(SETUP, 0, "iptbdnom");
  1291. goto out_card;
  1292. }
  1293. if (qeth_setup_channel(&card->read))
  1294. goto out_ip;
  1295. if (qeth_setup_channel(&card->write))
  1296. goto out_channel;
  1297. card->options.layer2 = -1;
  1298. card->qeth_service_level.seq_print = qeth_core_sl_print;
  1299. register_service_level(&card->qeth_service_level);
  1300. return card;
  1301. out_channel:
  1302. qeth_clean_channel(&card->read);
  1303. out_ip:
  1304. kfree(card->ip_tbd_list);
  1305. out_card:
  1306. kfree(card);
  1307. out:
  1308. return NULL;
  1309. }
  1310. static int qeth_determine_card_type(struct qeth_card *card)
  1311. {
  1312. int i = 0;
  1313. QETH_DBF_TEXT(SETUP, 2, "detcdtyp");
  1314. card->qdio.do_prio_queueing = QETH_PRIOQ_DEFAULT;
  1315. card->qdio.default_out_queue = QETH_DEFAULT_QUEUE;
  1316. while (known_devices[i][QETH_DEV_MODEL_IND]) {
  1317. if ((CARD_RDEV(card)->id.dev_type ==
  1318. known_devices[i][QETH_DEV_TYPE_IND]) &&
  1319. (CARD_RDEV(card)->id.dev_model ==
  1320. known_devices[i][QETH_DEV_MODEL_IND])) {
  1321. card->info.type = known_devices[i][QETH_DEV_MODEL_IND];
  1322. card->qdio.no_out_queues =
  1323. known_devices[i][QETH_QUEUE_NO_IND];
  1324. card->qdio.no_in_queues = 1;
  1325. card->info.is_multicast_different =
  1326. known_devices[i][QETH_MULTICAST_IND];
  1327. qeth_get_channel_path_desc(card);
  1328. return 0;
  1329. }
  1330. i++;
  1331. }
  1332. card->info.type = QETH_CARD_TYPE_UNKNOWN;
  1333. dev_err(&card->gdev->dev, "The adapter hardware is of an "
  1334. "unknown type\n");
  1335. return -ENOENT;
  1336. }
  1337. static int qeth_clear_channel(struct qeth_channel *channel)
  1338. {
  1339. unsigned long flags;
  1340. struct qeth_card *card;
  1341. int rc;
  1342. card = CARD_FROM_CDEV(channel->ccwdev);
  1343. QETH_CARD_TEXT(card, 3, "clearch");
  1344. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1345. rc = ccw_device_clear(channel->ccwdev, QETH_CLEAR_CHANNEL_PARM);
  1346. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1347. if (rc)
  1348. return rc;
  1349. rc = wait_event_interruptible_timeout(card->wait_q,
  1350. channel->state == CH_STATE_STOPPED, QETH_TIMEOUT);
  1351. if (rc == -ERESTARTSYS)
  1352. return rc;
  1353. if (channel->state != CH_STATE_STOPPED)
  1354. return -ETIME;
  1355. channel->state = CH_STATE_DOWN;
  1356. return 0;
  1357. }
  1358. static int qeth_halt_channel(struct qeth_channel *channel)
  1359. {
  1360. unsigned long flags;
  1361. struct qeth_card *card;
  1362. int rc;
  1363. card = CARD_FROM_CDEV(channel->ccwdev);
  1364. QETH_CARD_TEXT(card, 3, "haltch");
  1365. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1366. rc = ccw_device_halt(channel->ccwdev, QETH_HALT_CHANNEL_PARM);
  1367. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1368. if (rc)
  1369. return rc;
  1370. rc = wait_event_interruptible_timeout(card->wait_q,
  1371. channel->state == CH_STATE_HALTED, QETH_TIMEOUT);
  1372. if (rc == -ERESTARTSYS)
  1373. return rc;
  1374. if (channel->state != CH_STATE_HALTED)
  1375. return -ETIME;
  1376. return 0;
  1377. }
  1378. static int qeth_halt_channels(struct qeth_card *card)
  1379. {
  1380. int rc1 = 0, rc2 = 0, rc3 = 0;
  1381. QETH_CARD_TEXT(card, 3, "haltchs");
  1382. rc1 = qeth_halt_channel(&card->read);
  1383. rc2 = qeth_halt_channel(&card->write);
  1384. rc3 = qeth_halt_channel(&card->data);
  1385. if (rc1)
  1386. return rc1;
  1387. if (rc2)
  1388. return rc2;
  1389. return rc3;
  1390. }
  1391. static int qeth_clear_channels(struct qeth_card *card)
  1392. {
  1393. int rc1 = 0, rc2 = 0, rc3 = 0;
  1394. QETH_CARD_TEXT(card, 3, "clearchs");
  1395. rc1 = qeth_clear_channel(&card->read);
  1396. rc2 = qeth_clear_channel(&card->write);
  1397. rc3 = qeth_clear_channel(&card->data);
  1398. if (rc1)
  1399. return rc1;
  1400. if (rc2)
  1401. return rc2;
  1402. return rc3;
  1403. }
  1404. static int qeth_clear_halt_card(struct qeth_card *card, int halt)
  1405. {
  1406. int rc = 0;
  1407. QETH_CARD_TEXT(card, 3, "clhacrd");
  1408. if (halt)
  1409. rc = qeth_halt_channels(card);
  1410. if (rc)
  1411. return rc;
  1412. return qeth_clear_channels(card);
  1413. }
  1414. int qeth_qdio_clear_card(struct qeth_card *card, int use_halt)
  1415. {
  1416. int rc = 0;
  1417. QETH_CARD_TEXT(card, 3, "qdioclr");
  1418. switch (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_ESTABLISHED,
  1419. QETH_QDIO_CLEANING)) {
  1420. case QETH_QDIO_ESTABLISHED:
  1421. if (card->info.type == QETH_CARD_TYPE_IQD)
  1422. rc = qdio_shutdown(CARD_DDEV(card),
  1423. QDIO_FLAG_CLEANUP_USING_HALT);
  1424. else
  1425. rc = qdio_shutdown(CARD_DDEV(card),
  1426. QDIO_FLAG_CLEANUP_USING_CLEAR);
  1427. if (rc)
  1428. QETH_CARD_TEXT_(card, 3, "1err%d", rc);
  1429. qdio_free(CARD_DDEV(card));
  1430. atomic_set(&card->qdio.state, QETH_QDIO_ALLOCATED);
  1431. break;
  1432. case QETH_QDIO_CLEANING:
  1433. return rc;
  1434. default:
  1435. break;
  1436. }
  1437. rc = qeth_clear_halt_card(card, use_halt);
  1438. if (rc)
  1439. QETH_CARD_TEXT_(card, 3, "2err%d", rc);
  1440. card->state = CARD_STATE_DOWN;
  1441. return rc;
  1442. }
  1443. EXPORT_SYMBOL_GPL(qeth_qdio_clear_card);
  1444. static int qeth_read_conf_data(struct qeth_card *card, void **buffer,
  1445. int *length)
  1446. {
  1447. struct ciw *ciw;
  1448. char *rcd_buf;
  1449. int ret;
  1450. struct qeth_channel *channel = &card->data;
  1451. unsigned long flags;
  1452. /*
  1453. * scan for RCD command in extended SenseID data
  1454. */
  1455. ciw = ccw_device_get_ciw(channel->ccwdev, CIW_TYPE_RCD);
  1456. if (!ciw || ciw->cmd == 0)
  1457. return -EOPNOTSUPP;
  1458. rcd_buf = kzalloc(ciw->count, GFP_KERNEL | GFP_DMA);
  1459. if (!rcd_buf)
  1460. return -ENOMEM;
  1461. channel->ccw.cmd_code = ciw->cmd;
  1462. channel->ccw.cda = (__u32) __pa(rcd_buf);
  1463. channel->ccw.count = ciw->count;
  1464. channel->ccw.flags = CCW_FLAG_SLI;
  1465. channel->state = CH_STATE_RCD;
  1466. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1467. ret = ccw_device_start_timeout(channel->ccwdev, &channel->ccw,
  1468. QETH_RCD_PARM, LPM_ANYPATH, 0,
  1469. QETH_RCD_TIMEOUT);
  1470. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1471. if (!ret)
  1472. wait_event(card->wait_q,
  1473. (channel->state == CH_STATE_RCD_DONE ||
  1474. channel->state == CH_STATE_DOWN));
  1475. if (channel->state == CH_STATE_DOWN)
  1476. ret = -EIO;
  1477. else
  1478. channel->state = CH_STATE_DOWN;
  1479. if (ret) {
  1480. kfree(rcd_buf);
  1481. *buffer = NULL;
  1482. *length = 0;
  1483. } else {
  1484. *length = ciw->count;
  1485. *buffer = rcd_buf;
  1486. }
  1487. return ret;
  1488. }
  1489. static void qeth_configure_unitaddr(struct qeth_card *card, char *prcd)
  1490. {
  1491. QETH_DBF_TEXT(SETUP, 2, "cfgunit");
  1492. card->info.chpid = prcd[30];
  1493. card->info.unit_addr2 = prcd[31];
  1494. card->info.cula = prcd[63];
  1495. card->info.guestlan = ((prcd[0x10] == _ascebc['V']) &&
  1496. (prcd[0x11] == _ascebc['M']));
  1497. }
  1498. static void qeth_configure_blkt_default(struct qeth_card *card, char *prcd)
  1499. {
  1500. QETH_DBF_TEXT(SETUP, 2, "cfgblkt");
  1501. if (prcd[74] == 0xF0 && prcd[75] == 0xF0 &&
  1502. (prcd[76] == 0xF5 || prcd[76] == 0xF6)) {
  1503. card->info.blkt.time_total = 250;
  1504. card->info.blkt.inter_packet = 5;
  1505. card->info.blkt.inter_packet_jumbo = 15;
  1506. } else {
  1507. card->info.blkt.time_total = 0;
  1508. card->info.blkt.inter_packet = 0;
  1509. card->info.blkt.inter_packet_jumbo = 0;
  1510. }
  1511. }
  1512. static void qeth_init_tokens(struct qeth_card *card)
  1513. {
  1514. card->token.issuer_rm_w = 0x00010103UL;
  1515. card->token.cm_filter_w = 0x00010108UL;
  1516. card->token.cm_connection_w = 0x0001010aUL;
  1517. card->token.ulp_filter_w = 0x0001010bUL;
  1518. card->token.ulp_connection_w = 0x0001010dUL;
  1519. }
  1520. static void qeth_init_func_level(struct qeth_card *card)
  1521. {
  1522. switch (card->info.type) {
  1523. case QETH_CARD_TYPE_IQD:
  1524. card->info.func_level = QETH_IDX_FUNC_LEVEL_IQD;
  1525. break;
  1526. case QETH_CARD_TYPE_OSD:
  1527. case QETH_CARD_TYPE_OSN:
  1528. card->info.func_level = QETH_IDX_FUNC_LEVEL_OSD;
  1529. break;
  1530. default:
  1531. break;
  1532. }
  1533. }
  1534. static int qeth_idx_activate_get_answer(struct qeth_channel *channel,
  1535. void (*idx_reply_cb)(struct qeth_channel *,
  1536. struct qeth_cmd_buffer *))
  1537. {
  1538. struct qeth_cmd_buffer *iob;
  1539. unsigned long flags;
  1540. int rc;
  1541. struct qeth_card *card;
  1542. QETH_DBF_TEXT(SETUP, 2, "idxanswr");
  1543. card = CARD_FROM_CDEV(channel->ccwdev);
  1544. iob = qeth_get_buffer(channel);
  1545. iob->callback = idx_reply_cb;
  1546. memcpy(&channel->ccw, READ_CCW, sizeof(struct ccw1));
  1547. channel->ccw.count = QETH_BUFSIZE;
  1548. channel->ccw.cda = (__u32) __pa(iob->data);
  1549. wait_event(card->wait_q,
  1550. atomic_cmpxchg(&channel->irq_pending, 0, 1) == 0);
  1551. QETH_DBF_TEXT(SETUP, 6, "noirqpnd");
  1552. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1553. rc = ccw_device_start(channel->ccwdev,
  1554. &channel->ccw, (addr_t) iob, 0, 0);
  1555. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1556. if (rc) {
  1557. QETH_DBF_MESSAGE(2, "Error2 in activating channel rc=%d\n", rc);
  1558. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  1559. atomic_set(&channel->irq_pending, 0);
  1560. wake_up(&card->wait_q);
  1561. return rc;
  1562. }
  1563. rc = wait_event_interruptible_timeout(card->wait_q,
  1564. channel->state == CH_STATE_UP, QETH_TIMEOUT);
  1565. if (rc == -ERESTARTSYS)
  1566. return rc;
  1567. if (channel->state != CH_STATE_UP) {
  1568. rc = -ETIME;
  1569. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  1570. qeth_clear_cmd_buffers(channel);
  1571. } else
  1572. rc = 0;
  1573. return rc;
  1574. }
  1575. static int qeth_idx_activate_channel(struct qeth_channel *channel,
  1576. void (*idx_reply_cb)(struct qeth_channel *,
  1577. struct qeth_cmd_buffer *))
  1578. {
  1579. struct qeth_card *card;
  1580. struct qeth_cmd_buffer *iob;
  1581. unsigned long flags;
  1582. __u16 temp;
  1583. __u8 tmp;
  1584. int rc;
  1585. struct ccw_dev_id temp_devid;
  1586. card = CARD_FROM_CDEV(channel->ccwdev);
  1587. QETH_DBF_TEXT(SETUP, 2, "idxactch");
  1588. iob = qeth_get_buffer(channel);
  1589. iob->callback = idx_reply_cb;
  1590. memcpy(&channel->ccw, WRITE_CCW, sizeof(struct ccw1));
  1591. channel->ccw.count = IDX_ACTIVATE_SIZE;
  1592. channel->ccw.cda = (__u32) __pa(iob->data);
  1593. if (channel == &card->write) {
  1594. memcpy(iob->data, IDX_ACTIVATE_WRITE, IDX_ACTIVATE_SIZE);
  1595. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1596. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1597. card->seqno.trans_hdr++;
  1598. } else {
  1599. memcpy(iob->data, IDX_ACTIVATE_READ, IDX_ACTIVATE_SIZE);
  1600. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1601. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1602. }
  1603. tmp = ((__u8)card->info.portno) | 0x80;
  1604. memcpy(QETH_IDX_ACT_PNO(iob->data), &tmp, 1);
  1605. memcpy(QETH_IDX_ACT_ISSUER_RM_TOKEN(iob->data),
  1606. &card->token.issuer_rm_w, QETH_MPC_TOKEN_LENGTH);
  1607. memcpy(QETH_IDX_ACT_FUNC_LEVEL(iob->data),
  1608. &card->info.func_level, sizeof(__u16));
  1609. ccw_device_get_id(CARD_DDEV(card), &temp_devid);
  1610. memcpy(QETH_IDX_ACT_QDIO_DEV_CUA(iob->data), &temp_devid.devno, 2);
  1611. temp = (card->info.cula << 8) + card->info.unit_addr2;
  1612. memcpy(QETH_IDX_ACT_QDIO_DEV_REALADDR(iob->data), &temp, 2);
  1613. wait_event(card->wait_q,
  1614. atomic_cmpxchg(&channel->irq_pending, 0, 1) == 0);
  1615. QETH_DBF_TEXT(SETUP, 6, "noirqpnd");
  1616. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1617. rc = ccw_device_start(channel->ccwdev,
  1618. &channel->ccw, (addr_t) iob, 0, 0);
  1619. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1620. if (rc) {
  1621. QETH_DBF_MESSAGE(2, "Error1 in activating channel. rc=%d\n",
  1622. rc);
  1623. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  1624. atomic_set(&channel->irq_pending, 0);
  1625. wake_up(&card->wait_q);
  1626. return rc;
  1627. }
  1628. rc = wait_event_interruptible_timeout(card->wait_q,
  1629. channel->state == CH_STATE_ACTIVATING, QETH_TIMEOUT);
  1630. if (rc == -ERESTARTSYS)
  1631. return rc;
  1632. if (channel->state != CH_STATE_ACTIVATING) {
  1633. dev_warn(&channel->ccwdev->dev, "The qeth device driver"
  1634. " failed to recover an error on the device\n");
  1635. QETH_DBF_MESSAGE(2, "%s IDX activate timed out\n",
  1636. dev_name(&channel->ccwdev->dev));
  1637. QETH_DBF_TEXT_(SETUP, 2, "2err%d", -ETIME);
  1638. qeth_clear_cmd_buffers(channel);
  1639. return -ETIME;
  1640. }
  1641. return qeth_idx_activate_get_answer(channel, idx_reply_cb);
  1642. }
  1643. static int qeth_peer_func_level(int level)
  1644. {
  1645. if ((level & 0xff) == 8)
  1646. return (level & 0xff) + 0x400;
  1647. if (((level >> 8) & 3) == 1)
  1648. return (level & 0xff) + 0x200;
  1649. return level;
  1650. }
  1651. static void qeth_idx_write_cb(struct qeth_channel *channel,
  1652. struct qeth_cmd_buffer *iob)
  1653. {
  1654. struct qeth_card *card;
  1655. __u16 temp;
  1656. QETH_DBF_TEXT(SETUP , 2, "idxwrcb");
  1657. if (channel->state == CH_STATE_DOWN) {
  1658. channel->state = CH_STATE_ACTIVATING;
  1659. goto out;
  1660. }
  1661. card = CARD_FROM_CDEV(channel->ccwdev);
  1662. if (!(QETH_IS_IDX_ACT_POS_REPLY(iob->data))) {
  1663. if (QETH_IDX_ACT_CAUSE_CODE(iob->data) == QETH_IDX_ACT_ERR_EXCL)
  1664. dev_err(&card->write.ccwdev->dev,
  1665. "The adapter is used exclusively by another "
  1666. "host\n");
  1667. else
  1668. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on write channel:"
  1669. " negative reply\n",
  1670. dev_name(&card->write.ccwdev->dev));
  1671. goto out;
  1672. }
  1673. memcpy(&temp, QETH_IDX_ACT_FUNC_LEVEL(iob->data), 2);
  1674. if ((temp & ~0x0100) != qeth_peer_func_level(card->info.func_level)) {
  1675. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on write channel: "
  1676. "function level mismatch (sent: 0x%x, received: "
  1677. "0x%x)\n", dev_name(&card->write.ccwdev->dev),
  1678. card->info.func_level, temp);
  1679. goto out;
  1680. }
  1681. channel->state = CH_STATE_UP;
  1682. out:
  1683. qeth_release_buffer(channel, iob);
  1684. }
  1685. static void qeth_idx_read_cb(struct qeth_channel *channel,
  1686. struct qeth_cmd_buffer *iob)
  1687. {
  1688. struct qeth_card *card;
  1689. __u16 temp;
  1690. QETH_DBF_TEXT(SETUP , 2, "idxrdcb");
  1691. if (channel->state == CH_STATE_DOWN) {
  1692. channel->state = CH_STATE_ACTIVATING;
  1693. goto out;
  1694. }
  1695. card = CARD_FROM_CDEV(channel->ccwdev);
  1696. if (qeth_check_idx_response(card, iob->data))
  1697. goto out;
  1698. if (!(QETH_IS_IDX_ACT_POS_REPLY(iob->data))) {
  1699. switch (QETH_IDX_ACT_CAUSE_CODE(iob->data)) {
  1700. case QETH_IDX_ACT_ERR_EXCL:
  1701. dev_err(&card->write.ccwdev->dev,
  1702. "The adapter is used exclusively by another "
  1703. "host\n");
  1704. break;
  1705. case QETH_IDX_ACT_ERR_AUTH:
  1706. case QETH_IDX_ACT_ERR_AUTH_USER:
  1707. dev_err(&card->read.ccwdev->dev,
  1708. "Setting the device online failed because of "
  1709. "insufficient authorization\n");
  1710. break;
  1711. default:
  1712. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on read channel:"
  1713. " negative reply\n",
  1714. dev_name(&card->read.ccwdev->dev));
  1715. }
  1716. QETH_CARD_TEXT_(card, 2, "idxread%c",
  1717. QETH_IDX_ACT_CAUSE_CODE(iob->data));
  1718. goto out;
  1719. }
  1720. /**
  1721. * * temporary fix for microcode bug
  1722. * * to revert it,replace OR by AND
  1723. * */
  1724. if ((!QETH_IDX_NO_PORTNAME_REQUIRED(iob->data)) ||
  1725. (card->info.type == QETH_CARD_TYPE_OSD))
  1726. card->info.portname_required = 1;
  1727. memcpy(&temp, QETH_IDX_ACT_FUNC_LEVEL(iob->data), 2);
  1728. if (temp != qeth_peer_func_level(card->info.func_level)) {
  1729. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on read channel: function "
  1730. "level mismatch (sent: 0x%x, received: 0x%x)\n",
  1731. dev_name(&card->read.ccwdev->dev),
  1732. card->info.func_level, temp);
  1733. goto out;
  1734. }
  1735. memcpy(&card->token.issuer_rm_r,
  1736. QETH_IDX_ACT_ISSUER_RM_TOKEN(iob->data),
  1737. QETH_MPC_TOKEN_LENGTH);
  1738. memcpy(&card->info.mcl_level[0],
  1739. QETH_IDX_REPLY_LEVEL(iob->data), QETH_MCL_LENGTH);
  1740. channel->state = CH_STATE_UP;
  1741. out:
  1742. qeth_release_buffer(channel, iob);
  1743. }
  1744. void qeth_prepare_control_data(struct qeth_card *card, int len,
  1745. struct qeth_cmd_buffer *iob)
  1746. {
  1747. qeth_setup_ccw(&card->write, iob->data, len);
  1748. iob->callback = qeth_release_buffer;
  1749. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1750. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1751. card->seqno.trans_hdr++;
  1752. memcpy(QETH_PDU_HEADER_SEQ_NO(iob->data),
  1753. &card->seqno.pdu_hdr, QETH_SEQ_NO_LENGTH);
  1754. card->seqno.pdu_hdr++;
  1755. memcpy(QETH_PDU_HEADER_ACK_SEQ_NO(iob->data),
  1756. &card->seqno.pdu_hdr_ack, QETH_SEQ_NO_LENGTH);
  1757. QETH_DBF_HEX(CTRL, 2, iob->data, QETH_DBF_CTRL_LEN);
  1758. }
  1759. EXPORT_SYMBOL_GPL(qeth_prepare_control_data);
  1760. int qeth_send_control_data(struct qeth_card *card, int len,
  1761. struct qeth_cmd_buffer *iob,
  1762. int (*reply_cb)(struct qeth_card *, struct qeth_reply *,
  1763. unsigned long),
  1764. void *reply_param)
  1765. {
  1766. int rc;
  1767. unsigned long flags;
  1768. struct qeth_reply *reply = NULL;
  1769. unsigned long timeout, event_timeout;
  1770. struct qeth_ipa_cmd *cmd;
  1771. QETH_CARD_TEXT(card, 2, "sendctl");
  1772. if (card->read_or_write_problem) {
  1773. qeth_release_buffer(iob->channel, iob);
  1774. return -EIO;
  1775. }
  1776. reply = qeth_alloc_reply(card);
  1777. if (!reply) {
  1778. return -ENOMEM;
  1779. }
  1780. reply->callback = reply_cb;
  1781. reply->param = reply_param;
  1782. if (card->state == CARD_STATE_DOWN)
  1783. reply->seqno = QETH_IDX_COMMAND_SEQNO;
  1784. else
  1785. reply->seqno = card->seqno.ipa++;
  1786. init_waitqueue_head(&reply->wait_q);
  1787. spin_lock_irqsave(&card->lock, flags);
  1788. list_add_tail(&reply->list, &card->cmd_waiter_list);
  1789. spin_unlock_irqrestore(&card->lock, flags);
  1790. QETH_DBF_HEX(CTRL, 2, iob->data, QETH_DBF_CTRL_LEN);
  1791. while (atomic_cmpxchg(&card->write.irq_pending, 0, 1)) ;
  1792. qeth_prepare_control_data(card, len, iob);
  1793. if (IS_IPA(iob->data))
  1794. event_timeout = QETH_IPA_TIMEOUT;
  1795. else
  1796. event_timeout = QETH_TIMEOUT;
  1797. timeout = jiffies + event_timeout;
  1798. QETH_CARD_TEXT(card, 6, "noirqpnd");
  1799. spin_lock_irqsave(get_ccwdev_lock(card->write.ccwdev), flags);
  1800. rc = ccw_device_start(card->write.ccwdev, &card->write.ccw,
  1801. (addr_t) iob, 0, 0);
  1802. spin_unlock_irqrestore(get_ccwdev_lock(card->write.ccwdev), flags);
  1803. if (rc) {
  1804. QETH_DBF_MESSAGE(2, "%s qeth_send_control_data: "
  1805. "ccw_device_start rc = %i\n",
  1806. dev_name(&card->write.ccwdev->dev), rc);
  1807. QETH_CARD_TEXT_(card, 2, " err%d", rc);
  1808. spin_lock_irqsave(&card->lock, flags);
  1809. list_del_init(&reply->list);
  1810. qeth_put_reply(reply);
  1811. spin_unlock_irqrestore(&card->lock, flags);
  1812. qeth_release_buffer(iob->channel, iob);
  1813. atomic_set(&card->write.irq_pending, 0);
  1814. wake_up(&card->wait_q);
  1815. return rc;
  1816. }
  1817. /* we have only one long running ipassist, since we can ensure
  1818. process context of this command we can sleep */
  1819. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  1820. if ((cmd->hdr.command == IPA_CMD_SETIP) &&
  1821. (cmd->hdr.prot_version == QETH_PROT_IPV4)) {
  1822. if (!wait_event_timeout(reply->wait_q,
  1823. atomic_read(&reply->received), event_timeout))
  1824. goto time_err;
  1825. } else {
  1826. while (!atomic_read(&reply->received)) {
  1827. if (time_after(jiffies, timeout))
  1828. goto time_err;
  1829. cpu_relax();
  1830. };
  1831. }
  1832. if (reply->rc == -EIO)
  1833. goto error;
  1834. rc = reply->rc;
  1835. qeth_put_reply(reply);
  1836. return rc;
  1837. time_err:
  1838. reply->rc = -ETIME;
  1839. spin_lock_irqsave(&reply->card->lock, flags);
  1840. list_del_init(&reply->list);
  1841. spin_unlock_irqrestore(&reply->card->lock, flags);
  1842. atomic_inc(&reply->received);
  1843. error:
  1844. atomic_set(&card->write.irq_pending, 0);
  1845. qeth_release_buffer(iob->channel, iob);
  1846. card->write.buf_no = (card->write.buf_no + 1) % QETH_CMD_BUFFER_NO;
  1847. rc = reply->rc;
  1848. qeth_put_reply(reply);
  1849. return rc;
  1850. }
  1851. EXPORT_SYMBOL_GPL(qeth_send_control_data);
  1852. static int qeth_cm_enable_cb(struct qeth_card *card, struct qeth_reply *reply,
  1853. unsigned long data)
  1854. {
  1855. struct qeth_cmd_buffer *iob;
  1856. QETH_DBF_TEXT(SETUP, 2, "cmenblcb");
  1857. iob = (struct qeth_cmd_buffer *) data;
  1858. memcpy(&card->token.cm_filter_r,
  1859. QETH_CM_ENABLE_RESP_FILTER_TOKEN(iob->data),
  1860. QETH_MPC_TOKEN_LENGTH);
  1861. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1862. return 0;
  1863. }
  1864. static int qeth_cm_enable(struct qeth_card *card)
  1865. {
  1866. int rc;
  1867. struct qeth_cmd_buffer *iob;
  1868. QETH_DBF_TEXT(SETUP, 2, "cmenable");
  1869. iob = qeth_wait_for_buffer(&card->write);
  1870. memcpy(iob->data, CM_ENABLE, CM_ENABLE_SIZE);
  1871. memcpy(QETH_CM_ENABLE_ISSUER_RM_TOKEN(iob->data),
  1872. &card->token.issuer_rm_r, QETH_MPC_TOKEN_LENGTH);
  1873. memcpy(QETH_CM_ENABLE_FILTER_TOKEN(iob->data),
  1874. &card->token.cm_filter_w, QETH_MPC_TOKEN_LENGTH);
  1875. rc = qeth_send_control_data(card, CM_ENABLE_SIZE, iob,
  1876. qeth_cm_enable_cb, NULL);
  1877. return rc;
  1878. }
  1879. static int qeth_cm_setup_cb(struct qeth_card *card, struct qeth_reply *reply,
  1880. unsigned long data)
  1881. {
  1882. struct qeth_cmd_buffer *iob;
  1883. QETH_DBF_TEXT(SETUP, 2, "cmsetpcb");
  1884. iob = (struct qeth_cmd_buffer *) data;
  1885. memcpy(&card->token.cm_connection_r,
  1886. QETH_CM_SETUP_RESP_DEST_ADDR(iob->data),
  1887. QETH_MPC_TOKEN_LENGTH);
  1888. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1889. return 0;
  1890. }
  1891. static int qeth_cm_setup(struct qeth_card *card)
  1892. {
  1893. int rc;
  1894. struct qeth_cmd_buffer *iob;
  1895. QETH_DBF_TEXT(SETUP, 2, "cmsetup");
  1896. iob = qeth_wait_for_buffer(&card->write);
  1897. memcpy(iob->data, CM_SETUP, CM_SETUP_SIZE);
  1898. memcpy(QETH_CM_SETUP_DEST_ADDR(iob->data),
  1899. &card->token.issuer_rm_r, QETH_MPC_TOKEN_LENGTH);
  1900. memcpy(QETH_CM_SETUP_CONNECTION_TOKEN(iob->data),
  1901. &card->token.cm_connection_w, QETH_MPC_TOKEN_LENGTH);
  1902. memcpy(QETH_CM_SETUP_FILTER_TOKEN(iob->data),
  1903. &card->token.cm_filter_r, QETH_MPC_TOKEN_LENGTH);
  1904. rc = qeth_send_control_data(card, CM_SETUP_SIZE, iob,
  1905. qeth_cm_setup_cb, NULL);
  1906. return rc;
  1907. }
  1908. static inline int qeth_get_initial_mtu_for_card(struct qeth_card *card)
  1909. {
  1910. switch (card->info.type) {
  1911. case QETH_CARD_TYPE_UNKNOWN:
  1912. return 1500;
  1913. case QETH_CARD_TYPE_IQD:
  1914. return card->info.max_mtu;
  1915. case QETH_CARD_TYPE_OSD:
  1916. switch (card->info.link_type) {
  1917. case QETH_LINK_TYPE_HSTR:
  1918. case QETH_LINK_TYPE_LANE_TR:
  1919. return 2000;
  1920. default:
  1921. return 1492;
  1922. }
  1923. case QETH_CARD_TYPE_OSM:
  1924. case QETH_CARD_TYPE_OSX:
  1925. return 1492;
  1926. default:
  1927. return 1500;
  1928. }
  1929. }
  1930. static inline int qeth_get_mtu_outof_framesize(int framesize)
  1931. {
  1932. switch (framesize) {
  1933. case 0x4000:
  1934. return 8192;
  1935. case 0x6000:
  1936. return 16384;
  1937. case 0xa000:
  1938. return 32768;
  1939. case 0xffff:
  1940. return 57344;
  1941. default:
  1942. return 0;
  1943. }
  1944. }
  1945. static inline int qeth_mtu_is_valid(struct qeth_card *card, int mtu)
  1946. {
  1947. switch (card->info.type) {
  1948. case QETH_CARD_TYPE_OSD:
  1949. case QETH_CARD_TYPE_OSM:
  1950. case QETH_CARD_TYPE_OSX:
  1951. case QETH_CARD_TYPE_IQD:
  1952. return ((mtu >= 576) &&
  1953. (mtu <= card->info.max_mtu));
  1954. case QETH_CARD_TYPE_OSN:
  1955. case QETH_CARD_TYPE_UNKNOWN:
  1956. default:
  1957. return 1;
  1958. }
  1959. }
  1960. static int qeth_ulp_enable_cb(struct qeth_card *card, struct qeth_reply *reply,
  1961. unsigned long data)
  1962. {
  1963. __u16 mtu, framesize;
  1964. __u16 len;
  1965. __u8 link_type;
  1966. struct qeth_cmd_buffer *iob;
  1967. QETH_DBF_TEXT(SETUP, 2, "ulpenacb");
  1968. iob = (struct qeth_cmd_buffer *) data;
  1969. memcpy(&card->token.ulp_filter_r,
  1970. QETH_ULP_ENABLE_RESP_FILTER_TOKEN(iob->data),
  1971. QETH_MPC_TOKEN_LENGTH);
  1972. if (card->info.type == QETH_CARD_TYPE_IQD) {
  1973. memcpy(&framesize, QETH_ULP_ENABLE_RESP_MAX_MTU(iob->data), 2);
  1974. mtu = qeth_get_mtu_outof_framesize(framesize);
  1975. if (!mtu) {
  1976. iob->rc = -EINVAL;
  1977. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1978. return 0;
  1979. }
  1980. if (card->info.initial_mtu && (card->info.initial_mtu != mtu)) {
  1981. /* frame size has changed */
  1982. if (card->dev &&
  1983. ((card->dev->mtu == card->info.initial_mtu) ||
  1984. (card->dev->mtu > mtu)))
  1985. card->dev->mtu = mtu;
  1986. qeth_free_qdio_buffers(card);
  1987. }
  1988. card->info.initial_mtu = mtu;
  1989. card->info.max_mtu = mtu;
  1990. card->qdio.in_buf_size = mtu + 2 * PAGE_SIZE;
  1991. } else {
  1992. card->info.initial_mtu = qeth_get_initial_mtu_for_card(card);
  1993. card->info.max_mtu = *(__u16 *)QETH_ULP_ENABLE_RESP_MAX_MTU(
  1994. iob->data);
  1995. card->qdio.in_buf_size = QETH_IN_BUF_SIZE_DEFAULT;
  1996. }
  1997. memcpy(&len, QETH_ULP_ENABLE_RESP_DIFINFO_LEN(iob->data), 2);
  1998. if (len >= QETH_MPC_DIFINFO_LEN_INDICATES_LINK_TYPE) {
  1999. memcpy(&link_type,
  2000. QETH_ULP_ENABLE_RESP_LINK_TYPE(iob->data), 1);
  2001. card->info.link_type = link_type;
  2002. } else
  2003. card->info.link_type = 0;
  2004. QETH_DBF_TEXT_(SETUP, 2, "link%d", card->info.link_type);
  2005. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  2006. return 0;
  2007. }
  2008. static int qeth_ulp_enable(struct qeth_card *card)
  2009. {
  2010. int rc;
  2011. char prot_type;
  2012. struct qeth_cmd_buffer *iob;
  2013. /*FIXME: trace view callbacks*/
  2014. QETH_DBF_TEXT(SETUP, 2, "ulpenabl");
  2015. iob = qeth_wait_for_buffer(&card->write);
  2016. memcpy(iob->data, ULP_ENABLE, ULP_ENABLE_SIZE);
  2017. *(QETH_ULP_ENABLE_LINKNUM(iob->data)) =
  2018. (__u8) card->info.portno;
  2019. if (card->options.layer2)
  2020. if (card->info.type == QETH_CARD_TYPE_OSN)
  2021. prot_type = QETH_PROT_OSN2;
  2022. else
  2023. prot_type = QETH_PROT_LAYER2;
  2024. else
  2025. prot_type = QETH_PROT_TCPIP;
  2026. memcpy(QETH_ULP_ENABLE_PROT_TYPE(iob->data), &prot_type, 1);
  2027. memcpy(QETH_ULP_ENABLE_DEST_ADDR(iob->data),
  2028. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  2029. memcpy(QETH_ULP_ENABLE_FILTER_TOKEN(iob->data),
  2030. &card->token.ulp_filter_w, QETH_MPC_TOKEN_LENGTH);
  2031. memcpy(QETH_ULP_ENABLE_PORTNAME_AND_LL(iob->data),
  2032. card->info.portname, 9);
  2033. rc = qeth_send_control_data(card, ULP_ENABLE_SIZE, iob,
  2034. qeth_ulp_enable_cb, NULL);
  2035. return rc;
  2036. }
  2037. static int qeth_ulp_setup_cb(struct qeth_card *card, struct qeth_reply *reply,
  2038. unsigned long data)
  2039. {
  2040. struct qeth_cmd_buffer *iob;
  2041. int rc = 0;
  2042. QETH_DBF_TEXT(SETUP, 2, "ulpstpcb");
  2043. iob = (struct qeth_cmd_buffer *) data;
  2044. memcpy(&card->token.ulp_connection_r,
  2045. QETH_ULP_SETUP_RESP_CONNECTION_TOKEN(iob->data),
  2046. QETH_MPC_TOKEN_LENGTH);
  2047. if (!strncmp("00S", QETH_ULP_SETUP_RESP_CONNECTION_TOKEN(iob->data),
  2048. 3)) {
  2049. QETH_DBF_TEXT(SETUP, 2, "olmlimit");
  2050. dev_err(&card->gdev->dev, "A connection could not be "
  2051. "established because of an OLM limit\n");
  2052. iob->rc = -EMLINK;
  2053. }
  2054. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  2055. return rc;
  2056. }
  2057. static int qeth_ulp_setup(struct qeth_card *card)
  2058. {
  2059. int rc;
  2060. __u16 temp;
  2061. struct qeth_cmd_buffer *iob;
  2062. struct ccw_dev_id dev_id;
  2063. QETH_DBF_TEXT(SETUP, 2, "ulpsetup");
  2064. iob = qeth_wait_for_buffer(&card->write);
  2065. memcpy(iob->data, ULP_SETUP, ULP_SETUP_SIZE);
  2066. memcpy(QETH_ULP_SETUP_DEST_ADDR(iob->data),
  2067. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  2068. memcpy(QETH_ULP_SETUP_CONNECTION_TOKEN(iob->data),
  2069. &card->token.ulp_connection_w, QETH_MPC_TOKEN_LENGTH);
  2070. memcpy(QETH_ULP_SETUP_FILTER_TOKEN(iob->data),
  2071. &card->token.ulp_filter_r, QETH_MPC_TOKEN_LENGTH);
  2072. ccw_device_get_id(CARD_DDEV(card), &dev_id);
  2073. memcpy(QETH_ULP_SETUP_CUA(iob->data), &dev_id.devno, 2);
  2074. temp = (card->info.cula << 8) + card->info.unit_addr2;
  2075. memcpy(QETH_ULP_SETUP_REAL_DEVADDR(iob->data), &temp, 2);
  2076. rc = qeth_send_control_data(card, ULP_SETUP_SIZE, iob,
  2077. qeth_ulp_setup_cb, NULL);
  2078. return rc;
  2079. }
  2080. static int qeth_init_qdio_out_buf(struct qeth_qdio_out_q *q, int bidx)
  2081. {
  2082. int rc;
  2083. struct qeth_qdio_out_buffer *newbuf;
  2084. rc = 0;
  2085. newbuf = kmem_cache_zalloc(qeth_qdio_outbuf_cache, GFP_ATOMIC);
  2086. if (!newbuf) {
  2087. rc = -ENOMEM;
  2088. goto out;
  2089. }
  2090. newbuf->buffer = &q->qdio_bufs[bidx];
  2091. skb_queue_head_init(&newbuf->skb_list);
  2092. lockdep_set_class(&newbuf->skb_list.lock, &qdio_out_skb_queue_key);
  2093. newbuf->q = q;
  2094. newbuf->aob = NULL;
  2095. newbuf->next_pending = q->bufs[bidx];
  2096. atomic_set(&newbuf->state, QETH_QDIO_BUF_EMPTY);
  2097. q->bufs[bidx] = newbuf;
  2098. if (q->bufstates) {
  2099. q->bufstates[bidx].user = newbuf;
  2100. QETH_CARD_TEXT_(q->card, 2, "nbs%d", bidx);
  2101. QETH_CARD_TEXT_(q->card, 2, "%lx", (long) newbuf);
  2102. QETH_CARD_TEXT_(q->card, 2, "%lx",
  2103. (long) newbuf->next_pending);
  2104. }
  2105. out:
  2106. return rc;
  2107. }
  2108. static int qeth_alloc_qdio_buffers(struct qeth_card *card)
  2109. {
  2110. int i, j;
  2111. QETH_DBF_TEXT(SETUP, 2, "allcqdbf");
  2112. if (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_UNINITIALIZED,
  2113. QETH_QDIO_ALLOCATED) != QETH_QDIO_UNINITIALIZED)
  2114. return 0;
  2115. card->qdio.in_q = kzalloc(sizeof(struct qeth_qdio_q),
  2116. GFP_KERNEL);
  2117. if (!card->qdio.in_q)
  2118. goto out_nomem;
  2119. QETH_DBF_TEXT(SETUP, 2, "inq");
  2120. QETH_DBF_HEX(SETUP, 2, &card->qdio.in_q, sizeof(void *));
  2121. memset(card->qdio.in_q, 0, sizeof(struct qeth_qdio_q));
  2122. /* give inbound qeth_qdio_buffers their qdio_buffers */
  2123. for (i = 0; i < QDIO_MAX_BUFFERS_PER_Q; ++i) {
  2124. card->qdio.in_q->bufs[i].buffer =
  2125. &card->qdio.in_q->qdio_bufs[i];
  2126. card->qdio.in_q->bufs[i].rx_skb = NULL;
  2127. }
  2128. /* inbound buffer pool */
  2129. if (qeth_alloc_buffer_pool(card))
  2130. goto out_freeinq;
  2131. /* outbound */
  2132. card->qdio.out_qs =
  2133. kzalloc(card->qdio.no_out_queues *
  2134. sizeof(struct qeth_qdio_out_q *), GFP_KERNEL);
  2135. if (!card->qdio.out_qs)
  2136. goto out_freepool;
  2137. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  2138. card->qdio.out_qs[i] = kzalloc(sizeof(struct qeth_qdio_out_q),
  2139. GFP_KERNEL);
  2140. if (!card->qdio.out_qs[i])
  2141. goto out_freeoutq;
  2142. QETH_DBF_TEXT_(SETUP, 2, "outq %i", i);
  2143. QETH_DBF_HEX(SETUP, 2, &card->qdio.out_qs[i], sizeof(void *));
  2144. card->qdio.out_qs[i]->queue_no = i;
  2145. /* give outbound qeth_qdio_buffers their qdio_buffers */
  2146. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j) {
  2147. BUG_ON(card->qdio.out_qs[i]->bufs[j] != NULL);
  2148. if (qeth_init_qdio_out_buf(card->qdio.out_qs[i], j))
  2149. goto out_freeoutqbufs;
  2150. }
  2151. }
  2152. /* completion */
  2153. if (qeth_alloc_cq(card))
  2154. goto out_freeoutq;
  2155. return 0;
  2156. out_freeoutqbufs:
  2157. while (j > 0) {
  2158. --j;
  2159. kmem_cache_free(qeth_qdio_outbuf_cache,
  2160. card->qdio.out_qs[i]->bufs[j]);
  2161. card->qdio.out_qs[i]->bufs[j] = NULL;
  2162. }
  2163. out_freeoutq:
  2164. while (i > 0) {
  2165. kfree(card->qdio.out_qs[--i]);
  2166. qeth_clear_outq_buffers(card->qdio.out_qs[i], 1);
  2167. }
  2168. kfree(card->qdio.out_qs);
  2169. card->qdio.out_qs = NULL;
  2170. out_freepool:
  2171. qeth_free_buffer_pool(card);
  2172. out_freeinq:
  2173. kfree(card->qdio.in_q);
  2174. card->qdio.in_q = NULL;
  2175. out_nomem:
  2176. atomic_set(&card->qdio.state, QETH_QDIO_UNINITIALIZED);
  2177. return -ENOMEM;
  2178. }
  2179. static void qeth_create_qib_param_field(struct qeth_card *card,
  2180. char *param_field)
  2181. {
  2182. param_field[0] = _ascebc['P'];
  2183. param_field[1] = _ascebc['C'];
  2184. param_field[2] = _ascebc['I'];
  2185. param_field[3] = _ascebc['T'];
  2186. *((unsigned int *) (&param_field[4])) = QETH_PCI_THRESHOLD_A(card);
  2187. *((unsigned int *) (&param_field[8])) = QETH_PCI_THRESHOLD_B(card);
  2188. *((unsigned int *) (&param_field[12])) = QETH_PCI_TIMER_VALUE(card);
  2189. }
  2190. static void qeth_create_qib_param_field_blkt(struct qeth_card *card,
  2191. char *param_field)
  2192. {
  2193. param_field[16] = _ascebc['B'];
  2194. param_field[17] = _ascebc['L'];
  2195. param_field[18] = _ascebc['K'];
  2196. param_field[19] = _ascebc['T'];
  2197. *((unsigned int *) (&param_field[20])) = card->info.blkt.time_total;
  2198. *((unsigned int *) (&param_field[24])) = card->info.blkt.inter_packet;
  2199. *((unsigned int *) (&param_field[28])) =
  2200. card->info.blkt.inter_packet_jumbo;
  2201. }
  2202. static int qeth_qdio_activate(struct qeth_card *card)
  2203. {
  2204. QETH_DBF_TEXT(SETUP, 3, "qdioact");
  2205. return qdio_activate(CARD_DDEV(card));
  2206. }
  2207. static int qeth_dm_act(struct qeth_card *card)
  2208. {
  2209. int rc;
  2210. struct qeth_cmd_buffer *iob;
  2211. QETH_DBF_TEXT(SETUP, 2, "dmact");
  2212. iob = qeth_wait_for_buffer(&card->write);
  2213. memcpy(iob->data, DM_ACT, DM_ACT_SIZE);
  2214. memcpy(QETH_DM_ACT_DEST_ADDR(iob->data),
  2215. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  2216. memcpy(QETH_DM_ACT_CONNECTION_TOKEN(iob->data),
  2217. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  2218. rc = qeth_send_control_data(card, DM_ACT_SIZE, iob, NULL, NULL);
  2219. return rc;
  2220. }
  2221. static int qeth_mpc_initialize(struct qeth_card *card)
  2222. {
  2223. int rc;
  2224. QETH_DBF_TEXT(SETUP, 2, "mpcinit");
  2225. rc = qeth_issue_next_read(card);
  2226. if (rc) {
  2227. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  2228. return rc;
  2229. }
  2230. rc = qeth_cm_enable(card);
  2231. if (rc) {
  2232. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  2233. goto out_qdio;
  2234. }
  2235. rc = qeth_cm_setup(card);
  2236. if (rc) {
  2237. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  2238. goto out_qdio;
  2239. }
  2240. rc = qeth_ulp_enable(card);
  2241. if (rc) {
  2242. QETH_DBF_TEXT_(SETUP, 2, "4err%d", rc);
  2243. goto out_qdio;
  2244. }
  2245. rc = qeth_ulp_setup(card);
  2246. if (rc) {
  2247. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  2248. goto out_qdio;
  2249. }
  2250. rc = qeth_alloc_qdio_buffers(card);
  2251. if (rc) {
  2252. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  2253. goto out_qdio;
  2254. }
  2255. rc = qeth_qdio_establish(card);
  2256. if (rc) {
  2257. QETH_DBF_TEXT_(SETUP, 2, "6err%d", rc);
  2258. qeth_free_qdio_buffers(card);
  2259. goto out_qdio;
  2260. }
  2261. rc = qeth_qdio_activate(card);
  2262. if (rc) {
  2263. QETH_DBF_TEXT_(SETUP, 2, "7err%d", rc);
  2264. goto out_qdio;
  2265. }
  2266. rc = qeth_dm_act(card);
  2267. if (rc) {
  2268. QETH_DBF_TEXT_(SETUP, 2, "8err%d", rc);
  2269. goto out_qdio;
  2270. }
  2271. return 0;
  2272. out_qdio:
  2273. qeth_qdio_clear_card(card, card->info.type != QETH_CARD_TYPE_IQD);
  2274. return rc;
  2275. }
  2276. static void qeth_print_status_with_portname(struct qeth_card *card)
  2277. {
  2278. char dbf_text[15];
  2279. int i;
  2280. sprintf(dbf_text, "%s", card->info.portname + 1);
  2281. for (i = 0; i < 8; i++)
  2282. dbf_text[i] =
  2283. (char) _ebcasc[(__u8) dbf_text[i]];
  2284. dbf_text[8] = 0;
  2285. dev_info(&card->gdev->dev, "Device is a%s card%s%s%s\n"
  2286. "with link type %s (portname: %s)\n",
  2287. qeth_get_cardname(card),
  2288. (card->info.mcl_level[0]) ? " (level: " : "",
  2289. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  2290. (card->info.mcl_level[0]) ? ")" : "",
  2291. qeth_get_cardname_short(card),
  2292. dbf_text);
  2293. }
  2294. static void qeth_print_status_no_portname(struct qeth_card *card)
  2295. {
  2296. if (card->info.portname[0])
  2297. dev_info(&card->gdev->dev, "Device is a%s "
  2298. "card%s%s%s\nwith link type %s "
  2299. "(no portname needed by interface).\n",
  2300. qeth_get_cardname(card),
  2301. (card->info.mcl_level[0]) ? " (level: " : "",
  2302. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  2303. (card->info.mcl_level[0]) ? ")" : "",
  2304. qeth_get_cardname_short(card));
  2305. else
  2306. dev_info(&card->gdev->dev, "Device is a%s "
  2307. "card%s%s%s\nwith link type %s.\n",
  2308. qeth_get_cardname(card),
  2309. (card->info.mcl_level[0]) ? " (level: " : "",
  2310. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  2311. (card->info.mcl_level[0]) ? ")" : "",
  2312. qeth_get_cardname_short(card));
  2313. }
  2314. void qeth_print_status_message(struct qeth_card *card)
  2315. {
  2316. switch (card->info.type) {
  2317. case QETH_CARD_TYPE_OSD:
  2318. case QETH_CARD_TYPE_OSM:
  2319. case QETH_CARD_TYPE_OSX:
  2320. /* VM will use a non-zero first character
  2321. * to indicate a HiperSockets like reporting
  2322. * of the level OSA sets the first character to zero
  2323. * */
  2324. if (!card->info.mcl_level[0]) {
  2325. sprintf(card->info.mcl_level, "%02x%02x",
  2326. card->info.mcl_level[2],
  2327. card->info.mcl_level[3]);
  2328. card->info.mcl_level[QETH_MCL_LENGTH] = 0;
  2329. break;
  2330. }
  2331. /* fallthrough */
  2332. case QETH_CARD_TYPE_IQD:
  2333. if ((card->info.guestlan) ||
  2334. (card->info.mcl_level[0] & 0x80)) {
  2335. card->info.mcl_level[0] = (char) _ebcasc[(__u8)
  2336. card->info.mcl_level[0]];
  2337. card->info.mcl_level[1] = (char) _ebcasc[(__u8)
  2338. card->info.mcl_level[1]];
  2339. card->info.mcl_level[2] = (char) _ebcasc[(__u8)
  2340. card->info.mcl_level[2]];
  2341. card->info.mcl_level[3] = (char) _ebcasc[(__u8)
  2342. card->info.mcl_level[3]];
  2343. card->info.mcl_level[QETH_MCL_LENGTH] = 0;
  2344. }
  2345. break;
  2346. default:
  2347. memset(&card->info.mcl_level[0], 0, QETH_MCL_LENGTH + 1);
  2348. }
  2349. if (card->info.portname_required)
  2350. qeth_print_status_with_portname(card);
  2351. else
  2352. qeth_print_status_no_portname(card);
  2353. }
  2354. EXPORT_SYMBOL_GPL(qeth_print_status_message);
  2355. static void qeth_initialize_working_pool_list(struct qeth_card *card)
  2356. {
  2357. struct qeth_buffer_pool_entry *entry;
  2358. QETH_CARD_TEXT(card, 5, "inwrklst");
  2359. list_for_each_entry(entry,
  2360. &card->qdio.init_pool.entry_list, init_list) {
  2361. qeth_put_buffer_pool_entry(card, entry);
  2362. }
  2363. }
  2364. static inline struct qeth_buffer_pool_entry *qeth_find_free_buffer_pool_entry(
  2365. struct qeth_card *card)
  2366. {
  2367. struct list_head *plh;
  2368. struct qeth_buffer_pool_entry *entry;
  2369. int i, free;
  2370. struct page *page;
  2371. if (list_empty(&card->qdio.in_buf_pool.entry_list))
  2372. return NULL;
  2373. list_for_each(plh, &card->qdio.in_buf_pool.entry_list) {
  2374. entry = list_entry(plh, struct qeth_buffer_pool_entry, list);
  2375. free = 1;
  2376. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2377. if (page_count(virt_to_page(entry->elements[i])) > 1) {
  2378. free = 0;
  2379. break;
  2380. }
  2381. }
  2382. if (free) {
  2383. list_del_init(&entry->list);
  2384. return entry;
  2385. }
  2386. }
  2387. /* no free buffer in pool so take first one and swap pages */
  2388. entry = list_entry(card->qdio.in_buf_pool.entry_list.next,
  2389. struct qeth_buffer_pool_entry, list);
  2390. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2391. if (page_count(virt_to_page(entry->elements[i])) > 1) {
  2392. page = alloc_page(GFP_ATOMIC);
  2393. if (!page) {
  2394. return NULL;
  2395. } else {
  2396. free_page((unsigned long)entry->elements[i]);
  2397. entry->elements[i] = page_address(page);
  2398. if (card->options.performance_stats)
  2399. card->perf_stats.sg_alloc_page_rx++;
  2400. }
  2401. }
  2402. }
  2403. list_del_init(&entry->list);
  2404. return entry;
  2405. }
  2406. static int qeth_init_input_buffer(struct qeth_card *card,
  2407. struct qeth_qdio_buffer *buf)
  2408. {
  2409. struct qeth_buffer_pool_entry *pool_entry;
  2410. int i;
  2411. if ((card->options.cq == QETH_CQ_ENABLED) && (!buf->rx_skb)) {
  2412. buf->rx_skb = dev_alloc_skb(QETH_RX_PULL_LEN + ETH_HLEN);
  2413. if (!buf->rx_skb)
  2414. return 1;
  2415. }
  2416. pool_entry = qeth_find_free_buffer_pool_entry(card);
  2417. if (!pool_entry)
  2418. return 1;
  2419. /*
  2420. * since the buffer is accessed only from the input_tasklet
  2421. * there shouldn't be a need to synchronize; also, since we use
  2422. * the QETH_IN_BUF_REQUEUE_THRESHOLD we should never run out off
  2423. * buffers
  2424. */
  2425. buf->pool_entry = pool_entry;
  2426. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2427. buf->buffer->element[i].length = PAGE_SIZE;
  2428. buf->buffer->element[i].addr = pool_entry->elements[i];
  2429. if (i == QETH_MAX_BUFFER_ELEMENTS(card) - 1)
  2430. buf->buffer->element[i].eflags = SBAL_EFLAGS_LAST_ENTRY;
  2431. else
  2432. buf->buffer->element[i].eflags = 0;
  2433. buf->buffer->element[i].sflags = 0;
  2434. }
  2435. return 0;
  2436. }
  2437. int qeth_init_qdio_queues(struct qeth_card *card)
  2438. {
  2439. int i, j;
  2440. int rc;
  2441. QETH_DBF_TEXT(SETUP, 2, "initqdqs");
  2442. /* inbound queue */
  2443. memset(card->qdio.in_q->qdio_bufs, 0,
  2444. QDIO_MAX_BUFFERS_PER_Q * sizeof(struct qdio_buffer));
  2445. qeth_initialize_working_pool_list(card);
  2446. /*give only as many buffers to hardware as we have buffer pool entries*/
  2447. for (i = 0; i < card->qdio.in_buf_pool.buf_count - 1; ++i)
  2448. qeth_init_input_buffer(card, &card->qdio.in_q->bufs[i]);
  2449. card->qdio.in_q->next_buf_to_init =
  2450. card->qdio.in_buf_pool.buf_count - 1;
  2451. rc = do_QDIO(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT, 0, 0,
  2452. card->qdio.in_buf_pool.buf_count - 1);
  2453. if (rc) {
  2454. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  2455. return rc;
  2456. }
  2457. /* completion */
  2458. rc = qeth_cq_init(card);
  2459. if (rc) {
  2460. return rc;
  2461. }
  2462. /* outbound queue */
  2463. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  2464. memset(card->qdio.out_qs[i]->qdio_bufs, 0,
  2465. QDIO_MAX_BUFFERS_PER_Q * sizeof(struct qdio_buffer));
  2466. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j) {
  2467. qeth_clear_output_buffer(card->qdio.out_qs[i],
  2468. card->qdio.out_qs[i]->bufs[j],
  2469. QETH_QDIO_BUF_EMPTY);
  2470. }
  2471. card->qdio.out_qs[i]->card = card;
  2472. card->qdio.out_qs[i]->next_buf_to_fill = 0;
  2473. card->qdio.out_qs[i]->do_pack = 0;
  2474. atomic_set(&card->qdio.out_qs[i]->used_buffers, 0);
  2475. atomic_set(&card->qdio.out_qs[i]->set_pci_flags_count, 0);
  2476. atomic_set(&card->qdio.out_qs[i]->state,
  2477. QETH_OUT_Q_UNLOCKED);
  2478. }
  2479. return 0;
  2480. }
  2481. EXPORT_SYMBOL_GPL(qeth_init_qdio_queues);
  2482. static inline __u8 qeth_get_ipa_adp_type(enum qeth_link_types link_type)
  2483. {
  2484. switch (link_type) {
  2485. case QETH_LINK_TYPE_HSTR:
  2486. return 2;
  2487. default:
  2488. return 1;
  2489. }
  2490. }
  2491. static void qeth_fill_ipacmd_header(struct qeth_card *card,
  2492. struct qeth_ipa_cmd *cmd, __u8 command,
  2493. enum qeth_prot_versions prot)
  2494. {
  2495. memset(cmd, 0, sizeof(struct qeth_ipa_cmd));
  2496. cmd->hdr.command = command;
  2497. cmd->hdr.initiator = IPA_CMD_INITIATOR_HOST;
  2498. cmd->hdr.seqno = card->seqno.ipa;
  2499. cmd->hdr.adapter_type = qeth_get_ipa_adp_type(card->info.link_type);
  2500. cmd->hdr.rel_adapter_no = (__u8) card->info.portno;
  2501. if (card->options.layer2)
  2502. cmd->hdr.prim_version_no = 2;
  2503. else
  2504. cmd->hdr.prim_version_no = 1;
  2505. cmd->hdr.param_count = 1;
  2506. cmd->hdr.prot_version = prot;
  2507. cmd->hdr.ipa_supported = 0;
  2508. cmd->hdr.ipa_enabled = 0;
  2509. }
  2510. struct qeth_cmd_buffer *qeth_get_ipacmd_buffer(struct qeth_card *card,
  2511. enum qeth_ipa_cmds ipacmd, enum qeth_prot_versions prot)
  2512. {
  2513. struct qeth_cmd_buffer *iob;
  2514. struct qeth_ipa_cmd *cmd;
  2515. iob = qeth_wait_for_buffer(&card->write);
  2516. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  2517. qeth_fill_ipacmd_header(card, cmd, ipacmd, prot);
  2518. return iob;
  2519. }
  2520. EXPORT_SYMBOL_GPL(qeth_get_ipacmd_buffer);
  2521. void qeth_prepare_ipa_cmd(struct qeth_card *card, struct qeth_cmd_buffer *iob,
  2522. char prot_type)
  2523. {
  2524. memcpy(iob->data, IPA_PDU_HEADER, IPA_PDU_HEADER_SIZE);
  2525. memcpy(QETH_IPA_CMD_PROT_TYPE(iob->data), &prot_type, 1);
  2526. memcpy(QETH_IPA_CMD_DEST_ADDR(iob->data),
  2527. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  2528. }
  2529. EXPORT_SYMBOL_GPL(qeth_prepare_ipa_cmd);
  2530. int qeth_send_ipa_cmd(struct qeth_card *card, struct qeth_cmd_buffer *iob,
  2531. int (*reply_cb)(struct qeth_card *, struct qeth_reply*,
  2532. unsigned long),
  2533. void *reply_param)
  2534. {
  2535. int rc;
  2536. char prot_type;
  2537. QETH_CARD_TEXT(card, 4, "sendipa");
  2538. if (card->options.layer2)
  2539. if (card->info.type == QETH_CARD_TYPE_OSN)
  2540. prot_type = QETH_PROT_OSN2;
  2541. else
  2542. prot_type = QETH_PROT_LAYER2;
  2543. else
  2544. prot_type = QETH_PROT_TCPIP;
  2545. qeth_prepare_ipa_cmd(card, iob, prot_type);
  2546. rc = qeth_send_control_data(card, IPA_CMD_LENGTH,
  2547. iob, reply_cb, reply_param);
  2548. if (rc == -ETIME) {
  2549. qeth_clear_ipacmd_list(card);
  2550. qeth_schedule_recovery(card);
  2551. }
  2552. return rc;
  2553. }
  2554. EXPORT_SYMBOL_GPL(qeth_send_ipa_cmd);
  2555. int qeth_send_startlan(struct qeth_card *card)
  2556. {
  2557. int rc;
  2558. struct qeth_cmd_buffer *iob;
  2559. QETH_DBF_TEXT(SETUP, 2, "strtlan");
  2560. iob = qeth_get_ipacmd_buffer(card, IPA_CMD_STARTLAN, 0);
  2561. rc = qeth_send_ipa_cmd(card, iob, NULL, NULL);
  2562. return rc;
  2563. }
  2564. EXPORT_SYMBOL_GPL(qeth_send_startlan);
  2565. int qeth_default_setadapterparms_cb(struct qeth_card *card,
  2566. struct qeth_reply *reply, unsigned long data)
  2567. {
  2568. struct qeth_ipa_cmd *cmd;
  2569. QETH_CARD_TEXT(card, 4, "defadpcb");
  2570. cmd = (struct qeth_ipa_cmd *) data;
  2571. if (cmd->hdr.return_code == 0)
  2572. cmd->hdr.return_code =
  2573. cmd->data.setadapterparms.hdr.return_code;
  2574. return 0;
  2575. }
  2576. EXPORT_SYMBOL_GPL(qeth_default_setadapterparms_cb);
  2577. static int qeth_query_setadapterparms_cb(struct qeth_card *card,
  2578. struct qeth_reply *reply, unsigned long data)
  2579. {
  2580. struct qeth_ipa_cmd *cmd;
  2581. QETH_CARD_TEXT(card, 3, "quyadpcb");
  2582. cmd = (struct qeth_ipa_cmd *) data;
  2583. if (cmd->data.setadapterparms.data.query_cmds_supp.lan_type & 0x7f) {
  2584. card->info.link_type =
  2585. cmd->data.setadapterparms.data.query_cmds_supp.lan_type;
  2586. QETH_DBF_TEXT_(SETUP, 2, "lnk %d", card->info.link_type);
  2587. }
  2588. card->options.adp.supported_funcs =
  2589. cmd->data.setadapterparms.data.query_cmds_supp.supported_cmds;
  2590. return qeth_default_setadapterparms_cb(card, reply, (unsigned long)cmd);
  2591. }
  2592. struct qeth_cmd_buffer *qeth_get_adapter_cmd(struct qeth_card *card,
  2593. __u32 command, __u32 cmdlen)
  2594. {
  2595. struct qeth_cmd_buffer *iob;
  2596. struct qeth_ipa_cmd *cmd;
  2597. iob = qeth_get_ipacmd_buffer(card, IPA_CMD_SETADAPTERPARMS,
  2598. QETH_PROT_IPV4);
  2599. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  2600. cmd->data.setadapterparms.hdr.cmdlength = cmdlen;
  2601. cmd->data.setadapterparms.hdr.command_code = command;
  2602. cmd->data.setadapterparms.hdr.used_total = 1;
  2603. cmd->data.setadapterparms.hdr.seq_no = 1;
  2604. return iob;
  2605. }
  2606. EXPORT_SYMBOL_GPL(qeth_get_adapter_cmd);
  2607. int qeth_query_setadapterparms(struct qeth_card *card)
  2608. {
  2609. int rc;
  2610. struct qeth_cmd_buffer *iob;
  2611. QETH_CARD_TEXT(card, 3, "queryadp");
  2612. iob = qeth_get_adapter_cmd(card, IPA_SETADP_QUERY_COMMANDS_SUPPORTED,
  2613. sizeof(struct qeth_ipacmd_setadpparms));
  2614. rc = qeth_send_ipa_cmd(card, iob, qeth_query_setadapterparms_cb, NULL);
  2615. return rc;
  2616. }
  2617. EXPORT_SYMBOL_GPL(qeth_query_setadapterparms);
  2618. static int qeth_query_ipassists_cb(struct qeth_card *card,
  2619. struct qeth_reply *reply, unsigned long data)
  2620. {
  2621. struct qeth_ipa_cmd *cmd;
  2622. QETH_DBF_TEXT(SETUP, 2, "qipasscb");
  2623. cmd = (struct qeth_ipa_cmd *) data;
  2624. if (cmd->hdr.prot_version == QETH_PROT_IPV4) {
  2625. card->options.ipa4.supported_funcs = cmd->hdr.ipa_supported;
  2626. card->options.ipa4.enabled_funcs = cmd->hdr.ipa_enabled;
  2627. } else {
  2628. card->options.ipa6.supported_funcs = cmd->hdr.ipa_supported;
  2629. card->options.ipa6.enabled_funcs = cmd->hdr.ipa_enabled;
  2630. }
  2631. QETH_DBF_TEXT(SETUP, 2, "suppenbl");
  2632. QETH_DBF_TEXT_(SETUP, 2, "%08x", (__u32)cmd->hdr.ipa_supported);
  2633. QETH_DBF_TEXT_(SETUP, 2, "%08x", (__u32)cmd->hdr.ipa_enabled);
  2634. return 0;
  2635. }
  2636. int qeth_query_ipassists(struct qeth_card *card, enum qeth_prot_versions prot)
  2637. {
  2638. int rc;
  2639. struct qeth_cmd_buffer *iob;
  2640. QETH_DBF_TEXT_(SETUP, 2, "qipassi%i", prot);
  2641. iob = qeth_get_ipacmd_buffer(card, IPA_CMD_QIPASSIST, prot);
  2642. rc = qeth_send_ipa_cmd(card, iob, qeth_query_ipassists_cb, NULL);
  2643. return rc;
  2644. }
  2645. EXPORT_SYMBOL_GPL(qeth_query_ipassists);
  2646. static int qeth_query_setdiagass_cb(struct qeth_card *card,
  2647. struct qeth_reply *reply, unsigned long data)
  2648. {
  2649. struct qeth_ipa_cmd *cmd;
  2650. __u16 rc;
  2651. cmd = (struct qeth_ipa_cmd *)data;
  2652. rc = cmd->hdr.return_code;
  2653. if (rc)
  2654. QETH_CARD_TEXT_(card, 2, "diagq:%x", rc);
  2655. else
  2656. card->info.diagass_support = cmd->data.diagass.ext;
  2657. return 0;
  2658. }
  2659. static int qeth_query_setdiagass(struct qeth_card *card)
  2660. {
  2661. struct qeth_cmd_buffer *iob;
  2662. struct qeth_ipa_cmd *cmd;
  2663. QETH_DBF_TEXT(SETUP, 2, "qdiagass");
  2664. iob = qeth_get_ipacmd_buffer(card, IPA_CMD_SET_DIAG_ASS, 0);
  2665. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  2666. cmd->data.diagass.subcmd_len = 16;
  2667. cmd->data.diagass.subcmd = QETH_DIAGS_CMD_QUERY;
  2668. return qeth_send_ipa_cmd(card, iob, qeth_query_setdiagass_cb, NULL);
  2669. }
  2670. static void qeth_get_trap_id(struct qeth_card *card, struct qeth_trap_id *tid)
  2671. {
  2672. unsigned long info = get_zeroed_page(GFP_KERNEL);
  2673. struct sysinfo_2_2_2 *info222 = (struct sysinfo_2_2_2 *)info;
  2674. struct sysinfo_3_2_2 *info322 = (struct sysinfo_3_2_2 *)info;
  2675. struct ccw_dev_id ccwid;
  2676. int level, rc;
  2677. tid->chpid = card->info.chpid;
  2678. ccw_device_get_id(CARD_RDEV(card), &ccwid);
  2679. tid->ssid = ccwid.ssid;
  2680. tid->devno = ccwid.devno;
  2681. if (!info)
  2682. return;
  2683. rc = stsi(NULL, 0, 0, 0);
  2684. if (rc == -ENOSYS)
  2685. level = rc;
  2686. else
  2687. level = (((unsigned int) rc) >> 28);
  2688. if ((level >= 2) && (stsi(info222, 2, 2, 2) != -ENOSYS))
  2689. tid->lparnr = info222->lpar_number;
  2690. if ((level >= 3) && (stsi(info322, 3, 2, 2) != -ENOSYS)) {
  2691. EBCASC(info322->vm[0].name, sizeof(info322->vm[0].name));
  2692. memcpy(tid->vmname, info322->vm[0].name, sizeof(tid->vmname));
  2693. }
  2694. free_page(info);
  2695. return;
  2696. }
  2697. static int qeth_hw_trap_cb(struct qeth_card *card,
  2698. struct qeth_reply *reply, unsigned long data)
  2699. {
  2700. struct qeth_ipa_cmd *cmd;
  2701. __u16 rc;
  2702. cmd = (struct qeth_ipa_cmd *)data;
  2703. rc = cmd->hdr.return_code;
  2704. if (rc)
  2705. QETH_CARD_TEXT_(card, 2, "trapc:%x", rc);
  2706. return 0;
  2707. }
  2708. int qeth_hw_trap(struct qeth_card *card, enum qeth_diags_trap_action action)
  2709. {
  2710. struct qeth_cmd_buffer *iob;
  2711. struct qeth_ipa_cmd *cmd;
  2712. QETH_DBF_TEXT(SETUP, 2, "diagtrap");
  2713. iob = qeth_get_ipacmd_buffer(card, IPA_CMD_SET_DIAG_ASS, 0);
  2714. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  2715. cmd->data.diagass.subcmd_len = 80;
  2716. cmd->data.diagass.subcmd = QETH_DIAGS_CMD_TRAP;
  2717. cmd->data.diagass.type = 1;
  2718. cmd->data.diagass.action = action;
  2719. switch (action) {
  2720. case QETH_DIAGS_TRAP_ARM:
  2721. cmd->data.diagass.options = 0x0003;
  2722. cmd->data.diagass.ext = 0x00010000 +
  2723. sizeof(struct qeth_trap_id);
  2724. qeth_get_trap_id(card,
  2725. (struct qeth_trap_id *)cmd->data.diagass.cdata);
  2726. break;
  2727. case QETH_DIAGS_TRAP_DISARM:
  2728. cmd->data.diagass.options = 0x0001;
  2729. break;
  2730. case QETH_DIAGS_TRAP_CAPTURE:
  2731. break;
  2732. }
  2733. return qeth_send_ipa_cmd(card, iob, qeth_hw_trap_cb, NULL);
  2734. }
  2735. EXPORT_SYMBOL_GPL(qeth_hw_trap);
  2736. int qeth_check_qdio_errors(struct qeth_card *card, struct qdio_buffer *buf,
  2737. unsigned int qdio_error, const char *dbftext)
  2738. {
  2739. if (qdio_error) {
  2740. QETH_CARD_TEXT(card, 2, dbftext);
  2741. QETH_CARD_TEXT_(card, 2, " F15=%02X",
  2742. buf->element[15].sflags);
  2743. QETH_CARD_TEXT_(card, 2, " F14=%02X",
  2744. buf->element[14].sflags);
  2745. QETH_CARD_TEXT_(card, 2, " qerr=%X", qdio_error);
  2746. if ((buf->element[15].sflags) == 0x12) {
  2747. card->stats.rx_dropped++;
  2748. return 0;
  2749. } else
  2750. return 1;
  2751. }
  2752. return 0;
  2753. }
  2754. EXPORT_SYMBOL_GPL(qeth_check_qdio_errors);
  2755. void qeth_buffer_reclaim_work(struct work_struct *work)
  2756. {
  2757. struct qeth_card *card = container_of(work, struct qeth_card,
  2758. buffer_reclaim_work.work);
  2759. QETH_CARD_TEXT_(card, 2, "brw:%x", card->reclaim_index);
  2760. qeth_queue_input_buffer(card, card->reclaim_index);
  2761. }
  2762. void qeth_queue_input_buffer(struct qeth_card *card, int index)
  2763. {
  2764. struct qeth_qdio_q *queue = card->qdio.in_q;
  2765. struct list_head *lh;
  2766. int count;
  2767. int i;
  2768. int rc;
  2769. int newcount = 0;
  2770. count = (index < queue->next_buf_to_init)?
  2771. card->qdio.in_buf_pool.buf_count -
  2772. (queue->next_buf_to_init - index) :
  2773. card->qdio.in_buf_pool.buf_count -
  2774. (queue->next_buf_to_init + QDIO_MAX_BUFFERS_PER_Q - index);
  2775. /* only requeue at a certain threshold to avoid SIGAs */
  2776. if (count >= QETH_IN_BUF_REQUEUE_THRESHOLD(card)) {
  2777. for (i = queue->next_buf_to_init;
  2778. i < queue->next_buf_to_init + count; ++i) {
  2779. if (qeth_init_input_buffer(card,
  2780. &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q])) {
  2781. break;
  2782. } else {
  2783. newcount++;
  2784. }
  2785. }
  2786. if (newcount < count) {
  2787. /* we are in memory shortage so we switch back to
  2788. traditional skb allocation and drop packages */
  2789. atomic_set(&card->force_alloc_skb, 3);
  2790. count = newcount;
  2791. } else {
  2792. atomic_add_unless(&card->force_alloc_skb, -1, 0);
  2793. }
  2794. if (!count) {
  2795. i = 0;
  2796. list_for_each(lh, &card->qdio.in_buf_pool.entry_list)
  2797. i++;
  2798. if (i == card->qdio.in_buf_pool.buf_count) {
  2799. QETH_CARD_TEXT(card, 2, "qsarbw");
  2800. card->reclaim_index = index;
  2801. schedule_delayed_work(
  2802. &card->buffer_reclaim_work,
  2803. QETH_RECLAIM_WORK_TIME);
  2804. }
  2805. return;
  2806. }
  2807. /*
  2808. * according to old code it should be avoided to requeue all
  2809. * 128 buffers in order to benefit from PCI avoidance.
  2810. * this function keeps at least one buffer (the buffer at
  2811. * 'index') un-requeued -> this buffer is the first buffer that
  2812. * will be requeued the next time
  2813. */
  2814. if (card->options.performance_stats) {
  2815. card->perf_stats.inbound_do_qdio_cnt++;
  2816. card->perf_stats.inbound_do_qdio_start_time =
  2817. qeth_get_micros();
  2818. }
  2819. rc = do_QDIO(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT, 0,
  2820. queue->next_buf_to_init, count);
  2821. if (card->options.performance_stats)
  2822. card->perf_stats.inbound_do_qdio_time +=
  2823. qeth_get_micros() -
  2824. card->perf_stats.inbound_do_qdio_start_time;
  2825. if (rc) {
  2826. QETH_CARD_TEXT(card, 2, "qinberr");
  2827. }
  2828. queue->next_buf_to_init = (queue->next_buf_to_init + count) %
  2829. QDIO_MAX_BUFFERS_PER_Q;
  2830. }
  2831. }
  2832. EXPORT_SYMBOL_GPL(qeth_queue_input_buffer);
  2833. static int qeth_handle_send_error(struct qeth_card *card,
  2834. struct qeth_qdio_out_buffer *buffer, unsigned int qdio_err)
  2835. {
  2836. int sbalf15 = buffer->buffer->element[15].sflags;
  2837. QETH_CARD_TEXT(card, 6, "hdsnderr");
  2838. if (card->info.type == QETH_CARD_TYPE_IQD) {
  2839. if (sbalf15 == 0) {
  2840. qdio_err = 0;
  2841. } else {
  2842. qdio_err = 1;
  2843. }
  2844. }
  2845. qeth_check_qdio_errors(card, buffer->buffer, qdio_err, "qouterr");
  2846. if (!qdio_err)
  2847. return QETH_SEND_ERROR_NONE;
  2848. if ((sbalf15 >= 15) && (sbalf15 <= 31))
  2849. return QETH_SEND_ERROR_RETRY;
  2850. QETH_CARD_TEXT(card, 1, "lnkfail");
  2851. QETH_CARD_TEXT_(card, 1, "%04x %02x",
  2852. (u16)qdio_err, (u8)sbalf15);
  2853. return QETH_SEND_ERROR_LINK_FAILURE;
  2854. }
  2855. /*
  2856. * Switched to packing state if the number of used buffers on a queue
  2857. * reaches a certain limit.
  2858. */
  2859. static void qeth_switch_to_packing_if_needed(struct qeth_qdio_out_q *queue)
  2860. {
  2861. if (!queue->do_pack) {
  2862. if (atomic_read(&queue->used_buffers)
  2863. >= QETH_HIGH_WATERMARK_PACK){
  2864. /* switch non-PACKING -> PACKING */
  2865. QETH_CARD_TEXT(queue->card, 6, "np->pack");
  2866. if (queue->card->options.performance_stats)
  2867. queue->card->perf_stats.sc_dp_p++;
  2868. queue->do_pack = 1;
  2869. }
  2870. }
  2871. }
  2872. /*
  2873. * Switches from packing to non-packing mode. If there is a packing
  2874. * buffer on the queue this buffer will be prepared to be flushed.
  2875. * In that case 1 is returned to inform the caller. If no buffer
  2876. * has to be flushed, zero is returned.
  2877. */
  2878. static int qeth_switch_to_nonpacking_if_needed(struct qeth_qdio_out_q *queue)
  2879. {
  2880. struct qeth_qdio_out_buffer *buffer;
  2881. int flush_count = 0;
  2882. if (queue->do_pack) {
  2883. if (atomic_read(&queue->used_buffers)
  2884. <= QETH_LOW_WATERMARK_PACK) {
  2885. /* switch PACKING -> non-PACKING */
  2886. QETH_CARD_TEXT(queue->card, 6, "pack->np");
  2887. if (queue->card->options.performance_stats)
  2888. queue->card->perf_stats.sc_p_dp++;
  2889. queue->do_pack = 0;
  2890. /* flush packing buffers */
  2891. buffer = queue->bufs[queue->next_buf_to_fill];
  2892. if ((atomic_read(&buffer->state) ==
  2893. QETH_QDIO_BUF_EMPTY) &&
  2894. (buffer->next_element_to_fill > 0)) {
  2895. atomic_set(&buffer->state,
  2896. QETH_QDIO_BUF_PRIMED);
  2897. flush_count++;
  2898. queue->next_buf_to_fill =
  2899. (queue->next_buf_to_fill + 1) %
  2900. QDIO_MAX_BUFFERS_PER_Q;
  2901. }
  2902. }
  2903. }
  2904. return flush_count;
  2905. }
  2906. /*
  2907. * Called to flush a packing buffer if no more pci flags are on the queue.
  2908. * Checks if there is a packing buffer and prepares it to be flushed.
  2909. * In that case returns 1, otherwise zero.
  2910. */
  2911. static int qeth_flush_buffers_on_no_pci(struct qeth_qdio_out_q *queue)
  2912. {
  2913. struct qeth_qdio_out_buffer *buffer;
  2914. buffer = queue->bufs[queue->next_buf_to_fill];
  2915. if ((atomic_read(&buffer->state) == QETH_QDIO_BUF_EMPTY) &&
  2916. (buffer->next_element_to_fill > 0)) {
  2917. /* it's a packing buffer */
  2918. atomic_set(&buffer->state, QETH_QDIO_BUF_PRIMED);
  2919. queue->next_buf_to_fill =
  2920. (queue->next_buf_to_fill + 1) % QDIO_MAX_BUFFERS_PER_Q;
  2921. return 1;
  2922. }
  2923. return 0;
  2924. }
  2925. static void qeth_flush_buffers(struct qeth_qdio_out_q *queue, int index,
  2926. int count)
  2927. {
  2928. struct qeth_qdio_out_buffer *buf;
  2929. int rc;
  2930. int i;
  2931. unsigned int qdio_flags;
  2932. for (i = index; i < index + count; ++i) {
  2933. int bidx = i % QDIO_MAX_BUFFERS_PER_Q;
  2934. buf = queue->bufs[bidx];
  2935. buf->buffer->element[buf->next_element_to_fill - 1].eflags |=
  2936. SBAL_EFLAGS_LAST_ENTRY;
  2937. if (queue->bufstates)
  2938. queue->bufstates[bidx].user = buf;
  2939. if (queue->card->info.type == QETH_CARD_TYPE_IQD)
  2940. continue;
  2941. if (!queue->do_pack) {
  2942. if ((atomic_read(&queue->used_buffers) >=
  2943. (QETH_HIGH_WATERMARK_PACK -
  2944. QETH_WATERMARK_PACK_FUZZ)) &&
  2945. !atomic_read(&queue->set_pci_flags_count)) {
  2946. /* it's likely that we'll go to packing
  2947. * mode soon */
  2948. atomic_inc(&queue->set_pci_flags_count);
  2949. buf->buffer->element[0].sflags |= SBAL_SFLAGS0_PCI_REQ;
  2950. }
  2951. } else {
  2952. if (!atomic_read(&queue->set_pci_flags_count)) {
  2953. /*
  2954. * there's no outstanding PCI any more, so we
  2955. * have to request a PCI to be sure the the PCI
  2956. * will wake at some time in the future then we
  2957. * can flush packed buffers that might still be
  2958. * hanging around, which can happen if no
  2959. * further send was requested by the stack
  2960. */
  2961. atomic_inc(&queue->set_pci_flags_count);
  2962. buf->buffer->element[0].sflags |= SBAL_SFLAGS0_PCI_REQ;
  2963. }
  2964. }
  2965. }
  2966. queue->card->dev->trans_start = jiffies;
  2967. if (queue->card->options.performance_stats) {
  2968. queue->card->perf_stats.outbound_do_qdio_cnt++;
  2969. queue->card->perf_stats.outbound_do_qdio_start_time =
  2970. qeth_get_micros();
  2971. }
  2972. qdio_flags = QDIO_FLAG_SYNC_OUTPUT;
  2973. if (atomic_read(&queue->set_pci_flags_count))
  2974. qdio_flags |= QDIO_FLAG_PCI_OUT;
  2975. rc = do_QDIO(CARD_DDEV(queue->card), qdio_flags,
  2976. queue->queue_no, index, count);
  2977. if (queue->card->options.performance_stats)
  2978. queue->card->perf_stats.outbound_do_qdio_time +=
  2979. qeth_get_micros() -
  2980. queue->card->perf_stats.outbound_do_qdio_start_time;
  2981. atomic_add(count, &queue->used_buffers);
  2982. if (rc) {
  2983. queue->card->stats.tx_errors += count;
  2984. /* ignore temporary SIGA errors without busy condition */
  2985. if (rc == -ENOBUFS)
  2986. return;
  2987. QETH_CARD_TEXT(queue->card, 2, "flushbuf");
  2988. QETH_CARD_TEXT_(queue->card, 2, " q%d", queue->queue_no);
  2989. QETH_CARD_TEXT_(queue->card, 2, " idx%d", index);
  2990. QETH_CARD_TEXT_(queue->card, 2, " c%d", count);
  2991. QETH_CARD_TEXT_(queue->card, 2, " err%d", rc);
  2992. /* this must not happen under normal circumstances. if it
  2993. * happens something is really wrong -> recover */
  2994. qeth_schedule_recovery(queue->card);
  2995. return;
  2996. }
  2997. if (queue->card->options.performance_stats)
  2998. queue->card->perf_stats.bufs_sent += count;
  2999. }
  3000. static void qeth_check_outbound_queue(struct qeth_qdio_out_q *queue)
  3001. {
  3002. int index;
  3003. int flush_cnt = 0;
  3004. int q_was_packing = 0;
  3005. /*
  3006. * check if weed have to switch to non-packing mode or if
  3007. * we have to get a pci flag out on the queue
  3008. */
  3009. if ((atomic_read(&queue->used_buffers) <= QETH_LOW_WATERMARK_PACK) ||
  3010. !atomic_read(&queue->set_pci_flags_count)) {
  3011. if (atomic_xchg(&queue->state, QETH_OUT_Q_LOCKED_FLUSH) ==
  3012. QETH_OUT_Q_UNLOCKED) {
  3013. /*
  3014. * If we get in here, there was no action in
  3015. * do_send_packet. So, we check if there is a
  3016. * packing buffer to be flushed here.
  3017. */
  3018. netif_stop_queue(queue->card->dev);
  3019. index = queue->next_buf_to_fill;
  3020. q_was_packing = queue->do_pack;
  3021. /* queue->do_pack may change */
  3022. barrier();
  3023. flush_cnt += qeth_switch_to_nonpacking_if_needed(queue);
  3024. if (!flush_cnt &&
  3025. !atomic_read(&queue->set_pci_flags_count))
  3026. flush_cnt +=
  3027. qeth_flush_buffers_on_no_pci(queue);
  3028. if (queue->card->options.performance_stats &&
  3029. q_was_packing)
  3030. queue->card->perf_stats.bufs_sent_pack +=
  3031. flush_cnt;
  3032. if (flush_cnt)
  3033. qeth_flush_buffers(queue, index, flush_cnt);
  3034. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  3035. }
  3036. }
  3037. }
  3038. void qeth_qdio_start_poll(struct ccw_device *ccwdev, int queue,
  3039. unsigned long card_ptr)
  3040. {
  3041. struct qeth_card *card = (struct qeth_card *)card_ptr;
  3042. if (card->dev && (card->dev->flags & IFF_UP))
  3043. napi_schedule(&card->napi);
  3044. }
  3045. EXPORT_SYMBOL_GPL(qeth_qdio_start_poll);
  3046. int qeth_configure_cq(struct qeth_card *card, enum qeth_cq cq)
  3047. {
  3048. int rc;
  3049. if (card->options.cq == QETH_CQ_NOTAVAILABLE) {
  3050. rc = -1;
  3051. goto out;
  3052. } else {
  3053. if (card->options.cq == cq) {
  3054. rc = 0;
  3055. goto out;
  3056. }
  3057. if (card->state != CARD_STATE_DOWN &&
  3058. card->state != CARD_STATE_RECOVER) {
  3059. rc = -1;
  3060. goto out;
  3061. }
  3062. qeth_free_qdio_buffers(card);
  3063. card->options.cq = cq;
  3064. rc = 0;
  3065. }
  3066. out:
  3067. return rc;
  3068. }
  3069. EXPORT_SYMBOL_GPL(qeth_configure_cq);
  3070. static void qeth_qdio_cq_handler(struct qeth_card *card,
  3071. unsigned int qdio_err,
  3072. unsigned int queue, int first_element, int count) {
  3073. struct qeth_qdio_q *cq = card->qdio.c_q;
  3074. int i;
  3075. int rc;
  3076. if (!qeth_is_cq(card, queue))
  3077. goto out;
  3078. QETH_CARD_TEXT_(card, 5, "qcqhe%d", first_element);
  3079. QETH_CARD_TEXT_(card, 5, "qcqhc%d", count);
  3080. QETH_CARD_TEXT_(card, 5, "qcqherr%d", qdio_err);
  3081. if (qdio_err) {
  3082. netif_stop_queue(card->dev);
  3083. qeth_schedule_recovery(card);
  3084. goto out;
  3085. }
  3086. if (card->options.performance_stats) {
  3087. card->perf_stats.cq_cnt++;
  3088. card->perf_stats.cq_start_time = qeth_get_micros();
  3089. }
  3090. for (i = first_element; i < first_element + count; ++i) {
  3091. int bidx = i % QDIO_MAX_BUFFERS_PER_Q;
  3092. struct qdio_buffer *buffer = &cq->qdio_bufs[bidx];
  3093. int e;
  3094. e = 0;
  3095. while (buffer->element[e].addr) {
  3096. unsigned long phys_aob_addr;
  3097. phys_aob_addr = (unsigned long) buffer->element[e].addr;
  3098. qeth_qdio_handle_aob(card, phys_aob_addr);
  3099. buffer->element[e].addr = NULL;
  3100. buffer->element[e].eflags = 0;
  3101. buffer->element[e].sflags = 0;
  3102. buffer->element[e].length = 0;
  3103. ++e;
  3104. }
  3105. buffer->element[15].eflags = 0;
  3106. buffer->element[15].sflags = 0;
  3107. }
  3108. rc = do_QDIO(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT, queue,
  3109. card->qdio.c_q->next_buf_to_init,
  3110. count);
  3111. if (rc) {
  3112. dev_warn(&card->gdev->dev,
  3113. "QDIO reported an error, rc=%i\n", rc);
  3114. QETH_CARD_TEXT(card, 2, "qcqherr");
  3115. }
  3116. card->qdio.c_q->next_buf_to_init = (card->qdio.c_q->next_buf_to_init
  3117. + count) % QDIO_MAX_BUFFERS_PER_Q;
  3118. netif_wake_queue(card->dev);
  3119. if (card->options.performance_stats) {
  3120. int delta_t = qeth_get_micros();
  3121. delta_t -= card->perf_stats.cq_start_time;
  3122. card->perf_stats.cq_time += delta_t;
  3123. }
  3124. out:
  3125. return;
  3126. }
  3127. void qeth_qdio_input_handler(struct ccw_device *ccwdev, unsigned int qdio_err,
  3128. unsigned int queue, int first_elem, int count,
  3129. unsigned long card_ptr)
  3130. {
  3131. struct qeth_card *card = (struct qeth_card *)card_ptr;
  3132. QETH_CARD_TEXT_(card, 2, "qihq%d", queue);
  3133. QETH_CARD_TEXT_(card, 2, "qiec%d", qdio_err);
  3134. if (qeth_is_cq(card, queue))
  3135. qeth_qdio_cq_handler(card, qdio_err, queue, first_elem, count);
  3136. else if (qdio_err)
  3137. qeth_schedule_recovery(card);
  3138. }
  3139. EXPORT_SYMBOL_GPL(qeth_qdio_input_handler);
  3140. void qeth_qdio_output_handler(struct ccw_device *ccwdev,
  3141. unsigned int qdio_error, int __queue, int first_element,
  3142. int count, unsigned long card_ptr)
  3143. {
  3144. struct qeth_card *card = (struct qeth_card *) card_ptr;
  3145. struct qeth_qdio_out_q *queue = card->qdio.out_qs[__queue];
  3146. struct qeth_qdio_out_buffer *buffer;
  3147. int i;
  3148. QETH_CARD_TEXT(card, 6, "qdouhdl");
  3149. if (qdio_error & QDIO_ERROR_FATAL) {
  3150. QETH_CARD_TEXT(card, 2, "achkcond");
  3151. netif_stop_queue(card->dev);
  3152. qeth_schedule_recovery(card);
  3153. return;
  3154. }
  3155. if (card->options.performance_stats) {
  3156. card->perf_stats.outbound_handler_cnt++;
  3157. card->perf_stats.outbound_handler_start_time =
  3158. qeth_get_micros();
  3159. }
  3160. for (i = first_element; i < (first_element + count); ++i) {
  3161. int bidx = i % QDIO_MAX_BUFFERS_PER_Q;
  3162. buffer = queue->bufs[bidx];
  3163. qeth_handle_send_error(card, buffer, qdio_error);
  3164. if (queue->bufstates &&
  3165. (queue->bufstates[bidx].flags &
  3166. QDIO_OUTBUF_STATE_FLAG_PENDING) != 0) {
  3167. BUG_ON(card->options.cq != QETH_CQ_ENABLED);
  3168. if (atomic_cmpxchg(&buffer->state,
  3169. QETH_QDIO_BUF_PRIMED,
  3170. QETH_QDIO_BUF_PENDING) ==
  3171. QETH_QDIO_BUF_PRIMED) {
  3172. qeth_notify_skbs(queue, buffer,
  3173. TX_NOTIFY_PENDING);
  3174. }
  3175. buffer->aob = queue->bufstates[bidx].aob;
  3176. QETH_CARD_TEXT_(queue->card, 5, "pel%d", bidx);
  3177. QETH_CARD_TEXT(queue->card, 5, "aob");
  3178. QETH_CARD_TEXT_(queue->card, 5, "%lx",
  3179. virt_to_phys(buffer->aob));
  3180. BUG_ON(bidx < 0 || bidx >= QDIO_MAX_BUFFERS_PER_Q);
  3181. if (qeth_init_qdio_out_buf(queue, bidx)) {
  3182. QETH_CARD_TEXT(card, 2, "outofbuf");
  3183. qeth_schedule_recovery(card);
  3184. }
  3185. } else {
  3186. if (card->options.cq == QETH_CQ_ENABLED) {
  3187. enum iucv_tx_notify n;
  3188. n = qeth_compute_cq_notification(
  3189. buffer->buffer->element[15].sflags, 0);
  3190. qeth_notify_skbs(queue, buffer, n);
  3191. }
  3192. qeth_clear_output_buffer(queue, buffer,
  3193. QETH_QDIO_BUF_EMPTY);
  3194. }
  3195. qeth_cleanup_handled_pending(queue, bidx, 0);
  3196. }
  3197. atomic_sub(count, &queue->used_buffers);
  3198. /* check if we need to do something on this outbound queue */
  3199. if (card->info.type != QETH_CARD_TYPE_IQD)
  3200. qeth_check_outbound_queue(queue);
  3201. netif_wake_queue(queue->card->dev);
  3202. if (card->options.performance_stats)
  3203. card->perf_stats.outbound_handler_time += qeth_get_micros() -
  3204. card->perf_stats.outbound_handler_start_time;
  3205. }
  3206. EXPORT_SYMBOL_GPL(qeth_qdio_output_handler);
  3207. int qeth_get_priority_queue(struct qeth_card *card, struct sk_buff *skb,
  3208. int ipv, int cast_type)
  3209. {
  3210. if (!ipv && (card->info.type == QETH_CARD_TYPE_OSD ||
  3211. card->info.type == QETH_CARD_TYPE_OSX))
  3212. return card->qdio.default_out_queue;
  3213. switch (card->qdio.no_out_queues) {
  3214. case 4:
  3215. if (cast_type && card->info.is_multicast_different)
  3216. return card->info.is_multicast_different &
  3217. (card->qdio.no_out_queues - 1);
  3218. if (card->qdio.do_prio_queueing && (ipv == 4)) {
  3219. const u8 tos = ip_hdr(skb)->tos;
  3220. if (card->qdio.do_prio_queueing ==
  3221. QETH_PRIO_Q_ING_TOS) {
  3222. if (tos & IP_TOS_NOTIMPORTANT)
  3223. return 3;
  3224. if (tos & IP_TOS_HIGHRELIABILITY)
  3225. return 2;
  3226. if (tos & IP_TOS_HIGHTHROUGHPUT)
  3227. return 1;
  3228. if (tos & IP_TOS_LOWDELAY)
  3229. return 0;
  3230. }
  3231. if (card->qdio.do_prio_queueing ==
  3232. QETH_PRIO_Q_ING_PREC)
  3233. return 3 - (tos >> 6);
  3234. } else if (card->qdio.do_prio_queueing && (ipv == 6)) {
  3235. /* TODO: IPv6!!! */
  3236. }
  3237. return card->qdio.default_out_queue;
  3238. case 1: /* fallthrough for single-out-queue 1920-device */
  3239. default:
  3240. return card->qdio.default_out_queue;
  3241. }
  3242. }
  3243. EXPORT_SYMBOL_GPL(qeth_get_priority_queue);
  3244. int qeth_get_elements_no(struct qeth_card *card, void *hdr,
  3245. struct sk_buff *skb, int elems)
  3246. {
  3247. int dlen = skb->len - skb->data_len;
  3248. int elements_needed = PFN_UP((unsigned long)skb->data + dlen - 1) -
  3249. PFN_DOWN((unsigned long)skb->data);
  3250. elements_needed += skb_shinfo(skb)->nr_frags;
  3251. if ((elements_needed + elems) > QETH_MAX_BUFFER_ELEMENTS(card)) {
  3252. QETH_DBF_MESSAGE(2, "Invalid size of IP packet "
  3253. "(Number=%d / Length=%d). Discarded.\n",
  3254. (elements_needed+elems), skb->len);
  3255. return 0;
  3256. }
  3257. return elements_needed;
  3258. }
  3259. EXPORT_SYMBOL_GPL(qeth_get_elements_no);
  3260. int qeth_hdr_chk_and_bounce(struct sk_buff *skb, int len)
  3261. {
  3262. int hroom, inpage, rest;
  3263. if (((unsigned long)skb->data & PAGE_MASK) !=
  3264. (((unsigned long)skb->data + len - 1) & PAGE_MASK)) {
  3265. hroom = skb_headroom(skb);
  3266. inpage = PAGE_SIZE - ((unsigned long) skb->data % PAGE_SIZE);
  3267. rest = len - inpage;
  3268. if (rest > hroom)
  3269. return 1;
  3270. memmove(skb->data - rest, skb->data, skb->len - skb->data_len);
  3271. skb->data -= rest;
  3272. QETH_DBF_MESSAGE(2, "skb bounce len: %d rest: %d\n", len, rest);
  3273. }
  3274. return 0;
  3275. }
  3276. EXPORT_SYMBOL_GPL(qeth_hdr_chk_and_bounce);
  3277. static inline void __qeth_fill_buffer(struct sk_buff *skb,
  3278. struct qdio_buffer *buffer, int is_tso, int *next_element_to_fill,
  3279. int offset)
  3280. {
  3281. int length = skb->len - skb->data_len;
  3282. int length_here;
  3283. int element;
  3284. char *data;
  3285. int first_lap, cnt;
  3286. struct skb_frag_struct *frag;
  3287. element = *next_element_to_fill;
  3288. data = skb->data;
  3289. first_lap = (is_tso == 0 ? 1 : 0);
  3290. if (offset >= 0) {
  3291. data = skb->data + offset;
  3292. length -= offset;
  3293. first_lap = 0;
  3294. }
  3295. while (length > 0) {
  3296. /* length_here is the remaining amount of data in this page */
  3297. length_here = PAGE_SIZE - ((unsigned long) data % PAGE_SIZE);
  3298. if (length < length_here)
  3299. length_here = length;
  3300. buffer->element[element].addr = data;
  3301. buffer->element[element].length = length_here;
  3302. length -= length_here;
  3303. if (!length) {
  3304. if (first_lap)
  3305. if (skb_shinfo(skb)->nr_frags)
  3306. buffer->element[element].eflags =
  3307. SBAL_EFLAGS_FIRST_FRAG;
  3308. else
  3309. buffer->element[element].eflags = 0;
  3310. else
  3311. buffer->element[element].eflags =
  3312. SBAL_EFLAGS_MIDDLE_FRAG;
  3313. } else {
  3314. if (first_lap)
  3315. buffer->element[element].eflags =
  3316. SBAL_EFLAGS_FIRST_FRAG;
  3317. else
  3318. buffer->element[element].eflags =
  3319. SBAL_EFLAGS_MIDDLE_FRAG;
  3320. }
  3321. data += length_here;
  3322. element++;
  3323. first_lap = 0;
  3324. }
  3325. for (cnt = 0; cnt < skb_shinfo(skb)->nr_frags; cnt++) {
  3326. frag = &skb_shinfo(skb)->frags[cnt];
  3327. buffer->element[element].addr = (char *)
  3328. page_to_phys(skb_frag_page(frag))
  3329. + frag->page_offset;
  3330. buffer->element[element].length = frag->size;
  3331. buffer->element[element].eflags = SBAL_EFLAGS_MIDDLE_FRAG;
  3332. element++;
  3333. }
  3334. if (buffer->element[element - 1].eflags)
  3335. buffer->element[element - 1].eflags = SBAL_EFLAGS_LAST_FRAG;
  3336. *next_element_to_fill = element;
  3337. }
  3338. static inline int qeth_fill_buffer(struct qeth_qdio_out_q *queue,
  3339. struct qeth_qdio_out_buffer *buf, struct sk_buff *skb,
  3340. struct qeth_hdr *hdr, int offset, int hd_len)
  3341. {
  3342. struct qdio_buffer *buffer;
  3343. int flush_cnt = 0, hdr_len, large_send = 0;
  3344. buffer = buf->buffer;
  3345. atomic_inc(&skb->users);
  3346. skb_queue_tail(&buf->skb_list, skb);
  3347. /*check first on TSO ....*/
  3348. if (hdr->hdr.l3.id == QETH_HEADER_TYPE_TSO) {
  3349. int element = buf->next_element_to_fill;
  3350. hdr_len = sizeof(struct qeth_hdr_tso) +
  3351. ((struct qeth_hdr_tso *)hdr)->ext.dg_hdr_len;
  3352. /*fill first buffer entry only with header information */
  3353. buffer->element[element].addr = skb->data;
  3354. buffer->element[element].length = hdr_len;
  3355. buffer->element[element].eflags = SBAL_EFLAGS_FIRST_FRAG;
  3356. buf->next_element_to_fill++;
  3357. skb->data += hdr_len;
  3358. skb->len -= hdr_len;
  3359. large_send = 1;
  3360. }
  3361. if (offset >= 0) {
  3362. int element = buf->next_element_to_fill;
  3363. buffer->element[element].addr = hdr;
  3364. buffer->element[element].length = sizeof(struct qeth_hdr) +
  3365. hd_len;
  3366. buffer->element[element].eflags = SBAL_EFLAGS_FIRST_FRAG;
  3367. buf->is_header[element] = 1;
  3368. buf->next_element_to_fill++;
  3369. }
  3370. __qeth_fill_buffer(skb, buffer, large_send,
  3371. (int *)&buf->next_element_to_fill, offset);
  3372. if (!queue->do_pack) {
  3373. QETH_CARD_TEXT(queue->card, 6, "fillbfnp");
  3374. /* set state to PRIMED -> will be flushed */
  3375. atomic_set(&buf->state, QETH_QDIO_BUF_PRIMED);
  3376. flush_cnt = 1;
  3377. } else {
  3378. QETH_CARD_TEXT(queue->card, 6, "fillbfpa");
  3379. if (queue->card->options.performance_stats)
  3380. queue->card->perf_stats.skbs_sent_pack++;
  3381. if (buf->next_element_to_fill >=
  3382. QETH_MAX_BUFFER_ELEMENTS(queue->card)) {
  3383. /*
  3384. * packed buffer if full -> set state PRIMED
  3385. * -> will be flushed
  3386. */
  3387. atomic_set(&buf->state, QETH_QDIO_BUF_PRIMED);
  3388. flush_cnt = 1;
  3389. }
  3390. }
  3391. return flush_cnt;
  3392. }
  3393. int qeth_do_send_packet_fast(struct qeth_card *card,
  3394. struct qeth_qdio_out_q *queue, struct sk_buff *skb,
  3395. struct qeth_hdr *hdr, int elements_needed,
  3396. int offset, int hd_len)
  3397. {
  3398. struct qeth_qdio_out_buffer *buffer;
  3399. int index;
  3400. /* spin until we get the queue ... */
  3401. while (atomic_cmpxchg(&queue->state, QETH_OUT_Q_UNLOCKED,
  3402. QETH_OUT_Q_LOCKED) != QETH_OUT_Q_UNLOCKED);
  3403. /* ... now we've got the queue */
  3404. index = queue->next_buf_to_fill;
  3405. buffer = queue->bufs[queue->next_buf_to_fill];
  3406. /*
  3407. * check if buffer is empty to make sure that we do not 'overtake'
  3408. * ourselves and try to fill a buffer that is already primed
  3409. */
  3410. if (atomic_read(&buffer->state) != QETH_QDIO_BUF_EMPTY)
  3411. goto out;
  3412. queue->next_buf_to_fill = (queue->next_buf_to_fill + 1) %
  3413. QDIO_MAX_BUFFERS_PER_Q;
  3414. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  3415. qeth_fill_buffer(queue, buffer, skb, hdr, offset, hd_len);
  3416. qeth_flush_buffers(queue, index, 1);
  3417. return 0;
  3418. out:
  3419. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  3420. return -EBUSY;
  3421. }
  3422. EXPORT_SYMBOL_GPL(qeth_do_send_packet_fast);
  3423. int qeth_do_send_packet(struct qeth_card *card, struct qeth_qdio_out_q *queue,
  3424. struct sk_buff *skb, struct qeth_hdr *hdr,
  3425. int elements_needed)
  3426. {
  3427. struct qeth_qdio_out_buffer *buffer;
  3428. int start_index;
  3429. int flush_count = 0;
  3430. int do_pack = 0;
  3431. int tmp;
  3432. int rc = 0;
  3433. /* spin until we get the queue ... */
  3434. while (atomic_cmpxchg(&queue->state, QETH_OUT_Q_UNLOCKED,
  3435. QETH_OUT_Q_LOCKED) != QETH_OUT_Q_UNLOCKED);
  3436. start_index = queue->next_buf_to_fill;
  3437. buffer = queue->bufs[queue->next_buf_to_fill];
  3438. /*
  3439. * check if buffer is empty to make sure that we do not 'overtake'
  3440. * ourselves and try to fill a buffer that is already primed
  3441. */
  3442. if (atomic_read(&buffer->state) != QETH_QDIO_BUF_EMPTY) {
  3443. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  3444. return -EBUSY;
  3445. }
  3446. /* check if we need to switch packing state of this queue */
  3447. qeth_switch_to_packing_if_needed(queue);
  3448. if (queue->do_pack) {
  3449. do_pack = 1;
  3450. /* does packet fit in current buffer? */
  3451. if ((QETH_MAX_BUFFER_ELEMENTS(card) -
  3452. buffer->next_element_to_fill) < elements_needed) {
  3453. /* ... no -> set state PRIMED */
  3454. atomic_set(&buffer->state, QETH_QDIO_BUF_PRIMED);
  3455. flush_count++;
  3456. queue->next_buf_to_fill =
  3457. (queue->next_buf_to_fill + 1) %
  3458. QDIO_MAX_BUFFERS_PER_Q;
  3459. buffer = queue->bufs[queue->next_buf_to_fill];
  3460. /* we did a step forward, so check buffer state
  3461. * again */
  3462. if (atomic_read(&buffer->state) !=
  3463. QETH_QDIO_BUF_EMPTY) {
  3464. qeth_flush_buffers(queue, start_index,
  3465. flush_count);
  3466. atomic_set(&queue->state,
  3467. QETH_OUT_Q_UNLOCKED);
  3468. return -EBUSY;
  3469. }
  3470. }
  3471. }
  3472. tmp = qeth_fill_buffer(queue, buffer, skb, hdr, -1, 0);
  3473. queue->next_buf_to_fill = (queue->next_buf_to_fill + tmp) %
  3474. QDIO_MAX_BUFFERS_PER_Q;
  3475. flush_count += tmp;
  3476. if (flush_count)
  3477. qeth_flush_buffers(queue, start_index, flush_count);
  3478. else if (!atomic_read(&queue->set_pci_flags_count))
  3479. atomic_xchg(&queue->state, QETH_OUT_Q_LOCKED_FLUSH);
  3480. /*
  3481. * queue->state will go from LOCKED -> UNLOCKED or from
  3482. * LOCKED_FLUSH -> LOCKED if output_handler wanted to 'notify' us
  3483. * (switch packing state or flush buffer to get another pci flag out).
  3484. * In that case we will enter this loop
  3485. */
  3486. while (atomic_dec_return(&queue->state)) {
  3487. flush_count = 0;
  3488. start_index = queue->next_buf_to_fill;
  3489. /* check if we can go back to non-packing state */
  3490. flush_count += qeth_switch_to_nonpacking_if_needed(queue);
  3491. /*
  3492. * check if we need to flush a packing buffer to get a pci
  3493. * flag out on the queue
  3494. */
  3495. if (!flush_count && !atomic_read(&queue->set_pci_flags_count))
  3496. flush_count += qeth_flush_buffers_on_no_pci(queue);
  3497. if (flush_count)
  3498. qeth_flush_buffers(queue, start_index, flush_count);
  3499. }
  3500. /* at this point the queue is UNLOCKED again */
  3501. if (queue->card->options.performance_stats && do_pack)
  3502. queue->card->perf_stats.bufs_sent_pack += flush_count;
  3503. return rc;
  3504. }
  3505. EXPORT_SYMBOL_GPL(qeth_do_send_packet);
  3506. static int qeth_setadp_promisc_mode_cb(struct qeth_card *card,
  3507. struct qeth_reply *reply, unsigned long data)
  3508. {
  3509. struct qeth_ipa_cmd *cmd;
  3510. struct qeth_ipacmd_setadpparms *setparms;
  3511. QETH_CARD_TEXT(card, 4, "prmadpcb");
  3512. cmd = (struct qeth_ipa_cmd *) data;
  3513. setparms = &(cmd->data.setadapterparms);
  3514. qeth_default_setadapterparms_cb(card, reply, (unsigned long)cmd);
  3515. if (cmd->hdr.return_code) {
  3516. QETH_CARD_TEXT_(card, 4, "prmrc%2.2x", cmd->hdr.return_code);
  3517. setparms->data.mode = SET_PROMISC_MODE_OFF;
  3518. }
  3519. card->info.promisc_mode = setparms->data.mode;
  3520. return 0;
  3521. }
  3522. void qeth_setadp_promisc_mode(struct qeth_card *card)
  3523. {
  3524. enum qeth_ipa_promisc_modes mode;
  3525. struct net_device *dev = card->dev;
  3526. struct qeth_cmd_buffer *iob;
  3527. struct qeth_ipa_cmd *cmd;
  3528. QETH_CARD_TEXT(card, 4, "setprom");
  3529. if (((dev->flags & IFF_PROMISC) &&
  3530. (card->info.promisc_mode == SET_PROMISC_MODE_ON)) ||
  3531. (!(dev->flags & IFF_PROMISC) &&
  3532. (card->info.promisc_mode == SET_PROMISC_MODE_OFF)))
  3533. return;
  3534. mode = SET_PROMISC_MODE_OFF;
  3535. if (dev->flags & IFF_PROMISC)
  3536. mode = SET_PROMISC_MODE_ON;
  3537. QETH_CARD_TEXT_(card, 4, "mode:%x", mode);
  3538. iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_PROMISC_MODE,
  3539. sizeof(struct qeth_ipacmd_setadpparms));
  3540. cmd = (struct qeth_ipa_cmd *)(iob->data + IPA_PDU_HEADER_SIZE);
  3541. cmd->data.setadapterparms.data.mode = mode;
  3542. qeth_send_ipa_cmd(card, iob, qeth_setadp_promisc_mode_cb, NULL);
  3543. }
  3544. EXPORT_SYMBOL_GPL(qeth_setadp_promisc_mode);
  3545. int qeth_change_mtu(struct net_device *dev, int new_mtu)
  3546. {
  3547. struct qeth_card *card;
  3548. char dbf_text[15];
  3549. card = dev->ml_priv;
  3550. QETH_CARD_TEXT(card, 4, "chgmtu");
  3551. sprintf(dbf_text, "%8x", new_mtu);
  3552. QETH_CARD_TEXT(card, 4, dbf_text);
  3553. if (new_mtu < 64)
  3554. return -EINVAL;
  3555. if (new_mtu > 65535)
  3556. return -EINVAL;
  3557. if ((!qeth_is_supported(card, IPA_IP_FRAGMENTATION)) &&
  3558. (!qeth_mtu_is_valid(card, new_mtu)))
  3559. return -EINVAL;
  3560. dev->mtu = new_mtu;
  3561. return 0;
  3562. }
  3563. EXPORT_SYMBOL_GPL(qeth_change_mtu);
  3564. struct net_device_stats *qeth_get_stats(struct net_device *dev)
  3565. {
  3566. struct qeth_card *card;
  3567. card = dev->ml_priv;
  3568. QETH_CARD_TEXT(card, 5, "getstat");
  3569. return &card->stats;
  3570. }
  3571. EXPORT_SYMBOL_GPL(qeth_get_stats);
  3572. static int qeth_setadpparms_change_macaddr_cb(struct qeth_card *card,
  3573. struct qeth_reply *reply, unsigned long data)
  3574. {
  3575. struct qeth_ipa_cmd *cmd;
  3576. QETH_CARD_TEXT(card, 4, "chgmaccb");
  3577. cmd = (struct qeth_ipa_cmd *) data;
  3578. if (!card->options.layer2 ||
  3579. !(card->info.mac_bits & QETH_LAYER2_MAC_READ)) {
  3580. memcpy(card->dev->dev_addr,
  3581. &cmd->data.setadapterparms.data.change_addr.addr,
  3582. OSA_ADDR_LEN);
  3583. card->info.mac_bits |= QETH_LAYER2_MAC_READ;
  3584. }
  3585. qeth_default_setadapterparms_cb(card, reply, (unsigned long) cmd);
  3586. return 0;
  3587. }
  3588. int qeth_setadpparms_change_macaddr(struct qeth_card *card)
  3589. {
  3590. int rc;
  3591. struct qeth_cmd_buffer *iob;
  3592. struct qeth_ipa_cmd *cmd;
  3593. QETH_CARD_TEXT(card, 4, "chgmac");
  3594. iob = qeth_get_adapter_cmd(card, IPA_SETADP_ALTER_MAC_ADDRESS,
  3595. sizeof(struct qeth_ipacmd_setadpparms));
  3596. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  3597. cmd->data.setadapterparms.data.change_addr.cmd = CHANGE_ADDR_READ_MAC;
  3598. cmd->data.setadapterparms.data.change_addr.addr_size = OSA_ADDR_LEN;
  3599. memcpy(&cmd->data.setadapterparms.data.change_addr.addr,
  3600. card->dev->dev_addr, OSA_ADDR_LEN);
  3601. rc = qeth_send_ipa_cmd(card, iob, qeth_setadpparms_change_macaddr_cb,
  3602. NULL);
  3603. return rc;
  3604. }
  3605. EXPORT_SYMBOL_GPL(qeth_setadpparms_change_macaddr);
  3606. static int qeth_setadpparms_set_access_ctrl_cb(struct qeth_card *card,
  3607. struct qeth_reply *reply, unsigned long data)
  3608. {
  3609. struct qeth_ipa_cmd *cmd;
  3610. struct qeth_set_access_ctrl *access_ctrl_req;
  3611. QETH_CARD_TEXT(card, 4, "setaccb");
  3612. cmd = (struct qeth_ipa_cmd *) data;
  3613. access_ctrl_req = &cmd->data.setadapterparms.data.set_access_ctrl;
  3614. QETH_DBF_TEXT_(SETUP, 2, "setaccb");
  3615. QETH_DBF_TEXT_(SETUP, 2, "%s", card->gdev->dev.kobj.name);
  3616. QETH_DBF_TEXT_(SETUP, 2, "rc=%d",
  3617. cmd->data.setadapterparms.hdr.return_code);
  3618. switch (cmd->data.setadapterparms.hdr.return_code) {
  3619. case SET_ACCESS_CTRL_RC_SUCCESS:
  3620. case SET_ACCESS_CTRL_RC_ALREADY_NOT_ISOLATED:
  3621. case SET_ACCESS_CTRL_RC_ALREADY_ISOLATED:
  3622. {
  3623. card->options.isolation = access_ctrl_req->subcmd_code;
  3624. if (card->options.isolation == ISOLATION_MODE_NONE) {
  3625. dev_info(&card->gdev->dev,
  3626. "QDIO data connection isolation is deactivated\n");
  3627. } else {
  3628. dev_info(&card->gdev->dev,
  3629. "QDIO data connection isolation is activated\n");
  3630. }
  3631. QETH_DBF_MESSAGE(3, "OK:SET_ACCESS_CTRL(%s, %d)==%d\n",
  3632. card->gdev->dev.kobj.name,
  3633. access_ctrl_req->subcmd_code,
  3634. cmd->data.setadapterparms.hdr.return_code);
  3635. break;
  3636. }
  3637. case SET_ACCESS_CTRL_RC_NOT_SUPPORTED:
  3638. {
  3639. QETH_DBF_MESSAGE(3, "ERR:SET_ACCESS_CTRL(%s,%d)==%d\n",
  3640. card->gdev->dev.kobj.name,
  3641. access_ctrl_req->subcmd_code,
  3642. cmd->data.setadapterparms.hdr.return_code);
  3643. dev_err(&card->gdev->dev, "Adapter does not "
  3644. "support QDIO data connection isolation\n");
  3645. /* ensure isolation mode is "none" */
  3646. card->options.isolation = ISOLATION_MODE_NONE;
  3647. break;
  3648. }
  3649. case SET_ACCESS_CTRL_RC_NONE_SHARED_ADAPTER:
  3650. {
  3651. QETH_DBF_MESSAGE(3, "ERR:SET_ACCESS_MODE(%s,%d)==%d\n",
  3652. card->gdev->dev.kobj.name,
  3653. access_ctrl_req->subcmd_code,
  3654. cmd->data.setadapterparms.hdr.return_code);
  3655. dev_err(&card->gdev->dev,
  3656. "Adapter is dedicated. "
  3657. "QDIO data connection isolation not supported\n");
  3658. /* ensure isolation mode is "none" */
  3659. card->options.isolation = ISOLATION_MODE_NONE;
  3660. break;
  3661. }
  3662. case SET_ACCESS_CTRL_RC_ACTIVE_CHECKSUM_OFF:
  3663. {
  3664. QETH_DBF_MESSAGE(3, "ERR:SET_ACCESS_MODE(%s,%d)==%d\n",
  3665. card->gdev->dev.kobj.name,
  3666. access_ctrl_req->subcmd_code,
  3667. cmd->data.setadapterparms.hdr.return_code);
  3668. dev_err(&card->gdev->dev,
  3669. "TSO does not permit QDIO data connection isolation\n");
  3670. /* ensure isolation mode is "none" */
  3671. card->options.isolation = ISOLATION_MODE_NONE;
  3672. break;
  3673. }
  3674. default:
  3675. {
  3676. /* this should never happen */
  3677. QETH_DBF_MESSAGE(3, "ERR:SET_ACCESS_MODE(%s,%d)==%d"
  3678. "==UNKNOWN\n",
  3679. card->gdev->dev.kobj.name,
  3680. access_ctrl_req->subcmd_code,
  3681. cmd->data.setadapterparms.hdr.return_code);
  3682. /* ensure isolation mode is "none" */
  3683. card->options.isolation = ISOLATION_MODE_NONE;
  3684. break;
  3685. }
  3686. }
  3687. qeth_default_setadapterparms_cb(card, reply, (unsigned long) cmd);
  3688. return 0;
  3689. }
  3690. static int qeth_setadpparms_set_access_ctrl(struct qeth_card *card,
  3691. enum qeth_ipa_isolation_modes isolation)
  3692. {
  3693. int rc;
  3694. struct qeth_cmd_buffer *iob;
  3695. struct qeth_ipa_cmd *cmd;
  3696. struct qeth_set_access_ctrl *access_ctrl_req;
  3697. QETH_CARD_TEXT(card, 4, "setacctl");
  3698. QETH_DBF_TEXT_(SETUP, 2, "setacctl");
  3699. QETH_DBF_TEXT_(SETUP, 2, "%s", card->gdev->dev.kobj.name);
  3700. iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_ACCESS_CONTROL,
  3701. sizeof(struct qeth_ipacmd_setadpparms_hdr) +
  3702. sizeof(struct qeth_set_access_ctrl));
  3703. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  3704. access_ctrl_req = &cmd->data.setadapterparms.data.set_access_ctrl;
  3705. access_ctrl_req->subcmd_code = isolation;
  3706. rc = qeth_send_ipa_cmd(card, iob, qeth_setadpparms_set_access_ctrl_cb,
  3707. NULL);
  3708. QETH_DBF_TEXT_(SETUP, 2, "rc=%d", rc);
  3709. return rc;
  3710. }
  3711. int qeth_set_access_ctrl_online(struct qeth_card *card)
  3712. {
  3713. int rc = 0;
  3714. QETH_CARD_TEXT(card, 4, "setactlo");
  3715. if ((card->info.type == QETH_CARD_TYPE_OSD ||
  3716. card->info.type == QETH_CARD_TYPE_OSX) &&
  3717. qeth_adp_supported(card, IPA_SETADP_SET_ACCESS_CONTROL)) {
  3718. rc = qeth_setadpparms_set_access_ctrl(card,
  3719. card->options.isolation);
  3720. if (rc) {
  3721. QETH_DBF_MESSAGE(3,
  3722. "IPA(SET_ACCESS_CTRL,%s,%d) sent failed\n",
  3723. card->gdev->dev.kobj.name,
  3724. rc);
  3725. }
  3726. } else if (card->options.isolation != ISOLATION_MODE_NONE) {
  3727. card->options.isolation = ISOLATION_MODE_NONE;
  3728. dev_err(&card->gdev->dev, "Adapter does not "
  3729. "support QDIO data connection isolation\n");
  3730. rc = -EOPNOTSUPP;
  3731. }
  3732. return rc;
  3733. }
  3734. EXPORT_SYMBOL_GPL(qeth_set_access_ctrl_online);
  3735. void qeth_tx_timeout(struct net_device *dev)
  3736. {
  3737. struct qeth_card *card;
  3738. card = dev->ml_priv;
  3739. QETH_CARD_TEXT(card, 4, "txtimeo");
  3740. card->stats.tx_errors++;
  3741. qeth_schedule_recovery(card);
  3742. }
  3743. EXPORT_SYMBOL_GPL(qeth_tx_timeout);
  3744. int qeth_mdio_read(struct net_device *dev, int phy_id, int regnum)
  3745. {
  3746. struct qeth_card *card = dev->ml_priv;
  3747. int rc = 0;
  3748. switch (regnum) {
  3749. case MII_BMCR: /* Basic mode control register */
  3750. rc = BMCR_FULLDPLX;
  3751. if ((card->info.link_type != QETH_LINK_TYPE_GBIT_ETH) &&
  3752. (card->info.link_type != QETH_LINK_TYPE_OSN) &&
  3753. (card->info.link_type != QETH_LINK_TYPE_10GBIT_ETH))
  3754. rc |= BMCR_SPEED100;
  3755. break;
  3756. case MII_BMSR: /* Basic mode status register */
  3757. rc = BMSR_ERCAP | BMSR_ANEGCOMPLETE | BMSR_LSTATUS |
  3758. BMSR_10HALF | BMSR_10FULL | BMSR_100HALF | BMSR_100FULL |
  3759. BMSR_100BASE4;
  3760. break;
  3761. case MII_PHYSID1: /* PHYS ID 1 */
  3762. rc = (dev->dev_addr[0] << 16) | (dev->dev_addr[1] << 8) |
  3763. dev->dev_addr[2];
  3764. rc = (rc >> 5) & 0xFFFF;
  3765. break;
  3766. case MII_PHYSID2: /* PHYS ID 2 */
  3767. rc = (dev->dev_addr[2] << 10) & 0xFFFF;
  3768. break;
  3769. case MII_ADVERTISE: /* Advertisement control reg */
  3770. rc = ADVERTISE_ALL;
  3771. break;
  3772. case MII_LPA: /* Link partner ability reg */
  3773. rc = LPA_10HALF | LPA_10FULL | LPA_100HALF | LPA_100FULL |
  3774. LPA_100BASE4 | LPA_LPACK;
  3775. break;
  3776. case MII_EXPANSION: /* Expansion register */
  3777. break;
  3778. case MII_DCOUNTER: /* disconnect counter */
  3779. break;
  3780. case MII_FCSCOUNTER: /* false carrier counter */
  3781. break;
  3782. case MII_NWAYTEST: /* N-way auto-neg test register */
  3783. break;
  3784. case MII_RERRCOUNTER: /* rx error counter */
  3785. rc = card->stats.rx_errors;
  3786. break;
  3787. case MII_SREVISION: /* silicon revision */
  3788. break;
  3789. case MII_RESV1: /* reserved 1 */
  3790. break;
  3791. case MII_LBRERROR: /* loopback, rx, bypass error */
  3792. break;
  3793. case MII_PHYADDR: /* physical address */
  3794. break;
  3795. case MII_RESV2: /* reserved 2 */
  3796. break;
  3797. case MII_TPISTATUS: /* TPI status for 10mbps */
  3798. break;
  3799. case MII_NCONFIG: /* network interface config */
  3800. break;
  3801. default:
  3802. break;
  3803. }
  3804. return rc;
  3805. }
  3806. EXPORT_SYMBOL_GPL(qeth_mdio_read);
  3807. static int qeth_send_ipa_snmp_cmd(struct qeth_card *card,
  3808. struct qeth_cmd_buffer *iob, int len,
  3809. int (*reply_cb)(struct qeth_card *, struct qeth_reply *,
  3810. unsigned long),
  3811. void *reply_param)
  3812. {
  3813. u16 s1, s2;
  3814. QETH_CARD_TEXT(card, 4, "sendsnmp");
  3815. memcpy(iob->data, IPA_PDU_HEADER, IPA_PDU_HEADER_SIZE);
  3816. memcpy(QETH_IPA_CMD_DEST_ADDR(iob->data),
  3817. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  3818. /* adjust PDU length fields in IPA_PDU_HEADER */
  3819. s1 = (u32) IPA_PDU_HEADER_SIZE + len;
  3820. s2 = (u32) len;
  3821. memcpy(QETH_IPA_PDU_LEN_TOTAL(iob->data), &s1, 2);
  3822. memcpy(QETH_IPA_PDU_LEN_PDU1(iob->data), &s2, 2);
  3823. memcpy(QETH_IPA_PDU_LEN_PDU2(iob->data), &s2, 2);
  3824. memcpy(QETH_IPA_PDU_LEN_PDU3(iob->data), &s2, 2);
  3825. return qeth_send_control_data(card, IPA_PDU_HEADER_SIZE + len, iob,
  3826. reply_cb, reply_param);
  3827. }
  3828. static int qeth_snmp_command_cb(struct qeth_card *card,
  3829. struct qeth_reply *reply, unsigned long sdata)
  3830. {
  3831. struct qeth_ipa_cmd *cmd;
  3832. struct qeth_arp_query_info *qinfo;
  3833. struct qeth_snmp_cmd *snmp;
  3834. unsigned char *data;
  3835. __u16 data_len;
  3836. QETH_CARD_TEXT(card, 3, "snpcmdcb");
  3837. cmd = (struct qeth_ipa_cmd *) sdata;
  3838. data = (unsigned char *)((char *)cmd - reply->offset);
  3839. qinfo = (struct qeth_arp_query_info *) reply->param;
  3840. snmp = &cmd->data.setadapterparms.data.snmp;
  3841. if (cmd->hdr.return_code) {
  3842. QETH_CARD_TEXT_(card, 4, "scer1%i", cmd->hdr.return_code);
  3843. return 0;
  3844. }
  3845. if (cmd->data.setadapterparms.hdr.return_code) {
  3846. cmd->hdr.return_code =
  3847. cmd->data.setadapterparms.hdr.return_code;
  3848. QETH_CARD_TEXT_(card, 4, "scer2%i", cmd->hdr.return_code);
  3849. return 0;
  3850. }
  3851. data_len = *((__u16 *)QETH_IPA_PDU_LEN_PDU1(data));
  3852. if (cmd->data.setadapterparms.hdr.seq_no == 1)
  3853. data_len -= (__u16)((char *)&snmp->data - (char *)cmd);
  3854. else
  3855. data_len -= (__u16)((char *)&snmp->request - (char *)cmd);
  3856. /* check if there is enough room in userspace */
  3857. if ((qinfo->udata_len - qinfo->udata_offset) < data_len) {
  3858. QETH_CARD_TEXT_(card, 4, "scer3%i", -ENOMEM);
  3859. cmd->hdr.return_code = IPA_RC_ENOMEM;
  3860. return 0;
  3861. }
  3862. QETH_CARD_TEXT_(card, 4, "snore%i",
  3863. cmd->data.setadapterparms.hdr.used_total);
  3864. QETH_CARD_TEXT_(card, 4, "sseqn%i",
  3865. cmd->data.setadapterparms.hdr.seq_no);
  3866. /*copy entries to user buffer*/
  3867. if (cmd->data.setadapterparms.hdr.seq_no == 1) {
  3868. memcpy(qinfo->udata + qinfo->udata_offset,
  3869. (char *)snmp,
  3870. data_len + offsetof(struct qeth_snmp_cmd, data));
  3871. qinfo->udata_offset += offsetof(struct qeth_snmp_cmd, data);
  3872. } else {
  3873. memcpy(qinfo->udata + qinfo->udata_offset,
  3874. (char *)&snmp->request, data_len);
  3875. }
  3876. qinfo->udata_offset += data_len;
  3877. /* check if all replies received ... */
  3878. QETH_CARD_TEXT_(card, 4, "srtot%i",
  3879. cmd->data.setadapterparms.hdr.used_total);
  3880. QETH_CARD_TEXT_(card, 4, "srseq%i",
  3881. cmd->data.setadapterparms.hdr.seq_no);
  3882. if (cmd->data.setadapterparms.hdr.seq_no <
  3883. cmd->data.setadapterparms.hdr.used_total)
  3884. return 1;
  3885. return 0;
  3886. }
  3887. int qeth_snmp_command(struct qeth_card *card, char __user *udata)
  3888. {
  3889. struct qeth_cmd_buffer *iob;
  3890. struct qeth_ipa_cmd *cmd;
  3891. struct qeth_snmp_ureq *ureq;
  3892. int req_len;
  3893. struct qeth_arp_query_info qinfo = {0, };
  3894. int rc = 0;
  3895. QETH_CARD_TEXT(card, 3, "snmpcmd");
  3896. if (card->info.guestlan)
  3897. return -EOPNOTSUPP;
  3898. if ((!qeth_adp_supported(card, IPA_SETADP_SET_SNMP_CONTROL)) &&
  3899. (!card->options.layer2)) {
  3900. return -EOPNOTSUPP;
  3901. }
  3902. /* skip 4 bytes (data_len struct member) to get req_len */
  3903. if (copy_from_user(&req_len, udata + sizeof(int), sizeof(int)))
  3904. return -EFAULT;
  3905. ureq = memdup_user(udata, req_len + sizeof(struct qeth_snmp_ureq_hdr));
  3906. if (IS_ERR(ureq)) {
  3907. QETH_CARD_TEXT(card, 2, "snmpnome");
  3908. return PTR_ERR(ureq);
  3909. }
  3910. qinfo.udata_len = ureq->hdr.data_len;
  3911. qinfo.udata = kzalloc(qinfo.udata_len, GFP_KERNEL);
  3912. if (!qinfo.udata) {
  3913. kfree(ureq);
  3914. return -ENOMEM;
  3915. }
  3916. qinfo.udata_offset = sizeof(struct qeth_snmp_ureq_hdr);
  3917. iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_SNMP_CONTROL,
  3918. QETH_SNMP_SETADP_CMDLENGTH + req_len);
  3919. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  3920. memcpy(&cmd->data.setadapterparms.data.snmp, &ureq->cmd, req_len);
  3921. rc = qeth_send_ipa_snmp_cmd(card, iob, QETH_SETADP_BASE_LEN + req_len,
  3922. qeth_snmp_command_cb, (void *)&qinfo);
  3923. if (rc)
  3924. QETH_DBF_MESSAGE(2, "SNMP command failed on %s: (0x%x)\n",
  3925. QETH_CARD_IFNAME(card), rc);
  3926. else {
  3927. if (copy_to_user(udata, qinfo.udata, qinfo.udata_len))
  3928. rc = -EFAULT;
  3929. }
  3930. kfree(ureq);
  3931. kfree(qinfo.udata);
  3932. return rc;
  3933. }
  3934. EXPORT_SYMBOL_GPL(qeth_snmp_command);
  3935. static int qeth_setadpparms_query_oat_cb(struct qeth_card *card,
  3936. struct qeth_reply *reply, unsigned long data)
  3937. {
  3938. struct qeth_ipa_cmd *cmd;
  3939. struct qeth_qoat_priv *priv;
  3940. char *resdata;
  3941. int resdatalen;
  3942. QETH_CARD_TEXT(card, 3, "qoatcb");
  3943. cmd = (struct qeth_ipa_cmd *)data;
  3944. priv = (struct qeth_qoat_priv *)reply->param;
  3945. resdatalen = cmd->data.setadapterparms.hdr.cmdlength;
  3946. resdata = (char *)data + 28;
  3947. if (resdatalen > (priv->buffer_len - priv->response_len)) {
  3948. cmd->hdr.return_code = IPA_RC_FFFF;
  3949. return 0;
  3950. }
  3951. memcpy((priv->buffer + priv->response_len), resdata,
  3952. resdatalen);
  3953. priv->response_len += resdatalen;
  3954. if (cmd->data.setadapterparms.hdr.seq_no <
  3955. cmd->data.setadapterparms.hdr.used_total)
  3956. return 1;
  3957. return 0;
  3958. }
  3959. int qeth_query_oat_command(struct qeth_card *card, char __user *udata)
  3960. {
  3961. int rc = 0;
  3962. struct qeth_cmd_buffer *iob;
  3963. struct qeth_ipa_cmd *cmd;
  3964. struct qeth_query_oat *oat_req;
  3965. struct qeth_query_oat_data oat_data;
  3966. struct qeth_qoat_priv priv;
  3967. void __user *tmp;
  3968. QETH_CARD_TEXT(card, 3, "qoatcmd");
  3969. if (!qeth_adp_supported(card, IPA_SETADP_QUERY_OAT)) {
  3970. rc = -EOPNOTSUPP;
  3971. goto out;
  3972. }
  3973. if (copy_from_user(&oat_data, udata,
  3974. sizeof(struct qeth_query_oat_data))) {
  3975. rc = -EFAULT;
  3976. goto out;
  3977. }
  3978. priv.buffer_len = oat_data.buffer_len;
  3979. priv.response_len = 0;
  3980. priv.buffer = kzalloc(oat_data.buffer_len, GFP_KERNEL);
  3981. if (!priv.buffer) {
  3982. rc = -ENOMEM;
  3983. goto out;
  3984. }
  3985. iob = qeth_get_adapter_cmd(card, IPA_SETADP_QUERY_OAT,
  3986. sizeof(struct qeth_ipacmd_setadpparms_hdr) +
  3987. sizeof(struct qeth_query_oat));
  3988. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  3989. oat_req = &cmd->data.setadapterparms.data.query_oat;
  3990. oat_req->subcmd_code = oat_data.command;
  3991. rc = qeth_send_ipa_cmd(card, iob, qeth_setadpparms_query_oat_cb,
  3992. &priv);
  3993. if (!rc) {
  3994. if (is_compat_task())
  3995. tmp = compat_ptr(oat_data.ptr);
  3996. else
  3997. tmp = (void __user *)(unsigned long)oat_data.ptr;
  3998. if (copy_to_user(tmp, priv.buffer,
  3999. priv.response_len)) {
  4000. rc = -EFAULT;
  4001. goto out_free;
  4002. }
  4003. oat_data.response_len = priv.response_len;
  4004. if (copy_to_user(udata, &oat_data,
  4005. sizeof(struct qeth_query_oat_data)))
  4006. rc = -EFAULT;
  4007. } else
  4008. if (rc == IPA_RC_FFFF)
  4009. rc = -EFAULT;
  4010. out_free:
  4011. kfree(priv.buffer);
  4012. out:
  4013. return rc;
  4014. }
  4015. EXPORT_SYMBOL_GPL(qeth_query_oat_command);
  4016. static inline int qeth_get_qdio_q_format(struct qeth_card *card)
  4017. {
  4018. switch (card->info.type) {
  4019. case QETH_CARD_TYPE_IQD:
  4020. return 2;
  4021. default:
  4022. return 0;
  4023. }
  4024. }
  4025. static void qeth_determine_capabilities(struct qeth_card *card)
  4026. {
  4027. int rc;
  4028. int length;
  4029. char *prcd;
  4030. struct ccw_device *ddev;
  4031. int ddev_offline = 0;
  4032. QETH_DBF_TEXT(SETUP, 2, "detcapab");
  4033. ddev = CARD_DDEV(card);
  4034. if (!ddev->online) {
  4035. ddev_offline = 1;
  4036. rc = ccw_device_set_online(ddev);
  4037. if (rc) {
  4038. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  4039. goto out;
  4040. }
  4041. }
  4042. rc = qeth_read_conf_data(card, (void **) &prcd, &length);
  4043. if (rc) {
  4044. QETH_DBF_MESSAGE(2, "%s qeth_read_conf_data returned %i\n",
  4045. dev_name(&card->gdev->dev), rc);
  4046. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  4047. goto out_offline;
  4048. }
  4049. qeth_configure_unitaddr(card, prcd);
  4050. if (ddev_offline)
  4051. qeth_configure_blkt_default(card, prcd);
  4052. kfree(prcd);
  4053. rc = qdio_get_ssqd_desc(ddev, &card->ssqd);
  4054. if (rc)
  4055. QETH_DBF_TEXT_(SETUP, 2, "6err%d", rc);
  4056. QETH_DBF_TEXT_(SETUP, 2, "qfmt%d", card->ssqd.qfmt);
  4057. QETH_DBF_TEXT_(SETUP, 2, "%d", card->ssqd.qdioac1);
  4058. QETH_DBF_TEXT_(SETUP, 2, "%d", card->ssqd.qdioac3);
  4059. QETH_DBF_TEXT_(SETUP, 2, "icnt%d", card->ssqd.icnt);
  4060. if (!((card->ssqd.qfmt != QDIO_IQDIO_QFMT) ||
  4061. ((card->ssqd.qdioac1 & CHSC_AC1_INITIATE_INPUTQ) == 0) ||
  4062. ((card->ssqd.qdioac3 & CHSC_AC3_FORMAT2_CQ_AVAILABLE) == 0))) {
  4063. dev_info(&card->gdev->dev,
  4064. "Completion Queueing supported\n");
  4065. } else {
  4066. card->options.cq = QETH_CQ_NOTAVAILABLE;
  4067. }
  4068. out_offline:
  4069. if (ddev_offline == 1)
  4070. ccw_device_set_offline(ddev);
  4071. out:
  4072. return;
  4073. }
  4074. static inline void qeth_qdio_establish_cq(struct qeth_card *card,
  4075. struct qdio_buffer **in_sbal_ptrs,
  4076. void (**queue_start_poll) (struct ccw_device *, int, unsigned long)) {
  4077. int i;
  4078. if (card->options.cq == QETH_CQ_ENABLED) {
  4079. int offset = QDIO_MAX_BUFFERS_PER_Q *
  4080. (card->qdio.no_in_queues - 1);
  4081. i = QDIO_MAX_BUFFERS_PER_Q * (card->qdio.no_in_queues - 1);
  4082. for (i = 0; i < QDIO_MAX_BUFFERS_PER_Q; ++i) {
  4083. in_sbal_ptrs[offset + i] = (struct qdio_buffer *)
  4084. virt_to_phys(card->qdio.c_q->bufs[i].buffer);
  4085. }
  4086. queue_start_poll[card->qdio.no_in_queues - 1] = NULL;
  4087. }
  4088. }
  4089. static int qeth_qdio_establish(struct qeth_card *card)
  4090. {
  4091. struct qdio_initialize init_data;
  4092. char *qib_param_field;
  4093. struct qdio_buffer **in_sbal_ptrs;
  4094. void (**queue_start_poll) (struct ccw_device *, int, unsigned long);
  4095. struct qdio_buffer **out_sbal_ptrs;
  4096. int i, j, k;
  4097. int rc = 0;
  4098. QETH_DBF_TEXT(SETUP, 2, "qdioest");
  4099. qib_param_field = kzalloc(QDIO_MAX_BUFFERS_PER_Q * sizeof(char),
  4100. GFP_KERNEL);
  4101. if (!qib_param_field) {
  4102. rc = -ENOMEM;
  4103. goto out_free_nothing;
  4104. }
  4105. qeth_create_qib_param_field(card, qib_param_field);
  4106. qeth_create_qib_param_field_blkt(card, qib_param_field);
  4107. in_sbal_ptrs = kzalloc(card->qdio.no_in_queues *
  4108. QDIO_MAX_BUFFERS_PER_Q * sizeof(void *),
  4109. GFP_KERNEL);
  4110. if (!in_sbal_ptrs) {
  4111. rc = -ENOMEM;
  4112. goto out_free_qib_param;
  4113. }
  4114. for (i = 0; i < QDIO_MAX_BUFFERS_PER_Q; ++i) {
  4115. in_sbal_ptrs[i] = (struct qdio_buffer *)
  4116. virt_to_phys(card->qdio.in_q->bufs[i].buffer);
  4117. }
  4118. queue_start_poll = kzalloc(sizeof(void *) * card->qdio.no_in_queues,
  4119. GFP_KERNEL);
  4120. if (!queue_start_poll) {
  4121. rc = -ENOMEM;
  4122. goto out_free_in_sbals;
  4123. }
  4124. for (i = 0; i < card->qdio.no_in_queues; ++i)
  4125. queue_start_poll[i] = card->discipline->start_poll;
  4126. qeth_qdio_establish_cq(card, in_sbal_ptrs, queue_start_poll);
  4127. out_sbal_ptrs =
  4128. kzalloc(card->qdio.no_out_queues * QDIO_MAX_BUFFERS_PER_Q *
  4129. sizeof(void *), GFP_KERNEL);
  4130. if (!out_sbal_ptrs) {
  4131. rc = -ENOMEM;
  4132. goto out_free_queue_start_poll;
  4133. }
  4134. for (i = 0, k = 0; i < card->qdio.no_out_queues; ++i)
  4135. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j, ++k) {
  4136. out_sbal_ptrs[k] = (struct qdio_buffer *)virt_to_phys(
  4137. card->qdio.out_qs[i]->bufs[j]->buffer);
  4138. }
  4139. memset(&init_data, 0, sizeof(struct qdio_initialize));
  4140. init_data.cdev = CARD_DDEV(card);
  4141. init_data.q_format = qeth_get_qdio_q_format(card);
  4142. init_data.qib_param_field_format = 0;
  4143. init_data.qib_param_field = qib_param_field;
  4144. init_data.no_input_qs = card->qdio.no_in_queues;
  4145. init_data.no_output_qs = card->qdio.no_out_queues;
  4146. init_data.input_handler = card->discipline->input_handler;
  4147. init_data.output_handler = card->discipline->output_handler;
  4148. init_data.queue_start_poll_array = queue_start_poll;
  4149. init_data.int_parm = (unsigned long) card;
  4150. init_data.input_sbal_addr_array = (void **) in_sbal_ptrs;
  4151. init_data.output_sbal_addr_array = (void **) out_sbal_ptrs;
  4152. init_data.output_sbal_state_array = card->qdio.out_bufstates;
  4153. init_data.scan_threshold =
  4154. (card->info.type == QETH_CARD_TYPE_IQD) ? 8 : 32;
  4155. if (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_ALLOCATED,
  4156. QETH_QDIO_ESTABLISHED) == QETH_QDIO_ALLOCATED) {
  4157. rc = qdio_allocate(&init_data);
  4158. if (rc) {
  4159. atomic_set(&card->qdio.state, QETH_QDIO_ALLOCATED);
  4160. goto out;
  4161. }
  4162. rc = qdio_establish(&init_data);
  4163. if (rc) {
  4164. atomic_set(&card->qdio.state, QETH_QDIO_ALLOCATED);
  4165. qdio_free(CARD_DDEV(card));
  4166. }
  4167. }
  4168. switch (card->options.cq) {
  4169. case QETH_CQ_ENABLED:
  4170. dev_info(&card->gdev->dev, "Completion Queue support enabled");
  4171. break;
  4172. case QETH_CQ_DISABLED:
  4173. dev_info(&card->gdev->dev, "Completion Queue support disabled");
  4174. break;
  4175. default:
  4176. break;
  4177. }
  4178. out:
  4179. kfree(out_sbal_ptrs);
  4180. out_free_queue_start_poll:
  4181. kfree(queue_start_poll);
  4182. out_free_in_sbals:
  4183. kfree(in_sbal_ptrs);
  4184. out_free_qib_param:
  4185. kfree(qib_param_field);
  4186. out_free_nothing:
  4187. return rc;
  4188. }
  4189. static void qeth_core_free_card(struct qeth_card *card)
  4190. {
  4191. QETH_DBF_TEXT(SETUP, 2, "freecrd");
  4192. QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
  4193. qeth_clean_channel(&card->read);
  4194. qeth_clean_channel(&card->write);
  4195. if (card->dev)
  4196. free_netdev(card->dev);
  4197. kfree(card->ip_tbd_list);
  4198. qeth_free_qdio_buffers(card);
  4199. unregister_service_level(&card->qeth_service_level);
  4200. kfree(card);
  4201. }
  4202. static struct ccw_device_id qeth_ids[] = {
  4203. {CCW_DEVICE_DEVTYPE(0x1731, 0x01, 0x1732, 0x01),
  4204. .driver_info = QETH_CARD_TYPE_OSD},
  4205. {CCW_DEVICE_DEVTYPE(0x1731, 0x05, 0x1732, 0x05),
  4206. .driver_info = QETH_CARD_TYPE_IQD},
  4207. {CCW_DEVICE_DEVTYPE(0x1731, 0x06, 0x1732, 0x06),
  4208. .driver_info = QETH_CARD_TYPE_OSN},
  4209. {CCW_DEVICE_DEVTYPE(0x1731, 0x02, 0x1732, 0x03),
  4210. .driver_info = QETH_CARD_TYPE_OSM},
  4211. {CCW_DEVICE_DEVTYPE(0x1731, 0x02, 0x1732, 0x02),
  4212. .driver_info = QETH_CARD_TYPE_OSX},
  4213. {},
  4214. };
  4215. MODULE_DEVICE_TABLE(ccw, qeth_ids);
  4216. static struct ccw_driver qeth_ccw_driver = {
  4217. .driver = {
  4218. .owner = THIS_MODULE,
  4219. .name = "qeth",
  4220. },
  4221. .ids = qeth_ids,
  4222. .probe = ccwgroup_probe_ccwdev,
  4223. .remove = ccwgroup_remove_ccwdev,
  4224. };
  4225. int qeth_core_hardsetup_card(struct qeth_card *card)
  4226. {
  4227. int retries = 0;
  4228. int rc;
  4229. QETH_DBF_TEXT(SETUP, 2, "hrdsetup");
  4230. atomic_set(&card->force_alloc_skb, 0);
  4231. qeth_get_channel_path_desc(card);
  4232. retry:
  4233. if (retries)
  4234. QETH_DBF_MESSAGE(2, "%s Retrying to do IDX activates.\n",
  4235. dev_name(&card->gdev->dev));
  4236. ccw_device_set_offline(CARD_DDEV(card));
  4237. ccw_device_set_offline(CARD_WDEV(card));
  4238. ccw_device_set_offline(CARD_RDEV(card));
  4239. rc = ccw_device_set_online(CARD_RDEV(card));
  4240. if (rc)
  4241. goto retriable;
  4242. rc = ccw_device_set_online(CARD_WDEV(card));
  4243. if (rc)
  4244. goto retriable;
  4245. rc = ccw_device_set_online(CARD_DDEV(card));
  4246. if (rc)
  4247. goto retriable;
  4248. rc = qeth_qdio_clear_card(card, card->info.type != QETH_CARD_TYPE_IQD);
  4249. retriable:
  4250. if (rc == -ERESTARTSYS) {
  4251. QETH_DBF_TEXT(SETUP, 2, "break1");
  4252. return rc;
  4253. } else if (rc) {
  4254. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  4255. if (++retries > 3)
  4256. goto out;
  4257. else
  4258. goto retry;
  4259. }
  4260. qeth_determine_capabilities(card);
  4261. qeth_init_tokens(card);
  4262. qeth_init_func_level(card);
  4263. rc = qeth_idx_activate_channel(&card->read, qeth_idx_read_cb);
  4264. if (rc == -ERESTARTSYS) {
  4265. QETH_DBF_TEXT(SETUP, 2, "break2");
  4266. return rc;
  4267. } else if (rc) {
  4268. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  4269. if (--retries < 0)
  4270. goto out;
  4271. else
  4272. goto retry;
  4273. }
  4274. rc = qeth_idx_activate_channel(&card->write, qeth_idx_write_cb);
  4275. if (rc == -ERESTARTSYS) {
  4276. QETH_DBF_TEXT(SETUP, 2, "break3");
  4277. return rc;
  4278. } else if (rc) {
  4279. QETH_DBF_TEXT_(SETUP, 2, "4err%d", rc);
  4280. if (--retries < 0)
  4281. goto out;
  4282. else
  4283. goto retry;
  4284. }
  4285. card->read_or_write_problem = 0;
  4286. rc = qeth_mpc_initialize(card);
  4287. if (rc) {
  4288. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  4289. goto out;
  4290. }
  4291. card->options.ipa4.supported_funcs = 0;
  4292. card->options.adp.supported_funcs = 0;
  4293. card->info.diagass_support = 0;
  4294. qeth_query_ipassists(card, QETH_PROT_IPV4);
  4295. if (qeth_is_supported(card, IPA_SETADAPTERPARMS))
  4296. qeth_query_setadapterparms(card);
  4297. if (qeth_adp_supported(card, IPA_SETADP_SET_DIAG_ASSIST))
  4298. qeth_query_setdiagass(card);
  4299. return 0;
  4300. out:
  4301. dev_warn(&card->gdev->dev, "The qeth device driver failed to recover "
  4302. "an error on the device\n");
  4303. QETH_DBF_MESSAGE(2, "%s Initialization in hardsetup failed! rc=%d\n",
  4304. dev_name(&card->gdev->dev), rc);
  4305. return rc;
  4306. }
  4307. EXPORT_SYMBOL_GPL(qeth_core_hardsetup_card);
  4308. static inline int qeth_create_skb_frag(struct qeth_qdio_buffer *qethbuffer,
  4309. struct qdio_buffer_element *element,
  4310. struct sk_buff **pskb, int offset, int *pfrag, int data_len)
  4311. {
  4312. struct page *page = virt_to_page(element->addr);
  4313. if (*pskb == NULL) {
  4314. if (qethbuffer->rx_skb) {
  4315. /* only if qeth_card.options.cq == QETH_CQ_ENABLED */
  4316. *pskb = qethbuffer->rx_skb;
  4317. qethbuffer->rx_skb = NULL;
  4318. } else {
  4319. *pskb = dev_alloc_skb(QETH_RX_PULL_LEN + ETH_HLEN);
  4320. if (!(*pskb))
  4321. return -ENOMEM;
  4322. }
  4323. skb_reserve(*pskb, ETH_HLEN);
  4324. if (data_len <= QETH_RX_PULL_LEN) {
  4325. memcpy(skb_put(*pskb, data_len), element->addr + offset,
  4326. data_len);
  4327. } else {
  4328. get_page(page);
  4329. memcpy(skb_put(*pskb, QETH_RX_PULL_LEN),
  4330. element->addr + offset, QETH_RX_PULL_LEN);
  4331. skb_fill_page_desc(*pskb, *pfrag, page,
  4332. offset + QETH_RX_PULL_LEN,
  4333. data_len - QETH_RX_PULL_LEN);
  4334. (*pskb)->data_len += data_len - QETH_RX_PULL_LEN;
  4335. (*pskb)->len += data_len - QETH_RX_PULL_LEN;
  4336. (*pskb)->truesize += data_len - QETH_RX_PULL_LEN;
  4337. (*pfrag)++;
  4338. }
  4339. } else {
  4340. get_page(page);
  4341. skb_fill_page_desc(*pskb, *pfrag, page, offset, data_len);
  4342. (*pskb)->data_len += data_len;
  4343. (*pskb)->len += data_len;
  4344. (*pskb)->truesize += data_len;
  4345. (*pfrag)++;
  4346. }
  4347. return 0;
  4348. }
  4349. struct sk_buff *qeth_core_get_next_skb(struct qeth_card *card,
  4350. struct qeth_qdio_buffer *qethbuffer,
  4351. struct qdio_buffer_element **__element, int *__offset,
  4352. struct qeth_hdr **hdr)
  4353. {
  4354. struct qdio_buffer_element *element = *__element;
  4355. struct qdio_buffer *buffer = qethbuffer->buffer;
  4356. int offset = *__offset;
  4357. struct sk_buff *skb = NULL;
  4358. int skb_len = 0;
  4359. void *data_ptr;
  4360. int data_len;
  4361. int headroom = 0;
  4362. int use_rx_sg = 0;
  4363. int frag = 0;
  4364. /* qeth_hdr must not cross element boundaries */
  4365. if (element->length < offset + sizeof(struct qeth_hdr)) {
  4366. if (qeth_is_last_sbale(element))
  4367. return NULL;
  4368. element++;
  4369. offset = 0;
  4370. if (element->length < sizeof(struct qeth_hdr))
  4371. return NULL;
  4372. }
  4373. *hdr = element->addr + offset;
  4374. offset += sizeof(struct qeth_hdr);
  4375. switch ((*hdr)->hdr.l2.id) {
  4376. case QETH_HEADER_TYPE_LAYER2:
  4377. skb_len = (*hdr)->hdr.l2.pkt_length;
  4378. break;
  4379. case QETH_HEADER_TYPE_LAYER3:
  4380. skb_len = (*hdr)->hdr.l3.length;
  4381. headroom = ETH_HLEN;
  4382. break;
  4383. case QETH_HEADER_TYPE_OSN:
  4384. skb_len = (*hdr)->hdr.osn.pdu_length;
  4385. headroom = sizeof(struct qeth_hdr);
  4386. break;
  4387. default:
  4388. break;
  4389. }
  4390. if (!skb_len)
  4391. return NULL;
  4392. if (((skb_len >= card->options.rx_sg_cb) &&
  4393. (!(card->info.type == QETH_CARD_TYPE_OSN)) &&
  4394. (!atomic_read(&card->force_alloc_skb))) ||
  4395. (card->options.cq == QETH_CQ_ENABLED)) {
  4396. use_rx_sg = 1;
  4397. } else {
  4398. skb = dev_alloc_skb(skb_len + headroom);
  4399. if (!skb)
  4400. goto no_mem;
  4401. if (headroom)
  4402. skb_reserve(skb, headroom);
  4403. }
  4404. data_ptr = element->addr + offset;
  4405. while (skb_len) {
  4406. data_len = min(skb_len, (int)(element->length - offset));
  4407. if (data_len) {
  4408. if (use_rx_sg) {
  4409. if (qeth_create_skb_frag(qethbuffer, element,
  4410. &skb, offset, &frag, data_len))
  4411. goto no_mem;
  4412. } else {
  4413. memcpy(skb_put(skb, data_len), data_ptr,
  4414. data_len);
  4415. }
  4416. }
  4417. skb_len -= data_len;
  4418. if (skb_len) {
  4419. if (qeth_is_last_sbale(element)) {
  4420. QETH_CARD_TEXT(card, 4, "unexeob");
  4421. QETH_CARD_HEX(card, 2, buffer, sizeof(void *));
  4422. dev_kfree_skb_any(skb);
  4423. card->stats.rx_errors++;
  4424. return NULL;
  4425. }
  4426. element++;
  4427. offset = 0;
  4428. data_ptr = element->addr;
  4429. } else {
  4430. offset += data_len;
  4431. }
  4432. }
  4433. *__element = element;
  4434. *__offset = offset;
  4435. if (use_rx_sg && card->options.performance_stats) {
  4436. card->perf_stats.sg_skbs_rx++;
  4437. card->perf_stats.sg_frags_rx += skb_shinfo(skb)->nr_frags;
  4438. }
  4439. return skb;
  4440. no_mem:
  4441. if (net_ratelimit()) {
  4442. QETH_CARD_TEXT(card, 2, "noskbmem");
  4443. }
  4444. card->stats.rx_dropped++;
  4445. return NULL;
  4446. }
  4447. EXPORT_SYMBOL_GPL(qeth_core_get_next_skb);
  4448. static void qeth_unregister_dbf_views(void)
  4449. {
  4450. int x;
  4451. for (x = 0; x < QETH_DBF_INFOS; x++) {
  4452. debug_unregister(qeth_dbf[x].id);
  4453. qeth_dbf[x].id = NULL;
  4454. }
  4455. }
  4456. void qeth_dbf_longtext(debug_info_t *id, int level, char *fmt, ...)
  4457. {
  4458. char dbf_txt_buf[32];
  4459. va_list args;
  4460. if (level > id->level)
  4461. return;
  4462. va_start(args, fmt);
  4463. vsnprintf(dbf_txt_buf, sizeof(dbf_txt_buf), fmt, args);
  4464. va_end(args);
  4465. debug_text_event(id, level, dbf_txt_buf);
  4466. }
  4467. EXPORT_SYMBOL_GPL(qeth_dbf_longtext);
  4468. static int qeth_register_dbf_views(void)
  4469. {
  4470. int ret;
  4471. int x;
  4472. for (x = 0; x < QETH_DBF_INFOS; x++) {
  4473. /* register the areas */
  4474. qeth_dbf[x].id = debug_register(qeth_dbf[x].name,
  4475. qeth_dbf[x].pages,
  4476. qeth_dbf[x].areas,
  4477. qeth_dbf[x].len);
  4478. if (qeth_dbf[x].id == NULL) {
  4479. qeth_unregister_dbf_views();
  4480. return -ENOMEM;
  4481. }
  4482. /* register a view */
  4483. ret = debug_register_view(qeth_dbf[x].id, qeth_dbf[x].view);
  4484. if (ret) {
  4485. qeth_unregister_dbf_views();
  4486. return ret;
  4487. }
  4488. /* set a passing level */
  4489. debug_set_level(qeth_dbf[x].id, qeth_dbf[x].level);
  4490. }
  4491. return 0;
  4492. }
  4493. int qeth_core_load_discipline(struct qeth_card *card,
  4494. enum qeth_discipline_id discipline)
  4495. {
  4496. int rc = 0;
  4497. mutex_lock(&qeth_mod_mutex);
  4498. switch (discipline) {
  4499. case QETH_DISCIPLINE_LAYER3:
  4500. card->discipline = try_then_request_module(
  4501. symbol_get(qeth_l3_discipline), "qeth_l3");
  4502. break;
  4503. case QETH_DISCIPLINE_LAYER2:
  4504. card->discipline = try_then_request_module(
  4505. symbol_get(qeth_l2_discipline), "qeth_l2");
  4506. break;
  4507. }
  4508. if (!card->discipline) {
  4509. dev_err(&card->gdev->dev, "There is no kernel module to "
  4510. "support discipline %d\n", discipline);
  4511. rc = -EINVAL;
  4512. }
  4513. mutex_unlock(&qeth_mod_mutex);
  4514. return rc;
  4515. }
  4516. void qeth_core_free_discipline(struct qeth_card *card)
  4517. {
  4518. if (card->options.layer2)
  4519. symbol_put(qeth_l2_discipline);
  4520. else
  4521. symbol_put(qeth_l3_discipline);
  4522. card->discipline = NULL;
  4523. }
  4524. static const struct device_type qeth_generic_devtype = {
  4525. .name = "qeth_generic",
  4526. .groups = qeth_generic_attr_groups,
  4527. };
  4528. static const struct device_type qeth_osn_devtype = {
  4529. .name = "qeth_osn",
  4530. .groups = qeth_osn_attr_groups,
  4531. };
  4532. static int qeth_core_probe_device(struct ccwgroup_device *gdev)
  4533. {
  4534. struct qeth_card *card;
  4535. struct device *dev;
  4536. int rc;
  4537. unsigned long flags;
  4538. char dbf_name[20];
  4539. QETH_DBF_TEXT(SETUP, 2, "probedev");
  4540. dev = &gdev->dev;
  4541. if (!get_device(dev))
  4542. return -ENODEV;
  4543. QETH_DBF_TEXT_(SETUP, 2, "%s", dev_name(&gdev->dev));
  4544. card = qeth_alloc_card();
  4545. if (!card) {
  4546. QETH_DBF_TEXT_(SETUP, 2, "1err%d", -ENOMEM);
  4547. rc = -ENOMEM;
  4548. goto err_dev;
  4549. }
  4550. snprintf(dbf_name, sizeof(dbf_name), "qeth_card_%s",
  4551. dev_name(&gdev->dev));
  4552. card->debug = debug_register(dbf_name, 2, 1, 8);
  4553. if (!card->debug) {
  4554. QETH_DBF_TEXT_(SETUP, 2, "%s", "qcdbf");
  4555. rc = -ENOMEM;
  4556. goto err_card;
  4557. }
  4558. debug_register_view(card->debug, &debug_hex_ascii_view);
  4559. card->read.ccwdev = gdev->cdev[0];
  4560. card->write.ccwdev = gdev->cdev[1];
  4561. card->data.ccwdev = gdev->cdev[2];
  4562. dev_set_drvdata(&gdev->dev, card);
  4563. card->gdev = gdev;
  4564. gdev->cdev[0]->handler = qeth_irq;
  4565. gdev->cdev[1]->handler = qeth_irq;
  4566. gdev->cdev[2]->handler = qeth_irq;
  4567. rc = qeth_determine_card_type(card);
  4568. if (rc) {
  4569. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  4570. goto err_dbf;
  4571. }
  4572. rc = qeth_setup_card(card);
  4573. if (rc) {
  4574. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  4575. goto err_dbf;
  4576. }
  4577. if (card->info.type == QETH_CARD_TYPE_OSN)
  4578. gdev->dev.type = &qeth_osn_devtype;
  4579. else
  4580. gdev->dev.type = &qeth_generic_devtype;
  4581. switch (card->info.type) {
  4582. case QETH_CARD_TYPE_OSN:
  4583. case QETH_CARD_TYPE_OSM:
  4584. rc = qeth_core_load_discipline(card, QETH_DISCIPLINE_LAYER2);
  4585. if (rc)
  4586. goto err_dbf;
  4587. rc = card->discipline->setup(card->gdev);
  4588. if (rc)
  4589. goto err_disc;
  4590. case QETH_CARD_TYPE_OSD:
  4591. case QETH_CARD_TYPE_OSX:
  4592. default:
  4593. break;
  4594. }
  4595. write_lock_irqsave(&qeth_core_card_list.rwlock, flags);
  4596. list_add_tail(&card->list, &qeth_core_card_list.list);
  4597. write_unlock_irqrestore(&qeth_core_card_list.rwlock, flags);
  4598. qeth_determine_capabilities(card);
  4599. return 0;
  4600. err_disc:
  4601. qeth_core_free_discipline(card);
  4602. err_dbf:
  4603. debug_unregister(card->debug);
  4604. err_card:
  4605. qeth_core_free_card(card);
  4606. err_dev:
  4607. put_device(dev);
  4608. return rc;
  4609. }
  4610. static void qeth_core_remove_device(struct ccwgroup_device *gdev)
  4611. {
  4612. unsigned long flags;
  4613. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  4614. QETH_DBF_TEXT(SETUP, 2, "removedv");
  4615. if (card->discipline) {
  4616. card->discipline->remove(gdev);
  4617. qeth_core_free_discipline(card);
  4618. }
  4619. debug_unregister(card->debug);
  4620. write_lock_irqsave(&qeth_core_card_list.rwlock, flags);
  4621. list_del(&card->list);
  4622. write_unlock_irqrestore(&qeth_core_card_list.rwlock, flags);
  4623. qeth_core_free_card(card);
  4624. dev_set_drvdata(&gdev->dev, NULL);
  4625. put_device(&gdev->dev);
  4626. return;
  4627. }
  4628. static int qeth_core_set_online(struct ccwgroup_device *gdev)
  4629. {
  4630. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  4631. int rc = 0;
  4632. int def_discipline;
  4633. if (!card->discipline) {
  4634. if (card->info.type == QETH_CARD_TYPE_IQD)
  4635. def_discipline = QETH_DISCIPLINE_LAYER3;
  4636. else
  4637. def_discipline = QETH_DISCIPLINE_LAYER2;
  4638. rc = qeth_core_load_discipline(card, def_discipline);
  4639. if (rc)
  4640. goto err;
  4641. rc = card->discipline->setup(card->gdev);
  4642. if (rc)
  4643. goto err;
  4644. }
  4645. rc = card->discipline->set_online(gdev);
  4646. err:
  4647. return rc;
  4648. }
  4649. static int qeth_core_set_offline(struct ccwgroup_device *gdev)
  4650. {
  4651. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  4652. return card->discipline->set_offline(gdev);
  4653. }
  4654. static void qeth_core_shutdown(struct ccwgroup_device *gdev)
  4655. {
  4656. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  4657. if (card->discipline && card->discipline->shutdown)
  4658. card->discipline->shutdown(gdev);
  4659. }
  4660. static int qeth_core_prepare(struct ccwgroup_device *gdev)
  4661. {
  4662. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  4663. if (card->discipline && card->discipline->prepare)
  4664. return card->discipline->prepare(gdev);
  4665. return 0;
  4666. }
  4667. static void qeth_core_complete(struct ccwgroup_device *gdev)
  4668. {
  4669. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  4670. if (card->discipline && card->discipline->complete)
  4671. card->discipline->complete(gdev);
  4672. }
  4673. static int qeth_core_freeze(struct ccwgroup_device *gdev)
  4674. {
  4675. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  4676. if (card->discipline && card->discipline->freeze)
  4677. return card->discipline->freeze(gdev);
  4678. return 0;
  4679. }
  4680. static int qeth_core_thaw(struct ccwgroup_device *gdev)
  4681. {
  4682. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  4683. if (card->discipline && card->discipline->thaw)
  4684. return card->discipline->thaw(gdev);
  4685. return 0;
  4686. }
  4687. static int qeth_core_restore(struct ccwgroup_device *gdev)
  4688. {
  4689. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  4690. if (card->discipline && card->discipline->restore)
  4691. return card->discipline->restore(gdev);
  4692. return 0;
  4693. }
  4694. static struct ccwgroup_driver qeth_core_ccwgroup_driver = {
  4695. .driver = {
  4696. .owner = THIS_MODULE,
  4697. .name = "qeth",
  4698. },
  4699. .setup = qeth_core_probe_device,
  4700. .remove = qeth_core_remove_device,
  4701. .set_online = qeth_core_set_online,
  4702. .set_offline = qeth_core_set_offline,
  4703. .shutdown = qeth_core_shutdown,
  4704. .prepare = qeth_core_prepare,
  4705. .complete = qeth_core_complete,
  4706. .freeze = qeth_core_freeze,
  4707. .thaw = qeth_core_thaw,
  4708. .restore = qeth_core_restore,
  4709. };
  4710. static ssize_t qeth_core_driver_group_store(struct device_driver *ddrv,
  4711. const char *buf, size_t count)
  4712. {
  4713. int err;
  4714. err = ccwgroup_create_dev(qeth_core_root_dev,
  4715. &qeth_core_ccwgroup_driver, 3, buf);
  4716. return err ? err : count;
  4717. }
  4718. static DRIVER_ATTR(group, 0200, NULL, qeth_core_driver_group_store);
  4719. static struct attribute *qeth_drv_attrs[] = {
  4720. &driver_attr_group.attr,
  4721. NULL,
  4722. };
  4723. static struct attribute_group qeth_drv_attr_group = {
  4724. .attrs = qeth_drv_attrs,
  4725. };
  4726. static const struct attribute_group *qeth_drv_attr_groups[] = {
  4727. &qeth_drv_attr_group,
  4728. NULL,
  4729. };
  4730. static struct {
  4731. const char str[ETH_GSTRING_LEN];
  4732. } qeth_ethtool_stats_keys[] = {
  4733. /* 0 */{"rx skbs"},
  4734. {"rx buffers"},
  4735. {"tx skbs"},
  4736. {"tx buffers"},
  4737. {"tx skbs no packing"},
  4738. {"tx buffers no packing"},
  4739. {"tx skbs packing"},
  4740. {"tx buffers packing"},
  4741. {"tx sg skbs"},
  4742. {"tx sg frags"},
  4743. /* 10 */{"rx sg skbs"},
  4744. {"rx sg frags"},
  4745. {"rx sg page allocs"},
  4746. {"tx large kbytes"},
  4747. {"tx large count"},
  4748. {"tx pk state ch n->p"},
  4749. {"tx pk state ch p->n"},
  4750. {"tx pk watermark low"},
  4751. {"tx pk watermark high"},
  4752. {"queue 0 buffer usage"},
  4753. /* 20 */{"queue 1 buffer usage"},
  4754. {"queue 2 buffer usage"},
  4755. {"queue 3 buffer usage"},
  4756. {"rx poll time"},
  4757. {"rx poll count"},
  4758. {"rx do_QDIO time"},
  4759. {"rx do_QDIO count"},
  4760. {"tx handler time"},
  4761. {"tx handler count"},
  4762. {"tx time"},
  4763. /* 30 */{"tx count"},
  4764. {"tx do_QDIO time"},
  4765. {"tx do_QDIO count"},
  4766. {"tx csum"},
  4767. {"tx lin"},
  4768. {"cq handler count"},
  4769. {"cq handler time"}
  4770. };
  4771. int qeth_core_get_sset_count(struct net_device *dev, int stringset)
  4772. {
  4773. switch (stringset) {
  4774. case ETH_SS_STATS:
  4775. return (sizeof(qeth_ethtool_stats_keys) / ETH_GSTRING_LEN);
  4776. default:
  4777. return -EINVAL;
  4778. }
  4779. }
  4780. EXPORT_SYMBOL_GPL(qeth_core_get_sset_count);
  4781. void qeth_core_get_ethtool_stats(struct net_device *dev,
  4782. struct ethtool_stats *stats, u64 *data)
  4783. {
  4784. struct qeth_card *card = dev->ml_priv;
  4785. data[0] = card->stats.rx_packets -
  4786. card->perf_stats.initial_rx_packets;
  4787. data[1] = card->perf_stats.bufs_rec;
  4788. data[2] = card->stats.tx_packets -
  4789. card->perf_stats.initial_tx_packets;
  4790. data[3] = card->perf_stats.bufs_sent;
  4791. data[4] = card->stats.tx_packets - card->perf_stats.initial_tx_packets
  4792. - card->perf_stats.skbs_sent_pack;
  4793. data[5] = card->perf_stats.bufs_sent - card->perf_stats.bufs_sent_pack;
  4794. data[6] = card->perf_stats.skbs_sent_pack;
  4795. data[7] = card->perf_stats.bufs_sent_pack;
  4796. data[8] = card->perf_stats.sg_skbs_sent;
  4797. data[9] = card->perf_stats.sg_frags_sent;
  4798. data[10] = card->perf_stats.sg_skbs_rx;
  4799. data[11] = card->perf_stats.sg_frags_rx;
  4800. data[12] = card->perf_stats.sg_alloc_page_rx;
  4801. data[13] = (card->perf_stats.large_send_bytes >> 10);
  4802. data[14] = card->perf_stats.large_send_cnt;
  4803. data[15] = card->perf_stats.sc_dp_p;
  4804. data[16] = card->perf_stats.sc_p_dp;
  4805. data[17] = QETH_LOW_WATERMARK_PACK;
  4806. data[18] = QETH_HIGH_WATERMARK_PACK;
  4807. data[19] = atomic_read(&card->qdio.out_qs[0]->used_buffers);
  4808. data[20] = (card->qdio.no_out_queues > 1) ?
  4809. atomic_read(&card->qdio.out_qs[1]->used_buffers) : 0;
  4810. data[21] = (card->qdio.no_out_queues > 2) ?
  4811. atomic_read(&card->qdio.out_qs[2]->used_buffers) : 0;
  4812. data[22] = (card->qdio.no_out_queues > 3) ?
  4813. atomic_read(&card->qdio.out_qs[3]->used_buffers) : 0;
  4814. data[23] = card->perf_stats.inbound_time;
  4815. data[24] = card->perf_stats.inbound_cnt;
  4816. data[25] = card->perf_stats.inbound_do_qdio_time;
  4817. data[26] = card->perf_stats.inbound_do_qdio_cnt;
  4818. data[27] = card->perf_stats.outbound_handler_time;
  4819. data[28] = card->perf_stats.outbound_handler_cnt;
  4820. data[29] = card->perf_stats.outbound_time;
  4821. data[30] = card->perf_stats.outbound_cnt;
  4822. data[31] = card->perf_stats.outbound_do_qdio_time;
  4823. data[32] = card->perf_stats.outbound_do_qdio_cnt;
  4824. data[33] = card->perf_stats.tx_csum;
  4825. data[34] = card->perf_stats.tx_lin;
  4826. data[35] = card->perf_stats.cq_cnt;
  4827. data[36] = card->perf_stats.cq_time;
  4828. }
  4829. EXPORT_SYMBOL_GPL(qeth_core_get_ethtool_stats);
  4830. void qeth_core_get_strings(struct net_device *dev, u32 stringset, u8 *data)
  4831. {
  4832. switch (stringset) {
  4833. case ETH_SS_STATS:
  4834. memcpy(data, &qeth_ethtool_stats_keys,
  4835. sizeof(qeth_ethtool_stats_keys));
  4836. break;
  4837. default:
  4838. WARN_ON(1);
  4839. break;
  4840. }
  4841. }
  4842. EXPORT_SYMBOL_GPL(qeth_core_get_strings);
  4843. void qeth_core_get_drvinfo(struct net_device *dev,
  4844. struct ethtool_drvinfo *info)
  4845. {
  4846. struct qeth_card *card = dev->ml_priv;
  4847. if (card->options.layer2)
  4848. strcpy(info->driver, "qeth_l2");
  4849. else
  4850. strcpy(info->driver, "qeth_l3");
  4851. strcpy(info->version, "1.0");
  4852. strcpy(info->fw_version, card->info.mcl_level);
  4853. sprintf(info->bus_info, "%s/%s/%s",
  4854. CARD_RDEV_ID(card),
  4855. CARD_WDEV_ID(card),
  4856. CARD_DDEV_ID(card));
  4857. }
  4858. EXPORT_SYMBOL_GPL(qeth_core_get_drvinfo);
  4859. int qeth_core_ethtool_get_settings(struct net_device *netdev,
  4860. struct ethtool_cmd *ecmd)
  4861. {
  4862. struct qeth_card *card = netdev->ml_priv;
  4863. enum qeth_link_types link_type;
  4864. if ((card->info.type == QETH_CARD_TYPE_IQD) || (card->info.guestlan))
  4865. link_type = QETH_LINK_TYPE_10GBIT_ETH;
  4866. else
  4867. link_type = card->info.link_type;
  4868. ecmd->transceiver = XCVR_INTERNAL;
  4869. ecmd->supported = SUPPORTED_Autoneg;
  4870. ecmd->advertising = ADVERTISED_Autoneg;
  4871. ecmd->duplex = DUPLEX_FULL;
  4872. ecmd->autoneg = AUTONEG_ENABLE;
  4873. switch (link_type) {
  4874. case QETH_LINK_TYPE_FAST_ETH:
  4875. case QETH_LINK_TYPE_LANE_ETH100:
  4876. ecmd->supported |= SUPPORTED_10baseT_Half |
  4877. SUPPORTED_10baseT_Full |
  4878. SUPPORTED_100baseT_Half |
  4879. SUPPORTED_100baseT_Full |
  4880. SUPPORTED_TP;
  4881. ecmd->advertising |= ADVERTISED_10baseT_Half |
  4882. ADVERTISED_10baseT_Full |
  4883. ADVERTISED_100baseT_Half |
  4884. ADVERTISED_100baseT_Full |
  4885. ADVERTISED_TP;
  4886. ecmd->speed = SPEED_100;
  4887. ecmd->port = PORT_TP;
  4888. break;
  4889. case QETH_LINK_TYPE_GBIT_ETH:
  4890. case QETH_LINK_TYPE_LANE_ETH1000:
  4891. ecmd->supported |= SUPPORTED_10baseT_Half |
  4892. SUPPORTED_10baseT_Full |
  4893. SUPPORTED_100baseT_Half |
  4894. SUPPORTED_100baseT_Full |
  4895. SUPPORTED_1000baseT_Half |
  4896. SUPPORTED_1000baseT_Full |
  4897. SUPPORTED_FIBRE;
  4898. ecmd->advertising |= ADVERTISED_10baseT_Half |
  4899. ADVERTISED_10baseT_Full |
  4900. ADVERTISED_100baseT_Half |
  4901. ADVERTISED_100baseT_Full |
  4902. ADVERTISED_1000baseT_Half |
  4903. ADVERTISED_1000baseT_Full |
  4904. ADVERTISED_FIBRE;
  4905. ecmd->speed = SPEED_1000;
  4906. ecmd->port = PORT_FIBRE;
  4907. break;
  4908. case QETH_LINK_TYPE_10GBIT_ETH:
  4909. ecmd->supported |= SUPPORTED_10baseT_Half |
  4910. SUPPORTED_10baseT_Full |
  4911. SUPPORTED_100baseT_Half |
  4912. SUPPORTED_100baseT_Full |
  4913. SUPPORTED_1000baseT_Half |
  4914. SUPPORTED_1000baseT_Full |
  4915. SUPPORTED_10000baseT_Full |
  4916. SUPPORTED_FIBRE;
  4917. ecmd->advertising |= ADVERTISED_10baseT_Half |
  4918. ADVERTISED_10baseT_Full |
  4919. ADVERTISED_100baseT_Half |
  4920. ADVERTISED_100baseT_Full |
  4921. ADVERTISED_1000baseT_Half |
  4922. ADVERTISED_1000baseT_Full |
  4923. ADVERTISED_10000baseT_Full |
  4924. ADVERTISED_FIBRE;
  4925. ecmd->speed = SPEED_10000;
  4926. ecmd->port = PORT_FIBRE;
  4927. break;
  4928. default:
  4929. ecmd->supported |= SUPPORTED_10baseT_Half |
  4930. SUPPORTED_10baseT_Full |
  4931. SUPPORTED_TP;
  4932. ecmd->advertising |= ADVERTISED_10baseT_Half |
  4933. ADVERTISED_10baseT_Full |
  4934. ADVERTISED_TP;
  4935. ecmd->speed = SPEED_10;
  4936. ecmd->port = PORT_TP;
  4937. }
  4938. return 0;
  4939. }
  4940. EXPORT_SYMBOL_GPL(qeth_core_ethtool_get_settings);
  4941. static int __init qeth_core_init(void)
  4942. {
  4943. int rc;
  4944. pr_info("loading core functions\n");
  4945. INIT_LIST_HEAD(&qeth_core_card_list.list);
  4946. rwlock_init(&qeth_core_card_list.rwlock);
  4947. mutex_init(&qeth_mod_mutex);
  4948. rc = qeth_register_dbf_views();
  4949. if (rc)
  4950. goto out_err;
  4951. qeth_core_root_dev = root_device_register("qeth");
  4952. rc = IS_ERR(qeth_core_root_dev) ? PTR_ERR(qeth_core_root_dev) : 0;
  4953. if (rc)
  4954. goto register_err;
  4955. qeth_core_header_cache = kmem_cache_create("qeth_hdr",
  4956. sizeof(struct qeth_hdr) + ETH_HLEN, 64, 0, NULL);
  4957. if (!qeth_core_header_cache) {
  4958. rc = -ENOMEM;
  4959. goto slab_err;
  4960. }
  4961. qeth_qdio_outbuf_cache = kmem_cache_create("qeth_buf",
  4962. sizeof(struct qeth_qdio_out_buffer), 0, 0, NULL);
  4963. if (!qeth_qdio_outbuf_cache) {
  4964. rc = -ENOMEM;
  4965. goto cqslab_err;
  4966. }
  4967. rc = ccw_driver_register(&qeth_ccw_driver);
  4968. if (rc)
  4969. goto ccw_err;
  4970. qeth_core_ccwgroup_driver.driver.groups = qeth_drv_attr_groups;
  4971. rc = ccwgroup_driver_register(&qeth_core_ccwgroup_driver);
  4972. if (rc)
  4973. goto ccwgroup_err;
  4974. return 0;
  4975. ccwgroup_err:
  4976. ccw_driver_unregister(&qeth_ccw_driver);
  4977. ccw_err:
  4978. kmem_cache_destroy(qeth_qdio_outbuf_cache);
  4979. cqslab_err:
  4980. kmem_cache_destroy(qeth_core_header_cache);
  4981. slab_err:
  4982. root_device_unregister(qeth_core_root_dev);
  4983. register_err:
  4984. qeth_unregister_dbf_views();
  4985. out_err:
  4986. pr_err("Initializing the qeth device driver failed\n");
  4987. return rc;
  4988. }
  4989. static void __exit qeth_core_exit(void)
  4990. {
  4991. ccwgroup_driver_unregister(&qeth_core_ccwgroup_driver);
  4992. ccw_driver_unregister(&qeth_ccw_driver);
  4993. kmem_cache_destroy(qeth_qdio_outbuf_cache);
  4994. kmem_cache_destroy(qeth_core_header_cache);
  4995. root_device_unregister(qeth_core_root_dev);
  4996. qeth_unregister_dbf_views();
  4997. pr_info("core functions removed\n");
  4998. }
  4999. module_init(qeth_core_init);
  5000. module_exit(qeth_core_exit);
  5001. MODULE_AUTHOR("Frank Blaschka <frank.blaschka@de.ibm.com>");
  5002. MODULE_DESCRIPTION("qeth core functions");
  5003. MODULE_LICENSE("GPL");