pn544_hci.c 22 KB

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  1. /*
  2. * HCI based Driver for NXP PN544 NFC Chip
  3. *
  4. * Copyright (C) 2012 Intel Corporation. All rights reserved.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms and conditions of the GNU General Public License,
  8. * version 2, as published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the
  17. * Free Software Foundation, Inc.,
  18. * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19. */
  20. #include <linux/crc-ccitt.h>
  21. #include <linux/module.h>
  22. #include <linux/delay.h>
  23. #include <linux/slab.h>
  24. #include <linux/miscdevice.h>
  25. #include <linux/interrupt.h>
  26. #include <linux/gpio.h>
  27. #include <linux/i2c.h>
  28. #include <linux/nfc.h>
  29. #include <net/nfc/hci.h>
  30. #include <net/nfc/shdlc.h>
  31. #include <linux/nfc/pn544.h>
  32. #define DRIVER_DESC "HCI NFC driver for PN544"
  33. #define PN544_HCI_DRIVER_NAME "pn544_hci"
  34. /* Timing restrictions (ms) */
  35. #define PN544_HCI_RESETVEN_TIME 30
  36. static struct i2c_device_id pn544_hci_id_table[] = {
  37. {"pn544", 0},
  38. {}
  39. };
  40. MODULE_DEVICE_TABLE(i2c, pn544_hci_id_table);
  41. #define HCI_MODE 0
  42. #define FW_MODE 1
  43. /* framing in HCI mode */
  44. #define PN544_HCI_LLC_LEN 1
  45. #define PN544_HCI_LLC_CRC 2
  46. #define PN544_HCI_LLC_LEN_CRC (PN544_HCI_LLC_LEN + PN544_HCI_LLC_CRC)
  47. #define PN544_HCI_LLC_MIN_SIZE (1 + PN544_HCI_LLC_LEN_CRC)
  48. #define PN544_HCI_LLC_MAX_PAYLOAD 29
  49. #define PN544_HCI_LLC_MAX_SIZE (PN544_HCI_LLC_LEN_CRC + 1 + \
  50. PN544_HCI_LLC_MAX_PAYLOAD)
  51. enum pn544_state {
  52. PN544_ST_COLD,
  53. PN544_ST_FW_READY,
  54. PN544_ST_READY,
  55. };
  56. #define FULL_VERSION_LEN 11
  57. /* Proprietary commands */
  58. #define PN544_WRITE 0x3f
  59. /* Proprietary gates, events, commands and registers */
  60. /* NFC_HCI_RF_READER_A_GATE additional registers and commands */
  61. #define PN544_RF_READER_A_AUTO_ACTIVATION 0x10
  62. #define PN544_RF_READER_A_CMD_CONTINUE_ACTIVATION 0x12
  63. #define PN544_MIFARE_CMD 0x21
  64. /* Commands that apply to all RF readers */
  65. #define PN544_RF_READER_CMD_PRESENCE_CHECK 0x30
  66. #define PN544_RF_READER_CMD_ACTIVATE_NEXT 0x32
  67. /* NFC_HCI_ID_MGMT_GATE additional registers */
  68. #define PN544_ID_MGMT_FULL_VERSION_SW 0x10
  69. #define PN544_RF_READER_ISO15693_GATE 0x12
  70. #define PN544_RF_READER_F_GATE 0x14
  71. #define PN544_FELICA_ID 0x04
  72. #define PN544_FELICA_RAW 0x20
  73. #define PN544_RF_READER_JEWEL_GATE 0x15
  74. #define PN544_JEWEL_RAW_CMD 0x23
  75. #define PN544_RF_READER_NFCIP1_INITIATOR_GATE 0x30
  76. #define PN544_RF_READER_NFCIP1_TARGET_GATE 0x31
  77. #define PN544_SYS_MGMT_GATE 0x90
  78. #define PN544_SYS_MGMT_INFO_NOTIFICATION 0x02
  79. #define PN544_POLLING_LOOP_MGMT_GATE 0x94
  80. #define PN544_PL_RDPHASES 0x06
  81. #define PN544_PL_EMULATION 0x07
  82. #define PN544_PL_NFCT_DEACTIVATED 0x09
  83. #define PN544_SWP_MGMT_GATE 0xA0
  84. #define PN544_NFC_WI_MGMT_GATE 0xA1
  85. static u8 pn544_custom_gates[] = {
  86. PN544_SYS_MGMT_GATE,
  87. PN544_SWP_MGMT_GATE,
  88. PN544_POLLING_LOOP_MGMT_GATE,
  89. PN544_NFC_WI_MGMT_GATE,
  90. PN544_RF_READER_F_GATE,
  91. PN544_RF_READER_JEWEL_GATE,
  92. PN544_RF_READER_ISO15693_GATE,
  93. PN544_RF_READER_NFCIP1_INITIATOR_GATE,
  94. PN544_RF_READER_NFCIP1_TARGET_GATE
  95. };
  96. /* Largest headroom needed for outgoing custom commands */
  97. #define PN544_CMDS_HEADROOM 2
  98. struct pn544_hci_info {
  99. struct i2c_client *i2c_dev;
  100. struct nfc_shdlc *shdlc;
  101. enum pn544_state state;
  102. struct mutex info_lock;
  103. unsigned int gpio_en;
  104. unsigned int gpio_irq;
  105. unsigned int gpio_fw;
  106. unsigned int en_polarity;
  107. int hard_fault; /*
  108. * < 0 if hardware error occured (e.g. i2c err)
  109. * and prevents normal operation.
  110. */
  111. };
  112. static void pn544_hci_platform_init(struct pn544_hci_info *info)
  113. {
  114. int polarity, retry, ret;
  115. char rset_cmd[] = { 0x05, 0xF9, 0x04, 0x00, 0xC3, 0xE5 };
  116. int count = sizeof(rset_cmd);
  117. pr_info(DRIVER_DESC ": %s\n", __func__);
  118. dev_info(&info->i2c_dev->dev, "Detecting nfc_en polarity\n");
  119. /* Disable fw download */
  120. gpio_set_value(info->gpio_fw, 0);
  121. for (polarity = 0; polarity < 2; polarity++) {
  122. info->en_polarity = polarity;
  123. retry = 3;
  124. while (retry--) {
  125. /* power off */
  126. gpio_set_value(info->gpio_en, !info->en_polarity);
  127. usleep_range(10000, 15000);
  128. /* power on */
  129. gpio_set_value(info->gpio_en, info->en_polarity);
  130. usleep_range(10000, 15000);
  131. /* send reset */
  132. dev_dbg(&info->i2c_dev->dev, "Sending reset cmd\n");
  133. ret = i2c_master_send(info->i2c_dev, rset_cmd, count);
  134. if (ret == count) {
  135. dev_info(&info->i2c_dev->dev,
  136. "nfc_en polarity : active %s\n",
  137. (polarity == 0 ? "low" : "high"));
  138. goto out;
  139. }
  140. }
  141. }
  142. dev_err(&info->i2c_dev->dev,
  143. "Could not detect nfc_en polarity, fallback to active high\n");
  144. out:
  145. gpio_set_value(info->gpio_en, !info->en_polarity);
  146. }
  147. static int pn544_hci_enable(struct pn544_hci_info *info, int mode)
  148. {
  149. pr_info(DRIVER_DESC ": %s\n", __func__);
  150. gpio_set_value(info->gpio_fw, 0);
  151. gpio_set_value(info->gpio_en, info->en_polarity);
  152. usleep_range(10000, 15000);
  153. return 0;
  154. }
  155. static void pn544_hci_disable(struct pn544_hci_info *info)
  156. {
  157. pr_info(DRIVER_DESC ": %s\n", __func__);
  158. gpio_set_value(info->gpio_fw, 0);
  159. gpio_set_value(info->gpio_en, !info->en_polarity);
  160. usleep_range(10000, 15000);
  161. gpio_set_value(info->gpio_en, info->en_polarity);
  162. usleep_range(10000, 15000);
  163. gpio_set_value(info->gpio_en, !info->en_polarity);
  164. usleep_range(10000, 15000);
  165. }
  166. static int pn544_hci_i2c_write(struct i2c_client *client, u8 *buf, int len)
  167. {
  168. int r;
  169. usleep_range(3000, 6000);
  170. r = i2c_master_send(client, buf, len);
  171. if (r == -EREMOTEIO) { /* Retry, chip was in standby */
  172. usleep_range(6000, 10000);
  173. r = i2c_master_send(client, buf, len);
  174. }
  175. if (r >= 0 && r != len)
  176. r = -EREMOTEIO;
  177. return r;
  178. }
  179. static int check_crc(u8 *buf, int buflen)
  180. {
  181. int len;
  182. u16 crc;
  183. len = buf[0] + 1;
  184. crc = crc_ccitt(0xffff, buf, len - 2);
  185. crc = ~crc;
  186. if (buf[len - 2] != (crc & 0xff) || buf[len - 1] != (crc >> 8)) {
  187. pr_err(PN544_HCI_DRIVER_NAME ": CRC error 0x%x != 0x%x 0x%x\n",
  188. crc, buf[len - 1], buf[len - 2]);
  189. pr_info(DRIVER_DESC ": %s : BAD CRC\n", __func__);
  190. print_hex_dump(KERN_DEBUG, "crc: ", DUMP_PREFIX_NONE,
  191. 16, 2, buf, buflen, false);
  192. return -EPERM;
  193. }
  194. return 0;
  195. }
  196. /*
  197. * Reads an shdlc frame and returns it in a newly allocated sk_buff. Guarantees
  198. * that i2c bus will be flushed and that next read will start on a new frame.
  199. * returned skb contains only LLC header and payload.
  200. * returns:
  201. * -EREMOTEIO : i2c read error (fatal)
  202. * -EBADMSG : frame was incorrect and discarded
  203. * -ENOMEM : cannot allocate skb, frame dropped
  204. */
  205. static int pn544_hci_i2c_read(struct i2c_client *client, struct sk_buff **skb)
  206. {
  207. int r;
  208. u8 len;
  209. u8 tmp[PN544_HCI_LLC_MAX_SIZE - 1];
  210. r = i2c_master_recv(client, &len, 1);
  211. if (r != 1) {
  212. dev_err(&client->dev, "cannot read len byte\n");
  213. return -EREMOTEIO;
  214. }
  215. if ((len < (PN544_HCI_LLC_MIN_SIZE - 1)) ||
  216. (len > (PN544_HCI_LLC_MAX_SIZE - 1))) {
  217. dev_err(&client->dev, "invalid len byte\n");
  218. r = -EBADMSG;
  219. goto flush;
  220. }
  221. *skb = alloc_skb(1 + len, GFP_KERNEL);
  222. if (*skb == NULL) {
  223. r = -ENOMEM;
  224. goto flush;
  225. }
  226. *skb_put(*skb, 1) = len;
  227. r = i2c_master_recv(client, skb_put(*skb, len), len);
  228. if (r != len) {
  229. kfree_skb(*skb);
  230. return -EREMOTEIO;
  231. }
  232. r = check_crc((*skb)->data, (*skb)->len);
  233. if (r != 0) {
  234. kfree_skb(*skb);
  235. r = -EBADMSG;
  236. goto flush;
  237. }
  238. skb_pull(*skb, 1);
  239. skb_trim(*skb, (*skb)->len - 2);
  240. usleep_range(3000, 6000);
  241. return 0;
  242. flush:
  243. if (i2c_master_recv(client, tmp, sizeof(tmp)) < 0)
  244. r = -EREMOTEIO;
  245. usleep_range(3000, 6000);
  246. return r;
  247. }
  248. /*
  249. * Reads an shdlc frame from the chip. This is not as straightforward as it
  250. * seems. There are cases where we could loose the frame start synchronization.
  251. * The frame format is len-data-crc, and corruption can occur anywhere while
  252. * transiting on i2c bus, such that we could read an invalid len.
  253. * In order to recover synchronization with the next frame, we must be sure
  254. * to read the real amount of data without using the len byte. We do this by
  255. * assuming the following:
  256. * - the chip will always present only one single complete frame on the bus
  257. * before triggering the interrupt
  258. * - the chip will not present a new frame until we have completely read
  259. * the previous one (or until we have handled the interrupt).
  260. * The tricky case is when we read a corrupted len that is less than the real
  261. * len. We must detect this here in order to determine that we need to flush
  262. * the bus. This is the reason why we check the crc here.
  263. */
  264. static irqreturn_t pn544_hci_irq_thread_fn(int irq, void *dev_id)
  265. {
  266. struct pn544_hci_info *info = dev_id;
  267. struct i2c_client *client = info->i2c_dev;
  268. struct sk_buff *skb = NULL;
  269. int r;
  270. BUG_ON(!info);
  271. BUG_ON(irq != info->i2c_dev->irq);
  272. dev_dbg(&client->dev, "IRQ\n");
  273. if (info->hard_fault != 0)
  274. return IRQ_HANDLED;
  275. r = pn544_hci_i2c_read(client, &skb);
  276. if (r == -EREMOTEIO) {
  277. info->hard_fault = r;
  278. nfc_shdlc_recv_frame(info->shdlc, NULL);
  279. return IRQ_HANDLED;
  280. } else if ((r == -ENOMEM) || (r == -EBADMSG)) {
  281. return IRQ_HANDLED;
  282. }
  283. nfc_shdlc_recv_frame(info->shdlc, skb);
  284. return IRQ_HANDLED;
  285. }
  286. static int pn544_hci_open(struct nfc_shdlc *shdlc)
  287. {
  288. struct pn544_hci_info *info = nfc_shdlc_get_clientdata(shdlc);
  289. int r = 0;
  290. mutex_lock(&info->info_lock);
  291. if (info->state != PN544_ST_COLD) {
  292. r = -EBUSY;
  293. goto out;
  294. }
  295. r = pn544_hci_enable(info, HCI_MODE);
  296. out:
  297. mutex_unlock(&info->info_lock);
  298. return r;
  299. }
  300. static void pn544_hci_close(struct nfc_shdlc *shdlc)
  301. {
  302. struct pn544_hci_info *info = nfc_shdlc_get_clientdata(shdlc);
  303. mutex_lock(&info->info_lock);
  304. if (info->state == PN544_ST_COLD)
  305. goto out;
  306. pn544_hci_disable(info);
  307. out:
  308. mutex_unlock(&info->info_lock);
  309. }
  310. static int pn544_hci_ready(struct nfc_shdlc *shdlc)
  311. {
  312. struct nfc_hci_dev *hdev = nfc_shdlc_get_hci_dev(shdlc);
  313. struct sk_buff *skb;
  314. static struct hw_config {
  315. u8 adr[2];
  316. u8 value;
  317. } hw_config[] = {
  318. {{0x9f, 0x9a}, 0x00},
  319. {{0x98, 0x10}, 0xbc},
  320. {{0x9e, 0x71}, 0x00},
  321. {{0x98, 0x09}, 0x00},
  322. {{0x9e, 0xb4}, 0x00},
  323. {{0x9e, 0xd9}, 0xff},
  324. {{0x9e, 0xda}, 0xff},
  325. {{0x9e, 0xdb}, 0x23},
  326. {{0x9e, 0xdc}, 0x21},
  327. {{0x9e, 0xdd}, 0x22},
  328. {{0x9e, 0xde}, 0x24},
  329. {{0x9c, 0x01}, 0x08},
  330. {{0x9e, 0xaa}, 0x01},
  331. {{0x9b, 0xd1}, 0x0d},
  332. {{0x9b, 0xd2}, 0x24},
  333. {{0x9b, 0xd3}, 0x0a},
  334. {{0x9b, 0xd4}, 0x22},
  335. {{0x9b, 0xd5}, 0x08},
  336. {{0x9b, 0xd6}, 0x1e},
  337. {{0x9b, 0xdd}, 0x1c},
  338. {{0x9b, 0x84}, 0x13},
  339. {{0x99, 0x81}, 0x7f},
  340. {{0x99, 0x31}, 0x70},
  341. {{0x98, 0x00}, 0x3f},
  342. {{0x9f, 0x09}, 0x00},
  343. {{0x9f, 0x0a}, 0x05},
  344. {{0x9e, 0xd1}, 0xa1},
  345. {{0x99, 0x23}, 0x00},
  346. {{0x9e, 0x74}, 0x80},
  347. {{0x9f, 0x28}, 0x10},
  348. {{0x9f, 0x35}, 0x14},
  349. {{0x9f, 0x36}, 0x60},
  350. {{0x9c, 0x31}, 0x00},
  351. {{0x9c, 0x32}, 0xc8},
  352. {{0x9c, 0x19}, 0x40},
  353. {{0x9c, 0x1a}, 0x40},
  354. {{0x9c, 0x0c}, 0x00},
  355. {{0x9c, 0x0d}, 0x00},
  356. {{0x9c, 0x12}, 0x00},
  357. {{0x9c, 0x13}, 0x00},
  358. {{0x98, 0xa2}, 0x0e},
  359. {{0x98, 0x93}, 0x40},
  360. {{0x98, 0x7d}, 0x02},
  361. {{0x98, 0x7e}, 0x00},
  362. {{0x9f, 0xc8}, 0x01},
  363. };
  364. struct hw_config *p = hw_config;
  365. int count = ARRAY_SIZE(hw_config);
  366. struct sk_buff *res_skb;
  367. u8 param[4];
  368. int r;
  369. param[0] = 0;
  370. while (count--) {
  371. param[1] = p->adr[0];
  372. param[2] = p->adr[1];
  373. param[3] = p->value;
  374. r = nfc_hci_send_cmd(hdev, PN544_SYS_MGMT_GATE, PN544_WRITE,
  375. param, 4, &res_skb);
  376. if (r < 0)
  377. return r;
  378. if (res_skb->len != 1) {
  379. kfree_skb(res_skb);
  380. return -EPROTO;
  381. }
  382. if (res_skb->data[0] != p->value) {
  383. kfree_skb(res_skb);
  384. return -EIO;
  385. }
  386. kfree_skb(res_skb);
  387. p++;
  388. }
  389. param[0] = NFC_HCI_UICC_HOST_ID;
  390. r = nfc_hci_set_param(hdev, NFC_HCI_ADMIN_GATE,
  391. NFC_HCI_ADMIN_WHITELIST, param, 1);
  392. if (r < 0)
  393. return r;
  394. param[0] = 0x3d;
  395. r = nfc_hci_set_param(hdev, PN544_SYS_MGMT_GATE,
  396. PN544_SYS_MGMT_INFO_NOTIFICATION, param, 1);
  397. if (r < 0)
  398. return r;
  399. param[0] = 0x0;
  400. r = nfc_hci_set_param(hdev, NFC_HCI_RF_READER_A_GATE,
  401. PN544_RF_READER_A_AUTO_ACTIVATION, param, 1);
  402. if (r < 0)
  403. return r;
  404. r = nfc_hci_send_event(hdev, NFC_HCI_RF_READER_A_GATE,
  405. NFC_HCI_EVT_END_OPERATION, NULL, 0);
  406. if (r < 0)
  407. return r;
  408. param[0] = 0x1;
  409. r = nfc_hci_set_param(hdev, PN544_POLLING_LOOP_MGMT_GATE,
  410. PN544_PL_NFCT_DEACTIVATED, param, 1);
  411. if (r < 0)
  412. return r;
  413. param[0] = 0x0;
  414. r = nfc_hci_set_param(hdev, PN544_POLLING_LOOP_MGMT_GATE,
  415. PN544_PL_RDPHASES, param, 1);
  416. if (r < 0)
  417. return r;
  418. r = nfc_hci_get_param(hdev, NFC_HCI_ID_MGMT_GATE,
  419. PN544_ID_MGMT_FULL_VERSION_SW, &skb);
  420. if (r < 0)
  421. return r;
  422. if (skb->len != FULL_VERSION_LEN) {
  423. kfree_skb(skb);
  424. return -EINVAL;
  425. }
  426. print_hex_dump(KERN_DEBUG, "FULL VERSION SOFTWARE INFO: ",
  427. DUMP_PREFIX_NONE, 16, 1,
  428. skb->data, FULL_VERSION_LEN, false);
  429. kfree_skb(skb);
  430. return 0;
  431. }
  432. static int pn544_hci_xmit(struct nfc_shdlc *shdlc, struct sk_buff *skb)
  433. {
  434. struct pn544_hci_info *info = nfc_shdlc_get_clientdata(shdlc);
  435. struct i2c_client *client = info->i2c_dev;
  436. if (info->hard_fault != 0)
  437. return info->hard_fault;
  438. return pn544_hci_i2c_write(client, skb->data, skb->len);
  439. }
  440. static int pn544_hci_start_poll(struct nfc_shdlc *shdlc, u32 protocols)
  441. {
  442. struct nfc_hci_dev *hdev = nfc_shdlc_get_hci_dev(shdlc);
  443. u8 phases = 0;
  444. int r;
  445. u8 duration[2];
  446. u8 activated;
  447. pr_info(DRIVER_DESC ": %s protocols = %d\n", __func__, protocols);
  448. r = nfc_hci_send_event(hdev, NFC_HCI_RF_READER_A_GATE,
  449. NFC_HCI_EVT_END_OPERATION, NULL, 0);
  450. if (r < 0)
  451. return r;
  452. duration[0] = 0x18;
  453. duration[1] = 0x6a;
  454. r = nfc_hci_set_param(hdev, PN544_POLLING_LOOP_MGMT_GATE,
  455. PN544_PL_EMULATION, duration, 2);
  456. if (r < 0)
  457. return r;
  458. activated = 0;
  459. r = nfc_hci_set_param(hdev, PN544_POLLING_LOOP_MGMT_GATE,
  460. PN544_PL_NFCT_DEACTIVATED, &activated, 1);
  461. if (r < 0)
  462. return r;
  463. if (protocols & (NFC_PROTO_ISO14443_MASK | NFC_PROTO_MIFARE_MASK |
  464. NFC_PROTO_JEWEL_MASK))
  465. phases |= 1; /* Type A */
  466. if (protocols & NFC_PROTO_FELICA_MASK) {
  467. phases |= (1 << 2); /* Type F 212 */
  468. phases |= (1 << 3); /* Type F 424 */
  469. }
  470. phases |= (1 << 5); /* NFC active */
  471. r = nfc_hci_set_param(hdev, PN544_POLLING_LOOP_MGMT_GATE,
  472. PN544_PL_RDPHASES, &phases, 1);
  473. if (r < 0)
  474. return r;
  475. r = nfc_hci_send_event(hdev, NFC_HCI_RF_READER_A_GATE,
  476. NFC_HCI_EVT_READER_REQUESTED, NULL, 0);
  477. if (r < 0)
  478. nfc_hci_send_event(hdev, NFC_HCI_RF_READER_A_GATE,
  479. NFC_HCI_EVT_END_OPERATION, NULL, 0);
  480. return r;
  481. }
  482. static int pn544_hci_target_from_gate(struct nfc_shdlc *shdlc, u8 gate,
  483. struct nfc_target *target)
  484. {
  485. switch (gate) {
  486. case PN544_RF_READER_F_GATE:
  487. target->supported_protocols = NFC_PROTO_FELICA_MASK;
  488. break;
  489. case PN544_RF_READER_JEWEL_GATE:
  490. target->supported_protocols = NFC_PROTO_JEWEL_MASK;
  491. target->sens_res = 0x0c00;
  492. break;
  493. default:
  494. return -EPROTO;
  495. }
  496. return 0;
  497. }
  498. static int pn544_hci_complete_target_discovered(struct nfc_shdlc *shdlc,
  499. u8 gate,
  500. struct nfc_target *target)
  501. {
  502. struct nfc_hci_dev *hdev = nfc_shdlc_get_hci_dev(shdlc);
  503. struct sk_buff *uid_skb;
  504. int r = 0;
  505. if (target->supported_protocols & NFC_PROTO_MIFARE_MASK) {
  506. if (target->nfcid1_len != 4 && target->nfcid1_len != 7 &&
  507. target->nfcid1_len != 10)
  508. return -EPROTO;
  509. r = nfc_hci_send_cmd(hdev, NFC_HCI_RF_READER_A_GATE,
  510. PN544_RF_READER_CMD_ACTIVATE_NEXT,
  511. target->nfcid1, target->nfcid1_len, NULL);
  512. } else if (target->supported_protocols & NFC_PROTO_FELICA_MASK) {
  513. r = nfc_hci_get_param(hdev, PN544_RF_READER_F_GATE,
  514. PN544_FELICA_ID, &uid_skb);
  515. if (r < 0)
  516. return r;
  517. if (uid_skb->len != 8) {
  518. kfree_skb(uid_skb);
  519. return -EPROTO;
  520. }
  521. r = nfc_hci_send_cmd(hdev, PN544_RF_READER_F_GATE,
  522. PN544_RF_READER_CMD_ACTIVATE_NEXT,
  523. uid_skb->data, uid_skb->len, NULL);
  524. kfree_skb(uid_skb);
  525. } else if (target->supported_protocols & NFC_PROTO_ISO14443_MASK) {
  526. /*
  527. * TODO: maybe other ISO 14443 require some kind of continue
  528. * activation, but for now we've seen only this one below.
  529. */
  530. if (target->sens_res == 0x4403) /* Type 4 Mifare DESFire */
  531. r = nfc_hci_send_cmd(hdev, NFC_HCI_RF_READER_A_GATE,
  532. PN544_RF_READER_A_CMD_CONTINUE_ACTIVATION,
  533. NULL, 0, NULL);
  534. }
  535. return r;
  536. }
  537. #define MIFARE_CMD_AUTH_KEY_A 0x60
  538. #define MIFARE_CMD_AUTH_KEY_B 0x61
  539. #define MIFARE_CMD_HEADER 2
  540. #define MIFARE_UID_LEN 4
  541. #define MIFARE_KEY_LEN 6
  542. #define MIFARE_CMD_LEN 12
  543. /*
  544. * Returns:
  545. * <= 0: driver handled the data exchange
  546. * 1: driver doesn't especially handle, please do standard processing
  547. */
  548. static int pn544_hci_data_exchange(struct nfc_shdlc *shdlc,
  549. struct nfc_target *target,
  550. struct sk_buff *skb,
  551. struct sk_buff **res_skb)
  552. {
  553. struct nfc_hci_dev *hdev = nfc_shdlc_get_hci_dev(shdlc);
  554. int r;
  555. pr_info(DRIVER_DESC ": %s for gate=%d\n", __func__,
  556. target->hci_reader_gate);
  557. switch (target->hci_reader_gate) {
  558. case NFC_HCI_RF_READER_A_GATE:
  559. if (target->supported_protocols & NFC_PROTO_MIFARE_MASK) {
  560. /*
  561. * It seems that pn544 is inverting key and UID for
  562. * MIFARE authentication commands.
  563. */
  564. if (skb->len == MIFARE_CMD_LEN &&
  565. (skb->data[0] == MIFARE_CMD_AUTH_KEY_A ||
  566. skb->data[0] == MIFARE_CMD_AUTH_KEY_B)) {
  567. u8 uid[MIFARE_UID_LEN];
  568. u8 *data = skb->data + MIFARE_CMD_HEADER;
  569. memcpy(uid, data + MIFARE_KEY_LEN,
  570. MIFARE_UID_LEN);
  571. memmove(data + MIFARE_UID_LEN, data,
  572. MIFARE_KEY_LEN);
  573. memcpy(data, uid, MIFARE_UID_LEN);
  574. }
  575. return nfc_hci_send_cmd(hdev, target->hci_reader_gate,
  576. PN544_MIFARE_CMD,
  577. skb->data, skb->len, res_skb);
  578. } else
  579. return 1;
  580. case PN544_RF_READER_F_GATE:
  581. *skb_push(skb, 1) = 0;
  582. *skb_push(skb, 1) = 0;
  583. r = nfc_hci_send_cmd(hdev, target->hci_reader_gate,
  584. PN544_FELICA_RAW,
  585. skb->data, skb->len, res_skb);
  586. if (r == 0)
  587. skb_pull(*res_skb, 1);
  588. return r;
  589. case PN544_RF_READER_JEWEL_GATE:
  590. return nfc_hci_send_cmd(hdev, target->hci_reader_gate,
  591. PN544_JEWEL_RAW_CMD,
  592. skb->data, skb->len, res_skb);
  593. default:
  594. return 1;
  595. }
  596. }
  597. static int pn544_hci_check_presence(struct nfc_shdlc *shdlc,
  598. struct nfc_target *target)
  599. {
  600. struct nfc_hci_dev *hdev = nfc_shdlc_get_hci_dev(shdlc);
  601. return nfc_hci_send_cmd(hdev, target->hci_reader_gate,
  602. PN544_RF_READER_CMD_PRESENCE_CHECK,
  603. NULL, 0, NULL);
  604. }
  605. static struct nfc_shdlc_ops pn544_shdlc_ops = {
  606. .open = pn544_hci_open,
  607. .close = pn544_hci_close,
  608. .hci_ready = pn544_hci_ready,
  609. .xmit = pn544_hci_xmit,
  610. .start_poll = pn544_hci_start_poll,
  611. .target_from_gate = pn544_hci_target_from_gate,
  612. .complete_target_discovered = pn544_hci_complete_target_discovered,
  613. .data_exchange = pn544_hci_data_exchange,
  614. .check_presence = pn544_hci_check_presence,
  615. };
  616. static int __devinit pn544_hci_probe(struct i2c_client *client,
  617. const struct i2c_device_id *id)
  618. {
  619. struct pn544_hci_info *info;
  620. struct pn544_nfc_platform_data *pdata;
  621. int r = 0;
  622. u32 protocols;
  623. struct nfc_hci_init_data init_data;
  624. dev_dbg(&client->dev, "%s\n", __func__);
  625. dev_dbg(&client->dev, "IRQ: %d\n", client->irq);
  626. if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
  627. dev_err(&client->dev, "Need I2C_FUNC_I2C\n");
  628. return -ENODEV;
  629. }
  630. info = kzalloc(sizeof(struct pn544_hci_info), GFP_KERNEL);
  631. if (!info) {
  632. dev_err(&client->dev,
  633. "Cannot allocate memory for pn544_hci_info.\n");
  634. r = -ENOMEM;
  635. goto err_info_alloc;
  636. }
  637. info->i2c_dev = client;
  638. info->state = PN544_ST_COLD;
  639. mutex_init(&info->info_lock);
  640. i2c_set_clientdata(client, info);
  641. pdata = client->dev.platform_data;
  642. if (pdata == NULL) {
  643. dev_err(&client->dev, "No platform data\n");
  644. r = -EINVAL;
  645. goto err_pdata;
  646. }
  647. if (pdata->request_resources == NULL) {
  648. dev_err(&client->dev, "request_resources() missing\n");
  649. r = -EINVAL;
  650. goto err_pdata;
  651. }
  652. r = pdata->request_resources(client);
  653. if (r) {
  654. dev_err(&client->dev, "Cannot get platform resources\n");
  655. goto err_pdata;
  656. }
  657. info->gpio_en = pdata->get_gpio(NFC_GPIO_ENABLE);
  658. info->gpio_fw = pdata->get_gpio(NFC_GPIO_FW_RESET);
  659. info->gpio_irq = pdata->get_gpio(NFC_GPIO_IRQ);
  660. pn544_hci_platform_init(info);
  661. r = request_threaded_irq(client->irq, NULL, pn544_hci_irq_thread_fn,
  662. IRQF_TRIGGER_RISING, PN544_HCI_DRIVER_NAME,
  663. info);
  664. if (r < 0) {
  665. dev_err(&client->dev, "Unable to register IRQ handler\n");
  666. goto err_rti;
  667. }
  668. init_data.gate_count = ARRAY_SIZE(pn544_custom_gates);
  669. memcpy(init_data.gates, pn544_custom_gates,
  670. ARRAY_SIZE(pn544_custom_gates));
  671. /*
  672. * TODO: Session id must include the driver name + some bus addr
  673. * persistent info to discriminate 2 identical chips
  674. */
  675. strcpy(init_data.session_id, "ID544HCI");
  676. protocols = NFC_PROTO_JEWEL_MASK |
  677. NFC_PROTO_MIFARE_MASK |
  678. NFC_PROTO_FELICA_MASK |
  679. NFC_PROTO_ISO14443_MASK |
  680. NFC_PROTO_NFC_DEP_MASK;
  681. info->shdlc = nfc_shdlc_allocate(&pn544_shdlc_ops,
  682. &init_data, protocols,
  683. PN544_CMDS_HEADROOM, 0,
  684. PN544_HCI_LLC_MAX_PAYLOAD,
  685. dev_name(&client->dev));
  686. if (!info->shdlc) {
  687. dev_err(&client->dev, "Cannot allocate nfc shdlc.\n");
  688. r = -ENOMEM;
  689. goto err_allocshdlc;
  690. }
  691. nfc_shdlc_set_clientdata(info->shdlc, info);
  692. return 0;
  693. err_allocshdlc:
  694. free_irq(client->irq, info);
  695. err_rti:
  696. if (pdata->free_resources != NULL)
  697. pdata->free_resources();
  698. err_pdata:
  699. kfree(info);
  700. err_info_alloc:
  701. return r;
  702. }
  703. static __devexit int pn544_hci_remove(struct i2c_client *client)
  704. {
  705. struct pn544_hci_info *info = i2c_get_clientdata(client);
  706. struct pn544_nfc_platform_data *pdata = client->dev.platform_data;
  707. dev_dbg(&client->dev, "%s\n", __func__);
  708. nfc_shdlc_free(info->shdlc);
  709. if (info->state != PN544_ST_COLD) {
  710. if (pdata->disable)
  711. pdata->disable();
  712. }
  713. free_irq(client->irq, info);
  714. if (pdata->free_resources)
  715. pdata->free_resources();
  716. kfree(info);
  717. return 0;
  718. }
  719. static struct i2c_driver pn544_hci_driver = {
  720. .driver = {
  721. .name = PN544_HCI_DRIVER_NAME,
  722. },
  723. .probe = pn544_hci_probe,
  724. .id_table = pn544_hci_id_table,
  725. .remove = __devexit_p(pn544_hci_remove),
  726. };
  727. static int __init pn544_hci_init(void)
  728. {
  729. int r;
  730. pr_debug(DRIVER_DESC ": %s\n", __func__);
  731. r = i2c_add_driver(&pn544_hci_driver);
  732. if (r) {
  733. pr_err(PN544_HCI_DRIVER_NAME ": driver registration failed\n");
  734. return r;
  735. }
  736. return 0;
  737. }
  738. static void __exit pn544_hci_exit(void)
  739. {
  740. i2c_del_driver(&pn544_hci_driver);
  741. }
  742. module_init(pn544_hci_init);
  743. module_exit(pn544_hci_exit);
  744. MODULE_LICENSE("GPL");
  745. MODULE_DESCRIPTION(DRIVER_DESC);