main.c 39 KB

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  1. /*
  2. * This file is part of wl1271
  3. *
  4. * Copyright (C) 2008-2010 Nokia Corporation
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License
  8. * version 2 as published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  13. * General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  18. * 02110-1301 USA
  19. *
  20. */
  21. #include <linux/module.h>
  22. #include <linux/platform_device.h>
  23. #include <linux/err.h>
  24. #include <linux/wl12xx.h>
  25. #include "../wlcore/wlcore.h"
  26. #include "../wlcore/debug.h"
  27. #include "../wlcore/io.h"
  28. #include "../wlcore/acx.h"
  29. #include "../wlcore/tx.h"
  30. #include "../wlcore/rx.h"
  31. #include "../wlcore/io.h"
  32. #include "../wlcore/boot.h"
  33. #include "wl12xx.h"
  34. #include "reg.h"
  35. #include "cmd.h"
  36. #include "acx.h"
  37. static struct wlcore_conf wl12xx_conf = {
  38. .sg = {
  39. .params = {
  40. [CONF_SG_ACL_BT_MASTER_MIN_BR] = 10,
  41. [CONF_SG_ACL_BT_MASTER_MAX_BR] = 180,
  42. [CONF_SG_ACL_BT_SLAVE_MIN_BR] = 10,
  43. [CONF_SG_ACL_BT_SLAVE_MAX_BR] = 180,
  44. [CONF_SG_ACL_BT_MASTER_MIN_EDR] = 10,
  45. [CONF_SG_ACL_BT_MASTER_MAX_EDR] = 80,
  46. [CONF_SG_ACL_BT_SLAVE_MIN_EDR] = 10,
  47. [CONF_SG_ACL_BT_SLAVE_MAX_EDR] = 80,
  48. [CONF_SG_ACL_WLAN_PS_MASTER_BR] = 8,
  49. [CONF_SG_ACL_WLAN_PS_SLAVE_BR] = 8,
  50. [CONF_SG_ACL_WLAN_PS_MASTER_EDR] = 20,
  51. [CONF_SG_ACL_WLAN_PS_SLAVE_EDR] = 20,
  52. [CONF_SG_ACL_WLAN_ACTIVE_MASTER_MIN_BR] = 20,
  53. [CONF_SG_ACL_WLAN_ACTIVE_MASTER_MAX_BR] = 35,
  54. [CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MIN_BR] = 16,
  55. [CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MAX_BR] = 35,
  56. [CONF_SG_ACL_WLAN_ACTIVE_MASTER_MIN_EDR] = 32,
  57. [CONF_SG_ACL_WLAN_ACTIVE_MASTER_MAX_EDR] = 50,
  58. [CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MIN_EDR] = 28,
  59. [CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MAX_EDR] = 50,
  60. [CONF_SG_ACL_ACTIVE_SCAN_WLAN_BR] = 10,
  61. [CONF_SG_ACL_ACTIVE_SCAN_WLAN_EDR] = 20,
  62. [CONF_SG_ACL_PASSIVE_SCAN_BT_BR] = 75,
  63. [CONF_SG_ACL_PASSIVE_SCAN_WLAN_BR] = 15,
  64. [CONF_SG_ACL_PASSIVE_SCAN_BT_EDR] = 27,
  65. [CONF_SG_ACL_PASSIVE_SCAN_WLAN_EDR] = 17,
  66. /* active scan params */
  67. [CONF_SG_AUTO_SCAN_PROBE_REQ] = 170,
  68. [CONF_SG_ACTIVE_SCAN_DURATION_FACTOR_HV3] = 50,
  69. [CONF_SG_ACTIVE_SCAN_DURATION_FACTOR_A2DP] = 100,
  70. /* passive scan params */
  71. [CONF_SG_PASSIVE_SCAN_DURATION_FACTOR_A2DP_BR] = 800,
  72. [CONF_SG_PASSIVE_SCAN_DURATION_FACTOR_A2DP_EDR] = 200,
  73. [CONF_SG_PASSIVE_SCAN_DURATION_FACTOR_HV3] = 200,
  74. /* passive scan in dual antenna params */
  75. [CONF_SG_CONSECUTIVE_HV3_IN_PASSIVE_SCAN] = 0,
  76. [CONF_SG_BCN_HV3_COLLISION_THRESH_IN_PASSIVE_SCAN] = 0,
  77. [CONF_SG_TX_RX_PROTECTION_BWIDTH_IN_PASSIVE_SCAN] = 0,
  78. /* general params */
  79. [CONF_SG_STA_FORCE_PS_IN_BT_SCO] = 1,
  80. [CONF_SG_ANTENNA_CONFIGURATION] = 0,
  81. [CONF_SG_BEACON_MISS_PERCENT] = 60,
  82. [CONF_SG_DHCP_TIME] = 5000,
  83. [CONF_SG_RXT] = 1200,
  84. [CONF_SG_TXT] = 1000,
  85. [CONF_SG_ADAPTIVE_RXT_TXT] = 1,
  86. [CONF_SG_GENERAL_USAGE_BIT_MAP] = 3,
  87. [CONF_SG_HV3_MAX_SERVED] = 6,
  88. [CONF_SG_PS_POLL_TIMEOUT] = 10,
  89. [CONF_SG_UPSD_TIMEOUT] = 10,
  90. [CONF_SG_CONSECUTIVE_CTS_THRESHOLD] = 2,
  91. [CONF_SG_STA_RX_WINDOW_AFTER_DTIM] = 5,
  92. [CONF_SG_STA_CONNECTION_PROTECTION_TIME] = 30,
  93. /* AP params */
  94. [CONF_AP_BEACON_MISS_TX] = 3,
  95. [CONF_AP_RX_WINDOW_AFTER_BEACON] = 10,
  96. [CONF_AP_BEACON_WINDOW_INTERVAL] = 2,
  97. [CONF_AP_CONNECTION_PROTECTION_TIME] = 0,
  98. [CONF_AP_BT_ACL_VAL_BT_SERVE_TIME] = 25,
  99. [CONF_AP_BT_ACL_VAL_WL_SERVE_TIME] = 25,
  100. /* CTS Diluting params */
  101. [CONF_SG_CTS_DILUTED_BAD_RX_PACKETS_TH] = 0,
  102. [CONF_SG_CTS_CHOP_IN_DUAL_ANT_SCO_MASTER] = 0,
  103. },
  104. .state = CONF_SG_PROTECTIVE,
  105. },
  106. .rx = {
  107. .rx_msdu_life_time = 512000,
  108. .packet_detection_threshold = 0,
  109. .ps_poll_timeout = 15,
  110. .upsd_timeout = 15,
  111. .rts_threshold = IEEE80211_MAX_RTS_THRESHOLD,
  112. .rx_cca_threshold = 0,
  113. .irq_blk_threshold = 0xFFFF,
  114. .irq_pkt_threshold = 0,
  115. .irq_timeout = 600,
  116. .queue_type = CONF_RX_QUEUE_TYPE_LOW_PRIORITY,
  117. },
  118. .tx = {
  119. .tx_energy_detection = 0,
  120. .sta_rc_conf = {
  121. .enabled_rates = 0,
  122. .short_retry_limit = 10,
  123. .long_retry_limit = 10,
  124. .aflags = 0,
  125. },
  126. .ac_conf_count = 4,
  127. .ac_conf = {
  128. [CONF_TX_AC_BE] = {
  129. .ac = CONF_TX_AC_BE,
  130. .cw_min = 15,
  131. .cw_max = 63,
  132. .aifsn = 3,
  133. .tx_op_limit = 0,
  134. },
  135. [CONF_TX_AC_BK] = {
  136. .ac = CONF_TX_AC_BK,
  137. .cw_min = 15,
  138. .cw_max = 63,
  139. .aifsn = 7,
  140. .tx_op_limit = 0,
  141. },
  142. [CONF_TX_AC_VI] = {
  143. .ac = CONF_TX_AC_VI,
  144. .cw_min = 15,
  145. .cw_max = 63,
  146. .aifsn = CONF_TX_AIFS_PIFS,
  147. .tx_op_limit = 3008,
  148. },
  149. [CONF_TX_AC_VO] = {
  150. .ac = CONF_TX_AC_VO,
  151. .cw_min = 15,
  152. .cw_max = 63,
  153. .aifsn = CONF_TX_AIFS_PIFS,
  154. .tx_op_limit = 1504,
  155. },
  156. },
  157. .max_tx_retries = 100,
  158. .ap_aging_period = 300,
  159. .tid_conf_count = 4,
  160. .tid_conf = {
  161. [CONF_TX_AC_BE] = {
  162. .queue_id = CONF_TX_AC_BE,
  163. .channel_type = CONF_CHANNEL_TYPE_EDCF,
  164. .tsid = CONF_TX_AC_BE,
  165. .ps_scheme = CONF_PS_SCHEME_LEGACY,
  166. .ack_policy = CONF_ACK_POLICY_LEGACY,
  167. .apsd_conf = {0, 0},
  168. },
  169. [CONF_TX_AC_BK] = {
  170. .queue_id = CONF_TX_AC_BK,
  171. .channel_type = CONF_CHANNEL_TYPE_EDCF,
  172. .tsid = CONF_TX_AC_BK,
  173. .ps_scheme = CONF_PS_SCHEME_LEGACY,
  174. .ack_policy = CONF_ACK_POLICY_LEGACY,
  175. .apsd_conf = {0, 0},
  176. },
  177. [CONF_TX_AC_VI] = {
  178. .queue_id = CONF_TX_AC_VI,
  179. .channel_type = CONF_CHANNEL_TYPE_EDCF,
  180. .tsid = CONF_TX_AC_VI,
  181. .ps_scheme = CONF_PS_SCHEME_LEGACY,
  182. .ack_policy = CONF_ACK_POLICY_LEGACY,
  183. .apsd_conf = {0, 0},
  184. },
  185. [CONF_TX_AC_VO] = {
  186. .queue_id = CONF_TX_AC_VO,
  187. .channel_type = CONF_CHANNEL_TYPE_EDCF,
  188. .tsid = CONF_TX_AC_VO,
  189. .ps_scheme = CONF_PS_SCHEME_LEGACY,
  190. .ack_policy = CONF_ACK_POLICY_LEGACY,
  191. .apsd_conf = {0, 0},
  192. },
  193. },
  194. .frag_threshold = IEEE80211_MAX_FRAG_THRESHOLD,
  195. .tx_compl_timeout = 700,
  196. .tx_compl_threshold = 4,
  197. .basic_rate = CONF_HW_BIT_RATE_1MBPS,
  198. .basic_rate_5 = CONF_HW_BIT_RATE_6MBPS,
  199. .tmpl_short_retry_limit = 10,
  200. .tmpl_long_retry_limit = 10,
  201. .tx_watchdog_timeout = 5000,
  202. },
  203. .conn = {
  204. .wake_up_event = CONF_WAKE_UP_EVENT_DTIM,
  205. .listen_interval = 1,
  206. .suspend_wake_up_event = CONF_WAKE_UP_EVENT_N_DTIM,
  207. .suspend_listen_interval = 3,
  208. .bcn_filt_mode = CONF_BCN_FILT_MODE_ENABLED,
  209. .bcn_filt_ie_count = 2,
  210. .bcn_filt_ie = {
  211. [0] = {
  212. .ie = WLAN_EID_CHANNEL_SWITCH,
  213. .rule = CONF_BCN_RULE_PASS_ON_APPEARANCE,
  214. },
  215. [1] = {
  216. .ie = WLAN_EID_HT_OPERATION,
  217. .rule = CONF_BCN_RULE_PASS_ON_CHANGE,
  218. },
  219. },
  220. .synch_fail_thold = 10,
  221. .bss_lose_timeout = 100,
  222. .beacon_rx_timeout = 10000,
  223. .broadcast_timeout = 20000,
  224. .rx_broadcast_in_ps = 1,
  225. .ps_poll_threshold = 10,
  226. .bet_enable = CONF_BET_MODE_ENABLE,
  227. .bet_max_consecutive = 50,
  228. .psm_entry_retries = 8,
  229. .psm_exit_retries = 16,
  230. .psm_entry_nullfunc_retries = 3,
  231. .dynamic_ps_timeout = 40,
  232. .forced_ps = false,
  233. .keep_alive_interval = 55000,
  234. .max_listen_interval = 20,
  235. },
  236. .itrim = {
  237. .enable = false,
  238. .timeout = 50000,
  239. },
  240. .pm_config = {
  241. .host_clk_settling_time = 5000,
  242. .host_fast_wakeup_support = false
  243. },
  244. .roam_trigger = {
  245. .trigger_pacing = 1,
  246. .avg_weight_rssi_beacon = 20,
  247. .avg_weight_rssi_data = 10,
  248. .avg_weight_snr_beacon = 20,
  249. .avg_weight_snr_data = 10,
  250. },
  251. .scan = {
  252. .min_dwell_time_active = 7500,
  253. .max_dwell_time_active = 30000,
  254. .min_dwell_time_passive = 100000,
  255. .max_dwell_time_passive = 100000,
  256. .num_probe_reqs = 2,
  257. .split_scan_timeout = 50000,
  258. },
  259. .sched_scan = {
  260. /*
  261. * Values are in TU/1000 but since sched scan FW command
  262. * params are in TUs rounding up may occur.
  263. */
  264. .base_dwell_time = 7500,
  265. .max_dwell_time_delta = 22500,
  266. /* based on 250bits per probe @1Mbps */
  267. .dwell_time_delta_per_probe = 2000,
  268. /* based on 250bits per probe @6Mbps (plus a bit more) */
  269. .dwell_time_delta_per_probe_5 = 350,
  270. .dwell_time_passive = 100000,
  271. .dwell_time_dfs = 150000,
  272. .num_probe_reqs = 2,
  273. .rssi_threshold = -90,
  274. .snr_threshold = 0,
  275. },
  276. .ht = {
  277. .rx_ba_win_size = 8,
  278. .tx_ba_win_size = 64,
  279. .inactivity_timeout = 10000,
  280. .tx_ba_tid_bitmap = CONF_TX_BA_ENABLED_TID_BITMAP,
  281. },
  282. /*
  283. * Memory config for wl127x chips is given in the
  284. * wl12xx_default_priv_conf struct. The below configuration is
  285. * for wl128x chips.
  286. */
  287. .mem = {
  288. .num_stations = 1,
  289. .ssid_profiles = 1,
  290. .rx_block_num = 40,
  291. .tx_min_block_num = 40,
  292. .dynamic_memory = 1,
  293. .min_req_tx_blocks = 45,
  294. .min_req_rx_blocks = 22,
  295. .tx_min = 27,
  296. },
  297. .fm_coex = {
  298. .enable = true,
  299. .swallow_period = 5,
  300. .n_divider_fref_set_1 = 0xff, /* default */
  301. .n_divider_fref_set_2 = 12,
  302. .m_divider_fref_set_1 = 148,
  303. .m_divider_fref_set_2 = 0xffff, /* default */
  304. .coex_pll_stabilization_time = 0xffffffff, /* default */
  305. .ldo_stabilization_time = 0xffff, /* default */
  306. .fm_disturbed_band_margin = 0xff, /* default */
  307. .swallow_clk_diff = 0xff, /* default */
  308. },
  309. .rx_streaming = {
  310. .duration = 150,
  311. .queues = 0x1,
  312. .interval = 20,
  313. .always = 0,
  314. },
  315. .fwlog = {
  316. .mode = WL12XX_FWLOG_ON_DEMAND,
  317. .mem_blocks = 2,
  318. .severity = 0,
  319. .timestamp = WL12XX_FWLOG_TIMESTAMP_DISABLED,
  320. .output = WL12XX_FWLOG_OUTPUT_HOST,
  321. .threshold = 0,
  322. },
  323. .rate = {
  324. .rate_retry_score = 32000,
  325. .per_add = 8192,
  326. .per_th1 = 2048,
  327. .per_th2 = 4096,
  328. .max_per = 8100,
  329. .inverse_curiosity_factor = 5,
  330. .tx_fail_low_th = 4,
  331. .tx_fail_high_th = 10,
  332. .per_alpha_shift = 4,
  333. .per_add_shift = 13,
  334. .per_beta1_shift = 10,
  335. .per_beta2_shift = 8,
  336. .rate_check_up = 2,
  337. .rate_check_down = 12,
  338. .rate_retry_policy = {
  339. 0x00, 0x00, 0x00, 0x00, 0x00,
  340. 0x00, 0x00, 0x00, 0x00, 0x00,
  341. 0x00, 0x00, 0x00,
  342. },
  343. },
  344. .hangover = {
  345. .recover_time = 0,
  346. .hangover_period = 20,
  347. .dynamic_mode = 1,
  348. .early_termination_mode = 1,
  349. .max_period = 20,
  350. .min_period = 1,
  351. .increase_delta = 1,
  352. .decrease_delta = 2,
  353. .quiet_time = 4,
  354. .increase_time = 1,
  355. .window_size = 16,
  356. },
  357. };
  358. static struct wl12xx_priv_conf wl12xx_default_priv_conf = {
  359. .rf = {
  360. .tx_per_channel_power_compensation_2 = {
  361. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  362. },
  363. .tx_per_channel_power_compensation_5 = {
  364. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  365. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  366. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  367. },
  368. },
  369. .mem_wl127x = {
  370. .num_stations = 1,
  371. .ssid_profiles = 1,
  372. .rx_block_num = 70,
  373. .tx_min_block_num = 40,
  374. .dynamic_memory = 1,
  375. .min_req_tx_blocks = 100,
  376. .min_req_rx_blocks = 22,
  377. .tx_min = 27,
  378. },
  379. };
  380. #define WL12XX_TX_HW_BLOCK_SPARE_DEFAULT 1
  381. #define WL12XX_TX_HW_BLOCK_GEM_SPARE 2
  382. #define WL12XX_TX_HW_BLOCK_SIZE 252
  383. static const u8 wl12xx_rate_to_idx_2ghz[] = {
  384. /* MCS rates are used only with 11n */
  385. 7, /* WL12XX_CONF_HW_RXTX_RATE_MCS7_SGI */
  386. 7, /* WL12XX_CONF_HW_RXTX_RATE_MCS7 */
  387. 6, /* WL12XX_CONF_HW_RXTX_RATE_MCS6 */
  388. 5, /* WL12XX_CONF_HW_RXTX_RATE_MCS5 */
  389. 4, /* WL12XX_CONF_HW_RXTX_RATE_MCS4 */
  390. 3, /* WL12XX_CONF_HW_RXTX_RATE_MCS3 */
  391. 2, /* WL12XX_CONF_HW_RXTX_RATE_MCS2 */
  392. 1, /* WL12XX_CONF_HW_RXTX_RATE_MCS1 */
  393. 0, /* WL12XX_CONF_HW_RXTX_RATE_MCS0 */
  394. 11, /* WL12XX_CONF_HW_RXTX_RATE_54 */
  395. 10, /* WL12XX_CONF_HW_RXTX_RATE_48 */
  396. 9, /* WL12XX_CONF_HW_RXTX_RATE_36 */
  397. 8, /* WL12XX_CONF_HW_RXTX_RATE_24 */
  398. /* TI-specific rate */
  399. CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL12XX_CONF_HW_RXTX_RATE_22 */
  400. 7, /* WL12XX_CONF_HW_RXTX_RATE_18 */
  401. 6, /* WL12XX_CONF_HW_RXTX_RATE_12 */
  402. 3, /* WL12XX_CONF_HW_RXTX_RATE_11 */
  403. 5, /* WL12XX_CONF_HW_RXTX_RATE_9 */
  404. 4, /* WL12XX_CONF_HW_RXTX_RATE_6 */
  405. 2, /* WL12XX_CONF_HW_RXTX_RATE_5_5 */
  406. 1, /* WL12XX_CONF_HW_RXTX_RATE_2 */
  407. 0 /* WL12XX_CONF_HW_RXTX_RATE_1 */
  408. };
  409. static const u8 wl12xx_rate_to_idx_5ghz[] = {
  410. /* MCS rates are used only with 11n */
  411. 7, /* WL12XX_CONF_HW_RXTX_RATE_MCS7_SGI */
  412. 7, /* WL12XX_CONF_HW_RXTX_RATE_MCS7 */
  413. 6, /* WL12XX_CONF_HW_RXTX_RATE_MCS6 */
  414. 5, /* WL12XX_CONF_HW_RXTX_RATE_MCS5 */
  415. 4, /* WL12XX_CONF_HW_RXTX_RATE_MCS4 */
  416. 3, /* WL12XX_CONF_HW_RXTX_RATE_MCS3 */
  417. 2, /* WL12XX_CONF_HW_RXTX_RATE_MCS2 */
  418. 1, /* WL12XX_CONF_HW_RXTX_RATE_MCS1 */
  419. 0, /* WL12XX_CONF_HW_RXTX_RATE_MCS0 */
  420. 7, /* WL12XX_CONF_HW_RXTX_RATE_54 */
  421. 6, /* WL12XX_CONF_HW_RXTX_RATE_48 */
  422. 5, /* WL12XX_CONF_HW_RXTX_RATE_36 */
  423. 4, /* WL12XX_CONF_HW_RXTX_RATE_24 */
  424. /* TI-specific rate */
  425. CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL12XX_CONF_HW_RXTX_RATE_22 */
  426. 3, /* WL12XX_CONF_HW_RXTX_RATE_18 */
  427. 2, /* WL12XX_CONF_HW_RXTX_RATE_12 */
  428. CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL12XX_CONF_HW_RXTX_RATE_11 */
  429. 1, /* WL12XX_CONF_HW_RXTX_RATE_9 */
  430. 0, /* WL12XX_CONF_HW_RXTX_RATE_6 */
  431. CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL12XX_CONF_HW_RXTX_RATE_5_5 */
  432. CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL12XX_CONF_HW_RXTX_RATE_2 */
  433. CONF_HW_RXTX_RATE_UNSUPPORTED /* WL12XX_CONF_HW_RXTX_RATE_1 */
  434. };
  435. static const u8 *wl12xx_band_rate_to_idx[] = {
  436. [IEEE80211_BAND_2GHZ] = wl12xx_rate_to_idx_2ghz,
  437. [IEEE80211_BAND_5GHZ] = wl12xx_rate_to_idx_5ghz
  438. };
  439. enum wl12xx_hw_rates {
  440. WL12XX_CONF_HW_RXTX_RATE_MCS7_SGI = 0,
  441. WL12XX_CONF_HW_RXTX_RATE_MCS7,
  442. WL12XX_CONF_HW_RXTX_RATE_MCS6,
  443. WL12XX_CONF_HW_RXTX_RATE_MCS5,
  444. WL12XX_CONF_HW_RXTX_RATE_MCS4,
  445. WL12XX_CONF_HW_RXTX_RATE_MCS3,
  446. WL12XX_CONF_HW_RXTX_RATE_MCS2,
  447. WL12XX_CONF_HW_RXTX_RATE_MCS1,
  448. WL12XX_CONF_HW_RXTX_RATE_MCS0,
  449. WL12XX_CONF_HW_RXTX_RATE_54,
  450. WL12XX_CONF_HW_RXTX_RATE_48,
  451. WL12XX_CONF_HW_RXTX_RATE_36,
  452. WL12XX_CONF_HW_RXTX_RATE_24,
  453. WL12XX_CONF_HW_RXTX_RATE_22,
  454. WL12XX_CONF_HW_RXTX_RATE_18,
  455. WL12XX_CONF_HW_RXTX_RATE_12,
  456. WL12XX_CONF_HW_RXTX_RATE_11,
  457. WL12XX_CONF_HW_RXTX_RATE_9,
  458. WL12XX_CONF_HW_RXTX_RATE_6,
  459. WL12XX_CONF_HW_RXTX_RATE_5_5,
  460. WL12XX_CONF_HW_RXTX_RATE_2,
  461. WL12XX_CONF_HW_RXTX_RATE_1,
  462. WL12XX_CONF_HW_RXTX_RATE_MAX,
  463. };
  464. static struct wlcore_partition_set wl12xx_ptable[PART_TABLE_LEN] = {
  465. [PART_DOWN] = {
  466. .mem = {
  467. .start = 0x00000000,
  468. .size = 0x000177c0
  469. },
  470. .reg = {
  471. .start = REGISTERS_BASE,
  472. .size = 0x00008800
  473. },
  474. .mem2 = {
  475. .start = 0x00000000,
  476. .size = 0x00000000
  477. },
  478. .mem3 = {
  479. .start = 0x00000000,
  480. .size = 0x00000000
  481. },
  482. },
  483. [PART_BOOT] = { /* in wl12xx we can use a mix of work and down
  484. * partition here */
  485. .mem = {
  486. .start = 0x00040000,
  487. .size = 0x00014fc0
  488. },
  489. .reg = {
  490. .start = REGISTERS_BASE,
  491. .size = 0x00008800
  492. },
  493. .mem2 = {
  494. .start = 0x00000000,
  495. .size = 0x00000000
  496. },
  497. .mem3 = {
  498. .start = 0x00000000,
  499. .size = 0x00000000
  500. },
  501. },
  502. [PART_WORK] = {
  503. .mem = {
  504. .start = 0x00040000,
  505. .size = 0x00014fc0
  506. },
  507. .reg = {
  508. .start = REGISTERS_BASE,
  509. .size = 0x0000a000
  510. },
  511. .mem2 = {
  512. .start = 0x003004f8,
  513. .size = 0x00000004
  514. },
  515. .mem3 = {
  516. .start = 0x00040404,
  517. .size = 0x00000000
  518. },
  519. },
  520. [PART_DRPW] = {
  521. .mem = {
  522. .start = 0x00040000,
  523. .size = 0x00014fc0
  524. },
  525. .reg = {
  526. .start = DRPW_BASE,
  527. .size = 0x00006000
  528. },
  529. .mem2 = {
  530. .start = 0x00000000,
  531. .size = 0x00000000
  532. },
  533. .mem3 = {
  534. .start = 0x00000000,
  535. .size = 0x00000000
  536. }
  537. }
  538. };
  539. static const int wl12xx_rtable[REG_TABLE_LEN] = {
  540. [REG_ECPU_CONTROL] = WL12XX_REG_ECPU_CONTROL,
  541. [REG_INTERRUPT_NO_CLEAR] = WL12XX_REG_INTERRUPT_NO_CLEAR,
  542. [REG_INTERRUPT_ACK] = WL12XX_REG_INTERRUPT_ACK,
  543. [REG_COMMAND_MAILBOX_PTR] = WL12XX_REG_COMMAND_MAILBOX_PTR,
  544. [REG_EVENT_MAILBOX_PTR] = WL12XX_REG_EVENT_MAILBOX_PTR,
  545. [REG_INTERRUPT_TRIG] = WL12XX_REG_INTERRUPT_TRIG,
  546. [REG_INTERRUPT_MASK] = WL12XX_REG_INTERRUPT_MASK,
  547. [REG_PC_ON_RECOVERY] = WL12XX_SCR_PAD4,
  548. [REG_CHIP_ID_B] = WL12XX_CHIP_ID_B,
  549. [REG_CMD_MBOX_ADDRESS] = WL12XX_CMD_MBOX_ADDRESS,
  550. /* data access memory addresses, used with partition translation */
  551. [REG_SLV_MEM_DATA] = WL1271_SLV_MEM_DATA,
  552. [REG_SLV_REG_DATA] = WL1271_SLV_REG_DATA,
  553. /* raw data access memory addresses */
  554. [REG_RAW_FW_STATUS_ADDR] = FW_STATUS_ADDR,
  555. };
  556. /* TODO: maybe move to a new header file? */
  557. #define WL127X_FW_NAME_MULTI "ti-connectivity/wl127x-fw-4-mr.bin"
  558. #define WL127X_FW_NAME_SINGLE "ti-connectivity/wl127x-fw-4-sr.bin"
  559. #define WL127X_PLT_FW_NAME "ti-connectivity/wl127x-fw-4-plt.bin"
  560. #define WL128X_FW_NAME_MULTI "ti-connectivity/wl128x-fw-4-mr.bin"
  561. #define WL128X_FW_NAME_SINGLE "ti-connectivity/wl128x-fw-4-sr.bin"
  562. #define WL128X_PLT_FW_NAME "ti-connectivity/wl128x-fw-4-plt.bin"
  563. static void wl127x_prepare_read(struct wl1271 *wl, u32 rx_desc, u32 len)
  564. {
  565. if (wl->chip.id != CHIP_ID_1283_PG20) {
  566. struct wl1271_acx_mem_map *wl_mem_map = wl->target_mem_map;
  567. struct wl1271_rx_mem_pool_addr rx_mem_addr;
  568. /*
  569. * Choose the block we want to read
  570. * For aggregated packets, only the first memory block
  571. * should be retrieved. The FW takes care of the rest.
  572. */
  573. u32 mem_block = rx_desc & RX_MEM_BLOCK_MASK;
  574. rx_mem_addr.addr = (mem_block << 8) +
  575. le32_to_cpu(wl_mem_map->packet_memory_pool_start);
  576. rx_mem_addr.addr_extra = rx_mem_addr.addr + 4;
  577. wl1271_write(wl, WL1271_SLV_REG_DATA,
  578. &rx_mem_addr, sizeof(rx_mem_addr), false);
  579. }
  580. }
  581. static int wl12xx_identify_chip(struct wl1271 *wl)
  582. {
  583. int ret = 0;
  584. switch (wl->chip.id) {
  585. case CHIP_ID_1271_PG10:
  586. wl1271_warning("chip id 0x%x (1271 PG10) support is obsolete",
  587. wl->chip.id);
  588. /* clear the alignment quirk, since we don't support it */
  589. wl->quirks &= ~WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN;
  590. wl->quirks |= WLCORE_QUIRK_LEGACY_NVS;
  591. wl->sr_fw_name = WL127X_FW_NAME_SINGLE;
  592. wl->mr_fw_name = WL127X_FW_NAME_MULTI;
  593. memcpy(&wl->conf.mem, &wl12xx_default_priv_conf.mem_wl127x,
  594. sizeof(wl->conf.mem));
  595. /* read data preparation is only needed by wl127x */
  596. wl->ops->prepare_read = wl127x_prepare_read;
  597. break;
  598. case CHIP_ID_1271_PG20:
  599. wl1271_debug(DEBUG_BOOT, "chip id 0x%x (1271 PG20)",
  600. wl->chip.id);
  601. /* clear the alignment quirk, since we don't support it */
  602. wl->quirks &= ~WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN;
  603. wl->quirks |= WLCORE_QUIRK_LEGACY_NVS;
  604. wl->plt_fw_name = WL127X_PLT_FW_NAME;
  605. wl->sr_fw_name = WL127X_FW_NAME_SINGLE;
  606. wl->mr_fw_name = WL127X_FW_NAME_MULTI;
  607. memcpy(&wl->conf.mem, &wl12xx_default_priv_conf.mem_wl127x,
  608. sizeof(wl->conf.mem));
  609. /* read data preparation is only needed by wl127x */
  610. wl->ops->prepare_read = wl127x_prepare_read;
  611. break;
  612. case CHIP_ID_1283_PG20:
  613. wl1271_debug(DEBUG_BOOT, "chip id 0x%x (1283 PG20)",
  614. wl->chip.id);
  615. wl->plt_fw_name = WL128X_PLT_FW_NAME;
  616. wl->sr_fw_name = WL128X_FW_NAME_SINGLE;
  617. wl->mr_fw_name = WL128X_FW_NAME_MULTI;
  618. break;
  619. case CHIP_ID_1283_PG10:
  620. default:
  621. wl1271_warning("unsupported chip id: 0x%x", wl->chip.id);
  622. ret = -ENODEV;
  623. goto out;
  624. }
  625. out:
  626. return ret;
  627. }
  628. static void wl12xx_top_reg_write(struct wl1271 *wl, int addr, u16 val)
  629. {
  630. /* write address >> 1 + 0x30000 to OCP_POR_CTR */
  631. addr = (addr >> 1) + 0x30000;
  632. wl1271_write32(wl, WL12XX_OCP_POR_CTR, addr);
  633. /* write value to OCP_POR_WDATA */
  634. wl1271_write32(wl, WL12XX_OCP_DATA_WRITE, val);
  635. /* write 1 to OCP_CMD */
  636. wl1271_write32(wl, WL12XX_OCP_CMD, OCP_CMD_WRITE);
  637. }
  638. static u16 wl12xx_top_reg_read(struct wl1271 *wl, int addr)
  639. {
  640. u32 val;
  641. int timeout = OCP_CMD_LOOP;
  642. /* write address >> 1 + 0x30000 to OCP_POR_CTR */
  643. addr = (addr >> 1) + 0x30000;
  644. wl1271_write32(wl, WL12XX_OCP_POR_CTR, addr);
  645. /* write 2 to OCP_CMD */
  646. wl1271_write32(wl, WL12XX_OCP_CMD, OCP_CMD_READ);
  647. /* poll for data ready */
  648. do {
  649. val = wl1271_read32(wl, WL12XX_OCP_DATA_READ);
  650. } while (!(val & OCP_READY_MASK) && --timeout);
  651. if (!timeout) {
  652. wl1271_warning("Top register access timed out.");
  653. return 0xffff;
  654. }
  655. /* check data status and return if OK */
  656. if ((val & OCP_STATUS_MASK) == OCP_STATUS_OK)
  657. return val & 0xffff;
  658. else {
  659. wl1271_warning("Top register access returned error.");
  660. return 0xffff;
  661. }
  662. }
  663. static int wl128x_switch_tcxo_to_fref(struct wl1271 *wl)
  664. {
  665. u16 spare_reg;
  666. /* Mask bits [2] & [8:4] in the sys_clk_cfg register */
  667. spare_reg = wl12xx_top_reg_read(wl, WL_SPARE_REG);
  668. if (spare_reg == 0xFFFF)
  669. return -EFAULT;
  670. spare_reg |= (BIT(3) | BIT(5) | BIT(6));
  671. wl12xx_top_reg_write(wl, WL_SPARE_REG, spare_reg);
  672. /* Enable FREF_CLK_REQ & mux MCS and coex PLLs to FREF */
  673. wl12xx_top_reg_write(wl, SYS_CLK_CFG_REG,
  674. WL_CLK_REQ_TYPE_PG2 | MCS_PLL_CLK_SEL_FREF);
  675. /* Delay execution for 15msec, to let the HW settle */
  676. mdelay(15);
  677. return 0;
  678. }
  679. static bool wl128x_is_tcxo_valid(struct wl1271 *wl)
  680. {
  681. u16 tcxo_detection;
  682. tcxo_detection = wl12xx_top_reg_read(wl, TCXO_CLK_DETECT_REG);
  683. if (tcxo_detection & TCXO_DET_FAILED)
  684. return false;
  685. return true;
  686. }
  687. static bool wl128x_is_fref_valid(struct wl1271 *wl)
  688. {
  689. u16 fref_detection;
  690. fref_detection = wl12xx_top_reg_read(wl, FREF_CLK_DETECT_REG);
  691. if (fref_detection & FREF_CLK_DETECT_FAIL)
  692. return false;
  693. return true;
  694. }
  695. static int wl128x_manually_configure_mcs_pll(struct wl1271 *wl)
  696. {
  697. wl12xx_top_reg_write(wl, MCS_PLL_M_REG, MCS_PLL_M_REG_VAL);
  698. wl12xx_top_reg_write(wl, MCS_PLL_N_REG, MCS_PLL_N_REG_VAL);
  699. wl12xx_top_reg_write(wl, MCS_PLL_CONFIG_REG, MCS_PLL_CONFIG_REG_VAL);
  700. return 0;
  701. }
  702. static int wl128x_configure_mcs_pll(struct wl1271 *wl, int clk)
  703. {
  704. u16 spare_reg;
  705. u16 pll_config;
  706. u8 input_freq;
  707. /* Mask bits [3:1] in the sys_clk_cfg register */
  708. spare_reg = wl12xx_top_reg_read(wl, WL_SPARE_REG);
  709. if (spare_reg == 0xFFFF)
  710. return -EFAULT;
  711. spare_reg |= BIT(2);
  712. wl12xx_top_reg_write(wl, WL_SPARE_REG, spare_reg);
  713. /* Handle special cases of the TCXO clock */
  714. if (wl->tcxo_clock == WL12XX_TCXOCLOCK_16_8 ||
  715. wl->tcxo_clock == WL12XX_TCXOCLOCK_33_6)
  716. return wl128x_manually_configure_mcs_pll(wl);
  717. /* Set the input frequency according to the selected clock source */
  718. input_freq = (clk & 1) + 1;
  719. pll_config = wl12xx_top_reg_read(wl, MCS_PLL_CONFIG_REG);
  720. if (pll_config == 0xFFFF)
  721. return -EFAULT;
  722. pll_config |= (input_freq << MCS_SEL_IN_FREQ_SHIFT);
  723. pll_config |= MCS_PLL_ENABLE_HP;
  724. wl12xx_top_reg_write(wl, MCS_PLL_CONFIG_REG, pll_config);
  725. return 0;
  726. }
  727. /*
  728. * WL128x has two clocks input - TCXO and FREF.
  729. * TCXO is the main clock of the device, while FREF is used to sync
  730. * between the GPS and the cellular modem.
  731. * In cases where TCXO is 32.736MHz or 16.368MHz, the FREF will be used
  732. * as the WLAN/BT main clock.
  733. */
  734. static int wl128x_boot_clk(struct wl1271 *wl, int *selected_clock)
  735. {
  736. u16 sys_clk_cfg;
  737. /* For XTAL-only modes, FREF will be used after switching from TCXO */
  738. if (wl->ref_clock == WL12XX_REFCLOCK_26_XTAL ||
  739. wl->ref_clock == WL12XX_REFCLOCK_38_XTAL) {
  740. if (!wl128x_switch_tcxo_to_fref(wl))
  741. return -EINVAL;
  742. goto fref_clk;
  743. }
  744. /* Query the HW, to determine which clock source we should use */
  745. sys_clk_cfg = wl12xx_top_reg_read(wl, SYS_CLK_CFG_REG);
  746. if (sys_clk_cfg == 0xFFFF)
  747. return -EINVAL;
  748. if (sys_clk_cfg & PRCM_CM_EN_MUX_WLAN_FREF)
  749. goto fref_clk;
  750. /* If TCXO is either 32.736MHz or 16.368MHz, switch to FREF */
  751. if (wl->tcxo_clock == WL12XX_TCXOCLOCK_16_368 ||
  752. wl->tcxo_clock == WL12XX_TCXOCLOCK_32_736) {
  753. if (!wl128x_switch_tcxo_to_fref(wl))
  754. return -EINVAL;
  755. goto fref_clk;
  756. }
  757. /* TCXO clock is selected */
  758. if (!wl128x_is_tcxo_valid(wl))
  759. return -EINVAL;
  760. *selected_clock = wl->tcxo_clock;
  761. goto config_mcs_pll;
  762. fref_clk:
  763. /* FREF clock is selected */
  764. if (!wl128x_is_fref_valid(wl))
  765. return -EINVAL;
  766. *selected_clock = wl->ref_clock;
  767. config_mcs_pll:
  768. return wl128x_configure_mcs_pll(wl, *selected_clock);
  769. }
  770. static int wl127x_boot_clk(struct wl1271 *wl)
  771. {
  772. u32 pause;
  773. u32 clk;
  774. if (WL127X_PG_GET_MAJOR(wl->hw_pg_ver) < 3)
  775. wl->quirks |= WLCORE_QUIRK_END_OF_TRANSACTION;
  776. if (wl->ref_clock == CONF_REF_CLK_19_2_E ||
  777. wl->ref_clock == CONF_REF_CLK_38_4_E ||
  778. wl->ref_clock == CONF_REF_CLK_38_4_M_XTAL)
  779. /* ref clk: 19.2/38.4/38.4-XTAL */
  780. clk = 0x3;
  781. else if (wl->ref_clock == CONF_REF_CLK_26_E ||
  782. wl->ref_clock == CONF_REF_CLK_52_E)
  783. /* ref clk: 26/52 */
  784. clk = 0x5;
  785. else
  786. return -EINVAL;
  787. if (wl->ref_clock != CONF_REF_CLK_19_2_E) {
  788. u16 val;
  789. /* Set clock type (open drain) */
  790. val = wl12xx_top_reg_read(wl, OCP_REG_CLK_TYPE);
  791. val &= FREF_CLK_TYPE_BITS;
  792. wl12xx_top_reg_write(wl, OCP_REG_CLK_TYPE, val);
  793. /* Set clock pull mode (no pull) */
  794. val = wl12xx_top_reg_read(wl, OCP_REG_CLK_PULL);
  795. val |= NO_PULL;
  796. wl12xx_top_reg_write(wl, OCP_REG_CLK_PULL, val);
  797. } else {
  798. u16 val;
  799. /* Set clock polarity */
  800. val = wl12xx_top_reg_read(wl, OCP_REG_CLK_POLARITY);
  801. val &= FREF_CLK_POLARITY_BITS;
  802. val |= CLK_REQ_OUTN_SEL;
  803. wl12xx_top_reg_write(wl, OCP_REG_CLK_POLARITY, val);
  804. }
  805. wl1271_write32(wl, WL12XX_PLL_PARAMETERS, clk);
  806. pause = wl1271_read32(wl, WL12XX_PLL_PARAMETERS);
  807. wl1271_debug(DEBUG_BOOT, "pause1 0x%x", pause);
  808. pause &= ~(WU_COUNTER_PAUSE_VAL);
  809. pause |= WU_COUNTER_PAUSE_VAL;
  810. wl1271_write32(wl, WL12XX_WU_COUNTER_PAUSE, pause);
  811. return 0;
  812. }
  813. static int wl1271_boot_soft_reset(struct wl1271 *wl)
  814. {
  815. unsigned long timeout;
  816. u32 boot_data;
  817. /* perform soft reset */
  818. wl1271_write32(wl, WL12XX_SLV_SOFT_RESET, ACX_SLV_SOFT_RESET_BIT);
  819. /* SOFT_RESET is self clearing */
  820. timeout = jiffies + usecs_to_jiffies(SOFT_RESET_MAX_TIME);
  821. while (1) {
  822. boot_data = wl1271_read32(wl, WL12XX_SLV_SOFT_RESET);
  823. wl1271_debug(DEBUG_BOOT, "soft reset bootdata 0x%x", boot_data);
  824. if ((boot_data & ACX_SLV_SOFT_RESET_BIT) == 0)
  825. break;
  826. if (time_after(jiffies, timeout)) {
  827. /* 1.2 check pWhalBus->uSelfClearTime if the
  828. * timeout was reached */
  829. wl1271_error("soft reset timeout");
  830. return -1;
  831. }
  832. udelay(SOFT_RESET_STALL_TIME);
  833. }
  834. /* disable Rx/Tx */
  835. wl1271_write32(wl, WL12XX_ENABLE, 0x0);
  836. /* disable auto calibration on start*/
  837. wl1271_write32(wl, WL12XX_SPARE_A2, 0xffff);
  838. return 0;
  839. }
  840. static int wl12xx_pre_boot(struct wl1271 *wl)
  841. {
  842. int ret = 0;
  843. u32 clk;
  844. int selected_clock = -1;
  845. if (wl->chip.id == CHIP_ID_1283_PG20) {
  846. ret = wl128x_boot_clk(wl, &selected_clock);
  847. if (ret < 0)
  848. goto out;
  849. } else {
  850. ret = wl127x_boot_clk(wl);
  851. if (ret < 0)
  852. goto out;
  853. }
  854. /* Continue the ELP wake up sequence */
  855. wl1271_write32(wl, WL12XX_WELP_ARM_COMMAND, WELP_ARM_COMMAND_VAL);
  856. udelay(500);
  857. wlcore_set_partition(wl, &wl->ptable[PART_DRPW]);
  858. /* Read-modify-write DRPW_SCRATCH_START register (see next state)
  859. to be used by DRPw FW. The RTRIM value will be added by the FW
  860. before taking DRPw out of reset */
  861. clk = wl1271_read32(wl, WL12XX_DRPW_SCRATCH_START);
  862. wl1271_debug(DEBUG_BOOT, "clk2 0x%x", clk);
  863. if (wl->chip.id == CHIP_ID_1283_PG20)
  864. clk |= ((selected_clock & 0x3) << 1) << 4;
  865. else
  866. clk |= (wl->ref_clock << 1) << 4;
  867. wl1271_write32(wl, WL12XX_DRPW_SCRATCH_START, clk);
  868. wlcore_set_partition(wl, &wl->ptable[PART_WORK]);
  869. /* Disable interrupts */
  870. wlcore_write_reg(wl, REG_INTERRUPT_MASK, WL1271_ACX_INTR_ALL);
  871. ret = wl1271_boot_soft_reset(wl);
  872. if (ret < 0)
  873. goto out;
  874. out:
  875. return ret;
  876. }
  877. static void wl12xx_pre_upload(struct wl1271 *wl)
  878. {
  879. u32 tmp;
  880. /* write firmware's last address (ie. it's length) to
  881. * ACX_EEPROMLESS_IND_REG */
  882. wl1271_debug(DEBUG_BOOT, "ACX_EEPROMLESS_IND_REG");
  883. wl1271_write32(wl, WL12XX_EEPROMLESS_IND, WL12XX_EEPROMLESS_IND);
  884. tmp = wlcore_read_reg(wl, REG_CHIP_ID_B);
  885. wl1271_debug(DEBUG_BOOT, "chip id 0x%x", tmp);
  886. /* 6. read the EEPROM parameters */
  887. tmp = wl1271_read32(wl, WL12XX_SCR_PAD2);
  888. /* WL1271: The reference driver skips steps 7 to 10 (jumps directly
  889. * to upload_fw) */
  890. if (wl->chip.id == CHIP_ID_1283_PG20)
  891. wl12xx_top_reg_write(wl, SDIO_IO_DS, HCI_IO_DS_6MA);
  892. }
  893. static void wl12xx_enable_interrupts(struct wl1271 *wl)
  894. {
  895. u32 polarity;
  896. polarity = wl12xx_top_reg_read(wl, OCP_REG_POLARITY);
  897. /* We use HIGH polarity, so unset the LOW bit */
  898. polarity &= ~POLARITY_LOW;
  899. wl12xx_top_reg_write(wl, OCP_REG_POLARITY, polarity);
  900. wlcore_write_reg(wl, REG_INTERRUPT_MASK, WL1271_ACX_ALL_EVENTS_VECTOR);
  901. wlcore_enable_interrupts(wl);
  902. wlcore_write_reg(wl, REG_INTERRUPT_MASK,
  903. WL1271_ACX_INTR_ALL & ~(WL1271_INTR_MASK));
  904. wl1271_write32(wl, WL12XX_HI_CFG, HI_CFG_DEF_VAL);
  905. }
  906. static int wl12xx_boot(struct wl1271 *wl)
  907. {
  908. int ret;
  909. ret = wl12xx_pre_boot(wl);
  910. if (ret < 0)
  911. goto out;
  912. ret = wlcore_boot_upload_nvs(wl);
  913. if (ret < 0)
  914. goto out;
  915. wl12xx_pre_upload(wl);
  916. ret = wlcore_boot_upload_firmware(wl);
  917. if (ret < 0)
  918. goto out;
  919. ret = wlcore_boot_run_firmware(wl);
  920. if (ret < 0)
  921. goto out;
  922. wl12xx_enable_interrupts(wl);
  923. out:
  924. return ret;
  925. }
  926. static void wl12xx_trigger_cmd(struct wl1271 *wl, int cmd_box_addr,
  927. void *buf, size_t len)
  928. {
  929. wl1271_write(wl, cmd_box_addr, buf, len, false);
  930. wlcore_write_reg(wl, REG_INTERRUPT_TRIG, WL12XX_INTR_TRIG_CMD);
  931. }
  932. static void wl12xx_ack_event(struct wl1271 *wl)
  933. {
  934. wlcore_write_reg(wl, REG_INTERRUPT_TRIG, WL12XX_INTR_TRIG_EVENT_ACK);
  935. }
  936. static u32 wl12xx_calc_tx_blocks(struct wl1271 *wl, u32 len, u32 spare_blks)
  937. {
  938. u32 blk_size = WL12XX_TX_HW_BLOCK_SIZE;
  939. u32 align_len = wlcore_calc_packet_alignment(wl, len);
  940. return (align_len + blk_size - 1) / blk_size + spare_blks;
  941. }
  942. static void
  943. wl12xx_set_tx_desc_blocks(struct wl1271 *wl, struct wl1271_tx_hw_descr *desc,
  944. u32 blks, u32 spare_blks)
  945. {
  946. if (wl->chip.id == CHIP_ID_1283_PG20) {
  947. desc->wl128x_mem.total_mem_blocks = blks;
  948. } else {
  949. desc->wl127x_mem.extra_blocks = spare_blks;
  950. desc->wl127x_mem.total_mem_blocks = blks;
  951. }
  952. }
  953. static void
  954. wl12xx_set_tx_desc_data_len(struct wl1271 *wl, struct wl1271_tx_hw_descr *desc,
  955. struct sk_buff *skb)
  956. {
  957. u32 aligned_len = wlcore_calc_packet_alignment(wl, skb->len);
  958. if (wl->chip.id == CHIP_ID_1283_PG20) {
  959. desc->wl128x_mem.extra_bytes = aligned_len - skb->len;
  960. desc->length = cpu_to_le16(aligned_len >> 2);
  961. wl1271_debug(DEBUG_TX,
  962. "tx_fill_hdr: hlid: %d len: %d life: %d mem: %d extra: %d",
  963. desc->hlid,
  964. le16_to_cpu(desc->length),
  965. le16_to_cpu(desc->life_time),
  966. desc->wl128x_mem.total_mem_blocks,
  967. desc->wl128x_mem.extra_bytes);
  968. } else {
  969. /* calculate number of padding bytes */
  970. int pad = aligned_len - skb->len;
  971. desc->tx_attr |=
  972. cpu_to_le16(pad << TX_HW_ATTR_OFST_LAST_WORD_PAD);
  973. /* Store the aligned length in terms of words */
  974. desc->length = cpu_to_le16(aligned_len >> 2);
  975. wl1271_debug(DEBUG_TX,
  976. "tx_fill_hdr: pad: %d hlid: %d len: %d life: %d mem: %d",
  977. pad, desc->hlid,
  978. le16_to_cpu(desc->length),
  979. le16_to_cpu(desc->life_time),
  980. desc->wl127x_mem.total_mem_blocks);
  981. }
  982. }
  983. static enum wl_rx_buf_align
  984. wl12xx_get_rx_buf_align(struct wl1271 *wl, u32 rx_desc)
  985. {
  986. if (rx_desc & RX_BUF_UNALIGNED_PAYLOAD)
  987. return WLCORE_RX_BUF_UNALIGNED;
  988. return WLCORE_RX_BUF_ALIGNED;
  989. }
  990. static u32 wl12xx_get_rx_packet_len(struct wl1271 *wl, void *rx_data,
  991. u32 data_len)
  992. {
  993. struct wl1271_rx_descriptor *desc = rx_data;
  994. /* invalid packet */
  995. if (data_len < sizeof(*desc) ||
  996. data_len < sizeof(*desc) + desc->pad_len)
  997. return 0;
  998. return data_len - sizeof(*desc) - desc->pad_len;
  999. }
  1000. static void wl12xx_tx_delayed_compl(struct wl1271 *wl)
  1001. {
  1002. if (wl->fw_status->tx_results_counter == (wl->tx_results_count & 0xff))
  1003. return;
  1004. wl1271_tx_complete(wl);
  1005. }
  1006. static int wl12xx_hw_init(struct wl1271 *wl)
  1007. {
  1008. int ret;
  1009. if (wl->chip.id == CHIP_ID_1283_PG20) {
  1010. u32 host_cfg_bitmap = HOST_IF_CFG_RX_FIFO_ENABLE;
  1011. ret = wl128x_cmd_general_parms(wl);
  1012. if (ret < 0)
  1013. goto out;
  1014. ret = wl128x_cmd_radio_parms(wl);
  1015. if (ret < 0)
  1016. goto out;
  1017. if (wl->quirks & WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN)
  1018. /* Enable SDIO padding */
  1019. host_cfg_bitmap |= HOST_IF_CFG_TX_PAD_TO_SDIO_BLK;
  1020. /* Must be before wl1271_acx_init_mem_config() */
  1021. ret = wl1271_acx_host_if_cfg_bitmap(wl, host_cfg_bitmap);
  1022. if (ret < 0)
  1023. goto out;
  1024. } else {
  1025. ret = wl1271_cmd_general_parms(wl);
  1026. if (ret < 0)
  1027. goto out;
  1028. ret = wl1271_cmd_radio_parms(wl);
  1029. if (ret < 0)
  1030. goto out;
  1031. ret = wl1271_cmd_ext_radio_parms(wl);
  1032. if (ret < 0)
  1033. goto out;
  1034. }
  1035. out:
  1036. return ret;
  1037. }
  1038. static u32 wl12xx_sta_get_ap_rate_mask(struct wl1271 *wl,
  1039. struct wl12xx_vif *wlvif)
  1040. {
  1041. return wlvif->rate_set;
  1042. }
  1043. static int wl12xx_identify_fw(struct wl1271 *wl)
  1044. {
  1045. unsigned int *fw_ver = wl->chip.fw_ver;
  1046. /* Only new station firmwares support routing fw logs to the host */
  1047. if ((fw_ver[FW_VER_IF_TYPE] == FW_VER_IF_TYPE_STA) &&
  1048. (fw_ver[FW_VER_MINOR] < FW_VER_MINOR_FWLOG_STA_MIN))
  1049. wl->quirks |= WLCORE_QUIRK_FWLOG_NOT_IMPLEMENTED;
  1050. /* This feature is not yet supported for AP mode */
  1051. if (fw_ver[FW_VER_IF_TYPE] == FW_VER_IF_TYPE_AP)
  1052. wl->quirks |= WLCORE_QUIRK_FWLOG_NOT_IMPLEMENTED;
  1053. return 0;
  1054. }
  1055. static void wl12xx_conf_init(struct wl1271 *wl)
  1056. {
  1057. struct wl12xx_priv *priv = wl->priv;
  1058. /* apply driver default configuration */
  1059. memcpy(&wl->conf, &wl12xx_conf, sizeof(wl12xx_conf));
  1060. /* apply default private configuration */
  1061. memcpy(&priv->conf, &wl12xx_default_priv_conf, sizeof(priv->conf));
  1062. }
  1063. static bool wl12xx_mac_in_fuse(struct wl1271 *wl)
  1064. {
  1065. bool supported = false;
  1066. u8 major, minor;
  1067. if (wl->chip.id == CHIP_ID_1283_PG20) {
  1068. major = WL128X_PG_GET_MAJOR(wl->hw_pg_ver);
  1069. minor = WL128X_PG_GET_MINOR(wl->hw_pg_ver);
  1070. /* in wl128x we have the MAC address if the PG is >= (2, 1) */
  1071. if (major > 2 || (major == 2 && minor >= 1))
  1072. supported = true;
  1073. } else {
  1074. major = WL127X_PG_GET_MAJOR(wl->hw_pg_ver);
  1075. minor = WL127X_PG_GET_MINOR(wl->hw_pg_ver);
  1076. /* in wl127x we have the MAC address if the PG is >= (3, 1) */
  1077. if (major == 3 && minor >= 1)
  1078. supported = true;
  1079. }
  1080. wl1271_debug(DEBUG_PROBE,
  1081. "PG Ver major = %d minor = %d, MAC %s present",
  1082. major, minor, supported ? "is" : "is not");
  1083. return supported;
  1084. }
  1085. static void wl12xx_get_fuse_mac(struct wl1271 *wl)
  1086. {
  1087. u32 mac1, mac2;
  1088. wlcore_set_partition(wl, &wl->ptable[PART_DRPW]);
  1089. mac1 = wl1271_read32(wl, WL12XX_REG_FUSE_BD_ADDR_1);
  1090. mac2 = wl1271_read32(wl, WL12XX_REG_FUSE_BD_ADDR_2);
  1091. /* these are the two parts of the BD_ADDR */
  1092. wl->fuse_oui_addr = ((mac2 & 0xffff) << 8) +
  1093. ((mac1 & 0xff000000) >> 24);
  1094. wl->fuse_nic_addr = mac1 & 0xffffff;
  1095. wlcore_set_partition(wl, &wl->ptable[PART_DOWN]);
  1096. }
  1097. static s8 wl12xx_get_pg_ver(struct wl1271 *wl)
  1098. {
  1099. u32 die_info;
  1100. if (wl->chip.id == CHIP_ID_1283_PG20)
  1101. die_info = wl12xx_top_reg_read(wl, WL128X_REG_FUSE_DATA_2_1);
  1102. else
  1103. die_info = wl12xx_top_reg_read(wl, WL127X_REG_FUSE_DATA_2_1);
  1104. return (s8) (die_info & PG_VER_MASK) >> PG_VER_OFFSET;
  1105. }
  1106. static void wl12xx_get_mac(struct wl1271 *wl)
  1107. {
  1108. if (wl12xx_mac_in_fuse(wl))
  1109. wl12xx_get_fuse_mac(wl);
  1110. }
  1111. static struct wlcore_ops wl12xx_ops = {
  1112. .identify_chip = wl12xx_identify_chip,
  1113. .identify_fw = wl12xx_identify_fw,
  1114. .boot = wl12xx_boot,
  1115. .trigger_cmd = wl12xx_trigger_cmd,
  1116. .ack_event = wl12xx_ack_event,
  1117. .calc_tx_blocks = wl12xx_calc_tx_blocks,
  1118. .set_tx_desc_blocks = wl12xx_set_tx_desc_blocks,
  1119. .set_tx_desc_data_len = wl12xx_set_tx_desc_data_len,
  1120. .get_rx_buf_align = wl12xx_get_rx_buf_align,
  1121. .get_rx_packet_len = wl12xx_get_rx_packet_len,
  1122. .tx_immediate_compl = NULL,
  1123. .tx_delayed_compl = wl12xx_tx_delayed_compl,
  1124. .hw_init = wl12xx_hw_init,
  1125. .init_vif = NULL,
  1126. .sta_get_ap_rate_mask = wl12xx_sta_get_ap_rate_mask,
  1127. .get_pg_ver = wl12xx_get_pg_ver,
  1128. .get_mac = wl12xx_get_mac,
  1129. };
  1130. static struct ieee80211_sta_ht_cap wl12xx_ht_cap = {
  1131. .cap = IEEE80211_HT_CAP_GRN_FLD | IEEE80211_HT_CAP_SGI_20 |
  1132. (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT),
  1133. .ht_supported = true,
  1134. .ampdu_factor = IEEE80211_HT_MAX_AMPDU_8K,
  1135. .ampdu_density = IEEE80211_HT_MPDU_DENSITY_8,
  1136. .mcs = {
  1137. .rx_mask = { 0xff, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
  1138. .rx_highest = cpu_to_le16(72),
  1139. .tx_params = IEEE80211_HT_MCS_TX_DEFINED,
  1140. },
  1141. };
  1142. static int __devinit wl12xx_probe(struct platform_device *pdev)
  1143. {
  1144. struct wl1271 *wl;
  1145. struct ieee80211_hw *hw;
  1146. struct wl12xx_priv *priv;
  1147. hw = wlcore_alloc_hw(sizeof(*priv));
  1148. if (IS_ERR(hw)) {
  1149. wl1271_error("can't allocate hw");
  1150. return PTR_ERR(hw);
  1151. }
  1152. wl = hw->priv;
  1153. wl->ops = &wl12xx_ops;
  1154. wl->ptable = wl12xx_ptable;
  1155. wl->rtable = wl12xx_rtable;
  1156. wl->num_tx_desc = 16;
  1157. wl->normal_tx_spare = WL12XX_TX_HW_BLOCK_SPARE_DEFAULT;
  1158. wl->gem_tx_spare = WL12XX_TX_HW_BLOCK_GEM_SPARE;
  1159. wl->band_rate_to_idx = wl12xx_band_rate_to_idx;
  1160. wl->hw_tx_rate_tbl_size = WL12XX_CONF_HW_RXTX_RATE_MAX;
  1161. wl->hw_min_ht_rate = WL12XX_CONF_HW_RXTX_RATE_MCS0;
  1162. wl->fw_status_priv_len = 0;
  1163. memcpy(&wl->ht_cap, &wl12xx_ht_cap, sizeof(wl12xx_ht_cap));
  1164. wl12xx_conf_init(wl);
  1165. return wlcore_probe(wl, pdev);
  1166. }
  1167. static const struct platform_device_id wl12xx_id_table[] __devinitconst = {
  1168. { "wl12xx", 0 },
  1169. { } /* Terminating Entry */
  1170. };
  1171. MODULE_DEVICE_TABLE(platform, wl12xx_id_table);
  1172. static struct platform_driver wl12xx_driver = {
  1173. .probe = wl12xx_probe,
  1174. .remove = __devexit_p(wlcore_remove),
  1175. .id_table = wl12xx_id_table,
  1176. .driver = {
  1177. .name = "wl12xx_driver",
  1178. .owner = THIS_MODULE,
  1179. }
  1180. };
  1181. static int __init wl12xx_init(void)
  1182. {
  1183. return platform_driver_register(&wl12xx_driver);
  1184. }
  1185. module_init(wl12xx_init);
  1186. static void __exit wl12xx_exit(void)
  1187. {
  1188. platform_driver_unregister(&wl12xx_driver);
  1189. }
  1190. module_exit(wl12xx_exit);
  1191. MODULE_LICENSE("GPL v2");
  1192. MODULE_AUTHOR("Luciano Coelho <coelho@ti.com>");
  1193. MODULE_FIRMWARE(WL127X_FW_NAME_SINGLE);
  1194. MODULE_FIRMWARE(WL127X_FW_NAME_MULTI);
  1195. MODULE_FIRMWARE(WL127X_PLT_FW_NAME);
  1196. MODULE_FIRMWARE(WL128X_FW_NAME_SINGLE);
  1197. MODULE_FIRMWARE(WL128X_FW_NAME_MULTI);
  1198. MODULE_FIRMWARE(WL128X_PLT_FW_NAME);