dm.c 21 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2009-2012 Realtek Corporation.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of version 2 of the GNU General Public License as
  7. * published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program; if not, write to the Free Software Foundation, Inc.,
  16. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17. *
  18. * The full GNU General Public License is included in this distribution in the
  19. * file called LICENSE.
  20. *
  21. * Contact Information:
  22. * wlanfae <wlanfae@realtek.com>
  23. * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  24. * Hsinchu 300, Taiwan.
  25. *
  26. * Larry Finger <Larry.Finger@lwfinger.net>
  27. *
  28. *****************************************************************************/
  29. #include "../wifi.h"
  30. #include "../base.h"
  31. #include "reg.h"
  32. #include "def.h"
  33. #include "phy.h"
  34. #include "dm.h"
  35. #include "fw.h"
  36. static const u32 edca_setting_dl[PEER_MAX] = {
  37. 0xa44f, /* 0 UNKNOWN */
  38. 0x5ea44f, /* 1 REALTEK_90 */
  39. 0x5ea44f, /* 2 REALTEK_92SE */
  40. 0xa630, /* 3 BROAD */
  41. 0xa44f, /* 4 RAL */
  42. 0xa630, /* 5 ATH */
  43. 0xa630, /* 6 CISCO */
  44. 0xa42b, /* 7 MARV */
  45. };
  46. static const u32 edca_setting_dl_gmode[PEER_MAX] = {
  47. 0x4322, /* 0 UNKNOWN */
  48. 0xa44f, /* 1 REALTEK_90 */
  49. 0x5ea44f, /* 2 REALTEK_92SE */
  50. 0xa42b, /* 3 BROAD */
  51. 0x5e4322, /* 4 RAL */
  52. 0x4322, /* 5 ATH */
  53. 0xa430, /* 6 CISCO */
  54. 0x5ea44f, /* 7 MARV */
  55. };
  56. static const u32 edca_setting_ul[PEER_MAX] = {
  57. 0x5e4322, /* 0 UNKNOWN */
  58. 0xa44f, /* 1 REALTEK_90 */
  59. 0x5ea44f, /* 2 REALTEK_92SE */
  60. 0x5ea322, /* 3 BROAD */
  61. 0x5ea422, /* 4 RAL */
  62. 0x5ea322, /* 5 ATH */
  63. 0x3ea44f, /* 6 CISCO */
  64. 0x5ea44f, /* 7 MARV */
  65. };
  66. static void _rtl92s_dm_check_edca_turbo(struct ieee80211_hw *hw)
  67. {
  68. struct rtl_priv *rtlpriv = rtl_priv(hw);
  69. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  70. static u64 last_txok_cnt;
  71. static u64 last_rxok_cnt;
  72. u64 cur_txok_cnt = 0;
  73. u64 cur_rxok_cnt = 0;
  74. u32 edca_be_ul = edca_setting_ul[mac->vendor];
  75. u32 edca_be_dl = edca_setting_dl[mac->vendor];
  76. u32 edca_gmode = edca_setting_dl_gmode[mac->vendor];
  77. if (mac->link_state != MAC80211_LINKED) {
  78. rtlpriv->dm.current_turbo_edca = false;
  79. goto dm_checkedcaturbo_exit;
  80. }
  81. if ((!rtlpriv->dm.is_any_nonbepkts) &&
  82. (!rtlpriv->dm.disable_framebursting)) {
  83. cur_txok_cnt = rtlpriv->stats.txbytesunicast - last_txok_cnt;
  84. cur_rxok_cnt = rtlpriv->stats.rxbytesunicast - last_rxok_cnt;
  85. if (rtlpriv->phy.rf_type == RF_1T2R) {
  86. if (cur_txok_cnt > 4 * cur_rxok_cnt) {
  87. /* Uplink TP is present. */
  88. if (rtlpriv->dm.is_cur_rdlstate ||
  89. !rtlpriv->dm.current_turbo_edca) {
  90. rtl_write_dword(rtlpriv, EDCAPARA_BE,
  91. edca_be_ul);
  92. rtlpriv->dm.is_cur_rdlstate = false;
  93. }
  94. } else {/* Balance TP is present. */
  95. if (!rtlpriv->dm.is_cur_rdlstate ||
  96. !rtlpriv->dm.current_turbo_edca) {
  97. if (mac->mode == WIRELESS_MODE_G ||
  98. mac->mode == WIRELESS_MODE_B)
  99. rtl_write_dword(rtlpriv,
  100. EDCAPARA_BE,
  101. edca_gmode);
  102. else
  103. rtl_write_dword(rtlpriv,
  104. EDCAPARA_BE,
  105. edca_be_dl);
  106. rtlpriv->dm.is_cur_rdlstate = true;
  107. }
  108. }
  109. rtlpriv->dm.current_turbo_edca = true;
  110. } else {
  111. if (cur_rxok_cnt > 4 * cur_txok_cnt) {
  112. if (!rtlpriv->dm.is_cur_rdlstate ||
  113. !rtlpriv->dm.current_turbo_edca) {
  114. if (mac->mode == WIRELESS_MODE_G ||
  115. mac->mode == WIRELESS_MODE_B)
  116. rtl_write_dword(rtlpriv,
  117. EDCAPARA_BE,
  118. edca_gmode);
  119. else
  120. rtl_write_dword(rtlpriv,
  121. EDCAPARA_BE,
  122. edca_be_dl);
  123. rtlpriv->dm.is_cur_rdlstate = true;
  124. }
  125. } else {
  126. if (rtlpriv->dm.is_cur_rdlstate ||
  127. !rtlpriv->dm.current_turbo_edca) {
  128. rtl_write_dword(rtlpriv, EDCAPARA_BE,
  129. edca_be_ul);
  130. rtlpriv->dm.is_cur_rdlstate = false;
  131. }
  132. }
  133. rtlpriv->dm.current_turbo_edca = true;
  134. }
  135. } else {
  136. if (rtlpriv->dm.current_turbo_edca) {
  137. u8 tmp = AC0_BE;
  138. rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AC_PARAM,
  139. (u8 *)(&tmp));
  140. rtlpriv->dm.current_turbo_edca = false;
  141. }
  142. }
  143. dm_checkedcaturbo_exit:
  144. rtlpriv->dm.is_any_nonbepkts = false;
  145. last_txok_cnt = rtlpriv->stats.txbytesunicast;
  146. last_rxok_cnt = rtlpriv->stats.rxbytesunicast;
  147. }
  148. static void _rtl92s_dm_txpowertracking_callback_thermalmeter(
  149. struct ieee80211_hw *hw)
  150. {
  151. struct rtl_priv *rtlpriv = rtl_priv(hw);
  152. struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
  153. u8 thermalvalue = 0;
  154. rtlpriv->dm.txpower_trackinginit = true;
  155. thermalvalue = (u8)rtl_get_rfreg(hw, RF90_PATH_A, RF_T_METER, 0x1f);
  156. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  157. "Readback Thermal Meter = 0x%x pre thermal meter 0x%x eeprom_thermal meter 0x%x\n",
  158. thermalvalue,
  159. rtlpriv->dm.thermalvalue, rtlefuse->eeprom_thermalmeter);
  160. if (thermalvalue) {
  161. rtlpriv->dm.thermalvalue = thermalvalue;
  162. rtl92s_phy_set_fw_cmd(hw, FW_CMD_TXPWR_TRACK_THERMAL);
  163. }
  164. rtlpriv->dm.txpowercount = 0;
  165. }
  166. static void _rtl92s_dm_check_txpowertracking_thermalmeter(
  167. struct ieee80211_hw *hw)
  168. {
  169. struct rtl_priv *rtlpriv = rtl_priv(hw);
  170. struct rtl_phy *rtlphy = &(rtlpriv->phy);
  171. static u8 tm_trigger;
  172. u8 tx_power_checkcnt = 5;
  173. /* 2T2R TP issue */
  174. if (rtlphy->rf_type == RF_2T2R)
  175. return;
  176. if (!rtlpriv->dm.txpower_tracking)
  177. return;
  178. if (rtlpriv->dm.txpowercount <= tx_power_checkcnt) {
  179. rtlpriv->dm.txpowercount++;
  180. return;
  181. }
  182. if (!tm_trigger) {
  183. rtl_set_rfreg(hw, RF90_PATH_A, RF_T_METER,
  184. RFREG_OFFSET_MASK, 0x60);
  185. tm_trigger = 1;
  186. } else {
  187. _rtl92s_dm_txpowertracking_callback_thermalmeter(hw);
  188. tm_trigger = 0;
  189. }
  190. }
  191. static void _rtl92s_dm_refresh_rateadaptive_mask(struct ieee80211_hw *hw)
  192. {
  193. struct rtl_priv *rtlpriv = rtl_priv(hw);
  194. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  195. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  196. struct rate_adaptive *ra = &(rtlpriv->ra);
  197. u32 low_rssi_thresh = 0;
  198. u32 middle_rssi_thresh = 0;
  199. u32 high_rssi_thresh = 0;
  200. struct ieee80211_sta *sta = NULL;
  201. if (is_hal_stop(rtlhal))
  202. return;
  203. if (!rtlpriv->dm.useramask)
  204. return;
  205. if (!rtlpriv->dm.inform_fw_driverctrldm) {
  206. rtl92s_phy_set_fw_cmd(hw, FW_CMD_CTRL_DM_BY_DRIVER);
  207. rtlpriv->dm.inform_fw_driverctrldm = true;
  208. }
  209. rcu_read_lock();
  210. if (mac->opmode == NL80211_IFTYPE_STATION)
  211. sta = get_sta(hw, mac->vif, mac->bssid);
  212. if ((mac->link_state == MAC80211_LINKED) &&
  213. (mac->opmode == NL80211_IFTYPE_STATION)) {
  214. switch (ra->pre_ratr_state) {
  215. case DM_RATR_STA_HIGH:
  216. high_rssi_thresh = 40;
  217. middle_rssi_thresh = 30;
  218. low_rssi_thresh = 20;
  219. break;
  220. case DM_RATR_STA_MIDDLE:
  221. high_rssi_thresh = 44;
  222. middle_rssi_thresh = 30;
  223. low_rssi_thresh = 20;
  224. break;
  225. case DM_RATR_STA_LOW:
  226. high_rssi_thresh = 44;
  227. middle_rssi_thresh = 34;
  228. low_rssi_thresh = 20;
  229. break;
  230. case DM_RATR_STA_ULTRALOW:
  231. high_rssi_thresh = 44;
  232. middle_rssi_thresh = 34;
  233. low_rssi_thresh = 24;
  234. break;
  235. default:
  236. high_rssi_thresh = 44;
  237. middle_rssi_thresh = 34;
  238. low_rssi_thresh = 24;
  239. break;
  240. }
  241. if (rtlpriv->dm.undecorated_smoothed_pwdb >
  242. (long)high_rssi_thresh) {
  243. ra->ratr_state = DM_RATR_STA_HIGH;
  244. } else if (rtlpriv->dm.undecorated_smoothed_pwdb >
  245. (long)middle_rssi_thresh) {
  246. ra->ratr_state = DM_RATR_STA_LOW;
  247. } else if (rtlpriv->dm.undecorated_smoothed_pwdb >
  248. (long)low_rssi_thresh) {
  249. ra->ratr_state = DM_RATR_STA_LOW;
  250. } else {
  251. ra->ratr_state = DM_RATR_STA_ULTRALOW;
  252. }
  253. if (ra->pre_ratr_state != ra->ratr_state) {
  254. RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD,
  255. "RSSI = %ld RSSI_LEVEL = %d PreState = %d, CurState = %d\n",
  256. rtlpriv->dm.undecorated_smoothed_pwdb,
  257. ra->ratr_state,
  258. ra->pre_ratr_state, ra->ratr_state);
  259. rtlpriv->cfg->ops->update_rate_tbl(hw, sta,
  260. ra->ratr_state);
  261. ra->pre_ratr_state = ra->ratr_state;
  262. }
  263. }
  264. rcu_read_unlock();
  265. }
  266. static void _rtl92s_dm_switch_baseband_mrc(struct ieee80211_hw *hw)
  267. {
  268. struct rtl_priv *rtlpriv = rtl_priv(hw);
  269. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  270. struct rtl_phy *rtlphy = &(rtlpriv->phy);
  271. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  272. bool current_mrc;
  273. bool enable_mrc = true;
  274. long tmpentry_maxpwdb = 0;
  275. u8 rssi_a = 0;
  276. u8 rssi_b = 0;
  277. if (is_hal_stop(rtlhal))
  278. return;
  279. if ((rtlphy->rf_type == RF_1T1R) || (rtlphy->rf_type == RF_2T2R))
  280. return;
  281. rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_MRC, (u8 *)(&current_mrc));
  282. if (mac->link_state >= MAC80211_LINKED) {
  283. if (rtlpriv->dm.undecorated_smoothed_pwdb > tmpentry_maxpwdb) {
  284. rssi_a = rtlpriv->stats.rx_rssi_percentage[RF90_PATH_A];
  285. rssi_b = rtlpriv->stats.rx_rssi_percentage[RF90_PATH_B];
  286. }
  287. }
  288. /* MRC settings would NOT affect TP on Wireless B mode. */
  289. if (mac->mode != WIRELESS_MODE_B) {
  290. if ((rssi_a == 0) && (rssi_b == 0)) {
  291. enable_mrc = true;
  292. } else if (rssi_b > 30) {
  293. /* Turn on B-Path */
  294. enable_mrc = true;
  295. } else if (rssi_b < 5) {
  296. /* Turn off B-path */
  297. enable_mrc = false;
  298. /* Take care of RSSI differentiation. */
  299. } else if (rssi_a > 15 && (rssi_a >= rssi_b)) {
  300. if ((rssi_a - rssi_b) > 15)
  301. /* Turn off B-path */
  302. enable_mrc = false;
  303. else if ((rssi_a - rssi_b) < 10)
  304. /* Turn on B-Path */
  305. enable_mrc = true;
  306. else
  307. enable_mrc = current_mrc;
  308. } else {
  309. /* Turn on B-Path */
  310. enable_mrc = true;
  311. }
  312. }
  313. /* Update MRC settings if needed. */
  314. if (enable_mrc != current_mrc)
  315. rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_MRC,
  316. (u8 *)&enable_mrc);
  317. }
  318. void rtl92s_dm_init_edca_turbo(struct ieee80211_hw *hw)
  319. {
  320. struct rtl_priv *rtlpriv = rtl_priv(hw);
  321. rtlpriv->dm.current_turbo_edca = false;
  322. rtlpriv->dm.is_any_nonbepkts = false;
  323. rtlpriv->dm.is_cur_rdlstate = false;
  324. }
  325. static void _rtl92s_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw)
  326. {
  327. struct rtl_priv *rtlpriv = rtl_priv(hw);
  328. struct rate_adaptive *ra = &(rtlpriv->ra);
  329. ra->ratr_state = DM_RATR_STA_MAX;
  330. ra->pre_ratr_state = DM_RATR_STA_MAX;
  331. if (rtlpriv->dm.dm_type == DM_TYPE_BYDRIVER)
  332. rtlpriv->dm.useramask = true;
  333. else
  334. rtlpriv->dm.useramask = false;
  335. rtlpriv->dm.useramask = false;
  336. rtlpriv->dm.inform_fw_driverctrldm = false;
  337. }
  338. static void _rtl92s_dm_init_txpowertracking_thermalmeter(
  339. struct ieee80211_hw *hw)
  340. {
  341. struct rtl_priv *rtlpriv = rtl_priv(hw);
  342. rtlpriv->dm.txpower_tracking = true;
  343. rtlpriv->dm.txpowercount = 0;
  344. rtlpriv->dm.txpower_trackinginit = false;
  345. }
  346. static void _rtl92s_dm_false_alarm_counter_statistics(struct ieee80211_hw *hw)
  347. {
  348. struct rtl_priv *rtlpriv = rtl_priv(hw);
  349. struct false_alarm_statistics *falsealm_cnt = &(rtlpriv->falsealm_cnt);
  350. u32 ret_value;
  351. ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER1, MASKDWORD);
  352. falsealm_cnt->cnt_parity_fail = ((ret_value & 0xffff0000) >> 16);
  353. ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER2, MASKDWORD);
  354. falsealm_cnt->cnt_rate_illegal = (ret_value & 0xffff);
  355. falsealm_cnt->cnt_crc8_fail = ((ret_value & 0xffff0000) >> 16);
  356. ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER3, MASKDWORD);
  357. falsealm_cnt->cnt_mcs_fail = (ret_value & 0xffff);
  358. falsealm_cnt->cnt_ofdm_fail = falsealm_cnt->cnt_parity_fail +
  359. falsealm_cnt->cnt_rate_illegal + falsealm_cnt->cnt_crc8_fail +
  360. falsealm_cnt->cnt_mcs_fail;
  361. /* read CCK false alarm */
  362. ret_value = rtl_get_bbreg(hw, 0xc64, MASKDWORD);
  363. falsealm_cnt->cnt_cck_fail = (ret_value & 0xffff);
  364. falsealm_cnt->cnt_all = falsealm_cnt->cnt_ofdm_fail +
  365. falsealm_cnt->cnt_cck_fail;
  366. }
  367. static void rtl92s_backoff_enable_flag(struct ieee80211_hw *hw)
  368. {
  369. struct rtl_priv *rtlpriv = rtl_priv(hw);
  370. struct dig_t *digtable = &rtlpriv->dm_digtable;
  371. struct false_alarm_statistics *falsealm_cnt = &(rtlpriv->falsealm_cnt);
  372. if (falsealm_cnt->cnt_all > digtable->fa_highthresh) {
  373. if ((digtable->backoff_val - 6) <
  374. digtable->backoffval_range_min)
  375. digtable->backoff_val = digtable->backoffval_range_min;
  376. else
  377. digtable->backoff_val -= 6;
  378. } else if (falsealm_cnt->cnt_all < digtable->fa_lowthresh) {
  379. if ((digtable->backoff_val + 6) >
  380. digtable->backoffval_range_max)
  381. digtable->backoff_val =
  382. digtable->backoffval_range_max;
  383. else
  384. digtable->backoff_val += 6;
  385. }
  386. }
  387. static void _rtl92s_dm_initial_gain_sta_beforeconnect(struct ieee80211_hw *hw)
  388. {
  389. struct rtl_priv *rtlpriv = rtl_priv(hw);
  390. struct dig_t *digtable = &rtlpriv->dm_digtable;
  391. struct false_alarm_statistics *falsealm_cnt = &(rtlpriv->falsealm_cnt);
  392. static u8 initialized, force_write;
  393. u8 initial_gain = 0;
  394. if ((digtable->pre_sta_connectstate == digtable->cur_sta_connectstate) ||
  395. (digtable->cur_sta_connectstate == DIG_STA_BEFORE_CONNECT)) {
  396. if (digtable->cur_sta_connectstate == DIG_STA_BEFORE_CONNECT) {
  397. if (rtlpriv->psc.rfpwr_state != ERFON)
  398. return;
  399. if (digtable->backoff_enable_flag)
  400. rtl92s_backoff_enable_flag(hw);
  401. else
  402. digtable->backoff_val = DM_DIG_BACKOFF;
  403. if ((digtable->rssi_val + 10 - digtable->backoff_val) >
  404. digtable->rx_gain_range_max)
  405. digtable->cur_igvalue =
  406. digtable->rx_gain_range_max;
  407. else if ((digtable->rssi_val + 10 - digtable->backoff_val)
  408. < digtable->rx_gain_range_min)
  409. digtable->cur_igvalue =
  410. digtable->rx_gain_range_min;
  411. else
  412. digtable->cur_igvalue = digtable->rssi_val + 10 -
  413. digtable->backoff_val;
  414. if (falsealm_cnt->cnt_all > 10000)
  415. digtable->cur_igvalue =
  416. (digtable->cur_igvalue > 0x33) ?
  417. digtable->cur_igvalue : 0x33;
  418. if (falsealm_cnt->cnt_all > 16000)
  419. digtable->cur_igvalue =
  420. digtable->rx_gain_range_max;
  421. /* connected -> connected or disconnected -> disconnected */
  422. } else {
  423. /* Firmware control DIG, do nothing in driver dm */
  424. return;
  425. }
  426. /* disconnected -> connected or connected ->
  427. * disconnected or beforeconnect->(dis)connected */
  428. } else {
  429. /* Enable FW DIG */
  430. digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_MAX;
  431. rtl92s_phy_set_fw_cmd(hw, FW_CMD_DIG_ENABLE);
  432. digtable->backoff_val = DM_DIG_BACKOFF;
  433. digtable->cur_igvalue = rtlpriv->phy.default_initialgain[0];
  434. digtable->pre_igvalue = 0;
  435. return;
  436. }
  437. /* Forced writing to prevent from fw-dig overwriting. */
  438. if (digtable->pre_igvalue != rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1,
  439. MASKBYTE0))
  440. force_write = 1;
  441. if ((digtable->pre_igvalue != digtable->cur_igvalue) ||
  442. !initialized || force_write) {
  443. /* Disable FW DIG */
  444. rtl92s_phy_set_fw_cmd(hw, FW_CMD_DIG_DISABLE);
  445. initial_gain = (u8)digtable->cur_igvalue;
  446. /* Set initial gain. */
  447. rtl_set_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0, initial_gain);
  448. rtl_set_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0, initial_gain);
  449. digtable->pre_igvalue = digtable->cur_igvalue;
  450. initialized = 1;
  451. force_write = 0;
  452. }
  453. }
  454. static void _rtl92s_dm_ctrl_initgain_bytwoport(struct ieee80211_hw *hw)
  455. {
  456. struct rtl_priv *rtlpriv = rtl_priv(hw);
  457. struct dig_t *digtable = &rtlpriv->dm_digtable;
  458. if (rtlpriv->mac80211.act_scanning)
  459. return;
  460. /* Decide the current status and if modify initial gain or not */
  461. if (rtlpriv->mac80211.link_state >= MAC80211_LINKED ||
  462. rtlpriv->mac80211.opmode == NL80211_IFTYPE_ADHOC)
  463. digtable->cur_sta_connectstate = DIG_STA_CONNECT;
  464. else
  465. digtable->cur_sta_connectstate = DIG_STA_DISCONNECT;
  466. digtable->rssi_val = rtlpriv->dm.undecorated_smoothed_pwdb;
  467. /* Change dig mode to rssi */
  468. if (digtable->cur_sta_connectstate != DIG_STA_DISCONNECT) {
  469. if (digtable->dig_twoport_algorithm ==
  470. DIG_TWO_PORT_ALGO_FALSE_ALARM) {
  471. digtable->dig_twoport_algorithm = DIG_TWO_PORT_ALGO_RSSI;
  472. rtl92s_phy_set_fw_cmd(hw, FW_CMD_DIG_MODE_SS);
  473. }
  474. }
  475. _rtl92s_dm_false_alarm_counter_statistics(hw);
  476. _rtl92s_dm_initial_gain_sta_beforeconnect(hw);
  477. digtable->pre_sta_connectstate = digtable->cur_sta_connectstate;
  478. }
  479. static void _rtl92s_dm_ctrl_initgain_byrssi(struct ieee80211_hw *hw)
  480. {
  481. struct rtl_priv *rtlpriv = rtl_priv(hw);
  482. struct rtl_phy *rtlphy = &(rtlpriv->phy);
  483. struct dig_t *digtable = &rtlpriv->dm_digtable;
  484. /* 2T2R TP issue */
  485. if (rtlphy->rf_type == RF_2T2R)
  486. return;
  487. if (!rtlpriv->dm.dm_initialgain_enable)
  488. return;
  489. if (digtable->dig_enable_flag == false)
  490. return;
  491. _rtl92s_dm_ctrl_initgain_bytwoport(hw);
  492. }
  493. static void _rtl92s_dm_dynamic_txpower(struct ieee80211_hw *hw)
  494. {
  495. struct rtl_priv *rtlpriv = rtl_priv(hw);
  496. struct rtl_phy *rtlphy = &(rtlpriv->phy);
  497. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  498. long undecorated_smoothed_pwdb;
  499. long txpwr_threshold_lv1, txpwr_threshold_lv2;
  500. /* 2T2R TP issue */
  501. if (rtlphy->rf_type == RF_2T2R)
  502. return;
  503. if (!rtlpriv->dm.dynamic_txpower_enable ||
  504. rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) {
  505. rtlpriv->dm.dynamic_txhighpower_lvl = TX_HIGHPWR_LEVEL_NORMAL;
  506. return;
  507. }
  508. if ((mac->link_state < MAC80211_LINKED) &&
  509. (rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb == 0)) {
  510. RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
  511. "Not connected to any\n");
  512. rtlpriv->dm.dynamic_txhighpower_lvl = TX_HIGHPWR_LEVEL_NORMAL;
  513. rtlpriv->dm.last_dtp_lvl = TX_HIGHPWR_LEVEL_NORMAL;
  514. return;
  515. }
  516. if (mac->link_state >= MAC80211_LINKED) {
  517. if (mac->opmode == NL80211_IFTYPE_ADHOC) {
  518. undecorated_smoothed_pwdb =
  519. rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb;
  520. RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
  521. "AP Client PWDB = 0x%lx\n",
  522. undecorated_smoothed_pwdb);
  523. } else {
  524. undecorated_smoothed_pwdb =
  525. rtlpriv->dm.undecorated_smoothed_pwdb;
  526. RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
  527. "STA Default Port PWDB = 0x%lx\n",
  528. undecorated_smoothed_pwdb);
  529. }
  530. } else {
  531. undecorated_smoothed_pwdb =
  532. rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb;
  533. RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
  534. "AP Ext Port PWDB = 0x%lx\n",
  535. undecorated_smoothed_pwdb);
  536. }
  537. txpwr_threshold_lv2 = TX_POWER_NEAR_FIELD_THRESH_LVL2;
  538. txpwr_threshold_lv1 = TX_POWER_NEAR_FIELD_THRESH_LVL1;
  539. if (rtl_get_bbreg(hw, 0xc90, MASKBYTE0) == 1)
  540. rtlpriv->dm.dynamic_txhighpower_lvl = TX_HIGHPWR_LEVEL_NORMAL;
  541. else if (undecorated_smoothed_pwdb >= txpwr_threshold_lv2)
  542. rtlpriv->dm.dynamic_txhighpower_lvl = TX_HIGHPWR_LEVEL_NORMAL2;
  543. else if ((undecorated_smoothed_pwdb < (txpwr_threshold_lv2 - 3)) &&
  544. (undecorated_smoothed_pwdb >= txpwr_threshold_lv1))
  545. rtlpriv->dm.dynamic_txhighpower_lvl = TX_HIGHPWR_LEVEL_NORMAL1;
  546. else if (undecorated_smoothed_pwdb < (txpwr_threshold_lv1 - 3))
  547. rtlpriv->dm.dynamic_txhighpower_lvl = TX_HIGHPWR_LEVEL_NORMAL;
  548. if ((rtlpriv->dm.dynamic_txhighpower_lvl != rtlpriv->dm.last_dtp_lvl))
  549. rtl92s_phy_set_txpower(hw, rtlphy->current_channel);
  550. rtlpriv->dm.last_dtp_lvl = rtlpriv->dm.dynamic_txhighpower_lvl;
  551. }
  552. static void _rtl92s_dm_init_dig(struct ieee80211_hw *hw)
  553. {
  554. struct rtl_priv *rtlpriv = rtl_priv(hw);
  555. struct dig_t *digtable = &rtlpriv->dm_digtable;
  556. /* Disable DIG scheme now.*/
  557. digtable->dig_enable_flag = true;
  558. digtable->backoff_enable_flag = true;
  559. if ((rtlpriv->dm.dm_type == DM_TYPE_BYDRIVER) &&
  560. (hal_get_firmwareversion(rtlpriv) >= 0x3c))
  561. digtable->dig_algorithm = DIG_ALGO_BY_TOW_PORT;
  562. else
  563. digtable->dig_algorithm =
  564. DIG_ALGO_BEFORE_CONNECT_BY_RSSI_AND_ALARM;
  565. digtable->dig_twoport_algorithm = DIG_TWO_PORT_ALGO_RSSI;
  566. digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_MAX;
  567. /* off=by real rssi value, on=by digtable->rssi_val for new dig */
  568. digtable->dig_dbgmode = DM_DBG_OFF;
  569. digtable->dig_slgorithm_switch = 0;
  570. /* 2007/10/04 MH Define init gain threshol. */
  571. digtable->dig_state = DM_STA_DIG_MAX;
  572. digtable->dig_highpwrstate = DM_STA_DIG_MAX;
  573. digtable->cur_sta_connectstate = DIG_STA_DISCONNECT;
  574. digtable->pre_sta_connectstate = DIG_STA_DISCONNECT;
  575. digtable->cur_ap_connectstate = DIG_AP_DISCONNECT;
  576. digtable->pre_ap_connectstate = DIG_AP_DISCONNECT;
  577. digtable->rssi_lowthresh = DM_DIG_THRESH_LOW;
  578. digtable->rssi_highthresh = DM_DIG_THRESH_HIGH;
  579. digtable->fa_lowthresh = DM_FALSEALARM_THRESH_LOW;
  580. digtable->fa_highthresh = DM_FALSEALARM_THRESH_HIGH;
  581. digtable->rssi_highpower_lowthresh = DM_DIG_HIGH_PWR_THRESH_LOW;
  582. digtable->rssi_highpower_highthresh = DM_DIG_HIGH_PWR_THRESH_HIGH;
  583. /* for dig debug rssi value */
  584. digtable->rssi_val = 50;
  585. digtable->backoff_val = DM_DIG_BACKOFF;
  586. digtable->rx_gain_range_max = DM_DIG_MAX;
  587. digtable->rx_gain_range_min = DM_DIG_MIN;
  588. digtable->backoffval_range_max = DM_DIG_BACKOFF_MAX;
  589. digtable->backoffval_range_min = DM_DIG_BACKOFF_MIN;
  590. }
  591. static void _rtl92s_dm_init_dynamic_txpower(struct ieee80211_hw *hw)
  592. {
  593. struct rtl_priv *rtlpriv = rtl_priv(hw);
  594. if ((hal_get_firmwareversion(rtlpriv) >= 60) &&
  595. (rtlpriv->dm.dm_type == DM_TYPE_BYDRIVER))
  596. rtlpriv->dm.dynamic_txpower_enable = true;
  597. else
  598. rtlpriv->dm.dynamic_txpower_enable = false;
  599. rtlpriv->dm.last_dtp_lvl = TX_HIGHPWR_LEVEL_NORMAL;
  600. rtlpriv->dm.dynamic_txhighpower_lvl = TX_HIGHPWR_LEVEL_NORMAL;
  601. }
  602. void rtl92s_dm_init(struct ieee80211_hw *hw)
  603. {
  604. struct rtl_priv *rtlpriv = rtl_priv(hw);
  605. rtlpriv->dm.dm_type = DM_TYPE_BYDRIVER;
  606. rtlpriv->dm.undecorated_smoothed_pwdb = -1;
  607. _rtl92s_dm_init_dynamic_txpower(hw);
  608. rtl92s_dm_init_edca_turbo(hw);
  609. _rtl92s_dm_init_rate_adaptive_mask(hw);
  610. _rtl92s_dm_init_txpowertracking_thermalmeter(hw);
  611. _rtl92s_dm_init_dig(hw);
  612. rtl_write_dword(rtlpriv, WFM5, FW_CCA_CHK_ENABLE);
  613. }
  614. void rtl92s_dm_watchdog(struct ieee80211_hw *hw)
  615. {
  616. _rtl92s_dm_check_edca_turbo(hw);
  617. _rtl92s_dm_check_txpowertracking_thermalmeter(hw);
  618. _rtl92s_dm_ctrl_initgain_byrssi(hw);
  619. _rtl92s_dm_dynamic_txpower(hw);
  620. _rtl92s_dm_refresh_rateadaptive_mask(hw);
  621. _rtl92s_dm_switch_baseband_mrc(hw);
  622. }