xmit.c 64 KB

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  1. /*
  2. * Copyright (c) 2008-2011 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #include <linux/dma-mapping.h>
  17. #include "ath9k.h"
  18. #include "ar9003_mac.h"
  19. #define BITS_PER_BYTE 8
  20. #define OFDM_PLCP_BITS 22
  21. #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
  22. #define L_STF 8
  23. #define L_LTF 8
  24. #define L_SIG 4
  25. #define HT_SIG 8
  26. #define HT_STF 4
  27. #define HT_LTF(_ns) (4 * (_ns))
  28. #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */
  29. #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */
  30. #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
  31. #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
  32. static u16 bits_per_symbol[][2] = {
  33. /* 20MHz 40MHz */
  34. { 26, 54 }, /* 0: BPSK */
  35. { 52, 108 }, /* 1: QPSK 1/2 */
  36. { 78, 162 }, /* 2: QPSK 3/4 */
  37. { 104, 216 }, /* 3: 16-QAM 1/2 */
  38. { 156, 324 }, /* 4: 16-QAM 3/4 */
  39. { 208, 432 }, /* 5: 64-QAM 2/3 */
  40. { 234, 486 }, /* 6: 64-QAM 3/4 */
  41. { 260, 540 }, /* 7: 64-QAM 5/6 */
  42. };
  43. #define IS_HT_RATE(_rate) ((_rate) & 0x80)
  44. static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
  45. struct ath_atx_tid *tid, struct sk_buff *skb);
  46. static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
  47. int tx_flags, struct ath_txq *txq);
  48. static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
  49. struct ath_txq *txq, struct list_head *bf_q,
  50. struct ath_tx_status *ts, int txok);
  51. static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
  52. struct list_head *head, bool internal);
  53. static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
  54. struct ath_tx_status *ts, int nframes, int nbad,
  55. int txok);
  56. static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
  57. int seqno);
  58. static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
  59. struct ath_txq *txq,
  60. struct ath_atx_tid *tid,
  61. struct sk_buff *skb,
  62. bool dequeue);
  63. enum {
  64. MCS_HT20,
  65. MCS_HT20_SGI,
  66. MCS_HT40,
  67. MCS_HT40_SGI,
  68. };
  69. static int ath_max_4ms_framelen[4][32] = {
  70. [MCS_HT20] = {
  71. 3212, 6432, 9648, 12864, 19300, 25736, 28952, 32172,
  72. 6424, 12852, 19280, 25708, 38568, 51424, 57852, 64280,
  73. 9628, 19260, 28896, 38528, 57792, 65532, 65532, 65532,
  74. 12828, 25656, 38488, 51320, 65532, 65532, 65532, 65532,
  75. },
  76. [MCS_HT20_SGI] = {
  77. 3572, 7144, 10720, 14296, 21444, 28596, 32172, 35744,
  78. 7140, 14284, 21428, 28568, 42856, 57144, 64288, 65532,
  79. 10700, 21408, 32112, 42816, 64228, 65532, 65532, 65532,
  80. 14256, 28516, 42780, 57040, 65532, 65532, 65532, 65532,
  81. },
  82. [MCS_HT40] = {
  83. 6680, 13360, 20044, 26724, 40092, 53456, 60140, 65532,
  84. 13348, 26700, 40052, 53400, 65532, 65532, 65532, 65532,
  85. 20004, 40008, 60016, 65532, 65532, 65532, 65532, 65532,
  86. 26644, 53292, 65532, 65532, 65532, 65532, 65532, 65532,
  87. },
  88. [MCS_HT40_SGI] = {
  89. 7420, 14844, 22272, 29696, 44544, 59396, 65532, 65532,
  90. 14832, 29668, 44504, 59340, 65532, 65532, 65532, 65532,
  91. 22232, 44464, 65532, 65532, 65532, 65532, 65532, 65532,
  92. 29616, 59232, 65532, 65532, 65532, 65532, 65532, 65532,
  93. }
  94. };
  95. /*********************/
  96. /* Aggregation logic */
  97. /*********************/
  98. static void ath_txq_lock(struct ath_softc *sc, struct ath_txq *txq)
  99. __acquires(&txq->axq_lock)
  100. {
  101. spin_lock_bh(&txq->axq_lock);
  102. }
  103. static void ath_txq_unlock(struct ath_softc *sc, struct ath_txq *txq)
  104. __releases(&txq->axq_lock)
  105. {
  106. spin_unlock_bh(&txq->axq_lock);
  107. }
  108. static void ath_txq_unlock_complete(struct ath_softc *sc, struct ath_txq *txq)
  109. __releases(&txq->axq_lock)
  110. {
  111. struct sk_buff_head q;
  112. struct sk_buff *skb;
  113. __skb_queue_head_init(&q);
  114. skb_queue_splice_init(&txq->complete_q, &q);
  115. spin_unlock_bh(&txq->axq_lock);
  116. while ((skb = __skb_dequeue(&q)))
  117. ieee80211_tx_status(sc->hw, skb);
  118. }
  119. static void ath_tx_queue_tid(struct ath_txq *txq, struct ath_atx_tid *tid)
  120. {
  121. struct ath_atx_ac *ac = tid->ac;
  122. if (tid->paused)
  123. return;
  124. if (tid->sched)
  125. return;
  126. tid->sched = true;
  127. list_add_tail(&tid->list, &ac->tid_q);
  128. if (ac->sched)
  129. return;
  130. ac->sched = true;
  131. list_add_tail(&ac->list, &txq->axq_acq);
  132. }
  133. static void ath_tx_resume_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
  134. {
  135. struct ath_txq *txq = tid->ac->txq;
  136. WARN_ON(!tid->paused);
  137. ath_txq_lock(sc, txq);
  138. tid->paused = false;
  139. if (skb_queue_empty(&tid->buf_q))
  140. goto unlock;
  141. ath_tx_queue_tid(txq, tid);
  142. ath_txq_schedule(sc, txq);
  143. unlock:
  144. ath_txq_unlock_complete(sc, txq);
  145. }
  146. static struct ath_frame_info *get_frame_info(struct sk_buff *skb)
  147. {
  148. struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
  149. BUILD_BUG_ON(sizeof(struct ath_frame_info) >
  150. sizeof(tx_info->rate_driver_data));
  151. return (struct ath_frame_info *) &tx_info->rate_driver_data[0];
  152. }
  153. static void ath_send_bar(struct ath_atx_tid *tid, u16 seqno)
  154. {
  155. ieee80211_send_bar(tid->an->vif, tid->an->sta->addr, tid->tidno,
  156. seqno << IEEE80211_SEQ_SEQ_SHIFT);
  157. }
  158. static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
  159. {
  160. struct ath_txq *txq = tid->ac->txq;
  161. struct sk_buff *skb;
  162. struct ath_buf *bf;
  163. struct list_head bf_head;
  164. struct ath_tx_status ts;
  165. struct ath_frame_info *fi;
  166. bool sendbar = false;
  167. INIT_LIST_HEAD(&bf_head);
  168. memset(&ts, 0, sizeof(ts));
  169. while ((skb = __skb_dequeue(&tid->buf_q))) {
  170. fi = get_frame_info(skb);
  171. bf = fi->bf;
  172. if (bf && fi->retries) {
  173. list_add_tail(&bf->list, &bf_head);
  174. ath_tx_update_baw(sc, tid, bf->bf_state.seqno);
  175. ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0);
  176. sendbar = true;
  177. } else {
  178. ath_tx_send_normal(sc, txq, NULL, skb);
  179. }
  180. }
  181. if (tid->baw_head == tid->baw_tail) {
  182. tid->state &= ~AGGR_ADDBA_COMPLETE;
  183. tid->state &= ~AGGR_CLEANUP;
  184. }
  185. if (sendbar) {
  186. ath_txq_unlock(sc, txq);
  187. ath_send_bar(tid, tid->seq_start);
  188. ath_txq_lock(sc, txq);
  189. }
  190. }
  191. static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
  192. int seqno)
  193. {
  194. int index, cindex;
  195. index = ATH_BA_INDEX(tid->seq_start, seqno);
  196. cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
  197. __clear_bit(cindex, tid->tx_buf);
  198. while (tid->baw_head != tid->baw_tail && !test_bit(tid->baw_head, tid->tx_buf)) {
  199. INCR(tid->seq_start, IEEE80211_SEQ_MAX);
  200. INCR(tid->baw_head, ATH_TID_MAX_BUFS);
  201. if (tid->bar_index >= 0)
  202. tid->bar_index--;
  203. }
  204. }
  205. static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
  206. u16 seqno)
  207. {
  208. int index, cindex;
  209. index = ATH_BA_INDEX(tid->seq_start, seqno);
  210. cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
  211. __set_bit(cindex, tid->tx_buf);
  212. if (index >= ((tid->baw_tail - tid->baw_head) &
  213. (ATH_TID_MAX_BUFS - 1))) {
  214. tid->baw_tail = cindex;
  215. INCR(tid->baw_tail, ATH_TID_MAX_BUFS);
  216. }
  217. }
  218. /*
  219. * TODO: For frame(s) that are in the retry state, we will reuse the
  220. * sequence number(s) without setting the retry bit. The
  221. * alternative is to give up on these and BAR the receiver's window
  222. * forward.
  223. */
  224. static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq,
  225. struct ath_atx_tid *tid)
  226. {
  227. struct sk_buff *skb;
  228. struct ath_buf *bf;
  229. struct list_head bf_head;
  230. struct ath_tx_status ts;
  231. struct ath_frame_info *fi;
  232. memset(&ts, 0, sizeof(ts));
  233. INIT_LIST_HEAD(&bf_head);
  234. while ((skb = __skb_dequeue(&tid->buf_q))) {
  235. fi = get_frame_info(skb);
  236. bf = fi->bf;
  237. if (!bf) {
  238. ath_tx_complete(sc, skb, ATH_TX_ERROR, txq);
  239. continue;
  240. }
  241. list_add_tail(&bf->list, &bf_head);
  242. if (fi->retries)
  243. ath_tx_update_baw(sc, tid, bf->bf_state.seqno);
  244. ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0);
  245. }
  246. tid->seq_next = tid->seq_start;
  247. tid->baw_tail = tid->baw_head;
  248. tid->bar_index = -1;
  249. }
  250. static void ath_tx_set_retry(struct ath_softc *sc, struct ath_txq *txq,
  251. struct sk_buff *skb, int count)
  252. {
  253. struct ath_frame_info *fi = get_frame_info(skb);
  254. struct ath_buf *bf = fi->bf;
  255. struct ieee80211_hdr *hdr;
  256. int prev = fi->retries;
  257. TX_STAT_INC(txq->axq_qnum, a_retries);
  258. fi->retries += count;
  259. if (prev > 0)
  260. return;
  261. hdr = (struct ieee80211_hdr *)skb->data;
  262. hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY);
  263. dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
  264. sizeof(*hdr), DMA_TO_DEVICE);
  265. }
  266. static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc)
  267. {
  268. struct ath_buf *bf = NULL;
  269. spin_lock_bh(&sc->tx.txbuflock);
  270. if (unlikely(list_empty(&sc->tx.txbuf))) {
  271. spin_unlock_bh(&sc->tx.txbuflock);
  272. return NULL;
  273. }
  274. bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list);
  275. list_del(&bf->list);
  276. spin_unlock_bh(&sc->tx.txbuflock);
  277. return bf;
  278. }
  279. static void ath_tx_return_buffer(struct ath_softc *sc, struct ath_buf *bf)
  280. {
  281. spin_lock_bh(&sc->tx.txbuflock);
  282. list_add_tail(&bf->list, &sc->tx.txbuf);
  283. spin_unlock_bh(&sc->tx.txbuflock);
  284. }
  285. static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf)
  286. {
  287. struct ath_buf *tbf;
  288. tbf = ath_tx_get_buffer(sc);
  289. if (WARN_ON(!tbf))
  290. return NULL;
  291. ATH_TXBUF_RESET(tbf);
  292. tbf->bf_mpdu = bf->bf_mpdu;
  293. tbf->bf_buf_addr = bf->bf_buf_addr;
  294. memcpy(tbf->bf_desc, bf->bf_desc, sc->sc_ah->caps.tx_desc_len);
  295. tbf->bf_state = bf->bf_state;
  296. return tbf;
  297. }
  298. static void ath_tx_count_frames(struct ath_softc *sc, struct ath_buf *bf,
  299. struct ath_tx_status *ts, int txok,
  300. int *nframes, int *nbad)
  301. {
  302. struct ath_frame_info *fi;
  303. u16 seq_st = 0;
  304. u32 ba[WME_BA_BMP_SIZE >> 5];
  305. int ba_index;
  306. int isaggr = 0;
  307. *nbad = 0;
  308. *nframes = 0;
  309. isaggr = bf_isaggr(bf);
  310. if (isaggr) {
  311. seq_st = ts->ts_seqnum;
  312. memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
  313. }
  314. while (bf) {
  315. fi = get_frame_info(bf->bf_mpdu);
  316. ba_index = ATH_BA_INDEX(seq_st, bf->bf_state.seqno);
  317. (*nframes)++;
  318. if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index)))
  319. (*nbad)++;
  320. bf = bf->bf_next;
  321. }
  322. }
  323. static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
  324. struct ath_buf *bf, struct list_head *bf_q,
  325. struct ath_tx_status *ts, int txok, bool retry)
  326. {
  327. struct ath_node *an = NULL;
  328. struct sk_buff *skb;
  329. struct ieee80211_sta *sta;
  330. struct ieee80211_hw *hw = sc->hw;
  331. struct ieee80211_hdr *hdr;
  332. struct ieee80211_tx_info *tx_info;
  333. struct ath_atx_tid *tid = NULL;
  334. struct ath_buf *bf_next, *bf_last = bf->bf_lastbf;
  335. struct list_head bf_head;
  336. struct sk_buff_head bf_pending;
  337. u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0, seq_first;
  338. u32 ba[WME_BA_BMP_SIZE >> 5];
  339. int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0;
  340. bool rc_update = true;
  341. struct ieee80211_tx_rate rates[4];
  342. struct ath_frame_info *fi;
  343. int nframes;
  344. u8 tidno;
  345. bool flush = !!(ts->ts_status & ATH9K_TX_FLUSH);
  346. int i, retries;
  347. int bar_index = -1;
  348. skb = bf->bf_mpdu;
  349. hdr = (struct ieee80211_hdr *)skb->data;
  350. tx_info = IEEE80211_SKB_CB(skb);
  351. memcpy(rates, tx_info->control.rates, sizeof(rates));
  352. retries = ts->ts_longretry + 1;
  353. for (i = 0; i < ts->ts_rateindex; i++)
  354. retries += rates[i].count;
  355. rcu_read_lock();
  356. sta = ieee80211_find_sta_by_ifaddr(hw, hdr->addr1, hdr->addr2);
  357. if (!sta) {
  358. rcu_read_unlock();
  359. INIT_LIST_HEAD(&bf_head);
  360. while (bf) {
  361. bf_next = bf->bf_next;
  362. if (!bf->bf_stale || bf_next != NULL)
  363. list_move_tail(&bf->list, &bf_head);
  364. ath_tx_complete_buf(sc, bf, txq, &bf_head, ts, 0);
  365. bf = bf_next;
  366. }
  367. return;
  368. }
  369. an = (struct ath_node *)sta->drv_priv;
  370. tidno = ieee80211_get_qos_ctl(hdr)[0] & IEEE80211_QOS_CTL_TID_MASK;
  371. tid = ATH_AN_2_TID(an, tidno);
  372. seq_first = tid->seq_start;
  373. /*
  374. * The hardware occasionally sends a tx status for the wrong TID.
  375. * In this case, the BA status cannot be considered valid and all
  376. * subframes need to be retransmitted
  377. */
  378. if (tidno != ts->tid)
  379. txok = false;
  380. isaggr = bf_isaggr(bf);
  381. memset(ba, 0, WME_BA_BMP_SIZE >> 3);
  382. if (isaggr && txok) {
  383. if (ts->ts_flags & ATH9K_TX_BA) {
  384. seq_st = ts->ts_seqnum;
  385. memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
  386. } else {
  387. /*
  388. * AR5416 can become deaf/mute when BA
  389. * issue happens. Chip needs to be reset.
  390. * But AP code may have sychronization issues
  391. * when perform internal reset in this routine.
  392. * Only enable reset in STA mode for now.
  393. */
  394. if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION)
  395. needreset = 1;
  396. }
  397. }
  398. __skb_queue_head_init(&bf_pending);
  399. ath_tx_count_frames(sc, bf, ts, txok, &nframes, &nbad);
  400. while (bf) {
  401. u16 seqno = bf->bf_state.seqno;
  402. txfail = txpending = sendbar = 0;
  403. bf_next = bf->bf_next;
  404. skb = bf->bf_mpdu;
  405. tx_info = IEEE80211_SKB_CB(skb);
  406. fi = get_frame_info(skb);
  407. if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, seqno))) {
  408. /* transmit completion, subframe is
  409. * acked by block ack */
  410. acked_cnt++;
  411. } else if (!isaggr && txok) {
  412. /* transmit completion */
  413. acked_cnt++;
  414. } else if ((tid->state & AGGR_CLEANUP) || !retry) {
  415. /*
  416. * cleanup in progress, just fail
  417. * the un-acked sub-frames
  418. */
  419. txfail = 1;
  420. } else if (flush) {
  421. txpending = 1;
  422. } else if (fi->retries < ATH_MAX_SW_RETRIES) {
  423. if (txok || !an->sleeping)
  424. ath_tx_set_retry(sc, txq, bf->bf_mpdu,
  425. retries);
  426. txpending = 1;
  427. } else {
  428. txfail = 1;
  429. txfail_cnt++;
  430. bar_index = max_t(int, bar_index,
  431. ATH_BA_INDEX(seq_first, seqno));
  432. }
  433. /*
  434. * Make sure the last desc is reclaimed if it
  435. * not a holding desc.
  436. */
  437. INIT_LIST_HEAD(&bf_head);
  438. if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) ||
  439. bf_next != NULL || !bf_last->bf_stale)
  440. list_move_tail(&bf->list, &bf_head);
  441. if (!txpending || (tid->state & AGGR_CLEANUP)) {
  442. /*
  443. * complete the acked-ones/xretried ones; update
  444. * block-ack window
  445. */
  446. ath_tx_update_baw(sc, tid, seqno);
  447. if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) {
  448. memcpy(tx_info->control.rates, rates, sizeof(rates));
  449. ath_tx_rc_status(sc, bf, ts, nframes, nbad, txok);
  450. rc_update = false;
  451. }
  452. ath_tx_complete_buf(sc, bf, txq, &bf_head, ts,
  453. !txfail);
  454. } else {
  455. /* retry the un-acked ones */
  456. if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
  457. bf->bf_next == NULL && bf_last->bf_stale) {
  458. struct ath_buf *tbf;
  459. tbf = ath_clone_txbuf(sc, bf_last);
  460. /*
  461. * Update tx baw and complete the
  462. * frame with failed status if we
  463. * run out of tx buf.
  464. */
  465. if (!tbf) {
  466. ath_tx_update_baw(sc, tid, seqno);
  467. ath_tx_complete_buf(sc, bf, txq,
  468. &bf_head, ts, 0);
  469. bar_index = max_t(int, bar_index,
  470. ATH_BA_INDEX(seq_first, seqno));
  471. break;
  472. }
  473. fi->bf = tbf;
  474. }
  475. /*
  476. * Put this buffer to the temporary pending
  477. * queue to retain ordering
  478. */
  479. __skb_queue_tail(&bf_pending, skb);
  480. }
  481. bf = bf_next;
  482. }
  483. /* prepend un-acked frames to the beginning of the pending frame queue */
  484. if (!skb_queue_empty(&bf_pending)) {
  485. if (an->sleeping)
  486. ieee80211_sta_set_buffered(sta, tid->tidno, true);
  487. skb_queue_splice(&bf_pending, &tid->buf_q);
  488. if (!an->sleeping) {
  489. ath_tx_queue_tid(txq, tid);
  490. if (ts->ts_status & ATH9K_TXERR_FILT)
  491. tid->ac->clear_ps_filter = true;
  492. }
  493. }
  494. if (bar_index >= 0) {
  495. u16 bar_seq = ATH_BA_INDEX2SEQ(seq_first, bar_index);
  496. if (BAW_WITHIN(tid->seq_start, tid->baw_size, bar_seq))
  497. tid->bar_index = ATH_BA_INDEX(tid->seq_start, bar_seq);
  498. ath_txq_unlock(sc, txq);
  499. ath_send_bar(tid, ATH_BA_INDEX2SEQ(seq_first, bar_index + 1));
  500. ath_txq_lock(sc, txq);
  501. }
  502. if (tid->state & AGGR_CLEANUP)
  503. ath_tx_flush_tid(sc, tid);
  504. rcu_read_unlock();
  505. if (needreset) {
  506. RESET_STAT_INC(sc, RESET_TYPE_TX_ERROR);
  507. ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
  508. }
  509. }
  510. static bool ath_lookup_legacy(struct ath_buf *bf)
  511. {
  512. struct sk_buff *skb;
  513. struct ieee80211_tx_info *tx_info;
  514. struct ieee80211_tx_rate *rates;
  515. int i;
  516. skb = bf->bf_mpdu;
  517. tx_info = IEEE80211_SKB_CB(skb);
  518. rates = tx_info->control.rates;
  519. for (i = 0; i < 4; i++) {
  520. if (!rates[i].count || rates[i].idx < 0)
  521. break;
  522. if (!(rates[i].flags & IEEE80211_TX_RC_MCS))
  523. return true;
  524. }
  525. return false;
  526. }
  527. static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf,
  528. struct ath_atx_tid *tid)
  529. {
  530. struct sk_buff *skb;
  531. struct ieee80211_tx_info *tx_info;
  532. struct ieee80211_tx_rate *rates;
  533. u32 max_4ms_framelen, frmlen;
  534. u16 aggr_limit, bt_aggr_limit, legacy = 0;
  535. int i;
  536. skb = bf->bf_mpdu;
  537. tx_info = IEEE80211_SKB_CB(skb);
  538. rates = tx_info->control.rates;
  539. /*
  540. * Find the lowest frame length among the rate series that will have a
  541. * 4ms transmit duration.
  542. * TODO - TXOP limit needs to be considered.
  543. */
  544. max_4ms_framelen = ATH_AMPDU_LIMIT_MAX;
  545. for (i = 0; i < 4; i++) {
  546. int modeidx;
  547. if (!rates[i].count)
  548. continue;
  549. if (!(rates[i].flags & IEEE80211_TX_RC_MCS)) {
  550. legacy = 1;
  551. break;
  552. }
  553. if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
  554. modeidx = MCS_HT40;
  555. else
  556. modeidx = MCS_HT20;
  557. if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
  558. modeidx++;
  559. frmlen = ath_max_4ms_framelen[modeidx][rates[i].idx];
  560. max_4ms_framelen = min(max_4ms_framelen, frmlen);
  561. }
  562. /*
  563. * limit aggregate size by the minimum rate if rate selected is
  564. * not a probe rate, if rate selected is a probe rate then
  565. * avoid aggregation of this packet.
  566. */
  567. if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy)
  568. return 0;
  569. aggr_limit = min(max_4ms_framelen, (u32)ATH_AMPDU_LIMIT_MAX);
  570. /*
  571. * Override the default aggregation limit for BTCOEX.
  572. */
  573. bt_aggr_limit = ath9k_btcoex_aggr_limit(sc, max_4ms_framelen);
  574. if (bt_aggr_limit)
  575. aggr_limit = bt_aggr_limit;
  576. /*
  577. * h/w can accept aggregates up to 16 bit lengths (65535).
  578. * The IE, however can hold up to 65536, which shows up here
  579. * as zero. Ignore 65536 since we are constrained by hw.
  580. */
  581. if (tid->an->maxampdu)
  582. aggr_limit = min(aggr_limit, tid->an->maxampdu);
  583. return aggr_limit;
  584. }
  585. /*
  586. * Returns the number of delimiters to be added to
  587. * meet the minimum required mpdudensity.
  588. */
  589. static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid,
  590. struct ath_buf *bf, u16 frmlen,
  591. bool first_subfrm)
  592. {
  593. #define FIRST_DESC_NDELIMS 60
  594. struct sk_buff *skb = bf->bf_mpdu;
  595. struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
  596. u32 nsymbits, nsymbols;
  597. u16 minlen;
  598. u8 flags, rix;
  599. int width, streams, half_gi, ndelim, mindelim;
  600. struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
  601. /* Select standard number of delimiters based on frame length alone */
  602. ndelim = ATH_AGGR_GET_NDELIM(frmlen);
  603. /*
  604. * If encryption enabled, hardware requires some more padding between
  605. * subframes.
  606. * TODO - this could be improved to be dependent on the rate.
  607. * The hardware can keep up at lower rates, but not higher rates
  608. */
  609. if ((fi->keyix != ATH9K_TXKEYIX_INVALID) &&
  610. !(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA))
  611. ndelim += ATH_AGGR_ENCRYPTDELIM;
  612. /*
  613. * Add delimiter when using RTS/CTS with aggregation
  614. * and non enterprise AR9003 card
  615. */
  616. if (first_subfrm && !AR_SREV_9580_10_OR_LATER(sc->sc_ah) &&
  617. (sc->sc_ah->ent_mode & AR_ENT_OTP_MIN_PKT_SIZE_DISABLE))
  618. ndelim = max(ndelim, FIRST_DESC_NDELIMS);
  619. /*
  620. * Convert desired mpdu density from microeconds to bytes based
  621. * on highest rate in rate series (i.e. first rate) to determine
  622. * required minimum length for subframe. Take into account
  623. * whether high rate is 20 or 40Mhz and half or full GI.
  624. *
  625. * If there is no mpdu density restriction, no further calculation
  626. * is needed.
  627. */
  628. if (tid->an->mpdudensity == 0)
  629. return ndelim;
  630. rix = tx_info->control.rates[0].idx;
  631. flags = tx_info->control.rates[0].flags;
  632. width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0;
  633. half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0;
  634. if (half_gi)
  635. nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(tid->an->mpdudensity);
  636. else
  637. nsymbols = NUM_SYMBOLS_PER_USEC(tid->an->mpdudensity);
  638. if (nsymbols == 0)
  639. nsymbols = 1;
  640. streams = HT_RC_2_STREAMS(rix);
  641. nsymbits = bits_per_symbol[rix % 8][width] * streams;
  642. minlen = (nsymbols * nsymbits) / BITS_PER_BYTE;
  643. if (frmlen < minlen) {
  644. mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ;
  645. ndelim = max(mindelim, ndelim);
  646. }
  647. return ndelim;
  648. }
  649. static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc,
  650. struct ath_txq *txq,
  651. struct ath_atx_tid *tid,
  652. struct list_head *bf_q,
  653. int *aggr_len)
  654. {
  655. #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
  656. struct ath_buf *bf, *bf_first = NULL, *bf_prev = NULL;
  657. int rl = 0, nframes = 0, ndelim, prev_al = 0;
  658. u16 aggr_limit = 0, al = 0, bpad = 0,
  659. al_delta, h_baw = tid->baw_size / 2;
  660. enum ATH_AGGR_STATUS status = ATH_AGGR_DONE;
  661. struct ieee80211_tx_info *tx_info;
  662. struct ath_frame_info *fi;
  663. struct sk_buff *skb;
  664. u16 seqno;
  665. do {
  666. skb = skb_peek(&tid->buf_q);
  667. fi = get_frame_info(skb);
  668. bf = fi->bf;
  669. if (!fi->bf)
  670. bf = ath_tx_setup_buffer(sc, txq, tid, skb, true);
  671. if (!bf)
  672. continue;
  673. bf->bf_state.bf_type = BUF_AMPDU | BUF_AGGR;
  674. seqno = bf->bf_state.seqno;
  675. /* do not step over block-ack window */
  676. if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno)) {
  677. status = ATH_AGGR_BAW_CLOSED;
  678. break;
  679. }
  680. if (tid->bar_index > ATH_BA_INDEX(tid->seq_start, seqno)) {
  681. struct ath_tx_status ts = {};
  682. struct list_head bf_head;
  683. INIT_LIST_HEAD(&bf_head);
  684. list_add(&bf->list, &bf_head);
  685. __skb_unlink(skb, &tid->buf_q);
  686. ath_tx_update_baw(sc, tid, seqno);
  687. ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0);
  688. continue;
  689. }
  690. if (!bf_first)
  691. bf_first = bf;
  692. if (!rl) {
  693. aggr_limit = ath_lookup_rate(sc, bf, tid);
  694. rl = 1;
  695. }
  696. /* do not exceed aggregation limit */
  697. al_delta = ATH_AGGR_DELIM_SZ + fi->framelen;
  698. if (nframes &&
  699. ((aggr_limit < (al + bpad + al_delta + prev_al)) ||
  700. ath_lookup_legacy(bf))) {
  701. status = ATH_AGGR_LIMITED;
  702. break;
  703. }
  704. tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
  705. if (nframes && (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE))
  706. break;
  707. /* do not exceed subframe limit */
  708. if (nframes >= min((int)h_baw, ATH_AMPDU_SUBFRAME_DEFAULT)) {
  709. status = ATH_AGGR_LIMITED;
  710. break;
  711. }
  712. /* add padding for previous frame to aggregation length */
  713. al += bpad + al_delta;
  714. /*
  715. * Get the delimiters needed to meet the MPDU
  716. * density for this node.
  717. */
  718. ndelim = ath_compute_num_delims(sc, tid, bf_first, fi->framelen,
  719. !nframes);
  720. bpad = PADBYTES(al_delta) + (ndelim << 2);
  721. nframes++;
  722. bf->bf_next = NULL;
  723. /* link buffers of this frame to the aggregate */
  724. if (!fi->retries)
  725. ath_tx_addto_baw(sc, tid, seqno);
  726. bf->bf_state.ndelim = ndelim;
  727. __skb_unlink(skb, &tid->buf_q);
  728. list_add_tail(&bf->list, bf_q);
  729. if (bf_prev)
  730. bf_prev->bf_next = bf;
  731. bf_prev = bf;
  732. } while (!skb_queue_empty(&tid->buf_q));
  733. *aggr_len = al;
  734. return status;
  735. #undef PADBYTES
  736. }
  737. /*
  738. * rix - rate index
  739. * pktlen - total bytes (delims + data + fcs + pads + pad delims)
  740. * width - 0 for 20 MHz, 1 for 40 MHz
  741. * half_gi - to use 4us v/s 3.6 us for symbol time
  742. */
  743. static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, int pktlen,
  744. int width, int half_gi, bool shortPreamble)
  745. {
  746. u32 nbits, nsymbits, duration, nsymbols;
  747. int streams;
  748. /* find number of symbols: PLCP + data */
  749. streams = HT_RC_2_STREAMS(rix);
  750. nbits = (pktlen << 3) + OFDM_PLCP_BITS;
  751. nsymbits = bits_per_symbol[rix % 8][width] * streams;
  752. nsymbols = (nbits + nsymbits - 1) / nsymbits;
  753. if (!half_gi)
  754. duration = SYMBOL_TIME(nsymbols);
  755. else
  756. duration = SYMBOL_TIME_HALFGI(nsymbols);
  757. /* addup duration for legacy/ht training and signal fields */
  758. duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
  759. return duration;
  760. }
  761. static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf,
  762. struct ath_tx_info *info, int len)
  763. {
  764. struct ath_hw *ah = sc->sc_ah;
  765. struct sk_buff *skb;
  766. struct ieee80211_tx_info *tx_info;
  767. struct ieee80211_tx_rate *rates;
  768. const struct ieee80211_rate *rate;
  769. struct ieee80211_hdr *hdr;
  770. int i;
  771. u8 rix = 0;
  772. skb = bf->bf_mpdu;
  773. tx_info = IEEE80211_SKB_CB(skb);
  774. rates = tx_info->control.rates;
  775. hdr = (struct ieee80211_hdr *)skb->data;
  776. /* set dur_update_en for l-sig computation except for PS-Poll frames */
  777. info->dur_update = !ieee80211_is_pspoll(hdr->frame_control);
  778. /*
  779. * We check if Short Preamble is needed for the CTS rate by
  780. * checking the BSS's global flag.
  781. * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used.
  782. */
  783. rate = ieee80211_get_rts_cts_rate(sc->hw, tx_info);
  784. info->rtscts_rate = rate->hw_value;
  785. if (tx_info->control.vif &&
  786. tx_info->control.vif->bss_conf.use_short_preamble)
  787. info->rtscts_rate |= rate->hw_value_short;
  788. for (i = 0; i < 4; i++) {
  789. bool is_40, is_sgi, is_sp;
  790. int phy;
  791. if (!rates[i].count || (rates[i].idx < 0))
  792. continue;
  793. rix = rates[i].idx;
  794. info->rates[i].Tries = rates[i].count;
  795. if (rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
  796. info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
  797. info->flags |= ATH9K_TXDESC_RTSENA;
  798. } else if (rates[i].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
  799. info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
  800. info->flags |= ATH9K_TXDESC_CTSENA;
  801. }
  802. if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
  803. info->rates[i].RateFlags |= ATH9K_RATESERIES_2040;
  804. if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
  805. info->rates[i].RateFlags |= ATH9K_RATESERIES_HALFGI;
  806. is_sgi = !!(rates[i].flags & IEEE80211_TX_RC_SHORT_GI);
  807. is_40 = !!(rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH);
  808. is_sp = !!(rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE);
  809. if (rates[i].flags & IEEE80211_TX_RC_MCS) {
  810. /* MCS rates */
  811. info->rates[i].Rate = rix | 0x80;
  812. info->rates[i].ChSel = ath_txchainmask_reduction(sc,
  813. ah->txchainmask, info->rates[i].Rate);
  814. info->rates[i].PktDuration = ath_pkt_duration(sc, rix, len,
  815. is_40, is_sgi, is_sp);
  816. if (rix < 8 && (tx_info->flags & IEEE80211_TX_CTL_STBC))
  817. info->rates[i].RateFlags |= ATH9K_RATESERIES_STBC;
  818. continue;
  819. }
  820. /* legacy rates */
  821. if ((tx_info->band == IEEE80211_BAND_2GHZ) &&
  822. !(rate->flags & IEEE80211_RATE_ERP_G))
  823. phy = WLAN_RC_PHY_CCK;
  824. else
  825. phy = WLAN_RC_PHY_OFDM;
  826. rate = &sc->sbands[tx_info->band].bitrates[rates[i].idx];
  827. info->rates[i].Rate = rate->hw_value;
  828. if (rate->hw_value_short) {
  829. if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
  830. info->rates[i].Rate |= rate->hw_value_short;
  831. } else {
  832. is_sp = false;
  833. }
  834. if (bf->bf_state.bfs_paprd)
  835. info->rates[i].ChSel = ah->txchainmask;
  836. else
  837. info->rates[i].ChSel = ath_txchainmask_reduction(sc,
  838. ah->txchainmask, info->rates[i].Rate);
  839. info->rates[i].PktDuration = ath9k_hw_computetxtime(sc->sc_ah,
  840. phy, rate->bitrate * 100, len, rix, is_sp);
  841. }
  842. /* For AR5416 - RTS cannot be followed by a frame larger than 8K */
  843. if (bf_isaggr(bf) && (len > sc->sc_ah->caps.rts_aggr_limit))
  844. info->flags &= ~ATH9K_TXDESC_RTSENA;
  845. /* ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. */
  846. if (info->flags & ATH9K_TXDESC_RTSENA)
  847. info->flags &= ~ATH9K_TXDESC_CTSENA;
  848. }
  849. static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb)
  850. {
  851. struct ieee80211_hdr *hdr;
  852. enum ath9k_pkt_type htype;
  853. __le16 fc;
  854. hdr = (struct ieee80211_hdr *)skb->data;
  855. fc = hdr->frame_control;
  856. if (ieee80211_is_beacon(fc))
  857. htype = ATH9K_PKT_TYPE_BEACON;
  858. else if (ieee80211_is_probe_resp(fc))
  859. htype = ATH9K_PKT_TYPE_PROBE_RESP;
  860. else if (ieee80211_is_atim(fc))
  861. htype = ATH9K_PKT_TYPE_ATIM;
  862. else if (ieee80211_is_pspoll(fc))
  863. htype = ATH9K_PKT_TYPE_PSPOLL;
  864. else
  865. htype = ATH9K_PKT_TYPE_NORMAL;
  866. return htype;
  867. }
  868. static void ath_tx_fill_desc(struct ath_softc *sc, struct ath_buf *bf,
  869. struct ath_txq *txq, int len)
  870. {
  871. struct ath_hw *ah = sc->sc_ah;
  872. struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
  873. struct ath_buf *bf_first = bf;
  874. struct ath_tx_info info;
  875. bool aggr = !!(bf->bf_state.bf_type & BUF_AGGR);
  876. memset(&info, 0, sizeof(info));
  877. info.is_first = true;
  878. info.is_last = true;
  879. info.txpower = MAX_RATE_POWER;
  880. info.qcu = txq->axq_qnum;
  881. info.flags = ATH9K_TXDESC_INTREQ;
  882. if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
  883. info.flags |= ATH9K_TXDESC_NOACK;
  884. if (tx_info->flags & IEEE80211_TX_CTL_LDPC)
  885. info.flags |= ATH9K_TXDESC_LDPC;
  886. ath_buf_set_rate(sc, bf, &info, len);
  887. if (tx_info->flags & IEEE80211_TX_CTL_CLEAR_PS_FILT)
  888. info.flags |= ATH9K_TXDESC_CLRDMASK;
  889. if (bf->bf_state.bfs_paprd)
  890. info.flags |= (u32) bf->bf_state.bfs_paprd << ATH9K_TXDESC_PAPRD_S;
  891. while (bf) {
  892. struct sk_buff *skb = bf->bf_mpdu;
  893. struct ath_frame_info *fi = get_frame_info(skb);
  894. info.type = get_hw_packet_type(skb);
  895. if (bf->bf_next)
  896. info.link = bf->bf_next->bf_daddr;
  897. else
  898. info.link = 0;
  899. info.buf_addr[0] = bf->bf_buf_addr;
  900. info.buf_len[0] = skb->len;
  901. info.pkt_len = fi->framelen;
  902. info.keyix = fi->keyix;
  903. info.keytype = fi->keytype;
  904. if (aggr) {
  905. if (bf == bf_first)
  906. info.aggr = AGGR_BUF_FIRST;
  907. else if (!bf->bf_next)
  908. info.aggr = AGGR_BUF_LAST;
  909. else
  910. info.aggr = AGGR_BUF_MIDDLE;
  911. info.ndelim = bf->bf_state.ndelim;
  912. info.aggr_len = len;
  913. }
  914. ath9k_hw_set_txdesc(ah, bf->bf_desc, &info);
  915. bf = bf->bf_next;
  916. }
  917. }
  918. static void ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq,
  919. struct ath_atx_tid *tid)
  920. {
  921. struct ath_buf *bf;
  922. enum ATH_AGGR_STATUS status;
  923. struct ieee80211_tx_info *tx_info;
  924. struct list_head bf_q;
  925. int aggr_len;
  926. do {
  927. if (skb_queue_empty(&tid->buf_q))
  928. return;
  929. INIT_LIST_HEAD(&bf_q);
  930. status = ath_tx_form_aggr(sc, txq, tid, &bf_q, &aggr_len);
  931. /*
  932. * no frames picked up to be aggregated;
  933. * block-ack window is not open.
  934. */
  935. if (list_empty(&bf_q))
  936. break;
  937. bf = list_first_entry(&bf_q, struct ath_buf, list);
  938. bf->bf_lastbf = list_entry(bf_q.prev, struct ath_buf, list);
  939. tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
  940. if (tid->ac->clear_ps_filter) {
  941. tid->ac->clear_ps_filter = false;
  942. tx_info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
  943. } else {
  944. tx_info->flags &= ~IEEE80211_TX_CTL_CLEAR_PS_FILT;
  945. }
  946. /* if only one frame, send as non-aggregate */
  947. if (bf == bf->bf_lastbf) {
  948. aggr_len = get_frame_info(bf->bf_mpdu)->framelen;
  949. bf->bf_state.bf_type = BUF_AMPDU;
  950. } else {
  951. TX_STAT_INC(txq->axq_qnum, a_aggr);
  952. }
  953. ath_tx_fill_desc(sc, bf, txq, aggr_len);
  954. ath_tx_txqaddbuf(sc, txq, &bf_q, false);
  955. } while (txq->axq_ampdu_depth < ATH_AGGR_MIN_QDEPTH &&
  956. status != ATH_AGGR_BAW_CLOSED);
  957. }
  958. int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
  959. u16 tid, u16 *ssn)
  960. {
  961. struct ath_atx_tid *txtid;
  962. struct ath_node *an;
  963. an = (struct ath_node *)sta->drv_priv;
  964. txtid = ATH_AN_2_TID(an, tid);
  965. if (txtid->state & (AGGR_CLEANUP | AGGR_ADDBA_COMPLETE))
  966. return -EAGAIN;
  967. txtid->state |= AGGR_ADDBA_PROGRESS;
  968. txtid->paused = true;
  969. *ssn = txtid->seq_start = txtid->seq_next;
  970. txtid->bar_index = -1;
  971. memset(txtid->tx_buf, 0, sizeof(txtid->tx_buf));
  972. txtid->baw_head = txtid->baw_tail = 0;
  973. return 0;
  974. }
  975. void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
  976. {
  977. struct ath_node *an = (struct ath_node *)sta->drv_priv;
  978. struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid);
  979. struct ath_txq *txq = txtid->ac->txq;
  980. if (txtid->state & AGGR_CLEANUP)
  981. return;
  982. if (!(txtid->state & AGGR_ADDBA_COMPLETE)) {
  983. txtid->state &= ~AGGR_ADDBA_PROGRESS;
  984. return;
  985. }
  986. ath_txq_lock(sc, txq);
  987. txtid->paused = true;
  988. /*
  989. * If frames are still being transmitted for this TID, they will be
  990. * cleaned up during tx completion. To prevent race conditions, this
  991. * TID can only be reused after all in-progress subframes have been
  992. * completed.
  993. */
  994. if (txtid->baw_head != txtid->baw_tail)
  995. txtid->state |= AGGR_CLEANUP;
  996. else
  997. txtid->state &= ~AGGR_ADDBA_COMPLETE;
  998. ath_tx_flush_tid(sc, txtid);
  999. ath_txq_unlock_complete(sc, txq);
  1000. }
  1001. void ath_tx_aggr_sleep(struct ieee80211_sta *sta, struct ath_softc *sc,
  1002. struct ath_node *an)
  1003. {
  1004. struct ath_atx_tid *tid;
  1005. struct ath_atx_ac *ac;
  1006. struct ath_txq *txq;
  1007. bool buffered;
  1008. int tidno;
  1009. for (tidno = 0, tid = &an->tid[tidno];
  1010. tidno < WME_NUM_TID; tidno++, tid++) {
  1011. if (!tid->sched)
  1012. continue;
  1013. ac = tid->ac;
  1014. txq = ac->txq;
  1015. ath_txq_lock(sc, txq);
  1016. buffered = !skb_queue_empty(&tid->buf_q);
  1017. tid->sched = false;
  1018. list_del(&tid->list);
  1019. if (ac->sched) {
  1020. ac->sched = false;
  1021. list_del(&ac->list);
  1022. }
  1023. ath_txq_unlock(sc, txq);
  1024. ieee80211_sta_set_buffered(sta, tidno, buffered);
  1025. }
  1026. }
  1027. void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an)
  1028. {
  1029. struct ath_atx_tid *tid;
  1030. struct ath_atx_ac *ac;
  1031. struct ath_txq *txq;
  1032. int tidno;
  1033. for (tidno = 0, tid = &an->tid[tidno];
  1034. tidno < WME_NUM_TID; tidno++, tid++) {
  1035. ac = tid->ac;
  1036. txq = ac->txq;
  1037. ath_txq_lock(sc, txq);
  1038. ac->clear_ps_filter = true;
  1039. if (!skb_queue_empty(&tid->buf_q) && !tid->paused) {
  1040. ath_tx_queue_tid(txq, tid);
  1041. ath_txq_schedule(sc, txq);
  1042. }
  1043. ath_txq_unlock_complete(sc, txq);
  1044. }
  1045. }
  1046. void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
  1047. {
  1048. struct ath_atx_tid *txtid;
  1049. struct ath_node *an;
  1050. an = (struct ath_node *)sta->drv_priv;
  1051. txtid = ATH_AN_2_TID(an, tid);
  1052. txtid->baw_size = IEEE80211_MIN_AMPDU_BUF << sta->ht_cap.ampdu_factor;
  1053. txtid->state |= AGGR_ADDBA_COMPLETE;
  1054. txtid->state &= ~AGGR_ADDBA_PROGRESS;
  1055. ath_tx_resume_tid(sc, txtid);
  1056. }
  1057. /********************/
  1058. /* Queue Management */
  1059. /********************/
  1060. static void ath_txq_drain_pending_buffers(struct ath_softc *sc,
  1061. struct ath_txq *txq)
  1062. {
  1063. struct ath_atx_ac *ac, *ac_tmp;
  1064. struct ath_atx_tid *tid, *tid_tmp;
  1065. list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) {
  1066. list_del(&ac->list);
  1067. ac->sched = false;
  1068. list_for_each_entry_safe(tid, tid_tmp, &ac->tid_q, list) {
  1069. list_del(&tid->list);
  1070. tid->sched = false;
  1071. ath_tid_drain(sc, txq, tid);
  1072. }
  1073. }
  1074. }
  1075. struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
  1076. {
  1077. struct ath_hw *ah = sc->sc_ah;
  1078. struct ath9k_tx_queue_info qi;
  1079. static const int subtype_txq_to_hwq[] = {
  1080. [WME_AC_BE] = ATH_TXQ_AC_BE,
  1081. [WME_AC_BK] = ATH_TXQ_AC_BK,
  1082. [WME_AC_VI] = ATH_TXQ_AC_VI,
  1083. [WME_AC_VO] = ATH_TXQ_AC_VO,
  1084. };
  1085. int axq_qnum, i;
  1086. memset(&qi, 0, sizeof(qi));
  1087. qi.tqi_subtype = subtype_txq_to_hwq[subtype];
  1088. qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT;
  1089. qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
  1090. qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT;
  1091. qi.tqi_physCompBuf = 0;
  1092. /*
  1093. * Enable interrupts only for EOL and DESC conditions.
  1094. * We mark tx descriptors to receive a DESC interrupt
  1095. * when a tx queue gets deep; otherwise waiting for the
  1096. * EOL to reap descriptors. Note that this is done to
  1097. * reduce interrupt load and this only defers reaping
  1098. * descriptors, never transmitting frames. Aside from
  1099. * reducing interrupts this also permits more concurrency.
  1100. * The only potential downside is if the tx queue backs
  1101. * up in which case the top half of the kernel may backup
  1102. * due to a lack of tx descriptors.
  1103. *
  1104. * The UAPSD queue is an exception, since we take a desc-
  1105. * based intr on the EOSP frames.
  1106. */
  1107. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
  1108. qi.tqi_qflags = TXQ_FLAG_TXINT_ENABLE;
  1109. } else {
  1110. if (qtype == ATH9K_TX_QUEUE_UAPSD)
  1111. qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
  1112. else
  1113. qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
  1114. TXQ_FLAG_TXDESCINT_ENABLE;
  1115. }
  1116. axq_qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi);
  1117. if (axq_qnum == -1) {
  1118. /*
  1119. * NB: don't print a message, this happens
  1120. * normally on parts with too few tx queues
  1121. */
  1122. return NULL;
  1123. }
  1124. if (!ATH_TXQ_SETUP(sc, axq_qnum)) {
  1125. struct ath_txq *txq = &sc->tx.txq[axq_qnum];
  1126. txq->axq_qnum = axq_qnum;
  1127. txq->mac80211_qnum = -1;
  1128. txq->axq_link = NULL;
  1129. __skb_queue_head_init(&txq->complete_q);
  1130. INIT_LIST_HEAD(&txq->axq_q);
  1131. INIT_LIST_HEAD(&txq->axq_acq);
  1132. spin_lock_init(&txq->axq_lock);
  1133. txq->axq_depth = 0;
  1134. txq->axq_ampdu_depth = 0;
  1135. txq->axq_tx_inprogress = false;
  1136. sc->tx.txqsetup |= 1<<axq_qnum;
  1137. txq->txq_headidx = txq->txq_tailidx = 0;
  1138. for (i = 0; i < ATH_TXFIFO_DEPTH; i++)
  1139. INIT_LIST_HEAD(&txq->txq_fifo[i]);
  1140. }
  1141. return &sc->tx.txq[axq_qnum];
  1142. }
  1143. int ath_txq_update(struct ath_softc *sc, int qnum,
  1144. struct ath9k_tx_queue_info *qinfo)
  1145. {
  1146. struct ath_hw *ah = sc->sc_ah;
  1147. int error = 0;
  1148. struct ath9k_tx_queue_info qi;
  1149. if (qnum == sc->beacon.beaconq) {
  1150. /*
  1151. * XXX: for beacon queue, we just save the parameter.
  1152. * It will be picked up by ath_beaconq_config when
  1153. * it's necessary.
  1154. */
  1155. sc->beacon.beacon_qi = *qinfo;
  1156. return 0;
  1157. }
  1158. BUG_ON(sc->tx.txq[qnum].axq_qnum != qnum);
  1159. ath9k_hw_get_txq_props(ah, qnum, &qi);
  1160. qi.tqi_aifs = qinfo->tqi_aifs;
  1161. qi.tqi_cwmin = qinfo->tqi_cwmin;
  1162. qi.tqi_cwmax = qinfo->tqi_cwmax;
  1163. qi.tqi_burstTime = qinfo->tqi_burstTime;
  1164. qi.tqi_readyTime = qinfo->tqi_readyTime;
  1165. if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {
  1166. ath_err(ath9k_hw_common(sc->sc_ah),
  1167. "Unable to update hardware queue %u!\n", qnum);
  1168. error = -EIO;
  1169. } else {
  1170. ath9k_hw_resettxqueue(ah, qnum);
  1171. }
  1172. return error;
  1173. }
  1174. int ath_cabq_update(struct ath_softc *sc)
  1175. {
  1176. struct ath9k_tx_queue_info qi;
  1177. struct ath_beacon_config *cur_conf = &sc->cur_beacon_conf;
  1178. int qnum = sc->beacon.cabq->axq_qnum;
  1179. ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi);
  1180. /*
  1181. * Ensure the readytime % is within the bounds.
  1182. */
  1183. if (sc->config.cabqReadytime < ATH9K_READY_TIME_LO_BOUND)
  1184. sc->config.cabqReadytime = ATH9K_READY_TIME_LO_BOUND;
  1185. else if (sc->config.cabqReadytime > ATH9K_READY_TIME_HI_BOUND)
  1186. sc->config.cabqReadytime = ATH9K_READY_TIME_HI_BOUND;
  1187. qi.tqi_readyTime = (cur_conf->beacon_interval *
  1188. sc->config.cabqReadytime) / 100;
  1189. ath_txq_update(sc, qnum, &qi);
  1190. return 0;
  1191. }
  1192. static bool bf_is_ampdu_not_probing(struct ath_buf *bf)
  1193. {
  1194. struct ieee80211_tx_info *info = IEEE80211_SKB_CB(bf->bf_mpdu);
  1195. return bf_isampdu(bf) && !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE);
  1196. }
  1197. static void ath_drain_txq_list(struct ath_softc *sc, struct ath_txq *txq,
  1198. struct list_head *list, bool retry_tx)
  1199. {
  1200. struct ath_buf *bf, *lastbf;
  1201. struct list_head bf_head;
  1202. struct ath_tx_status ts;
  1203. memset(&ts, 0, sizeof(ts));
  1204. ts.ts_status = ATH9K_TX_FLUSH;
  1205. INIT_LIST_HEAD(&bf_head);
  1206. while (!list_empty(list)) {
  1207. bf = list_first_entry(list, struct ath_buf, list);
  1208. if (bf->bf_stale) {
  1209. list_del(&bf->list);
  1210. ath_tx_return_buffer(sc, bf);
  1211. continue;
  1212. }
  1213. lastbf = bf->bf_lastbf;
  1214. list_cut_position(&bf_head, list, &lastbf->list);
  1215. txq->axq_depth--;
  1216. if (bf_is_ampdu_not_probing(bf))
  1217. txq->axq_ampdu_depth--;
  1218. if (bf_isampdu(bf))
  1219. ath_tx_complete_aggr(sc, txq, bf, &bf_head, &ts, 0,
  1220. retry_tx);
  1221. else
  1222. ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0);
  1223. }
  1224. }
  1225. /*
  1226. * Drain a given TX queue (could be Beacon or Data)
  1227. *
  1228. * This assumes output has been stopped and
  1229. * we do not need to block ath_tx_tasklet.
  1230. */
  1231. void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq, bool retry_tx)
  1232. {
  1233. ath_txq_lock(sc, txq);
  1234. if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
  1235. int idx = txq->txq_tailidx;
  1236. while (!list_empty(&txq->txq_fifo[idx])) {
  1237. ath_drain_txq_list(sc, txq, &txq->txq_fifo[idx],
  1238. retry_tx);
  1239. INCR(idx, ATH_TXFIFO_DEPTH);
  1240. }
  1241. txq->txq_tailidx = idx;
  1242. }
  1243. txq->axq_link = NULL;
  1244. txq->axq_tx_inprogress = false;
  1245. ath_drain_txq_list(sc, txq, &txq->axq_q, retry_tx);
  1246. /* flush any pending frames if aggregation is enabled */
  1247. if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) && !retry_tx)
  1248. ath_txq_drain_pending_buffers(sc, txq);
  1249. ath_txq_unlock_complete(sc, txq);
  1250. }
  1251. bool ath_drain_all_txq(struct ath_softc *sc, bool retry_tx)
  1252. {
  1253. struct ath_hw *ah = sc->sc_ah;
  1254. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1255. struct ath_txq *txq;
  1256. int i;
  1257. u32 npend = 0;
  1258. if (sc->sc_flags & SC_OP_INVALID)
  1259. return true;
  1260. ath9k_hw_abort_tx_dma(ah);
  1261. /* Check if any queue remains active */
  1262. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  1263. if (!ATH_TXQ_SETUP(sc, i))
  1264. continue;
  1265. if (ath9k_hw_numtxpending(ah, sc->tx.txq[i].axq_qnum))
  1266. npend |= BIT(i);
  1267. }
  1268. if (npend)
  1269. ath_err(common, "Failed to stop TX DMA, queues=0x%03x!\n", npend);
  1270. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  1271. if (!ATH_TXQ_SETUP(sc, i))
  1272. continue;
  1273. /*
  1274. * The caller will resume queues with ieee80211_wake_queues.
  1275. * Mark the queue as not stopped to prevent ath_tx_complete
  1276. * from waking the queue too early.
  1277. */
  1278. txq = &sc->tx.txq[i];
  1279. txq->stopped = false;
  1280. ath_draintxq(sc, txq, retry_tx);
  1281. }
  1282. return !npend;
  1283. }
  1284. void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
  1285. {
  1286. ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum);
  1287. sc->tx.txqsetup &= ~(1<<txq->axq_qnum);
  1288. }
  1289. /* For each axq_acq entry, for each tid, try to schedule packets
  1290. * for transmit until ampdu_depth has reached min Q depth.
  1291. */
  1292. void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
  1293. {
  1294. struct ath_atx_ac *ac, *ac_tmp, *last_ac;
  1295. struct ath_atx_tid *tid, *last_tid;
  1296. if (work_pending(&sc->hw_reset_work) || list_empty(&txq->axq_acq) ||
  1297. txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH)
  1298. return;
  1299. ac = list_first_entry(&txq->axq_acq, struct ath_atx_ac, list);
  1300. last_ac = list_entry(txq->axq_acq.prev, struct ath_atx_ac, list);
  1301. list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) {
  1302. last_tid = list_entry(ac->tid_q.prev, struct ath_atx_tid, list);
  1303. list_del(&ac->list);
  1304. ac->sched = false;
  1305. while (!list_empty(&ac->tid_q)) {
  1306. tid = list_first_entry(&ac->tid_q, struct ath_atx_tid,
  1307. list);
  1308. list_del(&tid->list);
  1309. tid->sched = false;
  1310. if (tid->paused)
  1311. continue;
  1312. ath_tx_sched_aggr(sc, txq, tid);
  1313. /*
  1314. * add tid to round-robin queue if more frames
  1315. * are pending for the tid
  1316. */
  1317. if (!skb_queue_empty(&tid->buf_q))
  1318. ath_tx_queue_tid(txq, tid);
  1319. if (tid == last_tid ||
  1320. txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH)
  1321. break;
  1322. }
  1323. if (!list_empty(&ac->tid_q) && !ac->sched) {
  1324. ac->sched = true;
  1325. list_add_tail(&ac->list, &txq->axq_acq);
  1326. }
  1327. if (ac == last_ac ||
  1328. txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH)
  1329. return;
  1330. }
  1331. }
  1332. /***********/
  1333. /* TX, DMA */
  1334. /***********/
  1335. /*
  1336. * Insert a chain of ath_buf (descriptors) on a txq and
  1337. * assume the descriptors are already chained together by caller.
  1338. */
  1339. static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
  1340. struct list_head *head, bool internal)
  1341. {
  1342. struct ath_hw *ah = sc->sc_ah;
  1343. struct ath_common *common = ath9k_hw_common(ah);
  1344. struct ath_buf *bf, *bf_last;
  1345. bool puttxbuf = false;
  1346. bool edma;
  1347. /*
  1348. * Insert the frame on the outbound list and
  1349. * pass it on to the hardware.
  1350. */
  1351. if (list_empty(head))
  1352. return;
  1353. edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
  1354. bf = list_first_entry(head, struct ath_buf, list);
  1355. bf_last = list_entry(head->prev, struct ath_buf, list);
  1356. ath_dbg(common, QUEUE, "qnum: %d, txq depth: %d\n",
  1357. txq->axq_qnum, txq->axq_depth);
  1358. if (edma && list_empty(&txq->txq_fifo[txq->txq_headidx])) {
  1359. list_splice_tail_init(head, &txq->txq_fifo[txq->txq_headidx]);
  1360. INCR(txq->txq_headidx, ATH_TXFIFO_DEPTH);
  1361. puttxbuf = true;
  1362. } else {
  1363. list_splice_tail_init(head, &txq->axq_q);
  1364. if (txq->axq_link) {
  1365. ath9k_hw_set_desc_link(ah, txq->axq_link, bf->bf_daddr);
  1366. ath_dbg(common, XMIT, "link[%u] (%p)=%llx (%p)\n",
  1367. txq->axq_qnum, txq->axq_link,
  1368. ito64(bf->bf_daddr), bf->bf_desc);
  1369. } else if (!edma)
  1370. puttxbuf = true;
  1371. txq->axq_link = bf_last->bf_desc;
  1372. }
  1373. if (puttxbuf) {
  1374. TX_STAT_INC(txq->axq_qnum, puttxbuf);
  1375. ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
  1376. ath_dbg(common, XMIT, "TXDP[%u] = %llx (%p)\n",
  1377. txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc);
  1378. }
  1379. if (!edma) {
  1380. TX_STAT_INC(txq->axq_qnum, txstart);
  1381. ath9k_hw_txstart(ah, txq->axq_qnum);
  1382. }
  1383. if (!internal) {
  1384. txq->axq_depth++;
  1385. if (bf_is_ampdu_not_probing(bf))
  1386. txq->axq_ampdu_depth++;
  1387. }
  1388. }
  1389. static void ath_tx_send_ampdu(struct ath_softc *sc, struct ath_atx_tid *tid,
  1390. struct sk_buff *skb, struct ath_tx_control *txctl)
  1391. {
  1392. struct ath_frame_info *fi = get_frame_info(skb);
  1393. struct list_head bf_head;
  1394. struct ath_buf *bf;
  1395. /*
  1396. * Do not queue to h/w when any of the following conditions is true:
  1397. * - there are pending frames in software queue
  1398. * - the TID is currently paused for ADDBA/BAR request
  1399. * - seqno is not within block-ack window
  1400. * - h/w queue depth exceeds low water mark
  1401. */
  1402. if (!skb_queue_empty(&tid->buf_q) || tid->paused ||
  1403. !BAW_WITHIN(tid->seq_start, tid->baw_size, tid->seq_next) ||
  1404. txctl->txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH) {
  1405. /*
  1406. * Add this frame to software queue for scheduling later
  1407. * for aggregation.
  1408. */
  1409. TX_STAT_INC(txctl->txq->axq_qnum, a_queued_sw);
  1410. __skb_queue_tail(&tid->buf_q, skb);
  1411. if (!txctl->an || !txctl->an->sleeping)
  1412. ath_tx_queue_tid(txctl->txq, tid);
  1413. return;
  1414. }
  1415. bf = ath_tx_setup_buffer(sc, txctl->txq, tid, skb, false);
  1416. if (!bf)
  1417. return;
  1418. bf->bf_state.bf_type = BUF_AMPDU;
  1419. INIT_LIST_HEAD(&bf_head);
  1420. list_add(&bf->list, &bf_head);
  1421. /* Add sub-frame to BAW */
  1422. ath_tx_addto_baw(sc, tid, bf->bf_state.seqno);
  1423. /* Queue to h/w without aggregation */
  1424. TX_STAT_INC(txctl->txq->axq_qnum, a_queued_hw);
  1425. bf->bf_lastbf = bf;
  1426. ath_tx_fill_desc(sc, bf, txctl->txq, fi->framelen);
  1427. ath_tx_txqaddbuf(sc, txctl->txq, &bf_head, false);
  1428. }
  1429. static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
  1430. struct ath_atx_tid *tid, struct sk_buff *skb)
  1431. {
  1432. struct ath_frame_info *fi = get_frame_info(skb);
  1433. struct list_head bf_head;
  1434. struct ath_buf *bf;
  1435. bf = fi->bf;
  1436. if (!bf)
  1437. bf = ath_tx_setup_buffer(sc, txq, tid, skb, false);
  1438. if (!bf)
  1439. return;
  1440. INIT_LIST_HEAD(&bf_head);
  1441. list_add_tail(&bf->list, &bf_head);
  1442. bf->bf_state.bf_type = 0;
  1443. bf->bf_lastbf = bf;
  1444. ath_tx_fill_desc(sc, bf, txq, fi->framelen);
  1445. ath_tx_txqaddbuf(sc, txq, &bf_head, false);
  1446. TX_STAT_INC(txq->axq_qnum, queued);
  1447. }
  1448. static void setup_frame_info(struct ieee80211_hw *hw, struct sk_buff *skb,
  1449. int framelen)
  1450. {
  1451. struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
  1452. struct ieee80211_sta *sta = tx_info->control.sta;
  1453. struct ieee80211_key_conf *hw_key = tx_info->control.hw_key;
  1454. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
  1455. struct ath_frame_info *fi = get_frame_info(skb);
  1456. struct ath_node *an = NULL;
  1457. enum ath9k_key_type keytype;
  1458. keytype = ath9k_cmn_get_hw_crypto_keytype(skb);
  1459. if (sta)
  1460. an = (struct ath_node *) sta->drv_priv;
  1461. memset(fi, 0, sizeof(*fi));
  1462. if (hw_key)
  1463. fi->keyix = hw_key->hw_key_idx;
  1464. else if (an && ieee80211_is_data(hdr->frame_control) && an->ps_key > 0)
  1465. fi->keyix = an->ps_key;
  1466. else
  1467. fi->keyix = ATH9K_TXKEYIX_INVALID;
  1468. fi->keytype = keytype;
  1469. fi->framelen = framelen;
  1470. }
  1471. u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate)
  1472. {
  1473. struct ath_hw *ah = sc->sc_ah;
  1474. struct ath9k_channel *curchan = ah->curchan;
  1475. if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) &&
  1476. (curchan->channelFlags & CHANNEL_5GHZ) &&
  1477. (chainmask == 0x7) && (rate < 0x90))
  1478. return 0x3;
  1479. else
  1480. return chainmask;
  1481. }
  1482. /*
  1483. * Assign a descriptor (and sequence number if necessary,
  1484. * and map buffer for DMA. Frees skb on error
  1485. */
  1486. static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
  1487. struct ath_txq *txq,
  1488. struct ath_atx_tid *tid,
  1489. struct sk_buff *skb,
  1490. bool dequeue)
  1491. {
  1492. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1493. struct ath_frame_info *fi = get_frame_info(skb);
  1494. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
  1495. struct ath_buf *bf;
  1496. int fragno;
  1497. u16 seqno;
  1498. bf = ath_tx_get_buffer(sc);
  1499. if (!bf) {
  1500. ath_dbg(common, XMIT, "TX buffers are full\n");
  1501. goto error;
  1502. }
  1503. ATH_TXBUF_RESET(bf);
  1504. if (tid) {
  1505. fragno = le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG;
  1506. seqno = tid->seq_next;
  1507. hdr->seq_ctrl = cpu_to_le16(tid->seq_next << IEEE80211_SEQ_SEQ_SHIFT);
  1508. if (fragno)
  1509. hdr->seq_ctrl |= cpu_to_le16(fragno);
  1510. if (!ieee80211_has_morefrags(hdr->frame_control))
  1511. INCR(tid->seq_next, IEEE80211_SEQ_MAX);
  1512. bf->bf_state.seqno = seqno;
  1513. }
  1514. bf->bf_mpdu = skb;
  1515. bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
  1516. skb->len, DMA_TO_DEVICE);
  1517. if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) {
  1518. bf->bf_mpdu = NULL;
  1519. bf->bf_buf_addr = 0;
  1520. ath_err(ath9k_hw_common(sc->sc_ah),
  1521. "dma_mapping_error() on TX\n");
  1522. ath_tx_return_buffer(sc, bf);
  1523. goto error;
  1524. }
  1525. fi->bf = bf;
  1526. return bf;
  1527. error:
  1528. if (dequeue)
  1529. __skb_unlink(skb, &tid->buf_q);
  1530. dev_kfree_skb_any(skb);
  1531. return NULL;
  1532. }
  1533. /* FIXME: tx power */
  1534. static void ath_tx_start_dma(struct ath_softc *sc, struct sk_buff *skb,
  1535. struct ath_tx_control *txctl)
  1536. {
  1537. struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
  1538. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
  1539. struct ath_atx_tid *tid = NULL;
  1540. struct ath_buf *bf;
  1541. u8 tidno;
  1542. if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) && txctl->an &&
  1543. ieee80211_is_data_qos(hdr->frame_control)) {
  1544. tidno = ieee80211_get_qos_ctl(hdr)[0] &
  1545. IEEE80211_QOS_CTL_TID_MASK;
  1546. tid = ATH_AN_2_TID(txctl->an, tidno);
  1547. WARN_ON(tid->ac->txq != txctl->txq);
  1548. }
  1549. if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) && tid) {
  1550. /*
  1551. * Try aggregation if it's a unicast data frame
  1552. * and the destination is HT capable.
  1553. */
  1554. ath_tx_send_ampdu(sc, tid, skb, txctl);
  1555. } else {
  1556. bf = ath_tx_setup_buffer(sc, txctl->txq, tid, skb, false);
  1557. if (!bf)
  1558. return;
  1559. bf->bf_state.bfs_paprd = txctl->paprd;
  1560. if (txctl->paprd)
  1561. bf->bf_state.bfs_paprd_timestamp = jiffies;
  1562. ath_tx_send_normal(sc, txctl->txq, tid, skb);
  1563. }
  1564. }
  1565. /* Upon failure caller should free skb */
  1566. int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
  1567. struct ath_tx_control *txctl)
  1568. {
  1569. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
  1570. struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
  1571. struct ieee80211_sta *sta = info->control.sta;
  1572. struct ieee80211_vif *vif = info->control.vif;
  1573. struct ath_softc *sc = hw->priv;
  1574. struct ath_txq *txq = txctl->txq;
  1575. int padpos, padsize;
  1576. int frmlen = skb->len + FCS_LEN;
  1577. int q;
  1578. /* NOTE: sta can be NULL according to net/mac80211.h */
  1579. if (sta)
  1580. txctl->an = (struct ath_node *)sta->drv_priv;
  1581. if (info->control.hw_key)
  1582. frmlen += info->control.hw_key->icv_len;
  1583. /*
  1584. * As a temporary workaround, assign seq# here; this will likely need
  1585. * to be cleaned up to work better with Beacon transmission and virtual
  1586. * BSSes.
  1587. */
  1588. if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
  1589. if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
  1590. sc->tx.seq_no += 0x10;
  1591. hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
  1592. hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
  1593. }
  1594. /* Add the padding after the header if this is not already done */
  1595. padpos = ath9k_cmn_padpos(hdr->frame_control);
  1596. padsize = padpos & 3;
  1597. if (padsize && skb->len > padpos) {
  1598. if (skb_headroom(skb) < padsize)
  1599. return -ENOMEM;
  1600. skb_push(skb, padsize);
  1601. memmove(skb->data, skb->data + padsize, padpos);
  1602. hdr = (struct ieee80211_hdr *) skb->data;
  1603. }
  1604. if ((vif && vif->type != NL80211_IFTYPE_AP &&
  1605. vif->type != NL80211_IFTYPE_AP_VLAN) ||
  1606. !ieee80211_is_data(hdr->frame_control))
  1607. info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
  1608. setup_frame_info(hw, skb, frmlen);
  1609. /*
  1610. * At this point, the vif, hw_key and sta pointers in the tx control
  1611. * info are no longer valid (overwritten by the ath_frame_info data.
  1612. */
  1613. q = skb_get_queue_mapping(skb);
  1614. ath_txq_lock(sc, txq);
  1615. if (txq == sc->tx.txq_map[q] &&
  1616. ++txq->pending_frames > ATH_MAX_QDEPTH && !txq->stopped) {
  1617. ieee80211_stop_queue(sc->hw, q);
  1618. txq->stopped = true;
  1619. }
  1620. ath_tx_start_dma(sc, skb, txctl);
  1621. ath_txq_unlock(sc, txq);
  1622. return 0;
  1623. }
  1624. /*****************/
  1625. /* TX Completion */
  1626. /*****************/
  1627. static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
  1628. int tx_flags, struct ath_txq *txq)
  1629. {
  1630. struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
  1631. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1632. struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
  1633. int q, padpos, padsize;
  1634. ath_dbg(common, XMIT, "TX complete: skb: %p\n", skb);
  1635. if (!(tx_flags & ATH_TX_ERROR))
  1636. /* Frame was ACKed */
  1637. tx_info->flags |= IEEE80211_TX_STAT_ACK;
  1638. padpos = ath9k_cmn_padpos(hdr->frame_control);
  1639. padsize = padpos & 3;
  1640. if (padsize && skb->len>padpos+padsize) {
  1641. /*
  1642. * Remove MAC header padding before giving the frame back to
  1643. * mac80211.
  1644. */
  1645. memmove(skb->data + padsize, skb->data, padpos);
  1646. skb_pull(skb, padsize);
  1647. }
  1648. if ((sc->ps_flags & PS_WAIT_FOR_TX_ACK) && !txq->axq_depth) {
  1649. sc->ps_flags &= ~PS_WAIT_FOR_TX_ACK;
  1650. ath_dbg(common, PS,
  1651. "Going back to sleep after having received TX status (0x%lx)\n",
  1652. sc->ps_flags & (PS_WAIT_FOR_BEACON |
  1653. PS_WAIT_FOR_CAB |
  1654. PS_WAIT_FOR_PSPOLL_DATA |
  1655. PS_WAIT_FOR_TX_ACK));
  1656. }
  1657. q = skb_get_queue_mapping(skb);
  1658. if (txq == sc->tx.txq_map[q]) {
  1659. if (WARN_ON(--txq->pending_frames < 0))
  1660. txq->pending_frames = 0;
  1661. if (txq->stopped && txq->pending_frames < ATH_MAX_QDEPTH) {
  1662. ieee80211_wake_queue(sc->hw, q);
  1663. txq->stopped = false;
  1664. }
  1665. }
  1666. __skb_queue_tail(&txq->complete_q, skb);
  1667. }
  1668. static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
  1669. struct ath_txq *txq, struct list_head *bf_q,
  1670. struct ath_tx_status *ts, int txok)
  1671. {
  1672. struct sk_buff *skb = bf->bf_mpdu;
  1673. struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
  1674. unsigned long flags;
  1675. int tx_flags = 0;
  1676. if (!txok)
  1677. tx_flags |= ATH_TX_ERROR;
  1678. if (ts->ts_status & ATH9K_TXERR_FILT)
  1679. tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
  1680. dma_unmap_single(sc->dev, bf->bf_buf_addr, skb->len, DMA_TO_DEVICE);
  1681. bf->bf_buf_addr = 0;
  1682. if (bf->bf_state.bfs_paprd) {
  1683. if (time_after(jiffies,
  1684. bf->bf_state.bfs_paprd_timestamp +
  1685. msecs_to_jiffies(ATH_PAPRD_TIMEOUT)))
  1686. dev_kfree_skb_any(skb);
  1687. else
  1688. complete(&sc->paprd_complete);
  1689. } else {
  1690. ath_debug_stat_tx(sc, bf, ts, txq, tx_flags);
  1691. ath_tx_complete(sc, skb, tx_flags, txq);
  1692. }
  1693. /* At this point, skb (bf->bf_mpdu) is consumed...make sure we don't
  1694. * accidentally reference it later.
  1695. */
  1696. bf->bf_mpdu = NULL;
  1697. /*
  1698. * Return the list of ath_buf of this mpdu to free queue
  1699. */
  1700. spin_lock_irqsave(&sc->tx.txbuflock, flags);
  1701. list_splice_tail_init(bf_q, &sc->tx.txbuf);
  1702. spin_unlock_irqrestore(&sc->tx.txbuflock, flags);
  1703. }
  1704. static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
  1705. struct ath_tx_status *ts, int nframes, int nbad,
  1706. int txok)
  1707. {
  1708. struct sk_buff *skb = bf->bf_mpdu;
  1709. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
  1710. struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
  1711. struct ieee80211_hw *hw = sc->hw;
  1712. struct ath_hw *ah = sc->sc_ah;
  1713. u8 i, tx_rateindex;
  1714. if (txok)
  1715. tx_info->status.ack_signal = ts->ts_rssi;
  1716. tx_rateindex = ts->ts_rateindex;
  1717. WARN_ON(tx_rateindex >= hw->max_rates);
  1718. if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
  1719. tx_info->flags |= IEEE80211_TX_STAT_AMPDU;
  1720. BUG_ON(nbad > nframes);
  1721. }
  1722. tx_info->status.ampdu_len = nframes;
  1723. tx_info->status.ampdu_ack_len = nframes - nbad;
  1724. if ((ts->ts_status & ATH9K_TXERR_FILT) == 0 &&
  1725. (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) == 0) {
  1726. /*
  1727. * If an underrun error is seen assume it as an excessive
  1728. * retry only if max frame trigger level has been reached
  1729. * (2 KB for single stream, and 4 KB for dual stream).
  1730. * Adjust the long retry as if the frame was tried
  1731. * hw->max_rate_tries times to affect how rate control updates
  1732. * PER for the failed rate.
  1733. * In case of congestion on the bus penalizing this type of
  1734. * underruns should help hardware actually transmit new frames
  1735. * successfully by eventually preferring slower rates.
  1736. * This itself should also alleviate congestion on the bus.
  1737. */
  1738. if (unlikely(ts->ts_flags & (ATH9K_TX_DATA_UNDERRUN |
  1739. ATH9K_TX_DELIM_UNDERRUN)) &&
  1740. ieee80211_is_data(hdr->frame_control) &&
  1741. ah->tx_trig_level >= sc->sc_ah->config.max_txtrig_level)
  1742. tx_info->status.rates[tx_rateindex].count =
  1743. hw->max_rate_tries;
  1744. }
  1745. for (i = tx_rateindex + 1; i < hw->max_rates; i++) {
  1746. tx_info->status.rates[i].count = 0;
  1747. tx_info->status.rates[i].idx = -1;
  1748. }
  1749. tx_info->status.rates[tx_rateindex].count = ts->ts_longretry + 1;
  1750. }
  1751. static void ath_tx_process_buffer(struct ath_softc *sc, struct ath_txq *txq,
  1752. struct ath_tx_status *ts, struct ath_buf *bf,
  1753. struct list_head *bf_head)
  1754. {
  1755. int txok;
  1756. txq->axq_depth--;
  1757. txok = !(ts->ts_status & ATH9K_TXERR_MASK);
  1758. txq->axq_tx_inprogress = false;
  1759. if (bf_is_ampdu_not_probing(bf))
  1760. txq->axq_ampdu_depth--;
  1761. if (!bf_isampdu(bf)) {
  1762. ath_tx_rc_status(sc, bf, ts, 1, txok ? 0 : 1, txok);
  1763. ath_tx_complete_buf(sc, bf, txq, bf_head, ts, txok);
  1764. } else
  1765. ath_tx_complete_aggr(sc, txq, bf, bf_head, ts, txok, true);
  1766. if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
  1767. ath_txq_schedule(sc, txq);
  1768. }
  1769. static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
  1770. {
  1771. struct ath_hw *ah = sc->sc_ah;
  1772. struct ath_common *common = ath9k_hw_common(ah);
  1773. struct ath_buf *bf, *lastbf, *bf_held = NULL;
  1774. struct list_head bf_head;
  1775. struct ath_desc *ds;
  1776. struct ath_tx_status ts;
  1777. int status;
  1778. ath_dbg(common, QUEUE, "tx queue %d (%x), link %p\n",
  1779. txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
  1780. txq->axq_link);
  1781. ath_txq_lock(sc, txq);
  1782. for (;;) {
  1783. if (work_pending(&sc->hw_reset_work))
  1784. break;
  1785. if (list_empty(&txq->axq_q)) {
  1786. txq->axq_link = NULL;
  1787. if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
  1788. ath_txq_schedule(sc, txq);
  1789. break;
  1790. }
  1791. bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
  1792. /*
  1793. * There is a race condition that a BH gets scheduled
  1794. * after sw writes TxE and before hw re-load the last
  1795. * descriptor to get the newly chained one.
  1796. * Software must keep the last DONE descriptor as a
  1797. * holding descriptor - software does so by marking
  1798. * it with the STALE flag.
  1799. */
  1800. bf_held = NULL;
  1801. if (bf->bf_stale) {
  1802. bf_held = bf;
  1803. if (list_is_last(&bf_held->list, &txq->axq_q))
  1804. break;
  1805. bf = list_entry(bf_held->list.next, struct ath_buf,
  1806. list);
  1807. }
  1808. lastbf = bf->bf_lastbf;
  1809. ds = lastbf->bf_desc;
  1810. memset(&ts, 0, sizeof(ts));
  1811. status = ath9k_hw_txprocdesc(ah, ds, &ts);
  1812. if (status == -EINPROGRESS)
  1813. break;
  1814. TX_STAT_INC(txq->axq_qnum, txprocdesc);
  1815. /*
  1816. * Remove ath_buf's of the same transmit unit from txq,
  1817. * however leave the last descriptor back as the holding
  1818. * descriptor for hw.
  1819. */
  1820. lastbf->bf_stale = true;
  1821. INIT_LIST_HEAD(&bf_head);
  1822. if (!list_is_singular(&lastbf->list))
  1823. list_cut_position(&bf_head,
  1824. &txq->axq_q, lastbf->list.prev);
  1825. if (bf_held) {
  1826. list_del(&bf_held->list);
  1827. ath_tx_return_buffer(sc, bf_held);
  1828. }
  1829. ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
  1830. }
  1831. ath_txq_unlock_complete(sc, txq);
  1832. }
  1833. static void ath_tx_complete_poll_work(struct work_struct *work)
  1834. {
  1835. struct ath_softc *sc = container_of(work, struct ath_softc,
  1836. tx_complete_work.work);
  1837. struct ath_txq *txq;
  1838. int i;
  1839. bool needreset = false;
  1840. #ifdef CONFIG_ATH9K_DEBUGFS
  1841. sc->tx_complete_poll_work_seen++;
  1842. #endif
  1843. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
  1844. if (ATH_TXQ_SETUP(sc, i)) {
  1845. txq = &sc->tx.txq[i];
  1846. ath_txq_lock(sc, txq);
  1847. if (txq->axq_depth) {
  1848. if (txq->axq_tx_inprogress) {
  1849. needreset = true;
  1850. ath_txq_unlock(sc, txq);
  1851. break;
  1852. } else {
  1853. txq->axq_tx_inprogress = true;
  1854. }
  1855. }
  1856. ath_txq_unlock_complete(sc, txq);
  1857. }
  1858. if (needreset) {
  1859. ath_dbg(ath9k_hw_common(sc->sc_ah), RESET,
  1860. "tx hung, resetting the chip\n");
  1861. RESET_STAT_INC(sc, RESET_TYPE_TX_HANG);
  1862. ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
  1863. }
  1864. ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work,
  1865. msecs_to_jiffies(ATH_TX_COMPLETE_POLL_INT));
  1866. }
  1867. void ath_tx_tasklet(struct ath_softc *sc)
  1868. {
  1869. struct ath_hw *ah = sc->sc_ah;
  1870. u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1) & ah->intr_txqs;
  1871. int i;
  1872. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  1873. if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i)))
  1874. ath_tx_processq(sc, &sc->tx.txq[i]);
  1875. }
  1876. }
  1877. void ath_tx_edma_tasklet(struct ath_softc *sc)
  1878. {
  1879. struct ath_tx_status ts;
  1880. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1881. struct ath_hw *ah = sc->sc_ah;
  1882. struct ath_txq *txq;
  1883. struct ath_buf *bf, *lastbf;
  1884. struct list_head bf_head;
  1885. int status;
  1886. for (;;) {
  1887. if (work_pending(&sc->hw_reset_work))
  1888. break;
  1889. status = ath9k_hw_txprocdesc(ah, NULL, (void *)&ts);
  1890. if (status == -EINPROGRESS)
  1891. break;
  1892. if (status == -EIO) {
  1893. ath_dbg(common, XMIT, "Error processing tx status\n");
  1894. break;
  1895. }
  1896. /* Process beacon completions separately */
  1897. if (ts.qid == sc->beacon.beaconq) {
  1898. sc->beacon.tx_processed = true;
  1899. sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
  1900. continue;
  1901. }
  1902. txq = &sc->tx.txq[ts.qid];
  1903. ath_txq_lock(sc, txq);
  1904. if (list_empty(&txq->txq_fifo[txq->txq_tailidx])) {
  1905. ath_txq_unlock(sc, txq);
  1906. return;
  1907. }
  1908. bf = list_first_entry(&txq->txq_fifo[txq->txq_tailidx],
  1909. struct ath_buf, list);
  1910. lastbf = bf->bf_lastbf;
  1911. INIT_LIST_HEAD(&bf_head);
  1912. list_cut_position(&bf_head, &txq->txq_fifo[txq->txq_tailidx],
  1913. &lastbf->list);
  1914. if (list_empty(&txq->txq_fifo[txq->txq_tailidx])) {
  1915. INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH);
  1916. if (!list_empty(&txq->axq_q)) {
  1917. struct list_head bf_q;
  1918. INIT_LIST_HEAD(&bf_q);
  1919. txq->axq_link = NULL;
  1920. list_splice_tail_init(&txq->axq_q, &bf_q);
  1921. ath_tx_txqaddbuf(sc, txq, &bf_q, true);
  1922. }
  1923. }
  1924. ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
  1925. ath_txq_unlock_complete(sc, txq);
  1926. }
  1927. }
  1928. /*****************/
  1929. /* Init, Cleanup */
  1930. /*****************/
  1931. static int ath_txstatus_setup(struct ath_softc *sc, int size)
  1932. {
  1933. struct ath_descdma *dd = &sc->txsdma;
  1934. u8 txs_len = sc->sc_ah->caps.txs_len;
  1935. dd->dd_desc_len = size * txs_len;
  1936. dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
  1937. &dd->dd_desc_paddr, GFP_KERNEL);
  1938. if (!dd->dd_desc)
  1939. return -ENOMEM;
  1940. return 0;
  1941. }
  1942. static int ath_tx_edma_init(struct ath_softc *sc)
  1943. {
  1944. int err;
  1945. err = ath_txstatus_setup(sc, ATH_TXSTATUS_RING_SIZE);
  1946. if (!err)
  1947. ath9k_hw_setup_statusring(sc->sc_ah, sc->txsdma.dd_desc,
  1948. sc->txsdma.dd_desc_paddr,
  1949. ATH_TXSTATUS_RING_SIZE);
  1950. return err;
  1951. }
  1952. static void ath_tx_edma_cleanup(struct ath_softc *sc)
  1953. {
  1954. struct ath_descdma *dd = &sc->txsdma;
  1955. dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
  1956. dd->dd_desc_paddr);
  1957. }
  1958. int ath_tx_init(struct ath_softc *sc, int nbufs)
  1959. {
  1960. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1961. int error = 0;
  1962. spin_lock_init(&sc->tx.txbuflock);
  1963. error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf,
  1964. "tx", nbufs, 1, 1);
  1965. if (error != 0) {
  1966. ath_err(common,
  1967. "Failed to allocate tx descriptors: %d\n", error);
  1968. goto err;
  1969. }
  1970. error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf,
  1971. "beacon", ATH_BCBUF, 1, 1);
  1972. if (error != 0) {
  1973. ath_err(common,
  1974. "Failed to allocate beacon descriptors: %d\n", error);
  1975. goto err;
  1976. }
  1977. INIT_DELAYED_WORK(&sc->tx_complete_work, ath_tx_complete_poll_work);
  1978. if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
  1979. error = ath_tx_edma_init(sc);
  1980. if (error)
  1981. goto err;
  1982. }
  1983. err:
  1984. if (error != 0)
  1985. ath_tx_cleanup(sc);
  1986. return error;
  1987. }
  1988. void ath_tx_cleanup(struct ath_softc *sc)
  1989. {
  1990. if (sc->beacon.bdma.dd_desc_len != 0)
  1991. ath_descdma_cleanup(sc, &sc->beacon.bdma, &sc->beacon.bbuf);
  1992. if (sc->tx.txdma.dd_desc_len != 0)
  1993. ath_descdma_cleanup(sc, &sc->tx.txdma, &sc->tx.txbuf);
  1994. if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  1995. ath_tx_edma_cleanup(sc);
  1996. }
  1997. void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
  1998. {
  1999. struct ath_atx_tid *tid;
  2000. struct ath_atx_ac *ac;
  2001. int tidno, acno;
  2002. for (tidno = 0, tid = &an->tid[tidno];
  2003. tidno < WME_NUM_TID;
  2004. tidno++, tid++) {
  2005. tid->an = an;
  2006. tid->tidno = tidno;
  2007. tid->seq_start = tid->seq_next = 0;
  2008. tid->baw_size = WME_MAX_BA;
  2009. tid->baw_head = tid->baw_tail = 0;
  2010. tid->sched = false;
  2011. tid->paused = false;
  2012. tid->state &= ~AGGR_CLEANUP;
  2013. __skb_queue_head_init(&tid->buf_q);
  2014. acno = TID_TO_WME_AC(tidno);
  2015. tid->ac = &an->ac[acno];
  2016. tid->state &= ~AGGR_ADDBA_COMPLETE;
  2017. tid->state &= ~AGGR_ADDBA_PROGRESS;
  2018. }
  2019. for (acno = 0, ac = &an->ac[acno];
  2020. acno < WME_NUM_AC; acno++, ac++) {
  2021. ac->sched = false;
  2022. ac->txq = sc->tx.txq_map[acno];
  2023. INIT_LIST_HEAD(&ac->tid_q);
  2024. }
  2025. }
  2026. void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an)
  2027. {
  2028. struct ath_atx_ac *ac;
  2029. struct ath_atx_tid *tid;
  2030. struct ath_txq *txq;
  2031. int tidno;
  2032. for (tidno = 0, tid = &an->tid[tidno];
  2033. tidno < WME_NUM_TID; tidno++, tid++) {
  2034. ac = tid->ac;
  2035. txq = ac->txq;
  2036. ath_txq_lock(sc, txq);
  2037. if (tid->sched) {
  2038. list_del(&tid->list);
  2039. tid->sched = false;
  2040. }
  2041. if (ac->sched) {
  2042. list_del(&ac->list);
  2043. tid->ac->sched = false;
  2044. }
  2045. ath_tid_drain(sc, txq, tid);
  2046. tid->state &= ~AGGR_ADDBA_COMPLETE;
  2047. tid->state &= ~AGGR_CLEANUP;
  2048. ath_txq_unlock(sc, txq);
  2049. }
  2050. }