lmc_main.c 61 KB

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  1. /*
  2. * Copyright (c) 1997-2000 LAN Media Corporation (LMC)
  3. * All rights reserved. www.lanmedia.com
  4. * Generic HDLC port Copyright (C) 2008 Krzysztof Halasa <khc@pm.waw.pl>
  5. *
  6. * This code is written by:
  7. * Andrew Stanley-Jones (asj@cban.com)
  8. * Rob Braun (bbraun@vix.com),
  9. * Michael Graff (explorer@vix.com) and
  10. * Matt Thomas (matt@3am-software.com).
  11. *
  12. * With Help By:
  13. * David Boggs
  14. * Ron Crane
  15. * Alan Cox
  16. *
  17. * This software may be used and distributed according to the terms
  18. * of the GNU General Public License version 2, incorporated herein by reference.
  19. *
  20. * Driver for the LanMedia LMC5200, LMC5245, LMC1000, LMC1200 cards.
  21. *
  22. * To control link specific options lmcctl is required.
  23. * It can be obtained from ftp.lanmedia.com.
  24. *
  25. * Linux driver notes:
  26. * Linux uses the device struct lmc_private to pass private information
  27. * around.
  28. *
  29. * The initialization portion of this driver (the lmc_reset() and the
  30. * lmc_dec_reset() functions, as well as the led controls and the
  31. * lmc_initcsrs() functions.
  32. *
  33. * The watchdog function runs every second and checks to see if
  34. * we still have link, and that the timing source is what we expected
  35. * it to be. If link is lost, the interface is marked down, and
  36. * we no longer can transmit.
  37. *
  38. */
  39. #include <linux/kernel.h>
  40. #include <linux/module.h>
  41. #include <linux/string.h>
  42. #include <linux/timer.h>
  43. #include <linux/ptrace.h>
  44. #include <linux/errno.h>
  45. #include <linux/ioport.h>
  46. #include <linux/slab.h>
  47. #include <linux/interrupt.h>
  48. #include <linux/pci.h>
  49. #include <linux/delay.h>
  50. #include <linux/hdlc.h>
  51. #include <linux/init.h>
  52. #include <linux/in.h>
  53. #include <linux/if_arp.h>
  54. #include <linux/netdevice.h>
  55. #include <linux/etherdevice.h>
  56. #include <linux/skbuff.h>
  57. #include <linux/inet.h>
  58. #include <linux/bitops.h>
  59. #include <asm/processor.h> /* Processor type for cache alignment. */
  60. #include <asm/io.h>
  61. #include <asm/dma.h>
  62. #include <asm/uaccess.h>
  63. //#include <asm/spinlock.h>
  64. #define DRIVER_MAJOR_VERSION 1
  65. #define DRIVER_MINOR_VERSION 34
  66. #define DRIVER_SUB_VERSION 0
  67. #define DRIVER_VERSION ((DRIVER_MAJOR_VERSION << 8) + DRIVER_MINOR_VERSION)
  68. #include "lmc.h"
  69. #include "lmc_var.h"
  70. #include "lmc_ioctl.h"
  71. #include "lmc_debug.h"
  72. #include "lmc_proto.h"
  73. static int LMC_PKT_BUF_SZ = 1542;
  74. static DEFINE_PCI_DEVICE_TABLE(lmc_pci_tbl) = {
  75. { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_FAST,
  76. PCI_VENDOR_ID_LMC, PCI_ANY_ID },
  77. { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_FAST,
  78. PCI_ANY_ID, PCI_VENDOR_ID_LMC },
  79. { 0 }
  80. };
  81. MODULE_DEVICE_TABLE(pci, lmc_pci_tbl);
  82. MODULE_LICENSE("GPL v2");
  83. static netdev_tx_t lmc_start_xmit(struct sk_buff *skb,
  84. struct net_device *dev);
  85. static int lmc_rx (struct net_device *dev);
  86. static int lmc_open(struct net_device *dev);
  87. static int lmc_close(struct net_device *dev);
  88. static struct net_device_stats *lmc_get_stats(struct net_device *dev);
  89. static irqreturn_t lmc_interrupt(int irq, void *dev_instance);
  90. static void lmc_initcsrs(lmc_softc_t * const sc, lmc_csrptr_t csr_base, size_t csr_size);
  91. static void lmc_softreset(lmc_softc_t * const);
  92. static void lmc_running_reset(struct net_device *dev);
  93. static int lmc_ifdown(struct net_device * const);
  94. static void lmc_watchdog(unsigned long data);
  95. static void lmc_reset(lmc_softc_t * const sc);
  96. static void lmc_dec_reset(lmc_softc_t * const sc);
  97. static void lmc_driver_timeout(struct net_device *dev);
  98. /*
  99. * linux reserves 16 device specific IOCTLs. We call them
  100. * LMCIOC* to control various bits of our world.
  101. */
  102. int lmc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) /*fold00*/
  103. {
  104. lmc_softc_t *sc = dev_to_sc(dev);
  105. lmc_ctl_t ctl;
  106. int ret = -EOPNOTSUPP;
  107. u16 regVal;
  108. unsigned long flags;
  109. lmc_trace(dev, "lmc_ioctl in");
  110. /*
  111. * Most functions mess with the structure
  112. * Disable interrupts while we do the polling
  113. */
  114. switch (cmd) {
  115. /*
  116. * Return current driver state. Since we keep this up
  117. * To date internally, just copy this out to the user.
  118. */
  119. case LMCIOCGINFO: /*fold01*/
  120. if (copy_to_user(ifr->ifr_data, &sc->ictl, sizeof(lmc_ctl_t)))
  121. ret = -EFAULT;
  122. else
  123. ret = 0;
  124. break;
  125. case LMCIOCSINFO: /*fold01*/
  126. if (!capable(CAP_NET_ADMIN)) {
  127. ret = -EPERM;
  128. break;
  129. }
  130. if(dev->flags & IFF_UP){
  131. ret = -EBUSY;
  132. break;
  133. }
  134. if (copy_from_user(&ctl, ifr->ifr_data, sizeof(lmc_ctl_t))) {
  135. ret = -EFAULT;
  136. break;
  137. }
  138. spin_lock_irqsave(&sc->lmc_lock, flags);
  139. sc->lmc_media->set_status (sc, &ctl);
  140. if(ctl.crc_length != sc->ictl.crc_length) {
  141. sc->lmc_media->set_crc_length(sc, ctl.crc_length);
  142. if (sc->ictl.crc_length == LMC_CTL_CRC_LENGTH_16)
  143. sc->TxDescriptControlInit |= LMC_TDES_ADD_CRC_DISABLE;
  144. else
  145. sc->TxDescriptControlInit &= ~LMC_TDES_ADD_CRC_DISABLE;
  146. }
  147. spin_unlock_irqrestore(&sc->lmc_lock, flags);
  148. ret = 0;
  149. break;
  150. case LMCIOCIFTYPE: /*fold01*/
  151. {
  152. u16 old_type = sc->if_type;
  153. u16 new_type;
  154. if (!capable(CAP_NET_ADMIN)) {
  155. ret = -EPERM;
  156. break;
  157. }
  158. if (copy_from_user(&new_type, ifr->ifr_data, sizeof(u16))) {
  159. ret = -EFAULT;
  160. break;
  161. }
  162. if (new_type == old_type)
  163. {
  164. ret = 0 ;
  165. break; /* no change */
  166. }
  167. spin_lock_irqsave(&sc->lmc_lock, flags);
  168. lmc_proto_close(sc);
  169. sc->if_type = new_type;
  170. lmc_proto_attach(sc);
  171. ret = lmc_proto_open(sc);
  172. spin_unlock_irqrestore(&sc->lmc_lock, flags);
  173. break;
  174. }
  175. case LMCIOCGETXINFO: /*fold01*/
  176. spin_lock_irqsave(&sc->lmc_lock, flags);
  177. sc->lmc_xinfo.Magic0 = 0xBEEFCAFE;
  178. sc->lmc_xinfo.PciCardType = sc->lmc_cardtype;
  179. sc->lmc_xinfo.PciSlotNumber = 0;
  180. sc->lmc_xinfo.DriverMajorVersion = DRIVER_MAJOR_VERSION;
  181. sc->lmc_xinfo.DriverMinorVersion = DRIVER_MINOR_VERSION;
  182. sc->lmc_xinfo.DriverSubVersion = DRIVER_SUB_VERSION;
  183. sc->lmc_xinfo.XilinxRevisionNumber =
  184. lmc_mii_readreg (sc, 0, 3) & 0xf;
  185. sc->lmc_xinfo.MaxFrameSize = LMC_PKT_BUF_SZ;
  186. sc->lmc_xinfo.link_status = sc->lmc_media->get_link_status (sc);
  187. sc->lmc_xinfo.mii_reg16 = lmc_mii_readreg (sc, 0, 16);
  188. spin_unlock_irqrestore(&sc->lmc_lock, flags);
  189. sc->lmc_xinfo.Magic1 = 0xDEADBEEF;
  190. if (copy_to_user(ifr->ifr_data, &sc->lmc_xinfo,
  191. sizeof(struct lmc_xinfo)))
  192. ret = -EFAULT;
  193. else
  194. ret = 0;
  195. break;
  196. case LMCIOCGETLMCSTATS:
  197. spin_lock_irqsave(&sc->lmc_lock, flags);
  198. if (sc->lmc_cardtype == LMC_CARDTYPE_T1) {
  199. lmc_mii_writereg(sc, 0, 17, T1FRAMER_FERR_LSB);
  200. sc->extra_stats.framingBitErrorCount +=
  201. lmc_mii_readreg(sc, 0, 18) & 0xff;
  202. lmc_mii_writereg(sc, 0, 17, T1FRAMER_FERR_MSB);
  203. sc->extra_stats.framingBitErrorCount +=
  204. (lmc_mii_readreg(sc, 0, 18) & 0xff) << 8;
  205. lmc_mii_writereg(sc, 0, 17, T1FRAMER_LCV_LSB);
  206. sc->extra_stats.lineCodeViolationCount +=
  207. lmc_mii_readreg(sc, 0, 18) & 0xff;
  208. lmc_mii_writereg(sc, 0, 17, T1FRAMER_LCV_MSB);
  209. sc->extra_stats.lineCodeViolationCount +=
  210. (lmc_mii_readreg(sc, 0, 18) & 0xff) << 8;
  211. lmc_mii_writereg(sc, 0, 17, T1FRAMER_AERR);
  212. regVal = lmc_mii_readreg(sc, 0, 18) & 0xff;
  213. sc->extra_stats.lossOfFrameCount +=
  214. (regVal & T1FRAMER_LOF_MASK) >> 4;
  215. sc->extra_stats.changeOfFrameAlignmentCount +=
  216. (regVal & T1FRAMER_COFA_MASK) >> 2;
  217. sc->extra_stats.severelyErroredFrameCount +=
  218. regVal & T1FRAMER_SEF_MASK;
  219. }
  220. spin_unlock_irqrestore(&sc->lmc_lock, flags);
  221. if (copy_to_user(ifr->ifr_data, &sc->lmc_device->stats,
  222. sizeof(sc->lmc_device->stats)) ||
  223. copy_to_user(ifr->ifr_data + sizeof(sc->lmc_device->stats),
  224. &sc->extra_stats, sizeof(sc->extra_stats)))
  225. ret = -EFAULT;
  226. else
  227. ret = 0;
  228. break;
  229. case LMCIOCCLEARLMCSTATS:
  230. if (!capable(CAP_NET_ADMIN)) {
  231. ret = -EPERM;
  232. break;
  233. }
  234. spin_lock_irqsave(&sc->lmc_lock, flags);
  235. memset(&sc->lmc_device->stats, 0, sizeof(sc->lmc_device->stats));
  236. memset(&sc->extra_stats, 0, sizeof(sc->extra_stats));
  237. sc->extra_stats.check = STATCHECK;
  238. sc->extra_stats.version_size = (DRIVER_VERSION << 16) +
  239. sizeof(sc->lmc_device->stats) + sizeof(sc->extra_stats);
  240. sc->extra_stats.lmc_cardtype = sc->lmc_cardtype;
  241. spin_unlock_irqrestore(&sc->lmc_lock, flags);
  242. ret = 0;
  243. break;
  244. case LMCIOCSETCIRCUIT: /*fold01*/
  245. if (!capable(CAP_NET_ADMIN)){
  246. ret = -EPERM;
  247. break;
  248. }
  249. if(dev->flags & IFF_UP){
  250. ret = -EBUSY;
  251. break;
  252. }
  253. if (copy_from_user(&ctl, ifr->ifr_data, sizeof(lmc_ctl_t))) {
  254. ret = -EFAULT;
  255. break;
  256. }
  257. spin_lock_irqsave(&sc->lmc_lock, flags);
  258. sc->lmc_media->set_circuit_type(sc, ctl.circuit_type);
  259. sc->ictl.circuit_type = ctl.circuit_type;
  260. spin_unlock_irqrestore(&sc->lmc_lock, flags);
  261. ret = 0;
  262. break;
  263. case LMCIOCRESET: /*fold01*/
  264. if (!capable(CAP_NET_ADMIN)){
  265. ret = -EPERM;
  266. break;
  267. }
  268. spin_lock_irqsave(&sc->lmc_lock, flags);
  269. /* Reset driver and bring back to current state */
  270. printk (" REG16 before reset +%04x\n", lmc_mii_readreg (sc, 0, 16));
  271. lmc_running_reset (dev);
  272. printk (" REG16 after reset +%04x\n", lmc_mii_readreg (sc, 0, 16));
  273. LMC_EVENT_LOG(LMC_EVENT_FORCEDRESET, LMC_CSR_READ (sc, csr_status), lmc_mii_readreg (sc, 0, 16));
  274. spin_unlock_irqrestore(&sc->lmc_lock, flags);
  275. ret = 0;
  276. break;
  277. #ifdef DEBUG
  278. case LMCIOCDUMPEVENTLOG:
  279. if (copy_to_user(ifr->ifr_data, &lmcEventLogIndex, sizeof(u32))) {
  280. ret = -EFAULT;
  281. break;
  282. }
  283. if (copy_to_user(ifr->ifr_data + sizeof(u32), lmcEventLogBuf,
  284. sizeof(lmcEventLogBuf)))
  285. ret = -EFAULT;
  286. else
  287. ret = 0;
  288. break;
  289. #endif /* end ifdef _DBG_EVENTLOG */
  290. case LMCIOCT1CONTROL: /*fold01*/
  291. if (sc->lmc_cardtype != LMC_CARDTYPE_T1){
  292. ret = -EOPNOTSUPP;
  293. break;
  294. }
  295. break;
  296. case LMCIOCXILINX: /*fold01*/
  297. {
  298. struct lmc_xilinx_control xc; /*fold02*/
  299. if (!capable(CAP_NET_ADMIN)){
  300. ret = -EPERM;
  301. break;
  302. }
  303. /*
  304. * Stop the xwitter whlie we restart the hardware
  305. */
  306. netif_stop_queue(dev);
  307. if (copy_from_user(&xc, ifr->ifr_data, sizeof(struct lmc_xilinx_control))) {
  308. ret = -EFAULT;
  309. break;
  310. }
  311. switch(xc.command){
  312. case lmc_xilinx_reset: /*fold02*/
  313. {
  314. u16 mii;
  315. spin_lock_irqsave(&sc->lmc_lock, flags);
  316. mii = lmc_mii_readreg (sc, 0, 16);
  317. /*
  318. * Make all of them 0 and make input
  319. */
  320. lmc_gpio_mkinput(sc, 0xff);
  321. /*
  322. * make the reset output
  323. */
  324. lmc_gpio_mkoutput(sc, LMC_GEP_RESET);
  325. /*
  326. * RESET low to force configuration. This also forces
  327. * the transmitter clock to be internal, but we expect to reset
  328. * that later anyway.
  329. */
  330. sc->lmc_gpio &= ~LMC_GEP_RESET;
  331. LMC_CSR_WRITE(sc, csr_gp, sc->lmc_gpio);
  332. /*
  333. * hold for more than 10 microseconds
  334. */
  335. udelay(50);
  336. sc->lmc_gpio |= LMC_GEP_RESET;
  337. LMC_CSR_WRITE(sc, csr_gp, sc->lmc_gpio);
  338. /*
  339. * stop driving Xilinx-related signals
  340. */
  341. lmc_gpio_mkinput(sc, 0xff);
  342. /* Reset the frammer hardware */
  343. sc->lmc_media->set_link_status (sc, 1);
  344. sc->lmc_media->set_status (sc, NULL);
  345. // lmc_softreset(sc);
  346. {
  347. int i;
  348. for(i = 0; i < 5; i++){
  349. lmc_led_on(sc, LMC_DS3_LED0);
  350. mdelay(100);
  351. lmc_led_off(sc, LMC_DS3_LED0);
  352. lmc_led_on(sc, LMC_DS3_LED1);
  353. mdelay(100);
  354. lmc_led_off(sc, LMC_DS3_LED1);
  355. lmc_led_on(sc, LMC_DS3_LED3);
  356. mdelay(100);
  357. lmc_led_off(sc, LMC_DS3_LED3);
  358. lmc_led_on(sc, LMC_DS3_LED2);
  359. mdelay(100);
  360. lmc_led_off(sc, LMC_DS3_LED2);
  361. }
  362. }
  363. spin_unlock_irqrestore(&sc->lmc_lock, flags);
  364. ret = 0x0;
  365. }
  366. break;
  367. case lmc_xilinx_load_prom: /*fold02*/
  368. {
  369. u16 mii;
  370. int timeout = 500000;
  371. spin_lock_irqsave(&sc->lmc_lock, flags);
  372. mii = lmc_mii_readreg (sc, 0, 16);
  373. /*
  374. * Make all of them 0 and make input
  375. */
  376. lmc_gpio_mkinput(sc, 0xff);
  377. /*
  378. * make the reset output
  379. */
  380. lmc_gpio_mkoutput(sc, LMC_GEP_DP | LMC_GEP_RESET);
  381. /*
  382. * RESET low to force configuration. This also forces
  383. * the transmitter clock to be internal, but we expect to reset
  384. * that later anyway.
  385. */
  386. sc->lmc_gpio &= ~(LMC_GEP_RESET | LMC_GEP_DP);
  387. LMC_CSR_WRITE(sc, csr_gp, sc->lmc_gpio);
  388. /*
  389. * hold for more than 10 microseconds
  390. */
  391. udelay(50);
  392. sc->lmc_gpio |= LMC_GEP_DP | LMC_GEP_RESET;
  393. LMC_CSR_WRITE(sc, csr_gp, sc->lmc_gpio);
  394. /*
  395. * busy wait for the chip to reset
  396. */
  397. while( (LMC_CSR_READ(sc, csr_gp) & LMC_GEP_INIT) == 0 &&
  398. (timeout-- > 0))
  399. cpu_relax();
  400. /*
  401. * stop driving Xilinx-related signals
  402. */
  403. lmc_gpio_mkinput(sc, 0xff);
  404. spin_unlock_irqrestore(&sc->lmc_lock, flags);
  405. ret = 0x0;
  406. break;
  407. }
  408. case lmc_xilinx_load: /*fold02*/
  409. {
  410. char *data;
  411. int pos;
  412. int timeout = 500000;
  413. if (!xc.data) {
  414. ret = -EINVAL;
  415. break;
  416. }
  417. data = kmalloc(xc.len, GFP_KERNEL);
  418. if (!data) {
  419. ret = -ENOMEM;
  420. break;
  421. }
  422. if(copy_from_user(data, xc.data, xc.len))
  423. {
  424. kfree(data);
  425. ret = -ENOMEM;
  426. break;
  427. }
  428. printk("%s: Starting load of data Len: %d at 0x%p == 0x%p\n", dev->name, xc.len, xc.data, data);
  429. spin_lock_irqsave(&sc->lmc_lock, flags);
  430. lmc_gpio_mkinput(sc, 0xff);
  431. /*
  432. * Clear the Xilinx and start prgramming from the DEC
  433. */
  434. /*
  435. * Set ouput as:
  436. * Reset: 0 (active)
  437. * DP: 0 (active)
  438. * Mode: 1
  439. *
  440. */
  441. sc->lmc_gpio = 0x00;
  442. sc->lmc_gpio &= ~LMC_GEP_DP;
  443. sc->lmc_gpio &= ~LMC_GEP_RESET;
  444. sc->lmc_gpio |= LMC_GEP_MODE;
  445. LMC_CSR_WRITE(sc, csr_gp, sc->lmc_gpio);
  446. lmc_gpio_mkoutput(sc, LMC_GEP_MODE | LMC_GEP_DP | LMC_GEP_RESET);
  447. /*
  448. * Wait at least 10 us 20 to be safe
  449. */
  450. udelay(50);
  451. /*
  452. * Clear reset and activate programming lines
  453. * Reset: Input
  454. * DP: Input
  455. * Clock: Output
  456. * Data: Output
  457. * Mode: Output
  458. */
  459. lmc_gpio_mkinput(sc, LMC_GEP_DP | LMC_GEP_RESET);
  460. /*
  461. * Set LOAD, DATA, Clock to 1
  462. */
  463. sc->lmc_gpio = 0x00;
  464. sc->lmc_gpio |= LMC_GEP_MODE;
  465. sc->lmc_gpio |= LMC_GEP_DATA;
  466. sc->lmc_gpio |= LMC_GEP_CLK;
  467. LMC_CSR_WRITE(sc, csr_gp, sc->lmc_gpio);
  468. lmc_gpio_mkoutput(sc, LMC_GEP_DATA | LMC_GEP_CLK | LMC_GEP_MODE );
  469. /*
  470. * busy wait for the chip to reset
  471. */
  472. while( (LMC_CSR_READ(sc, csr_gp) & LMC_GEP_INIT) == 0 &&
  473. (timeout-- > 0))
  474. cpu_relax();
  475. printk(KERN_DEBUG "%s: Waited %d for the Xilinx to clear it's memory\n", dev->name, 500000-timeout);
  476. for(pos = 0; pos < xc.len; pos++){
  477. switch(data[pos]){
  478. case 0:
  479. sc->lmc_gpio &= ~LMC_GEP_DATA; /* Data is 0 */
  480. break;
  481. case 1:
  482. sc->lmc_gpio |= LMC_GEP_DATA; /* Data is 1 */
  483. break;
  484. default:
  485. printk(KERN_WARNING "%s Bad data in xilinx programming data at %d, got %d wanted 0 or 1\n", dev->name, pos, data[pos]);
  486. sc->lmc_gpio |= LMC_GEP_DATA; /* Assume it's 1 */
  487. }
  488. sc->lmc_gpio &= ~LMC_GEP_CLK; /* Clock to zero */
  489. sc->lmc_gpio |= LMC_GEP_MODE;
  490. LMC_CSR_WRITE(sc, csr_gp, sc->lmc_gpio);
  491. udelay(1);
  492. sc->lmc_gpio |= LMC_GEP_CLK; /* Put the clack back to one */
  493. sc->lmc_gpio |= LMC_GEP_MODE;
  494. LMC_CSR_WRITE(sc, csr_gp, sc->lmc_gpio);
  495. udelay(1);
  496. }
  497. if((LMC_CSR_READ(sc, csr_gp) & LMC_GEP_INIT) == 0){
  498. printk(KERN_WARNING "%s: Reprogramming FAILED. Needs to be reprogrammed. (corrupted data)\n", dev->name);
  499. }
  500. else if((LMC_CSR_READ(sc, csr_gp) & LMC_GEP_DP) == 0){
  501. printk(KERN_WARNING "%s: Reprogramming FAILED. Needs to be reprogrammed. (done)\n", dev->name);
  502. }
  503. else {
  504. printk(KERN_DEBUG "%s: Done reprogramming Xilinx, %d bits, good luck!\n", dev->name, pos);
  505. }
  506. lmc_gpio_mkinput(sc, 0xff);
  507. sc->lmc_miireg16 |= LMC_MII16_FIFO_RESET;
  508. lmc_mii_writereg(sc, 0, 16, sc->lmc_miireg16);
  509. sc->lmc_miireg16 &= ~LMC_MII16_FIFO_RESET;
  510. lmc_mii_writereg(sc, 0, 16, sc->lmc_miireg16);
  511. spin_unlock_irqrestore(&sc->lmc_lock, flags);
  512. kfree(data);
  513. ret = 0;
  514. break;
  515. }
  516. default: /*fold02*/
  517. ret = -EBADE;
  518. break;
  519. }
  520. netif_wake_queue(dev);
  521. sc->lmc_txfull = 0;
  522. }
  523. break;
  524. default: /*fold01*/
  525. /* If we don't know what to do, give the protocol a shot. */
  526. ret = lmc_proto_ioctl (sc, ifr, cmd);
  527. break;
  528. }
  529. lmc_trace(dev, "lmc_ioctl out");
  530. return ret;
  531. }
  532. /* the watchdog process that cruises around */
  533. static void lmc_watchdog (unsigned long data) /*fold00*/
  534. {
  535. struct net_device *dev = (struct net_device *)data;
  536. lmc_softc_t *sc = dev_to_sc(dev);
  537. int link_status;
  538. u32 ticks;
  539. unsigned long flags;
  540. lmc_trace(dev, "lmc_watchdog in");
  541. spin_lock_irqsave(&sc->lmc_lock, flags);
  542. if(sc->check != 0xBEAFCAFE){
  543. printk("LMC: Corrupt net_device struct, breaking out\n");
  544. spin_unlock_irqrestore(&sc->lmc_lock, flags);
  545. return;
  546. }
  547. /* Make sure the tx jabber and rx watchdog are off,
  548. * and the transmit and receive processes are running.
  549. */
  550. LMC_CSR_WRITE (sc, csr_15, 0x00000011);
  551. sc->lmc_cmdmode |= TULIP_CMD_TXRUN | TULIP_CMD_RXRUN;
  552. LMC_CSR_WRITE (sc, csr_command, sc->lmc_cmdmode);
  553. if (sc->lmc_ok == 0)
  554. goto kick_timer;
  555. LMC_EVENT_LOG(LMC_EVENT_WATCHDOG, LMC_CSR_READ (sc, csr_status), lmc_mii_readreg (sc, 0, 16));
  556. /* --- begin time out check -----------------------------------
  557. * check for a transmit interrupt timeout
  558. * Has the packet xmt vs xmt serviced threshold been exceeded */
  559. if (sc->lmc_taint_tx == sc->lastlmc_taint_tx &&
  560. sc->lmc_device->stats.tx_packets > sc->lasttx_packets &&
  561. sc->tx_TimeoutInd == 0)
  562. {
  563. /* wait for the watchdog to come around again */
  564. sc->tx_TimeoutInd = 1;
  565. }
  566. else if (sc->lmc_taint_tx == sc->lastlmc_taint_tx &&
  567. sc->lmc_device->stats.tx_packets > sc->lasttx_packets &&
  568. sc->tx_TimeoutInd)
  569. {
  570. LMC_EVENT_LOG(LMC_EVENT_XMTINTTMO, LMC_CSR_READ (sc, csr_status), 0);
  571. sc->tx_TimeoutDisplay = 1;
  572. sc->extra_stats.tx_TimeoutCnt++;
  573. /* DEC chip is stuck, hit it with a RESET!!!! */
  574. lmc_running_reset (dev);
  575. /* look at receive & transmit process state to make sure they are running */
  576. LMC_EVENT_LOG(LMC_EVENT_RESET1, LMC_CSR_READ (sc, csr_status), 0);
  577. /* look at: DSR - 02 for Reg 16
  578. * CTS - 08
  579. * DCD - 10
  580. * RI - 20
  581. * for Reg 17
  582. */
  583. LMC_EVENT_LOG(LMC_EVENT_RESET2, lmc_mii_readreg (sc, 0, 16), lmc_mii_readreg (sc, 0, 17));
  584. /* reset the transmit timeout detection flag */
  585. sc->tx_TimeoutInd = 0;
  586. sc->lastlmc_taint_tx = sc->lmc_taint_tx;
  587. sc->lasttx_packets = sc->lmc_device->stats.tx_packets;
  588. } else {
  589. sc->tx_TimeoutInd = 0;
  590. sc->lastlmc_taint_tx = sc->lmc_taint_tx;
  591. sc->lasttx_packets = sc->lmc_device->stats.tx_packets;
  592. }
  593. /* --- end time out check ----------------------------------- */
  594. link_status = sc->lmc_media->get_link_status (sc);
  595. /*
  596. * hardware level link lost, but the interface is marked as up.
  597. * Mark it as down.
  598. */
  599. if ((link_status == 0) && (sc->last_link_status != 0)) {
  600. printk(KERN_WARNING "%s: hardware/physical link down\n", dev->name);
  601. sc->last_link_status = 0;
  602. /* lmc_reset (sc); Why reset??? The link can go down ok */
  603. /* Inform the world that link has been lost */
  604. netif_carrier_off(dev);
  605. }
  606. /*
  607. * hardware link is up, but the interface is marked as down.
  608. * Bring it back up again.
  609. */
  610. if (link_status != 0 && sc->last_link_status == 0) {
  611. printk(KERN_WARNING "%s: hardware/physical link up\n", dev->name);
  612. sc->last_link_status = 1;
  613. /* lmc_reset (sc); Again why reset??? */
  614. netif_carrier_on(dev);
  615. }
  616. /* Call media specific watchdog functions */
  617. sc->lmc_media->watchdog(sc);
  618. /*
  619. * Poke the transmitter to make sure it
  620. * never stops, even if we run out of mem
  621. */
  622. LMC_CSR_WRITE(sc, csr_rxpoll, 0);
  623. /*
  624. * Check for code that failed
  625. * and try and fix it as appropriate
  626. */
  627. if(sc->failed_ring == 1){
  628. /*
  629. * Failed to setup the recv/xmit rin
  630. * Try again
  631. */
  632. sc->failed_ring = 0;
  633. lmc_softreset(sc);
  634. }
  635. if(sc->failed_recv_alloc == 1){
  636. /*
  637. * We failed to alloc mem in the
  638. * interrupt handler, go through the rings
  639. * and rebuild them
  640. */
  641. sc->failed_recv_alloc = 0;
  642. lmc_softreset(sc);
  643. }
  644. /*
  645. * remember the timer value
  646. */
  647. kick_timer:
  648. ticks = LMC_CSR_READ (sc, csr_gp_timer);
  649. LMC_CSR_WRITE (sc, csr_gp_timer, 0xffffffffUL);
  650. sc->ictl.ticks = 0x0000ffff - (ticks & 0x0000ffff);
  651. /*
  652. * restart this timer.
  653. */
  654. sc->timer.expires = jiffies + (HZ);
  655. add_timer (&sc->timer);
  656. spin_unlock_irqrestore(&sc->lmc_lock, flags);
  657. lmc_trace(dev, "lmc_watchdog out");
  658. }
  659. static int lmc_attach(struct net_device *dev, unsigned short encoding,
  660. unsigned short parity)
  661. {
  662. if (encoding == ENCODING_NRZ && parity == PARITY_CRC16_PR1_CCITT)
  663. return 0;
  664. return -EINVAL;
  665. }
  666. static const struct net_device_ops lmc_ops = {
  667. .ndo_open = lmc_open,
  668. .ndo_stop = lmc_close,
  669. .ndo_change_mtu = hdlc_change_mtu,
  670. .ndo_start_xmit = hdlc_start_xmit,
  671. .ndo_do_ioctl = lmc_ioctl,
  672. .ndo_tx_timeout = lmc_driver_timeout,
  673. .ndo_get_stats = lmc_get_stats,
  674. };
  675. static int __devinit lmc_init_one(struct pci_dev *pdev,
  676. const struct pci_device_id *ent)
  677. {
  678. lmc_softc_t *sc;
  679. struct net_device *dev;
  680. u16 subdevice;
  681. u16 AdapModelNum;
  682. int err;
  683. static int cards_found;
  684. /* lmc_trace(dev, "lmc_init_one in"); */
  685. err = pci_enable_device(pdev);
  686. if (err) {
  687. printk(KERN_ERR "lmc: pci enable failed: %d\n", err);
  688. return err;
  689. }
  690. err = pci_request_regions(pdev, "lmc");
  691. if (err) {
  692. printk(KERN_ERR "lmc: pci_request_region failed\n");
  693. goto err_req_io;
  694. }
  695. /*
  696. * Allocate our own device structure
  697. */
  698. sc = kzalloc(sizeof(lmc_softc_t), GFP_KERNEL);
  699. if (!sc) {
  700. err = -ENOMEM;
  701. goto err_kzalloc;
  702. }
  703. dev = alloc_hdlcdev(sc);
  704. if (!dev) {
  705. printk(KERN_ERR "lmc:alloc_netdev for device failed\n");
  706. goto err_hdlcdev;
  707. }
  708. dev->type = ARPHRD_HDLC;
  709. dev_to_hdlc(dev)->xmit = lmc_start_xmit;
  710. dev_to_hdlc(dev)->attach = lmc_attach;
  711. dev->netdev_ops = &lmc_ops;
  712. dev->watchdog_timeo = HZ; /* 1 second */
  713. dev->tx_queue_len = 100;
  714. sc->lmc_device = dev;
  715. sc->name = dev->name;
  716. sc->if_type = LMC_PPP;
  717. sc->check = 0xBEAFCAFE;
  718. dev->base_addr = pci_resource_start(pdev, 0);
  719. dev->irq = pdev->irq;
  720. pci_set_drvdata(pdev, dev);
  721. SET_NETDEV_DEV(dev, &pdev->dev);
  722. /*
  723. * This will get the protocol layer ready and do any 1 time init's
  724. * Must have a valid sc and dev structure
  725. */
  726. lmc_proto_attach(sc);
  727. /* Init the spin lock so can call it latter */
  728. spin_lock_init(&sc->lmc_lock);
  729. pci_set_master(pdev);
  730. printk(KERN_INFO "%s: detected at %lx, irq %d\n", dev->name,
  731. dev->base_addr, dev->irq);
  732. err = register_hdlc_device(dev);
  733. if (err) {
  734. printk(KERN_ERR "%s: register_netdev failed.\n", dev->name);
  735. free_netdev(dev);
  736. goto err_hdlcdev;
  737. }
  738. sc->lmc_cardtype = LMC_CARDTYPE_UNKNOWN;
  739. sc->lmc_timing = LMC_CTL_CLOCK_SOURCE_EXT;
  740. /*
  741. *
  742. * Check either the subvendor or the subdevice, some systems reverse
  743. * the setting in the bois, seems to be version and arch dependent?
  744. * Fix the error, exchange the two values
  745. */
  746. if ((subdevice = pdev->subsystem_device) == PCI_VENDOR_ID_LMC)
  747. subdevice = pdev->subsystem_vendor;
  748. switch (subdevice) {
  749. case PCI_DEVICE_ID_LMC_HSSI:
  750. printk(KERN_INFO "%s: LMC HSSI\n", dev->name);
  751. sc->lmc_cardtype = LMC_CARDTYPE_HSSI;
  752. sc->lmc_media = &lmc_hssi_media;
  753. break;
  754. case PCI_DEVICE_ID_LMC_DS3:
  755. printk(KERN_INFO "%s: LMC DS3\n", dev->name);
  756. sc->lmc_cardtype = LMC_CARDTYPE_DS3;
  757. sc->lmc_media = &lmc_ds3_media;
  758. break;
  759. case PCI_DEVICE_ID_LMC_SSI:
  760. printk(KERN_INFO "%s: LMC SSI\n", dev->name);
  761. sc->lmc_cardtype = LMC_CARDTYPE_SSI;
  762. sc->lmc_media = &lmc_ssi_media;
  763. break;
  764. case PCI_DEVICE_ID_LMC_T1:
  765. printk(KERN_INFO "%s: LMC T1\n", dev->name);
  766. sc->lmc_cardtype = LMC_CARDTYPE_T1;
  767. sc->lmc_media = &lmc_t1_media;
  768. break;
  769. default:
  770. printk(KERN_WARNING "%s: LMC UNKNOWN CARD!\n", dev->name);
  771. break;
  772. }
  773. lmc_initcsrs (sc, dev->base_addr, 8);
  774. lmc_gpio_mkinput (sc, 0xff);
  775. sc->lmc_gpio = 0; /* drive no signals yet */
  776. sc->lmc_media->defaults (sc);
  777. sc->lmc_media->set_link_status (sc, LMC_LINK_UP);
  778. /* verify that the PCI Sub System ID matches the Adapter Model number
  779. * from the MII register
  780. */
  781. AdapModelNum = (lmc_mii_readreg (sc, 0, 3) & 0x3f0) >> 4;
  782. if ((AdapModelNum != LMC_ADAP_T1 || /* detect LMC1200 */
  783. subdevice != PCI_DEVICE_ID_LMC_T1) &&
  784. (AdapModelNum != LMC_ADAP_SSI || /* detect LMC1000 */
  785. subdevice != PCI_DEVICE_ID_LMC_SSI) &&
  786. (AdapModelNum != LMC_ADAP_DS3 || /* detect LMC5245 */
  787. subdevice != PCI_DEVICE_ID_LMC_DS3) &&
  788. (AdapModelNum != LMC_ADAP_HSSI || /* detect LMC5200 */
  789. subdevice != PCI_DEVICE_ID_LMC_HSSI))
  790. printk(KERN_WARNING "%s: Model number (%d) miscompare for PCI"
  791. " Subsystem ID = 0x%04x\n",
  792. dev->name, AdapModelNum, subdevice);
  793. /*
  794. * reset clock
  795. */
  796. LMC_CSR_WRITE (sc, csr_gp_timer, 0xFFFFFFFFUL);
  797. sc->board_idx = cards_found++;
  798. sc->extra_stats.check = STATCHECK;
  799. sc->extra_stats.version_size = (DRIVER_VERSION << 16) +
  800. sizeof(sc->lmc_device->stats) + sizeof(sc->extra_stats);
  801. sc->extra_stats.lmc_cardtype = sc->lmc_cardtype;
  802. sc->lmc_ok = 0;
  803. sc->last_link_status = 0;
  804. lmc_trace(dev, "lmc_init_one out");
  805. return 0;
  806. err_hdlcdev:
  807. pci_set_drvdata(pdev, NULL);
  808. kfree(sc);
  809. err_kzalloc:
  810. pci_release_regions(pdev);
  811. err_req_io:
  812. pci_disable_device(pdev);
  813. return err;
  814. }
  815. /*
  816. * Called from pci when removing module.
  817. */
  818. static void __devexit lmc_remove_one(struct pci_dev *pdev)
  819. {
  820. struct net_device *dev = pci_get_drvdata(pdev);
  821. if (dev) {
  822. printk(KERN_DEBUG "%s: removing...\n", dev->name);
  823. unregister_hdlc_device(dev);
  824. free_netdev(dev);
  825. pci_release_regions(pdev);
  826. pci_disable_device(pdev);
  827. pci_set_drvdata(pdev, NULL);
  828. }
  829. }
  830. /* After this is called, packets can be sent.
  831. * Does not initialize the addresses
  832. */
  833. static int lmc_open(struct net_device *dev)
  834. {
  835. lmc_softc_t *sc = dev_to_sc(dev);
  836. int err;
  837. lmc_trace(dev, "lmc_open in");
  838. lmc_led_on(sc, LMC_DS3_LED0);
  839. lmc_dec_reset(sc);
  840. lmc_reset(sc);
  841. LMC_EVENT_LOG(LMC_EVENT_RESET1, LMC_CSR_READ(sc, csr_status), 0);
  842. LMC_EVENT_LOG(LMC_EVENT_RESET2, lmc_mii_readreg(sc, 0, 16),
  843. lmc_mii_readreg(sc, 0, 17));
  844. if (sc->lmc_ok){
  845. lmc_trace(dev, "lmc_open lmc_ok out");
  846. return 0;
  847. }
  848. lmc_softreset (sc);
  849. /* Since we have to use PCI bus, this should work on x86,alpha,ppc */
  850. if (request_irq (dev->irq, lmc_interrupt, IRQF_SHARED, dev->name, dev)){
  851. printk(KERN_WARNING "%s: could not get irq: %d\n", dev->name, dev->irq);
  852. lmc_trace(dev, "lmc_open irq failed out");
  853. return -EAGAIN;
  854. }
  855. sc->got_irq = 1;
  856. /* Assert Terminal Active */
  857. sc->lmc_miireg16 |= LMC_MII16_LED_ALL;
  858. sc->lmc_media->set_link_status (sc, LMC_LINK_UP);
  859. /*
  860. * reset to last state.
  861. */
  862. sc->lmc_media->set_status (sc, NULL);
  863. /* setup default bits to be used in tulip_desc_t transmit descriptor
  864. * -baz */
  865. sc->TxDescriptControlInit = (
  866. LMC_TDES_INTERRUPT_ON_COMPLETION
  867. | LMC_TDES_FIRST_SEGMENT
  868. | LMC_TDES_LAST_SEGMENT
  869. | LMC_TDES_SECOND_ADDR_CHAINED
  870. | LMC_TDES_DISABLE_PADDING
  871. );
  872. if (sc->ictl.crc_length == LMC_CTL_CRC_LENGTH_16) {
  873. /* disable 32 bit CRC generated by ASIC */
  874. sc->TxDescriptControlInit |= LMC_TDES_ADD_CRC_DISABLE;
  875. }
  876. sc->lmc_media->set_crc_length(sc, sc->ictl.crc_length);
  877. /* Acknoledge the Terminal Active and light LEDs */
  878. /* dev->flags |= IFF_UP; */
  879. if ((err = lmc_proto_open(sc)) != 0)
  880. return err;
  881. netif_start_queue(dev);
  882. sc->extra_stats.tx_tbusy0++;
  883. /*
  884. * select what interrupts we want to get
  885. */
  886. sc->lmc_intrmask = 0;
  887. /* Should be using the default interrupt mask defined in the .h file. */
  888. sc->lmc_intrmask |= (TULIP_STS_NORMALINTR
  889. | TULIP_STS_RXINTR
  890. | TULIP_STS_TXINTR
  891. | TULIP_STS_ABNRMLINTR
  892. | TULIP_STS_SYSERROR
  893. | TULIP_STS_TXSTOPPED
  894. | TULIP_STS_TXUNDERFLOW
  895. | TULIP_STS_RXSTOPPED
  896. | TULIP_STS_RXNOBUF
  897. );
  898. LMC_CSR_WRITE (sc, csr_intr, sc->lmc_intrmask);
  899. sc->lmc_cmdmode |= TULIP_CMD_TXRUN;
  900. sc->lmc_cmdmode |= TULIP_CMD_RXRUN;
  901. LMC_CSR_WRITE (sc, csr_command, sc->lmc_cmdmode);
  902. sc->lmc_ok = 1; /* Run watchdog */
  903. /*
  904. * Set the if up now - pfb
  905. */
  906. sc->last_link_status = 1;
  907. /*
  908. * Setup a timer for the watchdog on probe, and start it running.
  909. * Since lmc_ok == 0, it will be a NOP for now.
  910. */
  911. init_timer (&sc->timer);
  912. sc->timer.expires = jiffies + HZ;
  913. sc->timer.data = (unsigned long) dev;
  914. sc->timer.function = lmc_watchdog;
  915. add_timer (&sc->timer);
  916. lmc_trace(dev, "lmc_open out");
  917. return 0;
  918. }
  919. /* Total reset to compensate for the AdTran DSU doing bad things
  920. * under heavy load
  921. */
  922. static void lmc_running_reset (struct net_device *dev) /*fold00*/
  923. {
  924. lmc_softc_t *sc = dev_to_sc(dev);
  925. lmc_trace(dev, "lmc_running_reset in");
  926. /* stop interrupts */
  927. /* Clear the interrupt mask */
  928. LMC_CSR_WRITE (sc, csr_intr, 0x00000000);
  929. lmc_dec_reset (sc);
  930. lmc_reset (sc);
  931. lmc_softreset (sc);
  932. /* sc->lmc_miireg16 |= LMC_MII16_LED_ALL; */
  933. sc->lmc_media->set_link_status (sc, 1);
  934. sc->lmc_media->set_status (sc, NULL);
  935. netif_wake_queue(dev);
  936. sc->lmc_txfull = 0;
  937. sc->extra_stats.tx_tbusy0++;
  938. sc->lmc_intrmask = TULIP_DEFAULT_INTR_MASK;
  939. LMC_CSR_WRITE (sc, csr_intr, sc->lmc_intrmask);
  940. sc->lmc_cmdmode |= (TULIP_CMD_TXRUN | TULIP_CMD_RXRUN);
  941. LMC_CSR_WRITE (sc, csr_command, sc->lmc_cmdmode);
  942. lmc_trace(dev, "lmc_runnin_reset_out");
  943. }
  944. /* This is what is called when you ifconfig down a device.
  945. * This disables the timer for the watchdog and keepalives,
  946. * and disables the irq for dev.
  947. */
  948. static int lmc_close(struct net_device *dev)
  949. {
  950. /* not calling release_region() as we should */
  951. lmc_softc_t *sc = dev_to_sc(dev);
  952. lmc_trace(dev, "lmc_close in");
  953. sc->lmc_ok = 0;
  954. sc->lmc_media->set_link_status (sc, 0);
  955. del_timer (&sc->timer);
  956. lmc_proto_close(sc);
  957. lmc_ifdown (dev);
  958. lmc_trace(dev, "lmc_close out");
  959. return 0;
  960. }
  961. /* Ends the transfer of packets */
  962. /* When the interface goes down, this is called */
  963. static int lmc_ifdown (struct net_device *dev) /*fold00*/
  964. {
  965. lmc_softc_t *sc = dev_to_sc(dev);
  966. u32 csr6;
  967. int i;
  968. lmc_trace(dev, "lmc_ifdown in");
  969. /* Don't let anything else go on right now */
  970. // dev->start = 0;
  971. netif_stop_queue(dev);
  972. sc->extra_stats.tx_tbusy1++;
  973. /* stop interrupts */
  974. /* Clear the interrupt mask */
  975. LMC_CSR_WRITE (sc, csr_intr, 0x00000000);
  976. /* Stop Tx and Rx on the chip */
  977. csr6 = LMC_CSR_READ (sc, csr_command);
  978. csr6 &= ~LMC_DEC_ST; /* Turn off the Transmission bit */
  979. csr6 &= ~LMC_DEC_SR; /* Turn off the Receive bit */
  980. LMC_CSR_WRITE (sc, csr_command, csr6);
  981. sc->lmc_device->stats.rx_missed_errors +=
  982. LMC_CSR_READ(sc, csr_missed_frames) & 0xffff;
  983. /* release the interrupt */
  984. if(sc->got_irq == 1){
  985. free_irq (dev->irq, dev);
  986. sc->got_irq = 0;
  987. }
  988. /* free skbuffs in the Rx queue */
  989. for (i = 0; i < LMC_RXDESCS; i++)
  990. {
  991. struct sk_buff *skb = sc->lmc_rxq[i];
  992. sc->lmc_rxq[i] = NULL;
  993. sc->lmc_rxring[i].status = 0;
  994. sc->lmc_rxring[i].length = 0;
  995. sc->lmc_rxring[i].buffer1 = 0xDEADBEEF;
  996. if (skb != NULL)
  997. dev_kfree_skb(skb);
  998. sc->lmc_rxq[i] = NULL;
  999. }
  1000. for (i = 0; i < LMC_TXDESCS; i++)
  1001. {
  1002. if (sc->lmc_txq[i] != NULL)
  1003. dev_kfree_skb(sc->lmc_txq[i]);
  1004. sc->lmc_txq[i] = NULL;
  1005. }
  1006. lmc_led_off (sc, LMC_MII16_LED_ALL);
  1007. netif_wake_queue(dev);
  1008. sc->extra_stats.tx_tbusy0++;
  1009. lmc_trace(dev, "lmc_ifdown out");
  1010. return 0;
  1011. }
  1012. /* Interrupt handling routine. This will take an incoming packet, or clean
  1013. * up after a trasmit.
  1014. */
  1015. static irqreturn_t lmc_interrupt (int irq, void *dev_instance) /*fold00*/
  1016. {
  1017. struct net_device *dev = (struct net_device *) dev_instance;
  1018. lmc_softc_t *sc = dev_to_sc(dev);
  1019. u32 csr;
  1020. int i;
  1021. s32 stat;
  1022. unsigned int badtx;
  1023. u32 firstcsr;
  1024. int max_work = LMC_RXDESCS;
  1025. int handled = 0;
  1026. lmc_trace(dev, "lmc_interrupt in");
  1027. spin_lock(&sc->lmc_lock);
  1028. /*
  1029. * Read the csr to find what interrupts we have (if any)
  1030. */
  1031. csr = LMC_CSR_READ (sc, csr_status);
  1032. /*
  1033. * Make sure this is our interrupt
  1034. */
  1035. if ( ! (csr & sc->lmc_intrmask)) {
  1036. goto lmc_int_fail_out;
  1037. }
  1038. firstcsr = csr;
  1039. /* always go through this loop at least once */
  1040. while (csr & sc->lmc_intrmask) {
  1041. handled = 1;
  1042. /*
  1043. * Clear interrupt bits, we handle all case below
  1044. */
  1045. LMC_CSR_WRITE (sc, csr_status, csr);
  1046. /*
  1047. * One of
  1048. * - Transmit process timed out CSR5<1>
  1049. * - Transmit jabber timeout CSR5<3>
  1050. * - Transmit underflow CSR5<5>
  1051. * - Transmit Receiver buffer unavailable CSR5<7>
  1052. * - Receive process stopped CSR5<8>
  1053. * - Receive watchdog timeout CSR5<9>
  1054. * - Early transmit interrupt CSR5<10>
  1055. *
  1056. * Is this really right? Should we do a running reset for jabber?
  1057. * (being a WAN card and all)
  1058. */
  1059. if (csr & TULIP_STS_ABNRMLINTR){
  1060. lmc_running_reset (dev);
  1061. break;
  1062. }
  1063. if (csr & TULIP_STS_RXINTR){
  1064. lmc_trace(dev, "rx interrupt");
  1065. lmc_rx (dev);
  1066. }
  1067. if (csr & (TULIP_STS_TXINTR | TULIP_STS_TXNOBUF | TULIP_STS_TXSTOPPED)) {
  1068. int n_compl = 0 ;
  1069. /* reset the transmit timeout detection flag -baz */
  1070. sc->extra_stats.tx_NoCompleteCnt = 0;
  1071. badtx = sc->lmc_taint_tx;
  1072. i = badtx % LMC_TXDESCS;
  1073. while ((badtx < sc->lmc_next_tx)) {
  1074. stat = sc->lmc_txring[i].status;
  1075. LMC_EVENT_LOG (LMC_EVENT_XMTINT, stat,
  1076. sc->lmc_txring[i].length);
  1077. /*
  1078. * If bit 31 is 1 the tulip owns it break out of the loop
  1079. */
  1080. if (stat & 0x80000000)
  1081. break;
  1082. n_compl++ ; /* i.e., have an empty slot in ring */
  1083. /*
  1084. * If we have no skbuff or have cleared it
  1085. * Already continue to the next buffer
  1086. */
  1087. if (sc->lmc_txq[i] == NULL)
  1088. continue;
  1089. /*
  1090. * Check the total error summary to look for any errors
  1091. */
  1092. if (stat & 0x8000) {
  1093. sc->lmc_device->stats.tx_errors++;
  1094. if (stat & 0x4104)
  1095. sc->lmc_device->stats.tx_aborted_errors++;
  1096. if (stat & 0x0C00)
  1097. sc->lmc_device->stats.tx_carrier_errors++;
  1098. if (stat & 0x0200)
  1099. sc->lmc_device->stats.tx_window_errors++;
  1100. if (stat & 0x0002)
  1101. sc->lmc_device->stats.tx_fifo_errors++;
  1102. } else {
  1103. sc->lmc_device->stats.tx_bytes += sc->lmc_txring[i].length & 0x7ff;
  1104. sc->lmc_device->stats.tx_packets++;
  1105. }
  1106. // dev_kfree_skb(sc->lmc_txq[i]);
  1107. dev_kfree_skb_irq(sc->lmc_txq[i]);
  1108. sc->lmc_txq[i] = NULL;
  1109. badtx++;
  1110. i = badtx % LMC_TXDESCS;
  1111. }
  1112. if (sc->lmc_next_tx - badtx > LMC_TXDESCS)
  1113. {
  1114. printk ("%s: out of sync pointer\n", dev->name);
  1115. badtx += LMC_TXDESCS;
  1116. }
  1117. LMC_EVENT_LOG(LMC_EVENT_TBUSY0, n_compl, 0);
  1118. sc->lmc_txfull = 0;
  1119. netif_wake_queue(dev);
  1120. sc->extra_stats.tx_tbusy0++;
  1121. #ifdef DEBUG
  1122. sc->extra_stats.dirtyTx = badtx;
  1123. sc->extra_stats.lmc_next_tx = sc->lmc_next_tx;
  1124. sc->extra_stats.lmc_txfull = sc->lmc_txfull;
  1125. #endif
  1126. sc->lmc_taint_tx = badtx;
  1127. /*
  1128. * Why was there a break here???
  1129. */
  1130. } /* end handle transmit interrupt */
  1131. if (csr & TULIP_STS_SYSERROR) {
  1132. u32 error;
  1133. printk (KERN_WARNING "%s: system bus error csr: %#8.8x\n", dev->name, csr);
  1134. error = csr>>23 & 0x7;
  1135. switch(error){
  1136. case 0x000:
  1137. printk(KERN_WARNING "%s: Parity Fault (bad)\n", dev->name);
  1138. break;
  1139. case 0x001:
  1140. printk(KERN_WARNING "%s: Master Abort (naughty)\n", dev->name);
  1141. break;
  1142. case 0x010:
  1143. printk(KERN_WARNING "%s: Target Abort (not so naughty)\n", dev->name);
  1144. break;
  1145. default:
  1146. printk(KERN_WARNING "%s: This bus error code was supposed to be reserved!\n", dev->name);
  1147. }
  1148. lmc_dec_reset (sc);
  1149. lmc_reset (sc);
  1150. LMC_EVENT_LOG(LMC_EVENT_RESET1, LMC_CSR_READ (sc, csr_status), 0);
  1151. LMC_EVENT_LOG(LMC_EVENT_RESET2,
  1152. lmc_mii_readreg (sc, 0, 16),
  1153. lmc_mii_readreg (sc, 0, 17));
  1154. }
  1155. if(max_work-- <= 0)
  1156. break;
  1157. /*
  1158. * Get current csr status to make sure
  1159. * we've cleared all interrupts
  1160. */
  1161. csr = LMC_CSR_READ (sc, csr_status);
  1162. } /* end interrupt loop */
  1163. LMC_EVENT_LOG(LMC_EVENT_INT, firstcsr, csr);
  1164. lmc_int_fail_out:
  1165. spin_unlock(&sc->lmc_lock);
  1166. lmc_trace(dev, "lmc_interrupt out");
  1167. return IRQ_RETVAL(handled);
  1168. }
  1169. static netdev_tx_t lmc_start_xmit(struct sk_buff *skb,
  1170. struct net_device *dev)
  1171. {
  1172. lmc_softc_t *sc = dev_to_sc(dev);
  1173. u32 flag;
  1174. int entry;
  1175. unsigned long flags;
  1176. lmc_trace(dev, "lmc_start_xmit in");
  1177. spin_lock_irqsave(&sc->lmc_lock, flags);
  1178. /* normal path, tbusy known to be zero */
  1179. entry = sc->lmc_next_tx % LMC_TXDESCS;
  1180. sc->lmc_txq[entry] = skb;
  1181. sc->lmc_txring[entry].buffer1 = virt_to_bus (skb->data);
  1182. LMC_CONSOLE_LOG("xmit", skb->data, skb->len);
  1183. #ifndef GCOM
  1184. /* If the queue is less than half full, don't interrupt */
  1185. if (sc->lmc_next_tx - sc->lmc_taint_tx < LMC_TXDESCS / 2)
  1186. {
  1187. /* Do not interrupt on completion of this packet */
  1188. flag = 0x60000000;
  1189. netif_wake_queue(dev);
  1190. }
  1191. else if (sc->lmc_next_tx - sc->lmc_taint_tx == LMC_TXDESCS / 2)
  1192. {
  1193. /* This generates an interrupt on completion of this packet */
  1194. flag = 0xe0000000;
  1195. netif_wake_queue(dev);
  1196. }
  1197. else if (sc->lmc_next_tx - sc->lmc_taint_tx < LMC_TXDESCS - 1)
  1198. {
  1199. /* Do not interrupt on completion of this packet */
  1200. flag = 0x60000000;
  1201. netif_wake_queue(dev);
  1202. }
  1203. else
  1204. {
  1205. /* This generates an interrupt on completion of this packet */
  1206. flag = 0xe0000000;
  1207. sc->lmc_txfull = 1;
  1208. netif_stop_queue(dev);
  1209. }
  1210. #else
  1211. flag = LMC_TDES_INTERRUPT_ON_COMPLETION;
  1212. if (sc->lmc_next_tx - sc->lmc_taint_tx >= LMC_TXDESCS - 1)
  1213. { /* ring full, go busy */
  1214. sc->lmc_txfull = 1;
  1215. netif_stop_queue(dev);
  1216. sc->extra_stats.tx_tbusy1++;
  1217. LMC_EVENT_LOG(LMC_EVENT_TBUSY1, entry, 0);
  1218. }
  1219. #endif
  1220. if (entry == LMC_TXDESCS - 1) /* last descriptor in ring */
  1221. flag |= LMC_TDES_END_OF_RING; /* flag as such for Tulip */
  1222. /* don't pad small packets either */
  1223. flag = sc->lmc_txring[entry].length = (skb->len) | flag |
  1224. sc->TxDescriptControlInit;
  1225. /* set the transmit timeout flag to be checked in
  1226. * the watchdog timer handler. -baz
  1227. */
  1228. sc->extra_stats.tx_NoCompleteCnt++;
  1229. sc->lmc_next_tx++;
  1230. /* give ownership to the chip */
  1231. LMC_EVENT_LOG(LMC_EVENT_XMT, flag, entry);
  1232. sc->lmc_txring[entry].status = 0x80000000;
  1233. /* send now! */
  1234. LMC_CSR_WRITE (sc, csr_txpoll, 0);
  1235. spin_unlock_irqrestore(&sc->lmc_lock, flags);
  1236. lmc_trace(dev, "lmc_start_xmit_out");
  1237. return NETDEV_TX_OK;
  1238. }
  1239. static int lmc_rx(struct net_device *dev)
  1240. {
  1241. lmc_softc_t *sc = dev_to_sc(dev);
  1242. int i;
  1243. int rx_work_limit = LMC_RXDESCS;
  1244. unsigned int next_rx;
  1245. int rxIntLoopCnt; /* debug -baz */
  1246. int localLengthErrCnt = 0;
  1247. long stat;
  1248. struct sk_buff *skb, *nsb;
  1249. u16 len;
  1250. lmc_trace(dev, "lmc_rx in");
  1251. lmc_led_on(sc, LMC_DS3_LED3);
  1252. rxIntLoopCnt = 0; /* debug -baz */
  1253. i = sc->lmc_next_rx % LMC_RXDESCS;
  1254. next_rx = sc->lmc_next_rx;
  1255. while (((stat = sc->lmc_rxring[i].status) & LMC_RDES_OWN_BIT) != DESC_OWNED_BY_DC21X4)
  1256. {
  1257. rxIntLoopCnt++; /* debug -baz */
  1258. len = ((stat & LMC_RDES_FRAME_LENGTH) >> RDES_FRAME_LENGTH_BIT_NUMBER);
  1259. if ((stat & 0x0300) != 0x0300) { /* Check first segment and last segment */
  1260. if ((stat & 0x0000ffff) != 0x7fff) {
  1261. /* Oversized frame */
  1262. sc->lmc_device->stats.rx_length_errors++;
  1263. goto skip_packet;
  1264. }
  1265. }
  1266. if (stat & 0x00000008) { /* Catch a dribbling bit error */
  1267. sc->lmc_device->stats.rx_errors++;
  1268. sc->lmc_device->stats.rx_frame_errors++;
  1269. goto skip_packet;
  1270. }
  1271. if (stat & 0x00000004) { /* Catch a CRC error by the Xilinx */
  1272. sc->lmc_device->stats.rx_errors++;
  1273. sc->lmc_device->stats.rx_crc_errors++;
  1274. goto skip_packet;
  1275. }
  1276. if (len > LMC_PKT_BUF_SZ) {
  1277. sc->lmc_device->stats.rx_length_errors++;
  1278. localLengthErrCnt++;
  1279. goto skip_packet;
  1280. }
  1281. if (len < sc->lmc_crcSize + 2) {
  1282. sc->lmc_device->stats.rx_length_errors++;
  1283. sc->extra_stats.rx_SmallPktCnt++;
  1284. localLengthErrCnt++;
  1285. goto skip_packet;
  1286. }
  1287. if(stat & 0x00004000){
  1288. printk(KERN_WARNING "%s: Receiver descriptor error, receiver out of sync?\n", dev->name);
  1289. }
  1290. len -= sc->lmc_crcSize;
  1291. skb = sc->lmc_rxq[i];
  1292. /*
  1293. * We ran out of memory at some point
  1294. * just allocate an skb buff and continue.
  1295. */
  1296. if (!skb) {
  1297. nsb = dev_alloc_skb (LMC_PKT_BUF_SZ + 2);
  1298. if (nsb) {
  1299. sc->lmc_rxq[i] = nsb;
  1300. nsb->dev = dev;
  1301. sc->lmc_rxring[i].buffer1 = virt_to_bus(skb_tail_pointer(nsb));
  1302. }
  1303. sc->failed_recv_alloc = 1;
  1304. goto skip_packet;
  1305. }
  1306. sc->lmc_device->stats.rx_packets++;
  1307. sc->lmc_device->stats.rx_bytes += len;
  1308. LMC_CONSOLE_LOG("recv", skb->data, len);
  1309. /*
  1310. * I'm not sure of the sanity of this
  1311. * Packets could be arriving at a constant
  1312. * 44.210mbits/sec and we're going to copy
  1313. * them into a new buffer??
  1314. */
  1315. if(len > (LMC_MTU - (LMC_MTU>>2))){ /* len > LMC_MTU * 0.75 */
  1316. /*
  1317. * If it's a large packet don't copy it just hand it up
  1318. */
  1319. give_it_anyways:
  1320. sc->lmc_rxq[i] = NULL;
  1321. sc->lmc_rxring[i].buffer1 = 0x0;
  1322. skb_put (skb, len);
  1323. skb->protocol = lmc_proto_type(sc, skb);
  1324. skb_reset_mac_header(skb);
  1325. /* skb_reset_network_header(skb); */
  1326. skb->dev = dev;
  1327. lmc_proto_netif(sc, skb);
  1328. /*
  1329. * This skb will be destroyed by the upper layers, make a new one
  1330. */
  1331. nsb = dev_alloc_skb (LMC_PKT_BUF_SZ + 2);
  1332. if (nsb) {
  1333. sc->lmc_rxq[i] = nsb;
  1334. nsb->dev = dev;
  1335. sc->lmc_rxring[i].buffer1 = virt_to_bus(skb_tail_pointer(nsb));
  1336. /* Transferred to 21140 below */
  1337. }
  1338. else {
  1339. /*
  1340. * We've run out of memory, stop trying to allocate
  1341. * memory and exit the interrupt handler
  1342. *
  1343. * The chip may run out of receivers and stop
  1344. * in which care we'll try to allocate the buffer
  1345. * again. (once a second)
  1346. */
  1347. sc->extra_stats.rx_BuffAllocErr++;
  1348. LMC_EVENT_LOG(LMC_EVENT_RCVINT, stat, len);
  1349. sc->failed_recv_alloc = 1;
  1350. goto skip_out_of_mem;
  1351. }
  1352. }
  1353. else {
  1354. nsb = dev_alloc_skb(len);
  1355. if(!nsb) {
  1356. goto give_it_anyways;
  1357. }
  1358. skb_copy_from_linear_data(skb, skb_put(nsb, len), len);
  1359. nsb->protocol = lmc_proto_type(sc, nsb);
  1360. skb_reset_mac_header(nsb);
  1361. /* skb_reset_network_header(nsb); */
  1362. nsb->dev = dev;
  1363. lmc_proto_netif(sc, nsb);
  1364. }
  1365. skip_packet:
  1366. LMC_EVENT_LOG(LMC_EVENT_RCVINT, stat, len);
  1367. sc->lmc_rxring[i].status = DESC_OWNED_BY_DC21X4;
  1368. sc->lmc_next_rx++;
  1369. i = sc->lmc_next_rx % LMC_RXDESCS;
  1370. rx_work_limit--;
  1371. if (rx_work_limit < 0)
  1372. break;
  1373. }
  1374. /* detect condition for LMC1000 where DSU cable attaches and fills
  1375. * descriptors with bogus packets
  1376. *
  1377. if (localLengthErrCnt > LMC_RXDESCS - 3) {
  1378. sc->extra_stats.rx_BadPktSurgeCnt++;
  1379. LMC_EVENT_LOG(LMC_EVENT_BADPKTSURGE, localLengthErrCnt,
  1380. sc->extra_stats.rx_BadPktSurgeCnt);
  1381. } */
  1382. /* save max count of receive descriptors serviced */
  1383. if (rxIntLoopCnt > sc->extra_stats.rxIntLoopCnt)
  1384. sc->extra_stats.rxIntLoopCnt = rxIntLoopCnt; /* debug -baz */
  1385. #ifdef DEBUG
  1386. if (rxIntLoopCnt == 0)
  1387. {
  1388. for (i = 0; i < LMC_RXDESCS; i++)
  1389. {
  1390. if ((sc->lmc_rxring[i].status & LMC_RDES_OWN_BIT)
  1391. != DESC_OWNED_BY_DC21X4)
  1392. {
  1393. rxIntLoopCnt++;
  1394. }
  1395. }
  1396. LMC_EVENT_LOG(LMC_EVENT_RCVEND, rxIntLoopCnt, 0);
  1397. }
  1398. #endif
  1399. lmc_led_off(sc, LMC_DS3_LED3);
  1400. skip_out_of_mem:
  1401. lmc_trace(dev, "lmc_rx out");
  1402. return 0;
  1403. }
  1404. static struct net_device_stats *lmc_get_stats(struct net_device *dev)
  1405. {
  1406. lmc_softc_t *sc = dev_to_sc(dev);
  1407. unsigned long flags;
  1408. lmc_trace(dev, "lmc_get_stats in");
  1409. spin_lock_irqsave(&sc->lmc_lock, flags);
  1410. sc->lmc_device->stats.rx_missed_errors += LMC_CSR_READ(sc, csr_missed_frames) & 0xffff;
  1411. spin_unlock_irqrestore(&sc->lmc_lock, flags);
  1412. lmc_trace(dev, "lmc_get_stats out");
  1413. return &sc->lmc_device->stats;
  1414. }
  1415. static struct pci_driver lmc_driver = {
  1416. .name = "lmc",
  1417. .id_table = lmc_pci_tbl,
  1418. .probe = lmc_init_one,
  1419. .remove = __devexit_p(lmc_remove_one),
  1420. };
  1421. module_pci_driver(lmc_driver);
  1422. unsigned lmc_mii_readreg (lmc_softc_t * const sc, unsigned devaddr, unsigned regno) /*fold00*/
  1423. {
  1424. int i;
  1425. int command = (0xf6 << 10) | (devaddr << 5) | regno;
  1426. int retval = 0;
  1427. lmc_trace(sc->lmc_device, "lmc_mii_readreg in");
  1428. LMC_MII_SYNC (sc);
  1429. lmc_trace(sc->lmc_device, "lmc_mii_readreg: done sync");
  1430. for (i = 15; i >= 0; i--)
  1431. {
  1432. int dataval = (command & (1 << i)) ? 0x20000 : 0;
  1433. LMC_CSR_WRITE (sc, csr_9, dataval);
  1434. lmc_delay ();
  1435. /* __SLOW_DOWN_IO; */
  1436. LMC_CSR_WRITE (sc, csr_9, dataval | 0x10000);
  1437. lmc_delay ();
  1438. /* __SLOW_DOWN_IO; */
  1439. }
  1440. lmc_trace(sc->lmc_device, "lmc_mii_readreg: done1");
  1441. for (i = 19; i > 0; i--)
  1442. {
  1443. LMC_CSR_WRITE (sc, csr_9, 0x40000);
  1444. lmc_delay ();
  1445. /* __SLOW_DOWN_IO; */
  1446. retval = (retval << 1) | ((LMC_CSR_READ (sc, csr_9) & 0x80000) ? 1 : 0);
  1447. LMC_CSR_WRITE (sc, csr_9, 0x40000 | 0x10000);
  1448. lmc_delay ();
  1449. /* __SLOW_DOWN_IO; */
  1450. }
  1451. lmc_trace(sc->lmc_device, "lmc_mii_readreg out");
  1452. return (retval >> 1) & 0xffff;
  1453. }
  1454. void lmc_mii_writereg (lmc_softc_t * const sc, unsigned devaddr, unsigned regno, unsigned data) /*fold00*/
  1455. {
  1456. int i = 32;
  1457. int command = (0x5002 << 16) | (devaddr << 23) | (regno << 18) | data;
  1458. lmc_trace(sc->lmc_device, "lmc_mii_writereg in");
  1459. LMC_MII_SYNC (sc);
  1460. i = 31;
  1461. while (i >= 0)
  1462. {
  1463. int datav;
  1464. if (command & (1 << i))
  1465. datav = 0x20000;
  1466. else
  1467. datav = 0x00000;
  1468. LMC_CSR_WRITE (sc, csr_9, datav);
  1469. lmc_delay ();
  1470. /* __SLOW_DOWN_IO; */
  1471. LMC_CSR_WRITE (sc, csr_9, (datav | 0x10000));
  1472. lmc_delay ();
  1473. /* __SLOW_DOWN_IO; */
  1474. i--;
  1475. }
  1476. i = 2;
  1477. while (i > 0)
  1478. {
  1479. LMC_CSR_WRITE (sc, csr_9, 0x40000);
  1480. lmc_delay ();
  1481. /* __SLOW_DOWN_IO; */
  1482. LMC_CSR_WRITE (sc, csr_9, 0x50000);
  1483. lmc_delay ();
  1484. /* __SLOW_DOWN_IO; */
  1485. i--;
  1486. }
  1487. lmc_trace(sc->lmc_device, "lmc_mii_writereg out");
  1488. }
  1489. static void lmc_softreset (lmc_softc_t * const sc) /*fold00*/
  1490. {
  1491. int i;
  1492. lmc_trace(sc->lmc_device, "lmc_softreset in");
  1493. /* Initialize the receive rings and buffers. */
  1494. sc->lmc_txfull = 0;
  1495. sc->lmc_next_rx = 0;
  1496. sc->lmc_next_tx = 0;
  1497. sc->lmc_taint_rx = 0;
  1498. sc->lmc_taint_tx = 0;
  1499. /*
  1500. * Setup each one of the receiver buffers
  1501. * allocate an skbuff for each one, setup the descriptor table
  1502. * and point each buffer at the next one
  1503. */
  1504. for (i = 0; i < LMC_RXDESCS; i++)
  1505. {
  1506. struct sk_buff *skb;
  1507. if (sc->lmc_rxq[i] == NULL)
  1508. {
  1509. skb = dev_alloc_skb (LMC_PKT_BUF_SZ + 2);
  1510. if(skb == NULL){
  1511. printk(KERN_WARNING "%s: Failed to allocate receiver ring, will try again\n", sc->name);
  1512. sc->failed_ring = 1;
  1513. break;
  1514. }
  1515. else{
  1516. sc->lmc_rxq[i] = skb;
  1517. }
  1518. }
  1519. else
  1520. {
  1521. skb = sc->lmc_rxq[i];
  1522. }
  1523. skb->dev = sc->lmc_device;
  1524. /* owned by 21140 */
  1525. sc->lmc_rxring[i].status = 0x80000000;
  1526. /* used to be PKT_BUF_SZ now uses skb since we lose some to head room */
  1527. sc->lmc_rxring[i].length = skb_tailroom(skb);
  1528. /* use to be tail which is dumb since you're thinking why write
  1529. * to the end of the packj,et but since there's nothing there tail == data
  1530. */
  1531. sc->lmc_rxring[i].buffer1 = virt_to_bus (skb->data);
  1532. /* This is fair since the structure is static and we have the next address */
  1533. sc->lmc_rxring[i].buffer2 = virt_to_bus (&sc->lmc_rxring[i + 1]);
  1534. }
  1535. /*
  1536. * Sets end of ring
  1537. */
  1538. if (i != 0) {
  1539. sc->lmc_rxring[i - 1].length |= 0x02000000; /* Set end of buffers flag */
  1540. sc->lmc_rxring[i - 1].buffer2 = virt_to_bus(&sc->lmc_rxring[0]); /* Point back to the start */
  1541. }
  1542. LMC_CSR_WRITE (sc, csr_rxlist, virt_to_bus (sc->lmc_rxring)); /* write base address */
  1543. /* Initialize the transmit rings and buffers */
  1544. for (i = 0; i < LMC_TXDESCS; i++)
  1545. {
  1546. if (sc->lmc_txq[i] != NULL){ /* have buffer */
  1547. dev_kfree_skb(sc->lmc_txq[i]); /* free it */
  1548. sc->lmc_device->stats.tx_dropped++; /* We just dropped a packet */
  1549. }
  1550. sc->lmc_txq[i] = NULL;
  1551. sc->lmc_txring[i].status = 0x00000000;
  1552. sc->lmc_txring[i].buffer2 = virt_to_bus (&sc->lmc_txring[i + 1]);
  1553. }
  1554. sc->lmc_txring[i - 1].buffer2 = virt_to_bus (&sc->lmc_txring[0]);
  1555. LMC_CSR_WRITE (sc, csr_txlist, virt_to_bus (sc->lmc_txring));
  1556. lmc_trace(sc->lmc_device, "lmc_softreset out");
  1557. }
  1558. void lmc_gpio_mkinput(lmc_softc_t * const sc, u32 bits) /*fold00*/
  1559. {
  1560. lmc_trace(sc->lmc_device, "lmc_gpio_mkinput in");
  1561. sc->lmc_gpio_io &= ~bits;
  1562. LMC_CSR_WRITE(sc, csr_gp, TULIP_GP_PINSET | (sc->lmc_gpio_io));
  1563. lmc_trace(sc->lmc_device, "lmc_gpio_mkinput out");
  1564. }
  1565. void lmc_gpio_mkoutput(lmc_softc_t * const sc, u32 bits) /*fold00*/
  1566. {
  1567. lmc_trace(sc->lmc_device, "lmc_gpio_mkoutput in");
  1568. sc->lmc_gpio_io |= bits;
  1569. LMC_CSR_WRITE(sc, csr_gp, TULIP_GP_PINSET | (sc->lmc_gpio_io));
  1570. lmc_trace(sc->lmc_device, "lmc_gpio_mkoutput out");
  1571. }
  1572. void lmc_led_on(lmc_softc_t * const sc, u32 led) /*fold00*/
  1573. {
  1574. lmc_trace(sc->lmc_device, "lmc_led_on in");
  1575. if((~sc->lmc_miireg16) & led){ /* Already on! */
  1576. lmc_trace(sc->lmc_device, "lmc_led_on aon out");
  1577. return;
  1578. }
  1579. sc->lmc_miireg16 &= ~led;
  1580. lmc_mii_writereg(sc, 0, 16, sc->lmc_miireg16);
  1581. lmc_trace(sc->lmc_device, "lmc_led_on out");
  1582. }
  1583. void lmc_led_off(lmc_softc_t * const sc, u32 led) /*fold00*/
  1584. {
  1585. lmc_trace(sc->lmc_device, "lmc_led_off in");
  1586. if(sc->lmc_miireg16 & led){ /* Already set don't do anything */
  1587. lmc_trace(sc->lmc_device, "lmc_led_off aoff out");
  1588. return;
  1589. }
  1590. sc->lmc_miireg16 |= led;
  1591. lmc_mii_writereg(sc, 0, 16, sc->lmc_miireg16);
  1592. lmc_trace(sc->lmc_device, "lmc_led_off out");
  1593. }
  1594. static void lmc_reset(lmc_softc_t * const sc) /*fold00*/
  1595. {
  1596. lmc_trace(sc->lmc_device, "lmc_reset in");
  1597. sc->lmc_miireg16 |= LMC_MII16_FIFO_RESET;
  1598. lmc_mii_writereg(sc, 0, 16, sc->lmc_miireg16);
  1599. sc->lmc_miireg16 &= ~LMC_MII16_FIFO_RESET;
  1600. lmc_mii_writereg(sc, 0, 16, sc->lmc_miireg16);
  1601. /*
  1602. * make some of the GPIO pins be outputs
  1603. */
  1604. lmc_gpio_mkoutput(sc, LMC_GEP_RESET);
  1605. /*
  1606. * RESET low to force state reset. This also forces
  1607. * the transmitter clock to be internal, but we expect to reset
  1608. * that later anyway.
  1609. */
  1610. sc->lmc_gpio &= ~(LMC_GEP_RESET);
  1611. LMC_CSR_WRITE(sc, csr_gp, sc->lmc_gpio);
  1612. /*
  1613. * hold for more than 10 microseconds
  1614. */
  1615. udelay(50);
  1616. /*
  1617. * stop driving Xilinx-related signals
  1618. */
  1619. lmc_gpio_mkinput(sc, LMC_GEP_RESET);
  1620. /*
  1621. * Call media specific init routine
  1622. */
  1623. sc->lmc_media->init(sc);
  1624. sc->extra_stats.resetCount++;
  1625. lmc_trace(sc->lmc_device, "lmc_reset out");
  1626. }
  1627. static void lmc_dec_reset(lmc_softc_t * const sc) /*fold00*/
  1628. {
  1629. u32 val;
  1630. lmc_trace(sc->lmc_device, "lmc_dec_reset in");
  1631. /*
  1632. * disable all interrupts
  1633. */
  1634. sc->lmc_intrmask = 0;
  1635. LMC_CSR_WRITE(sc, csr_intr, sc->lmc_intrmask);
  1636. /*
  1637. * Reset the chip with a software reset command.
  1638. * Wait 10 microseconds (actually 50 PCI cycles but at
  1639. * 33MHz that comes to two microseconds but wait a
  1640. * bit longer anyways)
  1641. */
  1642. LMC_CSR_WRITE(sc, csr_busmode, TULIP_BUSMODE_SWRESET);
  1643. udelay(25);
  1644. #ifdef __sparc__
  1645. sc->lmc_busmode = LMC_CSR_READ(sc, csr_busmode);
  1646. sc->lmc_busmode = 0x00100000;
  1647. sc->lmc_busmode &= ~TULIP_BUSMODE_SWRESET;
  1648. LMC_CSR_WRITE(sc, csr_busmode, sc->lmc_busmode);
  1649. #endif
  1650. sc->lmc_cmdmode = LMC_CSR_READ(sc, csr_command);
  1651. /*
  1652. * We want:
  1653. * no ethernet address in frames we write
  1654. * disable padding (txdesc, padding disable)
  1655. * ignore runt frames (rdes0 bit 15)
  1656. * no receiver watchdog or transmitter jabber timer
  1657. * (csr15 bit 0,14 == 1)
  1658. * if using 16-bit CRC, turn off CRC (trans desc, crc disable)
  1659. */
  1660. sc->lmc_cmdmode |= ( TULIP_CMD_PROMISCUOUS
  1661. | TULIP_CMD_FULLDUPLEX
  1662. | TULIP_CMD_PASSBADPKT
  1663. | TULIP_CMD_NOHEARTBEAT
  1664. | TULIP_CMD_PORTSELECT
  1665. | TULIP_CMD_RECEIVEALL
  1666. | TULIP_CMD_MUSTBEONE
  1667. );
  1668. sc->lmc_cmdmode &= ~( TULIP_CMD_OPERMODE
  1669. | TULIP_CMD_THRESHOLDCTL
  1670. | TULIP_CMD_STOREFWD
  1671. | TULIP_CMD_TXTHRSHLDCTL
  1672. );
  1673. LMC_CSR_WRITE(sc, csr_command, sc->lmc_cmdmode);
  1674. /*
  1675. * disable receiver watchdog and transmit jabber
  1676. */
  1677. val = LMC_CSR_READ(sc, csr_sia_general);
  1678. val |= (TULIP_WATCHDOG_TXDISABLE | TULIP_WATCHDOG_RXDISABLE);
  1679. LMC_CSR_WRITE(sc, csr_sia_general, val);
  1680. lmc_trace(sc->lmc_device, "lmc_dec_reset out");
  1681. }
  1682. static void lmc_initcsrs(lmc_softc_t * const sc, lmc_csrptr_t csr_base, /*fold00*/
  1683. size_t csr_size)
  1684. {
  1685. lmc_trace(sc->lmc_device, "lmc_initcsrs in");
  1686. sc->lmc_csrs.csr_busmode = csr_base + 0 * csr_size;
  1687. sc->lmc_csrs.csr_txpoll = csr_base + 1 * csr_size;
  1688. sc->lmc_csrs.csr_rxpoll = csr_base + 2 * csr_size;
  1689. sc->lmc_csrs.csr_rxlist = csr_base + 3 * csr_size;
  1690. sc->lmc_csrs.csr_txlist = csr_base + 4 * csr_size;
  1691. sc->lmc_csrs.csr_status = csr_base + 5 * csr_size;
  1692. sc->lmc_csrs.csr_command = csr_base + 6 * csr_size;
  1693. sc->lmc_csrs.csr_intr = csr_base + 7 * csr_size;
  1694. sc->lmc_csrs.csr_missed_frames = csr_base + 8 * csr_size;
  1695. sc->lmc_csrs.csr_9 = csr_base + 9 * csr_size;
  1696. sc->lmc_csrs.csr_10 = csr_base + 10 * csr_size;
  1697. sc->lmc_csrs.csr_11 = csr_base + 11 * csr_size;
  1698. sc->lmc_csrs.csr_12 = csr_base + 12 * csr_size;
  1699. sc->lmc_csrs.csr_13 = csr_base + 13 * csr_size;
  1700. sc->lmc_csrs.csr_14 = csr_base + 14 * csr_size;
  1701. sc->lmc_csrs.csr_15 = csr_base + 15 * csr_size;
  1702. lmc_trace(sc->lmc_device, "lmc_initcsrs out");
  1703. }
  1704. static void lmc_driver_timeout(struct net_device *dev)
  1705. {
  1706. lmc_softc_t *sc = dev_to_sc(dev);
  1707. u32 csr6;
  1708. unsigned long flags;
  1709. lmc_trace(dev, "lmc_driver_timeout in");
  1710. spin_lock_irqsave(&sc->lmc_lock, flags);
  1711. printk("%s: Xmitter busy|\n", dev->name);
  1712. sc->extra_stats.tx_tbusy_calls++;
  1713. if (jiffies - dev_trans_start(dev) < TX_TIMEOUT)
  1714. goto bug_out;
  1715. /*
  1716. * Chip seems to have locked up
  1717. * Reset it
  1718. * This whips out all our decriptor
  1719. * table and starts from scartch
  1720. */
  1721. LMC_EVENT_LOG(LMC_EVENT_XMTPRCTMO,
  1722. LMC_CSR_READ (sc, csr_status),
  1723. sc->extra_stats.tx_ProcTimeout);
  1724. lmc_running_reset (dev);
  1725. LMC_EVENT_LOG(LMC_EVENT_RESET1, LMC_CSR_READ (sc, csr_status), 0);
  1726. LMC_EVENT_LOG(LMC_EVENT_RESET2,
  1727. lmc_mii_readreg (sc, 0, 16),
  1728. lmc_mii_readreg (sc, 0, 17));
  1729. /* restart the tx processes */
  1730. csr6 = LMC_CSR_READ (sc, csr_command);
  1731. LMC_CSR_WRITE (sc, csr_command, csr6 | 0x0002);
  1732. LMC_CSR_WRITE (sc, csr_command, csr6 | 0x2002);
  1733. /* immediate transmit */
  1734. LMC_CSR_WRITE (sc, csr_txpoll, 0);
  1735. sc->lmc_device->stats.tx_errors++;
  1736. sc->extra_stats.tx_ProcTimeout++; /* -baz */
  1737. dev->trans_start = jiffies; /* prevent tx timeout */
  1738. bug_out:
  1739. spin_unlock_irqrestore(&sc->lmc_lock, flags);
  1740. lmc_trace(dev, "lmc_driver_timout out");
  1741. }