resource_tracker.c 71 KB

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  1. /*
  2. * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
  3. * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies.
  4. * All rights reserved.
  5. * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
  6. *
  7. * This software is available to you under a choice of one of two
  8. * licenses. You may choose to be licensed under the terms of the GNU
  9. * General Public License (GPL) Version 2, available from the file
  10. * COPYING in the main directory of this source tree, or the
  11. * OpenIB.org BSD license below:
  12. *
  13. * Redistribution and use in source and binary forms, with or
  14. * without modification, are permitted provided that the following
  15. * conditions are met:
  16. *
  17. * - Redistributions of source code must retain the above
  18. * copyright notice, this list of conditions and the following
  19. * disclaimer.
  20. *
  21. * - Redistributions in binary form must reproduce the above
  22. * copyright notice, this list of conditions and the following
  23. * disclaimer in the documentation and/or other materials
  24. * provided with the distribution.
  25. *
  26. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  27. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  28. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  29. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  30. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  31. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  32. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  33. * SOFTWARE.
  34. */
  35. #include <linux/sched.h>
  36. #include <linux/pci.h>
  37. #include <linux/errno.h>
  38. #include <linux/kernel.h>
  39. #include <linux/io.h>
  40. #include <linux/slab.h>
  41. #include <linux/mlx4/cmd.h>
  42. #include <linux/mlx4/qp.h>
  43. #include "mlx4.h"
  44. #include "fw.h"
  45. #define MLX4_MAC_VALID (1ull << 63)
  46. #define MLX4_MAC_MASK 0x7fffffffffffffffULL
  47. #define ETH_ALEN 6
  48. struct mac_res {
  49. struct list_head list;
  50. u64 mac;
  51. u8 port;
  52. };
  53. struct res_common {
  54. struct list_head list;
  55. u32 res_id;
  56. int owner;
  57. int state;
  58. int from_state;
  59. int to_state;
  60. int removing;
  61. };
  62. enum {
  63. RES_ANY_BUSY = 1
  64. };
  65. struct res_gid {
  66. struct list_head list;
  67. u8 gid[16];
  68. enum mlx4_protocol prot;
  69. enum mlx4_steer_type steer;
  70. };
  71. enum res_qp_states {
  72. RES_QP_BUSY = RES_ANY_BUSY,
  73. /* QP number was allocated */
  74. RES_QP_RESERVED,
  75. /* ICM memory for QP context was mapped */
  76. RES_QP_MAPPED,
  77. /* QP is in hw ownership */
  78. RES_QP_HW
  79. };
  80. struct res_qp {
  81. struct res_common com;
  82. struct res_mtt *mtt;
  83. struct res_cq *rcq;
  84. struct res_cq *scq;
  85. struct res_srq *srq;
  86. struct list_head mcg_list;
  87. spinlock_t mcg_spl;
  88. int local_qpn;
  89. };
  90. enum res_mtt_states {
  91. RES_MTT_BUSY = RES_ANY_BUSY,
  92. RES_MTT_ALLOCATED,
  93. };
  94. static inline const char *mtt_states_str(enum res_mtt_states state)
  95. {
  96. switch (state) {
  97. case RES_MTT_BUSY: return "RES_MTT_BUSY";
  98. case RES_MTT_ALLOCATED: return "RES_MTT_ALLOCATED";
  99. default: return "Unknown";
  100. }
  101. }
  102. struct res_mtt {
  103. struct res_common com;
  104. int order;
  105. atomic_t ref_count;
  106. };
  107. enum res_mpt_states {
  108. RES_MPT_BUSY = RES_ANY_BUSY,
  109. RES_MPT_RESERVED,
  110. RES_MPT_MAPPED,
  111. RES_MPT_HW,
  112. };
  113. struct res_mpt {
  114. struct res_common com;
  115. struct res_mtt *mtt;
  116. int key;
  117. };
  118. enum res_eq_states {
  119. RES_EQ_BUSY = RES_ANY_BUSY,
  120. RES_EQ_RESERVED,
  121. RES_EQ_HW,
  122. };
  123. struct res_eq {
  124. struct res_common com;
  125. struct res_mtt *mtt;
  126. };
  127. enum res_cq_states {
  128. RES_CQ_BUSY = RES_ANY_BUSY,
  129. RES_CQ_ALLOCATED,
  130. RES_CQ_HW,
  131. };
  132. struct res_cq {
  133. struct res_common com;
  134. struct res_mtt *mtt;
  135. atomic_t ref_count;
  136. };
  137. enum res_srq_states {
  138. RES_SRQ_BUSY = RES_ANY_BUSY,
  139. RES_SRQ_ALLOCATED,
  140. RES_SRQ_HW,
  141. };
  142. struct res_srq {
  143. struct res_common com;
  144. struct res_mtt *mtt;
  145. struct res_cq *cq;
  146. atomic_t ref_count;
  147. };
  148. enum res_counter_states {
  149. RES_COUNTER_BUSY = RES_ANY_BUSY,
  150. RES_COUNTER_ALLOCATED,
  151. };
  152. struct res_counter {
  153. struct res_common com;
  154. int port;
  155. };
  156. enum res_xrcdn_states {
  157. RES_XRCD_BUSY = RES_ANY_BUSY,
  158. RES_XRCD_ALLOCATED,
  159. };
  160. struct res_xrcdn {
  161. struct res_common com;
  162. int port;
  163. };
  164. /* For Debug uses */
  165. static const char *ResourceType(enum mlx4_resource rt)
  166. {
  167. switch (rt) {
  168. case RES_QP: return "RES_QP";
  169. case RES_CQ: return "RES_CQ";
  170. case RES_SRQ: return "RES_SRQ";
  171. case RES_MPT: return "RES_MPT";
  172. case RES_MTT: return "RES_MTT";
  173. case RES_MAC: return "RES_MAC";
  174. case RES_EQ: return "RES_EQ";
  175. case RES_COUNTER: return "RES_COUNTER";
  176. case RES_XRCD: return "RES_XRCD";
  177. default: return "Unknown resource type !!!";
  178. };
  179. }
  180. int mlx4_init_resource_tracker(struct mlx4_dev *dev)
  181. {
  182. struct mlx4_priv *priv = mlx4_priv(dev);
  183. int i;
  184. int t;
  185. priv->mfunc.master.res_tracker.slave_list =
  186. kzalloc(dev->num_slaves * sizeof(struct slave_list),
  187. GFP_KERNEL);
  188. if (!priv->mfunc.master.res_tracker.slave_list)
  189. return -ENOMEM;
  190. for (i = 0 ; i < dev->num_slaves; i++) {
  191. for (t = 0; t < MLX4_NUM_OF_RESOURCE_TYPE; ++t)
  192. INIT_LIST_HEAD(&priv->mfunc.master.res_tracker.
  193. slave_list[i].res_list[t]);
  194. mutex_init(&priv->mfunc.master.res_tracker.slave_list[i].mutex);
  195. }
  196. mlx4_dbg(dev, "Started init_resource_tracker: %ld slaves\n",
  197. dev->num_slaves);
  198. for (i = 0 ; i < MLX4_NUM_OF_RESOURCE_TYPE; i++)
  199. INIT_RADIX_TREE(&priv->mfunc.master.res_tracker.res_tree[i],
  200. GFP_ATOMIC|__GFP_NOWARN);
  201. spin_lock_init(&priv->mfunc.master.res_tracker.lock);
  202. return 0 ;
  203. }
  204. void mlx4_free_resource_tracker(struct mlx4_dev *dev,
  205. enum mlx4_res_tracker_free_type type)
  206. {
  207. struct mlx4_priv *priv = mlx4_priv(dev);
  208. int i;
  209. if (priv->mfunc.master.res_tracker.slave_list) {
  210. if (type != RES_TR_FREE_STRUCTS_ONLY)
  211. for (i = 0 ; i < dev->num_slaves; i++)
  212. if (type == RES_TR_FREE_ALL ||
  213. dev->caps.function != i)
  214. mlx4_delete_all_resources_for_slave(dev, i);
  215. if (type != RES_TR_FREE_SLAVES_ONLY) {
  216. kfree(priv->mfunc.master.res_tracker.slave_list);
  217. priv->mfunc.master.res_tracker.slave_list = NULL;
  218. }
  219. }
  220. }
  221. static void update_ud_gid(struct mlx4_dev *dev,
  222. struct mlx4_qp_context *qp_ctx, u8 slave)
  223. {
  224. u32 ts = (be32_to_cpu(qp_ctx->flags) >> 16) & 0xff;
  225. if (MLX4_QP_ST_UD == ts)
  226. qp_ctx->pri_path.mgid_index = 0x80 | slave;
  227. mlx4_dbg(dev, "slave %d, new gid index: 0x%x ",
  228. slave, qp_ctx->pri_path.mgid_index);
  229. }
  230. static int mpt_mask(struct mlx4_dev *dev)
  231. {
  232. return dev->caps.num_mpts - 1;
  233. }
  234. static void *find_res(struct mlx4_dev *dev, int res_id,
  235. enum mlx4_resource type)
  236. {
  237. struct mlx4_priv *priv = mlx4_priv(dev);
  238. return radix_tree_lookup(&priv->mfunc.master.res_tracker.res_tree[type],
  239. res_id);
  240. }
  241. static int get_res(struct mlx4_dev *dev, int slave, int res_id,
  242. enum mlx4_resource type,
  243. void *res)
  244. {
  245. struct res_common *r;
  246. int err = 0;
  247. spin_lock_irq(mlx4_tlock(dev));
  248. r = find_res(dev, res_id, type);
  249. if (!r) {
  250. err = -ENONET;
  251. goto exit;
  252. }
  253. if (r->state == RES_ANY_BUSY) {
  254. err = -EBUSY;
  255. goto exit;
  256. }
  257. if (r->owner != slave) {
  258. err = -EPERM;
  259. goto exit;
  260. }
  261. r->from_state = r->state;
  262. r->state = RES_ANY_BUSY;
  263. mlx4_dbg(dev, "res %s id 0x%x to busy\n",
  264. ResourceType(type), r->res_id);
  265. if (res)
  266. *((struct res_common **)res) = r;
  267. exit:
  268. spin_unlock_irq(mlx4_tlock(dev));
  269. return err;
  270. }
  271. int mlx4_get_slave_from_resource_id(struct mlx4_dev *dev,
  272. enum mlx4_resource type,
  273. int res_id, int *slave)
  274. {
  275. struct res_common *r;
  276. int err = -ENOENT;
  277. int id = res_id;
  278. if (type == RES_QP)
  279. id &= 0x7fffff;
  280. spin_lock(mlx4_tlock(dev));
  281. r = find_res(dev, id, type);
  282. if (r) {
  283. *slave = r->owner;
  284. err = 0;
  285. }
  286. spin_unlock(mlx4_tlock(dev));
  287. return err;
  288. }
  289. static void put_res(struct mlx4_dev *dev, int slave, int res_id,
  290. enum mlx4_resource type)
  291. {
  292. struct res_common *r;
  293. spin_lock_irq(mlx4_tlock(dev));
  294. r = find_res(dev, res_id, type);
  295. if (r)
  296. r->state = r->from_state;
  297. spin_unlock_irq(mlx4_tlock(dev));
  298. }
  299. static struct res_common *alloc_qp_tr(int id)
  300. {
  301. struct res_qp *ret;
  302. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  303. if (!ret)
  304. return NULL;
  305. ret->com.res_id = id;
  306. ret->com.state = RES_QP_RESERVED;
  307. ret->local_qpn = id;
  308. INIT_LIST_HEAD(&ret->mcg_list);
  309. spin_lock_init(&ret->mcg_spl);
  310. return &ret->com;
  311. }
  312. static struct res_common *alloc_mtt_tr(int id, int order)
  313. {
  314. struct res_mtt *ret;
  315. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  316. if (!ret)
  317. return NULL;
  318. ret->com.res_id = id;
  319. ret->order = order;
  320. ret->com.state = RES_MTT_ALLOCATED;
  321. atomic_set(&ret->ref_count, 0);
  322. return &ret->com;
  323. }
  324. static struct res_common *alloc_mpt_tr(int id, int key)
  325. {
  326. struct res_mpt *ret;
  327. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  328. if (!ret)
  329. return NULL;
  330. ret->com.res_id = id;
  331. ret->com.state = RES_MPT_RESERVED;
  332. ret->key = key;
  333. return &ret->com;
  334. }
  335. static struct res_common *alloc_eq_tr(int id)
  336. {
  337. struct res_eq *ret;
  338. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  339. if (!ret)
  340. return NULL;
  341. ret->com.res_id = id;
  342. ret->com.state = RES_EQ_RESERVED;
  343. return &ret->com;
  344. }
  345. static struct res_common *alloc_cq_tr(int id)
  346. {
  347. struct res_cq *ret;
  348. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  349. if (!ret)
  350. return NULL;
  351. ret->com.res_id = id;
  352. ret->com.state = RES_CQ_ALLOCATED;
  353. atomic_set(&ret->ref_count, 0);
  354. return &ret->com;
  355. }
  356. static struct res_common *alloc_srq_tr(int id)
  357. {
  358. struct res_srq *ret;
  359. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  360. if (!ret)
  361. return NULL;
  362. ret->com.res_id = id;
  363. ret->com.state = RES_SRQ_ALLOCATED;
  364. atomic_set(&ret->ref_count, 0);
  365. return &ret->com;
  366. }
  367. static struct res_common *alloc_counter_tr(int id)
  368. {
  369. struct res_counter *ret;
  370. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  371. if (!ret)
  372. return NULL;
  373. ret->com.res_id = id;
  374. ret->com.state = RES_COUNTER_ALLOCATED;
  375. return &ret->com;
  376. }
  377. static struct res_common *alloc_xrcdn_tr(int id)
  378. {
  379. struct res_xrcdn *ret;
  380. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  381. if (!ret)
  382. return NULL;
  383. ret->com.res_id = id;
  384. ret->com.state = RES_XRCD_ALLOCATED;
  385. return &ret->com;
  386. }
  387. static struct res_common *alloc_tr(int id, enum mlx4_resource type, int slave,
  388. int extra)
  389. {
  390. struct res_common *ret;
  391. switch (type) {
  392. case RES_QP:
  393. ret = alloc_qp_tr(id);
  394. break;
  395. case RES_MPT:
  396. ret = alloc_mpt_tr(id, extra);
  397. break;
  398. case RES_MTT:
  399. ret = alloc_mtt_tr(id, extra);
  400. break;
  401. case RES_EQ:
  402. ret = alloc_eq_tr(id);
  403. break;
  404. case RES_CQ:
  405. ret = alloc_cq_tr(id);
  406. break;
  407. case RES_SRQ:
  408. ret = alloc_srq_tr(id);
  409. break;
  410. case RES_MAC:
  411. printk(KERN_ERR "implementation missing\n");
  412. return NULL;
  413. case RES_COUNTER:
  414. ret = alloc_counter_tr(id);
  415. break;
  416. case RES_XRCD:
  417. ret = alloc_xrcdn_tr(id);
  418. break;
  419. default:
  420. return NULL;
  421. }
  422. if (ret)
  423. ret->owner = slave;
  424. return ret;
  425. }
  426. static int add_res_range(struct mlx4_dev *dev, int slave, int base, int count,
  427. enum mlx4_resource type, int extra)
  428. {
  429. int i;
  430. int err;
  431. struct mlx4_priv *priv = mlx4_priv(dev);
  432. struct res_common **res_arr;
  433. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  434. struct radix_tree_root *root = &tracker->res_tree[type];
  435. res_arr = kzalloc(count * sizeof *res_arr, GFP_KERNEL);
  436. if (!res_arr)
  437. return -ENOMEM;
  438. for (i = 0; i < count; ++i) {
  439. res_arr[i] = alloc_tr(base + i, type, slave, extra);
  440. if (!res_arr[i]) {
  441. for (--i; i >= 0; --i)
  442. kfree(res_arr[i]);
  443. kfree(res_arr);
  444. return -ENOMEM;
  445. }
  446. }
  447. spin_lock_irq(mlx4_tlock(dev));
  448. for (i = 0; i < count; ++i) {
  449. if (find_res(dev, base + i, type)) {
  450. err = -EEXIST;
  451. goto undo;
  452. }
  453. err = radix_tree_insert(root, base + i, res_arr[i]);
  454. if (err)
  455. goto undo;
  456. list_add_tail(&res_arr[i]->list,
  457. &tracker->slave_list[slave].res_list[type]);
  458. }
  459. spin_unlock_irq(mlx4_tlock(dev));
  460. kfree(res_arr);
  461. return 0;
  462. undo:
  463. for (--i; i >= base; --i)
  464. radix_tree_delete(&tracker->res_tree[type], i);
  465. spin_unlock_irq(mlx4_tlock(dev));
  466. for (i = 0; i < count; ++i)
  467. kfree(res_arr[i]);
  468. kfree(res_arr);
  469. return err;
  470. }
  471. static int remove_qp_ok(struct res_qp *res)
  472. {
  473. if (res->com.state == RES_QP_BUSY)
  474. return -EBUSY;
  475. else if (res->com.state != RES_QP_RESERVED)
  476. return -EPERM;
  477. return 0;
  478. }
  479. static int remove_mtt_ok(struct res_mtt *res, int order)
  480. {
  481. if (res->com.state == RES_MTT_BUSY ||
  482. atomic_read(&res->ref_count)) {
  483. printk(KERN_DEBUG "%s-%d: state %s, ref_count %d\n",
  484. __func__, __LINE__,
  485. mtt_states_str(res->com.state),
  486. atomic_read(&res->ref_count));
  487. return -EBUSY;
  488. } else if (res->com.state != RES_MTT_ALLOCATED)
  489. return -EPERM;
  490. else if (res->order != order)
  491. return -EINVAL;
  492. return 0;
  493. }
  494. static int remove_mpt_ok(struct res_mpt *res)
  495. {
  496. if (res->com.state == RES_MPT_BUSY)
  497. return -EBUSY;
  498. else if (res->com.state != RES_MPT_RESERVED)
  499. return -EPERM;
  500. return 0;
  501. }
  502. static int remove_eq_ok(struct res_eq *res)
  503. {
  504. if (res->com.state == RES_MPT_BUSY)
  505. return -EBUSY;
  506. else if (res->com.state != RES_MPT_RESERVED)
  507. return -EPERM;
  508. return 0;
  509. }
  510. static int remove_counter_ok(struct res_counter *res)
  511. {
  512. if (res->com.state == RES_COUNTER_BUSY)
  513. return -EBUSY;
  514. else if (res->com.state != RES_COUNTER_ALLOCATED)
  515. return -EPERM;
  516. return 0;
  517. }
  518. static int remove_xrcdn_ok(struct res_xrcdn *res)
  519. {
  520. if (res->com.state == RES_XRCD_BUSY)
  521. return -EBUSY;
  522. else if (res->com.state != RES_XRCD_ALLOCATED)
  523. return -EPERM;
  524. return 0;
  525. }
  526. static int remove_cq_ok(struct res_cq *res)
  527. {
  528. if (res->com.state == RES_CQ_BUSY)
  529. return -EBUSY;
  530. else if (res->com.state != RES_CQ_ALLOCATED)
  531. return -EPERM;
  532. return 0;
  533. }
  534. static int remove_srq_ok(struct res_srq *res)
  535. {
  536. if (res->com.state == RES_SRQ_BUSY)
  537. return -EBUSY;
  538. else if (res->com.state != RES_SRQ_ALLOCATED)
  539. return -EPERM;
  540. return 0;
  541. }
  542. static int remove_ok(struct res_common *res, enum mlx4_resource type, int extra)
  543. {
  544. switch (type) {
  545. case RES_QP:
  546. return remove_qp_ok((struct res_qp *)res);
  547. case RES_CQ:
  548. return remove_cq_ok((struct res_cq *)res);
  549. case RES_SRQ:
  550. return remove_srq_ok((struct res_srq *)res);
  551. case RES_MPT:
  552. return remove_mpt_ok((struct res_mpt *)res);
  553. case RES_MTT:
  554. return remove_mtt_ok((struct res_mtt *)res, extra);
  555. case RES_MAC:
  556. return -ENOSYS;
  557. case RES_EQ:
  558. return remove_eq_ok((struct res_eq *)res);
  559. case RES_COUNTER:
  560. return remove_counter_ok((struct res_counter *)res);
  561. case RES_XRCD:
  562. return remove_xrcdn_ok((struct res_xrcdn *)res);
  563. default:
  564. return -EINVAL;
  565. }
  566. }
  567. static int rem_res_range(struct mlx4_dev *dev, int slave, int base, int count,
  568. enum mlx4_resource type, int extra)
  569. {
  570. int i;
  571. int err;
  572. struct mlx4_priv *priv = mlx4_priv(dev);
  573. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  574. struct res_common *r;
  575. spin_lock_irq(mlx4_tlock(dev));
  576. for (i = base; i < base + count; ++i) {
  577. r = radix_tree_lookup(&tracker->res_tree[type], i);
  578. if (!r) {
  579. err = -ENOENT;
  580. goto out;
  581. }
  582. if (r->owner != slave) {
  583. err = -EPERM;
  584. goto out;
  585. }
  586. err = remove_ok(r, type, extra);
  587. if (err)
  588. goto out;
  589. }
  590. for (i = base; i < base + count; ++i) {
  591. r = radix_tree_lookup(&tracker->res_tree[type], i);
  592. radix_tree_delete(&tracker->res_tree[type], i);
  593. list_del(&r->list);
  594. kfree(r);
  595. }
  596. err = 0;
  597. out:
  598. spin_unlock_irq(mlx4_tlock(dev));
  599. return err;
  600. }
  601. static int qp_res_start_move_to(struct mlx4_dev *dev, int slave, int qpn,
  602. enum res_qp_states state, struct res_qp **qp,
  603. int alloc)
  604. {
  605. struct mlx4_priv *priv = mlx4_priv(dev);
  606. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  607. struct res_qp *r;
  608. int err = 0;
  609. spin_lock_irq(mlx4_tlock(dev));
  610. r = radix_tree_lookup(&tracker->res_tree[RES_QP], qpn);
  611. if (!r)
  612. err = -ENOENT;
  613. else if (r->com.owner != slave)
  614. err = -EPERM;
  615. else {
  616. switch (state) {
  617. case RES_QP_BUSY:
  618. mlx4_dbg(dev, "%s: failed RES_QP, 0x%x\n",
  619. __func__, r->com.res_id);
  620. err = -EBUSY;
  621. break;
  622. case RES_QP_RESERVED:
  623. if (r->com.state == RES_QP_MAPPED && !alloc)
  624. break;
  625. mlx4_dbg(dev, "failed RES_QP, 0x%x\n", r->com.res_id);
  626. err = -EINVAL;
  627. break;
  628. case RES_QP_MAPPED:
  629. if ((r->com.state == RES_QP_RESERVED && alloc) ||
  630. r->com.state == RES_QP_HW)
  631. break;
  632. else {
  633. mlx4_dbg(dev, "failed RES_QP, 0x%x\n",
  634. r->com.res_id);
  635. err = -EINVAL;
  636. }
  637. break;
  638. case RES_QP_HW:
  639. if (r->com.state != RES_QP_MAPPED)
  640. err = -EINVAL;
  641. break;
  642. default:
  643. err = -EINVAL;
  644. }
  645. if (!err) {
  646. r->com.from_state = r->com.state;
  647. r->com.to_state = state;
  648. r->com.state = RES_QP_BUSY;
  649. if (qp)
  650. *qp = (struct res_qp *)r;
  651. }
  652. }
  653. spin_unlock_irq(mlx4_tlock(dev));
  654. return err;
  655. }
  656. static int mr_res_start_move_to(struct mlx4_dev *dev, int slave, int index,
  657. enum res_mpt_states state, struct res_mpt **mpt)
  658. {
  659. struct mlx4_priv *priv = mlx4_priv(dev);
  660. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  661. struct res_mpt *r;
  662. int err = 0;
  663. spin_lock_irq(mlx4_tlock(dev));
  664. r = radix_tree_lookup(&tracker->res_tree[RES_MPT], index);
  665. if (!r)
  666. err = -ENOENT;
  667. else if (r->com.owner != slave)
  668. err = -EPERM;
  669. else {
  670. switch (state) {
  671. case RES_MPT_BUSY:
  672. err = -EINVAL;
  673. break;
  674. case RES_MPT_RESERVED:
  675. if (r->com.state != RES_MPT_MAPPED)
  676. err = -EINVAL;
  677. break;
  678. case RES_MPT_MAPPED:
  679. if (r->com.state != RES_MPT_RESERVED &&
  680. r->com.state != RES_MPT_HW)
  681. err = -EINVAL;
  682. break;
  683. case RES_MPT_HW:
  684. if (r->com.state != RES_MPT_MAPPED)
  685. err = -EINVAL;
  686. break;
  687. default:
  688. err = -EINVAL;
  689. }
  690. if (!err) {
  691. r->com.from_state = r->com.state;
  692. r->com.to_state = state;
  693. r->com.state = RES_MPT_BUSY;
  694. if (mpt)
  695. *mpt = (struct res_mpt *)r;
  696. }
  697. }
  698. spin_unlock_irq(mlx4_tlock(dev));
  699. return err;
  700. }
  701. static int eq_res_start_move_to(struct mlx4_dev *dev, int slave, int index,
  702. enum res_eq_states state, struct res_eq **eq)
  703. {
  704. struct mlx4_priv *priv = mlx4_priv(dev);
  705. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  706. struct res_eq *r;
  707. int err = 0;
  708. spin_lock_irq(mlx4_tlock(dev));
  709. r = radix_tree_lookup(&tracker->res_tree[RES_EQ], index);
  710. if (!r)
  711. err = -ENOENT;
  712. else if (r->com.owner != slave)
  713. err = -EPERM;
  714. else {
  715. switch (state) {
  716. case RES_EQ_BUSY:
  717. err = -EINVAL;
  718. break;
  719. case RES_EQ_RESERVED:
  720. if (r->com.state != RES_EQ_HW)
  721. err = -EINVAL;
  722. break;
  723. case RES_EQ_HW:
  724. if (r->com.state != RES_EQ_RESERVED)
  725. err = -EINVAL;
  726. break;
  727. default:
  728. err = -EINVAL;
  729. }
  730. if (!err) {
  731. r->com.from_state = r->com.state;
  732. r->com.to_state = state;
  733. r->com.state = RES_EQ_BUSY;
  734. if (eq)
  735. *eq = r;
  736. }
  737. }
  738. spin_unlock_irq(mlx4_tlock(dev));
  739. return err;
  740. }
  741. static int cq_res_start_move_to(struct mlx4_dev *dev, int slave, int cqn,
  742. enum res_cq_states state, struct res_cq **cq)
  743. {
  744. struct mlx4_priv *priv = mlx4_priv(dev);
  745. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  746. struct res_cq *r;
  747. int err;
  748. spin_lock_irq(mlx4_tlock(dev));
  749. r = radix_tree_lookup(&tracker->res_tree[RES_CQ], cqn);
  750. if (!r)
  751. err = -ENOENT;
  752. else if (r->com.owner != slave)
  753. err = -EPERM;
  754. else {
  755. switch (state) {
  756. case RES_CQ_BUSY:
  757. err = -EBUSY;
  758. break;
  759. case RES_CQ_ALLOCATED:
  760. if (r->com.state != RES_CQ_HW)
  761. err = -EINVAL;
  762. else if (atomic_read(&r->ref_count))
  763. err = -EBUSY;
  764. else
  765. err = 0;
  766. break;
  767. case RES_CQ_HW:
  768. if (r->com.state != RES_CQ_ALLOCATED)
  769. err = -EINVAL;
  770. else
  771. err = 0;
  772. break;
  773. default:
  774. err = -EINVAL;
  775. }
  776. if (!err) {
  777. r->com.from_state = r->com.state;
  778. r->com.to_state = state;
  779. r->com.state = RES_CQ_BUSY;
  780. if (cq)
  781. *cq = r;
  782. }
  783. }
  784. spin_unlock_irq(mlx4_tlock(dev));
  785. return err;
  786. }
  787. static int srq_res_start_move_to(struct mlx4_dev *dev, int slave, int index,
  788. enum res_cq_states state, struct res_srq **srq)
  789. {
  790. struct mlx4_priv *priv = mlx4_priv(dev);
  791. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  792. struct res_srq *r;
  793. int err = 0;
  794. spin_lock_irq(mlx4_tlock(dev));
  795. r = radix_tree_lookup(&tracker->res_tree[RES_SRQ], index);
  796. if (!r)
  797. err = -ENOENT;
  798. else if (r->com.owner != slave)
  799. err = -EPERM;
  800. else {
  801. switch (state) {
  802. case RES_SRQ_BUSY:
  803. err = -EINVAL;
  804. break;
  805. case RES_SRQ_ALLOCATED:
  806. if (r->com.state != RES_SRQ_HW)
  807. err = -EINVAL;
  808. else if (atomic_read(&r->ref_count))
  809. err = -EBUSY;
  810. break;
  811. case RES_SRQ_HW:
  812. if (r->com.state != RES_SRQ_ALLOCATED)
  813. err = -EINVAL;
  814. break;
  815. default:
  816. err = -EINVAL;
  817. }
  818. if (!err) {
  819. r->com.from_state = r->com.state;
  820. r->com.to_state = state;
  821. r->com.state = RES_SRQ_BUSY;
  822. if (srq)
  823. *srq = r;
  824. }
  825. }
  826. spin_unlock_irq(mlx4_tlock(dev));
  827. return err;
  828. }
  829. static void res_abort_move(struct mlx4_dev *dev, int slave,
  830. enum mlx4_resource type, int id)
  831. {
  832. struct mlx4_priv *priv = mlx4_priv(dev);
  833. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  834. struct res_common *r;
  835. spin_lock_irq(mlx4_tlock(dev));
  836. r = radix_tree_lookup(&tracker->res_tree[type], id);
  837. if (r && (r->owner == slave))
  838. r->state = r->from_state;
  839. spin_unlock_irq(mlx4_tlock(dev));
  840. }
  841. static void res_end_move(struct mlx4_dev *dev, int slave,
  842. enum mlx4_resource type, int id)
  843. {
  844. struct mlx4_priv *priv = mlx4_priv(dev);
  845. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  846. struct res_common *r;
  847. spin_lock_irq(mlx4_tlock(dev));
  848. r = radix_tree_lookup(&tracker->res_tree[type], id);
  849. if (r && (r->owner == slave))
  850. r->state = r->to_state;
  851. spin_unlock_irq(mlx4_tlock(dev));
  852. }
  853. static int valid_reserved(struct mlx4_dev *dev, int slave, int qpn)
  854. {
  855. return mlx4_is_qp_reserved(dev, qpn);
  856. }
  857. static int qp_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  858. u64 in_param, u64 *out_param)
  859. {
  860. int err;
  861. int count;
  862. int align;
  863. int base;
  864. int qpn;
  865. switch (op) {
  866. case RES_OP_RESERVE:
  867. count = get_param_l(&in_param);
  868. align = get_param_h(&in_param);
  869. err = __mlx4_qp_reserve_range(dev, count, align, &base);
  870. if (err)
  871. return err;
  872. err = add_res_range(dev, slave, base, count, RES_QP, 0);
  873. if (err) {
  874. __mlx4_qp_release_range(dev, base, count);
  875. return err;
  876. }
  877. set_param_l(out_param, base);
  878. break;
  879. case RES_OP_MAP_ICM:
  880. qpn = get_param_l(&in_param) & 0x7fffff;
  881. if (valid_reserved(dev, slave, qpn)) {
  882. err = add_res_range(dev, slave, qpn, 1, RES_QP, 0);
  883. if (err)
  884. return err;
  885. }
  886. err = qp_res_start_move_to(dev, slave, qpn, RES_QP_MAPPED,
  887. NULL, 1);
  888. if (err)
  889. return err;
  890. if (!valid_reserved(dev, slave, qpn)) {
  891. err = __mlx4_qp_alloc_icm(dev, qpn);
  892. if (err) {
  893. res_abort_move(dev, slave, RES_QP, qpn);
  894. return err;
  895. }
  896. }
  897. res_end_move(dev, slave, RES_QP, qpn);
  898. break;
  899. default:
  900. err = -EINVAL;
  901. break;
  902. }
  903. return err;
  904. }
  905. static int mtt_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  906. u64 in_param, u64 *out_param)
  907. {
  908. int err = -EINVAL;
  909. int base;
  910. int order;
  911. if (op != RES_OP_RESERVE_AND_MAP)
  912. return err;
  913. order = get_param_l(&in_param);
  914. base = __mlx4_alloc_mtt_range(dev, order);
  915. if (base == -1)
  916. return -ENOMEM;
  917. err = add_res_range(dev, slave, base, 1, RES_MTT, order);
  918. if (err)
  919. __mlx4_free_mtt_range(dev, base, order);
  920. else
  921. set_param_l(out_param, base);
  922. return err;
  923. }
  924. static int mpt_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  925. u64 in_param, u64 *out_param)
  926. {
  927. int err = -EINVAL;
  928. int index;
  929. int id;
  930. struct res_mpt *mpt;
  931. switch (op) {
  932. case RES_OP_RESERVE:
  933. index = __mlx4_mr_reserve(dev);
  934. if (index == -1)
  935. break;
  936. id = index & mpt_mask(dev);
  937. err = add_res_range(dev, slave, id, 1, RES_MPT, index);
  938. if (err) {
  939. __mlx4_mr_release(dev, index);
  940. break;
  941. }
  942. set_param_l(out_param, index);
  943. break;
  944. case RES_OP_MAP_ICM:
  945. index = get_param_l(&in_param);
  946. id = index & mpt_mask(dev);
  947. err = mr_res_start_move_to(dev, slave, id,
  948. RES_MPT_MAPPED, &mpt);
  949. if (err)
  950. return err;
  951. err = __mlx4_mr_alloc_icm(dev, mpt->key);
  952. if (err) {
  953. res_abort_move(dev, slave, RES_MPT, id);
  954. return err;
  955. }
  956. res_end_move(dev, slave, RES_MPT, id);
  957. break;
  958. }
  959. return err;
  960. }
  961. static int cq_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  962. u64 in_param, u64 *out_param)
  963. {
  964. int cqn;
  965. int err;
  966. switch (op) {
  967. case RES_OP_RESERVE_AND_MAP:
  968. err = __mlx4_cq_alloc_icm(dev, &cqn);
  969. if (err)
  970. break;
  971. err = add_res_range(dev, slave, cqn, 1, RES_CQ, 0);
  972. if (err) {
  973. __mlx4_cq_free_icm(dev, cqn);
  974. break;
  975. }
  976. set_param_l(out_param, cqn);
  977. break;
  978. default:
  979. err = -EINVAL;
  980. }
  981. return err;
  982. }
  983. static int srq_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  984. u64 in_param, u64 *out_param)
  985. {
  986. int srqn;
  987. int err;
  988. switch (op) {
  989. case RES_OP_RESERVE_AND_MAP:
  990. err = __mlx4_srq_alloc_icm(dev, &srqn);
  991. if (err)
  992. break;
  993. err = add_res_range(dev, slave, srqn, 1, RES_SRQ, 0);
  994. if (err) {
  995. __mlx4_srq_free_icm(dev, srqn);
  996. break;
  997. }
  998. set_param_l(out_param, srqn);
  999. break;
  1000. default:
  1001. err = -EINVAL;
  1002. }
  1003. return err;
  1004. }
  1005. static int mac_add_to_slave(struct mlx4_dev *dev, int slave, u64 mac, int port)
  1006. {
  1007. struct mlx4_priv *priv = mlx4_priv(dev);
  1008. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  1009. struct mac_res *res;
  1010. res = kzalloc(sizeof *res, GFP_KERNEL);
  1011. if (!res)
  1012. return -ENOMEM;
  1013. res->mac = mac;
  1014. res->port = (u8) port;
  1015. list_add_tail(&res->list,
  1016. &tracker->slave_list[slave].res_list[RES_MAC]);
  1017. return 0;
  1018. }
  1019. static void mac_del_from_slave(struct mlx4_dev *dev, int slave, u64 mac,
  1020. int port)
  1021. {
  1022. struct mlx4_priv *priv = mlx4_priv(dev);
  1023. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  1024. struct list_head *mac_list =
  1025. &tracker->slave_list[slave].res_list[RES_MAC];
  1026. struct mac_res *res, *tmp;
  1027. list_for_each_entry_safe(res, tmp, mac_list, list) {
  1028. if (res->mac == mac && res->port == (u8) port) {
  1029. list_del(&res->list);
  1030. kfree(res);
  1031. break;
  1032. }
  1033. }
  1034. }
  1035. static void rem_slave_macs(struct mlx4_dev *dev, int slave)
  1036. {
  1037. struct mlx4_priv *priv = mlx4_priv(dev);
  1038. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  1039. struct list_head *mac_list =
  1040. &tracker->slave_list[slave].res_list[RES_MAC];
  1041. struct mac_res *res, *tmp;
  1042. list_for_each_entry_safe(res, tmp, mac_list, list) {
  1043. list_del(&res->list);
  1044. __mlx4_unregister_mac(dev, res->port, res->mac);
  1045. kfree(res);
  1046. }
  1047. }
  1048. static int mac_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1049. u64 in_param, u64 *out_param)
  1050. {
  1051. int err = -EINVAL;
  1052. int port;
  1053. u64 mac;
  1054. if (op != RES_OP_RESERVE_AND_MAP)
  1055. return err;
  1056. port = get_param_l(out_param);
  1057. mac = in_param;
  1058. err = __mlx4_register_mac(dev, port, mac);
  1059. if (err >= 0) {
  1060. set_param_l(out_param, err);
  1061. err = 0;
  1062. }
  1063. if (!err) {
  1064. err = mac_add_to_slave(dev, slave, mac, port);
  1065. if (err)
  1066. __mlx4_unregister_mac(dev, port, mac);
  1067. }
  1068. return err;
  1069. }
  1070. static int vlan_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1071. u64 in_param, u64 *out_param)
  1072. {
  1073. return 0;
  1074. }
  1075. static int counter_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1076. u64 in_param, u64 *out_param)
  1077. {
  1078. u32 index;
  1079. int err;
  1080. if (op != RES_OP_RESERVE)
  1081. return -EINVAL;
  1082. err = __mlx4_counter_alloc(dev, &index);
  1083. if (err)
  1084. return err;
  1085. err = add_res_range(dev, slave, index, 1, RES_COUNTER, 0);
  1086. if (err)
  1087. __mlx4_counter_free(dev, index);
  1088. else
  1089. set_param_l(out_param, index);
  1090. return err;
  1091. }
  1092. static int xrcdn_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1093. u64 in_param, u64 *out_param)
  1094. {
  1095. u32 xrcdn;
  1096. int err;
  1097. if (op != RES_OP_RESERVE)
  1098. return -EINVAL;
  1099. err = __mlx4_xrcd_alloc(dev, &xrcdn);
  1100. if (err)
  1101. return err;
  1102. err = add_res_range(dev, slave, xrcdn, 1, RES_XRCD, 0);
  1103. if (err)
  1104. __mlx4_xrcd_free(dev, xrcdn);
  1105. else
  1106. set_param_l(out_param, xrcdn);
  1107. return err;
  1108. }
  1109. int mlx4_ALLOC_RES_wrapper(struct mlx4_dev *dev, int slave,
  1110. struct mlx4_vhcr *vhcr,
  1111. struct mlx4_cmd_mailbox *inbox,
  1112. struct mlx4_cmd_mailbox *outbox,
  1113. struct mlx4_cmd_info *cmd)
  1114. {
  1115. int err;
  1116. int alop = vhcr->op_modifier;
  1117. switch (vhcr->in_modifier) {
  1118. case RES_QP:
  1119. err = qp_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1120. vhcr->in_param, &vhcr->out_param);
  1121. break;
  1122. case RES_MTT:
  1123. err = mtt_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1124. vhcr->in_param, &vhcr->out_param);
  1125. break;
  1126. case RES_MPT:
  1127. err = mpt_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1128. vhcr->in_param, &vhcr->out_param);
  1129. break;
  1130. case RES_CQ:
  1131. err = cq_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1132. vhcr->in_param, &vhcr->out_param);
  1133. break;
  1134. case RES_SRQ:
  1135. err = srq_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1136. vhcr->in_param, &vhcr->out_param);
  1137. break;
  1138. case RES_MAC:
  1139. err = mac_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1140. vhcr->in_param, &vhcr->out_param);
  1141. break;
  1142. case RES_VLAN:
  1143. err = vlan_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1144. vhcr->in_param, &vhcr->out_param);
  1145. break;
  1146. case RES_COUNTER:
  1147. err = counter_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1148. vhcr->in_param, &vhcr->out_param);
  1149. break;
  1150. case RES_XRCD:
  1151. err = xrcdn_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1152. vhcr->in_param, &vhcr->out_param);
  1153. break;
  1154. default:
  1155. err = -EINVAL;
  1156. break;
  1157. }
  1158. return err;
  1159. }
  1160. static int qp_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1161. u64 in_param)
  1162. {
  1163. int err;
  1164. int count;
  1165. int base;
  1166. int qpn;
  1167. switch (op) {
  1168. case RES_OP_RESERVE:
  1169. base = get_param_l(&in_param) & 0x7fffff;
  1170. count = get_param_h(&in_param);
  1171. err = rem_res_range(dev, slave, base, count, RES_QP, 0);
  1172. if (err)
  1173. break;
  1174. __mlx4_qp_release_range(dev, base, count);
  1175. break;
  1176. case RES_OP_MAP_ICM:
  1177. qpn = get_param_l(&in_param) & 0x7fffff;
  1178. err = qp_res_start_move_to(dev, slave, qpn, RES_QP_RESERVED,
  1179. NULL, 0);
  1180. if (err)
  1181. return err;
  1182. if (!valid_reserved(dev, slave, qpn))
  1183. __mlx4_qp_free_icm(dev, qpn);
  1184. res_end_move(dev, slave, RES_QP, qpn);
  1185. if (valid_reserved(dev, slave, qpn))
  1186. err = rem_res_range(dev, slave, qpn, 1, RES_QP, 0);
  1187. break;
  1188. default:
  1189. err = -EINVAL;
  1190. break;
  1191. }
  1192. return err;
  1193. }
  1194. static int mtt_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1195. u64 in_param, u64 *out_param)
  1196. {
  1197. int err = -EINVAL;
  1198. int base;
  1199. int order;
  1200. if (op != RES_OP_RESERVE_AND_MAP)
  1201. return err;
  1202. base = get_param_l(&in_param);
  1203. order = get_param_h(&in_param);
  1204. err = rem_res_range(dev, slave, base, 1, RES_MTT, order);
  1205. if (!err)
  1206. __mlx4_free_mtt_range(dev, base, order);
  1207. return err;
  1208. }
  1209. static int mpt_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1210. u64 in_param)
  1211. {
  1212. int err = -EINVAL;
  1213. int index;
  1214. int id;
  1215. struct res_mpt *mpt;
  1216. switch (op) {
  1217. case RES_OP_RESERVE:
  1218. index = get_param_l(&in_param);
  1219. id = index & mpt_mask(dev);
  1220. err = get_res(dev, slave, id, RES_MPT, &mpt);
  1221. if (err)
  1222. break;
  1223. index = mpt->key;
  1224. put_res(dev, slave, id, RES_MPT);
  1225. err = rem_res_range(dev, slave, id, 1, RES_MPT, 0);
  1226. if (err)
  1227. break;
  1228. __mlx4_mr_release(dev, index);
  1229. break;
  1230. case RES_OP_MAP_ICM:
  1231. index = get_param_l(&in_param);
  1232. id = index & mpt_mask(dev);
  1233. err = mr_res_start_move_to(dev, slave, id,
  1234. RES_MPT_RESERVED, &mpt);
  1235. if (err)
  1236. return err;
  1237. __mlx4_mr_free_icm(dev, mpt->key);
  1238. res_end_move(dev, slave, RES_MPT, id);
  1239. return err;
  1240. break;
  1241. default:
  1242. err = -EINVAL;
  1243. break;
  1244. }
  1245. return err;
  1246. }
  1247. static int cq_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1248. u64 in_param, u64 *out_param)
  1249. {
  1250. int cqn;
  1251. int err;
  1252. switch (op) {
  1253. case RES_OP_RESERVE_AND_MAP:
  1254. cqn = get_param_l(&in_param);
  1255. err = rem_res_range(dev, slave, cqn, 1, RES_CQ, 0);
  1256. if (err)
  1257. break;
  1258. __mlx4_cq_free_icm(dev, cqn);
  1259. break;
  1260. default:
  1261. err = -EINVAL;
  1262. break;
  1263. }
  1264. return err;
  1265. }
  1266. static int srq_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1267. u64 in_param, u64 *out_param)
  1268. {
  1269. int srqn;
  1270. int err;
  1271. switch (op) {
  1272. case RES_OP_RESERVE_AND_MAP:
  1273. srqn = get_param_l(&in_param);
  1274. err = rem_res_range(dev, slave, srqn, 1, RES_SRQ, 0);
  1275. if (err)
  1276. break;
  1277. __mlx4_srq_free_icm(dev, srqn);
  1278. break;
  1279. default:
  1280. err = -EINVAL;
  1281. break;
  1282. }
  1283. return err;
  1284. }
  1285. static int mac_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1286. u64 in_param, u64 *out_param)
  1287. {
  1288. int port;
  1289. int err = 0;
  1290. switch (op) {
  1291. case RES_OP_RESERVE_AND_MAP:
  1292. port = get_param_l(out_param);
  1293. mac_del_from_slave(dev, slave, in_param, port);
  1294. __mlx4_unregister_mac(dev, port, in_param);
  1295. break;
  1296. default:
  1297. err = -EINVAL;
  1298. break;
  1299. }
  1300. return err;
  1301. }
  1302. static int vlan_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1303. u64 in_param, u64 *out_param)
  1304. {
  1305. return 0;
  1306. }
  1307. static int counter_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1308. u64 in_param, u64 *out_param)
  1309. {
  1310. int index;
  1311. int err;
  1312. if (op != RES_OP_RESERVE)
  1313. return -EINVAL;
  1314. index = get_param_l(&in_param);
  1315. err = rem_res_range(dev, slave, index, 1, RES_COUNTER, 0);
  1316. if (err)
  1317. return err;
  1318. __mlx4_counter_free(dev, index);
  1319. return err;
  1320. }
  1321. static int xrcdn_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1322. u64 in_param, u64 *out_param)
  1323. {
  1324. int xrcdn;
  1325. int err;
  1326. if (op != RES_OP_RESERVE)
  1327. return -EINVAL;
  1328. xrcdn = get_param_l(&in_param);
  1329. err = rem_res_range(dev, slave, xrcdn, 1, RES_XRCD, 0);
  1330. if (err)
  1331. return err;
  1332. __mlx4_xrcd_free(dev, xrcdn);
  1333. return err;
  1334. }
  1335. int mlx4_FREE_RES_wrapper(struct mlx4_dev *dev, int slave,
  1336. struct mlx4_vhcr *vhcr,
  1337. struct mlx4_cmd_mailbox *inbox,
  1338. struct mlx4_cmd_mailbox *outbox,
  1339. struct mlx4_cmd_info *cmd)
  1340. {
  1341. int err = -EINVAL;
  1342. int alop = vhcr->op_modifier;
  1343. switch (vhcr->in_modifier) {
  1344. case RES_QP:
  1345. err = qp_free_res(dev, slave, vhcr->op_modifier, alop,
  1346. vhcr->in_param);
  1347. break;
  1348. case RES_MTT:
  1349. err = mtt_free_res(dev, slave, vhcr->op_modifier, alop,
  1350. vhcr->in_param, &vhcr->out_param);
  1351. break;
  1352. case RES_MPT:
  1353. err = mpt_free_res(dev, slave, vhcr->op_modifier, alop,
  1354. vhcr->in_param);
  1355. break;
  1356. case RES_CQ:
  1357. err = cq_free_res(dev, slave, vhcr->op_modifier, alop,
  1358. vhcr->in_param, &vhcr->out_param);
  1359. break;
  1360. case RES_SRQ:
  1361. err = srq_free_res(dev, slave, vhcr->op_modifier, alop,
  1362. vhcr->in_param, &vhcr->out_param);
  1363. break;
  1364. case RES_MAC:
  1365. err = mac_free_res(dev, slave, vhcr->op_modifier, alop,
  1366. vhcr->in_param, &vhcr->out_param);
  1367. break;
  1368. case RES_VLAN:
  1369. err = vlan_free_res(dev, slave, vhcr->op_modifier, alop,
  1370. vhcr->in_param, &vhcr->out_param);
  1371. break;
  1372. case RES_COUNTER:
  1373. err = counter_free_res(dev, slave, vhcr->op_modifier, alop,
  1374. vhcr->in_param, &vhcr->out_param);
  1375. break;
  1376. case RES_XRCD:
  1377. err = xrcdn_free_res(dev, slave, vhcr->op_modifier, alop,
  1378. vhcr->in_param, &vhcr->out_param);
  1379. default:
  1380. break;
  1381. }
  1382. return err;
  1383. }
  1384. /* ugly but other choices are uglier */
  1385. static int mr_phys_mpt(struct mlx4_mpt_entry *mpt)
  1386. {
  1387. return (be32_to_cpu(mpt->flags) >> 9) & 1;
  1388. }
  1389. static int mr_get_mtt_addr(struct mlx4_mpt_entry *mpt)
  1390. {
  1391. return (int)be64_to_cpu(mpt->mtt_addr) & 0xfffffff8;
  1392. }
  1393. static int mr_get_mtt_size(struct mlx4_mpt_entry *mpt)
  1394. {
  1395. return be32_to_cpu(mpt->mtt_sz);
  1396. }
  1397. static int qp_get_mtt_addr(struct mlx4_qp_context *qpc)
  1398. {
  1399. return be32_to_cpu(qpc->mtt_base_addr_l) & 0xfffffff8;
  1400. }
  1401. static int srq_get_mtt_addr(struct mlx4_srq_context *srqc)
  1402. {
  1403. return be32_to_cpu(srqc->mtt_base_addr_l) & 0xfffffff8;
  1404. }
  1405. static int qp_get_mtt_size(struct mlx4_qp_context *qpc)
  1406. {
  1407. int page_shift = (qpc->log_page_size & 0x3f) + 12;
  1408. int log_sq_size = (qpc->sq_size_stride >> 3) & 0xf;
  1409. int log_sq_sride = qpc->sq_size_stride & 7;
  1410. int log_rq_size = (qpc->rq_size_stride >> 3) & 0xf;
  1411. int log_rq_stride = qpc->rq_size_stride & 7;
  1412. int srq = (be32_to_cpu(qpc->srqn) >> 24) & 1;
  1413. int rss = (be32_to_cpu(qpc->flags) >> 13) & 1;
  1414. int xrc = (be32_to_cpu(qpc->local_qpn) >> 23) & 1;
  1415. int sq_size;
  1416. int rq_size;
  1417. int total_pages;
  1418. int total_mem;
  1419. int page_offset = (be32_to_cpu(qpc->params2) >> 6) & 0x3f;
  1420. sq_size = 1 << (log_sq_size + log_sq_sride + 4);
  1421. rq_size = (srq|rss|xrc) ? 0 : (1 << (log_rq_size + log_rq_stride + 4));
  1422. total_mem = sq_size + rq_size;
  1423. total_pages =
  1424. roundup_pow_of_two((total_mem + (page_offset << 6)) >>
  1425. page_shift);
  1426. return total_pages;
  1427. }
  1428. static int check_mtt_range(struct mlx4_dev *dev, int slave, int start,
  1429. int size, struct res_mtt *mtt)
  1430. {
  1431. int res_start = mtt->com.res_id;
  1432. int res_size = (1 << mtt->order);
  1433. if (start < res_start || start + size > res_start + res_size)
  1434. return -EPERM;
  1435. return 0;
  1436. }
  1437. int mlx4_SW2HW_MPT_wrapper(struct mlx4_dev *dev, int slave,
  1438. struct mlx4_vhcr *vhcr,
  1439. struct mlx4_cmd_mailbox *inbox,
  1440. struct mlx4_cmd_mailbox *outbox,
  1441. struct mlx4_cmd_info *cmd)
  1442. {
  1443. int err;
  1444. int index = vhcr->in_modifier;
  1445. struct res_mtt *mtt;
  1446. struct res_mpt *mpt;
  1447. int mtt_base = mr_get_mtt_addr(inbox->buf) / dev->caps.mtt_entry_sz;
  1448. int phys;
  1449. int id;
  1450. id = index & mpt_mask(dev);
  1451. err = mr_res_start_move_to(dev, slave, id, RES_MPT_HW, &mpt);
  1452. if (err)
  1453. return err;
  1454. phys = mr_phys_mpt(inbox->buf);
  1455. if (!phys) {
  1456. err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
  1457. if (err)
  1458. goto ex_abort;
  1459. err = check_mtt_range(dev, slave, mtt_base,
  1460. mr_get_mtt_size(inbox->buf), mtt);
  1461. if (err)
  1462. goto ex_put;
  1463. mpt->mtt = mtt;
  1464. }
  1465. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1466. if (err)
  1467. goto ex_put;
  1468. if (!phys) {
  1469. atomic_inc(&mtt->ref_count);
  1470. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  1471. }
  1472. res_end_move(dev, slave, RES_MPT, id);
  1473. return 0;
  1474. ex_put:
  1475. if (!phys)
  1476. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  1477. ex_abort:
  1478. res_abort_move(dev, slave, RES_MPT, id);
  1479. return err;
  1480. }
  1481. int mlx4_HW2SW_MPT_wrapper(struct mlx4_dev *dev, int slave,
  1482. struct mlx4_vhcr *vhcr,
  1483. struct mlx4_cmd_mailbox *inbox,
  1484. struct mlx4_cmd_mailbox *outbox,
  1485. struct mlx4_cmd_info *cmd)
  1486. {
  1487. int err;
  1488. int index = vhcr->in_modifier;
  1489. struct res_mpt *mpt;
  1490. int id;
  1491. id = index & mpt_mask(dev);
  1492. err = mr_res_start_move_to(dev, slave, id, RES_MPT_MAPPED, &mpt);
  1493. if (err)
  1494. return err;
  1495. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1496. if (err)
  1497. goto ex_abort;
  1498. if (mpt->mtt)
  1499. atomic_dec(&mpt->mtt->ref_count);
  1500. res_end_move(dev, slave, RES_MPT, id);
  1501. return 0;
  1502. ex_abort:
  1503. res_abort_move(dev, slave, RES_MPT, id);
  1504. return err;
  1505. }
  1506. int mlx4_QUERY_MPT_wrapper(struct mlx4_dev *dev, int slave,
  1507. struct mlx4_vhcr *vhcr,
  1508. struct mlx4_cmd_mailbox *inbox,
  1509. struct mlx4_cmd_mailbox *outbox,
  1510. struct mlx4_cmd_info *cmd)
  1511. {
  1512. int err;
  1513. int index = vhcr->in_modifier;
  1514. struct res_mpt *mpt;
  1515. int id;
  1516. id = index & mpt_mask(dev);
  1517. err = get_res(dev, slave, id, RES_MPT, &mpt);
  1518. if (err)
  1519. return err;
  1520. if (mpt->com.from_state != RES_MPT_HW) {
  1521. err = -EBUSY;
  1522. goto out;
  1523. }
  1524. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1525. out:
  1526. put_res(dev, slave, id, RES_MPT);
  1527. return err;
  1528. }
  1529. static int qp_get_rcqn(struct mlx4_qp_context *qpc)
  1530. {
  1531. return be32_to_cpu(qpc->cqn_recv) & 0xffffff;
  1532. }
  1533. static int qp_get_scqn(struct mlx4_qp_context *qpc)
  1534. {
  1535. return be32_to_cpu(qpc->cqn_send) & 0xffffff;
  1536. }
  1537. static u32 qp_get_srqn(struct mlx4_qp_context *qpc)
  1538. {
  1539. return be32_to_cpu(qpc->srqn) & 0x1ffffff;
  1540. }
  1541. int mlx4_RST2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
  1542. struct mlx4_vhcr *vhcr,
  1543. struct mlx4_cmd_mailbox *inbox,
  1544. struct mlx4_cmd_mailbox *outbox,
  1545. struct mlx4_cmd_info *cmd)
  1546. {
  1547. int err;
  1548. int qpn = vhcr->in_modifier & 0x7fffff;
  1549. struct res_mtt *mtt;
  1550. struct res_qp *qp;
  1551. struct mlx4_qp_context *qpc = inbox->buf + 8;
  1552. int mtt_base = qp_get_mtt_addr(qpc) / dev->caps.mtt_entry_sz;
  1553. int mtt_size = qp_get_mtt_size(qpc);
  1554. struct res_cq *rcq;
  1555. struct res_cq *scq;
  1556. int rcqn = qp_get_rcqn(qpc);
  1557. int scqn = qp_get_scqn(qpc);
  1558. u32 srqn = qp_get_srqn(qpc) & 0xffffff;
  1559. int use_srq = (qp_get_srqn(qpc) >> 24) & 1;
  1560. struct res_srq *srq;
  1561. int local_qpn = be32_to_cpu(qpc->local_qpn) & 0xffffff;
  1562. err = qp_res_start_move_to(dev, slave, qpn, RES_QP_HW, &qp, 0);
  1563. if (err)
  1564. return err;
  1565. qp->local_qpn = local_qpn;
  1566. err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
  1567. if (err)
  1568. goto ex_abort;
  1569. err = check_mtt_range(dev, slave, mtt_base, mtt_size, mtt);
  1570. if (err)
  1571. goto ex_put_mtt;
  1572. err = get_res(dev, slave, rcqn, RES_CQ, &rcq);
  1573. if (err)
  1574. goto ex_put_mtt;
  1575. if (scqn != rcqn) {
  1576. err = get_res(dev, slave, scqn, RES_CQ, &scq);
  1577. if (err)
  1578. goto ex_put_rcq;
  1579. } else
  1580. scq = rcq;
  1581. if (use_srq) {
  1582. err = get_res(dev, slave, srqn, RES_SRQ, &srq);
  1583. if (err)
  1584. goto ex_put_scq;
  1585. }
  1586. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1587. if (err)
  1588. goto ex_put_srq;
  1589. atomic_inc(&mtt->ref_count);
  1590. qp->mtt = mtt;
  1591. atomic_inc(&rcq->ref_count);
  1592. qp->rcq = rcq;
  1593. atomic_inc(&scq->ref_count);
  1594. qp->scq = scq;
  1595. if (scqn != rcqn)
  1596. put_res(dev, slave, scqn, RES_CQ);
  1597. if (use_srq) {
  1598. atomic_inc(&srq->ref_count);
  1599. put_res(dev, slave, srqn, RES_SRQ);
  1600. qp->srq = srq;
  1601. }
  1602. put_res(dev, slave, rcqn, RES_CQ);
  1603. put_res(dev, slave, mtt_base, RES_MTT);
  1604. res_end_move(dev, slave, RES_QP, qpn);
  1605. return 0;
  1606. ex_put_srq:
  1607. if (use_srq)
  1608. put_res(dev, slave, srqn, RES_SRQ);
  1609. ex_put_scq:
  1610. if (scqn != rcqn)
  1611. put_res(dev, slave, scqn, RES_CQ);
  1612. ex_put_rcq:
  1613. put_res(dev, slave, rcqn, RES_CQ);
  1614. ex_put_mtt:
  1615. put_res(dev, slave, mtt_base, RES_MTT);
  1616. ex_abort:
  1617. res_abort_move(dev, slave, RES_QP, qpn);
  1618. return err;
  1619. }
  1620. static int eq_get_mtt_addr(struct mlx4_eq_context *eqc)
  1621. {
  1622. return be32_to_cpu(eqc->mtt_base_addr_l) & 0xfffffff8;
  1623. }
  1624. static int eq_get_mtt_size(struct mlx4_eq_context *eqc)
  1625. {
  1626. int log_eq_size = eqc->log_eq_size & 0x1f;
  1627. int page_shift = (eqc->log_page_size & 0x3f) + 12;
  1628. if (log_eq_size + 5 < page_shift)
  1629. return 1;
  1630. return 1 << (log_eq_size + 5 - page_shift);
  1631. }
  1632. static int cq_get_mtt_addr(struct mlx4_cq_context *cqc)
  1633. {
  1634. return be32_to_cpu(cqc->mtt_base_addr_l) & 0xfffffff8;
  1635. }
  1636. static int cq_get_mtt_size(struct mlx4_cq_context *cqc)
  1637. {
  1638. int log_cq_size = (be32_to_cpu(cqc->logsize_usrpage) >> 24) & 0x1f;
  1639. int page_shift = (cqc->log_page_size & 0x3f) + 12;
  1640. if (log_cq_size + 5 < page_shift)
  1641. return 1;
  1642. return 1 << (log_cq_size + 5 - page_shift);
  1643. }
  1644. int mlx4_SW2HW_EQ_wrapper(struct mlx4_dev *dev, int slave,
  1645. struct mlx4_vhcr *vhcr,
  1646. struct mlx4_cmd_mailbox *inbox,
  1647. struct mlx4_cmd_mailbox *outbox,
  1648. struct mlx4_cmd_info *cmd)
  1649. {
  1650. int err;
  1651. int eqn = vhcr->in_modifier;
  1652. int res_id = (slave << 8) | eqn;
  1653. struct mlx4_eq_context *eqc = inbox->buf;
  1654. int mtt_base = eq_get_mtt_addr(eqc) / dev->caps.mtt_entry_sz;
  1655. int mtt_size = eq_get_mtt_size(eqc);
  1656. struct res_eq *eq;
  1657. struct res_mtt *mtt;
  1658. err = add_res_range(dev, slave, res_id, 1, RES_EQ, 0);
  1659. if (err)
  1660. return err;
  1661. err = eq_res_start_move_to(dev, slave, res_id, RES_EQ_HW, &eq);
  1662. if (err)
  1663. goto out_add;
  1664. err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
  1665. if (err)
  1666. goto out_move;
  1667. err = check_mtt_range(dev, slave, mtt_base, mtt_size, mtt);
  1668. if (err)
  1669. goto out_put;
  1670. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1671. if (err)
  1672. goto out_put;
  1673. atomic_inc(&mtt->ref_count);
  1674. eq->mtt = mtt;
  1675. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  1676. res_end_move(dev, slave, RES_EQ, res_id);
  1677. return 0;
  1678. out_put:
  1679. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  1680. out_move:
  1681. res_abort_move(dev, slave, RES_EQ, res_id);
  1682. out_add:
  1683. rem_res_range(dev, slave, res_id, 1, RES_EQ, 0);
  1684. return err;
  1685. }
  1686. static int get_containing_mtt(struct mlx4_dev *dev, int slave, int start,
  1687. int len, struct res_mtt **res)
  1688. {
  1689. struct mlx4_priv *priv = mlx4_priv(dev);
  1690. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  1691. struct res_mtt *mtt;
  1692. int err = -EINVAL;
  1693. spin_lock_irq(mlx4_tlock(dev));
  1694. list_for_each_entry(mtt, &tracker->slave_list[slave].res_list[RES_MTT],
  1695. com.list) {
  1696. if (!check_mtt_range(dev, slave, start, len, mtt)) {
  1697. *res = mtt;
  1698. mtt->com.from_state = mtt->com.state;
  1699. mtt->com.state = RES_MTT_BUSY;
  1700. err = 0;
  1701. break;
  1702. }
  1703. }
  1704. spin_unlock_irq(mlx4_tlock(dev));
  1705. return err;
  1706. }
  1707. int mlx4_WRITE_MTT_wrapper(struct mlx4_dev *dev, int slave,
  1708. struct mlx4_vhcr *vhcr,
  1709. struct mlx4_cmd_mailbox *inbox,
  1710. struct mlx4_cmd_mailbox *outbox,
  1711. struct mlx4_cmd_info *cmd)
  1712. {
  1713. struct mlx4_mtt mtt;
  1714. __be64 *page_list = inbox->buf;
  1715. u64 *pg_list = (u64 *)page_list;
  1716. int i;
  1717. struct res_mtt *rmtt = NULL;
  1718. int start = be64_to_cpu(page_list[0]);
  1719. int npages = vhcr->in_modifier;
  1720. int err;
  1721. err = get_containing_mtt(dev, slave, start, npages, &rmtt);
  1722. if (err)
  1723. return err;
  1724. /* Call the SW implementation of write_mtt:
  1725. * - Prepare a dummy mtt struct
  1726. * - Translate inbox contents to simple addresses in host endianess */
  1727. mtt.offset = 0; /* TBD this is broken but I don't handle it since
  1728. we don't really use it */
  1729. mtt.order = 0;
  1730. mtt.page_shift = 0;
  1731. for (i = 0; i < npages; ++i)
  1732. pg_list[i + 2] = (be64_to_cpu(page_list[i + 2]) & ~1ULL);
  1733. err = __mlx4_write_mtt(dev, &mtt, be64_to_cpu(page_list[0]), npages,
  1734. ((u64 *)page_list + 2));
  1735. if (rmtt)
  1736. put_res(dev, slave, rmtt->com.res_id, RES_MTT);
  1737. return err;
  1738. }
  1739. int mlx4_HW2SW_EQ_wrapper(struct mlx4_dev *dev, int slave,
  1740. struct mlx4_vhcr *vhcr,
  1741. struct mlx4_cmd_mailbox *inbox,
  1742. struct mlx4_cmd_mailbox *outbox,
  1743. struct mlx4_cmd_info *cmd)
  1744. {
  1745. int eqn = vhcr->in_modifier;
  1746. int res_id = eqn | (slave << 8);
  1747. struct res_eq *eq;
  1748. int err;
  1749. err = eq_res_start_move_to(dev, slave, res_id, RES_EQ_RESERVED, &eq);
  1750. if (err)
  1751. return err;
  1752. err = get_res(dev, slave, eq->mtt->com.res_id, RES_MTT, NULL);
  1753. if (err)
  1754. goto ex_abort;
  1755. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1756. if (err)
  1757. goto ex_put;
  1758. atomic_dec(&eq->mtt->ref_count);
  1759. put_res(dev, slave, eq->mtt->com.res_id, RES_MTT);
  1760. res_end_move(dev, slave, RES_EQ, res_id);
  1761. rem_res_range(dev, slave, res_id, 1, RES_EQ, 0);
  1762. return 0;
  1763. ex_put:
  1764. put_res(dev, slave, eq->mtt->com.res_id, RES_MTT);
  1765. ex_abort:
  1766. res_abort_move(dev, slave, RES_EQ, res_id);
  1767. return err;
  1768. }
  1769. int mlx4_GEN_EQE(struct mlx4_dev *dev, int slave, struct mlx4_eqe *eqe)
  1770. {
  1771. struct mlx4_priv *priv = mlx4_priv(dev);
  1772. struct mlx4_slave_event_eq_info *event_eq;
  1773. struct mlx4_cmd_mailbox *mailbox;
  1774. u32 in_modifier = 0;
  1775. int err;
  1776. int res_id;
  1777. struct res_eq *req;
  1778. if (!priv->mfunc.master.slave_state)
  1779. return -EINVAL;
  1780. event_eq = &priv->mfunc.master.slave_state[slave].event_eq[eqe->type];
  1781. /* Create the event only if the slave is registered */
  1782. if (event_eq->eqn < 0)
  1783. return 0;
  1784. mutex_lock(&priv->mfunc.master.gen_eqe_mutex[slave]);
  1785. res_id = (slave << 8) | event_eq->eqn;
  1786. err = get_res(dev, slave, res_id, RES_EQ, &req);
  1787. if (err)
  1788. goto unlock;
  1789. if (req->com.from_state != RES_EQ_HW) {
  1790. err = -EINVAL;
  1791. goto put;
  1792. }
  1793. mailbox = mlx4_alloc_cmd_mailbox(dev);
  1794. if (IS_ERR(mailbox)) {
  1795. err = PTR_ERR(mailbox);
  1796. goto put;
  1797. }
  1798. if (eqe->type == MLX4_EVENT_TYPE_CMD) {
  1799. ++event_eq->token;
  1800. eqe->event.cmd.token = cpu_to_be16(event_eq->token);
  1801. }
  1802. memcpy(mailbox->buf, (u8 *) eqe, 28);
  1803. in_modifier = (slave & 0xff) | ((event_eq->eqn & 0xff) << 16);
  1804. err = mlx4_cmd(dev, mailbox->dma, in_modifier, 0,
  1805. MLX4_CMD_GEN_EQE, MLX4_CMD_TIME_CLASS_B,
  1806. MLX4_CMD_NATIVE);
  1807. put_res(dev, slave, res_id, RES_EQ);
  1808. mutex_unlock(&priv->mfunc.master.gen_eqe_mutex[slave]);
  1809. mlx4_free_cmd_mailbox(dev, mailbox);
  1810. return err;
  1811. put:
  1812. put_res(dev, slave, res_id, RES_EQ);
  1813. unlock:
  1814. mutex_unlock(&priv->mfunc.master.gen_eqe_mutex[slave]);
  1815. return err;
  1816. }
  1817. int mlx4_QUERY_EQ_wrapper(struct mlx4_dev *dev, int slave,
  1818. struct mlx4_vhcr *vhcr,
  1819. struct mlx4_cmd_mailbox *inbox,
  1820. struct mlx4_cmd_mailbox *outbox,
  1821. struct mlx4_cmd_info *cmd)
  1822. {
  1823. int eqn = vhcr->in_modifier;
  1824. int res_id = eqn | (slave << 8);
  1825. struct res_eq *eq;
  1826. int err;
  1827. err = get_res(dev, slave, res_id, RES_EQ, &eq);
  1828. if (err)
  1829. return err;
  1830. if (eq->com.from_state != RES_EQ_HW) {
  1831. err = -EINVAL;
  1832. goto ex_put;
  1833. }
  1834. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1835. ex_put:
  1836. put_res(dev, slave, res_id, RES_EQ);
  1837. return err;
  1838. }
  1839. int mlx4_SW2HW_CQ_wrapper(struct mlx4_dev *dev, int slave,
  1840. struct mlx4_vhcr *vhcr,
  1841. struct mlx4_cmd_mailbox *inbox,
  1842. struct mlx4_cmd_mailbox *outbox,
  1843. struct mlx4_cmd_info *cmd)
  1844. {
  1845. int err;
  1846. int cqn = vhcr->in_modifier;
  1847. struct mlx4_cq_context *cqc = inbox->buf;
  1848. int mtt_base = cq_get_mtt_addr(cqc) / dev->caps.mtt_entry_sz;
  1849. struct res_cq *cq;
  1850. struct res_mtt *mtt;
  1851. err = cq_res_start_move_to(dev, slave, cqn, RES_CQ_HW, &cq);
  1852. if (err)
  1853. return err;
  1854. err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
  1855. if (err)
  1856. goto out_move;
  1857. err = check_mtt_range(dev, slave, mtt_base, cq_get_mtt_size(cqc), mtt);
  1858. if (err)
  1859. goto out_put;
  1860. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1861. if (err)
  1862. goto out_put;
  1863. atomic_inc(&mtt->ref_count);
  1864. cq->mtt = mtt;
  1865. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  1866. res_end_move(dev, slave, RES_CQ, cqn);
  1867. return 0;
  1868. out_put:
  1869. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  1870. out_move:
  1871. res_abort_move(dev, slave, RES_CQ, cqn);
  1872. return err;
  1873. }
  1874. int mlx4_HW2SW_CQ_wrapper(struct mlx4_dev *dev, int slave,
  1875. struct mlx4_vhcr *vhcr,
  1876. struct mlx4_cmd_mailbox *inbox,
  1877. struct mlx4_cmd_mailbox *outbox,
  1878. struct mlx4_cmd_info *cmd)
  1879. {
  1880. int err;
  1881. int cqn = vhcr->in_modifier;
  1882. struct res_cq *cq;
  1883. err = cq_res_start_move_to(dev, slave, cqn, RES_CQ_ALLOCATED, &cq);
  1884. if (err)
  1885. return err;
  1886. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1887. if (err)
  1888. goto out_move;
  1889. atomic_dec(&cq->mtt->ref_count);
  1890. res_end_move(dev, slave, RES_CQ, cqn);
  1891. return 0;
  1892. out_move:
  1893. res_abort_move(dev, slave, RES_CQ, cqn);
  1894. return err;
  1895. }
  1896. int mlx4_QUERY_CQ_wrapper(struct mlx4_dev *dev, int slave,
  1897. struct mlx4_vhcr *vhcr,
  1898. struct mlx4_cmd_mailbox *inbox,
  1899. struct mlx4_cmd_mailbox *outbox,
  1900. struct mlx4_cmd_info *cmd)
  1901. {
  1902. int cqn = vhcr->in_modifier;
  1903. struct res_cq *cq;
  1904. int err;
  1905. err = get_res(dev, slave, cqn, RES_CQ, &cq);
  1906. if (err)
  1907. return err;
  1908. if (cq->com.from_state != RES_CQ_HW)
  1909. goto ex_put;
  1910. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1911. ex_put:
  1912. put_res(dev, slave, cqn, RES_CQ);
  1913. return err;
  1914. }
  1915. static int handle_resize(struct mlx4_dev *dev, int slave,
  1916. struct mlx4_vhcr *vhcr,
  1917. struct mlx4_cmd_mailbox *inbox,
  1918. struct mlx4_cmd_mailbox *outbox,
  1919. struct mlx4_cmd_info *cmd,
  1920. struct res_cq *cq)
  1921. {
  1922. int err;
  1923. struct res_mtt *orig_mtt;
  1924. struct res_mtt *mtt;
  1925. struct mlx4_cq_context *cqc = inbox->buf;
  1926. int mtt_base = cq_get_mtt_addr(cqc) / dev->caps.mtt_entry_sz;
  1927. err = get_res(dev, slave, cq->mtt->com.res_id, RES_MTT, &orig_mtt);
  1928. if (err)
  1929. return err;
  1930. if (orig_mtt != cq->mtt) {
  1931. err = -EINVAL;
  1932. goto ex_put;
  1933. }
  1934. err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
  1935. if (err)
  1936. goto ex_put;
  1937. err = check_mtt_range(dev, slave, mtt_base, cq_get_mtt_size(cqc), mtt);
  1938. if (err)
  1939. goto ex_put1;
  1940. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1941. if (err)
  1942. goto ex_put1;
  1943. atomic_dec(&orig_mtt->ref_count);
  1944. put_res(dev, slave, orig_mtt->com.res_id, RES_MTT);
  1945. atomic_inc(&mtt->ref_count);
  1946. cq->mtt = mtt;
  1947. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  1948. return 0;
  1949. ex_put1:
  1950. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  1951. ex_put:
  1952. put_res(dev, slave, orig_mtt->com.res_id, RES_MTT);
  1953. return err;
  1954. }
  1955. int mlx4_MODIFY_CQ_wrapper(struct mlx4_dev *dev, int slave,
  1956. struct mlx4_vhcr *vhcr,
  1957. struct mlx4_cmd_mailbox *inbox,
  1958. struct mlx4_cmd_mailbox *outbox,
  1959. struct mlx4_cmd_info *cmd)
  1960. {
  1961. int cqn = vhcr->in_modifier;
  1962. struct res_cq *cq;
  1963. int err;
  1964. err = get_res(dev, slave, cqn, RES_CQ, &cq);
  1965. if (err)
  1966. return err;
  1967. if (cq->com.from_state != RES_CQ_HW)
  1968. goto ex_put;
  1969. if (vhcr->op_modifier == 0) {
  1970. err = handle_resize(dev, slave, vhcr, inbox, outbox, cmd, cq);
  1971. goto ex_put;
  1972. }
  1973. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1974. ex_put:
  1975. put_res(dev, slave, cqn, RES_CQ);
  1976. return err;
  1977. }
  1978. static int srq_get_mtt_size(struct mlx4_srq_context *srqc)
  1979. {
  1980. int log_srq_size = (be32_to_cpu(srqc->state_logsize_srqn) >> 24) & 0xf;
  1981. int log_rq_stride = srqc->logstride & 7;
  1982. int page_shift = (srqc->log_page_size & 0x3f) + 12;
  1983. if (log_srq_size + log_rq_stride + 4 < page_shift)
  1984. return 1;
  1985. return 1 << (log_srq_size + log_rq_stride + 4 - page_shift);
  1986. }
  1987. int mlx4_SW2HW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
  1988. struct mlx4_vhcr *vhcr,
  1989. struct mlx4_cmd_mailbox *inbox,
  1990. struct mlx4_cmd_mailbox *outbox,
  1991. struct mlx4_cmd_info *cmd)
  1992. {
  1993. int err;
  1994. int srqn = vhcr->in_modifier;
  1995. struct res_mtt *mtt;
  1996. struct res_srq *srq;
  1997. struct mlx4_srq_context *srqc = inbox->buf;
  1998. int mtt_base = srq_get_mtt_addr(srqc) / dev->caps.mtt_entry_sz;
  1999. if (srqn != (be32_to_cpu(srqc->state_logsize_srqn) & 0xffffff))
  2000. return -EINVAL;
  2001. err = srq_res_start_move_to(dev, slave, srqn, RES_SRQ_HW, &srq);
  2002. if (err)
  2003. return err;
  2004. err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
  2005. if (err)
  2006. goto ex_abort;
  2007. err = check_mtt_range(dev, slave, mtt_base, srq_get_mtt_size(srqc),
  2008. mtt);
  2009. if (err)
  2010. goto ex_put_mtt;
  2011. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2012. if (err)
  2013. goto ex_put_mtt;
  2014. atomic_inc(&mtt->ref_count);
  2015. srq->mtt = mtt;
  2016. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  2017. res_end_move(dev, slave, RES_SRQ, srqn);
  2018. return 0;
  2019. ex_put_mtt:
  2020. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  2021. ex_abort:
  2022. res_abort_move(dev, slave, RES_SRQ, srqn);
  2023. return err;
  2024. }
  2025. int mlx4_HW2SW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
  2026. struct mlx4_vhcr *vhcr,
  2027. struct mlx4_cmd_mailbox *inbox,
  2028. struct mlx4_cmd_mailbox *outbox,
  2029. struct mlx4_cmd_info *cmd)
  2030. {
  2031. int err;
  2032. int srqn = vhcr->in_modifier;
  2033. struct res_srq *srq;
  2034. err = srq_res_start_move_to(dev, slave, srqn, RES_SRQ_ALLOCATED, &srq);
  2035. if (err)
  2036. return err;
  2037. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2038. if (err)
  2039. goto ex_abort;
  2040. atomic_dec(&srq->mtt->ref_count);
  2041. if (srq->cq)
  2042. atomic_dec(&srq->cq->ref_count);
  2043. res_end_move(dev, slave, RES_SRQ, srqn);
  2044. return 0;
  2045. ex_abort:
  2046. res_abort_move(dev, slave, RES_SRQ, srqn);
  2047. return err;
  2048. }
  2049. int mlx4_QUERY_SRQ_wrapper(struct mlx4_dev *dev, int slave,
  2050. struct mlx4_vhcr *vhcr,
  2051. struct mlx4_cmd_mailbox *inbox,
  2052. struct mlx4_cmd_mailbox *outbox,
  2053. struct mlx4_cmd_info *cmd)
  2054. {
  2055. int err;
  2056. int srqn = vhcr->in_modifier;
  2057. struct res_srq *srq;
  2058. err = get_res(dev, slave, srqn, RES_SRQ, &srq);
  2059. if (err)
  2060. return err;
  2061. if (srq->com.from_state != RES_SRQ_HW) {
  2062. err = -EBUSY;
  2063. goto out;
  2064. }
  2065. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2066. out:
  2067. put_res(dev, slave, srqn, RES_SRQ);
  2068. return err;
  2069. }
  2070. int mlx4_ARM_SRQ_wrapper(struct mlx4_dev *dev, int slave,
  2071. struct mlx4_vhcr *vhcr,
  2072. struct mlx4_cmd_mailbox *inbox,
  2073. struct mlx4_cmd_mailbox *outbox,
  2074. struct mlx4_cmd_info *cmd)
  2075. {
  2076. int err;
  2077. int srqn = vhcr->in_modifier;
  2078. struct res_srq *srq;
  2079. err = get_res(dev, slave, srqn, RES_SRQ, &srq);
  2080. if (err)
  2081. return err;
  2082. if (srq->com.from_state != RES_SRQ_HW) {
  2083. err = -EBUSY;
  2084. goto out;
  2085. }
  2086. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2087. out:
  2088. put_res(dev, slave, srqn, RES_SRQ);
  2089. return err;
  2090. }
  2091. int mlx4_GEN_QP_wrapper(struct mlx4_dev *dev, int slave,
  2092. struct mlx4_vhcr *vhcr,
  2093. struct mlx4_cmd_mailbox *inbox,
  2094. struct mlx4_cmd_mailbox *outbox,
  2095. struct mlx4_cmd_info *cmd)
  2096. {
  2097. int err;
  2098. int qpn = vhcr->in_modifier & 0x7fffff;
  2099. struct res_qp *qp;
  2100. err = get_res(dev, slave, qpn, RES_QP, &qp);
  2101. if (err)
  2102. return err;
  2103. if (qp->com.from_state != RES_QP_HW) {
  2104. err = -EBUSY;
  2105. goto out;
  2106. }
  2107. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2108. out:
  2109. put_res(dev, slave, qpn, RES_QP);
  2110. return err;
  2111. }
  2112. int mlx4_INIT2RTR_QP_wrapper(struct mlx4_dev *dev, int slave,
  2113. struct mlx4_vhcr *vhcr,
  2114. struct mlx4_cmd_mailbox *inbox,
  2115. struct mlx4_cmd_mailbox *outbox,
  2116. struct mlx4_cmd_info *cmd)
  2117. {
  2118. struct mlx4_qp_context *qpc = inbox->buf + 8;
  2119. update_ud_gid(dev, qpc, (u8)slave);
  2120. return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2121. }
  2122. int mlx4_2RST_QP_wrapper(struct mlx4_dev *dev, int slave,
  2123. struct mlx4_vhcr *vhcr,
  2124. struct mlx4_cmd_mailbox *inbox,
  2125. struct mlx4_cmd_mailbox *outbox,
  2126. struct mlx4_cmd_info *cmd)
  2127. {
  2128. int err;
  2129. int qpn = vhcr->in_modifier & 0x7fffff;
  2130. struct res_qp *qp;
  2131. err = qp_res_start_move_to(dev, slave, qpn, RES_QP_MAPPED, &qp, 0);
  2132. if (err)
  2133. return err;
  2134. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2135. if (err)
  2136. goto ex_abort;
  2137. atomic_dec(&qp->mtt->ref_count);
  2138. atomic_dec(&qp->rcq->ref_count);
  2139. atomic_dec(&qp->scq->ref_count);
  2140. if (qp->srq)
  2141. atomic_dec(&qp->srq->ref_count);
  2142. res_end_move(dev, slave, RES_QP, qpn);
  2143. return 0;
  2144. ex_abort:
  2145. res_abort_move(dev, slave, RES_QP, qpn);
  2146. return err;
  2147. }
  2148. static struct res_gid *find_gid(struct mlx4_dev *dev, int slave,
  2149. struct res_qp *rqp, u8 *gid)
  2150. {
  2151. struct res_gid *res;
  2152. list_for_each_entry(res, &rqp->mcg_list, list) {
  2153. if (!memcmp(res->gid, gid, 16))
  2154. return res;
  2155. }
  2156. return NULL;
  2157. }
  2158. static int add_mcg_res(struct mlx4_dev *dev, int slave, struct res_qp *rqp,
  2159. u8 *gid, enum mlx4_protocol prot,
  2160. enum mlx4_steer_type steer)
  2161. {
  2162. struct res_gid *res;
  2163. int err;
  2164. res = kzalloc(sizeof *res, GFP_KERNEL);
  2165. if (!res)
  2166. return -ENOMEM;
  2167. spin_lock_irq(&rqp->mcg_spl);
  2168. if (find_gid(dev, slave, rqp, gid)) {
  2169. kfree(res);
  2170. err = -EEXIST;
  2171. } else {
  2172. memcpy(res->gid, gid, 16);
  2173. res->prot = prot;
  2174. res->steer = steer;
  2175. list_add_tail(&res->list, &rqp->mcg_list);
  2176. err = 0;
  2177. }
  2178. spin_unlock_irq(&rqp->mcg_spl);
  2179. return err;
  2180. }
  2181. static int rem_mcg_res(struct mlx4_dev *dev, int slave, struct res_qp *rqp,
  2182. u8 *gid, enum mlx4_protocol prot,
  2183. enum mlx4_steer_type steer)
  2184. {
  2185. struct res_gid *res;
  2186. int err;
  2187. spin_lock_irq(&rqp->mcg_spl);
  2188. res = find_gid(dev, slave, rqp, gid);
  2189. if (!res || res->prot != prot || res->steer != steer)
  2190. err = -EINVAL;
  2191. else {
  2192. list_del(&res->list);
  2193. kfree(res);
  2194. err = 0;
  2195. }
  2196. spin_unlock_irq(&rqp->mcg_spl);
  2197. return err;
  2198. }
  2199. int mlx4_QP_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
  2200. struct mlx4_vhcr *vhcr,
  2201. struct mlx4_cmd_mailbox *inbox,
  2202. struct mlx4_cmd_mailbox *outbox,
  2203. struct mlx4_cmd_info *cmd)
  2204. {
  2205. struct mlx4_qp qp; /* dummy for calling attach/detach */
  2206. u8 *gid = inbox->buf;
  2207. enum mlx4_protocol prot = (vhcr->in_modifier >> 28) & 0x7;
  2208. int err;
  2209. int qpn;
  2210. struct res_qp *rqp;
  2211. int attach = vhcr->op_modifier;
  2212. int block_loopback = vhcr->in_modifier >> 31;
  2213. u8 steer_type_mask = 2;
  2214. enum mlx4_steer_type type = (gid[7] & steer_type_mask) >> 1;
  2215. qpn = vhcr->in_modifier & 0xffffff;
  2216. err = get_res(dev, slave, qpn, RES_QP, &rqp);
  2217. if (err)
  2218. return err;
  2219. qp.qpn = qpn;
  2220. if (attach) {
  2221. err = add_mcg_res(dev, slave, rqp, gid, prot, type);
  2222. if (err)
  2223. goto ex_put;
  2224. err = mlx4_qp_attach_common(dev, &qp, gid,
  2225. block_loopback, prot, type);
  2226. if (err)
  2227. goto ex_rem;
  2228. } else {
  2229. err = rem_mcg_res(dev, slave, rqp, gid, prot, type);
  2230. if (err)
  2231. goto ex_put;
  2232. err = mlx4_qp_detach_common(dev, &qp, gid, prot, type);
  2233. }
  2234. put_res(dev, slave, qpn, RES_QP);
  2235. return 0;
  2236. ex_rem:
  2237. /* ignore error return below, already in error */
  2238. (void) rem_mcg_res(dev, slave, rqp, gid, prot, type);
  2239. ex_put:
  2240. put_res(dev, slave, qpn, RES_QP);
  2241. return err;
  2242. }
  2243. enum {
  2244. BUSY_MAX_RETRIES = 10
  2245. };
  2246. int mlx4_QUERY_IF_STAT_wrapper(struct mlx4_dev *dev, int slave,
  2247. struct mlx4_vhcr *vhcr,
  2248. struct mlx4_cmd_mailbox *inbox,
  2249. struct mlx4_cmd_mailbox *outbox,
  2250. struct mlx4_cmd_info *cmd)
  2251. {
  2252. int err;
  2253. int index = vhcr->in_modifier & 0xffff;
  2254. err = get_res(dev, slave, index, RES_COUNTER, NULL);
  2255. if (err)
  2256. return err;
  2257. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2258. put_res(dev, slave, index, RES_COUNTER);
  2259. return err;
  2260. }
  2261. static void detach_qp(struct mlx4_dev *dev, int slave, struct res_qp *rqp)
  2262. {
  2263. struct res_gid *rgid;
  2264. struct res_gid *tmp;
  2265. struct mlx4_qp qp; /* dummy for calling attach/detach */
  2266. list_for_each_entry_safe(rgid, tmp, &rqp->mcg_list, list) {
  2267. qp.qpn = rqp->local_qpn;
  2268. (void) mlx4_qp_detach_common(dev, &qp, rgid->gid, rgid->prot,
  2269. rgid->steer);
  2270. list_del(&rgid->list);
  2271. kfree(rgid);
  2272. }
  2273. }
  2274. static int _move_all_busy(struct mlx4_dev *dev, int slave,
  2275. enum mlx4_resource type, int print)
  2276. {
  2277. struct mlx4_priv *priv = mlx4_priv(dev);
  2278. struct mlx4_resource_tracker *tracker =
  2279. &priv->mfunc.master.res_tracker;
  2280. struct list_head *rlist = &tracker->slave_list[slave].res_list[type];
  2281. struct res_common *r;
  2282. struct res_common *tmp;
  2283. int busy;
  2284. busy = 0;
  2285. spin_lock_irq(mlx4_tlock(dev));
  2286. list_for_each_entry_safe(r, tmp, rlist, list) {
  2287. if (r->owner == slave) {
  2288. if (!r->removing) {
  2289. if (r->state == RES_ANY_BUSY) {
  2290. if (print)
  2291. mlx4_dbg(dev,
  2292. "%s id 0x%x is busy\n",
  2293. ResourceType(type),
  2294. r->res_id);
  2295. ++busy;
  2296. } else {
  2297. r->from_state = r->state;
  2298. r->state = RES_ANY_BUSY;
  2299. r->removing = 1;
  2300. }
  2301. }
  2302. }
  2303. }
  2304. spin_unlock_irq(mlx4_tlock(dev));
  2305. return busy;
  2306. }
  2307. static int move_all_busy(struct mlx4_dev *dev, int slave,
  2308. enum mlx4_resource type)
  2309. {
  2310. unsigned long begin;
  2311. int busy;
  2312. begin = jiffies;
  2313. do {
  2314. busy = _move_all_busy(dev, slave, type, 0);
  2315. if (time_after(jiffies, begin + 5 * HZ))
  2316. break;
  2317. if (busy)
  2318. cond_resched();
  2319. } while (busy);
  2320. if (busy)
  2321. busy = _move_all_busy(dev, slave, type, 1);
  2322. return busy;
  2323. }
  2324. static void rem_slave_qps(struct mlx4_dev *dev, int slave)
  2325. {
  2326. struct mlx4_priv *priv = mlx4_priv(dev);
  2327. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  2328. struct list_head *qp_list =
  2329. &tracker->slave_list[slave].res_list[RES_QP];
  2330. struct res_qp *qp;
  2331. struct res_qp *tmp;
  2332. int state;
  2333. u64 in_param;
  2334. int qpn;
  2335. int err;
  2336. err = move_all_busy(dev, slave, RES_QP);
  2337. if (err)
  2338. mlx4_warn(dev, "rem_slave_qps: Could not move all qps to busy"
  2339. "for slave %d\n", slave);
  2340. spin_lock_irq(mlx4_tlock(dev));
  2341. list_for_each_entry_safe(qp, tmp, qp_list, com.list) {
  2342. spin_unlock_irq(mlx4_tlock(dev));
  2343. if (qp->com.owner == slave) {
  2344. qpn = qp->com.res_id;
  2345. detach_qp(dev, slave, qp);
  2346. state = qp->com.from_state;
  2347. while (state != 0) {
  2348. switch (state) {
  2349. case RES_QP_RESERVED:
  2350. spin_lock_irq(mlx4_tlock(dev));
  2351. radix_tree_delete(&tracker->res_tree[RES_QP],
  2352. qp->com.res_id);
  2353. list_del(&qp->com.list);
  2354. spin_unlock_irq(mlx4_tlock(dev));
  2355. kfree(qp);
  2356. state = 0;
  2357. break;
  2358. case RES_QP_MAPPED:
  2359. if (!valid_reserved(dev, slave, qpn))
  2360. __mlx4_qp_free_icm(dev, qpn);
  2361. state = RES_QP_RESERVED;
  2362. break;
  2363. case RES_QP_HW:
  2364. in_param = slave;
  2365. err = mlx4_cmd(dev, in_param,
  2366. qp->local_qpn, 2,
  2367. MLX4_CMD_2RST_QP,
  2368. MLX4_CMD_TIME_CLASS_A,
  2369. MLX4_CMD_NATIVE);
  2370. if (err)
  2371. mlx4_dbg(dev, "rem_slave_qps: failed"
  2372. " to move slave %d qpn %d to"
  2373. " reset\n", slave,
  2374. qp->local_qpn);
  2375. atomic_dec(&qp->rcq->ref_count);
  2376. atomic_dec(&qp->scq->ref_count);
  2377. atomic_dec(&qp->mtt->ref_count);
  2378. if (qp->srq)
  2379. atomic_dec(&qp->srq->ref_count);
  2380. state = RES_QP_MAPPED;
  2381. break;
  2382. default:
  2383. state = 0;
  2384. }
  2385. }
  2386. }
  2387. spin_lock_irq(mlx4_tlock(dev));
  2388. }
  2389. spin_unlock_irq(mlx4_tlock(dev));
  2390. }
  2391. static void rem_slave_srqs(struct mlx4_dev *dev, int slave)
  2392. {
  2393. struct mlx4_priv *priv = mlx4_priv(dev);
  2394. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  2395. struct list_head *srq_list =
  2396. &tracker->slave_list[slave].res_list[RES_SRQ];
  2397. struct res_srq *srq;
  2398. struct res_srq *tmp;
  2399. int state;
  2400. u64 in_param;
  2401. LIST_HEAD(tlist);
  2402. int srqn;
  2403. int err;
  2404. err = move_all_busy(dev, slave, RES_SRQ);
  2405. if (err)
  2406. mlx4_warn(dev, "rem_slave_srqs: Could not move all srqs to "
  2407. "busy for slave %d\n", slave);
  2408. spin_lock_irq(mlx4_tlock(dev));
  2409. list_for_each_entry_safe(srq, tmp, srq_list, com.list) {
  2410. spin_unlock_irq(mlx4_tlock(dev));
  2411. if (srq->com.owner == slave) {
  2412. srqn = srq->com.res_id;
  2413. state = srq->com.from_state;
  2414. while (state != 0) {
  2415. switch (state) {
  2416. case RES_SRQ_ALLOCATED:
  2417. __mlx4_srq_free_icm(dev, srqn);
  2418. spin_lock_irq(mlx4_tlock(dev));
  2419. radix_tree_delete(&tracker->res_tree[RES_SRQ],
  2420. srqn);
  2421. list_del(&srq->com.list);
  2422. spin_unlock_irq(mlx4_tlock(dev));
  2423. kfree(srq);
  2424. state = 0;
  2425. break;
  2426. case RES_SRQ_HW:
  2427. in_param = slave;
  2428. err = mlx4_cmd(dev, in_param, srqn, 1,
  2429. MLX4_CMD_HW2SW_SRQ,
  2430. MLX4_CMD_TIME_CLASS_A,
  2431. MLX4_CMD_NATIVE);
  2432. if (err)
  2433. mlx4_dbg(dev, "rem_slave_srqs: failed"
  2434. " to move slave %d srq %d to"
  2435. " SW ownership\n",
  2436. slave, srqn);
  2437. atomic_dec(&srq->mtt->ref_count);
  2438. if (srq->cq)
  2439. atomic_dec(&srq->cq->ref_count);
  2440. state = RES_SRQ_ALLOCATED;
  2441. break;
  2442. default:
  2443. state = 0;
  2444. }
  2445. }
  2446. }
  2447. spin_lock_irq(mlx4_tlock(dev));
  2448. }
  2449. spin_unlock_irq(mlx4_tlock(dev));
  2450. }
  2451. static void rem_slave_cqs(struct mlx4_dev *dev, int slave)
  2452. {
  2453. struct mlx4_priv *priv = mlx4_priv(dev);
  2454. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  2455. struct list_head *cq_list =
  2456. &tracker->slave_list[slave].res_list[RES_CQ];
  2457. struct res_cq *cq;
  2458. struct res_cq *tmp;
  2459. int state;
  2460. u64 in_param;
  2461. LIST_HEAD(tlist);
  2462. int cqn;
  2463. int err;
  2464. err = move_all_busy(dev, slave, RES_CQ);
  2465. if (err)
  2466. mlx4_warn(dev, "rem_slave_cqs: Could not move all cqs to "
  2467. "busy for slave %d\n", slave);
  2468. spin_lock_irq(mlx4_tlock(dev));
  2469. list_for_each_entry_safe(cq, tmp, cq_list, com.list) {
  2470. spin_unlock_irq(mlx4_tlock(dev));
  2471. if (cq->com.owner == slave && !atomic_read(&cq->ref_count)) {
  2472. cqn = cq->com.res_id;
  2473. state = cq->com.from_state;
  2474. while (state != 0) {
  2475. switch (state) {
  2476. case RES_CQ_ALLOCATED:
  2477. __mlx4_cq_free_icm(dev, cqn);
  2478. spin_lock_irq(mlx4_tlock(dev));
  2479. radix_tree_delete(&tracker->res_tree[RES_CQ],
  2480. cqn);
  2481. list_del(&cq->com.list);
  2482. spin_unlock_irq(mlx4_tlock(dev));
  2483. kfree(cq);
  2484. state = 0;
  2485. break;
  2486. case RES_CQ_HW:
  2487. in_param = slave;
  2488. err = mlx4_cmd(dev, in_param, cqn, 1,
  2489. MLX4_CMD_HW2SW_CQ,
  2490. MLX4_CMD_TIME_CLASS_A,
  2491. MLX4_CMD_NATIVE);
  2492. if (err)
  2493. mlx4_dbg(dev, "rem_slave_cqs: failed"
  2494. " to move slave %d cq %d to"
  2495. " SW ownership\n",
  2496. slave, cqn);
  2497. atomic_dec(&cq->mtt->ref_count);
  2498. state = RES_CQ_ALLOCATED;
  2499. break;
  2500. default:
  2501. state = 0;
  2502. }
  2503. }
  2504. }
  2505. spin_lock_irq(mlx4_tlock(dev));
  2506. }
  2507. spin_unlock_irq(mlx4_tlock(dev));
  2508. }
  2509. static void rem_slave_mrs(struct mlx4_dev *dev, int slave)
  2510. {
  2511. struct mlx4_priv *priv = mlx4_priv(dev);
  2512. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  2513. struct list_head *mpt_list =
  2514. &tracker->slave_list[slave].res_list[RES_MPT];
  2515. struct res_mpt *mpt;
  2516. struct res_mpt *tmp;
  2517. int state;
  2518. u64 in_param;
  2519. LIST_HEAD(tlist);
  2520. int mptn;
  2521. int err;
  2522. err = move_all_busy(dev, slave, RES_MPT);
  2523. if (err)
  2524. mlx4_warn(dev, "rem_slave_mrs: Could not move all mpts to "
  2525. "busy for slave %d\n", slave);
  2526. spin_lock_irq(mlx4_tlock(dev));
  2527. list_for_each_entry_safe(mpt, tmp, mpt_list, com.list) {
  2528. spin_unlock_irq(mlx4_tlock(dev));
  2529. if (mpt->com.owner == slave) {
  2530. mptn = mpt->com.res_id;
  2531. state = mpt->com.from_state;
  2532. while (state != 0) {
  2533. switch (state) {
  2534. case RES_MPT_RESERVED:
  2535. __mlx4_mr_release(dev, mpt->key);
  2536. spin_lock_irq(mlx4_tlock(dev));
  2537. radix_tree_delete(&tracker->res_tree[RES_MPT],
  2538. mptn);
  2539. list_del(&mpt->com.list);
  2540. spin_unlock_irq(mlx4_tlock(dev));
  2541. kfree(mpt);
  2542. state = 0;
  2543. break;
  2544. case RES_MPT_MAPPED:
  2545. __mlx4_mr_free_icm(dev, mpt->key);
  2546. state = RES_MPT_RESERVED;
  2547. break;
  2548. case RES_MPT_HW:
  2549. in_param = slave;
  2550. err = mlx4_cmd(dev, in_param, mptn, 0,
  2551. MLX4_CMD_HW2SW_MPT,
  2552. MLX4_CMD_TIME_CLASS_A,
  2553. MLX4_CMD_NATIVE);
  2554. if (err)
  2555. mlx4_dbg(dev, "rem_slave_mrs: failed"
  2556. " to move slave %d mpt %d to"
  2557. " SW ownership\n",
  2558. slave, mptn);
  2559. if (mpt->mtt)
  2560. atomic_dec(&mpt->mtt->ref_count);
  2561. state = RES_MPT_MAPPED;
  2562. break;
  2563. default:
  2564. state = 0;
  2565. }
  2566. }
  2567. }
  2568. spin_lock_irq(mlx4_tlock(dev));
  2569. }
  2570. spin_unlock_irq(mlx4_tlock(dev));
  2571. }
  2572. static void rem_slave_mtts(struct mlx4_dev *dev, int slave)
  2573. {
  2574. struct mlx4_priv *priv = mlx4_priv(dev);
  2575. struct mlx4_resource_tracker *tracker =
  2576. &priv->mfunc.master.res_tracker;
  2577. struct list_head *mtt_list =
  2578. &tracker->slave_list[slave].res_list[RES_MTT];
  2579. struct res_mtt *mtt;
  2580. struct res_mtt *tmp;
  2581. int state;
  2582. LIST_HEAD(tlist);
  2583. int base;
  2584. int err;
  2585. err = move_all_busy(dev, slave, RES_MTT);
  2586. if (err)
  2587. mlx4_warn(dev, "rem_slave_mtts: Could not move all mtts to "
  2588. "busy for slave %d\n", slave);
  2589. spin_lock_irq(mlx4_tlock(dev));
  2590. list_for_each_entry_safe(mtt, tmp, mtt_list, com.list) {
  2591. spin_unlock_irq(mlx4_tlock(dev));
  2592. if (mtt->com.owner == slave) {
  2593. base = mtt->com.res_id;
  2594. state = mtt->com.from_state;
  2595. while (state != 0) {
  2596. switch (state) {
  2597. case RES_MTT_ALLOCATED:
  2598. __mlx4_free_mtt_range(dev, base,
  2599. mtt->order);
  2600. spin_lock_irq(mlx4_tlock(dev));
  2601. radix_tree_delete(&tracker->res_tree[RES_MTT],
  2602. base);
  2603. list_del(&mtt->com.list);
  2604. spin_unlock_irq(mlx4_tlock(dev));
  2605. kfree(mtt);
  2606. state = 0;
  2607. break;
  2608. default:
  2609. state = 0;
  2610. }
  2611. }
  2612. }
  2613. spin_lock_irq(mlx4_tlock(dev));
  2614. }
  2615. spin_unlock_irq(mlx4_tlock(dev));
  2616. }
  2617. static void rem_slave_eqs(struct mlx4_dev *dev, int slave)
  2618. {
  2619. struct mlx4_priv *priv = mlx4_priv(dev);
  2620. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  2621. struct list_head *eq_list =
  2622. &tracker->slave_list[slave].res_list[RES_EQ];
  2623. struct res_eq *eq;
  2624. struct res_eq *tmp;
  2625. int err;
  2626. int state;
  2627. LIST_HEAD(tlist);
  2628. int eqn;
  2629. struct mlx4_cmd_mailbox *mailbox;
  2630. err = move_all_busy(dev, slave, RES_EQ);
  2631. if (err)
  2632. mlx4_warn(dev, "rem_slave_eqs: Could not move all eqs to "
  2633. "busy for slave %d\n", slave);
  2634. spin_lock_irq(mlx4_tlock(dev));
  2635. list_for_each_entry_safe(eq, tmp, eq_list, com.list) {
  2636. spin_unlock_irq(mlx4_tlock(dev));
  2637. if (eq->com.owner == slave) {
  2638. eqn = eq->com.res_id;
  2639. state = eq->com.from_state;
  2640. while (state != 0) {
  2641. switch (state) {
  2642. case RES_EQ_RESERVED:
  2643. spin_lock_irq(mlx4_tlock(dev));
  2644. radix_tree_delete(&tracker->res_tree[RES_EQ],
  2645. eqn);
  2646. list_del(&eq->com.list);
  2647. spin_unlock_irq(mlx4_tlock(dev));
  2648. kfree(eq);
  2649. state = 0;
  2650. break;
  2651. case RES_EQ_HW:
  2652. mailbox = mlx4_alloc_cmd_mailbox(dev);
  2653. if (IS_ERR(mailbox)) {
  2654. cond_resched();
  2655. continue;
  2656. }
  2657. err = mlx4_cmd_box(dev, slave, 0,
  2658. eqn & 0xff, 0,
  2659. MLX4_CMD_HW2SW_EQ,
  2660. MLX4_CMD_TIME_CLASS_A,
  2661. MLX4_CMD_NATIVE);
  2662. if (err)
  2663. mlx4_dbg(dev, "rem_slave_eqs: failed"
  2664. " to move slave %d eqs %d to"
  2665. " SW ownership\n", slave, eqn);
  2666. mlx4_free_cmd_mailbox(dev, mailbox);
  2667. atomic_dec(&eq->mtt->ref_count);
  2668. state = RES_EQ_RESERVED;
  2669. break;
  2670. default:
  2671. state = 0;
  2672. }
  2673. }
  2674. }
  2675. spin_lock_irq(mlx4_tlock(dev));
  2676. }
  2677. spin_unlock_irq(mlx4_tlock(dev));
  2678. }
  2679. static void rem_slave_counters(struct mlx4_dev *dev, int slave)
  2680. {
  2681. struct mlx4_priv *priv = mlx4_priv(dev);
  2682. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  2683. struct list_head *counter_list =
  2684. &tracker->slave_list[slave].res_list[RES_COUNTER];
  2685. struct res_counter *counter;
  2686. struct res_counter *tmp;
  2687. int err;
  2688. int index;
  2689. err = move_all_busy(dev, slave, RES_COUNTER);
  2690. if (err)
  2691. mlx4_warn(dev, "rem_slave_counters: Could not move all counters to "
  2692. "busy for slave %d\n", slave);
  2693. spin_lock_irq(mlx4_tlock(dev));
  2694. list_for_each_entry_safe(counter, tmp, counter_list, com.list) {
  2695. if (counter->com.owner == slave) {
  2696. index = counter->com.res_id;
  2697. radix_tree_delete(&tracker->res_tree[RES_COUNTER], index);
  2698. list_del(&counter->com.list);
  2699. kfree(counter);
  2700. __mlx4_counter_free(dev, index);
  2701. }
  2702. }
  2703. spin_unlock_irq(mlx4_tlock(dev));
  2704. }
  2705. static void rem_slave_xrcdns(struct mlx4_dev *dev, int slave)
  2706. {
  2707. struct mlx4_priv *priv = mlx4_priv(dev);
  2708. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  2709. struct list_head *xrcdn_list =
  2710. &tracker->slave_list[slave].res_list[RES_XRCD];
  2711. struct res_xrcdn *xrcd;
  2712. struct res_xrcdn *tmp;
  2713. int err;
  2714. int xrcdn;
  2715. err = move_all_busy(dev, slave, RES_XRCD);
  2716. if (err)
  2717. mlx4_warn(dev, "rem_slave_xrcdns: Could not move all xrcdns to "
  2718. "busy for slave %d\n", slave);
  2719. spin_lock_irq(mlx4_tlock(dev));
  2720. list_for_each_entry_safe(xrcd, tmp, xrcdn_list, com.list) {
  2721. if (xrcd->com.owner == slave) {
  2722. xrcdn = xrcd->com.res_id;
  2723. radix_tree_delete(&tracker->res_tree[RES_XRCD], xrcdn);
  2724. list_del(&xrcd->com.list);
  2725. kfree(xrcd);
  2726. __mlx4_xrcd_free(dev, xrcdn);
  2727. }
  2728. }
  2729. spin_unlock_irq(mlx4_tlock(dev));
  2730. }
  2731. void mlx4_delete_all_resources_for_slave(struct mlx4_dev *dev, int slave)
  2732. {
  2733. struct mlx4_priv *priv = mlx4_priv(dev);
  2734. mutex_lock(&priv->mfunc.master.res_tracker.slave_list[slave].mutex);
  2735. /*VLAN*/
  2736. rem_slave_macs(dev, slave);
  2737. rem_slave_qps(dev, slave);
  2738. rem_slave_srqs(dev, slave);
  2739. rem_slave_cqs(dev, slave);
  2740. rem_slave_mrs(dev, slave);
  2741. rem_slave_eqs(dev, slave);
  2742. rem_slave_mtts(dev, slave);
  2743. rem_slave_counters(dev, slave);
  2744. rem_slave_xrcdns(dev, slave);
  2745. mutex_unlock(&priv->mfunc.master.res_tracker.slave_list[slave].mutex);
  2746. }