atl1c_main.c 76 KB

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  1. /*
  2. * Copyright(c) 2008 - 2009 Atheros Corporation. All rights reserved.
  3. *
  4. * Derived from Intel e1000 driver
  5. * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License as published by the Free
  9. * Software Foundation; either version 2 of the License, or (at your option)
  10. * any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15. * more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along with
  18. * this program; if not, write to the Free Software Foundation, Inc., 59
  19. * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  20. */
  21. #include "atl1c.h"
  22. #define ATL1C_DRV_VERSION "1.0.1.0-NAPI"
  23. char atl1c_driver_name[] = "atl1c";
  24. char atl1c_driver_version[] = ATL1C_DRV_VERSION;
  25. /*
  26. * atl1c_pci_tbl - PCI Device ID Table
  27. *
  28. * Wildcard entries (PCI_ANY_ID) should come last
  29. * Last entry must be all 0s
  30. *
  31. * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
  32. * Class, Class Mask, private data (not used) }
  33. */
  34. static DEFINE_PCI_DEVICE_TABLE(atl1c_pci_tbl) = {
  35. {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATTANSIC_L1C)},
  36. {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATTANSIC_L2C)},
  37. {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATHEROS_L2C_B)},
  38. {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATHEROS_L2C_B2)},
  39. {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATHEROS_L1D)},
  40. {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATHEROS_L1D_2_0)},
  41. /* required last entry */
  42. { 0 }
  43. };
  44. MODULE_DEVICE_TABLE(pci, atl1c_pci_tbl);
  45. MODULE_AUTHOR("Jie Yang");
  46. MODULE_AUTHOR("Qualcomm Atheros Inc., <nic-devel@qualcomm.com>");
  47. MODULE_DESCRIPTION("Qualcom Atheros 100/1000M Ethernet Network Driver");
  48. MODULE_LICENSE("GPL");
  49. MODULE_VERSION(ATL1C_DRV_VERSION);
  50. static int atl1c_stop_mac(struct atl1c_hw *hw);
  51. static void atl1c_disable_l0s_l1(struct atl1c_hw *hw);
  52. static void atl1c_set_aspm(struct atl1c_hw *hw, u16 link_speed);
  53. static void atl1c_start_mac(struct atl1c_adapter *adapter);
  54. static void atl1c_clean_rx_irq(struct atl1c_adapter *adapter,
  55. int *work_done, int work_to_do);
  56. static int atl1c_up(struct atl1c_adapter *adapter);
  57. static void atl1c_down(struct atl1c_adapter *adapter);
  58. static int atl1c_reset_mac(struct atl1c_hw *hw);
  59. static void atl1c_reset_dma_ring(struct atl1c_adapter *adapter);
  60. static int atl1c_configure(struct atl1c_adapter *adapter);
  61. static int atl1c_alloc_rx_buffer(struct atl1c_adapter *adapter);
  62. static const u16 atl1c_pay_load_size[] = {
  63. 128, 256, 512, 1024, 2048, 4096,
  64. };
  65. static const u32 atl1c_default_msg = NETIF_MSG_DRV | NETIF_MSG_PROBE |
  66. NETIF_MSG_LINK | NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP;
  67. static void atl1c_pcie_patch(struct atl1c_hw *hw)
  68. {
  69. u32 mst_data, data;
  70. /* pclk sel could switch to 25M */
  71. AT_READ_REG(hw, REG_MASTER_CTRL, &mst_data);
  72. mst_data &= ~MASTER_CTRL_CLK_SEL_DIS;
  73. AT_WRITE_REG(hw, REG_MASTER_CTRL, mst_data);
  74. /* WoL/PCIE related settings */
  75. if (hw->nic_type == athr_l1c || hw->nic_type == athr_l2c) {
  76. AT_READ_REG(hw, REG_PCIE_PHYMISC, &data);
  77. data |= PCIE_PHYMISC_FORCE_RCV_DET;
  78. AT_WRITE_REG(hw, REG_PCIE_PHYMISC, data);
  79. } else { /* new dev set bit5 of MASTER */
  80. if (!(mst_data & MASTER_CTRL_WAKEN_25M))
  81. AT_WRITE_REG(hw, REG_MASTER_CTRL,
  82. mst_data | MASTER_CTRL_WAKEN_25M);
  83. }
  84. /* aspm/PCIE setting only for l2cb 1.0 */
  85. if (hw->nic_type == athr_l2c_b && hw->revision_id == L2CB_V10) {
  86. AT_READ_REG(hw, REG_PCIE_PHYMISC2, &data);
  87. data = FIELD_SETX(data, PCIE_PHYMISC2_CDR_BW,
  88. L2CB1_PCIE_PHYMISC2_CDR_BW);
  89. data = FIELD_SETX(data, PCIE_PHYMISC2_L0S_TH,
  90. L2CB1_PCIE_PHYMISC2_L0S_TH);
  91. AT_WRITE_REG(hw, REG_PCIE_PHYMISC2, data);
  92. /* extend L1 sync timer */
  93. AT_READ_REG(hw, REG_LINK_CTRL, &data);
  94. data |= LINK_CTRL_EXT_SYNC;
  95. AT_WRITE_REG(hw, REG_LINK_CTRL, data);
  96. }
  97. /* l2cb 1.x & l1d 1.x */
  98. if (hw->nic_type == athr_l2c_b || hw->nic_type == athr_l1d) {
  99. AT_READ_REG(hw, REG_PM_CTRL, &data);
  100. data |= PM_CTRL_L0S_BUFSRX_EN;
  101. AT_WRITE_REG(hw, REG_PM_CTRL, data);
  102. /* clear vendor msg */
  103. AT_READ_REG(hw, REG_DMA_DBG, &data);
  104. AT_WRITE_REG(hw, REG_DMA_DBG, data & ~DMA_DBG_VENDOR_MSG);
  105. }
  106. }
  107. /* FIXME: no need any more ? */
  108. /*
  109. * atl1c_init_pcie - init PCIE module
  110. */
  111. static void atl1c_reset_pcie(struct atl1c_hw *hw, u32 flag)
  112. {
  113. u32 data;
  114. u32 pci_cmd;
  115. struct pci_dev *pdev = hw->adapter->pdev;
  116. int pos;
  117. AT_READ_REG(hw, PCI_COMMAND, &pci_cmd);
  118. pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
  119. pci_cmd |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
  120. PCI_COMMAND_IO);
  121. AT_WRITE_REG(hw, PCI_COMMAND, pci_cmd);
  122. /*
  123. * Clear any PowerSaveing Settings
  124. */
  125. pci_enable_wake(pdev, PCI_D3hot, 0);
  126. pci_enable_wake(pdev, PCI_D3cold, 0);
  127. /* wol sts read-clear */
  128. AT_READ_REG(hw, REG_WOL_CTRL, &data);
  129. AT_WRITE_REG(hw, REG_WOL_CTRL, 0);
  130. /*
  131. * Mask some pcie error bits
  132. */
  133. pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR);
  134. pci_read_config_dword(pdev, pos + PCI_ERR_UNCOR_SEVER, &data);
  135. data &= ~(PCI_ERR_UNC_DLP | PCI_ERR_UNC_FCP);
  136. pci_write_config_dword(pdev, pos + PCI_ERR_UNCOR_SEVER, data);
  137. /* clear error status */
  138. pci_write_config_word(pdev, pci_pcie_cap(pdev) + PCI_EXP_DEVSTA,
  139. PCI_EXP_DEVSTA_NFED |
  140. PCI_EXP_DEVSTA_FED |
  141. PCI_EXP_DEVSTA_CED |
  142. PCI_EXP_DEVSTA_URD);
  143. AT_READ_REG(hw, REG_LTSSM_ID_CTRL, &data);
  144. data &= ~LTSSM_ID_EN_WRO;
  145. AT_WRITE_REG(hw, REG_LTSSM_ID_CTRL, data);
  146. atl1c_pcie_patch(hw);
  147. if (flag & ATL1C_PCIE_L0S_L1_DISABLE)
  148. atl1c_disable_l0s_l1(hw);
  149. msleep(5);
  150. }
  151. /*
  152. * atl1c_irq_enable - Enable default interrupt generation settings
  153. * @adapter: board private structure
  154. */
  155. static inline void atl1c_irq_enable(struct atl1c_adapter *adapter)
  156. {
  157. if (likely(atomic_dec_and_test(&adapter->irq_sem))) {
  158. AT_WRITE_REG(&adapter->hw, REG_ISR, 0x7FFFFFFF);
  159. AT_WRITE_REG(&adapter->hw, REG_IMR, adapter->hw.intr_mask);
  160. AT_WRITE_FLUSH(&adapter->hw);
  161. }
  162. }
  163. /*
  164. * atl1c_irq_disable - Mask off interrupt generation on the NIC
  165. * @adapter: board private structure
  166. */
  167. static inline void atl1c_irq_disable(struct atl1c_adapter *adapter)
  168. {
  169. atomic_inc(&adapter->irq_sem);
  170. AT_WRITE_REG(&adapter->hw, REG_IMR, 0);
  171. AT_WRITE_REG(&adapter->hw, REG_ISR, ISR_DIS_INT);
  172. AT_WRITE_FLUSH(&adapter->hw);
  173. synchronize_irq(adapter->pdev->irq);
  174. }
  175. /*
  176. * atl1c_irq_reset - reset interrupt confiure on the NIC
  177. * @adapter: board private structure
  178. */
  179. static inline void atl1c_irq_reset(struct atl1c_adapter *adapter)
  180. {
  181. atomic_set(&adapter->irq_sem, 1);
  182. atl1c_irq_enable(adapter);
  183. }
  184. /*
  185. * atl1c_wait_until_idle - wait up to AT_HW_MAX_IDLE_DELAY reads
  186. * of the idle status register until the device is actually idle
  187. */
  188. static u32 atl1c_wait_until_idle(struct atl1c_hw *hw, u32 modu_ctrl)
  189. {
  190. int timeout;
  191. u32 data;
  192. for (timeout = 0; timeout < AT_HW_MAX_IDLE_DELAY; timeout++) {
  193. AT_READ_REG(hw, REG_IDLE_STATUS, &data);
  194. if ((data & modu_ctrl) == 0)
  195. return 0;
  196. msleep(1);
  197. }
  198. return data;
  199. }
  200. /*
  201. * atl1c_phy_config - Timer Call-back
  202. * @data: pointer to netdev cast into an unsigned long
  203. */
  204. static void atl1c_phy_config(unsigned long data)
  205. {
  206. struct atl1c_adapter *adapter = (struct atl1c_adapter *) data;
  207. struct atl1c_hw *hw = &adapter->hw;
  208. unsigned long flags;
  209. spin_lock_irqsave(&adapter->mdio_lock, flags);
  210. atl1c_restart_autoneg(hw);
  211. spin_unlock_irqrestore(&adapter->mdio_lock, flags);
  212. }
  213. void atl1c_reinit_locked(struct atl1c_adapter *adapter)
  214. {
  215. WARN_ON(in_interrupt());
  216. atl1c_down(adapter);
  217. atl1c_up(adapter);
  218. clear_bit(__AT_RESETTING, &adapter->flags);
  219. }
  220. static void atl1c_check_link_status(struct atl1c_adapter *adapter)
  221. {
  222. struct atl1c_hw *hw = &adapter->hw;
  223. struct net_device *netdev = adapter->netdev;
  224. struct pci_dev *pdev = adapter->pdev;
  225. int err;
  226. unsigned long flags;
  227. u16 speed, duplex, phy_data;
  228. spin_lock_irqsave(&adapter->mdio_lock, flags);
  229. /* MII_BMSR must read twise */
  230. atl1c_read_phy_reg(hw, MII_BMSR, &phy_data);
  231. atl1c_read_phy_reg(hw, MII_BMSR, &phy_data);
  232. spin_unlock_irqrestore(&adapter->mdio_lock, flags);
  233. if ((phy_data & BMSR_LSTATUS) == 0) {
  234. /* link down */
  235. netif_carrier_off(netdev);
  236. netif_stop_queue(netdev);
  237. hw->hibernate = true;
  238. if (atl1c_reset_mac(hw) != 0)
  239. if (netif_msg_hw(adapter))
  240. dev_warn(&pdev->dev, "reset mac failed\n");
  241. atl1c_set_aspm(hw, SPEED_0);
  242. atl1c_post_phy_linkchg(hw, SPEED_0);
  243. atl1c_reset_dma_ring(adapter);
  244. atl1c_configure(adapter);
  245. } else {
  246. /* Link Up */
  247. hw->hibernate = false;
  248. spin_lock_irqsave(&adapter->mdio_lock, flags);
  249. err = atl1c_get_speed_and_duplex(hw, &speed, &duplex);
  250. spin_unlock_irqrestore(&adapter->mdio_lock, flags);
  251. if (unlikely(err))
  252. return;
  253. /* link result is our setting */
  254. if (adapter->link_speed != speed ||
  255. adapter->link_duplex != duplex) {
  256. adapter->link_speed = speed;
  257. adapter->link_duplex = duplex;
  258. atl1c_set_aspm(hw, speed);
  259. atl1c_post_phy_linkchg(hw, speed);
  260. atl1c_start_mac(adapter);
  261. if (netif_msg_link(adapter))
  262. dev_info(&pdev->dev,
  263. "%s: %s NIC Link is Up<%d Mbps %s>\n",
  264. atl1c_driver_name, netdev->name,
  265. adapter->link_speed,
  266. adapter->link_duplex == FULL_DUPLEX ?
  267. "Full Duplex" : "Half Duplex");
  268. }
  269. if (!netif_carrier_ok(netdev))
  270. netif_carrier_on(netdev);
  271. }
  272. }
  273. static void atl1c_link_chg_event(struct atl1c_adapter *adapter)
  274. {
  275. struct net_device *netdev = adapter->netdev;
  276. struct pci_dev *pdev = adapter->pdev;
  277. u16 phy_data;
  278. u16 link_up;
  279. spin_lock(&adapter->mdio_lock);
  280. atl1c_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
  281. atl1c_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
  282. spin_unlock(&adapter->mdio_lock);
  283. link_up = phy_data & BMSR_LSTATUS;
  284. /* notify upper layer link down ASAP */
  285. if (!link_up) {
  286. if (netif_carrier_ok(netdev)) {
  287. /* old link state: Up */
  288. netif_carrier_off(netdev);
  289. if (netif_msg_link(adapter))
  290. dev_info(&pdev->dev,
  291. "%s: %s NIC Link is Down\n",
  292. atl1c_driver_name, netdev->name);
  293. adapter->link_speed = SPEED_0;
  294. }
  295. }
  296. set_bit(ATL1C_WORK_EVENT_LINK_CHANGE, &adapter->work_event);
  297. schedule_work(&adapter->common_task);
  298. }
  299. static void atl1c_common_task(struct work_struct *work)
  300. {
  301. struct atl1c_adapter *adapter;
  302. struct net_device *netdev;
  303. adapter = container_of(work, struct atl1c_adapter, common_task);
  304. netdev = adapter->netdev;
  305. if (test_bit(__AT_DOWN, &adapter->flags))
  306. return;
  307. if (test_and_clear_bit(ATL1C_WORK_EVENT_RESET, &adapter->work_event)) {
  308. netif_device_detach(netdev);
  309. atl1c_down(adapter);
  310. atl1c_up(adapter);
  311. netif_device_attach(netdev);
  312. }
  313. if (test_and_clear_bit(ATL1C_WORK_EVENT_LINK_CHANGE,
  314. &adapter->work_event)) {
  315. atl1c_irq_disable(adapter);
  316. atl1c_check_link_status(adapter);
  317. atl1c_irq_enable(adapter);
  318. }
  319. }
  320. static void atl1c_del_timer(struct atl1c_adapter *adapter)
  321. {
  322. del_timer_sync(&adapter->phy_config_timer);
  323. }
  324. /*
  325. * atl1c_tx_timeout - Respond to a Tx Hang
  326. * @netdev: network interface device structure
  327. */
  328. static void atl1c_tx_timeout(struct net_device *netdev)
  329. {
  330. struct atl1c_adapter *adapter = netdev_priv(netdev);
  331. /* Do the reset outside of interrupt context */
  332. set_bit(ATL1C_WORK_EVENT_RESET, &adapter->work_event);
  333. schedule_work(&adapter->common_task);
  334. }
  335. /*
  336. * atl1c_set_multi - Multicast and Promiscuous mode set
  337. * @netdev: network interface device structure
  338. *
  339. * The set_multi entry point is called whenever the multicast address
  340. * list or the network interface flags are updated. This routine is
  341. * responsible for configuring the hardware for proper multicast,
  342. * promiscuous mode, and all-multi behavior.
  343. */
  344. static void atl1c_set_multi(struct net_device *netdev)
  345. {
  346. struct atl1c_adapter *adapter = netdev_priv(netdev);
  347. struct atl1c_hw *hw = &adapter->hw;
  348. struct netdev_hw_addr *ha;
  349. u32 mac_ctrl_data;
  350. u32 hash_value;
  351. /* Check for Promiscuous and All Multicast modes */
  352. AT_READ_REG(hw, REG_MAC_CTRL, &mac_ctrl_data);
  353. if (netdev->flags & IFF_PROMISC) {
  354. mac_ctrl_data |= MAC_CTRL_PROMIS_EN;
  355. } else if (netdev->flags & IFF_ALLMULTI) {
  356. mac_ctrl_data |= MAC_CTRL_MC_ALL_EN;
  357. mac_ctrl_data &= ~MAC_CTRL_PROMIS_EN;
  358. } else {
  359. mac_ctrl_data &= ~(MAC_CTRL_PROMIS_EN | MAC_CTRL_MC_ALL_EN);
  360. }
  361. AT_WRITE_REG(hw, REG_MAC_CTRL, mac_ctrl_data);
  362. /* clear the old settings from the multicast hash table */
  363. AT_WRITE_REG(hw, REG_RX_HASH_TABLE, 0);
  364. AT_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0);
  365. /* comoute mc addresses' hash value ,and put it into hash table */
  366. netdev_for_each_mc_addr(ha, netdev) {
  367. hash_value = atl1c_hash_mc_addr(hw, ha->addr);
  368. atl1c_hash_set(hw, hash_value);
  369. }
  370. }
  371. static void __atl1c_vlan_mode(netdev_features_t features, u32 *mac_ctrl_data)
  372. {
  373. if (features & NETIF_F_HW_VLAN_RX) {
  374. /* enable VLAN tag insert/strip */
  375. *mac_ctrl_data |= MAC_CTRL_RMV_VLAN;
  376. } else {
  377. /* disable VLAN tag insert/strip */
  378. *mac_ctrl_data &= ~MAC_CTRL_RMV_VLAN;
  379. }
  380. }
  381. static void atl1c_vlan_mode(struct net_device *netdev,
  382. netdev_features_t features)
  383. {
  384. struct atl1c_adapter *adapter = netdev_priv(netdev);
  385. struct pci_dev *pdev = adapter->pdev;
  386. u32 mac_ctrl_data = 0;
  387. if (netif_msg_pktdata(adapter))
  388. dev_dbg(&pdev->dev, "atl1c_vlan_mode\n");
  389. atl1c_irq_disable(adapter);
  390. AT_READ_REG(&adapter->hw, REG_MAC_CTRL, &mac_ctrl_data);
  391. __atl1c_vlan_mode(features, &mac_ctrl_data);
  392. AT_WRITE_REG(&adapter->hw, REG_MAC_CTRL, mac_ctrl_data);
  393. atl1c_irq_enable(adapter);
  394. }
  395. static void atl1c_restore_vlan(struct atl1c_adapter *adapter)
  396. {
  397. struct pci_dev *pdev = adapter->pdev;
  398. if (netif_msg_pktdata(adapter))
  399. dev_dbg(&pdev->dev, "atl1c_restore_vlan\n");
  400. atl1c_vlan_mode(adapter->netdev, adapter->netdev->features);
  401. }
  402. /*
  403. * atl1c_set_mac - Change the Ethernet Address of the NIC
  404. * @netdev: network interface device structure
  405. * @p: pointer to an address structure
  406. *
  407. * Returns 0 on success, negative on failure
  408. */
  409. static int atl1c_set_mac_addr(struct net_device *netdev, void *p)
  410. {
  411. struct atl1c_adapter *adapter = netdev_priv(netdev);
  412. struct sockaddr *addr = p;
  413. if (!is_valid_ether_addr(addr->sa_data))
  414. return -EADDRNOTAVAIL;
  415. if (netif_running(netdev))
  416. return -EBUSY;
  417. memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
  418. memcpy(adapter->hw.mac_addr, addr->sa_data, netdev->addr_len);
  419. netdev->addr_assign_type &= ~NET_ADDR_RANDOM;
  420. atl1c_hw_set_mac_addr(&adapter->hw, adapter->hw.mac_addr);
  421. return 0;
  422. }
  423. static void atl1c_set_rxbufsize(struct atl1c_adapter *adapter,
  424. struct net_device *dev)
  425. {
  426. int mtu = dev->mtu;
  427. adapter->rx_buffer_len = mtu > AT_RX_BUF_SIZE ?
  428. roundup(mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN, 8) : AT_RX_BUF_SIZE;
  429. }
  430. static netdev_features_t atl1c_fix_features(struct net_device *netdev,
  431. netdev_features_t features)
  432. {
  433. /*
  434. * Since there is no support for separate rx/tx vlan accel
  435. * enable/disable make sure tx flag is always in same state as rx.
  436. */
  437. if (features & NETIF_F_HW_VLAN_RX)
  438. features |= NETIF_F_HW_VLAN_TX;
  439. else
  440. features &= ~NETIF_F_HW_VLAN_TX;
  441. if (netdev->mtu > MAX_TSO_FRAME_SIZE)
  442. features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
  443. return features;
  444. }
  445. static int atl1c_set_features(struct net_device *netdev,
  446. netdev_features_t features)
  447. {
  448. netdev_features_t changed = netdev->features ^ features;
  449. if (changed & NETIF_F_HW_VLAN_RX)
  450. atl1c_vlan_mode(netdev, features);
  451. return 0;
  452. }
  453. /*
  454. * atl1c_change_mtu - Change the Maximum Transfer Unit
  455. * @netdev: network interface device structure
  456. * @new_mtu: new value for maximum frame size
  457. *
  458. * Returns 0 on success, negative on failure
  459. */
  460. static int atl1c_change_mtu(struct net_device *netdev, int new_mtu)
  461. {
  462. struct atl1c_adapter *adapter = netdev_priv(netdev);
  463. struct atl1c_hw *hw = &adapter->hw;
  464. int old_mtu = netdev->mtu;
  465. int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
  466. /* Fast Ethernet controller doesn't support jumbo packet */
  467. if (((hw->nic_type == athr_l2c ||
  468. hw->nic_type == athr_l2c_b ||
  469. hw->nic_type == athr_l2c_b2) && new_mtu > ETH_DATA_LEN) ||
  470. max_frame < ETH_ZLEN + ETH_FCS_LEN ||
  471. max_frame > MAX_JUMBO_FRAME_SIZE) {
  472. if (netif_msg_link(adapter))
  473. dev_warn(&adapter->pdev->dev, "invalid MTU setting\n");
  474. return -EINVAL;
  475. }
  476. /* set MTU */
  477. if (old_mtu != new_mtu && netif_running(netdev)) {
  478. while (test_and_set_bit(__AT_RESETTING, &adapter->flags))
  479. msleep(1);
  480. netdev->mtu = new_mtu;
  481. adapter->hw.max_frame_size = new_mtu;
  482. atl1c_set_rxbufsize(adapter, netdev);
  483. atl1c_down(adapter);
  484. netdev_update_features(netdev);
  485. atl1c_up(adapter);
  486. clear_bit(__AT_RESETTING, &adapter->flags);
  487. }
  488. return 0;
  489. }
  490. /*
  491. * caller should hold mdio_lock
  492. */
  493. static int atl1c_mdio_read(struct net_device *netdev, int phy_id, int reg_num)
  494. {
  495. struct atl1c_adapter *adapter = netdev_priv(netdev);
  496. u16 result;
  497. atl1c_read_phy_reg(&adapter->hw, reg_num, &result);
  498. return result;
  499. }
  500. static void atl1c_mdio_write(struct net_device *netdev, int phy_id,
  501. int reg_num, int val)
  502. {
  503. struct atl1c_adapter *adapter = netdev_priv(netdev);
  504. atl1c_write_phy_reg(&adapter->hw, reg_num, val);
  505. }
  506. /*
  507. * atl1c_mii_ioctl -
  508. * @netdev:
  509. * @ifreq:
  510. * @cmd:
  511. */
  512. static int atl1c_mii_ioctl(struct net_device *netdev,
  513. struct ifreq *ifr, int cmd)
  514. {
  515. struct atl1c_adapter *adapter = netdev_priv(netdev);
  516. struct pci_dev *pdev = adapter->pdev;
  517. struct mii_ioctl_data *data = if_mii(ifr);
  518. unsigned long flags;
  519. int retval = 0;
  520. if (!netif_running(netdev))
  521. return -EINVAL;
  522. spin_lock_irqsave(&adapter->mdio_lock, flags);
  523. switch (cmd) {
  524. case SIOCGMIIPHY:
  525. data->phy_id = 0;
  526. break;
  527. case SIOCGMIIREG:
  528. if (atl1c_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
  529. &data->val_out)) {
  530. retval = -EIO;
  531. goto out;
  532. }
  533. break;
  534. case SIOCSMIIREG:
  535. if (data->reg_num & ~(0x1F)) {
  536. retval = -EFAULT;
  537. goto out;
  538. }
  539. dev_dbg(&pdev->dev, "<atl1c_mii_ioctl> write %x %x",
  540. data->reg_num, data->val_in);
  541. if (atl1c_write_phy_reg(&adapter->hw,
  542. data->reg_num, data->val_in)) {
  543. retval = -EIO;
  544. goto out;
  545. }
  546. break;
  547. default:
  548. retval = -EOPNOTSUPP;
  549. break;
  550. }
  551. out:
  552. spin_unlock_irqrestore(&adapter->mdio_lock, flags);
  553. return retval;
  554. }
  555. /*
  556. * atl1c_ioctl -
  557. * @netdev:
  558. * @ifreq:
  559. * @cmd:
  560. */
  561. static int atl1c_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
  562. {
  563. switch (cmd) {
  564. case SIOCGMIIPHY:
  565. case SIOCGMIIREG:
  566. case SIOCSMIIREG:
  567. return atl1c_mii_ioctl(netdev, ifr, cmd);
  568. default:
  569. return -EOPNOTSUPP;
  570. }
  571. }
  572. /*
  573. * atl1c_alloc_queues - Allocate memory for all rings
  574. * @adapter: board private structure to initialize
  575. *
  576. */
  577. static int __devinit atl1c_alloc_queues(struct atl1c_adapter *adapter)
  578. {
  579. return 0;
  580. }
  581. static void atl1c_set_mac_type(struct atl1c_hw *hw)
  582. {
  583. switch (hw->device_id) {
  584. case PCI_DEVICE_ID_ATTANSIC_L2C:
  585. hw->nic_type = athr_l2c;
  586. break;
  587. case PCI_DEVICE_ID_ATTANSIC_L1C:
  588. hw->nic_type = athr_l1c;
  589. break;
  590. case PCI_DEVICE_ID_ATHEROS_L2C_B:
  591. hw->nic_type = athr_l2c_b;
  592. break;
  593. case PCI_DEVICE_ID_ATHEROS_L2C_B2:
  594. hw->nic_type = athr_l2c_b2;
  595. break;
  596. case PCI_DEVICE_ID_ATHEROS_L1D:
  597. hw->nic_type = athr_l1d;
  598. break;
  599. case PCI_DEVICE_ID_ATHEROS_L1D_2_0:
  600. hw->nic_type = athr_l1d_2;
  601. break;
  602. default:
  603. break;
  604. }
  605. }
  606. static int atl1c_setup_mac_funcs(struct atl1c_hw *hw)
  607. {
  608. u32 link_ctrl_data;
  609. atl1c_set_mac_type(hw);
  610. AT_READ_REG(hw, REG_LINK_CTRL, &link_ctrl_data);
  611. hw->ctrl_flags = ATL1C_INTR_MODRT_ENABLE |
  612. ATL1C_TXQ_MODE_ENHANCE;
  613. hw->ctrl_flags |= ATL1C_ASPM_L0S_SUPPORT |
  614. ATL1C_ASPM_L1_SUPPORT;
  615. hw->ctrl_flags |= ATL1C_ASPM_CTRL_MON;
  616. if (hw->nic_type == athr_l1c ||
  617. hw->nic_type == athr_l1d ||
  618. hw->nic_type == athr_l1d_2)
  619. hw->link_cap_flags |= ATL1C_LINK_CAP_1000M;
  620. return 0;
  621. }
  622. struct atl1c_platform_patch {
  623. u16 pci_did;
  624. u8 pci_revid;
  625. u16 subsystem_vid;
  626. u16 subsystem_did;
  627. u32 patch_flag;
  628. #define ATL1C_LINK_PATCH 0x1
  629. };
  630. static const struct atl1c_platform_patch plats[] __devinitdata = {
  631. {0x2060, 0xC1, 0x1019, 0x8152, 0x1},
  632. {0x2060, 0xC1, 0x1019, 0x2060, 0x1},
  633. {0x2060, 0xC1, 0x1019, 0xE000, 0x1},
  634. {0x2062, 0xC0, 0x1019, 0x8152, 0x1},
  635. {0x2062, 0xC0, 0x1019, 0x2062, 0x1},
  636. {0x2062, 0xC0, 0x1458, 0xE000, 0x1},
  637. {0x2062, 0xC1, 0x1019, 0x8152, 0x1},
  638. {0x2062, 0xC1, 0x1019, 0x2062, 0x1},
  639. {0x2062, 0xC1, 0x1458, 0xE000, 0x1},
  640. {0x2062, 0xC1, 0x1565, 0x2802, 0x1},
  641. {0x2062, 0xC1, 0x1565, 0x2801, 0x1},
  642. {0x1073, 0xC0, 0x1019, 0x8151, 0x1},
  643. {0x1073, 0xC0, 0x1019, 0x1073, 0x1},
  644. {0x1073, 0xC0, 0x1458, 0xE000, 0x1},
  645. {0x1083, 0xC0, 0x1458, 0xE000, 0x1},
  646. {0x1083, 0xC0, 0x1019, 0x8151, 0x1},
  647. {0x1083, 0xC0, 0x1019, 0x1083, 0x1},
  648. {0x1083, 0xC0, 0x1462, 0x7680, 0x1},
  649. {0x1083, 0xC0, 0x1565, 0x2803, 0x1},
  650. {0},
  651. };
  652. static void __devinit atl1c_patch_assign(struct atl1c_hw *hw)
  653. {
  654. int i = 0;
  655. hw->msi_lnkpatch = false;
  656. while (plats[i].pci_did != 0) {
  657. if (plats[i].pci_did == hw->device_id &&
  658. plats[i].pci_revid == hw->revision_id &&
  659. plats[i].subsystem_vid == hw->subsystem_vendor_id &&
  660. plats[i].subsystem_did == hw->subsystem_id) {
  661. if (plats[i].patch_flag & ATL1C_LINK_PATCH)
  662. hw->msi_lnkpatch = true;
  663. }
  664. i++;
  665. }
  666. }
  667. /*
  668. * atl1c_sw_init - Initialize general software structures (struct atl1c_adapter)
  669. * @adapter: board private structure to initialize
  670. *
  671. * atl1c_sw_init initializes the Adapter private data structure.
  672. * Fields are initialized based on PCI device information and
  673. * OS network device settings (MTU size).
  674. */
  675. static int __devinit atl1c_sw_init(struct atl1c_adapter *adapter)
  676. {
  677. struct atl1c_hw *hw = &adapter->hw;
  678. struct pci_dev *pdev = adapter->pdev;
  679. u32 revision;
  680. adapter->wol = 0;
  681. device_set_wakeup_enable(&pdev->dev, false);
  682. adapter->link_speed = SPEED_0;
  683. adapter->link_duplex = FULL_DUPLEX;
  684. adapter->tpd_ring[0].count = 1024;
  685. adapter->rfd_ring.count = 512;
  686. hw->vendor_id = pdev->vendor;
  687. hw->device_id = pdev->device;
  688. hw->subsystem_vendor_id = pdev->subsystem_vendor;
  689. hw->subsystem_id = pdev->subsystem_device;
  690. AT_READ_REG(hw, PCI_CLASS_REVISION, &revision);
  691. hw->revision_id = revision & 0xFF;
  692. /* before link up, we assume hibernate is true */
  693. hw->hibernate = true;
  694. hw->media_type = MEDIA_TYPE_AUTO_SENSOR;
  695. if (atl1c_setup_mac_funcs(hw) != 0) {
  696. dev_err(&pdev->dev, "set mac function pointers failed\n");
  697. return -1;
  698. }
  699. atl1c_patch_assign(hw);
  700. hw->intr_mask = IMR_NORMAL_MASK;
  701. hw->phy_configured = false;
  702. hw->preamble_len = 7;
  703. hw->max_frame_size = adapter->netdev->mtu;
  704. hw->autoneg_advertised = ADVERTISED_Autoneg;
  705. hw->indirect_tab = 0xE4E4E4E4;
  706. hw->base_cpu = 0;
  707. hw->ict = 50000; /* 100ms */
  708. hw->smb_timer = 200000; /* 400ms */
  709. hw->rx_imt = 200;
  710. hw->tx_imt = 1000;
  711. hw->tpd_burst = 5;
  712. hw->rfd_burst = 8;
  713. hw->dma_order = atl1c_dma_ord_out;
  714. hw->dmar_block = atl1c_dma_req_1024;
  715. if (atl1c_alloc_queues(adapter)) {
  716. dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
  717. return -ENOMEM;
  718. }
  719. /* TODO */
  720. atl1c_set_rxbufsize(adapter, adapter->netdev);
  721. atomic_set(&adapter->irq_sem, 1);
  722. spin_lock_init(&adapter->mdio_lock);
  723. spin_lock_init(&adapter->tx_lock);
  724. set_bit(__AT_DOWN, &adapter->flags);
  725. return 0;
  726. }
  727. static inline void atl1c_clean_buffer(struct pci_dev *pdev,
  728. struct atl1c_buffer *buffer_info, int in_irq)
  729. {
  730. u16 pci_driection;
  731. if (buffer_info->flags & ATL1C_BUFFER_FREE)
  732. return;
  733. if (buffer_info->dma) {
  734. if (buffer_info->flags & ATL1C_PCIMAP_FROMDEVICE)
  735. pci_driection = PCI_DMA_FROMDEVICE;
  736. else
  737. pci_driection = PCI_DMA_TODEVICE;
  738. if (buffer_info->flags & ATL1C_PCIMAP_SINGLE)
  739. pci_unmap_single(pdev, buffer_info->dma,
  740. buffer_info->length, pci_driection);
  741. else if (buffer_info->flags & ATL1C_PCIMAP_PAGE)
  742. pci_unmap_page(pdev, buffer_info->dma,
  743. buffer_info->length, pci_driection);
  744. }
  745. if (buffer_info->skb) {
  746. if (in_irq)
  747. dev_kfree_skb_irq(buffer_info->skb);
  748. else
  749. dev_kfree_skb(buffer_info->skb);
  750. }
  751. buffer_info->dma = 0;
  752. buffer_info->skb = NULL;
  753. ATL1C_SET_BUFFER_STATE(buffer_info, ATL1C_BUFFER_FREE);
  754. }
  755. /*
  756. * atl1c_clean_tx_ring - Free Tx-skb
  757. * @adapter: board private structure
  758. */
  759. static void atl1c_clean_tx_ring(struct atl1c_adapter *adapter,
  760. enum atl1c_trans_queue type)
  761. {
  762. struct atl1c_tpd_ring *tpd_ring = &adapter->tpd_ring[type];
  763. struct atl1c_buffer *buffer_info;
  764. struct pci_dev *pdev = adapter->pdev;
  765. u16 index, ring_count;
  766. ring_count = tpd_ring->count;
  767. for (index = 0; index < ring_count; index++) {
  768. buffer_info = &tpd_ring->buffer_info[index];
  769. atl1c_clean_buffer(pdev, buffer_info, 0);
  770. }
  771. /* Zero out Tx-buffers */
  772. memset(tpd_ring->desc, 0, sizeof(struct atl1c_tpd_desc) *
  773. ring_count);
  774. atomic_set(&tpd_ring->next_to_clean, 0);
  775. tpd_ring->next_to_use = 0;
  776. }
  777. /*
  778. * atl1c_clean_rx_ring - Free rx-reservation skbs
  779. * @adapter: board private structure
  780. */
  781. static void atl1c_clean_rx_ring(struct atl1c_adapter *adapter)
  782. {
  783. struct atl1c_rfd_ring *rfd_ring = &adapter->rfd_ring;
  784. struct atl1c_rrd_ring *rrd_ring = &adapter->rrd_ring;
  785. struct atl1c_buffer *buffer_info;
  786. struct pci_dev *pdev = adapter->pdev;
  787. int j;
  788. for (j = 0; j < rfd_ring->count; j++) {
  789. buffer_info = &rfd_ring->buffer_info[j];
  790. atl1c_clean_buffer(pdev, buffer_info, 0);
  791. }
  792. /* zero out the descriptor ring */
  793. memset(rfd_ring->desc, 0, rfd_ring->size);
  794. rfd_ring->next_to_clean = 0;
  795. rfd_ring->next_to_use = 0;
  796. rrd_ring->next_to_use = 0;
  797. rrd_ring->next_to_clean = 0;
  798. }
  799. /*
  800. * Read / Write Ptr Initialize:
  801. */
  802. static void atl1c_init_ring_ptrs(struct atl1c_adapter *adapter)
  803. {
  804. struct atl1c_tpd_ring *tpd_ring = adapter->tpd_ring;
  805. struct atl1c_rfd_ring *rfd_ring = &adapter->rfd_ring;
  806. struct atl1c_rrd_ring *rrd_ring = &adapter->rrd_ring;
  807. struct atl1c_buffer *buffer_info;
  808. int i, j;
  809. for (i = 0; i < AT_MAX_TRANSMIT_QUEUE; i++) {
  810. tpd_ring[i].next_to_use = 0;
  811. atomic_set(&tpd_ring[i].next_to_clean, 0);
  812. buffer_info = tpd_ring[i].buffer_info;
  813. for (j = 0; j < tpd_ring->count; j++)
  814. ATL1C_SET_BUFFER_STATE(&buffer_info[i],
  815. ATL1C_BUFFER_FREE);
  816. }
  817. rfd_ring->next_to_use = 0;
  818. rfd_ring->next_to_clean = 0;
  819. rrd_ring->next_to_use = 0;
  820. rrd_ring->next_to_clean = 0;
  821. for (j = 0; j < rfd_ring->count; j++) {
  822. buffer_info = &rfd_ring->buffer_info[j];
  823. ATL1C_SET_BUFFER_STATE(buffer_info, ATL1C_BUFFER_FREE);
  824. }
  825. }
  826. /*
  827. * atl1c_free_ring_resources - Free Tx / RX descriptor Resources
  828. * @adapter: board private structure
  829. *
  830. * Free all transmit software resources
  831. */
  832. static void atl1c_free_ring_resources(struct atl1c_adapter *adapter)
  833. {
  834. struct pci_dev *pdev = adapter->pdev;
  835. pci_free_consistent(pdev, adapter->ring_header.size,
  836. adapter->ring_header.desc,
  837. adapter->ring_header.dma);
  838. adapter->ring_header.desc = NULL;
  839. /* Note: just free tdp_ring.buffer_info,
  840. * it contain rfd_ring.buffer_info, do not double free */
  841. if (adapter->tpd_ring[0].buffer_info) {
  842. kfree(adapter->tpd_ring[0].buffer_info);
  843. adapter->tpd_ring[0].buffer_info = NULL;
  844. }
  845. }
  846. /*
  847. * atl1c_setup_mem_resources - allocate Tx / RX descriptor resources
  848. * @adapter: board private structure
  849. *
  850. * Return 0 on success, negative on failure
  851. */
  852. static int atl1c_setup_ring_resources(struct atl1c_adapter *adapter)
  853. {
  854. struct pci_dev *pdev = adapter->pdev;
  855. struct atl1c_tpd_ring *tpd_ring = adapter->tpd_ring;
  856. struct atl1c_rfd_ring *rfd_ring = &adapter->rfd_ring;
  857. struct atl1c_rrd_ring *rrd_ring = &adapter->rrd_ring;
  858. struct atl1c_ring_header *ring_header = &adapter->ring_header;
  859. int size;
  860. int i;
  861. int count = 0;
  862. int rx_desc_count = 0;
  863. u32 offset = 0;
  864. rrd_ring->count = rfd_ring->count;
  865. for (i = 1; i < AT_MAX_TRANSMIT_QUEUE; i++)
  866. tpd_ring[i].count = tpd_ring[0].count;
  867. /* 2 tpd queue, one high priority queue,
  868. * another normal priority queue */
  869. size = sizeof(struct atl1c_buffer) * (tpd_ring->count * 2 +
  870. rfd_ring->count);
  871. tpd_ring->buffer_info = kzalloc(size, GFP_KERNEL);
  872. if (unlikely(!tpd_ring->buffer_info)) {
  873. dev_err(&pdev->dev, "kzalloc failed, size = %d\n",
  874. size);
  875. goto err_nomem;
  876. }
  877. for (i = 0; i < AT_MAX_TRANSMIT_QUEUE; i++) {
  878. tpd_ring[i].buffer_info =
  879. (struct atl1c_buffer *) (tpd_ring->buffer_info + count);
  880. count += tpd_ring[i].count;
  881. }
  882. rfd_ring->buffer_info =
  883. (struct atl1c_buffer *) (tpd_ring->buffer_info + count);
  884. count += rfd_ring->count;
  885. rx_desc_count += rfd_ring->count;
  886. /*
  887. * real ring DMA buffer
  888. * each ring/block may need up to 8 bytes for alignment, hence the
  889. * additional bytes tacked onto the end.
  890. */
  891. ring_header->size = size =
  892. sizeof(struct atl1c_tpd_desc) * tpd_ring->count * 2 +
  893. sizeof(struct atl1c_rx_free_desc) * rx_desc_count +
  894. sizeof(struct atl1c_recv_ret_status) * rx_desc_count +
  895. 8 * 4;
  896. ring_header->desc = pci_alloc_consistent(pdev, ring_header->size,
  897. &ring_header->dma);
  898. if (unlikely(!ring_header->desc)) {
  899. dev_err(&pdev->dev, "pci_alloc_consistend failed\n");
  900. goto err_nomem;
  901. }
  902. memset(ring_header->desc, 0, ring_header->size);
  903. /* init TPD ring */
  904. tpd_ring[0].dma = roundup(ring_header->dma, 8);
  905. offset = tpd_ring[0].dma - ring_header->dma;
  906. for (i = 0; i < AT_MAX_TRANSMIT_QUEUE; i++) {
  907. tpd_ring[i].dma = ring_header->dma + offset;
  908. tpd_ring[i].desc = (u8 *) ring_header->desc + offset;
  909. tpd_ring[i].size =
  910. sizeof(struct atl1c_tpd_desc) * tpd_ring[i].count;
  911. offset += roundup(tpd_ring[i].size, 8);
  912. }
  913. /* init RFD ring */
  914. rfd_ring->dma = ring_header->dma + offset;
  915. rfd_ring->desc = (u8 *) ring_header->desc + offset;
  916. rfd_ring->size = sizeof(struct atl1c_rx_free_desc) * rfd_ring->count;
  917. offset += roundup(rfd_ring->size, 8);
  918. /* init RRD ring */
  919. rrd_ring->dma = ring_header->dma + offset;
  920. rrd_ring->desc = (u8 *) ring_header->desc + offset;
  921. rrd_ring->size = sizeof(struct atl1c_recv_ret_status) *
  922. rrd_ring->count;
  923. offset += roundup(rrd_ring->size, 8);
  924. return 0;
  925. err_nomem:
  926. kfree(tpd_ring->buffer_info);
  927. return -ENOMEM;
  928. }
  929. static void atl1c_configure_des_ring(struct atl1c_adapter *adapter)
  930. {
  931. struct atl1c_hw *hw = &adapter->hw;
  932. struct atl1c_rfd_ring *rfd_ring = &adapter->rfd_ring;
  933. struct atl1c_rrd_ring *rrd_ring = &adapter->rrd_ring;
  934. struct atl1c_tpd_ring *tpd_ring = (struct atl1c_tpd_ring *)
  935. adapter->tpd_ring;
  936. /* TPD */
  937. AT_WRITE_REG(hw, REG_TX_BASE_ADDR_HI,
  938. (u32)((tpd_ring[atl1c_trans_normal].dma &
  939. AT_DMA_HI_ADDR_MASK) >> 32));
  940. /* just enable normal priority TX queue */
  941. AT_WRITE_REG(hw, REG_TPD_PRI0_ADDR_LO,
  942. (u32)(tpd_ring[atl1c_trans_normal].dma &
  943. AT_DMA_LO_ADDR_MASK));
  944. AT_WRITE_REG(hw, REG_TPD_PRI1_ADDR_LO,
  945. (u32)(tpd_ring[atl1c_trans_high].dma &
  946. AT_DMA_LO_ADDR_MASK));
  947. AT_WRITE_REG(hw, REG_TPD_RING_SIZE,
  948. (u32)(tpd_ring[0].count & TPD_RING_SIZE_MASK));
  949. /* RFD */
  950. AT_WRITE_REG(hw, REG_RX_BASE_ADDR_HI,
  951. (u32)((rfd_ring->dma & AT_DMA_HI_ADDR_MASK) >> 32));
  952. AT_WRITE_REG(hw, REG_RFD0_HEAD_ADDR_LO,
  953. (u32)(rfd_ring->dma & AT_DMA_LO_ADDR_MASK));
  954. AT_WRITE_REG(hw, REG_RFD_RING_SIZE,
  955. rfd_ring->count & RFD_RING_SIZE_MASK);
  956. AT_WRITE_REG(hw, REG_RX_BUF_SIZE,
  957. adapter->rx_buffer_len & RX_BUF_SIZE_MASK);
  958. /* RRD */
  959. AT_WRITE_REG(hw, REG_RRD0_HEAD_ADDR_LO,
  960. (u32)(rrd_ring->dma & AT_DMA_LO_ADDR_MASK));
  961. AT_WRITE_REG(hw, REG_RRD_RING_SIZE,
  962. (rrd_ring->count & RRD_RING_SIZE_MASK));
  963. if (hw->nic_type == athr_l2c_b) {
  964. AT_WRITE_REG(hw, REG_SRAM_RXF_LEN, 0x02a0L);
  965. AT_WRITE_REG(hw, REG_SRAM_TXF_LEN, 0x0100L);
  966. AT_WRITE_REG(hw, REG_SRAM_RXF_ADDR, 0x029f0000L);
  967. AT_WRITE_REG(hw, REG_SRAM_RFD0_INFO, 0x02bf02a0L);
  968. AT_WRITE_REG(hw, REG_SRAM_TXF_ADDR, 0x03bf02c0L);
  969. AT_WRITE_REG(hw, REG_SRAM_TRD_ADDR, 0x03df03c0L);
  970. AT_WRITE_REG(hw, REG_TXF_WATER_MARK, 0); /* TX watermark, to enter l1 state.*/
  971. AT_WRITE_REG(hw, REG_RXD_DMA_CTRL, 0); /* RXD threshold.*/
  972. }
  973. /* Load all of base address above */
  974. AT_WRITE_REG(hw, REG_LOAD_PTR, 1);
  975. }
  976. static void atl1c_configure_tx(struct atl1c_adapter *adapter)
  977. {
  978. struct atl1c_hw *hw = &adapter->hw;
  979. int max_pay_load;
  980. u16 tx_offload_thresh;
  981. u32 txq_ctrl_data;
  982. tx_offload_thresh = MAX_TSO_FRAME_SIZE;
  983. AT_WRITE_REG(hw, REG_TX_TSO_OFFLOAD_THRESH,
  984. (tx_offload_thresh >> 3) & TX_TSO_OFFLOAD_THRESH_MASK);
  985. max_pay_load = pcie_get_readrq(adapter->pdev) >> 8;
  986. hw->dmar_block = min_t(u32, max_pay_load, hw->dmar_block);
  987. /*
  988. * if BIOS had changed the dam-read-max-length to an invalid value,
  989. * restore it to default value
  990. */
  991. if (hw->dmar_block < DEVICE_CTRL_MAXRRS_MIN) {
  992. pcie_set_readrq(adapter->pdev, 128 << DEVICE_CTRL_MAXRRS_MIN);
  993. hw->dmar_block = DEVICE_CTRL_MAXRRS_MIN;
  994. }
  995. txq_ctrl_data =
  996. hw->nic_type == athr_l2c_b || hw->nic_type == athr_l2c_b2 ?
  997. L2CB_TXQ_CFGV : L1C_TXQ_CFGV;
  998. AT_WRITE_REG(hw, REG_TXQ_CTRL, txq_ctrl_data);
  999. }
  1000. static void atl1c_configure_rx(struct atl1c_adapter *adapter)
  1001. {
  1002. struct atl1c_hw *hw = &adapter->hw;
  1003. u32 rxq_ctrl_data;
  1004. rxq_ctrl_data = (hw->rfd_burst & RXQ_RFD_BURST_NUM_MASK) <<
  1005. RXQ_RFD_BURST_NUM_SHIFT;
  1006. if (hw->ctrl_flags & ATL1C_RX_IPV6_CHKSUM)
  1007. rxq_ctrl_data |= IPV6_CHKSUM_CTRL_EN;
  1008. /* aspm for gigabit */
  1009. if (hw->nic_type != athr_l1d_2 && (hw->device_id & 1) != 0)
  1010. rxq_ctrl_data = FIELD_SETX(rxq_ctrl_data, ASPM_THRUPUT_LIMIT,
  1011. ASPM_THRUPUT_LIMIT_100M);
  1012. AT_WRITE_REG(hw, REG_RXQ_CTRL, rxq_ctrl_data);
  1013. }
  1014. static void atl1c_configure_dma(struct atl1c_adapter *adapter)
  1015. {
  1016. struct atl1c_hw *hw = &adapter->hw;
  1017. u32 dma_ctrl_data;
  1018. dma_ctrl_data = FIELDX(DMA_CTRL_RORDER_MODE, DMA_CTRL_RORDER_MODE_OUT) |
  1019. DMA_CTRL_RREQ_PRI_DATA |
  1020. FIELDX(DMA_CTRL_RREQ_BLEN, hw->dmar_block) |
  1021. FIELDX(DMA_CTRL_WDLY_CNT, DMA_CTRL_WDLY_CNT_DEF) |
  1022. FIELDX(DMA_CTRL_RDLY_CNT, DMA_CTRL_RDLY_CNT_DEF);
  1023. AT_WRITE_REG(hw, REG_DMA_CTRL, dma_ctrl_data);
  1024. }
  1025. /*
  1026. * Stop the mac, transmit and receive units
  1027. * hw - Struct containing variables accessed by shared code
  1028. * return : 0 or idle status (if error)
  1029. */
  1030. static int atl1c_stop_mac(struct atl1c_hw *hw)
  1031. {
  1032. u32 data;
  1033. AT_READ_REG(hw, REG_RXQ_CTRL, &data);
  1034. data &= ~RXQ_CTRL_EN;
  1035. AT_WRITE_REG(hw, REG_RXQ_CTRL, data);
  1036. AT_READ_REG(hw, REG_TXQ_CTRL, &data);
  1037. data &= ~TXQ_CTRL_EN;
  1038. AT_WRITE_REG(hw, REG_TXQ_CTRL, data);
  1039. atl1c_wait_until_idle(hw, IDLE_STATUS_RXQ_BUSY | IDLE_STATUS_TXQ_BUSY);
  1040. AT_READ_REG(hw, REG_MAC_CTRL, &data);
  1041. data &= ~(MAC_CTRL_TX_EN | MAC_CTRL_RX_EN);
  1042. AT_WRITE_REG(hw, REG_MAC_CTRL, data);
  1043. return (int)atl1c_wait_until_idle(hw,
  1044. IDLE_STATUS_TXMAC_BUSY | IDLE_STATUS_RXMAC_BUSY);
  1045. }
  1046. static void atl1c_start_mac(struct atl1c_adapter *adapter)
  1047. {
  1048. struct atl1c_hw *hw = &adapter->hw;
  1049. u32 mac, txq, rxq;
  1050. hw->mac_duplex = adapter->link_duplex == FULL_DUPLEX ? true : false;
  1051. hw->mac_speed = adapter->link_speed == SPEED_1000 ?
  1052. atl1c_mac_speed_1000 : atl1c_mac_speed_10_100;
  1053. AT_READ_REG(hw, REG_TXQ_CTRL, &txq);
  1054. AT_READ_REG(hw, REG_RXQ_CTRL, &rxq);
  1055. AT_READ_REG(hw, REG_MAC_CTRL, &mac);
  1056. txq |= TXQ_CTRL_EN;
  1057. rxq |= RXQ_CTRL_EN;
  1058. mac |= MAC_CTRL_TX_EN | MAC_CTRL_TX_FLOW |
  1059. MAC_CTRL_RX_EN | MAC_CTRL_RX_FLOW |
  1060. MAC_CTRL_ADD_CRC | MAC_CTRL_PAD |
  1061. MAC_CTRL_BC_EN | MAC_CTRL_SINGLE_PAUSE_EN |
  1062. MAC_CTRL_HASH_ALG_CRC32;
  1063. if (hw->mac_duplex)
  1064. mac |= MAC_CTRL_DUPLX;
  1065. else
  1066. mac &= ~MAC_CTRL_DUPLX;
  1067. mac = FIELD_SETX(mac, MAC_CTRL_SPEED, hw->mac_speed);
  1068. mac = FIELD_SETX(mac, MAC_CTRL_PRMLEN, hw->preamble_len);
  1069. AT_WRITE_REG(hw, REG_TXQ_CTRL, txq);
  1070. AT_WRITE_REG(hw, REG_RXQ_CTRL, rxq);
  1071. AT_WRITE_REG(hw, REG_MAC_CTRL, mac);
  1072. }
  1073. /*
  1074. * Reset the transmit and receive units; mask and clear all interrupts.
  1075. * hw - Struct containing variables accessed by shared code
  1076. * return : 0 or idle status (if error)
  1077. */
  1078. static int atl1c_reset_mac(struct atl1c_hw *hw)
  1079. {
  1080. struct atl1c_adapter *adapter = (struct atl1c_adapter *)hw->adapter;
  1081. struct pci_dev *pdev = adapter->pdev;
  1082. u32 ctrl_data = 0;
  1083. atl1c_stop_mac(hw);
  1084. /*
  1085. * Issue Soft Reset to the MAC. This will reset the chip's
  1086. * transmit, receive, DMA. It will not effect
  1087. * the current PCI configuration. The global reset bit is self-
  1088. * clearing, and should clear within a microsecond.
  1089. */
  1090. AT_READ_REG(hw, REG_MASTER_CTRL, &ctrl_data);
  1091. ctrl_data |= MASTER_CTRL_OOB_DIS;
  1092. AT_WRITE_REG(hw, REG_MASTER_CTRL, ctrl_data | MASTER_CTRL_SOFT_RST);
  1093. AT_WRITE_FLUSH(hw);
  1094. msleep(10);
  1095. /* Wait at least 10ms for All module to be Idle */
  1096. if (atl1c_wait_until_idle(hw, IDLE_STATUS_MASK)) {
  1097. dev_err(&pdev->dev,
  1098. "MAC state machine can't be idle since"
  1099. " disabled for 10ms second\n");
  1100. return -1;
  1101. }
  1102. AT_WRITE_REG(hw, REG_MASTER_CTRL, ctrl_data);
  1103. /* driver control speed/duplex */
  1104. AT_READ_REG(hw, REG_MAC_CTRL, &ctrl_data);
  1105. AT_WRITE_REG(hw, REG_MAC_CTRL, ctrl_data | MAC_CTRL_SPEED_MODE_SW);
  1106. /* clk switch setting */
  1107. AT_READ_REG(hw, REG_SERDES, &ctrl_data);
  1108. switch (hw->nic_type) {
  1109. case athr_l2c_b:
  1110. ctrl_data &= ~(SERDES_PHY_CLK_SLOWDOWN |
  1111. SERDES_MAC_CLK_SLOWDOWN);
  1112. AT_WRITE_REG(hw, REG_SERDES, ctrl_data);
  1113. break;
  1114. case athr_l2c_b2:
  1115. case athr_l1d_2:
  1116. ctrl_data |= SERDES_PHY_CLK_SLOWDOWN | SERDES_MAC_CLK_SLOWDOWN;
  1117. AT_WRITE_REG(hw, REG_SERDES, ctrl_data);
  1118. break;
  1119. default:
  1120. break;
  1121. }
  1122. return 0;
  1123. }
  1124. static void atl1c_disable_l0s_l1(struct atl1c_hw *hw)
  1125. {
  1126. u16 ctrl_flags = hw->ctrl_flags;
  1127. hw->ctrl_flags &= ~(ATL1C_ASPM_L0S_SUPPORT | ATL1C_ASPM_L1_SUPPORT);
  1128. atl1c_set_aspm(hw, SPEED_0);
  1129. hw->ctrl_flags = ctrl_flags;
  1130. }
  1131. /*
  1132. * Set ASPM state.
  1133. * Enable/disable L0s/L1 depend on link state.
  1134. */
  1135. static void atl1c_set_aspm(struct atl1c_hw *hw, u16 link_speed)
  1136. {
  1137. u32 pm_ctrl_data;
  1138. u32 link_l1_timer;
  1139. AT_READ_REG(hw, REG_PM_CTRL, &pm_ctrl_data);
  1140. pm_ctrl_data &= ~(PM_CTRL_ASPM_L1_EN |
  1141. PM_CTRL_ASPM_L0S_EN |
  1142. PM_CTRL_MAC_ASPM_CHK);
  1143. /* L1 timer */
  1144. if (hw->nic_type == athr_l2c_b2 || hw->nic_type == athr_l1d_2) {
  1145. pm_ctrl_data &= ~PMCTRL_TXL1_AFTER_L0S;
  1146. link_l1_timer =
  1147. link_speed == SPEED_1000 || link_speed == SPEED_100 ?
  1148. L1D_PMCTRL_L1_ENTRY_TM_16US : 1;
  1149. pm_ctrl_data = FIELD_SETX(pm_ctrl_data,
  1150. L1D_PMCTRL_L1_ENTRY_TM, link_l1_timer);
  1151. } else {
  1152. link_l1_timer = hw->nic_type == athr_l2c_b ?
  1153. L2CB1_PM_CTRL_L1_ENTRY_TM : L1C_PM_CTRL_L1_ENTRY_TM;
  1154. if (link_speed != SPEED_1000 && link_speed != SPEED_100)
  1155. link_l1_timer = 1;
  1156. pm_ctrl_data = FIELD_SETX(pm_ctrl_data,
  1157. PM_CTRL_L1_ENTRY_TIMER, link_l1_timer);
  1158. }
  1159. /* L0S/L1 enable */
  1160. if ((hw->ctrl_flags & ATL1C_ASPM_L0S_SUPPORT) && link_speed != SPEED_0)
  1161. pm_ctrl_data |= PM_CTRL_ASPM_L0S_EN | PM_CTRL_MAC_ASPM_CHK;
  1162. if (hw->ctrl_flags & ATL1C_ASPM_L1_SUPPORT)
  1163. pm_ctrl_data |= PM_CTRL_ASPM_L1_EN | PM_CTRL_MAC_ASPM_CHK;
  1164. /* l2cb & l1d & l2cb2 & l1d2 */
  1165. if (hw->nic_type == athr_l2c_b || hw->nic_type == athr_l1d ||
  1166. hw->nic_type == athr_l2c_b2 || hw->nic_type == athr_l1d_2) {
  1167. pm_ctrl_data = FIELD_SETX(pm_ctrl_data,
  1168. PM_CTRL_PM_REQ_TIMER, PM_CTRL_PM_REQ_TO_DEF);
  1169. pm_ctrl_data |= PM_CTRL_RCVR_WT_TIMER |
  1170. PM_CTRL_SERDES_PD_EX_L1 |
  1171. PM_CTRL_CLK_SWH_L1;
  1172. pm_ctrl_data &= ~(PM_CTRL_SERDES_L1_EN |
  1173. PM_CTRL_SERDES_PLL_L1_EN |
  1174. PM_CTRL_SERDES_BUFS_RX_L1_EN |
  1175. PM_CTRL_SA_DLY_EN |
  1176. PM_CTRL_HOTRST);
  1177. /* disable l0s if link down or l2cb */
  1178. if (link_speed == SPEED_0 || hw->nic_type == athr_l2c_b)
  1179. pm_ctrl_data &= ~PM_CTRL_ASPM_L0S_EN;
  1180. } else { /* l1c */
  1181. pm_ctrl_data =
  1182. FIELD_SETX(pm_ctrl_data, PM_CTRL_L1_ENTRY_TIMER, 0);
  1183. if (link_speed != SPEED_0) {
  1184. pm_ctrl_data |= PM_CTRL_SERDES_L1_EN |
  1185. PM_CTRL_SERDES_PLL_L1_EN |
  1186. PM_CTRL_SERDES_BUFS_RX_L1_EN;
  1187. pm_ctrl_data &= ~(PM_CTRL_SERDES_PD_EX_L1 |
  1188. PM_CTRL_CLK_SWH_L1 |
  1189. PM_CTRL_ASPM_L0S_EN |
  1190. PM_CTRL_ASPM_L1_EN);
  1191. } else { /* link down */
  1192. pm_ctrl_data |= PM_CTRL_CLK_SWH_L1;
  1193. pm_ctrl_data &= ~(PM_CTRL_SERDES_L1_EN |
  1194. PM_CTRL_SERDES_PLL_L1_EN |
  1195. PM_CTRL_SERDES_BUFS_RX_L1_EN |
  1196. PM_CTRL_ASPM_L0S_EN);
  1197. }
  1198. }
  1199. AT_WRITE_REG(hw, REG_PM_CTRL, pm_ctrl_data);
  1200. return;
  1201. }
  1202. /*
  1203. * atl1c_configure - Configure Transmit&Receive Unit after Reset
  1204. * @adapter: board private structure
  1205. *
  1206. * Configure the Tx /Rx unit of the MAC after a reset.
  1207. */
  1208. static int atl1c_configure_mac(struct atl1c_adapter *adapter)
  1209. {
  1210. struct atl1c_hw *hw = &adapter->hw;
  1211. u32 master_ctrl_data = 0;
  1212. u32 intr_modrt_data;
  1213. u32 data;
  1214. AT_READ_REG(hw, REG_MASTER_CTRL, &master_ctrl_data);
  1215. master_ctrl_data &= ~(MASTER_CTRL_TX_ITIMER_EN |
  1216. MASTER_CTRL_RX_ITIMER_EN |
  1217. MASTER_CTRL_INT_RDCLR);
  1218. /* clear interrupt status */
  1219. AT_WRITE_REG(hw, REG_ISR, 0xFFFFFFFF);
  1220. /* Clear any WOL status */
  1221. AT_WRITE_REG(hw, REG_WOL_CTRL, 0);
  1222. /* set Interrupt Clear Timer
  1223. * HW will enable self to assert interrupt event to system after
  1224. * waiting x-time for software to notify it accept interrupt.
  1225. */
  1226. data = CLK_GATING_EN_ALL;
  1227. if (hw->ctrl_flags & ATL1C_CLK_GATING_EN) {
  1228. if (hw->nic_type == athr_l2c_b)
  1229. data &= ~CLK_GATING_RXMAC_EN;
  1230. } else
  1231. data = 0;
  1232. AT_WRITE_REG(hw, REG_CLK_GATING_CTRL, data);
  1233. AT_WRITE_REG(hw, REG_INT_RETRIG_TIMER,
  1234. hw->ict & INT_RETRIG_TIMER_MASK);
  1235. atl1c_configure_des_ring(adapter);
  1236. if (hw->ctrl_flags & ATL1C_INTR_MODRT_ENABLE) {
  1237. intr_modrt_data = (hw->tx_imt & IRQ_MODRT_TIMER_MASK) <<
  1238. IRQ_MODRT_TX_TIMER_SHIFT;
  1239. intr_modrt_data |= (hw->rx_imt & IRQ_MODRT_TIMER_MASK) <<
  1240. IRQ_MODRT_RX_TIMER_SHIFT;
  1241. AT_WRITE_REG(hw, REG_IRQ_MODRT_TIMER_INIT, intr_modrt_data);
  1242. master_ctrl_data |=
  1243. MASTER_CTRL_TX_ITIMER_EN | MASTER_CTRL_RX_ITIMER_EN;
  1244. }
  1245. if (hw->ctrl_flags & ATL1C_INTR_CLEAR_ON_READ)
  1246. master_ctrl_data |= MASTER_CTRL_INT_RDCLR;
  1247. master_ctrl_data |= MASTER_CTRL_SA_TIMER_EN;
  1248. AT_WRITE_REG(hw, REG_MASTER_CTRL, master_ctrl_data);
  1249. AT_WRITE_REG(hw, REG_SMB_STAT_TIMER,
  1250. hw->smb_timer & SMB_STAT_TIMER_MASK);
  1251. /* set MTU */
  1252. AT_WRITE_REG(hw, REG_MTU, hw->max_frame_size + ETH_HLEN +
  1253. VLAN_HLEN + ETH_FCS_LEN);
  1254. atl1c_configure_tx(adapter);
  1255. atl1c_configure_rx(adapter);
  1256. atl1c_configure_dma(adapter);
  1257. return 0;
  1258. }
  1259. static int atl1c_configure(struct atl1c_adapter *adapter)
  1260. {
  1261. struct net_device *netdev = adapter->netdev;
  1262. int num;
  1263. atl1c_init_ring_ptrs(adapter);
  1264. atl1c_set_multi(netdev);
  1265. atl1c_restore_vlan(adapter);
  1266. num = atl1c_alloc_rx_buffer(adapter);
  1267. if (unlikely(num == 0))
  1268. return -ENOMEM;
  1269. if (atl1c_configure_mac(adapter))
  1270. return -EIO;
  1271. return 0;
  1272. }
  1273. static void atl1c_update_hw_stats(struct atl1c_adapter *adapter)
  1274. {
  1275. u16 hw_reg_addr = 0;
  1276. unsigned long *stats_item = NULL;
  1277. u32 data;
  1278. /* update rx status */
  1279. hw_reg_addr = REG_MAC_RX_STATUS_BIN;
  1280. stats_item = &adapter->hw_stats.rx_ok;
  1281. while (hw_reg_addr <= REG_MAC_RX_STATUS_END) {
  1282. AT_READ_REG(&adapter->hw, hw_reg_addr, &data);
  1283. *stats_item += data;
  1284. stats_item++;
  1285. hw_reg_addr += 4;
  1286. }
  1287. /* update tx status */
  1288. hw_reg_addr = REG_MAC_TX_STATUS_BIN;
  1289. stats_item = &adapter->hw_stats.tx_ok;
  1290. while (hw_reg_addr <= REG_MAC_TX_STATUS_END) {
  1291. AT_READ_REG(&adapter->hw, hw_reg_addr, &data);
  1292. *stats_item += data;
  1293. stats_item++;
  1294. hw_reg_addr += 4;
  1295. }
  1296. }
  1297. /*
  1298. * atl1c_get_stats - Get System Network Statistics
  1299. * @netdev: network interface device structure
  1300. *
  1301. * Returns the address of the device statistics structure.
  1302. * The statistics are actually updated from the timer callback.
  1303. */
  1304. static struct net_device_stats *atl1c_get_stats(struct net_device *netdev)
  1305. {
  1306. struct atl1c_adapter *adapter = netdev_priv(netdev);
  1307. struct atl1c_hw_stats *hw_stats = &adapter->hw_stats;
  1308. struct net_device_stats *net_stats = &netdev->stats;
  1309. atl1c_update_hw_stats(adapter);
  1310. net_stats->rx_packets = hw_stats->rx_ok;
  1311. net_stats->tx_packets = hw_stats->tx_ok;
  1312. net_stats->rx_bytes = hw_stats->rx_byte_cnt;
  1313. net_stats->tx_bytes = hw_stats->tx_byte_cnt;
  1314. net_stats->multicast = hw_stats->rx_mcast;
  1315. net_stats->collisions = hw_stats->tx_1_col +
  1316. hw_stats->tx_2_col * 2 +
  1317. hw_stats->tx_late_col + hw_stats->tx_abort_col;
  1318. net_stats->rx_errors = hw_stats->rx_frag + hw_stats->rx_fcs_err +
  1319. hw_stats->rx_len_err + hw_stats->rx_sz_ov +
  1320. hw_stats->rx_rrd_ov + hw_stats->rx_align_err;
  1321. net_stats->rx_fifo_errors = hw_stats->rx_rxf_ov;
  1322. net_stats->rx_length_errors = hw_stats->rx_len_err;
  1323. net_stats->rx_crc_errors = hw_stats->rx_fcs_err;
  1324. net_stats->rx_frame_errors = hw_stats->rx_align_err;
  1325. net_stats->rx_over_errors = hw_stats->rx_rrd_ov + hw_stats->rx_rxf_ov;
  1326. net_stats->rx_missed_errors = hw_stats->rx_rrd_ov + hw_stats->rx_rxf_ov;
  1327. net_stats->tx_errors = hw_stats->tx_late_col + hw_stats->tx_abort_col +
  1328. hw_stats->tx_underrun + hw_stats->tx_trunc;
  1329. net_stats->tx_fifo_errors = hw_stats->tx_underrun;
  1330. net_stats->tx_aborted_errors = hw_stats->tx_abort_col;
  1331. net_stats->tx_window_errors = hw_stats->tx_late_col;
  1332. return net_stats;
  1333. }
  1334. static inline void atl1c_clear_phy_int(struct atl1c_adapter *adapter)
  1335. {
  1336. u16 phy_data;
  1337. spin_lock(&adapter->mdio_lock);
  1338. atl1c_read_phy_reg(&adapter->hw, MII_ISR, &phy_data);
  1339. spin_unlock(&adapter->mdio_lock);
  1340. }
  1341. static bool atl1c_clean_tx_irq(struct atl1c_adapter *adapter,
  1342. enum atl1c_trans_queue type)
  1343. {
  1344. struct atl1c_tpd_ring *tpd_ring = (struct atl1c_tpd_ring *)
  1345. &adapter->tpd_ring[type];
  1346. struct atl1c_buffer *buffer_info;
  1347. struct pci_dev *pdev = adapter->pdev;
  1348. u16 next_to_clean = atomic_read(&tpd_ring->next_to_clean);
  1349. u16 hw_next_to_clean;
  1350. u16 reg;
  1351. reg = type == atl1c_trans_high ? REG_TPD_PRI1_CIDX : REG_TPD_PRI0_CIDX;
  1352. AT_READ_REGW(&adapter->hw, reg, &hw_next_to_clean);
  1353. while (next_to_clean != hw_next_to_clean) {
  1354. buffer_info = &tpd_ring->buffer_info[next_to_clean];
  1355. atl1c_clean_buffer(pdev, buffer_info, 1);
  1356. if (++next_to_clean == tpd_ring->count)
  1357. next_to_clean = 0;
  1358. atomic_set(&tpd_ring->next_to_clean, next_to_clean);
  1359. }
  1360. if (netif_queue_stopped(adapter->netdev) &&
  1361. netif_carrier_ok(adapter->netdev)) {
  1362. netif_wake_queue(adapter->netdev);
  1363. }
  1364. return true;
  1365. }
  1366. /*
  1367. * atl1c_intr - Interrupt Handler
  1368. * @irq: interrupt number
  1369. * @data: pointer to a network interface device structure
  1370. * @pt_regs: CPU registers structure
  1371. */
  1372. static irqreturn_t atl1c_intr(int irq, void *data)
  1373. {
  1374. struct net_device *netdev = data;
  1375. struct atl1c_adapter *adapter = netdev_priv(netdev);
  1376. struct pci_dev *pdev = adapter->pdev;
  1377. struct atl1c_hw *hw = &adapter->hw;
  1378. int max_ints = AT_MAX_INT_WORK;
  1379. int handled = IRQ_NONE;
  1380. u32 status;
  1381. u32 reg_data;
  1382. do {
  1383. AT_READ_REG(hw, REG_ISR, &reg_data);
  1384. status = reg_data & hw->intr_mask;
  1385. if (status == 0 || (status & ISR_DIS_INT) != 0) {
  1386. if (max_ints != AT_MAX_INT_WORK)
  1387. handled = IRQ_HANDLED;
  1388. break;
  1389. }
  1390. /* link event */
  1391. if (status & ISR_GPHY)
  1392. atl1c_clear_phy_int(adapter);
  1393. /* Ack ISR */
  1394. AT_WRITE_REG(hw, REG_ISR, status | ISR_DIS_INT);
  1395. if (status & ISR_RX_PKT) {
  1396. if (likely(napi_schedule_prep(&adapter->napi))) {
  1397. hw->intr_mask &= ~ISR_RX_PKT;
  1398. AT_WRITE_REG(hw, REG_IMR, hw->intr_mask);
  1399. __napi_schedule(&adapter->napi);
  1400. }
  1401. }
  1402. if (status & ISR_TX_PKT)
  1403. atl1c_clean_tx_irq(adapter, atl1c_trans_normal);
  1404. handled = IRQ_HANDLED;
  1405. /* check if PCIE PHY Link down */
  1406. if (status & ISR_ERROR) {
  1407. if (netif_msg_hw(adapter))
  1408. dev_err(&pdev->dev,
  1409. "atl1c hardware error (status = 0x%x)\n",
  1410. status & ISR_ERROR);
  1411. /* reset MAC */
  1412. set_bit(ATL1C_WORK_EVENT_RESET, &adapter->work_event);
  1413. schedule_work(&adapter->common_task);
  1414. return IRQ_HANDLED;
  1415. }
  1416. if (status & ISR_OVER)
  1417. if (netif_msg_intr(adapter))
  1418. dev_warn(&pdev->dev,
  1419. "TX/RX overflow (status = 0x%x)\n",
  1420. status & ISR_OVER);
  1421. /* link event */
  1422. if (status & (ISR_GPHY | ISR_MANUAL)) {
  1423. netdev->stats.tx_carrier_errors++;
  1424. atl1c_link_chg_event(adapter);
  1425. break;
  1426. }
  1427. } while (--max_ints > 0);
  1428. /* re-enable Interrupt*/
  1429. AT_WRITE_REG(&adapter->hw, REG_ISR, 0);
  1430. return handled;
  1431. }
  1432. static inline void atl1c_rx_checksum(struct atl1c_adapter *adapter,
  1433. struct sk_buff *skb, struct atl1c_recv_ret_status *prrs)
  1434. {
  1435. /*
  1436. * The pid field in RRS in not correct sometimes, so we
  1437. * cannot figure out if the packet is fragmented or not,
  1438. * so we tell the KERNEL CHECKSUM_NONE
  1439. */
  1440. skb_checksum_none_assert(skb);
  1441. }
  1442. static int atl1c_alloc_rx_buffer(struct atl1c_adapter *adapter)
  1443. {
  1444. struct atl1c_rfd_ring *rfd_ring = &adapter->rfd_ring;
  1445. struct pci_dev *pdev = adapter->pdev;
  1446. struct atl1c_buffer *buffer_info, *next_info;
  1447. struct sk_buff *skb;
  1448. void *vir_addr = NULL;
  1449. u16 num_alloc = 0;
  1450. u16 rfd_next_to_use, next_next;
  1451. struct atl1c_rx_free_desc *rfd_desc;
  1452. next_next = rfd_next_to_use = rfd_ring->next_to_use;
  1453. if (++next_next == rfd_ring->count)
  1454. next_next = 0;
  1455. buffer_info = &rfd_ring->buffer_info[rfd_next_to_use];
  1456. next_info = &rfd_ring->buffer_info[next_next];
  1457. while (next_info->flags & ATL1C_BUFFER_FREE) {
  1458. rfd_desc = ATL1C_RFD_DESC(rfd_ring, rfd_next_to_use);
  1459. skb = netdev_alloc_skb(adapter->netdev, adapter->rx_buffer_len);
  1460. if (unlikely(!skb)) {
  1461. if (netif_msg_rx_err(adapter))
  1462. dev_warn(&pdev->dev, "alloc rx buffer failed\n");
  1463. break;
  1464. }
  1465. /*
  1466. * Make buffer alignment 2 beyond a 16 byte boundary
  1467. * this will result in a 16 byte aligned IP header after
  1468. * the 14 byte MAC header is removed
  1469. */
  1470. vir_addr = skb->data;
  1471. ATL1C_SET_BUFFER_STATE(buffer_info, ATL1C_BUFFER_BUSY);
  1472. buffer_info->skb = skb;
  1473. buffer_info->length = adapter->rx_buffer_len;
  1474. buffer_info->dma = pci_map_single(pdev, vir_addr,
  1475. buffer_info->length,
  1476. PCI_DMA_FROMDEVICE);
  1477. ATL1C_SET_PCIMAP_TYPE(buffer_info, ATL1C_PCIMAP_SINGLE,
  1478. ATL1C_PCIMAP_FROMDEVICE);
  1479. rfd_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
  1480. rfd_next_to_use = next_next;
  1481. if (++next_next == rfd_ring->count)
  1482. next_next = 0;
  1483. buffer_info = &rfd_ring->buffer_info[rfd_next_to_use];
  1484. next_info = &rfd_ring->buffer_info[next_next];
  1485. num_alloc++;
  1486. }
  1487. if (num_alloc) {
  1488. /* TODO: update mailbox here */
  1489. wmb();
  1490. rfd_ring->next_to_use = rfd_next_to_use;
  1491. AT_WRITE_REG(&adapter->hw, REG_MB_RFD0_PROD_IDX,
  1492. rfd_ring->next_to_use & MB_RFDX_PROD_IDX_MASK);
  1493. }
  1494. return num_alloc;
  1495. }
  1496. static void atl1c_clean_rrd(struct atl1c_rrd_ring *rrd_ring,
  1497. struct atl1c_recv_ret_status *rrs, u16 num)
  1498. {
  1499. u16 i;
  1500. /* the relationship between rrd and rfd is one map one */
  1501. for (i = 0; i < num; i++, rrs = ATL1C_RRD_DESC(rrd_ring,
  1502. rrd_ring->next_to_clean)) {
  1503. rrs->word3 &= ~RRS_RXD_UPDATED;
  1504. if (++rrd_ring->next_to_clean == rrd_ring->count)
  1505. rrd_ring->next_to_clean = 0;
  1506. }
  1507. }
  1508. static void atl1c_clean_rfd(struct atl1c_rfd_ring *rfd_ring,
  1509. struct atl1c_recv_ret_status *rrs, u16 num)
  1510. {
  1511. u16 i;
  1512. u16 rfd_index;
  1513. struct atl1c_buffer *buffer_info = rfd_ring->buffer_info;
  1514. rfd_index = (rrs->word0 >> RRS_RX_RFD_INDEX_SHIFT) &
  1515. RRS_RX_RFD_INDEX_MASK;
  1516. for (i = 0; i < num; i++) {
  1517. buffer_info[rfd_index].skb = NULL;
  1518. ATL1C_SET_BUFFER_STATE(&buffer_info[rfd_index],
  1519. ATL1C_BUFFER_FREE);
  1520. if (++rfd_index == rfd_ring->count)
  1521. rfd_index = 0;
  1522. }
  1523. rfd_ring->next_to_clean = rfd_index;
  1524. }
  1525. static void atl1c_clean_rx_irq(struct atl1c_adapter *adapter,
  1526. int *work_done, int work_to_do)
  1527. {
  1528. u16 rfd_num, rfd_index;
  1529. u16 count = 0;
  1530. u16 length;
  1531. struct pci_dev *pdev = adapter->pdev;
  1532. struct net_device *netdev = adapter->netdev;
  1533. struct atl1c_rfd_ring *rfd_ring = &adapter->rfd_ring;
  1534. struct atl1c_rrd_ring *rrd_ring = &adapter->rrd_ring;
  1535. struct sk_buff *skb;
  1536. struct atl1c_recv_ret_status *rrs;
  1537. struct atl1c_buffer *buffer_info;
  1538. while (1) {
  1539. if (*work_done >= work_to_do)
  1540. break;
  1541. rrs = ATL1C_RRD_DESC(rrd_ring, rrd_ring->next_to_clean);
  1542. if (likely(RRS_RXD_IS_VALID(rrs->word3))) {
  1543. rfd_num = (rrs->word0 >> RRS_RX_RFD_CNT_SHIFT) &
  1544. RRS_RX_RFD_CNT_MASK;
  1545. if (unlikely(rfd_num != 1))
  1546. /* TODO support mul rfd*/
  1547. if (netif_msg_rx_err(adapter))
  1548. dev_warn(&pdev->dev,
  1549. "Multi rfd not support yet!\n");
  1550. goto rrs_checked;
  1551. } else {
  1552. break;
  1553. }
  1554. rrs_checked:
  1555. atl1c_clean_rrd(rrd_ring, rrs, rfd_num);
  1556. if (rrs->word3 & (RRS_RX_ERR_SUM | RRS_802_3_LEN_ERR)) {
  1557. atl1c_clean_rfd(rfd_ring, rrs, rfd_num);
  1558. if (netif_msg_rx_err(adapter))
  1559. dev_warn(&pdev->dev,
  1560. "wrong packet! rrs word3 is %x\n",
  1561. rrs->word3);
  1562. continue;
  1563. }
  1564. length = le16_to_cpu((rrs->word3 >> RRS_PKT_SIZE_SHIFT) &
  1565. RRS_PKT_SIZE_MASK);
  1566. /* Good Receive */
  1567. if (likely(rfd_num == 1)) {
  1568. rfd_index = (rrs->word0 >> RRS_RX_RFD_INDEX_SHIFT) &
  1569. RRS_RX_RFD_INDEX_MASK;
  1570. buffer_info = &rfd_ring->buffer_info[rfd_index];
  1571. pci_unmap_single(pdev, buffer_info->dma,
  1572. buffer_info->length, PCI_DMA_FROMDEVICE);
  1573. skb = buffer_info->skb;
  1574. } else {
  1575. /* TODO */
  1576. if (netif_msg_rx_err(adapter))
  1577. dev_warn(&pdev->dev,
  1578. "Multi rfd not support yet!\n");
  1579. break;
  1580. }
  1581. atl1c_clean_rfd(rfd_ring, rrs, rfd_num);
  1582. skb_put(skb, length - ETH_FCS_LEN);
  1583. skb->protocol = eth_type_trans(skb, netdev);
  1584. atl1c_rx_checksum(adapter, skb, rrs);
  1585. if (rrs->word3 & RRS_VLAN_INS) {
  1586. u16 vlan;
  1587. AT_TAG_TO_VLAN(rrs->vlan_tag, vlan);
  1588. vlan = le16_to_cpu(vlan);
  1589. __vlan_hwaccel_put_tag(skb, vlan);
  1590. }
  1591. netif_receive_skb(skb);
  1592. (*work_done)++;
  1593. count++;
  1594. }
  1595. if (count)
  1596. atl1c_alloc_rx_buffer(adapter);
  1597. }
  1598. /*
  1599. * atl1c_clean - NAPI Rx polling callback
  1600. * @adapter: board private structure
  1601. */
  1602. static int atl1c_clean(struct napi_struct *napi, int budget)
  1603. {
  1604. struct atl1c_adapter *adapter =
  1605. container_of(napi, struct atl1c_adapter, napi);
  1606. int work_done = 0;
  1607. /* Keep link state information with original netdev */
  1608. if (!netif_carrier_ok(adapter->netdev))
  1609. goto quit_polling;
  1610. /* just enable one RXQ */
  1611. atl1c_clean_rx_irq(adapter, &work_done, budget);
  1612. if (work_done < budget) {
  1613. quit_polling:
  1614. napi_complete(napi);
  1615. adapter->hw.intr_mask |= ISR_RX_PKT;
  1616. AT_WRITE_REG(&adapter->hw, REG_IMR, adapter->hw.intr_mask);
  1617. }
  1618. return work_done;
  1619. }
  1620. #ifdef CONFIG_NET_POLL_CONTROLLER
  1621. /*
  1622. * Polling 'interrupt' - used by things like netconsole to send skbs
  1623. * without having to re-enable interrupts. It's not called while
  1624. * the interrupt routine is executing.
  1625. */
  1626. static void atl1c_netpoll(struct net_device *netdev)
  1627. {
  1628. struct atl1c_adapter *adapter = netdev_priv(netdev);
  1629. disable_irq(adapter->pdev->irq);
  1630. atl1c_intr(adapter->pdev->irq, netdev);
  1631. enable_irq(adapter->pdev->irq);
  1632. }
  1633. #endif
  1634. static inline u16 atl1c_tpd_avail(struct atl1c_adapter *adapter, enum atl1c_trans_queue type)
  1635. {
  1636. struct atl1c_tpd_ring *tpd_ring = &adapter->tpd_ring[type];
  1637. u16 next_to_use = 0;
  1638. u16 next_to_clean = 0;
  1639. next_to_clean = atomic_read(&tpd_ring->next_to_clean);
  1640. next_to_use = tpd_ring->next_to_use;
  1641. return (u16)(next_to_clean > next_to_use) ?
  1642. (next_to_clean - next_to_use - 1) :
  1643. (tpd_ring->count + next_to_clean - next_to_use - 1);
  1644. }
  1645. /*
  1646. * get next usable tpd
  1647. * Note: should call atl1c_tdp_avail to make sure
  1648. * there is enough tpd to use
  1649. */
  1650. static struct atl1c_tpd_desc *atl1c_get_tpd(struct atl1c_adapter *adapter,
  1651. enum atl1c_trans_queue type)
  1652. {
  1653. struct atl1c_tpd_ring *tpd_ring = &adapter->tpd_ring[type];
  1654. struct atl1c_tpd_desc *tpd_desc;
  1655. u16 next_to_use = 0;
  1656. next_to_use = tpd_ring->next_to_use;
  1657. if (++tpd_ring->next_to_use == tpd_ring->count)
  1658. tpd_ring->next_to_use = 0;
  1659. tpd_desc = ATL1C_TPD_DESC(tpd_ring, next_to_use);
  1660. memset(tpd_desc, 0, sizeof(struct atl1c_tpd_desc));
  1661. return tpd_desc;
  1662. }
  1663. static struct atl1c_buffer *
  1664. atl1c_get_tx_buffer(struct atl1c_adapter *adapter, struct atl1c_tpd_desc *tpd)
  1665. {
  1666. struct atl1c_tpd_ring *tpd_ring = adapter->tpd_ring;
  1667. return &tpd_ring->buffer_info[tpd -
  1668. (struct atl1c_tpd_desc *)tpd_ring->desc];
  1669. }
  1670. /* Calculate the transmit packet descript needed*/
  1671. static u16 atl1c_cal_tpd_req(const struct sk_buff *skb)
  1672. {
  1673. u16 tpd_req;
  1674. u16 proto_hdr_len = 0;
  1675. tpd_req = skb_shinfo(skb)->nr_frags + 1;
  1676. if (skb_is_gso(skb)) {
  1677. proto_hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
  1678. if (proto_hdr_len < skb_headlen(skb))
  1679. tpd_req++;
  1680. if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
  1681. tpd_req++;
  1682. }
  1683. return tpd_req;
  1684. }
  1685. static int atl1c_tso_csum(struct atl1c_adapter *adapter,
  1686. struct sk_buff *skb,
  1687. struct atl1c_tpd_desc **tpd,
  1688. enum atl1c_trans_queue type)
  1689. {
  1690. struct pci_dev *pdev = adapter->pdev;
  1691. u8 hdr_len;
  1692. u32 real_len;
  1693. unsigned short offload_type;
  1694. int err;
  1695. if (skb_is_gso(skb)) {
  1696. if (skb_header_cloned(skb)) {
  1697. err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
  1698. if (unlikely(err))
  1699. return -1;
  1700. }
  1701. offload_type = skb_shinfo(skb)->gso_type;
  1702. if (offload_type & SKB_GSO_TCPV4) {
  1703. real_len = (((unsigned char *)ip_hdr(skb) - skb->data)
  1704. + ntohs(ip_hdr(skb)->tot_len));
  1705. if (real_len < skb->len)
  1706. pskb_trim(skb, real_len);
  1707. hdr_len = (skb_transport_offset(skb) + tcp_hdrlen(skb));
  1708. if (unlikely(skb->len == hdr_len)) {
  1709. /* only xsum need */
  1710. if (netif_msg_tx_queued(adapter))
  1711. dev_warn(&pdev->dev,
  1712. "IPV4 tso with zero data??\n");
  1713. goto check_sum;
  1714. } else {
  1715. ip_hdr(skb)->check = 0;
  1716. tcp_hdr(skb)->check = ~csum_tcpudp_magic(
  1717. ip_hdr(skb)->saddr,
  1718. ip_hdr(skb)->daddr,
  1719. 0, IPPROTO_TCP, 0);
  1720. (*tpd)->word1 |= 1 << TPD_IPV4_PACKET_SHIFT;
  1721. }
  1722. }
  1723. if (offload_type & SKB_GSO_TCPV6) {
  1724. struct atl1c_tpd_ext_desc *etpd =
  1725. *(struct atl1c_tpd_ext_desc **)(tpd);
  1726. memset(etpd, 0, sizeof(struct atl1c_tpd_ext_desc));
  1727. *tpd = atl1c_get_tpd(adapter, type);
  1728. ipv6_hdr(skb)->payload_len = 0;
  1729. /* check payload == 0 byte ? */
  1730. hdr_len = (skb_transport_offset(skb) + tcp_hdrlen(skb));
  1731. if (unlikely(skb->len == hdr_len)) {
  1732. /* only xsum need */
  1733. if (netif_msg_tx_queued(adapter))
  1734. dev_warn(&pdev->dev,
  1735. "IPV6 tso with zero data??\n");
  1736. goto check_sum;
  1737. } else
  1738. tcp_hdr(skb)->check = ~csum_ipv6_magic(
  1739. &ipv6_hdr(skb)->saddr,
  1740. &ipv6_hdr(skb)->daddr,
  1741. 0, IPPROTO_TCP, 0);
  1742. etpd->word1 |= 1 << TPD_LSO_EN_SHIFT;
  1743. etpd->word1 |= 1 << TPD_LSO_VER_SHIFT;
  1744. etpd->pkt_len = cpu_to_le32(skb->len);
  1745. (*tpd)->word1 |= 1 << TPD_LSO_VER_SHIFT;
  1746. }
  1747. (*tpd)->word1 |= 1 << TPD_LSO_EN_SHIFT;
  1748. (*tpd)->word1 |= (skb_transport_offset(skb) & TPD_TCPHDR_OFFSET_MASK) <<
  1749. TPD_TCPHDR_OFFSET_SHIFT;
  1750. (*tpd)->word1 |= (skb_shinfo(skb)->gso_size & TPD_MSS_MASK) <<
  1751. TPD_MSS_SHIFT;
  1752. return 0;
  1753. }
  1754. check_sum:
  1755. if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
  1756. u8 css, cso;
  1757. cso = skb_checksum_start_offset(skb);
  1758. if (unlikely(cso & 0x1)) {
  1759. if (netif_msg_tx_err(adapter))
  1760. dev_err(&adapter->pdev->dev,
  1761. "payload offset should not an event number\n");
  1762. return -1;
  1763. } else {
  1764. css = cso + skb->csum_offset;
  1765. (*tpd)->word1 |= ((cso >> 1) & TPD_PLOADOFFSET_MASK) <<
  1766. TPD_PLOADOFFSET_SHIFT;
  1767. (*tpd)->word1 |= ((css >> 1) & TPD_CCSUM_OFFSET_MASK) <<
  1768. TPD_CCSUM_OFFSET_SHIFT;
  1769. (*tpd)->word1 |= 1 << TPD_CCSUM_EN_SHIFT;
  1770. }
  1771. }
  1772. return 0;
  1773. }
  1774. static void atl1c_tx_map(struct atl1c_adapter *adapter,
  1775. struct sk_buff *skb, struct atl1c_tpd_desc *tpd,
  1776. enum atl1c_trans_queue type)
  1777. {
  1778. struct atl1c_tpd_desc *use_tpd = NULL;
  1779. struct atl1c_buffer *buffer_info = NULL;
  1780. u16 buf_len = skb_headlen(skb);
  1781. u16 map_len = 0;
  1782. u16 mapped_len = 0;
  1783. u16 hdr_len = 0;
  1784. u16 nr_frags;
  1785. u16 f;
  1786. int tso;
  1787. nr_frags = skb_shinfo(skb)->nr_frags;
  1788. tso = (tpd->word1 >> TPD_LSO_EN_SHIFT) & TPD_LSO_EN_MASK;
  1789. if (tso) {
  1790. /* TSO */
  1791. map_len = hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
  1792. use_tpd = tpd;
  1793. buffer_info = atl1c_get_tx_buffer(adapter, use_tpd);
  1794. buffer_info->length = map_len;
  1795. buffer_info->dma = pci_map_single(adapter->pdev,
  1796. skb->data, hdr_len, PCI_DMA_TODEVICE);
  1797. ATL1C_SET_BUFFER_STATE(buffer_info, ATL1C_BUFFER_BUSY);
  1798. ATL1C_SET_PCIMAP_TYPE(buffer_info, ATL1C_PCIMAP_SINGLE,
  1799. ATL1C_PCIMAP_TODEVICE);
  1800. mapped_len += map_len;
  1801. use_tpd->buffer_addr = cpu_to_le64(buffer_info->dma);
  1802. use_tpd->buffer_len = cpu_to_le16(buffer_info->length);
  1803. }
  1804. if (mapped_len < buf_len) {
  1805. /* mapped_len == 0, means we should use the first tpd,
  1806. which is given by caller */
  1807. if (mapped_len == 0)
  1808. use_tpd = tpd;
  1809. else {
  1810. use_tpd = atl1c_get_tpd(adapter, type);
  1811. memcpy(use_tpd, tpd, sizeof(struct atl1c_tpd_desc));
  1812. }
  1813. buffer_info = atl1c_get_tx_buffer(adapter, use_tpd);
  1814. buffer_info->length = buf_len - mapped_len;
  1815. buffer_info->dma =
  1816. pci_map_single(adapter->pdev, skb->data + mapped_len,
  1817. buffer_info->length, PCI_DMA_TODEVICE);
  1818. ATL1C_SET_BUFFER_STATE(buffer_info, ATL1C_BUFFER_BUSY);
  1819. ATL1C_SET_PCIMAP_TYPE(buffer_info, ATL1C_PCIMAP_SINGLE,
  1820. ATL1C_PCIMAP_TODEVICE);
  1821. use_tpd->buffer_addr = cpu_to_le64(buffer_info->dma);
  1822. use_tpd->buffer_len = cpu_to_le16(buffer_info->length);
  1823. }
  1824. for (f = 0; f < nr_frags; f++) {
  1825. struct skb_frag_struct *frag;
  1826. frag = &skb_shinfo(skb)->frags[f];
  1827. use_tpd = atl1c_get_tpd(adapter, type);
  1828. memcpy(use_tpd, tpd, sizeof(struct atl1c_tpd_desc));
  1829. buffer_info = atl1c_get_tx_buffer(adapter, use_tpd);
  1830. buffer_info->length = skb_frag_size(frag);
  1831. buffer_info->dma = skb_frag_dma_map(&adapter->pdev->dev,
  1832. frag, 0,
  1833. buffer_info->length,
  1834. DMA_TO_DEVICE);
  1835. ATL1C_SET_BUFFER_STATE(buffer_info, ATL1C_BUFFER_BUSY);
  1836. ATL1C_SET_PCIMAP_TYPE(buffer_info, ATL1C_PCIMAP_PAGE,
  1837. ATL1C_PCIMAP_TODEVICE);
  1838. use_tpd->buffer_addr = cpu_to_le64(buffer_info->dma);
  1839. use_tpd->buffer_len = cpu_to_le16(buffer_info->length);
  1840. }
  1841. /* The last tpd */
  1842. use_tpd->word1 |= 1 << TPD_EOP_SHIFT;
  1843. /* The last buffer info contain the skb address,
  1844. so it will be free after unmap */
  1845. buffer_info->skb = skb;
  1846. }
  1847. static void atl1c_tx_queue(struct atl1c_adapter *adapter, struct sk_buff *skb,
  1848. struct atl1c_tpd_desc *tpd, enum atl1c_trans_queue type)
  1849. {
  1850. struct atl1c_tpd_ring *tpd_ring = &adapter->tpd_ring[type];
  1851. u16 reg;
  1852. reg = type == atl1c_trans_high ? REG_TPD_PRI1_PIDX : REG_TPD_PRI0_PIDX;
  1853. AT_WRITE_REGW(&adapter->hw, reg, tpd_ring->next_to_use);
  1854. }
  1855. static netdev_tx_t atl1c_xmit_frame(struct sk_buff *skb,
  1856. struct net_device *netdev)
  1857. {
  1858. struct atl1c_adapter *adapter = netdev_priv(netdev);
  1859. unsigned long flags;
  1860. u16 tpd_req = 1;
  1861. struct atl1c_tpd_desc *tpd;
  1862. enum atl1c_trans_queue type = atl1c_trans_normal;
  1863. if (test_bit(__AT_DOWN, &adapter->flags)) {
  1864. dev_kfree_skb_any(skb);
  1865. return NETDEV_TX_OK;
  1866. }
  1867. tpd_req = atl1c_cal_tpd_req(skb);
  1868. if (!spin_trylock_irqsave(&adapter->tx_lock, flags)) {
  1869. if (netif_msg_pktdata(adapter))
  1870. dev_info(&adapter->pdev->dev, "tx locked\n");
  1871. return NETDEV_TX_LOCKED;
  1872. }
  1873. if (atl1c_tpd_avail(adapter, type) < tpd_req) {
  1874. /* no enough descriptor, just stop queue */
  1875. netif_stop_queue(netdev);
  1876. spin_unlock_irqrestore(&adapter->tx_lock, flags);
  1877. return NETDEV_TX_BUSY;
  1878. }
  1879. tpd = atl1c_get_tpd(adapter, type);
  1880. /* do TSO and check sum */
  1881. if (atl1c_tso_csum(adapter, skb, &tpd, type) != 0) {
  1882. spin_unlock_irqrestore(&adapter->tx_lock, flags);
  1883. dev_kfree_skb_any(skb);
  1884. return NETDEV_TX_OK;
  1885. }
  1886. if (unlikely(vlan_tx_tag_present(skb))) {
  1887. u16 vlan = vlan_tx_tag_get(skb);
  1888. __le16 tag;
  1889. vlan = cpu_to_le16(vlan);
  1890. AT_VLAN_TO_TAG(vlan, tag);
  1891. tpd->word1 |= 1 << TPD_INS_VTAG_SHIFT;
  1892. tpd->vlan_tag = tag;
  1893. }
  1894. if (skb_network_offset(skb) != ETH_HLEN)
  1895. tpd->word1 |= 1 << TPD_ETH_TYPE_SHIFT; /* Ethernet frame */
  1896. atl1c_tx_map(adapter, skb, tpd, type);
  1897. atl1c_tx_queue(adapter, skb, tpd, type);
  1898. spin_unlock_irqrestore(&adapter->tx_lock, flags);
  1899. return NETDEV_TX_OK;
  1900. }
  1901. static void atl1c_free_irq(struct atl1c_adapter *adapter)
  1902. {
  1903. struct net_device *netdev = adapter->netdev;
  1904. free_irq(adapter->pdev->irq, netdev);
  1905. if (adapter->have_msi)
  1906. pci_disable_msi(adapter->pdev);
  1907. }
  1908. static int atl1c_request_irq(struct atl1c_adapter *adapter)
  1909. {
  1910. struct pci_dev *pdev = adapter->pdev;
  1911. struct net_device *netdev = adapter->netdev;
  1912. int flags = 0;
  1913. int err = 0;
  1914. adapter->have_msi = true;
  1915. err = pci_enable_msi(adapter->pdev);
  1916. if (err) {
  1917. if (netif_msg_ifup(adapter))
  1918. dev_err(&pdev->dev,
  1919. "Unable to allocate MSI interrupt Error: %d\n",
  1920. err);
  1921. adapter->have_msi = false;
  1922. }
  1923. if (!adapter->have_msi)
  1924. flags |= IRQF_SHARED;
  1925. err = request_irq(adapter->pdev->irq, atl1c_intr, flags,
  1926. netdev->name, netdev);
  1927. if (err) {
  1928. if (netif_msg_ifup(adapter))
  1929. dev_err(&pdev->dev,
  1930. "Unable to allocate interrupt Error: %d\n",
  1931. err);
  1932. if (adapter->have_msi)
  1933. pci_disable_msi(adapter->pdev);
  1934. return err;
  1935. }
  1936. if (netif_msg_ifup(adapter))
  1937. dev_dbg(&pdev->dev, "atl1c_request_irq OK\n");
  1938. return err;
  1939. }
  1940. static void atl1c_reset_dma_ring(struct atl1c_adapter *adapter)
  1941. {
  1942. /* release tx-pending skbs and reset tx/rx ring index */
  1943. atl1c_clean_tx_ring(adapter, atl1c_trans_normal);
  1944. atl1c_clean_tx_ring(adapter, atl1c_trans_high);
  1945. atl1c_clean_rx_ring(adapter);
  1946. }
  1947. static int atl1c_up(struct atl1c_adapter *adapter)
  1948. {
  1949. struct net_device *netdev = adapter->netdev;
  1950. int err;
  1951. netif_carrier_off(netdev);
  1952. err = atl1c_configure(adapter);
  1953. if (unlikely(err))
  1954. goto err_up;
  1955. err = atl1c_request_irq(adapter);
  1956. if (unlikely(err))
  1957. goto err_up;
  1958. atl1c_check_link_status(adapter);
  1959. clear_bit(__AT_DOWN, &adapter->flags);
  1960. napi_enable(&adapter->napi);
  1961. atl1c_irq_enable(adapter);
  1962. netif_start_queue(netdev);
  1963. return err;
  1964. err_up:
  1965. atl1c_clean_rx_ring(adapter);
  1966. return err;
  1967. }
  1968. static void atl1c_down(struct atl1c_adapter *adapter)
  1969. {
  1970. struct net_device *netdev = adapter->netdev;
  1971. atl1c_del_timer(adapter);
  1972. adapter->work_event = 0; /* clear all event */
  1973. /* signal that we're down so the interrupt handler does not
  1974. * reschedule our watchdog timer */
  1975. set_bit(__AT_DOWN, &adapter->flags);
  1976. netif_carrier_off(netdev);
  1977. napi_disable(&adapter->napi);
  1978. atl1c_irq_disable(adapter);
  1979. atl1c_free_irq(adapter);
  1980. /* disable ASPM if device inactive */
  1981. atl1c_disable_l0s_l1(&adapter->hw);
  1982. /* reset MAC to disable all RX/TX */
  1983. atl1c_reset_mac(&adapter->hw);
  1984. msleep(1);
  1985. adapter->link_speed = SPEED_0;
  1986. adapter->link_duplex = -1;
  1987. atl1c_reset_dma_ring(adapter);
  1988. }
  1989. /*
  1990. * atl1c_open - Called when a network interface is made active
  1991. * @netdev: network interface device structure
  1992. *
  1993. * Returns 0 on success, negative value on failure
  1994. *
  1995. * The open entry point is called when a network interface is made
  1996. * active by the system (IFF_UP). At this point all resources needed
  1997. * for transmit and receive operations are allocated, the interrupt
  1998. * handler is registered with the OS, the watchdog timer is started,
  1999. * and the stack is notified that the interface is ready.
  2000. */
  2001. static int atl1c_open(struct net_device *netdev)
  2002. {
  2003. struct atl1c_adapter *adapter = netdev_priv(netdev);
  2004. int err;
  2005. /* disallow open during test */
  2006. if (test_bit(__AT_TESTING, &adapter->flags))
  2007. return -EBUSY;
  2008. /* allocate rx/tx dma buffer & descriptors */
  2009. err = atl1c_setup_ring_resources(adapter);
  2010. if (unlikely(err))
  2011. return err;
  2012. err = atl1c_up(adapter);
  2013. if (unlikely(err))
  2014. goto err_up;
  2015. return 0;
  2016. err_up:
  2017. atl1c_free_irq(adapter);
  2018. atl1c_free_ring_resources(adapter);
  2019. atl1c_reset_mac(&adapter->hw);
  2020. return err;
  2021. }
  2022. /*
  2023. * atl1c_close - Disables a network interface
  2024. * @netdev: network interface device structure
  2025. *
  2026. * Returns 0, this is not allowed to fail
  2027. *
  2028. * The close entry point is called when an interface is de-activated
  2029. * by the OS. The hardware is still under the drivers control, but
  2030. * needs to be disabled. A global MAC reset is issued to stop the
  2031. * hardware, and all transmit and receive resources are freed.
  2032. */
  2033. static int atl1c_close(struct net_device *netdev)
  2034. {
  2035. struct atl1c_adapter *adapter = netdev_priv(netdev);
  2036. WARN_ON(test_bit(__AT_RESETTING, &adapter->flags));
  2037. set_bit(__AT_DOWN, &adapter->flags);
  2038. cancel_work_sync(&adapter->common_task);
  2039. atl1c_down(adapter);
  2040. atl1c_free_ring_resources(adapter);
  2041. return 0;
  2042. }
  2043. static int atl1c_suspend(struct device *dev)
  2044. {
  2045. struct pci_dev *pdev = to_pci_dev(dev);
  2046. struct net_device *netdev = pci_get_drvdata(pdev);
  2047. struct atl1c_adapter *adapter = netdev_priv(netdev);
  2048. struct atl1c_hw *hw = &adapter->hw;
  2049. u32 wufc = adapter->wol;
  2050. atl1c_disable_l0s_l1(hw);
  2051. if (netif_running(netdev)) {
  2052. WARN_ON(test_bit(__AT_RESETTING, &adapter->flags));
  2053. atl1c_down(adapter);
  2054. }
  2055. netif_device_detach(netdev);
  2056. if (wufc)
  2057. if (atl1c_phy_to_ps_link(hw) != 0)
  2058. dev_dbg(&pdev->dev, "phy power saving failed");
  2059. atl1c_power_saving(hw, wufc);
  2060. return 0;
  2061. }
  2062. #ifdef CONFIG_PM_SLEEP
  2063. static int atl1c_resume(struct device *dev)
  2064. {
  2065. struct pci_dev *pdev = to_pci_dev(dev);
  2066. struct net_device *netdev = pci_get_drvdata(pdev);
  2067. struct atl1c_adapter *adapter = netdev_priv(netdev);
  2068. AT_WRITE_REG(&adapter->hw, REG_WOL_CTRL, 0);
  2069. atl1c_reset_pcie(&adapter->hw, ATL1C_PCIE_L0S_L1_DISABLE);
  2070. atl1c_phy_reset(&adapter->hw);
  2071. atl1c_reset_mac(&adapter->hw);
  2072. atl1c_phy_init(&adapter->hw);
  2073. #if 0
  2074. AT_READ_REG(&adapter->hw, REG_PM_CTRLSTAT, &pm_data);
  2075. pm_data &= ~PM_CTRLSTAT_PME_EN;
  2076. AT_WRITE_REG(&adapter->hw, REG_PM_CTRLSTAT, pm_data);
  2077. #endif
  2078. netif_device_attach(netdev);
  2079. if (netif_running(netdev))
  2080. atl1c_up(adapter);
  2081. return 0;
  2082. }
  2083. #endif
  2084. static void atl1c_shutdown(struct pci_dev *pdev)
  2085. {
  2086. struct net_device *netdev = pci_get_drvdata(pdev);
  2087. struct atl1c_adapter *adapter = netdev_priv(netdev);
  2088. atl1c_suspend(&pdev->dev);
  2089. pci_wake_from_d3(pdev, adapter->wol);
  2090. pci_set_power_state(pdev, PCI_D3hot);
  2091. }
  2092. static const struct net_device_ops atl1c_netdev_ops = {
  2093. .ndo_open = atl1c_open,
  2094. .ndo_stop = atl1c_close,
  2095. .ndo_validate_addr = eth_validate_addr,
  2096. .ndo_start_xmit = atl1c_xmit_frame,
  2097. .ndo_set_mac_address = atl1c_set_mac_addr,
  2098. .ndo_set_rx_mode = atl1c_set_multi,
  2099. .ndo_change_mtu = atl1c_change_mtu,
  2100. .ndo_fix_features = atl1c_fix_features,
  2101. .ndo_set_features = atl1c_set_features,
  2102. .ndo_do_ioctl = atl1c_ioctl,
  2103. .ndo_tx_timeout = atl1c_tx_timeout,
  2104. .ndo_get_stats = atl1c_get_stats,
  2105. #ifdef CONFIG_NET_POLL_CONTROLLER
  2106. .ndo_poll_controller = atl1c_netpoll,
  2107. #endif
  2108. };
  2109. static int atl1c_init_netdev(struct net_device *netdev, struct pci_dev *pdev)
  2110. {
  2111. SET_NETDEV_DEV(netdev, &pdev->dev);
  2112. pci_set_drvdata(pdev, netdev);
  2113. netdev->netdev_ops = &atl1c_netdev_ops;
  2114. netdev->watchdog_timeo = AT_TX_WATCHDOG;
  2115. atl1c_set_ethtool_ops(netdev);
  2116. /* TODO: add when ready */
  2117. netdev->hw_features = NETIF_F_SG |
  2118. NETIF_F_HW_CSUM |
  2119. NETIF_F_HW_VLAN_RX |
  2120. NETIF_F_TSO |
  2121. NETIF_F_TSO6;
  2122. netdev->features = netdev->hw_features |
  2123. NETIF_F_HW_VLAN_TX;
  2124. return 0;
  2125. }
  2126. /*
  2127. * atl1c_probe - Device Initialization Routine
  2128. * @pdev: PCI device information struct
  2129. * @ent: entry in atl1c_pci_tbl
  2130. *
  2131. * Returns 0 on success, negative on failure
  2132. *
  2133. * atl1c_probe initializes an adapter identified by a pci_dev structure.
  2134. * The OS initialization, configuring of the adapter private structure,
  2135. * and a hardware reset occur.
  2136. */
  2137. static int __devinit atl1c_probe(struct pci_dev *pdev,
  2138. const struct pci_device_id *ent)
  2139. {
  2140. struct net_device *netdev;
  2141. struct atl1c_adapter *adapter;
  2142. static int cards_found;
  2143. int err = 0;
  2144. /* enable device (incl. PCI PM wakeup and hotplug setup) */
  2145. err = pci_enable_device_mem(pdev);
  2146. if (err) {
  2147. dev_err(&pdev->dev, "cannot enable PCI device\n");
  2148. return err;
  2149. }
  2150. /*
  2151. * The atl1c chip can DMA to 64-bit addresses, but it uses a single
  2152. * shared register for the high 32 bits, so only a single, aligned,
  2153. * 4 GB physical address range can be used at a time.
  2154. *
  2155. * Supporting 64-bit DMA on this hardware is more trouble than it's
  2156. * worth. It is far easier to limit to 32-bit DMA than update
  2157. * various kernel subsystems to support the mechanics required by a
  2158. * fixed-high-32-bit system.
  2159. */
  2160. if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0) ||
  2161. (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)) != 0)) {
  2162. dev_err(&pdev->dev, "No usable DMA configuration,aborting\n");
  2163. goto err_dma;
  2164. }
  2165. err = pci_request_regions(pdev, atl1c_driver_name);
  2166. if (err) {
  2167. dev_err(&pdev->dev, "cannot obtain PCI resources\n");
  2168. goto err_pci_reg;
  2169. }
  2170. pci_set_master(pdev);
  2171. netdev = alloc_etherdev(sizeof(struct atl1c_adapter));
  2172. if (netdev == NULL) {
  2173. err = -ENOMEM;
  2174. goto err_alloc_etherdev;
  2175. }
  2176. err = atl1c_init_netdev(netdev, pdev);
  2177. if (err) {
  2178. dev_err(&pdev->dev, "init netdevice failed\n");
  2179. goto err_init_netdev;
  2180. }
  2181. adapter = netdev_priv(netdev);
  2182. adapter->bd_number = cards_found;
  2183. adapter->netdev = netdev;
  2184. adapter->pdev = pdev;
  2185. adapter->hw.adapter = adapter;
  2186. adapter->msg_enable = netif_msg_init(-1, atl1c_default_msg);
  2187. adapter->hw.hw_addr = ioremap(pci_resource_start(pdev, 0), pci_resource_len(pdev, 0));
  2188. if (!adapter->hw.hw_addr) {
  2189. err = -EIO;
  2190. dev_err(&pdev->dev, "cannot map device registers\n");
  2191. goto err_ioremap;
  2192. }
  2193. /* init mii data */
  2194. adapter->mii.dev = netdev;
  2195. adapter->mii.mdio_read = atl1c_mdio_read;
  2196. adapter->mii.mdio_write = atl1c_mdio_write;
  2197. adapter->mii.phy_id_mask = 0x1f;
  2198. adapter->mii.reg_num_mask = MDIO_CTRL_REG_MASK;
  2199. netif_napi_add(netdev, &adapter->napi, atl1c_clean, 64);
  2200. setup_timer(&adapter->phy_config_timer, atl1c_phy_config,
  2201. (unsigned long)adapter);
  2202. /* setup the private structure */
  2203. err = atl1c_sw_init(adapter);
  2204. if (err) {
  2205. dev_err(&pdev->dev, "net device private data init failed\n");
  2206. goto err_sw_init;
  2207. }
  2208. atl1c_reset_pcie(&adapter->hw, ATL1C_PCIE_L0S_L1_DISABLE);
  2209. /* Init GPHY as early as possible due to power saving issue */
  2210. atl1c_phy_reset(&adapter->hw);
  2211. err = atl1c_reset_mac(&adapter->hw);
  2212. if (err) {
  2213. err = -EIO;
  2214. goto err_reset;
  2215. }
  2216. /* reset the controller to
  2217. * put the device in a known good starting state */
  2218. err = atl1c_phy_init(&adapter->hw);
  2219. if (err) {
  2220. err = -EIO;
  2221. goto err_reset;
  2222. }
  2223. if (atl1c_read_mac_addr(&adapter->hw)) {
  2224. /* got a random MAC address, set NET_ADDR_RANDOM to netdev */
  2225. netdev->addr_assign_type |= NET_ADDR_RANDOM;
  2226. }
  2227. memcpy(netdev->dev_addr, adapter->hw.mac_addr, netdev->addr_len);
  2228. memcpy(netdev->perm_addr, adapter->hw.mac_addr, netdev->addr_len);
  2229. if (netif_msg_probe(adapter))
  2230. dev_dbg(&pdev->dev, "mac address : %pM\n",
  2231. adapter->hw.mac_addr);
  2232. atl1c_hw_set_mac_addr(&adapter->hw, adapter->hw.mac_addr);
  2233. INIT_WORK(&adapter->common_task, atl1c_common_task);
  2234. adapter->work_event = 0;
  2235. err = register_netdev(netdev);
  2236. if (err) {
  2237. dev_err(&pdev->dev, "register netdevice failed\n");
  2238. goto err_register;
  2239. }
  2240. if (netif_msg_probe(adapter))
  2241. dev_info(&pdev->dev, "version %s\n", ATL1C_DRV_VERSION);
  2242. cards_found++;
  2243. return 0;
  2244. err_reset:
  2245. err_register:
  2246. err_sw_init:
  2247. iounmap(adapter->hw.hw_addr);
  2248. err_init_netdev:
  2249. err_ioremap:
  2250. free_netdev(netdev);
  2251. err_alloc_etherdev:
  2252. pci_release_regions(pdev);
  2253. err_pci_reg:
  2254. err_dma:
  2255. pci_disable_device(pdev);
  2256. return err;
  2257. }
  2258. /*
  2259. * atl1c_remove - Device Removal Routine
  2260. * @pdev: PCI device information struct
  2261. *
  2262. * atl1c_remove is called by the PCI subsystem to alert the driver
  2263. * that it should release a PCI device. The could be caused by a
  2264. * Hot-Plug event, or because the driver is going to be removed from
  2265. * memory.
  2266. */
  2267. static void __devexit atl1c_remove(struct pci_dev *pdev)
  2268. {
  2269. struct net_device *netdev = pci_get_drvdata(pdev);
  2270. struct atl1c_adapter *adapter = netdev_priv(netdev);
  2271. unregister_netdev(netdev);
  2272. /* restore permanent address */
  2273. atl1c_hw_set_mac_addr(&adapter->hw, adapter->hw.perm_mac_addr);
  2274. atl1c_phy_disable(&adapter->hw);
  2275. iounmap(adapter->hw.hw_addr);
  2276. pci_release_regions(pdev);
  2277. pci_disable_device(pdev);
  2278. free_netdev(netdev);
  2279. }
  2280. /*
  2281. * atl1c_io_error_detected - called when PCI error is detected
  2282. * @pdev: Pointer to PCI device
  2283. * @state: The current pci connection state
  2284. *
  2285. * This function is called after a PCI bus error affecting
  2286. * this device has been detected.
  2287. */
  2288. static pci_ers_result_t atl1c_io_error_detected(struct pci_dev *pdev,
  2289. pci_channel_state_t state)
  2290. {
  2291. struct net_device *netdev = pci_get_drvdata(pdev);
  2292. struct atl1c_adapter *adapter = netdev_priv(netdev);
  2293. netif_device_detach(netdev);
  2294. if (state == pci_channel_io_perm_failure)
  2295. return PCI_ERS_RESULT_DISCONNECT;
  2296. if (netif_running(netdev))
  2297. atl1c_down(adapter);
  2298. pci_disable_device(pdev);
  2299. /* Request a slot slot reset. */
  2300. return PCI_ERS_RESULT_NEED_RESET;
  2301. }
  2302. /*
  2303. * atl1c_io_slot_reset - called after the pci bus has been reset.
  2304. * @pdev: Pointer to PCI device
  2305. *
  2306. * Restart the card from scratch, as if from a cold-boot. Implementation
  2307. * resembles the first-half of the e1000_resume routine.
  2308. */
  2309. static pci_ers_result_t atl1c_io_slot_reset(struct pci_dev *pdev)
  2310. {
  2311. struct net_device *netdev = pci_get_drvdata(pdev);
  2312. struct atl1c_adapter *adapter = netdev_priv(netdev);
  2313. if (pci_enable_device(pdev)) {
  2314. if (netif_msg_hw(adapter))
  2315. dev_err(&pdev->dev,
  2316. "Cannot re-enable PCI device after reset\n");
  2317. return PCI_ERS_RESULT_DISCONNECT;
  2318. }
  2319. pci_set_master(pdev);
  2320. pci_enable_wake(pdev, PCI_D3hot, 0);
  2321. pci_enable_wake(pdev, PCI_D3cold, 0);
  2322. atl1c_reset_mac(&adapter->hw);
  2323. return PCI_ERS_RESULT_RECOVERED;
  2324. }
  2325. /*
  2326. * atl1c_io_resume - called when traffic can start flowing again.
  2327. * @pdev: Pointer to PCI device
  2328. *
  2329. * This callback is called when the error recovery driver tells us that
  2330. * its OK to resume normal operation. Implementation resembles the
  2331. * second-half of the atl1c_resume routine.
  2332. */
  2333. static void atl1c_io_resume(struct pci_dev *pdev)
  2334. {
  2335. struct net_device *netdev = pci_get_drvdata(pdev);
  2336. struct atl1c_adapter *adapter = netdev_priv(netdev);
  2337. if (netif_running(netdev)) {
  2338. if (atl1c_up(adapter)) {
  2339. if (netif_msg_hw(adapter))
  2340. dev_err(&pdev->dev,
  2341. "Cannot bring device back up after reset\n");
  2342. return;
  2343. }
  2344. }
  2345. netif_device_attach(netdev);
  2346. }
  2347. static struct pci_error_handlers atl1c_err_handler = {
  2348. .error_detected = atl1c_io_error_detected,
  2349. .slot_reset = atl1c_io_slot_reset,
  2350. .resume = atl1c_io_resume,
  2351. };
  2352. static SIMPLE_DEV_PM_OPS(atl1c_pm_ops, atl1c_suspend, atl1c_resume);
  2353. static struct pci_driver atl1c_driver = {
  2354. .name = atl1c_driver_name,
  2355. .id_table = atl1c_pci_tbl,
  2356. .probe = atl1c_probe,
  2357. .remove = __devexit_p(atl1c_remove),
  2358. .shutdown = atl1c_shutdown,
  2359. .err_handler = &atl1c_err_handler,
  2360. .driver.pm = &atl1c_pm_ops,
  2361. };
  2362. /*
  2363. * atl1c_init_module - Driver Registration Routine
  2364. *
  2365. * atl1c_init_module is the first routine called when the driver is
  2366. * loaded. All it does is register with the PCI subsystem.
  2367. */
  2368. static int __init atl1c_init_module(void)
  2369. {
  2370. return pci_register_driver(&atl1c_driver);
  2371. }
  2372. /*
  2373. * atl1c_exit_module - Driver Exit Cleanup Routine
  2374. *
  2375. * atl1c_exit_module is called just before the driver is removed
  2376. * from memory.
  2377. */
  2378. static void __exit atl1c_exit_module(void)
  2379. {
  2380. pci_unregister_driver(&atl1c_driver);
  2381. }
  2382. module_init(atl1c_init_module);
  2383. module_exit(atl1c_exit_module);