sdhci-tegra.c 11 KB

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  1. /*
  2. * Copyright (C) 2010 Google, Inc.
  3. *
  4. * This software is licensed under the terms of the GNU General Public
  5. * License version 2, as published by the Free Software Foundation, and
  6. * may be copied, distributed, and modified under those terms.
  7. *
  8. * This program is distributed in the hope that it will be useful,
  9. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. * GNU General Public License for more details.
  12. *
  13. */
  14. #include <linux/err.h>
  15. #include <linux/module.h>
  16. #include <linux/init.h>
  17. #include <linux/platform_device.h>
  18. #include <linux/clk.h>
  19. #include <linux/io.h>
  20. #include <linux/of.h>
  21. #include <linux/of_device.h>
  22. #include <linux/of_gpio.h>
  23. #include <linux/gpio.h>
  24. #include <linux/mmc/card.h>
  25. #include <linux/mmc/host.h>
  26. #include <asm/gpio.h>
  27. #include <mach/gpio-tegra.h>
  28. #include <mach/sdhci.h>
  29. #include "sdhci-pltfm.h"
  30. /* Tegra SDHOST controller vendor register definitions */
  31. #define SDHCI_TEGRA_VENDOR_MISC_CTRL 0x120
  32. #define SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 0x20
  33. #define NVQUIRK_FORCE_SDHCI_SPEC_200 BIT(0)
  34. #define NVQUIRK_ENABLE_BLOCK_GAP_DET BIT(1)
  35. #define NVQUIRK_ENABLE_SDHCI_SPEC_300 BIT(2)
  36. struct sdhci_tegra_soc_data {
  37. struct sdhci_pltfm_data *pdata;
  38. u32 nvquirks;
  39. };
  40. struct sdhci_tegra {
  41. const struct tegra_sdhci_platform_data *plat;
  42. const struct sdhci_tegra_soc_data *soc_data;
  43. };
  44. static u32 tegra_sdhci_readl(struct sdhci_host *host, int reg)
  45. {
  46. u32 val;
  47. if (unlikely(reg == SDHCI_PRESENT_STATE)) {
  48. /* Use wp_gpio here instead? */
  49. val = readl(host->ioaddr + reg);
  50. return val | SDHCI_WRITE_PROTECT;
  51. }
  52. return readl(host->ioaddr + reg);
  53. }
  54. static u16 tegra_sdhci_readw(struct sdhci_host *host, int reg)
  55. {
  56. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  57. struct sdhci_tegra *tegra_host = pltfm_host->priv;
  58. const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
  59. if (unlikely((soc_data->nvquirks & NVQUIRK_FORCE_SDHCI_SPEC_200) &&
  60. (reg == SDHCI_HOST_VERSION))) {
  61. /* Erratum: Version register is invalid in HW. */
  62. return SDHCI_SPEC_200;
  63. }
  64. return readw(host->ioaddr + reg);
  65. }
  66. static void tegra_sdhci_writel(struct sdhci_host *host, u32 val, int reg)
  67. {
  68. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  69. struct sdhci_tegra *tegra_host = pltfm_host->priv;
  70. const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
  71. /* Seems like we're getting spurious timeout and crc errors, so
  72. * disable signalling of them. In case of real errors software
  73. * timers should take care of eventually detecting them.
  74. */
  75. if (unlikely(reg == SDHCI_SIGNAL_ENABLE))
  76. val &= ~(SDHCI_INT_TIMEOUT|SDHCI_INT_CRC);
  77. writel(val, host->ioaddr + reg);
  78. if (unlikely((soc_data->nvquirks & NVQUIRK_ENABLE_BLOCK_GAP_DET) &&
  79. (reg == SDHCI_INT_ENABLE))) {
  80. /* Erratum: Must enable block gap interrupt detection */
  81. u8 gap_ctrl = readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL);
  82. if (val & SDHCI_INT_CARD_INT)
  83. gap_ctrl |= 0x8;
  84. else
  85. gap_ctrl &= ~0x8;
  86. writeb(gap_ctrl, host->ioaddr + SDHCI_BLOCK_GAP_CONTROL);
  87. }
  88. }
  89. static unsigned int tegra_sdhci_get_ro(struct sdhci_host *host)
  90. {
  91. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  92. struct sdhci_tegra *tegra_host = pltfm_host->priv;
  93. const struct tegra_sdhci_platform_data *plat = tegra_host->plat;
  94. if (!gpio_is_valid(plat->wp_gpio))
  95. return -1;
  96. return gpio_get_value(plat->wp_gpio);
  97. }
  98. static irqreturn_t carddetect_irq(int irq, void *data)
  99. {
  100. struct sdhci_host *sdhost = (struct sdhci_host *)data;
  101. tasklet_schedule(&sdhost->card_tasklet);
  102. return IRQ_HANDLED;
  103. };
  104. static void tegra_sdhci_reset_exit(struct sdhci_host *host, u8 mask)
  105. {
  106. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  107. struct sdhci_tegra *tegra_host = pltfm_host->priv;
  108. const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
  109. if (!(mask & SDHCI_RESET_ALL))
  110. return;
  111. /* Erratum: Enable SDHCI spec v3.00 support */
  112. if (soc_data->nvquirks & NVQUIRK_ENABLE_SDHCI_SPEC_300) {
  113. u32 misc_ctrl;
  114. misc_ctrl = sdhci_readb(host, SDHCI_TEGRA_VENDOR_MISC_CTRL);
  115. misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300;
  116. sdhci_writeb(host, misc_ctrl, SDHCI_TEGRA_VENDOR_MISC_CTRL);
  117. }
  118. }
  119. static int tegra_sdhci_8bit(struct sdhci_host *host, int bus_width)
  120. {
  121. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  122. struct sdhci_tegra *tegra_host = pltfm_host->priv;
  123. const struct tegra_sdhci_platform_data *plat = tegra_host->plat;
  124. u32 ctrl;
  125. ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
  126. if (plat->is_8bit && bus_width == MMC_BUS_WIDTH_8) {
  127. ctrl &= ~SDHCI_CTRL_4BITBUS;
  128. ctrl |= SDHCI_CTRL_8BITBUS;
  129. } else {
  130. ctrl &= ~SDHCI_CTRL_8BITBUS;
  131. if (bus_width == MMC_BUS_WIDTH_4)
  132. ctrl |= SDHCI_CTRL_4BITBUS;
  133. else
  134. ctrl &= ~SDHCI_CTRL_4BITBUS;
  135. }
  136. sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
  137. return 0;
  138. }
  139. static struct sdhci_ops tegra_sdhci_ops = {
  140. .get_ro = tegra_sdhci_get_ro,
  141. .read_l = tegra_sdhci_readl,
  142. .read_w = tegra_sdhci_readw,
  143. .write_l = tegra_sdhci_writel,
  144. .platform_8bit_width = tegra_sdhci_8bit,
  145. .platform_reset_exit = tegra_sdhci_reset_exit,
  146. };
  147. #ifdef CONFIG_ARCH_TEGRA_2x_SOC
  148. static struct sdhci_pltfm_data sdhci_tegra20_pdata = {
  149. .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
  150. SDHCI_QUIRK_SINGLE_POWER_WRITE |
  151. SDHCI_QUIRK_NO_HISPD_BIT |
  152. SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC,
  153. .ops = &tegra_sdhci_ops,
  154. };
  155. static struct sdhci_tegra_soc_data soc_data_tegra20 = {
  156. .pdata = &sdhci_tegra20_pdata,
  157. .nvquirks = NVQUIRK_FORCE_SDHCI_SPEC_200 |
  158. NVQUIRK_ENABLE_BLOCK_GAP_DET,
  159. };
  160. #endif
  161. #ifdef CONFIG_ARCH_TEGRA_3x_SOC
  162. static struct sdhci_pltfm_data sdhci_tegra30_pdata = {
  163. .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
  164. SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
  165. SDHCI_QUIRK_SINGLE_POWER_WRITE |
  166. SDHCI_QUIRK_NO_HISPD_BIT |
  167. SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC,
  168. .ops = &tegra_sdhci_ops,
  169. };
  170. static struct sdhci_tegra_soc_data soc_data_tegra30 = {
  171. .pdata = &sdhci_tegra30_pdata,
  172. .nvquirks = NVQUIRK_ENABLE_SDHCI_SPEC_300,
  173. };
  174. #endif
  175. static const struct of_device_id sdhci_tegra_dt_match[] __devinitdata = {
  176. #ifdef CONFIG_ARCH_TEGRA_3x_SOC
  177. { .compatible = "nvidia,tegra30-sdhci", .data = &soc_data_tegra30 },
  178. #endif
  179. #ifdef CONFIG_ARCH_TEGRA_2x_SOC
  180. { .compatible = "nvidia,tegra20-sdhci", .data = &soc_data_tegra20 },
  181. #endif
  182. {}
  183. };
  184. MODULE_DEVICE_TABLE(of, sdhci_dt_ids);
  185. static struct tegra_sdhci_platform_data * __devinit sdhci_tegra_dt_parse_pdata(
  186. struct platform_device *pdev)
  187. {
  188. struct tegra_sdhci_platform_data *plat;
  189. struct device_node *np = pdev->dev.of_node;
  190. if (!np)
  191. return NULL;
  192. plat = devm_kzalloc(&pdev->dev, sizeof(*plat), GFP_KERNEL);
  193. if (!plat) {
  194. dev_err(&pdev->dev, "Can't allocate platform data\n");
  195. return NULL;
  196. }
  197. plat->cd_gpio = of_get_named_gpio(np, "cd-gpios", 0);
  198. plat->wp_gpio = of_get_named_gpio(np, "wp-gpios", 0);
  199. plat->power_gpio = of_get_named_gpio(np, "power-gpios", 0);
  200. if (of_find_property(np, "support-8bit", NULL))
  201. plat->is_8bit = 1;
  202. return plat;
  203. }
  204. static int __devinit sdhci_tegra_probe(struct platform_device *pdev)
  205. {
  206. const struct of_device_id *match;
  207. const struct sdhci_tegra_soc_data *soc_data;
  208. struct sdhci_host *host;
  209. struct sdhci_pltfm_host *pltfm_host;
  210. struct tegra_sdhci_platform_data *plat;
  211. struct sdhci_tegra *tegra_host;
  212. struct clk *clk;
  213. int rc;
  214. match = of_match_device(sdhci_tegra_dt_match, &pdev->dev);
  215. if (match)
  216. soc_data = match->data;
  217. else
  218. soc_data = &soc_data_tegra20;
  219. host = sdhci_pltfm_init(pdev, soc_data->pdata);
  220. if (IS_ERR(host))
  221. return PTR_ERR(host);
  222. pltfm_host = sdhci_priv(host);
  223. plat = pdev->dev.platform_data;
  224. if (plat == NULL)
  225. plat = sdhci_tegra_dt_parse_pdata(pdev);
  226. if (plat == NULL) {
  227. dev_err(mmc_dev(host->mmc), "missing platform data\n");
  228. rc = -ENXIO;
  229. goto err_no_plat;
  230. }
  231. tegra_host = devm_kzalloc(&pdev->dev, sizeof(*tegra_host), GFP_KERNEL);
  232. if (!tegra_host) {
  233. dev_err(mmc_dev(host->mmc), "failed to allocate tegra_host\n");
  234. rc = -ENOMEM;
  235. goto err_no_plat;
  236. }
  237. tegra_host->plat = plat;
  238. tegra_host->soc_data = soc_data;
  239. pltfm_host->priv = tegra_host;
  240. if (gpio_is_valid(plat->power_gpio)) {
  241. rc = gpio_request(plat->power_gpio, "sdhci_power");
  242. if (rc) {
  243. dev_err(mmc_dev(host->mmc),
  244. "failed to allocate power gpio\n");
  245. goto err_power_req;
  246. }
  247. gpio_direction_output(plat->power_gpio, 1);
  248. }
  249. if (gpio_is_valid(plat->cd_gpio)) {
  250. rc = gpio_request(plat->cd_gpio, "sdhci_cd");
  251. if (rc) {
  252. dev_err(mmc_dev(host->mmc),
  253. "failed to allocate cd gpio\n");
  254. goto err_cd_req;
  255. }
  256. gpio_direction_input(plat->cd_gpio);
  257. rc = request_irq(gpio_to_irq(plat->cd_gpio), carddetect_irq,
  258. IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
  259. mmc_hostname(host->mmc), host);
  260. if (rc) {
  261. dev_err(mmc_dev(host->mmc), "request irq error\n");
  262. goto err_cd_irq_req;
  263. }
  264. }
  265. if (gpio_is_valid(plat->wp_gpio)) {
  266. rc = gpio_request(plat->wp_gpio, "sdhci_wp");
  267. if (rc) {
  268. dev_err(mmc_dev(host->mmc),
  269. "failed to allocate wp gpio\n");
  270. goto err_wp_req;
  271. }
  272. gpio_direction_input(plat->wp_gpio);
  273. }
  274. clk = clk_get(mmc_dev(host->mmc), NULL);
  275. if (IS_ERR(clk)) {
  276. dev_err(mmc_dev(host->mmc), "clk err\n");
  277. rc = PTR_ERR(clk);
  278. goto err_clk_get;
  279. }
  280. clk_enable(clk);
  281. pltfm_host->clk = clk;
  282. host->mmc->pm_caps = plat->pm_flags;
  283. if (plat->is_8bit)
  284. host->mmc->caps |= MMC_CAP_8_BIT_DATA;
  285. rc = sdhci_add_host(host);
  286. if (rc)
  287. goto err_add_host;
  288. return 0;
  289. err_add_host:
  290. clk_disable(pltfm_host->clk);
  291. clk_put(pltfm_host->clk);
  292. err_clk_get:
  293. if (gpio_is_valid(plat->wp_gpio))
  294. gpio_free(plat->wp_gpio);
  295. err_wp_req:
  296. if (gpio_is_valid(plat->cd_gpio))
  297. free_irq(gpio_to_irq(plat->cd_gpio), host);
  298. err_cd_irq_req:
  299. if (gpio_is_valid(plat->cd_gpio))
  300. gpio_free(plat->cd_gpio);
  301. err_cd_req:
  302. if (gpio_is_valid(plat->power_gpio))
  303. gpio_free(plat->power_gpio);
  304. err_power_req:
  305. err_no_plat:
  306. sdhci_pltfm_free(pdev);
  307. return rc;
  308. }
  309. static int __devexit sdhci_tegra_remove(struct platform_device *pdev)
  310. {
  311. struct sdhci_host *host = platform_get_drvdata(pdev);
  312. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  313. struct sdhci_tegra *tegra_host = pltfm_host->priv;
  314. const struct tegra_sdhci_platform_data *plat = tegra_host->plat;
  315. int dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff);
  316. sdhci_remove_host(host, dead);
  317. if (gpio_is_valid(plat->wp_gpio))
  318. gpio_free(plat->wp_gpio);
  319. if (gpio_is_valid(plat->cd_gpio)) {
  320. free_irq(gpio_to_irq(plat->cd_gpio), host);
  321. gpio_free(plat->cd_gpio);
  322. }
  323. if (gpio_is_valid(plat->power_gpio))
  324. gpio_free(plat->power_gpio);
  325. clk_disable(pltfm_host->clk);
  326. clk_put(pltfm_host->clk);
  327. sdhci_pltfm_free(pdev);
  328. return 0;
  329. }
  330. static struct platform_driver sdhci_tegra_driver = {
  331. .driver = {
  332. .name = "sdhci-tegra",
  333. .owner = THIS_MODULE,
  334. .of_match_table = sdhci_tegra_dt_match,
  335. .pm = SDHCI_PLTFM_PMOPS,
  336. },
  337. .probe = sdhci_tegra_probe,
  338. .remove = __devexit_p(sdhci_tegra_remove),
  339. };
  340. module_platform_driver(sdhci_tegra_driver);
  341. MODULE_DESCRIPTION("SDHCI driver for Tegra");
  342. MODULE_AUTHOR("Google, Inc.");
  343. MODULE_LICENSE("GPL v2");