pt1.c 25 KB

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  1. /*
  2. * driver for Earthsoft PT1/PT2
  3. *
  4. * Copyright (C) 2009 HIRANO Takahito <hiranotaka@zng.info>
  5. *
  6. * based on pt1dvr - http://pt1dvr.sourceforge.jp/
  7. * by Tomoaki Ishikawa <tomy@users.sourceforge.jp>
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License as published by
  11. * the Free Software Foundation; either version 2 of the License, or
  12. * (at your option) any later version.
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this program; if not, write to the Free Software
  21. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  22. */
  23. #include <linux/kernel.h>
  24. #include <linux/module.h>
  25. #include <linux/slab.h>
  26. #include <linux/vmalloc.h>
  27. #include <linux/pci.h>
  28. #include <linux/kthread.h>
  29. #include <linux/freezer.h>
  30. #include <linux/ratelimit.h>
  31. #include "dvbdev.h"
  32. #include "dvb_demux.h"
  33. #include "dmxdev.h"
  34. #include "dvb_net.h"
  35. #include "dvb_frontend.h"
  36. #include "va1j5jf8007t.h"
  37. #include "va1j5jf8007s.h"
  38. #define DRIVER_NAME "earth-pt1"
  39. #define PT1_PAGE_SHIFT 12
  40. #define PT1_PAGE_SIZE (1 << PT1_PAGE_SHIFT)
  41. #define PT1_NR_UPACKETS 1024
  42. #define PT1_NR_BUFS 511
  43. struct pt1_buffer_page {
  44. __le32 upackets[PT1_NR_UPACKETS];
  45. };
  46. struct pt1_table_page {
  47. __le32 next_pfn;
  48. __le32 buf_pfns[PT1_NR_BUFS];
  49. };
  50. struct pt1_buffer {
  51. struct pt1_buffer_page *page;
  52. dma_addr_t addr;
  53. };
  54. struct pt1_table {
  55. struct pt1_table_page *page;
  56. dma_addr_t addr;
  57. struct pt1_buffer bufs[PT1_NR_BUFS];
  58. };
  59. #define PT1_NR_ADAPS 4
  60. struct pt1_adapter;
  61. struct pt1 {
  62. struct pci_dev *pdev;
  63. void __iomem *regs;
  64. struct i2c_adapter i2c_adap;
  65. int i2c_running;
  66. struct pt1_adapter *adaps[PT1_NR_ADAPS];
  67. struct pt1_table *tables;
  68. struct task_struct *kthread;
  69. int table_index;
  70. int buf_index;
  71. struct mutex lock;
  72. int power;
  73. int reset;
  74. };
  75. struct pt1_adapter {
  76. struct pt1 *pt1;
  77. int index;
  78. u8 *buf;
  79. int upacket_count;
  80. int packet_count;
  81. int st_count;
  82. struct dvb_adapter adap;
  83. struct dvb_demux demux;
  84. int users;
  85. struct dmxdev dmxdev;
  86. struct dvb_frontend *fe;
  87. int (*orig_set_voltage)(struct dvb_frontend *fe,
  88. fe_sec_voltage_t voltage);
  89. int (*orig_sleep)(struct dvb_frontend *fe);
  90. int (*orig_init)(struct dvb_frontend *fe);
  91. fe_sec_voltage_t voltage;
  92. int sleep;
  93. };
  94. #define pt1_printk(level, pt1, format, arg...) \
  95. dev_printk(level, &(pt1)->pdev->dev, format, ##arg)
  96. static void pt1_write_reg(struct pt1 *pt1, int reg, u32 data)
  97. {
  98. writel(data, pt1->regs + reg * 4);
  99. }
  100. static u32 pt1_read_reg(struct pt1 *pt1, int reg)
  101. {
  102. return readl(pt1->regs + reg * 4);
  103. }
  104. static int pt1_nr_tables = 8;
  105. module_param_named(nr_tables, pt1_nr_tables, int, 0);
  106. static void pt1_increment_table_count(struct pt1 *pt1)
  107. {
  108. pt1_write_reg(pt1, 0, 0x00000020);
  109. }
  110. static void pt1_init_table_count(struct pt1 *pt1)
  111. {
  112. pt1_write_reg(pt1, 0, 0x00000010);
  113. }
  114. static void pt1_register_tables(struct pt1 *pt1, u32 first_pfn)
  115. {
  116. pt1_write_reg(pt1, 5, first_pfn);
  117. pt1_write_reg(pt1, 0, 0x0c000040);
  118. }
  119. static void pt1_unregister_tables(struct pt1 *pt1)
  120. {
  121. pt1_write_reg(pt1, 0, 0x08080000);
  122. }
  123. static int pt1_sync(struct pt1 *pt1)
  124. {
  125. int i;
  126. for (i = 0; i < 57; i++) {
  127. if (pt1_read_reg(pt1, 0) & 0x20000000)
  128. return 0;
  129. pt1_write_reg(pt1, 0, 0x00000008);
  130. }
  131. pt1_printk(KERN_ERR, pt1, "could not sync\n");
  132. return -EIO;
  133. }
  134. static u64 pt1_identify(struct pt1 *pt1)
  135. {
  136. int i;
  137. u64 id;
  138. id = 0;
  139. for (i = 0; i < 57; i++) {
  140. id |= (u64)(pt1_read_reg(pt1, 0) >> 30 & 1) << i;
  141. pt1_write_reg(pt1, 0, 0x00000008);
  142. }
  143. return id;
  144. }
  145. static int pt1_unlock(struct pt1 *pt1)
  146. {
  147. int i;
  148. pt1_write_reg(pt1, 0, 0x00000008);
  149. for (i = 0; i < 3; i++) {
  150. if (pt1_read_reg(pt1, 0) & 0x80000000)
  151. return 0;
  152. schedule_timeout_uninterruptible((HZ + 999) / 1000);
  153. }
  154. pt1_printk(KERN_ERR, pt1, "could not unlock\n");
  155. return -EIO;
  156. }
  157. static int pt1_reset_pci(struct pt1 *pt1)
  158. {
  159. int i;
  160. pt1_write_reg(pt1, 0, 0x01010000);
  161. pt1_write_reg(pt1, 0, 0x01000000);
  162. for (i = 0; i < 10; i++) {
  163. if (pt1_read_reg(pt1, 0) & 0x00000001)
  164. return 0;
  165. schedule_timeout_uninterruptible((HZ + 999) / 1000);
  166. }
  167. pt1_printk(KERN_ERR, pt1, "could not reset PCI\n");
  168. return -EIO;
  169. }
  170. static int pt1_reset_ram(struct pt1 *pt1)
  171. {
  172. int i;
  173. pt1_write_reg(pt1, 0, 0x02020000);
  174. pt1_write_reg(pt1, 0, 0x02000000);
  175. for (i = 0; i < 10; i++) {
  176. if (pt1_read_reg(pt1, 0) & 0x00000002)
  177. return 0;
  178. schedule_timeout_uninterruptible((HZ + 999) / 1000);
  179. }
  180. pt1_printk(KERN_ERR, pt1, "could not reset RAM\n");
  181. return -EIO;
  182. }
  183. static int pt1_do_enable_ram(struct pt1 *pt1)
  184. {
  185. int i, j;
  186. u32 status;
  187. status = pt1_read_reg(pt1, 0) & 0x00000004;
  188. pt1_write_reg(pt1, 0, 0x00000002);
  189. for (i = 0; i < 10; i++) {
  190. for (j = 0; j < 1024; j++) {
  191. if ((pt1_read_reg(pt1, 0) & 0x00000004) != status)
  192. return 0;
  193. }
  194. schedule_timeout_uninterruptible((HZ + 999) / 1000);
  195. }
  196. pt1_printk(KERN_ERR, pt1, "could not enable RAM\n");
  197. return -EIO;
  198. }
  199. static int pt1_enable_ram(struct pt1 *pt1)
  200. {
  201. int i, ret;
  202. int phase;
  203. schedule_timeout_uninterruptible((HZ + 999) / 1000);
  204. phase = pt1->pdev->device == 0x211a ? 128 : 166;
  205. for (i = 0; i < phase; i++) {
  206. ret = pt1_do_enable_ram(pt1);
  207. if (ret < 0)
  208. return ret;
  209. }
  210. return 0;
  211. }
  212. static void pt1_disable_ram(struct pt1 *pt1)
  213. {
  214. pt1_write_reg(pt1, 0, 0x0b0b0000);
  215. }
  216. static void pt1_set_stream(struct pt1 *pt1, int index, int enabled)
  217. {
  218. pt1_write_reg(pt1, 2, 1 << (index + 8) | enabled << index);
  219. }
  220. static void pt1_init_streams(struct pt1 *pt1)
  221. {
  222. int i;
  223. for (i = 0; i < PT1_NR_ADAPS; i++)
  224. pt1_set_stream(pt1, i, 0);
  225. }
  226. static int pt1_filter(struct pt1 *pt1, struct pt1_buffer_page *page)
  227. {
  228. u32 upacket;
  229. int i;
  230. int index;
  231. struct pt1_adapter *adap;
  232. int offset;
  233. u8 *buf;
  234. int sc;
  235. if (!page->upackets[PT1_NR_UPACKETS - 1])
  236. return 0;
  237. for (i = 0; i < PT1_NR_UPACKETS; i++) {
  238. upacket = le32_to_cpu(page->upackets[i]);
  239. index = (upacket >> 29) - 1;
  240. if (index < 0 || index >= PT1_NR_ADAPS)
  241. continue;
  242. adap = pt1->adaps[index];
  243. if (upacket >> 25 & 1)
  244. adap->upacket_count = 0;
  245. else if (!adap->upacket_count)
  246. continue;
  247. if (upacket >> 24 & 1)
  248. printk_ratelimited(KERN_INFO "earth-pt1: device "
  249. "buffer overflowing. table[%d] buf[%d]\n",
  250. pt1->table_index, pt1->buf_index);
  251. sc = upacket >> 26 & 0x7;
  252. if (adap->st_count != -1 && sc != ((adap->st_count + 1) & 0x7))
  253. printk_ratelimited(KERN_INFO "earth-pt1: data loss"
  254. " in streamID(adapter)[%d]\n", index);
  255. adap->st_count = sc;
  256. buf = adap->buf;
  257. offset = adap->packet_count * 188 + adap->upacket_count * 3;
  258. buf[offset] = upacket >> 16;
  259. buf[offset + 1] = upacket >> 8;
  260. if (adap->upacket_count != 62)
  261. buf[offset + 2] = upacket;
  262. if (++adap->upacket_count >= 63) {
  263. adap->upacket_count = 0;
  264. if (++adap->packet_count >= 21) {
  265. dvb_dmx_swfilter_packets(&adap->demux, buf, 21);
  266. adap->packet_count = 0;
  267. }
  268. }
  269. }
  270. page->upackets[PT1_NR_UPACKETS - 1] = 0;
  271. return 1;
  272. }
  273. static int pt1_thread(void *data)
  274. {
  275. struct pt1 *pt1;
  276. struct pt1_buffer_page *page;
  277. pt1 = data;
  278. set_freezable();
  279. while (!kthread_should_stop()) {
  280. try_to_freeze();
  281. page = pt1->tables[pt1->table_index].bufs[pt1->buf_index].page;
  282. if (!pt1_filter(pt1, page)) {
  283. schedule_timeout_interruptible((HZ + 999) / 1000);
  284. continue;
  285. }
  286. if (++pt1->buf_index >= PT1_NR_BUFS) {
  287. pt1_increment_table_count(pt1);
  288. pt1->buf_index = 0;
  289. if (++pt1->table_index >= pt1_nr_tables)
  290. pt1->table_index = 0;
  291. }
  292. }
  293. return 0;
  294. }
  295. static void pt1_free_page(struct pt1 *pt1, void *page, dma_addr_t addr)
  296. {
  297. dma_free_coherent(&pt1->pdev->dev, PT1_PAGE_SIZE, page, addr);
  298. }
  299. static void *pt1_alloc_page(struct pt1 *pt1, dma_addr_t *addrp, u32 *pfnp)
  300. {
  301. void *page;
  302. dma_addr_t addr;
  303. page = dma_alloc_coherent(&pt1->pdev->dev, PT1_PAGE_SIZE, &addr,
  304. GFP_KERNEL);
  305. if (page == NULL)
  306. return NULL;
  307. BUG_ON(addr & (PT1_PAGE_SIZE - 1));
  308. BUG_ON(addr >> PT1_PAGE_SHIFT >> 31 >> 1);
  309. *addrp = addr;
  310. *pfnp = addr >> PT1_PAGE_SHIFT;
  311. return page;
  312. }
  313. static void pt1_cleanup_buffer(struct pt1 *pt1, struct pt1_buffer *buf)
  314. {
  315. pt1_free_page(pt1, buf->page, buf->addr);
  316. }
  317. static int
  318. pt1_init_buffer(struct pt1 *pt1, struct pt1_buffer *buf, u32 *pfnp)
  319. {
  320. struct pt1_buffer_page *page;
  321. dma_addr_t addr;
  322. page = pt1_alloc_page(pt1, &addr, pfnp);
  323. if (page == NULL)
  324. return -ENOMEM;
  325. page->upackets[PT1_NR_UPACKETS - 1] = 0;
  326. buf->page = page;
  327. buf->addr = addr;
  328. return 0;
  329. }
  330. static void pt1_cleanup_table(struct pt1 *pt1, struct pt1_table *table)
  331. {
  332. int i;
  333. for (i = 0; i < PT1_NR_BUFS; i++)
  334. pt1_cleanup_buffer(pt1, &table->bufs[i]);
  335. pt1_free_page(pt1, table->page, table->addr);
  336. }
  337. static int
  338. pt1_init_table(struct pt1 *pt1, struct pt1_table *table, u32 *pfnp)
  339. {
  340. struct pt1_table_page *page;
  341. dma_addr_t addr;
  342. int i, ret;
  343. u32 buf_pfn;
  344. page = pt1_alloc_page(pt1, &addr, pfnp);
  345. if (page == NULL)
  346. return -ENOMEM;
  347. for (i = 0; i < PT1_NR_BUFS; i++) {
  348. ret = pt1_init_buffer(pt1, &table->bufs[i], &buf_pfn);
  349. if (ret < 0)
  350. goto err;
  351. page->buf_pfns[i] = cpu_to_le32(buf_pfn);
  352. }
  353. pt1_increment_table_count(pt1);
  354. table->page = page;
  355. table->addr = addr;
  356. return 0;
  357. err:
  358. while (i--)
  359. pt1_cleanup_buffer(pt1, &table->bufs[i]);
  360. pt1_free_page(pt1, page, addr);
  361. return ret;
  362. }
  363. static void pt1_cleanup_tables(struct pt1 *pt1)
  364. {
  365. struct pt1_table *tables;
  366. int i;
  367. tables = pt1->tables;
  368. pt1_unregister_tables(pt1);
  369. for (i = 0; i < pt1_nr_tables; i++)
  370. pt1_cleanup_table(pt1, &tables[i]);
  371. vfree(tables);
  372. }
  373. static int pt1_init_tables(struct pt1 *pt1)
  374. {
  375. struct pt1_table *tables;
  376. int i, ret;
  377. u32 first_pfn, pfn;
  378. tables = vmalloc(sizeof(struct pt1_table) * pt1_nr_tables);
  379. if (tables == NULL)
  380. return -ENOMEM;
  381. pt1_init_table_count(pt1);
  382. i = 0;
  383. if (pt1_nr_tables) {
  384. ret = pt1_init_table(pt1, &tables[0], &first_pfn);
  385. if (ret)
  386. goto err;
  387. i++;
  388. }
  389. while (i < pt1_nr_tables) {
  390. ret = pt1_init_table(pt1, &tables[i], &pfn);
  391. if (ret)
  392. goto err;
  393. tables[i - 1].page->next_pfn = cpu_to_le32(pfn);
  394. i++;
  395. }
  396. tables[pt1_nr_tables - 1].page->next_pfn = cpu_to_le32(first_pfn);
  397. pt1_register_tables(pt1, first_pfn);
  398. pt1->tables = tables;
  399. return 0;
  400. err:
  401. while (i--)
  402. pt1_cleanup_table(pt1, &tables[i]);
  403. vfree(tables);
  404. return ret;
  405. }
  406. static int pt1_start_polling(struct pt1 *pt1)
  407. {
  408. int ret = 0;
  409. mutex_lock(&pt1->lock);
  410. if (!pt1->kthread) {
  411. pt1->kthread = kthread_run(pt1_thread, pt1, "earth-pt1");
  412. if (IS_ERR(pt1->kthread)) {
  413. ret = PTR_ERR(pt1->kthread);
  414. pt1->kthread = NULL;
  415. }
  416. }
  417. mutex_unlock(&pt1->lock);
  418. return ret;
  419. }
  420. static int pt1_start_feed(struct dvb_demux_feed *feed)
  421. {
  422. struct pt1_adapter *adap;
  423. adap = container_of(feed->demux, struct pt1_adapter, demux);
  424. if (!adap->users++) {
  425. int ret;
  426. ret = pt1_start_polling(adap->pt1);
  427. if (ret)
  428. return ret;
  429. pt1_set_stream(adap->pt1, adap->index, 1);
  430. }
  431. return 0;
  432. }
  433. static void pt1_stop_polling(struct pt1 *pt1)
  434. {
  435. int i, count;
  436. mutex_lock(&pt1->lock);
  437. for (i = 0, count = 0; i < PT1_NR_ADAPS; i++)
  438. count += pt1->adaps[i]->users;
  439. if (count == 0 && pt1->kthread) {
  440. kthread_stop(pt1->kthread);
  441. pt1->kthread = NULL;
  442. }
  443. mutex_unlock(&pt1->lock);
  444. }
  445. static int pt1_stop_feed(struct dvb_demux_feed *feed)
  446. {
  447. struct pt1_adapter *adap;
  448. adap = container_of(feed->demux, struct pt1_adapter, demux);
  449. if (!--adap->users) {
  450. pt1_set_stream(adap->pt1, adap->index, 0);
  451. pt1_stop_polling(adap->pt1);
  452. }
  453. return 0;
  454. }
  455. static void
  456. pt1_update_power(struct pt1 *pt1)
  457. {
  458. int bits;
  459. int i;
  460. struct pt1_adapter *adap;
  461. static const int sleep_bits[] = {
  462. 1 << 4,
  463. 1 << 6 | 1 << 7,
  464. 1 << 5,
  465. 1 << 6 | 1 << 8,
  466. };
  467. bits = pt1->power | !pt1->reset << 3;
  468. mutex_lock(&pt1->lock);
  469. for (i = 0; i < PT1_NR_ADAPS; i++) {
  470. adap = pt1->adaps[i];
  471. switch (adap->voltage) {
  472. case SEC_VOLTAGE_13: /* actually 11V */
  473. bits |= 1 << 1;
  474. break;
  475. case SEC_VOLTAGE_18: /* actually 15V */
  476. bits |= 1 << 1 | 1 << 2;
  477. break;
  478. default:
  479. break;
  480. }
  481. /* XXX: The bits should be changed depending on adap->sleep. */
  482. bits |= sleep_bits[i];
  483. }
  484. pt1_write_reg(pt1, 1, bits);
  485. mutex_unlock(&pt1->lock);
  486. }
  487. static int pt1_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t voltage)
  488. {
  489. struct pt1_adapter *adap;
  490. adap = container_of(fe->dvb, struct pt1_adapter, adap);
  491. adap->voltage = voltage;
  492. pt1_update_power(adap->pt1);
  493. if (adap->orig_set_voltage)
  494. return adap->orig_set_voltage(fe, voltage);
  495. else
  496. return 0;
  497. }
  498. static int pt1_sleep(struct dvb_frontend *fe)
  499. {
  500. struct pt1_adapter *adap;
  501. adap = container_of(fe->dvb, struct pt1_adapter, adap);
  502. adap->sleep = 1;
  503. pt1_update_power(adap->pt1);
  504. if (adap->orig_sleep)
  505. return adap->orig_sleep(fe);
  506. else
  507. return 0;
  508. }
  509. static int pt1_wakeup(struct dvb_frontend *fe)
  510. {
  511. struct pt1_adapter *adap;
  512. adap = container_of(fe->dvb, struct pt1_adapter, adap);
  513. adap->sleep = 0;
  514. pt1_update_power(adap->pt1);
  515. schedule_timeout_uninterruptible((HZ + 999) / 1000);
  516. if (adap->orig_init)
  517. return adap->orig_init(fe);
  518. else
  519. return 0;
  520. }
  521. static void pt1_free_adapter(struct pt1_adapter *adap)
  522. {
  523. adap->demux.dmx.close(&adap->demux.dmx);
  524. dvb_dmxdev_release(&adap->dmxdev);
  525. dvb_dmx_release(&adap->demux);
  526. dvb_unregister_adapter(&adap->adap);
  527. free_page((unsigned long)adap->buf);
  528. kfree(adap);
  529. }
  530. DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
  531. static struct pt1_adapter *
  532. pt1_alloc_adapter(struct pt1 *pt1)
  533. {
  534. struct pt1_adapter *adap;
  535. void *buf;
  536. struct dvb_adapter *dvb_adap;
  537. struct dvb_demux *demux;
  538. struct dmxdev *dmxdev;
  539. int ret;
  540. adap = kzalloc(sizeof(struct pt1_adapter), GFP_KERNEL);
  541. if (!adap) {
  542. ret = -ENOMEM;
  543. goto err;
  544. }
  545. adap->pt1 = pt1;
  546. adap->voltage = SEC_VOLTAGE_OFF;
  547. adap->sleep = 1;
  548. buf = (u8 *)__get_free_page(GFP_KERNEL);
  549. if (!buf) {
  550. ret = -ENOMEM;
  551. goto err_kfree;
  552. }
  553. adap->buf = buf;
  554. adap->upacket_count = 0;
  555. adap->packet_count = 0;
  556. adap->st_count = -1;
  557. dvb_adap = &adap->adap;
  558. dvb_adap->priv = adap;
  559. ret = dvb_register_adapter(dvb_adap, DRIVER_NAME, THIS_MODULE,
  560. &pt1->pdev->dev, adapter_nr);
  561. if (ret < 0)
  562. goto err_free_page;
  563. demux = &adap->demux;
  564. demux->dmx.capabilities = DMX_TS_FILTERING | DMX_SECTION_FILTERING;
  565. demux->priv = adap;
  566. demux->feednum = 256;
  567. demux->filternum = 256;
  568. demux->start_feed = pt1_start_feed;
  569. demux->stop_feed = pt1_stop_feed;
  570. demux->write_to_decoder = NULL;
  571. ret = dvb_dmx_init(demux);
  572. if (ret < 0)
  573. goto err_unregister_adapter;
  574. dmxdev = &adap->dmxdev;
  575. dmxdev->filternum = 256;
  576. dmxdev->demux = &demux->dmx;
  577. dmxdev->capabilities = 0;
  578. ret = dvb_dmxdev_init(dmxdev, dvb_adap);
  579. if (ret < 0)
  580. goto err_dmx_release;
  581. return adap;
  582. err_dmx_release:
  583. dvb_dmx_release(demux);
  584. err_unregister_adapter:
  585. dvb_unregister_adapter(dvb_adap);
  586. err_free_page:
  587. free_page((unsigned long)buf);
  588. err_kfree:
  589. kfree(adap);
  590. err:
  591. return ERR_PTR(ret);
  592. }
  593. static void pt1_cleanup_adapters(struct pt1 *pt1)
  594. {
  595. int i;
  596. for (i = 0; i < PT1_NR_ADAPS; i++)
  597. pt1_free_adapter(pt1->adaps[i]);
  598. }
  599. static int pt1_init_adapters(struct pt1 *pt1)
  600. {
  601. int i;
  602. struct pt1_adapter *adap;
  603. int ret;
  604. for (i = 0; i < PT1_NR_ADAPS; i++) {
  605. adap = pt1_alloc_adapter(pt1);
  606. if (IS_ERR(adap)) {
  607. ret = PTR_ERR(adap);
  608. goto err;
  609. }
  610. adap->index = i;
  611. pt1->adaps[i] = adap;
  612. }
  613. return 0;
  614. err:
  615. while (i--)
  616. pt1_free_adapter(pt1->adaps[i]);
  617. return ret;
  618. }
  619. static void pt1_cleanup_frontend(struct pt1_adapter *adap)
  620. {
  621. dvb_unregister_frontend(adap->fe);
  622. }
  623. static int pt1_init_frontend(struct pt1_adapter *adap, struct dvb_frontend *fe)
  624. {
  625. int ret;
  626. adap->orig_set_voltage = fe->ops.set_voltage;
  627. adap->orig_sleep = fe->ops.sleep;
  628. adap->orig_init = fe->ops.init;
  629. fe->ops.set_voltage = pt1_set_voltage;
  630. fe->ops.sleep = pt1_sleep;
  631. fe->ops.init = pt1_wakeup;
  632. ret = dvb_register_frontend(&adap->adap, fe);
  633. if (ret < 0)
  634. return ret;
  635. adap->fe = fe;
  636. return 0;
  637. }
  638. static void pt1_cleanup_frontends(struct pt1 *pt1)
  639. {
  640. int i;
  641. for (i = 0; i < PT1_NR_ADAPS; i++)
  642. pt1_cleanup_frontend(pt1->adaps[i]);
  643. }
  644. struct pt1_config {
  645. struct va1j5jf8007s_config va1j5jf8007s_config;
  646. struct va1j5jf8007t_config va1j5jf8007t_config;
  647. };
  648. static const struct pt1_config pt1_configs[2] = {
  649. {
  650. {
  651. .demod_address = 0x1b,
  652. .frequency = VA1J5JF8007S_20MHZ,
  653. },
  654. {
  655. .demod_address = 0x1a,
  656. .frequency = VA1J5JF8007T_20MHZ,
  657. },
  658. }, {
  659. {
  660. .demod_address = 0x19,
  661. .frequency = VA1J5JF8007S_20MHZ,
  662. },
  663. {
  664. .demod_address = 0x18,
  665. .frequency = VA1J5JF8007T_20MHZ,
  666. },
  667. },
  668. };
  669. static const struct pt1_config pt2_configs[2] = {
  670. {
  671. {
  672. .demod_address = 0x1b,
  673. .frequency = VA1J5JF8007S_25MHZ,
  674. },
  675. {
  676. .demod_address = 0x1a,
  677. .frequency = VA1J5JF8007T_25MHZ,
  678. },
  679. }, {
  680. {
  681. .demod_address = 0x19,
  682. .frequency = VA1J5JF8007S_25MHZ,
  683. },
  684. {
  685. .demod_address = 0x18,
  686. .frequency = VA1J5JF8007T_25MHZ,
  687. },
  688. },
  689. };
  690. static int pt1_init_frontends(struct pt1 *pt1)
  691. {
  692. int i, j;
  693. struct i2c_adapter *i2c_adap;
  694. const struct pt1_config *configs, *config;
  695. struct dvb_frontend *fe[4];
  696. int ret;
  697. i = 0;
  698. j = 0;
  699. i2c_adap = &pt1->i2c_adap;
  700. configs = pt1->pdev->device == 0x211a ? pt1_configs : pt2_configs;
  701. do {
  702. config = &configs[i / 2];
  703. fe[i] = va1j5jf8007s_attach(&config->va1j5jf8007s_config,
  704. i2c_adap);
  705. if (!fe[i]) {
  706. ret = -ENODEV; /* This does not sound nice... */
  707. goto err;
  708. }
  709. i++;
  710. fe[i] = va1j5jf8007t_attach(&config->va1j5jf8007t_config,
  711. i2c_adap);
  712. if (!fe[i]) {
  713. ret = -ENODEV;
  714. goto err;
  715. }
  716. i++;
  717. ret = va1j5jf8007s_prepare(fe[i - 2]);
  718. if (ret < 0)
  719. goto err;
  720. ret = va1j5jf8007t_prepare(fe[i - 1]);
  721. if (ret < 0)
  722. goto err;
  723. } while (i < 4);
  724. do {
  725. ret = pt1_init_frontend(pt1->adaps[j], fe[j]);
  726. if (ret < 0)
  727. goto err;
  728. } while (++j < 4);
  729. return 0;
  730. err:
  731. while (i-- > j)
  732. fe[i]->ops.release(fe[i]);
  733. while (j--)
  734. dvb_unregister_frontend(fe[j]);
  735. return ret;
  736. }
  737. static void pt1_i2c_emit(struct pt1 *pt1, int addr, int busy, int read_enable,
  738. int clock, int data, int next_addr)
  739. {
  740. pt1_write_reg(pt1, 4, addr << 18 | busy << 13 | read_enable << 12 |
  741. !clock << 11 | !data << 10 | next_addr);
  742. }
  743. static void pt1_i2c_write_bit(struct pt1 *pt1, int addr, int *addrp, int data)
  744. {
  745. pt1_i2c_emit(pt1, addr, 1, 0, 0, data, addr + 1);
  746. pt1_i2c_emit(pt1, addr + 1, 1, 0, 1, data, addr + 2);
  747. pt1_i2c_emit(pt1, addr + 2, 1, 0, 0, data, addr + 3);
  748. *addrp = addr + 3;
  749. }
  750. static void pt1_i2c_read_bit(struct pt1 *pt1, int addr, int *addrp)
  751. {
  752. pt1_i2c_emit(pt1, addr, 1, 0, 0, 1, addr + 1);
  753. pt1_i2c_emit(pt1, addr + 1, 1, 0, 1, 1, addr + 2);
  754. pt1_i2c_emit(pt1, addr + 2, 1, 1, 1, 1, addr + 3);
  755. pt1_i2c_emit(pt1, addr + 3, 1, 0, 0, 1, addr + 4);
  756. *addrp = addr + 4;
  757. }
  758. static void pt1_i2c_write_byte(struct pt1 *pt1, int addr, int *addrp, int data)
  759. {
  760. int i;
  761. for (i = 0; i < 8; i++)
  762. pt1_i2c_write_bit(pt1, addr, &addr, data >> (7 - i) & 1);
  763. pt1_i2c_write_bit(pt1, addr, &addr, 1);
  764. *addrp = addr;
  765. }
  766. static void pt1_i2c_read_byte(struct pt1 *pt1, int addr, int *addrp, int last)
  767. {
  768. int i;
  769. for (i = 0; i < 8; i++)
  770. pt1_i2c_read_bit(pt1, addr, &addr);
  771. pt1_i2c_write_bit(pt1, addr, &addr, last);
  772. *addrp = addr;
  773. }
  774. static void pt1_i2c_prepare(struct pt1 *pt1, int addr, int *addrp)
  775. {
  776. pt1_i2c_emit(pt1, addr, 1, 0, 1, 1, addr + 1);
  777. pt1_i2c_emit(pt1, addr + 1, 1, 0, 1, 0, addr + 2);
  778. pt1_i2c_emit(pt1, addr + 2, 1, 0, 0, 0, addr + 3);
  779. *addrp = addr + 3;
  780. }
  781. static void
  782. pt1_i2c_write_msg(struct pt1 *pt1, int addr, int *addrp, struct i2c_msg *msg)
  783. {
  784. int i;
  785. pt1_i2c_prepare(pt1, addr, &addr);
  786. pt1_i2c_write_byte(pt1, addr, &addr, msg->addr << 1);
  787. for (i = 0; i < msg->len; i++)
  788. pt1_i2c_write_byte(pt1, addr, &addr, msg->buf[i]);
  789. *addrp = addr;
  790. }
  791. static void
  792. pt1_i2c_read_msg(struct pt1 *pt1, int addr, int *addrp, struct i2c_msg *msg)
  793. {
  794. int i;
  795. pt1_i2c_prepare(pt1, addr, &addr);
  796. pt1_i2c_write_byte(pt1, addr, &addr, msg->addr << 1 | 1);
  797. for (i = 0; i < msg->len; i++)
  798. pt1_i2c_read_byte(pt1, addr, &addr, i == msg->len - 1);
  799. *addrp = addr;
  800. }
  801. static int pt1_i2c_end(struct pt1 *pt1, int addr)
  802. {
  803. pt1_i2c_emit(pt1, addr, 1, 0, 0, 0, addr + 1);
  804. pt1_i2c_emit(pt1, addr + 1, 1, 0, 1, 0, addr + 2);
  805. pt1_i2c_emit(pt1, addr + 2, 1, 0, 1, 1, 0);
  806. pt1_write_reg(pt1, 0, 0x00000004);
  807. do {
  808. if (signal_pending(current))
  809. return -EINTR;
  810. schedule_timeout_interruptible((HZ + 999) / 1000);
  811. } while (pt1_read_reg(pt1, 0) & 0x00000080);
  812. return 0;
  813. }
  814. static void pt1_i2c_begin(struct pt1 *pt1, int *addrp)
  815. {
  816. int addr;
  817. addr = 0;
  818. pt1_i2c_emit(pt1, addr, 0, 0, 1, 1, addr /* itself */);
  819. addr = addr + 1;
  820. if (!pt1->i2c_running) {
  821. pt1_i2c_emit(pt1, addr, 1, 0, 1, 1, addr + 1);
  822. pt1_i2c_emit(pt1, addr + 1, 1, 0, 1, 0, addr + 2);
  823. addr = addr + 2;
  824. pt1->i2c_running = 1;
  825. }
  826. *addrp = addr;
  827. }
  828. static int pt1_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
  829. {
  830. struct pt1 *pt1;
  831. int i;
  832. struct i2c_msg *msg, *next_msg;
  833. int addr, ret;
  834. u16 len;
  835. u32 word;
  836. pt1 = i2c_get_adapdata(adap);
  837. for (i = 0; i < num; i++) {
  838. msg = &msgs[i];
  839. if (msg->flags & I2C_M_RD)
  840. return -ENOTSUPP;
  841. if (i + 1 < num)
  842. next_msg = &msgs[i + 1];
  843. else
  844. next_msg = NULL;
  845. if (next_msg && next_msg->flags & I2C_M_RD) {
  846. i++;
  847. len = next_msg->len;
  848. if (len > 4)
  849. return -ENOTSUPP;
  850. pt1_i2c_begin(pt1, &addr);
  851. pt1_i2c_write_msg(pt1, addr, &addr, msg);
  852. pt1_i2c_read_msg(pt1, addr, &addr, next_msg);
  853. ret = pt1_i2c_end(pt1, addr);
  854. if (ret < 0)
  855. return ret;
  856. word = pt1_read_reg(pt1, 2);
  857. while (len--) {
  858. next_msg->buf[len] = word;
  859. word >>= 8;
  860. }
  861. } else {
  862. pt1_i2c_begin(pt1, &addr);
  863. pt1_i2c_write_msg(pt1, addr, &addr, msg);
  864. ret = pt1_i2c_end(pt1, addr);
  865. if (ret < 0)
  866. return ret;
  867. }
  868. }
  869. return num;
  870. }
  871. static u32 pt1_i2c_func(struct i2c_adapter *adap)
  872. {
  873. return I2C_FUNC_I2C;
  874. }
  875. static const struct i2c_algorithm pt1_i2c_algo = {
  876. .master_xfer = pt1_i2c_xfer,
  877. .functionality = pt1_i2c_func,
  878. };
  879. static void pt1_i2c_wait(struct pt1 *pt1)
  880. {
  881. int i;
  882. for (i = 0; i < 128; i++)
  883. pt1_i2c_emit(pt1, 0, 0, 0, 1, 1, 0);
  884. }
  885. static void pt1_i2c_init(struct pt1 *pt1)
  886. {
  887. int i;
  888. for (i = 0; i < 1024; i++)
  889. pt1_i2c_emit(pt1, i, 0, 0, 1, 1, 0);
  890. }
  891. static void __devexit pt1_remove(struct pci_dev *pdev)
  892. {
  893. struct pt1 *pt1;
  894. void __iomem *regs;
  895. pt1 = pci_get_drvdata(pdev);
  896. regs = pt1->regs;
  897. if (pt1->kthread)
  898. kthread_stop(pt1->kthread);
  899. pt1_cleanup_tables(pt1);
  900. pt1_cleanup_frontends(pt1);
  901. pt1_disable_ram(pt1);
  902. pt1->power = 0;
  903. pt1->reset = 1;
  904. pt1_update_power(pt1);
  905. pt1_cleanup_adapters(pt1);
  906. i2c_del_adapter(&pt1->i2c_adap);
  907. pci_set_drvdata(pdev, NULL);
  908. kfree(pt1);
  909. pci_iounmap(pdev, regs);
  910. pci_release_regions(pdev);
  911. pci_disable_device(pdev);
  912. }
  913. static int __devinit
  914. pt1_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  915. {
  916. int ret;
  917. void __iomem *regs;
  918. struct pt1 *pt1;
  919. struct i2c_adapter *i2c_adap;
  920. ret = pci_enable_device(pdev);
  921. if (ret < 0)
  922. goto err;
  923. ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  924. if (ret < 0)
  925. goto err_pci_disable_device;
  926. pci_set_master(pdev);
  927. ret = pci_request_regions(pdev, DRIVER_NAME);
  928. if (ret < 0)
  929. goto err_pci_disable_device;
  930. regs = pci_iomap(pdev, 0, 0);
  931. if (!regs) {
  932. ret = -EIO;
  933. goto err_pci_release_regions;
  934. }
  935. pt1 = kzalloc(sizeof(struct pt1), GFP_KERNEL);
  936. if (!pt1) {
  937. ret = -ENOMEM;
  938. goto err_pci_iounmap;
  939. }
  940. mutex_init(&pt1->lock);
  941. pt1->pdev = pdev;
  942. pt1->regs = regs;
  943. pci_set_drvdata(pdev, pt1);
  944. ret = pt1_init_adapters(pt1);
  945. if (ret < 0)
  946. goto err_kfree;
  947. mutex_init(&pt1->lock);
  948. pt1->power = 0;
  949. pt1->reset = 1;
  950. pt1_update_power(pt1);
  951. i2c_adap = &pt1->i2c_adap;
  952. i2c_adap->algo = &pt1_i2c_algo;
  953. i2c_adap->algo_data = NULL;
  954. i2c_adap->dev.parent = &pdev->dev;
  955. strcpy(i2c_adap->name, DRIVER_NAME);
  956. i2c_set_adapdata(i2c_adap, pt1);
  957. ret = i2c_add_adapter(i2c_adap);
  958. if (ret < 0)
  959. goto err_pt1_cleanup_adapters;
  960. pt1_i2c_init(pt1);
  961. pt1_i2c_wait(pt1);
  962. ret = pt1_sync(pt1);
  963. if (ret < 0)
  964. goto err_i2c_del_adapter;
  965. pt1_identify(pt1);
  966. ret = pt1_unlock(pt1);
  967. if (ret < 0)
  968. goto err_i2c_del_adapter;
  969. ret = pt1_reset_pci(pt1);
  970. if (ret < 0)
  971. goto err_i2c_del_adapter;
  972. ret = pt1_reset_ram(pt1);
  973. if (ret < 0)
  974. goto err_i2c_del_adapter;
  975. ret = pt1_enable_ram(pt1);
  976. if (ret < 0)
  977. goto err_i2c_del_adapter;
  978. pt1_init_streams(pt1);
  979. pt1->power = 1;
  980. pt1_update_power(pt1);
  981. schedule_timeout_uninterruptible((HZ + 49) / 50);
  982. pt1->reset = 0;
  983. pt1_update_power(pt1);
  984. schedule_timeout_uninterruptible((HZ + 999) / 1000);
  985. ret = pt1_init_frontends(pt1);
  986. if (ret < 0)
  987. goto err_pt1_disable_ram;
  988. ret = pt1_init_tables(pt1);
  989. if (ret < 0)
  990. goto err_pt1_cleanup_frontends;
  991. return 0;
  992. err_pt1_cleanup_frontends:
  993. pt1_cleanup_frontends(pt1);
  994. err_pt1_disable_ram:
  995. pt1_disable_ram(pt1);
  996. pt1->power = 0;
  997. pt1->reset = 1;
  998. pt1_update_power(pt1);
  999. err_i2c_del_adapter:
  1000. i2c_del_adapter(i2c_adap);
  1001. err_pt1_cleanup_adapters:
  1002. pt1_cleanup_adapters(pt1);
  1003. err_kfree:
  1004. pci_set_drvdata(pdev, NULL);
  1005. kfree(pt1);
  1006. err_pci_iounmap:
  1007. pci_iounmap(pdev, regs);
  1008. err_pci_release_regions:
  1009. pci_release_regions(pdev);
  1010. err_pci_disable_device:
  1011. pci_disable_device(pdev);
  1012. err:
  1013. return ret;
  1014. }
  1015. static struct pci_device_id pt1_id_table[] = {
  1016. { PCI_DEVICE(0x10ee, 0x211a) },
  1017. { PCI_DEVICE(0x10ee, 0x222a) },
  1018. { },
  1019. };
  1020. MODULE_DEVICE_TABLE(pci, pt1_id_table);
  1021. static struct pci_driver pt1_driver = {
  1022. .name = DRIVER_NAME,
  1023. .probe = pt1_probe,
  1024. .remove = __devexit_p(pt1_remove),
  1025. .id_table = pt1_id_table,
  1026. };
  1027. static int __init pt1_init(void)
  1028. {
  1029. return pci_register_driver(&pt1_driver);
  1030. }
  1031. static void __exit pt1_cleanup(void)
  1032. {
  1033. pci_unregister_driver(&pt1_driver);
  1034. }
  1035. module_init(pt1_init);
  1036. module_exit(pt1_cleanup);
  1037. MODULE_AUTHOR("Takahito HIRANO <hiranotaka@zng.info>");
  1038. MODULE_DESCRIPTION("Earthsoft PT1/PT2 Driver");
  1039. MODULE_LICENSE("GPL");