i2c-designware-core.c 19 KB

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  1. /*
  2. * Synopsys DesignWare I2C adapter driver (master only).
  3. *
  4. * Based on the TI DAVINCI I2C adapter driver.
  5. *
  6. * Copyright (C) 2006 Texas Instruments.
  7. * Copyright (C) 2007 MontaVista Software Inc.
  8. * Copyright (C) 2009 Provigent Ltd.
  9. *
  10. * ----------------------------------------------------------------------------
  11. *
  12. * This program is free software; you can redistribute it and/or modify
  13. * it under the terms of the GNU General Public License as published by
  14. * the Free Software Foundation; either version 2 of the License, or
  15. * (at your option) any later version.
  16. *
  17. * This program is distributed in the hope that it will be useful,
  18. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  20. * GNU General Public License for more details.
  21. *
  22. * You should have received a copy of the GNU General Public License
  23. * along with this program; if not, write to the Free Software
  24. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  25. * ----------------------------------------------------------------------------
  26. *
  27. */
  28. #include <linux/clk.h>
  29. #include <linux/errno.h>
  30. #include <linux/err.h>
  31. #include <linux/i2c.h>
  32. #include <linux/interrupt.h>
  33. #include <linux/io.h>
  34. #include <linux/pm_runtime.h>
  35. #include <linux/delay.h>
  36. #include "i2c-designware-core.h"
  37. /*
  38. * Registers offset
  39. */
  40. #define DW_IC_CON 0x0
  41. #define DW_IC_TAR 0x4
  42. #define DW_IC_DATA_CMD 0x10
  43. #define DW_IC_SS_SCL_HCNT 0x14
  44. #define DW_IC_SS_SCL_LCNT 0x18
  45. #define DW_IC_FS_SCL_HCNT 0x1c
  46. #define DW_IC_FS_SCL_LCNT 0x20
  47. #define DW_IC_INTR_STAT 0x2c
  48. #define DW_IC_INTR_MASK 0x30
  49. #define DW_IC_RAW_INTR_STAT 0x34
  50. #define DW_IC_RX_TL 0x38
  51. #define DW_IC_TX_TL 0x3c
  52. #define DW_IC_CLR_INTR 0x40
  53. #define DW_IC_CLR_RX_UNDER 0x44
  54. #define DW_IC_CLR_RX_OVER 0x48
  55. #define DW_IC_CLR_TX_OVER 0x4c
  56. #define DW_IC_CLR_RD_REQ 0x50
  57. #define DW_IC_CLR_TX_ABRT 0x54
  58. #define DW_IC_CLR_RX_DONE 0x58
  59. #define DW_IC_CLR_ACTIVITY 0x5c
  60. #define DW_IC_CLR_STOP_DET 0x60
  61. #define DW_IC_CLR_START_DET 0x64
  62. #define DW_IC_CLR_GEN_CALL 0x68
  63. #define DW_IC_ENABLE 0x6c
  64. #define DW_IC_STATUS 0x70
  65. #define DW_IC_TXFLR 0x74
  66. #define DW_IC_RXFLR 0x78
  67. #define DW_IC_TX_ABRT_SOURCE 0x80
  68. #define DW_IC_COMP_PARAM_1 0xf4
  69. #define DW_IC_COMP_TYPE 0xfc
  70. #define DW_IC_COMP_TYPE_VALUE 0x44570140
  71. #define DW_IC_INTR_RX_UNDER 0x001
  72. #define DW_IC_INTR_RX_OVER 0x002
  73. #define DW_IC_INTR_RX_FULL 0x004
  74. #define DW_IC_INTR_TX_OVER 0x008
  75. #define DW_IC_INTR_TX_EMPTY 0x010
  76. #define DW_IC_INTR_RD_REQ 0x020
  77. #define DW_IC_INTR_TX_ABRT 0x040
  78. #define DW_IC_INTR_RX_DONE 0x080
  79. #define DW_IC_INTR_ACTIVITY 0x100
  80. #define DW_IC_INTR_STOP_DET 0x200
  81. #define DW_IC_INTR_START_DET 0x400
  82. #define DW_IC_INTR_GEN_CALL 0x800
  83. #define DW_IC_INTR_DEFAULT_MASK (DW_IC_INTR_RX_FULL | \
  84. DW_IC_INTR_TX_EMPTY | \
  85. DW_IC_INTR_TX_ABRT | \
  86. DW_IC_INTR_STOP_DET)
  87. #define DW_IC_STATUS_ACTIVITY 0x1
  88. #define DW_IC_ERR_TX_ABRT 0x1
  89. /*
  90. * status codes
  91. */
  92. #define STATUS_IDLE 0x0
  93. #define STATUS_WRITE_IN_PROGRESS 0x1
  94. #define STATUS_READ_IN_PROGRESS 0x2
  95. #define TIMEOUT 20 /* ms */
  96. /*
  97. * hardware abort codes from the DW_IC_TX_ABRT_SOURCE register
  98. *
  99. * only expected abort codes are listed here
  100. * refer to the datasheet for the full list
  101. */
  102. #define ABRT_7B_ADDR_NOACK 0
  103. #define ABRT_10ADDR1_NOACK 1
  104. #define ABRT_10ADDR2_NOACK 2
  105. #define ABRT_TXDATA_NOACK 3
  106. #define ABRT_GCALL_NOACK 4
  107. #define ABRT_GCALL_READ 5
  108. #define ABRT_SBYTE_ACKDET 7
  109. #define ABRT_SBYTE_NORSTRT 9
  110. #define ABRT_10B_RD_NORSTRT 10
  111. #define ABRT_MASTER_DIS 11
  112. #define ARB_LOST 12
  113. #define DW_IC_TX_ABRT_7B_ADDR_NOACK (1UL << ABRT_7B_ADDR_NOACK)
  114. #define DW_IC_TX_ABRT_10ADDR1_NOACK (1UL << ABRT_10ADDR1_NOACK)
  115. #define DW_IC_TX_ABRT_10ADDR2_NOACK (1UL << ABRT_10ADDR2_NOACK)
  116. #define DW_IC_TX_ABRT_TXDATA_NOACK (1UL << ABRT_TXDATA_NOACK)
  117. #define DW_IC_TX_ABRT_GCALL_NOACK (1UL << ABRT_GCALL_NOACK)
  118. #define DW_IC_TX_ABRT_GCALL_READ (1UL << ABRT_GCALL_READ)
  119. #define DW_IC_TX_ABRT_SBYTE_ACKDET (1UL << ABRT_SBYTE_ACKDET)
  120. #define DW_IC_TX_ABRT_SBYTE_NORSTRT (1UL << ABRT_SBYTE_NORSTRT)
  121. #define DW_IC_TX_ABRT_10B_RD_NORSTRT (1UL << ABRT_10B_RD_NORSTRT)
  122. #define DW_IC_TX_ABRT_MASTER_DIS (1UL << ABRT_MASTER_DIS)
  123. #define DW_IC_TX_ARB_LOST (1UL << ARB_LOST)
  124. #define DW_IC_TX_ABRT_NOACK (DW_IC_TX_ABRT_7B_ADDR_NOACK | \
  125. DW_IC_TX_ABRT_10ADDR1_NOACK | \
  126. DW_IC_TX_ABRT_10ADDR2_NOACK | \
  127. DW_IC_TX_ABRT_TXDATA_NOACK | \
  128. DW_IC_TX_ABRT_GCALL_NOACK)
  129. static char *abort_sources[] = {
  130. [ABRT_7B_ADDR_NOACK] =
  131. "slave address not acknowledged (7bit mode)",
  132. [ABRT_10ADDR1_NOACK] =
  133. "first address byte not acknowledged (10bit mode)",
  134. [ABRT_10ADDR2_NOACK] =
  135. "second address byte not acknowledged (10bit mode)",
  136. [ABRT_TXDATA_NOACK] =
  137. "data not acknowledged",
  138. [ABRT_GCALL_NOACK] =
  139. "no acknowledgement for a general call",
  140. [ABRT_GCALL_READ] =
  141. "read after general call",
  142. [ABRT_SBYTE_ACKDET] =
  143. "start byte acknowledged",
  144. [ABRT_SBYTE_NORSTRT] =
  145. "trying to send start byte when restart is disabled",
  146. [ABRT_10B_RD_NORSTRT] =
  147. "trying to read when restart is disabled (10bit mode)",
  148. [ABRT_MASTER_DIS] =
  149. "trying to use disabled adapter",
  150. [ARB_LOST] =
  151. "lost arbitration",
  152. };
  153. u32 dw_readl(struct dw_i2c_dev *dev, int offset)
  154. {
  155. u32 value;
  156. if (dev->accessor_flags & ACCESS_16BIT)
  157. value = readw(dev->base + offset) |
  158. (readw(dev->base + offset + 2) << 16);
  159. else
  160. value = readl(dev->base + offset);
  161. if (dev->accessor_flags & ACCESS_SWAP)
  162. return swab32(value);
  163. else
  164. return value;
  165. }
  166. void dw_writel(struct dw_i2c_dev *dev, u32 b, int offset)
  167. {
  168. if (dev->accessor_flags & ACCESS_SWAP)
  169. b = swab32(b);
  170. if (dev->accessor_flags & ACCESS_16BIT) {
  171. writew((u16)b, dev->base + offset);
  172. writew((u16)(b >> 16), dev->base + offset + 2);
  173. } else {
  174. writel(b, dev->base + offset);
  175. }
  176. }
  177. static u32
  178. i2c_dw_scl_hcnt(u32 ic_clk, u32 tSYMBOL, u32 tf, int cond, int offset)
  179. {
  180. /*
  181. * DesignWare I2C core doesn't seem to have solid strategy to meet
  182. * the tHD;STA timing spec. Configuring _HCNT based on tHIGH spec
  183. * will result in violation of the tHD;STA spec.
  184. */
  185. if (cond)
  186. /*
  187. * Conditional expression:
  188. *
  189. * IC_[FS]S_SCL_HCNT + (1+4+3) >= IC_CLK * tHIGH
  190. *
  191. * This is based on the DW manuals, and represents an ideal
  192. * configuration. The resulting I2C bus speed will be
  193. * faster than any of the others.
  194. *
  195. * If your hardware is free from tHD;STA issue, try this one.
  196. */
  197. return (ic_clk * tSYMBOL + 5000) / 10000 - 8 + offset;
  198. else
  199. /*
  200. * Conditional expression:
  201. *
  202. * IC_[FS]S_SCL_HCNT + 3 >= IC_CLK * (tHD;STA + tf)
  203. *
  204. * This is just experimental rule; the tHD;STA period turned
  205. * out to be proportinal to (_HCNT + 3). With this setting,
  206. * we could meet both tHIGH and tHD;STA timing specs.
  207. *
  208. * If unsure, you'd better to take this alternative.
  209. *
  210. * The reason why we need to take into account "tf" here,
  211. * is the same as described in i2c_dw_scl_lcnt().
  212. */
  213. return (ic_clk * (tSYMBOL + tf) + 5000) / 10000 - 3 + offset;
  214. }
  215. static u32 i2c_dw_scl_lcnt(u32 ic_clk, u32 tLOW, u32 tf, int offset)
  216. {
  217. /*
  218. * Conditional expression:
  219. *
  220. * IC_[FS]S_SCL_LCNT + 1 >= IC_CLK * (tLOW + tf)
  221. *
  222. * DW I2C core starts counting the SCL CNTs for the LOW period
  223. * of the SCL clock (tLOW) as soon as it pulls the SCL line.
  224. * In order to meet the tLOW timing spec, we need to take into
  225. * account the fall time of SCL signal (tf). Default tf value
  226. * should be 0.3 us, for safety.
  227. */
  228. return ((ic_clk * (tLOW + tf) + 5000) / 10000) - 1 + offset;
  229. }
  230. /**
  231. * i2c_dw_init() - initialize the designware i2c master hardware
  232. * @dev: device private data
  233. *
  234. * This functions configures and enables the I2C master.
  235. * This function is called during I2C init function, and in case of timeout at
  236. * run time.
  237. */
  238. int i2c_dw_init(struct dw_i2c_dev *dev)
  239. {
  240. u32 input_clock_khz;
  241. u32 hcnt, lcnt;
  242. u32 reg;
  243. input_clock_khz = dev->get_clk_rate_khz(dev);
  244. reg = dw_readl(dev, DW_IC_COMP_TYPE);
  245. if (reg == ___constant_swab32(DW_IC_COMP_TYPE_VALUE)) {
  246. /* Configure register endianess access */
  247. dev->accessor_flags |= ACCESS_SWAP;
  248. } else if (reg == (DW_IC_COMP_TYPE_VALUE & 0x0000ffff)) {
  249. /* Configure register access mode 16bit */
  250. dev->accessor_flags |= ACCESS_16BIT;
  251. } else if (reg != DW_IC_COMP_TYPE_VALUE) {
  252. dev_err(dev->dev, "Unknown Synopsys component type: "
  253. "0x%08x\n", reg);
  254. return -ENODEV;
  255. }
  256. /* Disable the adapter */
  257. dw_writel(dev, 0, DW_IC_ENABLE);
  258. /* set standard and fast speed deviders for high/low periods */
  259. /* Standard-mode */
  260. hcnt = i2c_dw_scl_hcnt(input_clock_khz,
  261. 40, /* tHD;STA = tHIGH = 4.0 us */
  262. 3, /* tf = 0.3 us */
  263. 0, /* 0: DW default, 1: Ideal */
  264. 0); /* No offset */
  265. lcnt = i2c_dw_scl_lcnt(input_clock_khz,
  266. 47, /* tLOW = 4.7 us */
  267. 3, /* tf = 0.3 us */
  268. 0); /* No offset */
  269. dw_writel(dev, hcnt, DW_IC_SS_SCL_HCNT);
  270. dw_writel(dev, lcnt, DW_IC_SS_SCL_LCNT);
  271. dev_dbg(dev->dev, "Standard-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt);
  272. /* Fast-mode */
  273. hcnt = i2c_dw_scl_hcnt(input_clock_khz,
  274. 6, /* tHD;STA = tHIGH = 0.6 us */
  275. 3, /* tf = 0.3 us */
  276. 0, /* 0: DW default, 1: Ideal */
  277. 0); /* No offset */
  278. lcnt = i2c_dw_scl_lcnt(input_clock_khz,
  279. 13, /* tLOW = 1.3 us */
  280. 3, /* tf = 0.3 us */
  281. 0); /* No offset */
  282. dw_writel(dev, hcnt, DW_IC_FS_SCL_HCNT);
  283. dw_writel(dev, lcnt, DW_IC_FS_SCL_LCNT);
  284. dev_dbg(dev->dev, "Fast-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt);
  285. /* Configure Tx/Rx FIFO threshold levels */
  286. dw_writel(dev, dev->tx_fifo_depth - 1, DW_IC_TX_TL);
  287. dw_writel(dev, 0, DW_IC_RX_TL);
  288. /* configure the i2c master */
  289. dw_writel(dev, dev->master_cfg , DW_IC_CON);
  290. return 0;
  291. }
  292. /*
  293. * Waiting for bus not busy
  294. */
  295. static int i2c_dw_wait_bus_not_busy(struct dw_i2c_dev *dev)
  296. {
  297. int timeout = TIMEOUT;
  298. while (dw_readl(dev, DW_IC_STATUS) & DW_IC_STATUS_ACTIVITY) {
  299. if (timeout <= 0) {
  300. dev_warn(dev->dev, "timeout waiting for bus ready\n");
  301. return -ETIMEDOUT;
  302. }
  303. timeout--;
  304. mdelay(1);
  305. }
  306. return 0;
  307. }
  308. static void i2c_dw_xfer_init(struct dw_i2c_dev *dev)
  309. {
  310. struct i2c_msg *msgs = dev->msgs;
  311. u32 ic_con;
  312. /* Disable the adapter */
  313. dw_writel(dev, 0, DW_IC_ENABLE);
  314. /* set the slave (target) address */
  315. dw_writel(dev, msgs[dev->msg_write_idx].addr, DW_IC_TAR);
  316. /* if the slave address is ten bit address, enable 10BITADDR */
  317. ic_con = dw_readl(dev, DW_IC_CON);
  318. if (msgs[dev->msg_write_idx].flags & I2C_M_TEN)
  319. ic_con |= DW_IC_CON_10BITADDR_MASTER;
  320. else
  321. ic_con &= ~DW_IC_CON_10BITADDR_MASTER;
  322. dw_writel(dev, ic_con, DW_IC_CON);
  323. /* Enable the adapter */
  324. dw_writel(dev, 1, DW_IC_ENABLE);
  325. /* Enable interrupts */
  326. dw_writel(dev, DW_IC_INTR_DEFAULT_MASK, DW_IC_INTR_MASK);
  327. }
  328. /*
  329. * Initiate (and continue) low level master read/write transaction.
  330. * This function is only called from i2c_dw_isr, and pumping i2c_msg
  331. * messages into the tx buffer. Even if the size of i2c_msg data is
  332. * longer than the size of the tx buffer, it handles everything.
  333. */
  334. void
  335. i2c_dw_xfer_msg(struct dw_i2c_dev *dev)
  336. {
  337. struct i2c_msg *msgs = dev->msgs;
  338. u32 intr_mask;
  339. int tx_limit, rx_limit;
  340. u32 addr = msgs[dev->msg_write_idx].addr;
  341. u32 buf_len = dev->tx_buf_len;
  342. u8 *buf = dev->tx_buf;
  343. intr_mask = DW_IC_INTR_DEFAULT_MASK;
  344. for (; dev->msg_write_idx < dev->msgs_num; dev->msg_write_idx++) {
  345. /*
  346. * if target address has changed, we need to
  347. * reprogram the target address in the i2c
  348. * adapter when we are done with this transfer
  349. */
  350. if (msgs[dev->msg_write_idx].addr != addr) {
  351. dev_err(dev->dev,
  352. "%s: invalid target address\n", __func__);
  353. dev->msg_err = -EINVAL;
  354. break;
  355. }
  356. if (msgs[dev->msg_write_idx].len == 0) {
  357. dev_err(dev->dev,
  358. "%s: invalid message length\n", __func__);
  359. dev->msg_err = -EINVAL;
  360. break;
  361. }
  362. if (!(dev->status & STATUS_WRITE_IN_PROGRESS)) {
  363. /* new i2c_msg */
  364. buf = msgs[dev->msg_write_idx].buf;
  365. buf_len = msgs[dev->msg_write_idx].len;
  366. }
  367. tx_limit = dev->tx_fifo_depth - dw_readl(dev, DW_IC_TXFLR);
  368. rx_limit = dev->rx_fifo_depth - dw_readl(dev, DW_IC_RXFLR);
  369. while (buf_len > 0 && tx_limit > 0 && rx_limit > 0) {
  370. if (msgs[dev->msg_write_idx].flags & I2C_M_RD) {
  371. dw_writel(dev, 0x100, DW_IC_DATA_CMD);
  372. rx_limit--;
  373. } else
  374. dw_writel(dev, *buf++, DW_IC_DATA_CMD);
  375. tx_limit--; buf_len--;
  376. }
  377. dev->tx_buf = buf;
  378. dev->tx_buf_len = buf_len;
  379. if (buf_len > 0) {
  380. /* more bytes to be written */
  381. dev->status |= STATUS_WRITE_IN_PROGRESS;
  382. break;
  383. } else
  384. dev->status &= ~STATUS_WRITE_IN_PROGRESS;
  385. }
  386. /*
  387. * If i2c_msg index search is completed, we don't need TX_EMPTY
  388. * interrupt any more.
  389. */
  390. if (dev->msg_write_idx == dev->msgs_num)
  391. intr_mask &= ~DW_IC_INTR_TX_EMPTY;
  392. if (dev->msg_err)
  393. intr_mask = 0;
  394. dw_writel(dev, intr_mask, DW_IC_INTR_MASK);
  395. }
  396. static void
  397. i2c_dw_read(struct dw_i2c_dev *dev)
  398. {
  399. struct i2c_msg *msgs = dev->msgs;
  400. int rx_valid;
  401. for (; dev->msg_read_idx < dev->msgs_num; dev->msg_read_idx++) {
  402. u32 len;
  403. u8 *buf;
  404. if (!(msgs[dev->msg_read_idx].flags & I2C_M_RD))
  405. continue;
  406. if (!(dev->status & STATUS_READ_IN_PROGRESS)) {
  407. len = msgs[dev->msg_read_idx].len;
  408. buf = msgs[dev->msg_read_idx].buf;
  409. } else {
  410. len = dev->rx_buf_len;
  411. buf = dev->rx_buf;
  412. }
  413. rx_valid = dw_readl(dev, DW_IC_RXFLR);
  414. for (; len > 0 && rx_valid > 0; len--, rx_valid--)
  415. *buf++ = dw_readl(dev, DW_IC_DATA_CMD);
  416. if (len > 0) {
  417. dev->status |= STATUS_READ_IN_PROGRESS;
  418. dev->rx_buf_len = len;
  419. dev->rx_buf = buf;
  420. return;
  421. } else
  422. dev->status &= ~STATUS_READ_IN_PROGRESS;
  423. }
  424. }
  425. static int i2c_dw_handle_tx_abort(struct dw_i2c_dev *dev)
  426. {
  427. unsigned long abort_source = dev->abort_source;
  428. int i;
  429. if (abort_source & DW_IC_TX_ABRT_NOACK) {
  430. for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources))
  431. dev_dbg(dev->dev,
  432. "%s: %s\n", __func__, abort_sources[i]);
  433. return -EREMOTEIO;
  434. }
  435. for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources))
  436. dev_err(dev->dev, "%s: %s\n", __func__, abort_sources[i]);
  437. if (abort_source & DW_IC_TX_ARB_LOST)
  438. return -EAGAIN;
  439. else if (abort_source & DW_IC_TX_ABRT_GCALL_READ)
  440. return -EINVAL; /* wrong msgs[] data */
  441. else
  442. return -EIO;
  443. }
  444. /*
  445. * Prepare controller for a transaction and call i2c_dw_xfer_msg
  446. */
  447. int
  448. i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
  449. {
  450. struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
  451. int ret;
  452. dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num);
  453. mutex_lock(&dev->lock);
  454. pm_runtime_get_sync(dev->dev);
  455. INIT_COMPLETION(dev->cmd_complete);
  456. dev->msgs = msgs;
  457. dev->msgs_num = num;
  458. dev->cmd_err = 0;
  459. dev->msg_write_idx = 0;
  460. dev->msg_read_idx = 0;
  461. dev->msg_err = 0;
  462. dev->status = STATUS_IDLE;
  463. dev->abort_source = 0;
  464. ret = i2c_dw_wait_bus_not_busy(dev);
  465. if (ret < 0)
  466. goto done;
  467. /* start the transfers */
  468. i2c_dw_xfer_init(dev);
  469. /* wait for tx to complete */
  470. ret = wait_for_completion_interruptible_timeout(&dev->cmd_complete, HZ);
  471. if (ret == 0) {
  472. dev_err(dev->dev, "controller timed out\n");
  473. i2c_dw_init(dev);
  474. ret = -ETIMEDOUT;
  475. goto done;
  476. } else if (ret < 0)
  477. goto done;
  478. if (dev->msg_err) {
  479. ret = dev->msg_err;
  480. goto done;
  481. }
  482. /* no error */
  483. if (likely(!dev->cmd_err)) {
  484. /* Disable the adapter */
  485. dw_writel(dev, 0, DW_IC_ENABLE);
  486. ret = num;
  487. goto done;
  488. }
  489. /* We have an error */
  490. if (dev->cmd_err == DW_IC_ERR_TX_ABRT) {
  491. ret = i2c_dw_handle_tx_abort(dev);
  492. goto done;
  493. }
  494. ret = -EIO;
  495. done:
  496. pm_runtime_put(dev->dev);
  497. mutex_unlock(&dev->lock);
  498. return ret;
  499. }
  500. u32 i2c_dw_func(struct i2c_adapter *adap)
  501. {
  502. struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
  503. return dev->functionality;
  504. }
  505. static u32 i2c_dw_read_clear_intrbits(struct dw_i2c_dev *dev)
  506. {
  507. u32 stat;
  508. /*
  509. * The IC_INTR_STAT register just indicates "enabled" interrupts.
  510. * Ths unmasked raw version of interrupt status bits are available
  511. * in the IC_RAW_INTR_STAT register.
  512. *
  513. * That is,
  514. * stat = dw_readl(IC_INTR_STAT);
  515. * equals to,
  516. * stat = dw_readl(IC_RAW_INTR_STAT) & dw_readl(IC_INTR_MASK);
  517. *
  518. * The raw version might be useful for debugging purposes.
  519. */
  520. stat = dw_readl(dev, DW_IC_INTR_STAT);
  521. /*
  522. * Do not use the IC_CLR_INTR register to clear interrupts, or
  523. * you'll miss some interrupts, triggered during the period from
  524. * dw_readl(IC_INTR_STAT) to dw_readl(IC_CLR_INTR).
  525. *
  526. * Instead, use the separately-prepared IC_CLR_* registers.
  527. */
  528. if (stat & DW_IC_INTR_RX_UNDER)
  529. dw_readl(dev, DW_IC_CLR_RX_UNDER);
  530. if (stat & DW_IC_INTR_RX_OVER)
  531. dw_readl(dev, DW_IC_CLR_RX_OVER);
  532. if (stat & DW_IC_INTR_TX_OVER)
  533. dw_readl(dev, DW_IC_CLR_TX_OVER);
  534. if (stat & DW_IC_INTR_RD_REQ)
  535. dw_readl(dev, DW_IC_CLR_RD_REQ);
  536. if (stat & DW_IC_INTR_TX_ABRT) {
  537. /*
  538. * The IC_TX_ABRT_SOURCE register is cleared whenever
  539. * the IC_CLR_TX_ABRT is read. Preserve it beforehand.
  540. */
  541. dev->abort_source = dw_readl(dev, DW_IC_TX_ABRT_SOURCE);
  542. dw_readl(dev, DW_IC_CLR_TX_ABRT);
  543. }
  544. if (stat & DW_IC_INTR_RX_DONE)
  545. dw_readl(dev, DW_IC_CLR_RX_DONE);
  546. if (stat & DW_IC_INTR_ACTIVITY)
  547. dw_readl(dev, DW_IC_CLR_ACTIVITY);
  548. if (stat & DW_IC_INTR_STOP_DET)
  549. dw_readl(dev, DW_IC_CLR_STOP_DET);
  550. if (stat & DW_IC_INTR_START_DET)
  551. dw_readl(dev, DW_IC_CLR_START_DET);
  552. if (stat & DW_IC_INTR_GEN_CALL)
  553. dw_readl(dev, DW_IC_CLR_GEN_CALL);
  554. return stat;
  555. }
  556. /*
  557. * Interrupt service routine. This gets called whenever an I2C interrupt
  558. * occurs.
  559. */
  560. irqreturn_t i2c_dw_isr(int this_irq, void *dev_id)
  561. {
  562. struct dw_i2c_dev *dev = dev_id;
  563. u32 stat, enabled;
  564. enabled = dw_readl(dev, DW_IC_ENABLE);
  565. stat = dw_readl(dev, DW_IC_RAW_INTR_STAT);
  566. dev_dbg(dev->dev, "%s: %s enabled= 0x%x stat=0x%x\n", __func__,
  567. dev->adapter.name, enabled, stat);
  568. if (!enabled || !(stat & ~DW_IC_INTR_ACTIVITY))
  569. return IRQ_NONE;
  570. stat = i2c_dw_read_clear_intrbits(dev);
  571. if (stat & DW_IC_INTR_TX_ABRT) {
  572. dev->cmd_err |= DW_IC_ERR_TX_ABRT;
  573. dev->status = STATUS_IDLE;
  574. /*
  575. * Anytime TX_ABRT is set, the contents of the tx/rx
  576. * buffers are flushed. Make sure to skip them.
  577. */
  578. dw_writel(dev, 0, DW_IC_INTR_MASK);
  579. goto tx_aborted;
  580. }
  581. if (stat & DW_IC_INTR_RX_FULL)
  582. i2c_dw_read(dev);
  583. if (stat & DW_IC_INTR_TX_EMPTY)
  584. i2c_dw_xfer_msg(dev);
  585. /*
  586. * No need to modify or disable the interrupt mask here.
  587. * i2c_dw_xfer_msg() will take care of it according to
  588. * the current transmit status.
  589. */
  590. tx_aborted:
  591. if ((stat & (DW_IC_INTR_TX_ABRT | DW_IC_INTR_STOP_DET)) || dev->msg_err)
  592. complete(&dev->cmd_complete);
  593. return IRQ_HANDLED;
  594. }
  595. void i2c_dw_enable(struct dw_i2c_dev *dev)
  596. {
  597. /* Enable the adapter */
  598. dw_writel(dev, 1, DW_IC_ENABLE);
  599. }
  600. u32 i2c_dw_is_enabled(struct dw_i2c_dev *dev)
  601. {
  602. return dw_readl(dev, DW_IC_ENABLE);
  603. }
  604. void i2c_dw_disable(struct dw_i2c_dev *dev)
  605. {
  606. /* Disable controller */
  607. dw_writel(dev, 0, DW_IC_ENABLE);
  608. /* Disable all interupts */
  609. dw_writel(dev, 0, DW_IC_INTR_MASK);
  610. dw_readl(dev, DW_IC_CLR_INTR);
  611. }
  612. void i2c_dw_clear_int(struct dw_i2c_dev *dev)
  613. {
  614. dw_readl(dev, DW_IC_CLR_INTR);
  615. }
  616. void i2c_dw_disable_int(struct dw_i2c_dev *dev)
  617. {
  618. dw_writel(dev, 0, DW_IC_INTR_MASK);
  619. }
  620. u32 i2c_dw_read_comp_param(struct dw_i2c_dev *dev)
  621. {
  622. return dw_readl(dev, DW_IC_COMP_PARAM_1);
  623. }