radeon_fence.c 17 KB

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  1. /*
  2. * Copyright 2009 Jerome Glisse.
  3. * All Rights Reserved.
  4. *
  5. * Permission is hereby granted, free of charge, to any person obtaining a
  6. * copy of this software and associated documentation files (the
  7. * "Software"), to deal in the Software without restriction, including
  8. * without limitation the rights to use, copy, modify, merge, publish,
  9. * distribute, sub license, and/or sell copies of the Software, and to
  10. * permit persons to whom the Software is furnished to do so, subject to
  11. * the following conditions:
  12. *
  13. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15. * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16. * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17. * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18. * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19. * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20. *
  21. * The above copyright notice and this permission notice (including the
  22. * next paragraph) shall be included in all copies or substantial portions
  23. * of the Software.
  24. *
  25. */
  26. /*
  27. * Authors:
  28. * Jerome Glisse <glisse@freedesktop.org>
  29. * Dave Airlie
  30. */
  31. #include <linux/seq_file.h>
  32. #include <linux/atomic.h>
  33. #include <linux/wait.h>
  34. #include <linux/list.h>
  35. #include <linux/kref.h>
  36. #include <linux/slab.h>
  37. #include "drmP.h"
  38. #include "drm.h"
  39. #include "radeon_reg.h"
  40. #include "radeon.h"
  41. #include "radeon_trace.h"
  42. static void radeon_fence_write(struct radeon_device *rdev, u32 seq, int ring)
  43. {
  44. if (rdev->wb.enabled) {
  45. *rdev->fence_drv[ring].cpu_addr = cpu_to_le32(seq);
  46. } else {
  47. WREG32(rdev->fence_drv[ring].scratch_reg, seq);
  48. }
  49. }
  50. static u32 radeon_fence_read(struct radeon_device *rdev, int ring)
  51. {
  52. u32 seq = 0;
  53. if (rdev->wb.enabled) {
  54. seq = le32_to_cpu(*rdev->fence_drv[ring].cpu_addr);
  55. } else {
  56. seq = RREG32(rdev->fence_drv[ring].scratch_reg);
  57. }
  58. return seq;
  59. }
  60. int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence)
  61. {
  62. /* we are protected by the ring emission mutex */
  63. if (fence->seq && fence->seq < RADEON_FENCE_NOTEMITED_SEQ) {
  64. return 0;
  65. }
  66. fence->seq = ++rdev->fence_drv[fence->ring].seq;
  67. radeon_fence_ring_emit(rdev, fence->ring, fence);
  68. trace_radeon_fence_emit(rdev->ddev, fence->seq);
  69. return 0;
  70. }
  71. void radeon_fence_process(struct radeon_device *rdev, int ring)
  72. {
  73. uint64_t seq, last_seq;
  74. unsigned count_loop = 0;
  75. bool wake = false;
  76. /* Note there is a scenario here for an infinite loop but it's
  77. * very unlikely to happen. For it to happen, the current polling
  78. * process need to be interrupted by another process and another
  79. * process needs to update the last_seq btw the atomic read and
  80. * xchg of the current process.
  81. *
  82. * More over for this to go in infinite loop there need to be
  83. * continuously new fence signaled ie radeon_fence_read needs
  84. * to return a different value each time for both the currently
  85. * polling process and the other process that xchg the last_seq
  86. * btw atomic read and xchg of the current process. And the
  87. * value the other process set as last seq must be higher than
  88. * the seq value we just read. Which means that current process
  89. * need to be interrupted after radeon_fence_read and before
  90. * atomic xchg.
  91. *
  92. * To be even more safe we count the number of time we loop and
  93. * we bail after 10 loop just accepting the fact that we might
  94. * have temporarly set the last_seq not to the true real last
  95. * seq but to an older one.
  96. */
  97. last_seq = atomic64_read(&rdev->fence_drv[ring].last_seq);
  98. do {
  99. seq = radeon_fence_read(rdev, ring);
  100. seq |= last_seq & 0xffffffff00000000LL;
  101. if (seq < last_seq) {
  102. seq += 0x100000000LL;
  103. }
  104. if (seq == last_seq) {
  105. break;
  106. }
  107. /* If we loop over we don't want to return without
  108. * checking if a fence is signaled as it means that the
  109. * seq we just read is different from the previous on.
  110. */
  111. wake = true;
  112. last_seq = seq;
  113. if ((count_loop++) > 10) {
  114. /* We looped over too many time leave with the
  115. * fact that we might have set an older fence
  116. * seq then the current real last seq as signaled
  117. * by the hw.
  118. */
  119. break;
  120. }
  121. } while (atomic64_xchg(&rdev->fence_drv[ring].last_seq, seq) > seq);
  122. if (wake) {
  123. rdev->fence_drv[ring].last_activity = jiffies;
  124. wake_up_all(&rdev->fence_queue);
  125. }
  126. }
  127. static void radeon_fence_destroy(struct kref *kref)
  128. {
  129. struct radeon_fence *fence;
  130. fence = container_of(kref, struct radeon_fence, kref);
  131. fence->seq = RADEON_FENCE_NOTEMITED_SEQ;
  132. kfree(fence);
  133. }
  134. int radeon_fence_create(struct radeon_device *rdev,
  135. struct radeon_fence **fence,
  136. int ring)
  137. {
  138. *fence = kmalloc(sizeof(struct radeon_fence), GFP_KERNEL);
  139. if ((*fence) == NULL) {
  140. return -ENOMEM;
  141. }
  142. kref_init(&((*fence)->kref));
  143. (*fence)->rdev = rdev;
  144. (*fence)->seq = RADEON_FENCE_NOTEMITED_SEQ;
  145. (*fence)->ring = ring;
  146. return 0;
  147. }
  148. static bool radeon_fence_seq_signaled(struct radeon_device *rdev,
  149. u64 seq, unsigned ring)
  150. {
  151. if (atomic64_read(&rdev->fence_drv[ring].last_seq) >= seq) {
  152. return true;
  153. }
  154. /* poll new last sequence at least once */
  155. radeon_fence_process(rdev, ring);
  156. if (atomic64_read(&rdev->fence_drv[ring].last_seq) >= seq) {
  157. return true;
  158. }
  159. return false;
  160. }
  161. bool radeon_fence_signaled(struct radeon_fence *fence)
  162. {
  163. if (!fence) {
  164. return true;
  165. }
  166. if (fence->seq == RADEON_FENCE_NOTEMITED_SEQ) {
  167. WARN(1, "Querying an unemitted fence : %p !\n", fence);
  168. return true;
  169. }
  170. if (fence->seq == RADEON_FENCE_SIGNALED_SEQ) {
  171. return true;
  172. }
  173. if (radeon_fence_seq_signaled(fence->rdev, fence->seq, fence->ring)) {
  174. fence->seq = RADEON_FENCE_SIGNALED_SEQ;
  175. return true;
  176. }
  177. return false;
  178. }
  179. static int radeon_fence_wait_seq(struct radeon_device *rdev, u64 target_seq,
  180. unsigned ring, bool intr, bool lock_ring)
  181. {
  182. unsigned long timeout, last_activity;
  183. uint64_t seq;
  184. unsigned i;
  185. bool signaled;
  186. int r;
  187. while (target_seq > atomic64_read(&rdev->fence_drv[ring].last_seq)) {
  188. if (!rdev->ring[ring].ready) {
  189. return -EBUSY;
  190. }
  191. timeout = jiffies - RADEON_FENCE_JIFFIES_TIMEOUT;
  192. if (time_after(rdev->fence_drv[ring].last_activity, timeout)) {
  193. /* the normal case, timeout is somewhere before last_activity */
  194. timeout = rdev->fence_drv[ring].last_activity - timeout;
  195. } else {
  196. /* either jiffies wrapped around, or no fence was signaled in the last 500ms
  197. * anyway we will just wait for the minimum amount and then check for a lockup
  198. */
  199. timeout = 1;
  200. }
  201. seq = atomic64_read(&rdev->fence_drv[ring].last_seq);
  202. /* Save current last activity valuee, used to check for GPU lockups */
  203. last_activity = rdev->fence_drv[ring].last_activity;
  204. trace_radeon_fence_wait_begin(rdev->ddev, seq);
  205. radeon_irq_kms_sw_irq_get(rdev, ring);
  206. if (intr) {
  207. r = wait_event_interruptible_timeout(rdev->fence_queue,
  208. (signaled = radeon_fence_seq_signaled(rdev, target_seq, ring)),
  209. timeout);
  210. } else {
  211. r = wait_event_timeout(rdev->fence_queue,
  212. (signaled = radeon_fence_seq_signaled(rdev, target_seq, ring)),
  213. timeout);
  214. }
  215. radeon_irq_kms_sw_irq_put(rdev, ring);
  216. if (unlikely(r < 0)) {
  217. return r;
  218. }
  219. trace_radeon_fence_wait_end(rdev->ddev, seq);
  220. if (unlikely(!signaled)) {
  221. /* we were interrupted for some reason and fence
  222. * isn't signaled yet, resume waiting */
  223. if (r) {
  224. continue;
  225. }
  226. /* check if sequence value has changed since last_activity */
  227. if (seq != atomic64_read(&rdev->fence_drv[ring].last_seq)) {
  228. continue;
  229. }
  230. if (lock_ring) {
  231. mutex_lock(&rdev->ring_lock);
  232. }
  233. /* test if somebody else has already decided that this is a lockup */
  234. if (last_activity != rdev->fence_drv[ring].last_activity) {
  235. if (lock_ring) {
  236. mutex_unlock(&rdev->ring_lock);
  237. }
  238. continue;
  239. }
  240. if (radeon_ring_is_lockup(rdev, ring, &rdev->ring[ring])) {
  241. /* good news we believe it's a lockup */
  242. dev_warn(rdev->dev, "GPU lockup (waiting for 0x%016llx last fence id 0x%016llx)\n",
  243. target_seq, seq);
  244. /* change last activity so nobody else think there is a lockup */
  245. for (i = 0; i < RADEON_NUM_RINGS; ++i) {
  246. rdev->fence_drv[i].last_activity = jiffies;
  247. }
  248. /* mark the ring as not ready any more */
  249. rdev->ring[ring].ready = false;
  250. if (lock_ring) {
  251. mutex_unlock(&rdev->ring_lock);
  252. }
  253. return -EDEADLK;
  254. }
  255. if (lock_ring) {
  256. mutex_unlock(&rdev->ring_lock);
  257. }
  258. }
  259. }
  260. return 0;
  261. }
  262. int radeon_fence_wait(struct radeon_fence *fence, bool intr)
  263. {
  264. int r;
  265. if (fence == NULL) {
  266. WARN(1, "Querying an invalid fence : %p !\n", fence);
  267. return -EINVAL;
  268. }
  269. r = radeon_fence_wait_seq(fence->rdev, fence->seq,
  270. fence->ring, intr, true);
  271. if (r) {
  272. return r;
  273. }
  274. fence->seq = RADEON_FENCE_SIGNALED_SEQ;
  275. return 0;
  276. }
  277. bool radeon_fence_any_seq_signaled(struct radeon_device *rdev, u64 *seq)
  278. {
  279. unsigned i;
  280. for (i = 0; i < RADEON_NUM_RINGS; ++i) {
  281. if (seq[i] && radeon_fence_seq_signaled(rdev, seq[i], i)) {
  282. return true;
  283. }
  284. }
  285. return false;
  286. }
  287. static int radeon_fence_wait_any_seq(struct radeon_device *rdev,
  288. u64 *target_seq, bool intr)
  289. {
  290. unsigned long timeout, last_activity, tmp;
  291. unsigned i, ring = RADEON_NUM_RINGS;
  292. bool signaled;
  293. int r;
  294. for (i = 0, last_activity = 0; i < RADEON_NUM_RINGS; ++i) {
  295. if (!target_seq[i]) {
  296. continue;
  297. }
  298. /* use the most recent one as indicator */
  299. if (time_after(rdev->fence_drv[i].last_activity, last_activity)) {
  300. last_activity = rdev->fence_drv[i].last_activity;
  301. }
  302. /* For lockup detection just pick the lowest ring we are
  303. * actively waiting for
  304. */
  305. if (i < ring) {
  306. ring = i;
  307. }
  308. }
  309. /* nothing to wait for ? */
  310. if (ring == RADEON_NUM_RINGS) {
  311. return 0;
  312. }
  313. while (!radeon_fence_any_seq_signaled(rdev, target_seq)) {
  314. timeout = jiffies - RADEON_FENCE_JIFFIES_TIMEOUT;
  315. if (time_after(last_activity, timeout)) {
  316. /* the normal case, timeout is somewhere before last_activity */
  317. timeout = last_activity - timeout;
  318. } else {
  319. /* either jiffies wrapped around, or no fence was signaled in the last 500ms
  320. * anyway we will just wait for the minimum amount and then check for a lockup
  321. */
  322. timeout = 1;
  323. }
  324. trace_radeon_fence_wait_begin(rdev->ddev, target_seq[ring]);
  325. for (i = 0; i < RADEON_NUM_RINGS; ++i) {
  326. if (target_seq[i]) {
  327. radeon_irq_kms_sw_irq_get(rdev, i);
  328. }
  329. }
  330. if (intr) {
  331. r = wait_event_interruptible_timeout(rdev->fence_queue,
  332. (signaled = radeon_fence_any_seq_signaled(rdev, target_seq)),
  333. timeout);
  334. } else {
  335. r = wait_event_timeout(rdev->fence_queue,
  336. (signaled = radeon_fence_any_seq_signaled(rdev, target_seq)),
  337. timeout);
  338. }
  339. for (i = 0; i < RADEON_NUM_RINGS; ++i) {
  340. if (target_seq[i]) {
  341. radeon_irq_kms_sw_irq_put(rdev, i);
  342. }
  343. }
  344. if (unlikely(r < 0)) {
  345. return r;
  346. }
  347. trace_radeon_fence_wait_end(rdev->ddev, target_seq[ring]);
  348. if (unlikely(!signaled)) {
  349. /* we were interrupted for some reason and fence
  350. * isn't signaled yet, resume waiting */
  351. if (r) {
  352. continue;
  353. }
  354. mutex_lock(&rdev->ring_lock);
  355. for (i = 0, tmp = 0; i < RADEON_NUM_RINGS; ++i) {
  356. if (time_after(rdev->fence_drv[i].last_activity, tmp)) {
  357. tmp = rdev->fence_drv[i].last_activity;
  358. }
  359. }
  360. /* test if somebody else has already decided that this is a lockup */
  361. if (last_activity != tmp) {
  362. last_activity = tmp;
  363. mutex_unlock(&rdev->ring_lock);
  364. continue;
  365. }
  366. if (radeon_ring_is_lockup(rdev, ring, &rdev->ring[ring])) {
  367. /* good news we believe it's a lockup */
  368. dev_warn(rdev->dev, "GPU lockup (waiting for 0x%016llx)\n",
  369. target_seq[ring]);
  370. /* change last activity so nobody else think there is a lockup */
  371. for (i = 0; i < RADEON_NUM_RINGS; ++i) {
  372. rdev->fence_drv[i].last_activity = jiffies;
  373. }
  374. /* mark the ring as not ready any more */
  375. rdev->ring[ring].ready = false;
  376. mutex_unlock(&rdev->ring_lock);
  377. return -EDEADLK;
  378. }
  379. mutex_unlock(&rdev->ring_lock);
  380. }
  381. }
  382. return 0;
  383. }
  384. int radeon_fence_wait_any(struct radeon_device *rdev,
  385. struct radeon_fence **fences,
  386. bool intr)
  387. {
  388. uint64_t seq[RADEON_NUM_RINGS];
  389. unsigned i;
  390. int r;
  391. for (i = 0; i < RADEON_NUM_RINGS; ++i) {
  392. seq[i] = 0;
  393. if (!fences[i]) {
  394. continue;
  395. }
  396. if (fences[i]->seq == RADEON_FENCE_SIGNALED_SEQ) {
  397. /* something was allready signaled */
  398. return 0;
  399. }
  400. if (fences[i]->seq < RADEON_FENCE_NOTEMITED_SEQ) {
  401. seq[i] = fences[i]->seq;
  402. }
  403. }
  404. r = radeon_fence_wait_any_seq(rdev, seq, intr);
  405. if (r) {
  406. return r;
  407. }
  408. return 0;
  409. }
  410. int radeon_fence_wait_next_locked(struct radeon_device *rdev, int ring)
  411. {
  412. uint64_t seq;
  413. /* We are not protected by ring lock when reading current seq but
  414. * it's ok as worst case is we return to early while we could have
  415. * wait.
  416. */
  417. seq = atomic64_read(&rdev->fence_drv[ring].last_seq) + 1ULL;
  418. if (seq >= rdev->fence_drv[ring].seq) {
  419. /* nothing to wait for, last_seq is
  420. already the last emited fence */
  421. return -ENOENT;
  422. }
  423. return radeon_fence_wait_seq(rdev, seq, ring, false, false);
  424. }
  425. int radeon_fence_wait_empty_locked(struct radeon_device *rdev, int ring)
  426. {
  427. /* We are not protected by ring lock when reading current seq
  428. * but it's ok as wait empty is call from place where no more
  429. * activity can be scheduled so there won't be concurrent access
  430. * to seq value.
  431. */
  432. return radeon_fence_wait_seq(rdev, rdev->fence_drv[ring].seq,
  433. ring, false, false);
  434. }
  435. struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence)
  436. {
  437. kref_get(&fence->kref);
  438. return fence;
  439. }
  440. void radeon_fence_unref(struct radeon_fence **fence)
  441. {
  442. struct radeon_fence *tmp = *fence;
  443. *fence = NULL;
  444. if (tmp) {
  445. kref_put(&tmp->kref, radeon_fence_destroy);
  446. }
  447. }
  448. unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring)
  449. {
  450. uint64_t emitted;
  451. /* We are not protected by ring lock when reading the last sequence
  452. * but it's ok to report slightly wrong fence count here.
  453. */
  454. radeon_fence_process(rdev, ring);
  455. emitted = rdev->fence_drv[ring].seq - atomic64_read(&rdev->fence_drv[ring].last_seq);
  456. /* to avoid 32bits warp around */
  457. if (emitted > 0x10000000) {
  458. emitted = 0x10000000;
  459. }
  460. return (unsigned)emitted;
  461. }
  462. int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring)
  463. {
  464. uint64_t index;
  465. int r;
  466. radeon_scratch_free(rdev, rdev->fence_drv[ring].scratch_reg);
  467. if (rdev->wb.use_event) {
  468. rdev->fence_drv[ring].scratch_reg = 0;
  469. index = R600_WB_EVENT_OFFSET + ring * 4;
  470. } else {
  471. r = radeon_scratch_get(rdev, &rdev->fence_drv[ring].scratch_reg);
  472. if (r) {
  473. dev_err(rdev->dev, "fence failed to get scratch register\n");
  474. return r;
  475. }
  476. index = RADEON_WB_SCRATCH_OFFSET +
  477. rdev->fence_drv[ring].scratch_reg -
  478. rdev->scratch.reg_base;
  479. }
  480. rdev->fence_drv[ring].cpu_addr = &rdev->wb.wb[index/4];
  481. rdev->fence_drv[ring].gpu_addr = rdev->wb.gpu_addr + index;
  482. radeon_fence_write(rdev, rdev->fence_drv[ring].seq, ring);
  483. rdev->fence_drv[ring].initialized = true;
  484. dev_info(rdev->dev, "fence driver on ring %d use gpu addr 0x%016llx and cpu addr 0x%p\n",
  485. ring, rdev->fence_drv[ring].gpu_addr, rdev->fence_drv[ring].cpu_addr);
  486. return 0;
  487. }
  488. static void radeon_fence_driver_init_ring(struct radeon_device *rdev, int ring)
  489. {
  490. rdev->fence_drv[ring].scratch_reg = -1;
  491. rdev->fence_drv[ring].cpu_addr = NULL;
  492. rdev->fence_drv[ring].gpu_addr = 0;
  493. rdev->fence_drv[ring].seq = 0;
  494. atomic64_set(&rdev->fence_drv[ring].last_seq, 0);
  495. rdev->fence_drv[ring].last_activity = jiffies;
  496. rdev->fence_drv[ring].initialized = false;
  497. }
  498. int radeon_fence_driver_init(struct radeon_device *rdev)
  499. {
  500. int ring;
  501. init_waitqueue_head(&rdev->fence_queue);
  502. for (ring = 0; ring < RADEON_NUM_RINGS; ring++) {
  503. radeon_fence_driver_init_ring(rdev, ring);
  504. }
  505. if (radeon_debugfs_fence_init(rdev)) {
  506. dev_err(rdev->dev, "fence debugfs file creation failed\n");
  507. }
  508. return 0;
  509. }
  510. void radeon_fence_driver_fini(struct radeon_device *rdev)
  511. {
  512. int ring;
  513. mutex_lock(&rdev->ring_lock);
  514. for (ring = 0; ring < RADEON_NUM_RINGS; ring++) {
  515. if (!rdev->fence_drv[ring].initialized)
  516. continue;
  517. radeon_fence_wait_empty_locked(rdev, ring);
  518. wake_up_all(&rdev->fence_queue);
  519. radeon_scratch_free(rdev, rdev->fence_drv[ring].scratch_reg);
  520. rdev->fence_drv[ring].initialized = false;
  521. }
  522. mutex_unlock(&rdev->ring_lock);
  523. }
  524. /*
  525. * Fence debugfs
  526. */
  527. #if defined(CONFIG_DEBUG_FS)
  528. static int radeon_debugfs_fence_info(struct seq_file *m, void *data)
  529. {
  530. struct drm_info_node *node = (struct drm_info_node *)m->private;
  531. struct drm_device *dev = node->minor->dev;
  532. struct radeon_device *rdev = dev->dev_private;
  533. int i;
  534. for (i = 0; i < RADEON_NUM_RINGS; ++i) {
  535. if (!rdev->fence_drv[i].initialized)
  536. continue;
  537. seq_printf(m, "--- ring %d ---\n", i);
  538. seq_printf(m, "Last signaled fence 0x%016llx\n",
  539. (unsigned long long)atomic64_read(&rdev->fence_drv[i].last_seq));
  540. seq_printf(m, "Last emitted 0x%016llx\n",
  541. rdev->fence_drv[i].seq);
  542. }
  543. return 0;
  544. }
  545. static struct drm_info_list radeon_debugfs_fence_list[] = {
  546. {"radeon_fence_info", &radeon_debugfs_fence_info, 0, NULL},
  547. };
  548. #endif
  549. int radeon_debugfs_fence_init(struct radeon_device *rdev)
  550. {
  551. #if defined(CONFIG_DEBUG_FS)
  552. return radeon_debugfs_add_files(rdev, radeon_debugfs_fence_list, 1);
  553. #else
  554. return 0;
  555. #endif
  556. }