evergreen_hdmi.c 7.6 KB

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  1. /*
  2. * Copyright 2008 Advanced Micro Devices, Inc.
  3. * Copyright 2008 Red Hat Inc.
  4. * Copyright 2009 Christian König.
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a
  7. * copy of this software and associated documentation files (the "Software"),
  8. * to deal in the Software without restriction, including without limitation
  9. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10. * and/or sell copies of the Software, and to permit persons to whom the
  11. * Software is furnished to do so, subject to the following conditions:
  12. *
  13. * The above copyright notice and this permission notice shall be included in
  14. * all copies or substantial portions of the Software.
  15. *
  16. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22. * OTHER DEALINGS IN THE SOFTWARE.
  23. *
  24. * Authors: Christian König
  25. * Rafał Miłecki
  26. */
  27. #include "drmP.h"
  28. #include "radeon_drm.h"
  29. #include "radeon.h"
  30. #include "radeon_asic.h"
  31. #include "evergreend.h"
  32. #include "atom.h"
  33. /*
  34. * update the N and CTS parameters for a given pixel clock rate
  35. */
  36. static void evergreen_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock)
  37. {
  38. struct drm_device *dev = encoder->dev;
  39. struct radeon_device *rdev = dev->dev_private;
  40. struct radeon_hdmi_acr acr = r600_hdmi_acr(clock);
  41. struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  42. struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
  43. uint32_t offset = dig->afmt->offset;
  44. WREG32(HDMI_ACR_32_0 + offset, HDMI_ACR_CTS_32(acr.cts_32khz));
  45. WREG32(HDMI_ACR_32_1 + offset, acr.n_32khz);
  46. WREG32(HDMI_ACR_44_0 + offset, HDMI_ACR_CTS_44(acr.cts_44_1khz));
  47. WREG32(HDMI_ACR_44_1 + offset, acr.n_44_1khz);
  48. WREG32(HDMI_ACR_48_0 + offset, HDMI_ACR_CTS_48(acr.cts_48khz));
  49. WREG32(HDMI_ACR_48_1 + offset, acr.n_48khz);
  50. }
  51. /*
  52. * calculate the crc for a given info frame
  53. */
  54. static void evergreen_hdmi_infoframe_checksum(uint8_t packetType,
  55. uint8_t versionNumber,
  56. uint8_t length,
  57. uint8_t *frame)
  58. {
  59. int i;
  60. frame[0] = packetType + versionNumber + length;
  61. for (i = 1; i <= length; i++)
  62. frame[0] += frame[i];
  63. frame[0] = 0x100 - frame[0];
  64. }
  65. /*
  66. * build a HDMI Video Info Frame
  67. */
  68. static void evergreen_hdmi_videoinfoframe(
  69. struct drm_encoder *encoder,
  70. uint8_t color_format,
  71. int active_information_present,
  72. uint8_t active_format_aspect_ratio,
  73. uint8_t scan_information,
  74. uint8_t colorimetry,
  75. uint8_t ex_colorimetry,
  76. uint8_t quantization,
  77. int ITC,
  78. uint8_t picture_aspect_ratio,
  79. uint8_t video_format_identification,
  80. uint8_t pixel_repetition,
  81. uint8_t non_uniform_picture_scaling,
  82. uint8_t bar_info_data_valid,
  83. uint16_t top_bar,
  84. uint16_t bottom_bar,
  85. uint16_t left_bar,
  86. uint16_t right_bar
  87. )
  88. {
  89. struct drm_device *dev = encoder->dev;
  90. struct radeon_device *rdev = dev->dev_private;
  91. struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  92. struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
  93. uint32_t offset = dig->afmt->offset;
  94. uint8_t frame[14];
  95. frame[0x0] = 0;
  96. frame[0x1] =
  97. (scan_information & 0x3) |
  98. ((bar_info_data_valid & 0x3) << 2) |
  99. ((active_information_present & 0x1) << 4) |
  100. ((color_format & 0x3) << 5);
  101. frame[0x2] =
  102. (active_format_aspect_ratio & 0xF) |
  103. ((picture_aspect_ratio & 0x3) << 4) |
  104. ((colorimetry & 0x3) << 6);
  105. frame[0x3] =
  106. (non_uniform_picture_scaling & 0x3) |
  107. ((quantization & 0x3) << 2) |
  108. ((ex_colorimetry & 0x7) << 4) |
  109. ((ITC & 0x1) << 7);
  110. frame[0x4] = (video_format_identification & 0x7F);
  111. frame[0x5] = (pixel_repetition & 0xF);
  112. frame[0x6] = (top_bar & 0xFF);
  113. frame[0x7] = (top_bar >> 8);
  114. frame[0x8] = (bottom_bar & 0xFF);
  115. frame[0x9] = (bottom_bar >> 8);
  116. frame[0xA] = (left_bar & 0xFF);
  117. frame[0xB] = (left_bar >> 8);
  118. frame[0xC] = (right_bar & 0xFF);
  119. frame[0xD] = (right_bar >> 8);
  120. evergreen_hdmi_infoframe_checksum(0x82, 0x02, 0x0D, frame);
  121. /* Our header values (type, version, length) should be alright, Intel
  122. * is using the same. Checksum function also seems to be OK, it works
  123. * fine for audio infoframe. However calculated value is always lower
  124. * by 2 in comparison to fglrx. It breaks displaying anything in case
  125. * of TVs that strictly check the checksum. Hack it manually here to
  126. * workaround this issue. */
  127. frame[0x0] += 2;
  128. WREG32(AFMT_AVI_INFO0 + offset,
  129. frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
  130. WREG32(AFMT_AVI_INFO1 + offset,
  131. frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
  132. WREG32(AFMT_AVI_INFO2 + offset,
  133. frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
  134. WREG32(AFMT_AVI_INFO3 + offset,
  135. frame[0xC] | (frame[0xD] << 8));
  136. }
  137. /*
  138. * update the info frames with the data from the current display mode
  139. */
  140. void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode)
  141. {
  142. struct drm_device *dev = encoder->dev;
  143. struct radeon_device *rdev = dev->dev_private;
  144. struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  145. struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
  146. uint32_t offset;
  147. if (ASIC_IS_DCE5(rdev))
  148. return;
  149. /* Silent, r600_hdmi_enable will raise WARN for us */
  150. if (!dig->afmt->enabled)
  151. return;
  152. offset = dig->afmt->offset;
  153. r600_audio_set_clock(encoder, mode->clock);
  154. WREG32(HDMI_VBI_PACKET_CONTROL + offset,
  155. HDMI_NULL_SEND); /* send null packets when required */
  156. WREG32(AFMT_AUDIO_CRC_CONTROL + offset, 0x1000);
  157. WREG32(HDMI_AUDIO_PACKET_CONTROL + offset,
  158. HDMI_AUDIO_DELAY_EN(1) | /* set the default audio delay */
  159. HDMI_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */
  160. WREG32(AFMT_AUDIO_PACKET_CONTROL + offset,
  161. AFMT_AUDIO_SAMPLE_SEND | /* send audio packets */
  162. AFMT_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */
  163. WREG32(HDMI_ACR_PACKET_CONTROL + offset,
  164. HDMI_ACR_AUTO_SEND | /* allow hw to sent ACR packets when required */
  165. HDMI_ACR_SOURCE); /* select SW CTS value */
  166. WREG32(HDMI_VBI_PACKET_CONTROL + offset,
  167. HDMI_NULL_SEND | /* send null packets when required */
  168. HDMI_GC_SEND | /* send general control packets */
  169. HDMI_GC_CONT); /* send general control packets every frame */
  170. WREG32(HDMI_INFOFRAME_CONTROL0 + offset,
  171. HDMI_AVI_INFO_SEND | /* enable AVI info frames */
  172. HDMI_AVI_INFO_CONT | /* send AVI info frames every frame/field */
  173. HDMI_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */
  174. HDMI_AUDIO_INFO_CONT); /* required for audio info values to be updated */
  175. WREG32(AFMT_INFOFRAME_CONTROL0 + offset,
  176. AFMT_AUDIO_INFO_UPDATE); /* required for audio info values to be updated */
  177. WREG32(HDMI_INFOFRAME_CONTROL1 + offset,
  178. HDMI_AVI_INFO_LINE(2) | /* anything other than 0 */
  179. HDMI_AUDIO_INFO_LINE(2)); /* anything other than 0 */
  180. WREG32(HDMI_GC + offset, 0); /* unset HDMI_GC_AVMUTE */
  181. evergreen_hdmi_videoinfoframe(encoder, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  182. 0, 0, 0, 0, 0, 0);
  183. evergreen_hdmi_update_ACR(encoder, mode->clock);
  184. /* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */
  185. WREG32(AFMT_RAMP_CONTROL0 + offset, 0x00FFFFFF);
  186. WREG32(AFMT_RAMP_CONTROL1 + offset, 0x007FFFFF);
  187. WREG32(AFMT_RAMP_CONTROL2 + offset, 0x00000001);
  188. WREG32(AFMT_RAMP_CONTROL3 + offset, 0x00000001);
  189. }