evergreen.c 108 KB

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  1. /*
  2. * Copyright 2010 Advanced Micro Devices, Inc.
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice shall be included in
  12. * all copies or substantial portions of the Software.
  13. *
  14. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  17. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20. * OTHER DEALINGS IN THE SOFTWARE.
  21. *
  22. * Authors: Alex Deucher
  23. */
  24. #include <linux/firmware.h>
  25. #include <linux/platform_device.h>
  26. #include <linux/slab.h>
  27. #include "drmP.h"
  28. #include "radeon.h"
  29. #include "radeon_asic.h"
  30. #include "radeon_drm.h"
  31. #include "evergreend.h"
  32. #include "atom.h"
  33. #include "avivod.h"
  34. #include "evergreen_reg.h"
  35. #include "evergreen_blit_shaders.h"
  36. #define EVERGREEN_PFP_UCODE_SIZE 1120
  37. #define EVERGREEN_PM4_UCODE_SIZE 1376
  38. static void evergreen_gpu_init(struct radeon_device *rdev);
  39. void evergreen_fini(struct radeon_device *rdev);
  40. void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
  41. extern void cayman_cp_int_cntl_setup(struct radeon_device *rdev,
  42. int ring, u32 cp_int_cntl);
  43. void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
  44. unsigned *bankh, unsigned *mtaspect,
  45. unsigned *tile_split)
  46. {
  47. *bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK;
  48. *bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK;
  49. *mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK;
  50. *tile_split = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK;
  51. switch (*bankw) {
  52. default:
  53. case 1: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_1; break;
  54. case 2: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_2; break;
  55. case 4: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_4; break;
  56. case 8: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_8; break;
  57. }
  58. switch (*bankh) {
  59. default:
  60. case 1: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_1; break;
  61. case 2: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_2; break;
  62. case 4: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_4; break;
  63. case 8: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_8; break;
  64. }
  65. switch (*mtaspect) {
  66. default:
  67. case 1: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_1; break;
  68. case 2: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_2; break;
  69. case 4: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_4; break;
  70. case 8: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_8; break;
  71. }
  72. }
  73. void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev)
  74. {
  75. u16 ctl, v;
  76. int cap, err;
  77. cap = pci_pcie_cap(rdev->pdev);
  78. if (!cap)
  79. return;
  80. err = pci_read_config_word(rdev->pdev, cap + PCI_EXP_DEVCTL, &ctl);
  81. if (err)
  82. return;
  83. v = (ctl & PCI_EXP_DEVCTL_READRQ) >> 12;
  84. /* if bios or OS sets MAX_READ_REQUEST_SIZE to an invalid value, fix it
  85. * to avoid hangs or perfomance issues
  86. */
  87. if ((v == 0) || (v == 6) || (v == 7)) {
  88. ctl &= ~PCI_EXP_DEVCTL_READRQ;
  89. ctl |= (2 << 12);
  90. pci_write_config_word(rdev->pdev, cap + PCI_EXP_DEVCTL, ctl);
  91. }
  92. }
  93. void dce4_wait_for_vblank(struct radeon_device *rdev, int crtc)
  94. {
  95. struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc];
  96. int i;
  97. if (RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset) & EVERGREEN_CRTC_MASTER_EN) {
  98. for (i = 0; i < rdev->usec_timeout; i++) {
  99. if (!(RREG32(EVERGREEN_CRTC_STATUS + radeon_crtc->crtc_offset) & EVERGREEN_CRTC_V_BLANK))
  100. break;
  101. udelay(1);
  102. }
  103. for (i = 0; i < rdev->usec_timeout; i++) {
  104. if (RREG32(EVERGREEN_CRTC_STATUS + radeon_crtc->crtc_offset) & EVERGREEN_CRTC_V_BLANK)
  105. break;
  106. udelay(1);
  107. }
  108. }
  109. }
  110. void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc)
  111. {
  112. /* enable the pflip int */
  113. radeon_irq_kms_pflip_irq_get(rdev, crtc);
  114. }
  115. void evergreen_post_page_flip(struct radeon_device *rdev, int crtc)
  116. {
  117. /* disable the pflip int */
  118. radeon_irq_kms_pflip_irq_put(rdev, crtc);
  119. }
  120. u32 evergreen_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
  121. {
  122. struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
  123. u32 tmp = RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset);
  124. int i;
  125. /* Lock the graphics update lock */
  126. tmp |= EVERGREEN_GRPH_UPDATE_LOCK;
  127. WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
  128. /* update the scanout addresses */
  129. WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
  130. upper_32_bits(crtc_base));
  131. WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
  132. (u32)crtc_base);
  133. WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
  134. upper_32_bits(crtc_base));
  135. WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
  136. (u32)crtc_base);
  137. /* Wait for update_pending to go high. */
  138. for (i = 0; i < rdev->usec_timeout; i++) {
  139. if (RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING)
  140. break;
  141. udelay(1);
  142. }
  143. DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
  144. /* Unlock the lock, so double-buffering can take place inside vblank */
  145. tmp &= ~EVERGREEN_GRPH_UPDATE_LOCK;
  146. WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
  147. /* Return current update_pending status: */
  148. return RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING;
  149. }
  150. /* get temperature in millidegrees */
  151. int evergreen_get_temp(struct radeon_device *rdev)
  152. {
  153. u32 temp, toffset;
  154. int actual_temp = 0;
  155. if (rdev->family == CHIP_JUNIPER) {
  156. toffset = (RREG32(CG_THERMAL_CTRL) & TOFFSET_MASK) >>
  157. TOFFSET_SHIFT;
  158. temp = (RREG32(CG_TS0_STATUS) & TS0_ADC_DOUT_MASK) >>
  159. TS0_ADC_DOUT_SHIFT;
  160. if (toffset & 0x100)
  161. actual_temp = temp / 2 - (0x200 - toffset);
  162. else
  163. actual_temp = temp / 2 + toffset;
  164. actual_temp = actual_temp * 1000;
  165. } else {
  166. temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >>
  167. ASIC_T_SHIFT;
  168. if (temp & 0x400)
  169. actual_temp = -256;
  170. else if (temp & 0x200)
  171. actual_temp = 255;
  172. else if (temp & 0x100) {
  173. actual_temp = temp & 0x1ff;
  174. actual_temp |= ~0x1ff;
  175. } else
  176. actual_temp = temp & 0xff;
  177. actual_temp = (actual_temp * 1000) / 2;
  178. }
  179. return actual_temp;
  180. }
  181. int sumo_get_temp(struct radeon_device *rdev)
  182. {
  183. u32 temp = RREG32(CG_THERMAL_STATUS) & 0xff;
  184. int actual_temp = temp - 49;
  185. return actual_temp * 1000;
  186. }
  187. void sumo_pm_init_profile(struct radeon_device *rdev)
  188. {
  189. int idx;
  190. /* default */
  191. rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
  192. rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
  193. rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
  194. rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
  195. /* low,mid sh/mh */
  196. if (rdev->flags & RADEON_IS_MOBILITY)
  197. idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
  198. else
  199. idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
  200. rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx;
  201. rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx;
  202. rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
  203. rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
  204. rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx;
  205. rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx;
  206. rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
  207. rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
  208. rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx;
  209. rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx;
  210. rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
  211. rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
  212. rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx;
  213. rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx;
  214. rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
  215. rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
  216. /* high sh/mh */
  217. idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
  218. rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx;
  219. rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx;
  220. rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
  221. rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx =
  222. rdev->pm.power_state[idx].num_clock_modes - 1;
  223. rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx;
  224. rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx;
  225. rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
  226. rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx =
  227. rdev->pm.power_state[idx].num_clock_modes - 1;
  228. }
  229. void evergreen_pm_misc(struct radeon_device *rdev)
  230. {
  231. int req_ps_idx = rdev->pm.requested_power_state_index;
  232. int req_cm_idx = rdev->pm.requested_clock_mode_index;
  233. struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
  234. struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
  235. if (voltage->type == VOLTAGE_SW) {
  236. /* 0xff01 is a flag rather then an actual voltage */
  237. if (voltage->voltage == 0xff01)
  238. return;
  239. if (voltage->voltage && (voltage->voltage != rdev->pm.current_vddc)) {
  240. radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
  241. rdev->pm.current_vddc = voltage->voltage;
  242. DRM_DEBUG("Setting: vddc: %d\n", voltage->voltage);
  243. }
  244. /* 0xff01 is a flag rather then an actual voltage */
  245. if (voltage->vddci == 0xff01)
  246. return;
  247. if (voltage->vddci && (voltage->vddci != rdev->pm.current_vddci)) {
  248. radeon_atom_set_voltage(rdev, voltage->vddci, SET_VOLTAGE_TYPE_ASIC_VDDCI);
  249. rdev->pm.current_vddci = voltage->vddci;
  250. DRM_DEBUG("Setting: vddci: %d\n", voltage->vddci);
  251. }
  252. }
  253. }
  254. void evergreen_pm_prepare(struct radeon_device *rdev)
  255. {
  256. struct drm_device *ddev = rdev->ddev;
  257. struct drm_crtc *crtc;
  258. struct radeon_crtc *radeon_crtc;
  259. u32 tmp;
  260. /* disable any active CRTCs */
  261. list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
  262. radeon_crtc = to_radeon_crtc(crtc);
  263. if (radeon_crtc->enabled) {
  264. tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
  265. tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
  266. WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
  267. }
  268. }
  269. }
  270. void evergreen_pm_finish(struct radeon_device *rdev)
  271. {
  272. struct drm_device *ddev = rdev->ddev;
  273. struct drm_crtc *crtc;
  274. struct radeon_crtc *radeon_crtc;
  275. u32 tmp;
  276. /* enable any active CRTCs */
  277. list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
  278. radeon_crtc = to_radeon_crtc(crtc);
  279. if (radeon_crtc->enabled) {
  280. tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
  281. tmp &= ~EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
  282. WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
  283. }
  284. }
  285. }
  286. bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
  287. {
  288. bool connected = false;
  289. switch (hpd) {
  290. case RADEON_HPD_1:
  291. if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
  292. connected = true;
  293. break;
  294. case RADEON_HPD_2:
  295. if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
  296. connected = true;
  297. break;
  298. case RADEON_HPD_3:
  299. if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
  300. connected = true;
  301. break;
  302. case RADEON_HPD_4:
  303. if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
  304. connected = true;
  305. break;
  306. case RADEON_HPD_5:
  307. if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
  308. connected = true;
  309. break;
  310. case RADEON_HPD_6:
  311. if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
  312. connected = true;
  313. break;
  314. default:
  315. break;
  316. }
  317. return connected;
  318. }
  319. void evergreen_hpd_set_polarity(struct radeon_device *rdev,
  320. enum radeon_hpd_id hpd)
  321. {
  322. u32 tmp;
  323. bool connected = evergreen_hpd_sense(rdev, hpd);
  324. switch (hpd) {
  325. case RADEON_HPD_1:
  326. tmp = RREG32(DC_HPD1_INT_CONTROL);
  327. if (connected)
  328. tmp &= ~DC_HPDx_INT_POLARITY;
  329. else
  330. tmp |= DC_HPDx_INT_POLARITY;
  331. WREG32(DC_HPD1_INT_CONTROL, tmp);
  332. break;
  333. case RADEON_HPD_2:
  334. tmp = RREG32(DC_HPD2_INT_CONTROL);
  335. if (connected)
  336. tmp &= ~DC_HPDx_INT_POLARITY;
  337. else
  338. tmp |= DC_HPDx_INT_POLARITY;
  339. WREG32(DC_HPD2_INT_CONTROL, tmp);
  340. break;
  341. case RADEON_HPD_3:
  342. tmp = RREG32(DC_HPD3_INT_CONTROL);
  343. if (connected)
  344. tmp &= ~DC_HPDx_INT_POLARITY;
  345. else
  346. tmp |= DC_HPDx_INT_POLARITY;
  347. WREG32(DC_HPD3_INT_CONTROL, tmp);
  348. break;
  349. case RADEON_HPD_4:
  350. tmp = RREG32(DC_HPD4_INT_CONTROL);
  351. if (connected)
  352. tmp &= ~DC_HPDx_INT_POLARITY;
  353. else
  354. tmp |= DC_HPDx_INT_POLARITY;
  355. WREG32(DC_HPD4_INT_CONTROL, tmp);
  356. break;
  357. case RADEON_HPD_5:
  358. tmp = RREG32(DC_HPD5_INT_CONTROL);
  359. if (connected)
  360. tmp &= ~DC_HPDx_INT_POLARITY;
  361. else
  362. tmp |= DC_HPDx_INT_POLARITY;
  363. WREG32(DC_HPD5_INT_CONTROL, tmp);
  364. break;
  365. case RADEON_HPD_6:
  366. tmp = RREG32(DC_HPD6_INT_CONTROL);
  367. if (connected)
  368. tmp &= ~DC_HPDx_INT_POLARITY;
  369. else
  370. tmp |= DC_HPDx_INT_POLARITY;
  371. WREG32(DC_HPD6_INT_CONTROL, tmp);
  372. break;
  373. default:
  374. break;
  375. }
  376. }
  377. void evergreen_hpd_init(struct radeon_device *rdev)
  378. {
  379. struct drm_device *dev = rdev->ddev;
  380. struct drm_connector *connector;
  381. u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) |
  382. DC_HPDx_RX_INT_TIMER(0xfa) | DC_HPDx_EN;
  383. list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
  384. struct radeon_connector *radeon_connector = to_radeon_connector(connector);
  385. switch (radeon_connector->hpd.hpd) {
  386. case RADEON_HPD_1:
  387. WREG32(DC_HPD1_CONTROL, tmp);
  388. rdev->irq.hpd[0] = true;
  389. break;
  390. case RADEON_HPD_2:
  391. WREG32(DC_HPD2_CONTROL, tmp);
  392. rdev->irq.hpd[1] = true;
  393. break;
  394. case RADEON_HPD_3:
  395. WREG32(DC_HPD3_CONTROL, tmp);
  396. rdev->irq.hpd[2] = true;
  397. break;
  398. case RADEON_HPD_4:
  399. WREG32(DC_HPD4_CONTROL, tmp);
  400. rdev->irq.hpd[3] = true;
  401. break;
  402. case RADEON_HPD_5:
  403. WREG32(DC_HPD5_CONTROL, tmp);
  404. rdev->irq.hpd[4] = true;
  405. break;
  406. case RADEON_HPD_6:
  407. WREG32(DC_HPD6_CONTROL, tmp);
  408. rdev->irq.hpd[5] = true;
  409. break;
  410. default:
  411. break;
  412. }
  413. radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
  414. }
  415. if (rdev->irq.installed)
  416. evergreen_irq_set(rdev);
  417. }
  418. void evergreen_hpd_fini(struct radeon_device *rdev)
  419. {
  420. struct drm_device *dev = rdev->ddev;
  421. struct drm_connector *connector;
  422. list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
  423. struct radeon_connector *radeon_connector = to_radeon_connector(connector);
  424. switch (radeon_connector->hpd.hpd) {
  425. case RADEON_HPD_1:
  426. WREG32(DC_HPD1_CONTROL, 0);
  427. rdev->irq.hpd[0] = false;
  428. break;
  429. case RADEON_HPD_2:
  430. WREG32(DC_HPD2_CONTROL, 0);
  431. rdev->irq.hpd[1] = false;
  432. break;
  433. case RADEON_HPD_3:
  434. WREG32(DC_HPD3_CONTROL, 0);
  435. rdev->irq.hpd[2] = false;
  436. break;
  437. case RADEON_HPD_4:
  438. WREG32(DC_HPD4_CONTROL, 0);
  439. rdev->irq.hpd[3] = false;
  440. break;
  441. case RADEON_HPD_5:
  442. WREG32(DC_HPD5_CONTROL, 0);
  443. rdev->irq.hpd[4] = false;
  444. break;
  445. case RADEON_HPD_6:
  446. WREG32(DC_HPD6_CONTROL, 0);
  447. rdev->irq.hpd[5] = false;
  448. break;
  449. default:
  450. break;
  451. }
  452. }
  453. }
  454. /* watermark setup */
  455. static u32 evergreen_line_buffer_adjust(struct radeon_device *rdev,
  456. struct radeon_crtc *radeon_crtc,
  457. struct drm_display_mode *mode,
  458. struct drm_display_mode *other_mode)
  459. {
  460. u32 tmp;
  461. /*
  462. * Line Buffer Setup
  463. * There are 3 line buffers, each one shared by 2 display controllers.
  464. * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
  465. * the display controllers. The paritioning is done via one of four
  466. * preset allocations specified in bits 2:0:
  467. * first display controller
  468. * 0 - first half of lb (3840 * 2)
  469. * 1 - first 3/4 of lb (5760 * 2)
  470. * 2 - whole lb (7680 * 2), other crtc must be disabled
  471. * 3 - first 1/4 of lb (1920 * 2)
  472. * second display controller
  473. * 4 - second half of lb (3840 * 2)
  474. * 5 - second 3/4 of lb (5760 * 2)
  475. * 6 - whole lb (7680 * 2), other crtc must be disabled
  476. * 7 - last 1/4 of lb (1920 * 2)
  477. */
  478. /* this can get tricky if we have two large displays on a paired group
  479. * of crtcs. Ideally for multiple large displays we'd assign them to
  480. * non-linked crtcs for maximum line buffer allocation.
  481. */
  482. if (radeon_crtc->base.enabled && mode) {
  483. if (other_mode)
  484. tmp = 0; /* 1/2 */
  485. else
  486. tmp = 2; /* whole */
  487. } else
  488. tmp = 0;
  489. /* second controller of the pair uses second half of the lb */
  490. if (radeon_crtc->crtc_id % 2)
  491. tmp += 4;
  492. WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, tmp);
  493. if (radeon_crtc->base.enabled && mode) {
  494. switch (tmp) {
  495. case 0:
  496. case 4:
  497. default:
  498. if (ASIC_IS_DCE5(rdev))
  499. return 4096 * 2;
  500. else
  501. return 3840 * 2;
  502. case 1:
  503. case 5:
  504. if (ASIC_IS_DCE5(rdev))
  505. return 6144 * 2;
  506. else
  507. return 5760 * 2;
  508. case 2:
  509. case 6:
  510. if (ASIC_IS_DCE5(rdev))
  511. return 8192 * 2;
  512. else
  513. return 7680 * 2;
  514. case 3:
  515. case 7:
  516. if (ASIC_IS_DCE5(rdev))
  517. return 2048 * 2;
  518. else
  519. return 1920 * 2;
  520. }
  521. }
  522. /* controller not enabled, so no lb used */
  523. return 0;
  524. }
  525. u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev)
  526. {
  527. u32 tmp = RREG32(MC_SHARED_CHMAP);
  528. switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
  529. case 0:
  530. default:
  531. return 1;
  532. case 1:
  533. return 2;
  534. case 2:
  535. return 4;
  536. case 3:
  537. return 8;
  538. }
  539. }
  540. struct evergreen_wm_params {
  541. u32 dram_channels; /* number of dram channels */
  542. u32 yclk; /* bandwidth per dram data pin in kHz */
  543. u32 sclk; /* engine clock in kHz */
  544. u32 disp_clk; /* display clock in kHz */
  545. u32 src_width; /* viewport width */
  546. u32 active_time; /* active display time in ns */
  547. u32 blank_time; /* blank time in ns */
  548. bool interlaced; /* mode is interlaced */
  549. fixed20_12 vsc; /* vertical scale ratio */
  550. u32 num_heads; /* number of active crtcs */
  551. u32 bytes_per_pixel; /* bytes per pixel display + overlay */
  552. u32 lb_size; /* line buffer allocated to pipe */
  553. u32 vtaps; /* vertical scaler taps */
  554. };
  555. static u32 evergreen_dram_bandwidth(struct evergreen_wm_params *wm)
  556. {
  557. /* Calculate DRAM Bandwidth and the part allocated to display. */
  558. fixed20_12 dram_efficiency; /* 0.7 */
  559. fixed20_12 yclk, dram_channels, bandwidth;
  560. fixed20_12 a;
  561. a.full = dfixed_const(1000);
  562. yclk.full = dfixed_const(wm->yclk);
  563. yclk.full = dfixed_div(yclk, a);
  564. dram_channels.full = dfixed_const(wm->dram_channels * 4);
  565. a.full = dfixed_const(10);
  566. dram_efficiency.full = dfixed_const(7);
  567. dram_efficiency.full = dfixed_div(dram_efficiency, a);
  568. bandwidth.full = dfixed_mul(dram_channels, yclk);
  569. bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
  570. return dfixed_trunc(bandwidth);
  571. }
  572. static u32 evergreen_dram_bandwidth_for_display(struct evergreen_wm_params *wm)
  573. {
  574. /* Calculate DRAM Bandwidth and the part allocated to display. */
  575. fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
  576. fixed20_12 yclk, dram_channels, bandwidth;
  577. fixed20_12 a;
  578. a.full = dfixed_const(1000);
  579. yclk.full = dfixed_const(wm->yclk);
  580. yclk.full = dfixed_div(yclk, a);
  581. dram_channels.full = dfixed_const(wm->dram_channels * 4);
  582. a.full = dfixed_const(10);
  583. disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
  584. disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
  585. bandwidth.full = dfixed_mul(dram_channels, yclk);
  586. bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
  587. return dfixed_trunc(bandwidth);
  588. }
  589. static u32 evergreen_data_return_bandwidth(struct evergreen_wm_params *wm)
  590. {
  591. /* Calculate the display Data return Bandwidth */
  592. fixed20_12 return_efficiency; /* 0.8 */
  593. fixed20_12 sclk, bandwidth;
  594. fixed20_12 a;
  595. a.full = dfixed_const(1000);
  596. sclk.full = dfixed_const(wm->sclk);
  597. sclk.full = dfixed_div(sclk, a);
  598. a.full = dfixed_const(10);
  599. return_efficiency.full = dfixed_const(8);
  600. return_efficiency.full = dfixed_div(return_efficiency, a);
  601. a.full = dfixed_const(32);
  602. bandwidth.full = dfixed_mul(a, sclk);
  603. bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
  604. return dfixed_trunc(bandwidth);
  605. }
  606. static u32 evergreen_dmif_request_bandwidth(struct evergreen_wm_params *wm)
  607. {
  608. /* Calculate the DMIF Request Bandwidth */
  609. fixed20_12 disp_clk_request_efficiency; /* 0.8 */
  610. fixed20_12 disp_clk, bandwidth;
  611. fixed20_12 a;
  612. a.full = dfixed_const(1000);
  613. disp_clk.full = dfixed_const(wm->disp_clk);
  614. disp_clk.full = dfixed_div(disp_clk, a);
  615. a.full = dfixed_const(10);
  616. disp_clk_request_efficiency.full = dfixed_const(8);
  617. disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
  618. a.full = dfixed_const(32);
  619. bandwidth.full = dfixed_mul(a, disp_clk);
  620. bandwidth.full = dfixed_mul(bandwidth, disp_clk_request_efficiency);
  621. return dfixed_trunc(bandwidth);
  622. }
  623. static u32 evergreen_available_bandwidth(struct evergreen_wm_params *wm)
  624. {
  625. /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
  626. u32 dram_bandwidth = evergreen_dram_bandwidth(wm);
  627. u32 data_return_bandwidth = evergreen_data_return_bandwidth(wm);
  628. u32 dmif_req_bandwidth = evergreen_dmif_request_bandwidth(wm);
  629. return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
  630. }
  631. static u32 evergreen_average_bandwidth(struct evergreen_wm_params *wm)
  632. {
  633. /* Calculate the display mode Average Bandwidth
  634. * DisplayMode should contain the source and destination dimensions,
  635. * timing, etc.
  636. */
  637. fixed20_12 bpp;
  638. fixed20_12 line_time;
  639. fixed20_12 src_width;
  640. fixed20_12 bandwidth;
  641. fixed20_12 a;
  642. a.full = dfixed_const(1000);
  643. line_time.full = dfixed_const(wm->active_time + wm->blank_time);
  644. line_time.full = dfixed_div(line_time, a);
  645. bpp.full = dfixed_const(wm->bytes_per_pixel);
  646. src_width.full = dfixed_const(wm->src_width);
  647. bandwidth.full = dfixed_mul(src_width, bpp);
  648. bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
  649. bandwidth.full = dfixed_div(bandwidth, line_time);
  650. return dfixed_trunc(bandwidth);
  651. }
  652. static u32 evergreen_latency_watermark(struct evergreen_wm_params *wm)
  653. {
  654. /* First calcualte the latency in ns */
  655. u32 mc_latency = 2000; /* 2000 ns. */
  656. u32 available_bandwidth = evergreen_available_bandwidth(wm);
  657. u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
  658. u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
  659. u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
  660. u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
  661. (wm->num_heads * cursor_line_pair_return_time);
  662. u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
  663. u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
  664. fixed20_12 a, b, c;
  665. if (wm->num_heads == 0)
  666. return 0;
  667. a.full = dfixed_const(2);
  668. b.full = dfixed_const(1);
  669. if ((wm->vsc.full > a.full) ||
  670. ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
  671. (wm->vtaps >= 5) ||
  672. ((wm->vsc.full >= a.full) && wm->interlaced))
  673. max_src_lines_per_dst_line = 4;
  674. else
  675. max_src_lines_per_dst_line = 2;
  676. a.full = dfixed_const(available_bandwidth);
  677. b.full = dfixed_const(wm->num_heads);
  678. a.full = dfixed_div(a, b);
  679. b.full = dfixed_const(1000);
  680. c.full = dfixed_const(wm->disp_clk);
  681. b.full = dfixed_div(c, b);
  682. c.full = dfixed_const(wm->bytes_per_pixel);
  683. b.full = dfixed_mul(b, c);
  684. lb_fill_bw = min(dfixed_trunc(a), dfixed_trunc(b));
  685. a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
  686. b.full = dfixed_const(1000);
  687. c.full = dfixed_const(lb_fill_bw);
  688. b.full = dfixed_div(c, b);
  689. a.full = dfixed_div(a, b);
  690. line_fill_time = dfixed_trunc(a);
  691. if (line_fill_time < wm->active_time)
  692. return latency;
  693. else
  694. return latency + (line_fill_time - wm->active_time);
  695. }
  696. static bool evergreen_average_bandwidth_vs_dram_bandwidth_for_display(struct evergreen_wm_params *wm)
  697. {
  698. if (evergreen_average_bandwidth(wm) <=
  699. (evergreen_dram_bandwidth_for_display(wm) / wm->num_heads))
  700. return true;
  701. else
  702. return false;
  703. };
  704. static bool evergreen_average_bandwidth_vs_available_bandwidth(struct evergreen_wm_params *wm)
  705. {
  706. if (evergreen_average_bandwidth(wm) <=
  707. (evergreen_available_bandwidth(wm) / wm->num_heads))
  708. return true;
  709. else
  710. return false;
  711. };
  712. static bool evergreen_check_latency_hiding(struct evergreen_wm_params *wm)
  713. {
  714. u32 lb_partitions = wm->lb_size / wm->src_width;
  715. u32 line_time = wm->active_time + wm->blank_time;
  716. u32 latency_tolerant_lines;
  717. u32 latency_hiding;
  718. fixed20_12 a;
  719. a.full = dfixed_const(1);
  720. if (wm->vsc.full > a.full)
  721. latency_tolerant_lines = 1;
  722. else {
  723. if (lb_partitions <= (wm->vtaps + 1))
  724. latency_tolerant_lines = 1;
  725. else
  726. latency_tolerant_lines = 2;
  727. }
  728. latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
  729. if (evergreen_latency_watermark(wm) <= latency_hiding)
  730. return true;
  731. else
  732. return false;
  733. }
  734. static void evergreen_program_watermarks(struct radeon_device *rdev,
  735. struct radeon_crtc *radeon_crtc,
  736. u32 lb_size, u32 num_heads)
  737. {
  738. struct drm_display_mode *mode = &radeon_crtc->base.mode;
  739. struct evergreen_wm_params wm;
  740. u32 pixel_period;
  741. u32 line_time = 0;
  742. u32 latency_watermark_a = 0, latency_watermark_b = 0;
  743. u32 priority_a_mark = 0, priority_b_mark = 0;
  744. u32 priority_a_cnt = PRIORITY_OFF;
  745. u32 priority_b_cnt = PRIORITY_OFF;
  746. u32 pipe_offset = radeon_crtc->crtc_id * 16;
  747. u32 tmp, arb_control3;
  748. fixed20_12 a, b, c;
  749. if (radeon_crtc->base.enabled && num_heads && mode) {
  750. pixel_period = 1000000 / (u32)mode->clock;
  751. line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
  752. priority_a_cnt = 0;
  753. priority_b_cnt = 0;
  754. wm.yclk = rdev->pm.current_mclk * 10;
  755. wm.sclk = rdev->pm.current_sclk * 10;
  756. wm.disp_clk = mode->clock;
  757. wm.src_width = mode->crtc_hdisplay;
  758. wm.active_time = mode->crtc_hdisplay * pixel_period;
  759. wm.blank_time = line_time - wm.active_time;
  760. wm.interlaced = false;
  761. if (mode->flags & DRM_MODE_FLAG_INTERLACE)
  762. wm.interlaced = true;
  763. wm.vsc = radeon_crtc->vsc;
  764. wm.vtaps = 1;
  765. if (radeon_crtc->rmx_type != RMX_OFF)
  766. wm.vtaps = 2;
  767. wm.bytes_per_pixel = 4; /* XXX: get this from fb config */
  768. wm.lb_size = lb_size;
  769. wm.dram_channels = evergreen_get_number_of_dram_channels(rdev);
  770. wm.num_heads = num_heads;
  771. /* set for high clocks */
  772. latency_watermark_a = min(evergreen_latency_watermark(&wm), (u32)65535);
  773. /* set for low clocks */
  774. /* wm.yclk = low clk; wm.sclk = low clk */
  775. latency_watermark_b = min(evergreen_latency_watermark(&wm), (u32)65535);
  776. /* possibly force display priority to high */
  777. /* should really do this at mode validation time... */
  778. if (!evergreen_average_bandwidth_vs_dram_bandwidth_for_display(&wm) ||
  779. !evergreen_average_bandwidth_vs_available_bandwidth(&wm) ||
  780. !evergreen_check_latency_hiding(&wm) ||
  781. (rdev->disp_priority == 2)) {
  782. DRM_DEBUG_KMS("force priority to high\n");
  783. priority_a_cnt |= PRIORITY_ALWAYS_ON;
  784. priority_b_cnt |= PRIORITY_ALWAYS_ON;
  785. }
  786. a.full = dfixed_const(1000);
  787. b.full = dfixed_const(mode->clock);
  788. b.full = dfixed_div(b, a);
  789. c.full = dfixed_const(latency_watermark_a);
  790. c.full = dfixed_mul(c, b);
  791. c.full = dfixed_mul(c, radeon_crtc->hsc);
  792. c.full = dfixed_div(c, a);
  793. a.full = dfixed_const(16);
  794. c.full = dfixed_div(c, a);
  795. priority_a_mark = dfixed_trunc(c);
  796. priority_a_cnt |= priority_a_mark & PRIORITY_MARK_MASK;
  797. a.full = dfixed_const(1000);
  798. b.full = dfixed_const(mode->clock);
  799. b.full = dfixed_div(b, a);
  800. c.full = dfixed_const(latency_watermark_b);
  801. c.full = dfixed_mul(c, b);
  802. c.full = dfixed_mul(c, radeon_crtc->hsc);
  803. c.full = dfixed_div(c, a);
  804. a.full = dfixed_const(16);
  805. c.full = dfixed_div(c, a);
  806. priority_b_mark = dfixed_trunc(c);
  807. priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK;
  808. }
  809. /* select wm A */
  810. arb_control3 = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
  811. tmp = arb_control3;
  812. tmp &= ~LATENCY_WATERMARK_MASK(3);
  813. tmp |= LATENCY_WATERMARK_MASK(1);
  814. WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
  815. WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,
  816. (LATENCY_LOW_WATERMARK(latency_watermark_a) |
  817. LATENCY_HIGH_WATERMARK(line_time)));
  818. /* select wm B */
  819. tmp = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
  820. tmp &= ~LATENCY_WATERMARK_MASK(3);
  821. tmp |= LATENCY_WATERMARK_MASK(2);
  822. WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
  823. WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,
  824. (LATENCY_LOW_WATERMARK(latency_watermark_b) |
  825. LATENCY_HIGH_WATERMARK(line_time)));
  826. /* restore original selection */
  827. WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, arb_control3);
  828. /* write the priority marks */
  829. WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt);
  830. WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt);
  831. }
  832. void evergreen_bandwidth_update(struct radeon_device *rdev)
  833. {
  834. struct drm_display_mode *mode0 = NULL;
  835. struct drm_display_mode *mode1 = NULL;
  836. u32 num_heads = 0, lb_size;
  837. int i;
  838. radeon_update_display_priority(rdev);
  839. for (i = 0; i < rdev->num_crtc; i++) {
  840. if (rdev->mode_info.crtcs[i]->base.enabled)
  841. num_heads++;
  842. }
  843. for (i = 0; i < rdev->num_crtc; i += 2) {
  844. mode0 = &rdev->mode_info.crtcs[i]->base.mode;
  845. mode1 = &rdev->mode_info.crtcs[i+1]->base.mode;
  846. lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode0, mode1);
  847. evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i], lb_size, num_heads);
  848. lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i+1], mode1, mode0);
  849. evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i+1], lb_size, num_heads);
  850. }
  851. }
  852. int evergreen_mc_wait_for_idle(struct radeon_device *rdev)
  853. {
  854. unsigned i;
  855. u32 tmp;
  856. for (i = 0; i < rdev->usec_timeout; i++) {
  857. /* read MC_STATUS */
  858. tmp = RREG32(SRBM_STATUS) & 0x1F00;
  859. if (!tmp)
  860. return 0;
  861. udelay(1);
  862. }
  863. return -1;
  864. }
  865. /*
  866. * GART
  867. */
  868. void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev)
  869. {
  870. unsigned i;
  871. u32 tmp;
  872. WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
  873. WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
  874. for (i = 0; i < rdev->usec_timeout; i++) {
  875. /* read MC_STATUS */
  876. tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
  877. tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
  878. if (tmp == 2) {
  879. printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
  880. return;
  881. }
  882. if (tmp) {
  883. return;
  884. }
  885. udelay(1);
  886. }
  887. }
  888. int evergreen_pcie_gart_enable(struct radeon_device *rdev)
  889. {
  890. u32 tmp;
  891. int r;
  892. if (rdev->gart.robj == NULL) {
  893. dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
  894. return -EINVAL;
  895. }
  896. r = radeon_gart_table_vram_pin(rdev);
  897. if (r)
  898. return r;
  899. radeon_gart_restore(rdev);
  900. /* Setup L2 cache */
  901. WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
  902. ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
  903. EFFECTIVE_L2_QUEUE_SIZE(7));
  904. WREG32(VM_L2_CNTL2, 0);
  905. WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
  906. /* Setup TLB control */
  907. tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
  908. SYSTEM_ACCESS_MODE_NOT_IN_SYS |
  909. SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
  910. EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
  911. if (rdev->flags & RADEON_IS_IGP) {
  912. WREG32(FUS_MC_VM_MD_L1_TLB0_CNTL, tmp);
  913. WREG32(FUS_MC_VM_MD_L1_TLB1_CNTL, tmp);
  914. WREG32(FUS_MC_VM_MD_L1_TLB2_CNTL, tmp);
  915. } else {
  916. WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
  917. WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
  918. WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
  919. if ((rdev->family == CHIP_JUNIPER) ||
  920. (rdev->family == CHIP_CYPRESS) ||
  921. (rdev->family == CHIP_HEMLOCK) ||
  922. (rdev->family == CHIP_BARTS))
  923. WREG32(MC_VM_MD_L1_TLB3_CNTL, tmp);
  924. }
  925. WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
  926. WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
  927. WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
  928. WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
  929. WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
  930. WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
  931. WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
  932. WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
  933. RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
  934. WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
  935. (u32)(rdev->dummy_page.addr >> 12));
  936. WREG32(VM_CONTEXT1_CNTL, 0);
  937. evergreen_pcie_gart_tlb_flush(rdev);
  938. DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
  939. (unsigned)(rdev->mc.gtt_size >> 20),
  940. (unsigned long long)rdev->gart.table_addr);
  941. rdev->gart.ready = true;
  942. return 0;
  943. }
  944. void evergreen_pcie_gart_disable(struct radeon_device *rdev)
  945. {
  946. u32 tmp;
  947. /* Disable all tables */
  948. WREG32(VM_CONTEXT0_CNTL, 0);
  949. WREG32(VM_CONTEXT1_CNTL, 0);
  950. /* Setup L2 cache */
  951. WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
  952. EFFECTIVE_L2_QUEUE_SIZE(7));
  953. WREG32(VM_L2_CNTL2, 0);
  954. WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
  955. /* Setup TLB control */
  956. tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
  957. WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
  958. WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
  959. WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
  960. WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
  961. WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
  962. WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
  963. WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
  964. radeon_gart_table_vram_unpin(rdev);
  965. }
  966. void evergreen_pcie_gart_fini(struct radeon_device *rdev)
  967. {
  968. evergreen_pcie_gart_disable(rdev);
  969. radeon_gart_table_vram_free(rdev);
  970. radeon_gart_fini(rdev);
  971. }
  972. void evergreen_agp_enable(struct radeon_device *rdev)
  973. {
  974. u32 tmp;
  975. /* Setup L2 cache */
  976. WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
  977. ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
  978. EFFECTIVE_L2_QUEUE_SIZE(7));
  979. WREG32(VM_L2_CNTL2, 0);
  980. WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
  981. /* Setup TLB control */
  982. tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
  983. SYSTEM_ACCESS_MODE_NOT_IN_SYS |
  984. SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
  985. EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
  986. WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
  987. WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
  988. WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
  989. WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
  990. WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
  991. WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
  992. WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
  993. WREG32(VM_CONTEXT0_CNTL, 0);
  994. WREG32(VM_CONTEXT1_CNTL, 0);
  995. }
  996. void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save)
  997. {
  998. save->vga_control[0] = RREG32(D1VGA_CONTROL);
  999. save->vga_control[1] = RREG32(D2VGA_CONTROL);
  1000. save->vga_render_control = RREG32(VGA_RENDER_CONTROL);
  1001. save->vga_hdp_control = RREG32(VGA_HDP_CONTROL);
  1002. save->crtc_control[0] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET);
  1003. save->crtc_control[1] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
  1004. if (rdev->num_crtc >= 4) {
  1005. save->vga_control[2] = RREG32(EVERGREEN_D3VGA_CONTROL);
  1006. save->vga_control[3] = RREG32(EVERGREEN_D4VGA_CONTROL);
  1007. save->crtc_control[2] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET);
  1008. save->crtc_control[3] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
  1009. }
  1010. if (rdev->num_crtc >= 6) {
  1011. save->vga_control[4] = RREG32(EVERGREEN_D5VGA_CONTROL);
  1012. save->vga_control[5] = RREG32(EVERGREEN_D6VGA_CONTROL);
  1013. save->crtc_control[4] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET);
  1014. save->crtc_control[5] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
  1015. }
  1016. /* Stop all video */
  1017. WREG32(VGA_RENDER_CONTROL, 0);
  1018. WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
  1019. WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
  1020. if (rdev->num_crtc >= 4) {
  1021. WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
  1022. WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
  1023. }
  1024. if (rdev->num_crtc >= 6) {
  1025. WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
  1026. WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
  1027. }
  1028. WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
  1029. WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
  1030. if (rdev->num_crtc >= 4) {
  1031. WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
  1032. WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
  1033. }
  1034. if (rdev->num_crtc >= 6) {
  1035. WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
  1036. WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
  1037. }
  1038. WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
  1039. WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
  1040. if (rdev->num_crtc >= 4) {
  1041. WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
  1042. WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
  1043. }
  1044. if (rdev->num_crtc >= 6) {
  1045. WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
  1046. WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
  1047. }
  1048. WREG32(D1VGA_CONTROL, 0);
  1049. WREG32(D2VGA_CONTROL, 0);
  1050. if (rdev->num_crtc >= 4) {
  1051. WREG32(EVERGREEN_D3VGA_CONTROL, 0);
  1052. WREG32(EVERGREEN_D4VGA_CONTROL, 0);
  1053. }
  1054. if (rdev->num_crtc >= 6) {
  1055. WREG32(EVERGREEN_D5VGA_CONTROL, 0);
  1056. WREG32(EVERGREEN_D6VGA_CONTROL, 0);
  1057. }
  1058. }
  1059. void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save)
  1060. {
  1061. WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET,
  1062. upper_32_bits(rdev->mc.vram_start));
  1063. WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET,
  1064. upper_32_bits(rdev->mc.vram_start));
  1065. WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET,
  1066. (u32)rdev->mc.vram_start);
  1067. WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET,
  1068. (u32)rdev->mc.vram_start);
  1069. WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET,
  1070. upper_32_bits(rdev->mc.vram_start));
  1071. WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET,
  1072. upper_32_bits(rdev->mc.vram_start));
  1073. WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET,
  1074. (u32)rdev->mc.vram_start);
  1075. WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET,
  1076. (u32)rdev->mc.vram_start);
  1077. if (rdev->num_crtc >= 4) {
  1078. WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
  1079. upper_32_bits(rdev->mc.vram_start));
  1080. WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
  1081. upper_32_bits(rdev->mc.vram_start));
  1082. WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET,
  1083. (u32)rdev->mc.vram_start);
  1084. WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET,
  1085. (u32)rdev->mc.vram_start);
  1086. WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET,
  1087. upper_32_bits(rdev->mc.vram_start));
  1088. WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET,
  1089. upper_32_bits(rdev->mc.vram_start));
  1090. WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET,
  1091. (u32)rdev->mc.vram_start);
  1092. WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET,
  1093. (u32)rdev->mc.vram_start);
  1094. }
  1095. if (rdev->num_crtc >= 6) {
  1096. WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
  1097. upper_32_bits(rdev->mc.vram_start));
  1098. WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
  1099. upper_32_bits(rdev->mc.vram_start));
  1100. WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET,
  1101. (u32)rdev->mc.vram_start);
  1102. WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET,
  1103. (u32)rdev->mc.vram_start);
  1104. WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET,
  1105. upper_32_bits(rdev->mc.vram_start));
  1106. WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET,
  1107. upper_32_bits(rdev->mc.vram_start));
  1108. WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET,
  1109. (u32)rdev->mc.vram_start);
  1110. WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET,
  1111. (u32)rdev->mc.vram_start);
  1112. }
  1113. WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start));
  1114. WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);
  1115. /* Unlock host access */
  1116. WREG32(VGA_HDP_CONTROL, save->vga_hdp_control);
  1117. mdelay(1);
  1118. /* Restore video state */
  1119. WREG32(D1VGA_CONTROL, save->vga_control[0]);
  1120. WREG32(D2VGA_CONTROL, save->vga_control[1]);
  1121. if (rdev->num_crtc >= 4) {
  1122. WREG32(EVERGREEN_D3VGA_CONTROL, save->vga_control[2]);
  1123. WREG32(EVERGREEN_D4VGA_CONTROL, save->vga_control[3]);
  1124. }
  1125. if (rdev->num_crtc >= 6) {
  1126. WREG32(EVERGREEN_D5VGA_CONTROL, save->vga_control[4]);
  1127. WREG32(EVERGREEN_D6VGA_CONTROL, save->vga_control[5]);
  1128. }
  1129. WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
  1130. WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
  1131. if (rdev->num_crtc >= 4) {
  1132. WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
  1133. WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
  1134. }
  1135. if (rdev->num_crtc >= 6) {
  1136. WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
  1137. WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
  1138. }
  1139. WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, save->crtc_control[0]);
  1140. WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, save->crtc_control[1]);
  1141. if (rdev->num_crtc >= 4) {
  1142. WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, save->crtc_control[2]);
  1143. WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, save->crtc_control[3]);
  1144. }
  1145. if (rdev->num_crtc >= 6) {
  1146. WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, save->crtc_control[4]);
  1147. WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, save->crtc_control[5]);
  1148. }
  1149. WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
  1150. WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
  1151. if (rdev->num_crtc >= 4) {
  1152. WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
  1153. WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
  1154. }
  1155. if (rdev->num_crtc >= 6) {
  1156. WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
  1157. WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
  1158. }
  1159. WREG32(VGA_RENDER_CONTROL, save->vga_render_control);
  1160. }
  1161. void evergreen_mc_program(struct radeon_device *rdev)
  1162. {
  1163. struct evergreen_mc_save save;
  1164. u32 tmp;
  1165. int i, j;
  1166. /* Initialize HDP */
  1167. for (i = 0, j = 0; i < 32; i++, j += 0x18) {
  1168. WREG32((0x2c14 + j), 0x00000000);
  1169. WREG32((0x2c18 + j), 0x00000000);
  1170. WREG32((0x2c1c + j), 0x00000000);
  1171. WREG32((0x2c20 + j), 0x00000000);
  1172. WREG32((0x2c24 + j), 0x00000000);
  1173. }
  1174. WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
  1175. evergreen_mc_stop(rdev, &save);
  1176. if (evergreen_mc_wait_for_idle(rdev)) {
  1177. dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
  1178. }
  1179. /* Lockout access through VGA aperture*/
  1180. WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
  1181. /* Update configuration */
  1182. if (rdev->flags & RADEON_IS_AGP) {
  1183. if (rdev->mc.vram_start < rdev->mc.gtt_start) {
  1184. /* VRAM before AGP */
  1185. WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
  1186. rdev->mc.vram_start >> 12);
  1187. WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
  1188. rdev->mc.gtt_end >> 12);
  1189. } else {
  1190. /* VRAM after AGP */
  1191. WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
  1192. rdev->mc.gtt_start >> 12);
  1193. WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
  1194. rdev->mc.vram_end >> 12);
  1195. }
  1196. } else {
  1197. WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
  1198. rdev->mc.vram_start >> 12);
  1199. WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
  1200. rdev->mc.vram_end >> 12);
  1201. }
  1202. WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12);
  1203. /* llano/ontario only */
  1204. if ((rdev->family == CHIP_PALM) ||
  1205. (rdev->family == CHIP_SUMO) ||
  1206. (rdev->family == CHIP_SUMO2)) {
  1207. tmp = RREG32(MC_FUS_VM_FB_OFFSET) & 0x000FFFFF;
  1208. tmp |= ((rdev->mc.vram_end >> 20) & 0xF) << 24;
  1209. tmp |= ((rdev->mc.vram_start >> 20) & 0xF) << 20;
  1210. WREG32(MC_FUS_VM_FB_OFFSET, tmp);
  1211. }
  1212. tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
  1213. tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
  1214. WREG32(MC_VM_FB_LOCATION, tmp);
  1215. WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
  1216. WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
  1217. WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
  1218. if (rdev->flags & RADEON_IS_AGP) {
  1219. WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
  1220. WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
  1221. WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
  1222. } else {
  1223. WREG32(MC_VM_AGP_BASE, 0);
  1224. WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
  1225. WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
  1226. }
  1227. if (evergreen_mc_wait_for_idle(rdev)) {
  1228. dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
  1229. }
  1230. evergreen_mc_resume(rdev, &save);
  1231. /* we need to own VRAM, so turn off the VGA renderer here
  1232. * to stop it overwriting our objects */
  1233. rv515_vga_render_disable(rdev);
  1234. }
  1235. /*
  1236. * CP.
  1237. */
  1238. void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
  1239. {
  1240. struct radeon_ring *ring = &rdev->ring[ib->fence->ring];
  1241. /* set to DX10/11 mode */
  1242. radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0));
  1243. radeon_ring_write(ring, 1);
  1244. /* FIXME: implement */
  1245. radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
  1246. radeon_ring_write(ring,
  1247. #ifdef __BIG_ENDIAN
  1248. (2 << 0) |
  1249. #endif
  1250. (ib->gpu_addr & 0xFFFFFFFC));
  1251. radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);
  1252. radeon_ring_write(ring, ib->length_dw);
  1253. }
  1254. static int evergreen_cp_load_microcode(struct radeon_device *rdev)
  1255. {
  1256. const __be32 *fw_data;
  1257. int i;
  1258. if (!rdev->me_fw || !rdev->pfp_fw)
  1259. return -EINVAL;
  1260. r700_cp_stop(rdev);
  1261. WREG32(CP_RB_CNTL,
  1262. #ifdef __BIG_ENDIAN
  1263. BUF_SWAP_32BIT |
  1264. #endif
  1265. RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
  1266. fw_data = (const __be32 *)rdev->pfp_fw->data;
  1267. WREG32(CP_PFP_UCODE_ADDR, 0);
  1268. for (i = 0; i < EVERGREEN_PFP_UCODE_SIZE; i++)
  1269. WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
  1270. WREG32(CP_PFP_UCODE_ADDR, 0);
  1271. fw_data = (const __be32 *)rdev->me_fw->data;
  1272. WREG32(CP_ME_RAM_WADDR, 0);
  1273. for (i = 0; i < EVERGREEN_PM4_UCODE_SIZE; i++)
  1274. WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
  1275. WREG32(CP_PFP_UCODE_ADDR, 0);
  1276. WREG32(CP_ME_RAM_WADDR, 0);
  1277. WREG32(CP_ME_RAM_RADDR, 0);
  1278. return 0;
  1279. }
  1280. static int evergreen_cp_start(struct radeon_device *rdev)
  1281. {
  1282. struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
  1283. int r, i;
  1284. uint32_t cp_me;
  1285. r = radeon_ring_lock(rdev, ring, 7);
  1286. if (r) {
  1287. DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
  1288. return r;
  1289. }
  1290. radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
  1291. radeon_ring_write(ring, 0x1);
  1292. radeon_ring_write(ring, 0x0);
  1293. radeon_ring_write(ring, rdev->config.evergreen.max_hw_contexts - 1);
  1294. radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
  1295. radeon_ring_write(ring, 0);
  1296. radeon_ring_write(ring, 0);
  1297. radeon_ring_unlock_commit(rdev, ring);
  1298. cp_me = 0xff;
  1299. WREG32(CP_ME_CNTL, cp_me);
  1300. r = radeon_ring_lock(rdev, ring, evergreen_default_size + 19);
  1301. if (r) {
  1302. DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
  1303. return r;
  1304. }
  1305. /* setup clear context state */
  1306. radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
  1307. radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
  1308. for (i = 0; i < evergreen_default_size; i++)
  1309. radeon_ring_write(ring, evergreen_default_state[i]);
  1310. radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
  1311. radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
  1312. /* set clear context state */
  1313. radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
  1314. radeon_ring_write(ring, 0);
  1315. /* SQ_VTX_BASE_VTX_LOC */
  1316. radeon_ring_write(ring, 0xc0026f00);
  1317. radeon_ring_write(ring, 0x00000000);
  1318. radeon_ring_write(ring, 0x00000000);
  1319. radeon_ring_write(ring, 0x00000000);
  1320. /* Clear consts */
  1321. radeon_ring_write(ring, 0xc0036f00);
  1322. radeon_ring_write(ring, 0x00000bc4);
  1323. radeon_ring_write(ring, 0xffffffff);
  1324. radeon_ring_write(ring, 0xffffffff);
  1325. radeon_ring_write(ring, 0xffffffff);
  1326. radeon_ring_write(ring, 0xc0026900);
  1327. radeon_ring_write(ring, 0x00000316);
  1328. radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
  1329. radeon_ring_write(ring, 0x00000010); /* */
  1330. radeon_ring_unlock_commit(rdev, ring);
  1331. return 0;
  1332. }
  1333. int evergreen_cp_resume(struct radeon_device *rdev)
  1334. {
  1335. struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
  1336. u32 tmp;
  1337. u32 rb_bufsz;
  1338. int r;
  1339. /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
  1340. WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
  1341. SOFT_RESET_PA |
  1342. SOFT_RESET_SH |
  1343. SOFT_RESET_VGT |
  1344. SOFT_RESET_SPI |
  1345. SOFT_RESET_SX));
  1346. RREG32(GRBM_SOFT_RESET);
  1347. mdelay(15);
  1348. WREG32(GRBM_SOFT_RESET, 0);
  1349. RREG32(GRBM_SOFT_RESET);
  1350. /* Set ring buffer size */
  1351. rb_bufsz = drm_order(ring->ring_size / 8);
  1352. tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
  1353. #ifdef __BIG_ENDIAN
  1354. tmp |= BUF_SWAP_32BIT;
  1355. #endif
  1356. WREG32(CP_RB_CNTL, tmp);
  1357. WREG32(CP_SEM_WAIT_TIMER, 0x0);
  1358. WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
  1359. /* Set the write pointer delay */
  1360. WREG32(CP_RB_WPTR_DELAY, 0);
  1361. /* Initialize the ring buffer's read and write pointers */
  1362. WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
  1363. WREG32(CP_RB_RPTR_WR, 0);
  1364. ring->wptr = 0;
  1365. WREG32(CP_RB_WPTR, ring->wptr);
  1366. /* set the wb address wether it's enabled or not */
  1367. WREG32(CP_RB_RPTR_ADDR,
  1368. ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC));
  1369. WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
  1370. WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
  1371. if (rdev->wb.enabled)
  1372. WREG32(SCRATCH_UMSK, 0xff);
  1373. else {
  1374. tmp |= RB_NO_UPDATE;
  1375. WREG32(SCRATCH_UMSK, 0);
  1376. }
  1377. mdelay(1);
  1378. WREG32(CP_RB_CNTL, tmp);
  1379. WREG32(CP_RB_BASE, ring->gpu_addr >> 8);
  1380. WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
  1381. ring->rptr = RREG32(CP_RB_RPTR);
  1382. evergreen_cp_start(rdev);
  1383. ring->ready = true;
  1384. r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
  1385. if (r) {
  1386. ring->ready = false;
  1387. return r;
  1388. }
  1389. return 0;
  1390. }
  1391. /*
  1392. * Core functions
  1393. */
  1394. static void evergreen_gpu_init(struct radeon_device *rdev)
  1395. {
  1396. u32 gb_addr_config;
  1397. u32 mc_shared_chmap, mc_arb_ramcfg;
  1398. u32 sx_debug_1;
  1399. u32 smx_dc_ctl0;
  1400. u32 sq_config;
  1401. u32 sq_lds_resource_mgmt;
  1402. u32 sq_gpr_resource_mgmt_1;
  1403. u32 sq_gpr_resource_mgmt_2;
  1404. u32 sq_gpr_resource_mgmt_3;
  1405. u32 sq_thread_resource_mgmt;
  1406. u32 sq_thread_resource_mgmt_2;
  1407. u32 sq_stack_resource_mgmt_1;
  1408. u32 sq_stack_resource_mgmt_2;
  1409. u32 sq_stack_resource_mgmt_3;
  1410. u32 vgt_cache_invalidation;
  1411. u32 hdp_host_path_cntl, tmp;
  1412. u32 disabled_rb_mask;
  1413. int i, j, num_shader_engines, ps_thread_count;
  1414. switch (rdev->family) {
  1415. case CHIP_CYPRESS:
  1416. case CHIP_HEMLOCK:
  1417. rdev->config.evergreen.num_ses = 2;
  1418. rdev->config.evergreen.max_pipes = 4;
  1419. rdev->config.evergreen.max_tile_pipes = 8;
  1420. rdev->config.evergreen.max_simds = 10;
  1421. rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
  1422. rdev->config.evergreen.max_gprs = 256;
  1423. rdev->config.evergreen.max_threads = 248;
  1424. rdev->config.evergreen.max_gs_threads = 32;
  1425. rdev->config.evergreen.max_stack_entries = 512;
  1426. rdev->config.evergreen.sx_num_of_sets = 4;
  1427. rdev->config.evergreen.sx_max_export_size = 256;
  1428. rdev->config.evergreen.sx_max_export_pos_size = 64;
  1429. rdev->config.evergreen.sx_max_export_smx_size = 192;
  1430. rdev->config.evergreen.max_hw_contexts = 8;
  1431. rdev->config.evergreen.sq_num_cf_insts = 2;
  1432. rdev->config.evergreen.sc_prim_fifo_size = 0x100;
  1433. rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
  1434. rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
  1435. gb_addr_config = CYPRESS_GB_ADDR_CONFIG_GOLDEN;
  1436. break;
  1437. case CHIP_JUNIPER:
  1438. rdev->config.evergreen.num_ses = 1;
  1439. rdev->config.evergreen.max_pipes = 4;
  1440. rdev->config.evergreen.max_tile_pipes = 4;
  1441. rdev->config.evergreen.max_simds = 10;
  1442. rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
  1443. rdev->config.evergreen.max_gprs = 256;
  1444. rdev->config.evergreen.max_threads = 248;
  1445. rdev->config.evergreen.max_gs_threads = 32;
  1446. rdev->config.evergreen.max_stack_entries = 512;
  1447. rdev->config.evergreen.sx_num_of_sets = 4;
  1448. rdev->config.evergreen.sx_max_export_size = 256;
  1449. rdev->config.evergreen.sx_max_export_pos_size = 64;
  1450. rdev->config.evergreen.sx_max_export_smx_size = 192;
  1451. rdev->config.evergreen.max_hw_contexts = 8;
  1452. rdev->config.evergreen.sq_num_cf_insts = 2;
  1453. rdev->config.evergreen.sc_prim_fifo_size = 0x100;
  1454. rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
  1455. rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
  1456. gb_addr_config = JUNIPER_GB_ADDR_CONFIG_GOLDEN;
  1457. break;
  1458. case CHIP_REDWOOD:
  1459. rdev->config.evergreen.num_ses = 1;
  1460. rdev->config.evergreen.max_pipes = 4;
  1461. rdev->config.evergreen.max_tile_pipes = 4;
  1462. rdev->config.evergreen.max_simds = 5;
  1463. rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
  1464. rdev->config.evergreen.max_gprs = 256;
  1465. rdev->config.evergreen.max_threads = 248;
  1466. rdev->config.evergreen.max_gs_threads = 32;
  1467. rdev->config.evergreen.max_stack_entries = 256;
  1468. rdev->config.evergreen.sx_num_of_sets = 4;
  1469. rdev->config.evergreen.sx_max_export_size = 256;
  1470. rdev->config.evergreen.sx_max_export_pos_size = 64;
  1471. rdev->config.evergreen.sx_max_export_smx_size = 192;
  1472. rdev->config.evergreen.max_hw_contexts = 8;
  1473. rdev->config.evergreen.sq_num_cf_insts = 2;
  1474. rdev->config.evergreen.sc_prim_fifo_size = 0x100;
  1475. rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
  1476. rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
  1477. gb_addr_config = REDWOOD_GB_ADDR_CONFIG_GOLDEN;
  1478. break;
  1479. case CHIP_CEDAR:
  1480. default:
  1481. rdev->config.evergreen.num_ses = 1;
  1482. rdev->config.evergreen.max_pipes = 2;
  1483. rdev->config.evergreen.max_tile_pipes = 2;
  1484. rdev->config.evergreen.max_simds = 2;
  1485. rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
  1486. rdev->config.evergreen.max_gprs = 256;
  1487. rdev->config.evergreen.max_threads = 192;
  1488. rdev->config.evergreen.max_gs_threads = 16;
  1489. rdev->config.evergreen.max_stack_entries = 256;
  1490. rdev->config.evergreen.sx_num_of_sets = 4;
  1491. rdev->config.evergreen.sx_max_export_size = 128;
  1492. rdev->config.evergreen.sx_max_export_pos_size = 32;
  1493. rdev->config.evergreen.sx_max_export_smx_size = 96;
  1494. rdev->config.evergreen.max_hw_contexts = 4;
  1495. rdev->config.evergreen.sq_num_cf_insts = 1;
  1496. rdev->config.evergreen.sc_prim_fifo_size = 0x40;
  1497. rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
  1498. rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
  1499. gb_addr_config = CEDAR_GB_ADDR_CONFIG_GOLDEN;
  1500. break;
  1501. case CHIP_PALM:
  1502. rdev->config.evergreen.num_ses = 1;
  1503. rdev->config.evergreen.max_pipes = 2;
  1504. rdev->config.evergreen.max_tile_pipes = 2;
  1505. rdev->config.evergreen.max_simds = 2;
  1506. rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
  1507. rdev->config.evergreen.max_gprs = 256;
  1508. rdev->config.evergreen.max_threads = 192;
  1509. rdev->config.evergreen.max_gs_threads = 16;
  1510. rdev->config.evergreen.max_stack_entries = 256;
  1511. rdev->config.evergreen.sx_num_of_sets = 4;
  1512. rdev->config.evergreen.sx_max_export_size = 128;
  1513. rdev->config.evergreen.sx_max_export_pos_size = 32;
  1514. rdev->config.evergreen.sx_max_export_smx_size = 96;
  1515. rdev->config.evergreen.max_hw_contexts = 4;
  1516. rdev->config.evergreen.sq_num_cf_insts = 1;
  1517. rdev->config.evergreen.sc_prim_fifo_size = 0x40;
  1518. rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
  1519. rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
  1520. gb_addr_config = CEDAR_GB_ADDR_CONFIG_GOLDEN;
  1521. break;
  1522. case CHIP_SUMO:
  1523. rdev->config.evergreen.num_ses = 1;
  1524. rdev->config.evergreen.max_pipes = 4;
  1525. rdev->config.evergreen.max_tile_pipes = 2;
  1526. if (rdev->pdev->device == 0x9648)
  1527. rdev->config.evergreen.max_simds = 3;
  1528. else if ((rdev->pdev->device == 0x9647) ||
  1529. (rdev->pdev->device == 0x964a))
  1530. rdev->config.evergreen.max_simds = 4;
  1531. else
  1532. rdev->config.evergreen.max_simds = 5;
  1533. rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
  1534. rdev->config.evergreen.max_gprs = 256;
  1535. rdev->config.evergreen.max_threads = 248;
  1536. rdev->config.evergreen.max_gs_threads = 32;
  1537. rdev->config.evergreen.max_stack_entries = 256;
  1538. rdev->config.evergreen.sx_num_of_sets = 4;
  1539. rdev->config.evergreen.sx_max_export_size = 256;
  1540. rdev->config.evergreen.sx_max_export_pos_size = 64;
  1541. rdev->config.evergreen.sx_max_export_smx_size = 192;
  1542. rdev->config.evergreen.max_hw_contexts = 8;
  1543. rdev->config.evergreen.sq_num_cf_insts = 2;
  1544. rdev->config.evergreen.sc_prim_fifo_size = 0x40;
  1545. rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
  1546. rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
  1547. gb_addr_config = REDWOOD_GB_ADDR_CONFIG_GOLDEN;
  1548. break;
  1549. case CHIP_SUMO2:
  1550. rdev->config.evergreen.num_ses = 1;
  1551. rdev->config.evergreen.max_pipes = 4;
  1552. rdev->config.evergreen.max_tile_pipes = 4;
  1553. rdev->config.evergreen.max_simds = 2;
  1554. rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
  1555. rdev->config.evergreen.max_gprs = 256;
  1556. rdev->config.evergreen.max_threads = 248;
  1557. rdev->config.evergreen.max_gs_threads = 32;
  1558. rdev->config.evergreen.max_stack_entries = 512;
  1559. rdev->config.evergreen.sx_num_of_sets = 4;
  1560. rdev->config.evergreen.sx_max_export_size = 256;
  1561. rdev->config.evergreen.sx_max_export_pos_size = 64;
  1562. rdev->config.evergreen.sx_max_export_smx_size = 192;
  1563. rdev->config.evergreen.max_hw_contexts = 8;
  1564. rdev->config.evergreen.sq_num_cf_insts = 2;
  1565. rdev->config.evergreen.sc_prim_fifo_size = 0x40;
  1566. rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
  1567. rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
  1568. gb_addr_config = REDWOOD_GB_ADDR_CONFIG_GOLDEN;
  1569. break;
  1570. case CHIP_BARTS:
  1571. rdev->config.evergreen.num_ses = 2;
  1572. rdev->config.evergreen.max_pipes = 4;
  1573. rdev->config.evergreen.max_tile_pipes = 8;
  1574. rdev->config.evergreen.max_simds = 7;
  1575. rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
  1576. rdev->config.evergreen.max_gprs = 256;
  1577. rdev->config.evergreen.max_threads = 248;
  1578. rdev->config.evergreen.max_gs_threads = 32;
  1579. rdev->config.evergreen.max_stack_entries = 512;
  1580. rdev->config.evergreen.sx_num_of_sets = 4;
  1581. rdev->config.evergreen.sx_max_export_size = 256;
  1582. rdev->config.evergreen.sx_max_export_pos_size = 64;
  1583. rdev->config.evergreen.sx_max_export_smx_size = 192;
  1584. rdev->config.evergreen.max_hw_contexts = 8;
  1585. rdev->config.evergreen.sq_num_cf_insts = 2;
  1586. rdev->config.evergreen.sc_prim_fifo_size = 0x100;
  1587. rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
  1588. rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
  1589. gb_addr_config = BARTS_GB_ADDR_CONFIG_GOLDEN;
  1590. break;
  1591. case CHIP_TURKS:
  1592. rdev->config.evergreen.num_ses = 1;
  1593. rdev->config.evergreen.max_pipes = 4;
  1594. rdev->config.evergreen.max_tile_pipes = 4;
  1595. rdev->config.evergreen.max_simds = 6;
  1596. rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
  1597. rdev->config.evergreen.max_gprs = 256;
  1598. rdev->config.evergreen.max_threads = 248;
  1599. rdev->config.evergreen.max_gs_threads = 32;
  1600. rdev->config.evergreen.max_stack_entries = 256;
  1601. rdev->config.evergreen.sx_num_of_sets = 4;
  1602. rdev->config.evergreen.sx_max_export_size = 256;
  1603. rdev->config.evergreen.sx_max_export_pos_size = 64;
  1604. rdev->config.evergreen.sx_max_export_smx_size = 192;
  1605. rdev->config.evergreen.max_hw_contexts = 8;
  1606. rdev->config.evergreen.sq_num_cf_insts = 2;
  1607. rdev->config.evergreen.sc_prim_fifo_size = 0x100;
  1608. rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
  1609. rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
  1610. gb_addr_config = TURKS_GB_ADDR_CONFIG_GOLDEN;
  1611. break;
  1612. case CHIP_CAICOS:
  1613. rdev->config.evergreen.num_ses = 1;
  1614. rdev->config.evergreen.max_pipes = 4;
  1615. rdev->config.evergreen.max_tile_pipes = 2;
  1616. rdev->config.evergreen.max_simds = 2;
  1617. rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
  1618. rdev->config.evergreen.max_gprs = 256;
  1619. rdev->config.evergreen.max_threads = 192;
  1620. rdev->config.evergreen.max_gs_threads = 16;
  1621. rdev->config.evergreen.max_stack_entries = 256;
  1622. rdev->config.evergreen.sx_num_of_sets = 4;
  1623. rdev->config.evergreen.sx_max_export_size = 128;
  1624. rdev->config.evergreen.sx_max_export_pos_size = 32;
  1625. rdev->config.evergreen.sx_max_export_smx_size = 96;
  1626. rdev->config.evergreen.max_hw_contexts = 4;
  1627. rdev->config.evergreen.sq_num_cf_insts = 1;
  1628. rdev->config.evergreen.sc_prim_fifo_size = 0x40;
  1629. rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
  1630. rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
  1631. gb_addr_config = CAICOS_GB_ADDR_CONFIG_GOLDEN;
  1632. break;
  1633. }
  1634. /* Initialize HDP */
  1635. for (i = 0, j = 0; i < 32; i++, j += 0x18) {
  1636. WREG32((0x2c14 + j), 0x00000000);
  1637. WREG32((0x2c18 + j), 0x00000000);
  1638. WREG32((0x2c1c + j), 0x00000000);
  1639. WREG32((0x2c20 + j), 0x00000000);
  1640. WREG32((0x2c24 + j), 0x00000000);
  1641. }
  1642. WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
  1643. evergreen_fix_pci_max_read_req_size(rdev);
  1644. mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
  1645. if ((rdev->family == CHIP_PALM) ||
  1646. (rdev->family == CHIP_SUMO) ||
  1647. (rdev->family == CHIP_SUMO2))
  1648. mc_arb_ramcfg = RREG32(FUS_MC_ARB_RAMCFG);
  1649. else
  1650. mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
  1651. /* setup tiling info dword. gb_addr_config is not adequate since it does
  1652. * not have bank info, so create a custom tiling dword.
  1653. * bits 3:0 num_pipes
  1654. * bits 7:4 num_banks
  1655. * bits 11:8 group_size
  1656. * bits 15:12 row_size
  1657. */
  1658. rdev->config.evergreen.tile_config = 0;
  1659. switch (rdev->config.evergreen.max_tile_pipes) {
  1660. case 1:
  1661. default:
  1662. rdev->config.evergreen.tile_config |= (0 << 0);
  1663. break;
  1664. case 2:
  1665. rdev->config.evergreen.tile_config |= (1 << 0);
  1666. break;
  1667. case 4:
  1668. rdev->config.evergreen.tile_config |= (2 << 0);
  1669. break;
  1670. case 8:
  1671. rdev->config.evergreen.tile_config |= (3 << 0);
  1672. break;
  1673. }
  1674. /* num banks is 8 on all fusion asics. 0 = 4, 1 = 8, 2 = 16 */
  1675. if (rdev->flags & RADEON_IS_IGP)
  1676. rdev->config.evergreen.tile_config |= 1 << 4;
  1677. else {
  1678. if ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT)
  1679. rdev->config.evergreen.tile_config |= 1 << 4;
  1680. else
  1681. rdev->config.evergreen.tile_config |= 0 << 4;
  1682. }
  1683. rdev->config.evergreen.tile_config |= 0 << 8;
  1684. rdev->config.evergreen.tile_config |=
  1685. ((gb_addr_config & 0x30000000) >> 28) << 12;
  1686. num_shader_engines = (gb_addr_config & NUM_SHADER_ENGINES(3) >> 12) + 1;
  1687. if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK)) {
  1688. u32 efuse_straps_4;
  1689. u32 efuse_straps_3;
  1690. WREG32(RCU_IND_INDEX, 0x204);
  1691. efuse_straps_4 = RREG32(RCU_IND_DATA);
  1692. WREG32(RCU_IND_INDEX, 0x203);
  1693. efuse_straps_3 = RREG32(RCU_IND_DATA);
  1694. tmp = (((efuse_straps_4 & 0xf) << 4) |
  1695. ((efuse_straps_3 & 0xf0000000) >> 28));
  1696. } else {
  1697. tmp = 0;
  1698. for (i = (rdev->config.evergreen.num_ses - 1); i >= 0; i--) {
  1699. u32 rb_disable_bitmap;
  1700. WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
  1701. WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
  1702. rb_disable_bitmap = (RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000) >> 16;
  1703. tmp <<= 4;
  1704. tmp |= rb_disable_bitmap;
  1705. }
  1706. }
  1707. /* enabled rb are just the one not disabled :) */
  1708. disabled_rb_mask = tmp;
  1709. WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
  1710. WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
  1711. WREG32(GB_ADDR_CONFIG, gb_addr_config);
  1712. WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
  1713. WREG32(HDP_ADDR_CONFIG, gb_addr_config);
  1714. tmp = gb_addr_config & NUM_PIPES_MASK;
  1715. tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.evergreen.max_backends,
  1716. EVERGREEN_MAX_BACKENDS, disabled_rb_mask);
  1717. WREG32(GB_BACKEND_MAP, tmp);
  1718. WREG32(CGTS_SYS_TCC_DISABLE, 0);
  1719. WREG32(CGTS_TCC_DISABLE, 0);
  1720. WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
  1721. WREG32(CGTS_USER_TCC_DISABLE, 0);
  1722. /* set HW defaults for 3D engine */
  1723. WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
  1724. ROQ_IB2_START(0x2b)));
  1725. WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
  1726. WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO |
  1727. SYNC_GRADIENT |
  1728. SYNC_WALKER |
  1729. SYNC_ALIGNER));
  1730. sx_debug_1 = RREG32(SX_DEBUG_1);
  1731. sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
  1732. WREG32(SX_DEBUG_1, sx_debug_1);
  1733. smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
  1734. smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff);
  1735. smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.evergreen.sx_num_of_sets);
  1736. WREG32(SMX_DC_CTL0, smx_dc_ctl0);
  1737. WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_size / 4) - 1) |
  1738. POSITION_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_pos_size / 4) - 1) |
  1739. SMX_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_smx_size / 4) - 1)));
  1740. WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.evergreen.sc_prim_fifo_size) |
  1741. SC_HIZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_hiz_tile_fifo_size) |
  1742. SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_earlyz_tile_fifo_size)));
  1743. WREG32(VGT_NUM_INSTANCES, 1);
  1744. WREG32(SPI_CONFIG_CNTL, 0);
  1745. WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
  1746. WREG32(CP_PERFMON_CNTL, 0);
  1747. WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.evergreen.sq_num_cf_insts) |
  1748. FETCH_FIFO_HIWATER(0x4) |
  1749. DONE_FIFO_HIWATER(0xe0) |
  1750. ALU_UPDATE_FIFO_HIWATER(0x8)));
  1751. sq_config = RREG32(SQ_CONFIG);
  1752. sq_config &= ~(PS_PRIO(3) |
  1753. VS_PRIO(3) |
  1754. GS_PRIO(3) |
  1755. ES_PRIO(3));
  1756. sq_config |= (VC_ENABLE |
  1757. EXPORT_SRC_C |
  1758. PS_PRIO(0) |
  1759. VS_PRIO(1) |
  1760. GS_PRIO(2) |
  1761. ES_PRIO(3));
  1762. switch (rdev->family) {
  1763. case CHIP_CEDAR:
  1764. case CHIP_PALM:
  1765. case CHIP_SUMO:
  1766. case CHIP_SUMO2:
  1767. case CHIP_CAICOS:
  1768. /* no vertex cache */
  1769. sq_config &= ~VC_ENABLE;
  1770. break;
  1771. default:
  1772. break;
  1773. }
  1774. sq_lds_resource_mgmt = RREG32(SQ_LDS_RESOURCE_MGMT);
  1775. sq_gpr_resource_mgmt_1 = NUM_PS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2))* 12 / 32);
  1776. sq_gpr_resource_mgmt_1 |= NUM_VS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 6 / 32);
  1777. sq_gpr_resource_mgmt_1 |= NUM_CLAUSE_TEMP_GPRS(4);
  1778. sq_gpr_resource_mgmt_2 = NUM_GS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
  1779. sq_gpr_resource_mgmt_2 |= NUM_ES_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
  1780. sq_gpr_resource_mgmt_3 = NUM_HS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
  1781. sq_gpr_resource_mgmt_3 |= NUM_LS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
  1782. switch (rdev->family) {
  1783. case CHIP_CEDAR:
  1784. case CHIP_PALM:
  1785. case CHIP_SUMO:
  1786. case CHIP_SUMO2:
  1787. ps_thread_count = 96;
  1788. break;
  1789. default:
  1790. ps_thread_count = 128;
  1791. break;
  1792. }
  1793. sq_thread_resource_mgmt = NUM_PS_THREADS(ps_thread_count);
  1794. sq_thread_resource_mgmt |= NUM_VS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
  1795. sq_thread_resource_mgmt |= NUM_GS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
  1796. sq_thread_resource_mgmt |= NUM_ES_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
  1797. sq_thread_resource_mgmt_2 = NUM_HS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
  1798. sq_thread_resource_mgmt_2 |= NUM_LS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
  1799. sq_stack_resource_mgmt_1 = NUM_PS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
  1800. sq_stack_resource_mgmt_1 |= NUM_VS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
  1801. sq_stack_resource_mgmt_2 = NUM_GS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
  1802. sq_stack_resource_mgmt_2 |= NUM_ES_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
  1803. sq_stack_resource_mgmt_3 = NUM_HS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
  1804. sq_stack_resource_mgmt_3 |= NUM_LS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
  1805. WREG32(SQ_CONFIG, sq_config);
  1806. WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
  1807. WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
  1808. WREG32(SQ_GPR_RESOURCE_MGMT_3, sq_gpr_resource_mgmt_3);
  1809. WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
  1810. WREG32(SQ_THREAD_RESOURCE_MGMT_2, sq_thread_resource_mgmt_2);
  1811. WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
  1812. WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
  1813. WREG32(SQ_STACK_RESOURCE_MGMT_3, sq_stack_resource_mgmt_3);
  1814. WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
  1815. WREG32(SQ_LDS_RESOURCE_MGMT, sq_lds_resource_mgmt);
  1816. WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
  1817. FORCE_EOV_MAX_REZ_CNT(255)));
  1818. switch (rdev->family) {
  1819. case CHIP_CEDAR:
  1820. case CHIP_PALM:
  1821. case CHIP_SUMO:
  1822. case CHIP_SUMO2:
  1823. case CHIP_CAICOS:
  1824. vgt_cache_invalidation = CACHE_INVALIDATION(TC_ONLY);
  1825. break;
  1826. default:
  1827. vgt_cache_invalidation = CACHE_INVALIDATION(VC_AND_TC);
  1828. break;
  1829. }
  1830. vgt_cache_invalidation |= AUTO_INVLD_EN(ES_AND_GS_AUTO);
  1831. WREG32(VGT_CACHE_INVALIDATION, vgt_cache_invalidation);
  1832. WREG32(VGT_GS_VERTEX_REUSE, 16);
  1833. WREG32(PA_SU_LINE_STIPPLE_VALUE, 0);
  1834. WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
  1835. WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
  1836. WREG32(VGT_OUT_DEALLOC_CNTL, 16);
  1837. WREG32(CB_PERF_CTR0_SEL_0, 0);
  1838. WREG32(CB_PERF_CTR0_SEL_1, 0);
  1839. WREG32(CB_PERF_CTR1_SEL_0, 0);
  1840. WREG32(CB_PERF_CTR1_SEL_1, 0);
  1841. WREG32(CB_PERF_CTR2_SEL_0, 0);
  1842. WREG32(CB_PERF_CTR2_SEL_1, 0);
  1843. WREG32(CB_PERF_CTR3_SEL_0, 0);
  1844. WREG32(CB_PERF_CTR3_SEL_1, 0);
  1845. /* clear render buffer base addresses */
  1846. WREG32(CB_COLOR0_BASE, 0);
  1847. WREG32(CB_COLOR1_BASE, 0);
  1848. WREG32(CB_COLOR2_BASE, 0);
  1849. WREG32(CB_COLOR3_BASE, 0);
  1850. WREG32(CB_COLOR4_BASE, 0);
  1851. WREG32(CB_COLOR5_BASE, 0);
  1852. WREG32(CB_COLOR6_BASE, 0);
  1853. WREG32(CB_COLOR7_BASE, 0);
  1854. WREG32(CB_COLOR8_BASE, 0);
  1855. WREG32(CB_COLOR9_BASE, 0);
  1856. WREG32(CB_COLOR10_BASE, 0);
  1857. WREG32(CB_COLOR11_BASE, 0);
  1858. /* set the shader const cache sizes to 0 */
  1859. for (i = SQ_ALU_CONST_BUFFER_SIZE_PS_0; i < 0x28200; i += 4)
  1860. WREG32(i, 0);
  1861. for (i = SQ_ALU_CONST_BUFFER_SIZE_HS_0; i < 0x29000; i += 4)
  1862. WREG32(i, 0);
  1863. tmp = RREG32(HDP_MISC_CNTL);
  1864. tmp |= HDP_FLUSH_INVALIDATE_CACHE;
  1865. WREG32(HDP_MISC_CNTL, tmp);
  1866. hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
  1867. WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
  1868. WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
  1869. udelay(50);
  1870. }
  1871. int evergreen_mc_init(struct radeon_device *rdev)
  1872. {
  1873. u32 tmp;
  1874. int chansize, numchan;
  1875. /* Get VRAM informations */
  1876. rdev->mc.vram_is_ddr = true;
  1877. if ((rdev->family == CHIP_PALM) ||
  1878. (rdev->family == CHIP_SUMO) ||
  1879. (rdev->family == CHIP_SUMO2))
  1880. tmp = RREG32(FUS_MC_ARB_RAMCFG);
  1881. else
  1882. tmp = RREG32(MC_ARB_RAMCFG);
  1883. if (tmp & CHANSIZE_OVERRIDE) {
  1884. chansize = 16;
  1885. } else if (tmp & CHANSIZE_MASK) {
  1886. chansize = 64;
  1887. } else {
  1888. chansize = 32;
  1889. }
  1890. tmp = RREG32(MC_SHARED_CHMAP);
  1891. switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
  1892. case 0:
  1893. default:
  1894. numchan = 1;
  1895. break;
  1896. case 1:
  1897. numchan = 2;
  1898. break;
  1899. case 2:
  1900. numchan = 4;
  1901. break;
  1902. case 3:
  1903. numchan = 8;
  1904. break;
  1905. }
  1906. rdev->mc.vram_width = numchan * chansize;
  1907. /* Could aper size report 0 ? */
  1908. rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
  1909. rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
  1910. /* Setup GPU memory space */
  1911. if ((rdev->family == CHIP_PALM) ||
  1912. (rdev->family == CHIP_SUMO) ||
  1913. (rdev->family == CHIP_SUMO2)) {
  1914. /* size in bytes on fusion */
  1915. rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
  1916. rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
  1917. } else {
  1918. /* size in MB on evergreen/cayman/tn */
  1919. rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
  1920. rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
  1921. }
  1922. rdev->mc.visible_vram_size = rdev->mc.aper_size;
  1923. r700_vram_gtt_location(rdev, &rdev->mc);
  1924. radeon_update_bandwidth_info(rdev);
  1925. return 0;
  1926. }
  1927. bool evergreen_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
  1928. {
  1929. u32 srbm_status;
  1930. u32 grbm_status;
  1931. u32 grbm_status_se0, grbm_status_se1;
  1932. srbm_status = RREG32(SRBM_STATUS);
  1933. grbm_status = RREG32(GRBM_STATUS);
  1934. grbm_status_se0 = RREG32(GRBM_STATUS_SE0);
  1935. grbm_status_se1 = RREG32(GRBM_STATUS_SE1);
  1936. if (!(grbm_status & GUI_ACTIVE)) {
  1937. radeon_ring_lockup_update(ring);
  1938. return false;
  1939. }
  1940. /* force CP activities */
  1941. radeon_ring_force_activity(rdev, ring);
  1942. return radeon_ring_test_lockup(rdev, ring);
  1943. }
  1944. static int evergreen_gpu_soft_reset(struct radeon_device *rdev)
  1945. {
  1946. struct evergreen_mc_save save;
  1947. u32 grbm_reset = 0;
  1948. if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
  1949. return 0;
  1950. dev_info(rdev->dev, "GPU softreset \n");
  1951. dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
  1952. RREG32(GRBM_STATUS));
  1953. dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
  1954. RREG32(GRBM_STATUS_SE0));
  1955. dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
  1956. RREG32(GRBM_STATUS_SE1));
  1957. dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
  1958. RREG32(SRBM_STATUS));
  1959. evergreen_mc_stop(rdev, &save);
  1960. if (evergreen_mc_wait_for_idle(rdev)) {
  1961. dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
  1962. }
  1963. /* Disable CP parsing/prefetching */
  1964. WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
  1965. /* reset all the gfx blocks */
  1966. grbm_reset = (SOFT_RESET_CP |
  1967. SOFT_RESET_CB |
  1968. SOFT_RESET_DB |
  1969. SOFT_RESET_PA |
  1970. SOFT_RESET_SC |
  1971. SOFT_RESET_SPI |
  1972. SOFT_RESET_SH |
  1973. SOFT_RESET_SX |
  1974. SOFT_RESET_TC |
  1975. SOFT_RESET_TA |
  1976. SOFT_RESET_VC |
  1977. SOFT_RESET_VGT);
  1978. dev_info(rdev->dev, " GRBM_SOFT_RESET=0x%08X\n", grbm_reset);
  1979. WREG32(GRBM_SOFT_RESET, grbm_reset);
  1980. (void)RREG32(GRBM_SOFT_RESET);
  1981. udelay(50);
  1982. WREG32(GRBM_SOFT_RESET, 0);
  1983. (void)RREG32(GRBM_SOFT_RESET);
  1984. /* Wait a little for things to settle down */
  1985. udelay(50);
  1986. dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
  1987. RREG32(GRBM_STATUS));
  1988. dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
  1989. RREG32(GRBM_STATUS_SE0));
  1990. dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
  1991. RREG32(GRBM_STATUS_SE1));
  1992. dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
  1993. RREG32(SRBM_STATUS));
  1994. evergreen_mc_resume(rdev, &save);
  1995. return 0;
  1996. }
  1997. int evergreen_asic_reset(struct radeon_device *rdev)
  1998. {
  1999. return evergreen_gpu_soft_reset(rdev);
  2000. }
  2001. /* Interrupts */
  2002. u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc)
  2003. {
  2004. switch (crtc) {
  2005. case 0:
  2006. return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC0_REGISTER_OFFSET);
  2007. case 1:
  2008. return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC1_REGISTER_OFFSET);
  2009. case 2:
  2010. return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC2_REGISTER_OFFSET);
  2011. case 3:
  2012. return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC3_REGISTER_OFFSET);
  2013. case 4:
  2014. return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC4_REGISTER_OFFSET);
  2015. case 5:
  2016. return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC5_REGISTER_OFFSET);
  2017. default:
  2018. return 0;
  2019. }
  2020. }
  2021. void evergreen_disable_interrupt_state(struct radeon_device *rdev)
  2022. {
  2023. u32 tmp;
  2024. if (rdev->family >= CHIP_CAYMAN) {
  2025. cayman_cp_int_cntl_setup(rdev, 0,
  2026. CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
  2027. cayman_cp_int_cntl_setup(rdev, 1, 0);
  2028. cayman_cp_int_cntl_setup(rdev, 2, 0);
  2029. } else
  2030. WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
  2031. WREG32(GRBM_INT_CNTL, 0);
  2032. WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
  2033. WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
  2034. if (rdev->num_crtc >= 4) {
  2035. WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
  2036. WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
  2037. }
  2038. if (rdev->num_crtc >= 6) {
  2039. WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
  2040. WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
  2041. }
  2042. WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
  2043. WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
  2044. if (rdev->num_crtc >= 4) {
  2045. WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
  2046. WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
  2047. }
  2048. if (rdev->num_crtc >= 6) {
  2049. WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
  2050. WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
  2051. }
  2052. /* only one DAC on DCE6 */
  2053. if (!ASIC_IS_DCE6(rdev))
  2054. WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
  2055. WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
  2056. tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
  2057. WREG32(DC_HPD1_INT_CONTROL, tmp);
  2058. tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
  2059. WREG32(DC_HPD2_INT_CONTROL, tmp);
  2060. tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
  2061. WREG32(DC_HPD3_INT_CONTROL, tmp);
  2062. tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
  2063. WREG32(DC_HPD4_INT_CONTROL, tmp);
  2064. tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
  2065. WREG32(DC_HPD5_INT_CONTROL, tmp);
  2066. tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
  2067. WREG32(DC_HPD6_INT_CONTROL, tmp);
  2068. }
  2069. int evergreen_irq_set(struct radeon_device *rdev)
  2070. {
  2071. u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
  2072. u32 cp_int_cntl1 = 0, cp_int_cntl2 = 0;
  2073. u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0;
  2074. u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6;
  2075. u32 grbm_int_cntl = 0;
  2076. u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0;
  2077. u32 afmt1 = 0, afmt2 = 0, afmt3 = 0, afmt4 = 0, afmt5 = 0, afmt6 = 0;
  2078. if (!rdev->irq.installed) {
  2079. WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
  2080. return -EINVAL;
  2081. }
  2082. /* don't enable anything if the ih is disabled */
  2083. if (!rdev->ih.enabled) {
  2084. r600_disable_interrupts(rdev);
  2085. /* force the active interrupt state to all disabled */
  2086. evergreen_disable_interrupt_state(rdev);
  2087. return 0;
  2088. }
  2089. hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
  2090. hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
  2091. hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
  2092. hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
  2093. hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
  2094. hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
  2095. afmt1 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
  2096. afmt2 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
  2097. afmt3 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
  2098. afmt4 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
  2099. afmt5 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
  2100. afmt6 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
  2101. if (rdev->family >= CHIP_CAYMAN) {
  2102. /* enable CP interrupts on all rings */
  2103. if (rdev->irq.sw_int[RADEON_RING_TYPE_GFX_INDEX]) {
  2104. DRM_DEBUG("evergreen_irq_set: sw int gfx\n");
  2105. cp_int_cntl |= TIME_STAMP_INT_ENABLE;
  2106. }
  2107. if (rdev->irq.sw_int[CAYMAN_RING_TYPE_CP1_INDEX]) {
  2108. DRM_DEBUG("evergreen_irq_set: sw int cp1\n");
  2109. cp_int_cntl1 |= TIME_STAMP_INT_ENABLE;
  2110. }
  2111. if (rdev->irq.sw_int[CAYMAN_RING_TYPE_CP2_INDEX]) {
  2112. DRM_DEBUG("evergreen_irq_set: sw int cp2\n");
  2113. cp_int_cntl2 |= TIME_STAMP_INT_ENABLE;
  2114. }
  2115. } else {
  2116. if (rdev->irq.sw_int[RADEON_RING_TYPE_GFX_INDEX]) {
  2117. DRM_DEBUG("evergreen_irq_set: sw int gfx\n");
  2118. cp_int_cntl |= RB_INT_ENABLE;
  2119. cp_int_cntl |= TIME_STAMP_INT_ENABLE;
  2120. }
  2121. }
  2122. if (rdev->irq.crtc_vblank_int[0] ||
  2123. rdev->irq.pflip[0]) {
  2124. DRM_DEBUG("evergreen_irq_set: vblank 0\n");
  2125. crtc1 |= VBLANK_INT_MASK;
  2126. }
  2127. if (rdev->irq.crtc_vblank_int[1] ||
  2128. rdev->irq.pflip[1]) {
  2129. DRM_DEBUG("evergreen_irq_set: vblank 1\n");
  2130. crtc2 |= VBLANK_INT_MASK;
  2131. }
  2132. if (rdev->irq.crtc_vblank_int[2] ||
  2133. rdev->irq.pflip[2]) {
  2134. DRM_DEBUG("evergreen_irq_set: vblank 2\n");
  2135. crtc3 |= VBLANK_INT_MASK;
  2136. }
  2137. if (rdev->irq.crtc_vblank_int[3] ||
  2138. rdev->irq.pflip[3]) {
  2139. DRM_DEBUG("evergreen_irq_set: vblank 3\n");
  2140. crtc4 |= VBLANK_INT_MASK;
  2141. }
  2142. if (rdev->irq.crtc_vblank_int[4] ||
  2143. rdev->irq.pflip[4]) {
  2144. DRM_DEBUG("evergreen_irq_set: vblank 4\n");
  2145. crtc5 |= VBLANK_INT_MASK;
  2146. }
  2147. if (rdev->irq.crtc_vblank_int[5] ||
  2148. rdev->irq.pflip[5]) {
  2149. DRM_DEBUG("evergreen_irq_set: vblank 5\n");
  2150. crtc6 |= VBLANK_INT_MASK;
  2151. }
  2152. if (rdev->irq.hpd[0]) {
  2153. DRM_DEBUG("evergreen_irq_set: hpd 1\n");
  2154. hpd1 |= DC_HPDx_INT_EN;
  2155. }
  2156. if (rdev->irq.hpd[1]) {
  2157. DRM_DEBUG("evergreen_irq_set: hpd 2\n");
  2158. hpd2 |= DC_HPDx_INT_EN;
  2159. }
  2160. if (rdev->irq.hpd[2]) {
  2161. DRM_DEBUG("evergreen_irq_set: hpd 3\n");
  2162. hpd3 |= DC_HPDx_INT_EN;
  2163. }
  2164. if (rdev->irq.hpd[3]) {
  2165. DRM_DEBUG("evergreen_irq_set: hpd 4\n");
  2166. hpd4 |= DC_HPDx_INT_EN;
  2167. }
  2168. if (rdev->irq.hpd[4]) {
  2169. DRM_DEBUG("evergreen_irq_set: hpd 5\n");
  2170. hpd5 |= DC_HPDx_INT_EN;
  2171. }
  2172. if (rdev->irq.hpd[5]) {
  2173. DRM_DEBUG("evergreen_irq_set: hpd 6\n");
  2174. hpd6 |= DC_HPDx_INT_EN;
  2175. }
  2176. if (rdev->irq.afmt[0]) {
  2177. DRM_DEBUG("evergreen_irq_set: hdmi 0\n");
  2178. afmt1 |= AFMT_AZ_FORMAT_WTRIG_MASK;
  2179. }
  2180. if (rdev->irq.afmt[1]) {
  2181. DRM_DEBUG("evergreen_irq_set: hdmi 1\n");
  2182. afmt2 |= AFMT_AZ_FORMAT_WTRIG_MASK;
  2183. }
  2184. if (rdev->irq.afmt[2]) {
  2185. DRM_DEBUG("evergreen_irq_set: hdmi 2\n");
  2186. afmt3 |= AFMT_AZ_FORMAT_WTRIG_MASK;
  2187. }
  2188. if (rdev->irq.afmt[3]) {
  2189. DRM_DEBUG("evergreen_irq_set: hdmi 3\n");
  2190. afmt4 |= AFMT_AZ_FORMAT_WTRIG_MASK;
  2191. }
  2192. if (rdev->irq.afmt[4]) {
  2193. DRM_DEBUG("evergreen_irq_set: hdmi 4\n");
  2194. afmt5 |= AFMT_AZ_FORMAT_WTRIG_MASK;
  2195. }
  2196. if (rdev->irq.afmt[5]) {
  2197. DRM_DEBUG("evergreen_irq_set: hdmi 5\n");
  2198. afmt6 |= AFMT_AZ_FORMAT_WTRIG_MASK;
  2199. }
  2200. if (rdev->irq.gui_idle) {
  2201. DRM_DEBUG("gui idle\n");
  2202. grbm_int_cntl |= GUI_IDLE_INT_ENABLE;
  2203. }
  2204. if (rdev->family >= CHIP_CAYMAN) {
  2205. cayman_cp_int_cntl_setup(rdev, 0, cp_int_cntl);
  2206. cayman_cp_int_cntl_setup(rdev, 1, cp_int_cntl1);
  2207. cayman_cp_int_cntl_setup(rdev, 2, cp_int_cntl2);
  2208. } else
  2209. WREG32(CP_INT_CNTL, cp_int_cntl);
  2210. WREG32(GRBM_INT_CNTL, grbm_int_cntl);
  2211. WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);
  2212. WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2);
  2213. if (rdev->num_crtc >= 4) {
  2214. WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3);
  2215. WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4);
  2216. }
  2217. if (rdev->num_crtc >= 6) {
  2218. WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5);
  2219. WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);
  2220. }
  2221. WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1);
  2222. WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2);
  2223. if (rdev->num_crtc >= 4) {
  2224. WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3);
  2225. WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4);
  2226. }
  2227. if (rdev->num_crtc >= 6) {
  2228. WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, grph5);
  2229. WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6);
  2230. }
  2231. WREG32(DC_HPD1_INT_CONTROL, hpd1);
  2232. WREG32(DC_HPD2_INT_CONTROL, hpd2);
  2233. WREG32(DC_HPD3_INT_CONTROL, hpd3);
  2234. WREG32(DC_HPD4_INT_CONTROL, hpd4);
  2235. WREG32(DC_HPD5_INT_CONTROL, hpd5);
  2236. WREG32(DC_HPD6_INT_CONTROL, hpd6);
  2237. WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, afmt1);
  2238. WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, afmt2);
  2239. WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, afmt3);
  2240. WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, afmt4);
  2241. WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, afmt5);
  2242. WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, afmt6);
  2243. return 0;
  2244. }
  2245. static void evergreen_irq_ack(struct radeon_device *rdev)
  2246. {
  2247. u32 tmp;
  2248. rdev->irq.stat_regs.evergreen.disp_int = RREG32(DISP_INTERRUPT_STATUS);
  2249. rdev->irq.stat_regs.evergreen.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
  2250. rdev->irq.stat_regs.evergreen.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2);
  2251. rdev->irq.stat_regs.evergreen.disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3);
  2252. rdev->irq.stat_regs.evergreen.disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4);
  2253. rdev->irq.stat_regs.evergreen.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5);
  2254. rdev->irq.stat_regs.evergreen.d1grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET);
  2255. rdev->irq.stat_regs.evergreen.d2grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET);
  2256. if (rdev->num_crtc >= 4) {
  2257. rdev->irq.stat_regs.evergreen.d3grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET);
  2258. rdev->irq.stat_regs.evergreen.d4grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET);
  2259. }
  2260. if (rdev->num_crtc >= 6) {
  2261. rdev->irq.stat_regs.evergreen.d5grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET);
  2262. rdev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
  2263. }
  2264. rdev->irq.stat_regs.evergreen.afmt_status1 = RREG32(AFMT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET);
  2265. rdev->irq.stat_regs.evergreen.afmt_status2 = RREG32(AFMT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET);
  2266. rdev->irq.stat_regs.evergreen.afmt_status3 = RREG32(AFMT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET);
  2267. rdev->irq.stat_regs.evergreen.afmt_status4 = RREG32(AFMT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET);
  2268. rdev->irq.stat_regs.evergreen.afmt_status5 = RREG32(AFMT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET);
  2269. rdev->irq.stat_regs.evergreen.afmt_status6 = RREG32(AFMT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
  2270. if (rdev->irq.stat_regs.evergreen.d1grph_int & GRPH_PFLIP_INT_OCCURRED)
  2271. WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
  2272. if (rdev->irq.stat_regs.evergreen.d2grph_int & GRPH_PFLIP_INT_OCCURRED)
  2273. WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
  2274. if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT)
  2275. WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK);
  2276. if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT)
  2277. WREG32(VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK);
  2278. if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT)
  2279. WREG32(VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK);
  2280. if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT)
  2281. WREG32(VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK);
  2282. if (rdev->num_crtc >= 4) {
  2283. if (rdev->irq.stat_regs.evergreen.d3grph_int & GRPH_PFLIP_INT_OCCURRED)
  2284. WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
  2285. if (rdev->irq.stat_regs.evergreen.d4grph_int & GRPH_PFLIP_INT_OCCURRED)
  2286. WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
  2287. if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)
  2288. WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK);
  2289. if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT)
  2290. WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK);
  2291. if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT)
  2292. WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK);
  2293. if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT)
  2294. WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK);
  2295. }
  2296. if (rdev->num_crtc >= 6) {
  2297. if (rdev->irq.stat_regs.evergreen.d5grph_int & GRPH_PFLIP_INT_OCCURRED)
  2298. WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
  2299. if (rdev->irq.stat_regs.evergreen.d6grph_int & GRPH_PFLIP_INT_OCCURRED)
  2300. WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
  2301. if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)
  2302. WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK);
  2303. if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT)
  2304. WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK);
  2305. if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT)
  2306. WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK);
  2307. if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT)
  2308. WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK);
  2309. }
  2310. if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
  2311. tmp = RREG32(DC_HPD1_INT_CONTROL);
  2312. tmp |= DC_HPDx_INT_ACK;
  2313. WREG32(DC_HPD1_INT_CONTROL, tmp);
  2314. }
  2315. if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
  2316. tmp = RREG32(DC_HPD2_INT_CONTROL);
  2317. tmp |= DC_HPDx_INT_ACK;
  2318. WREG32(DC_HPD2_INT_CONTROL, tmp);
  2319. }
  2320. if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
  2321. tmp = RREG32(DC_HPD3_INT_CONTROL);
  2322. tmp |= DC_HPDx_INT_ACK;
  2323. WREG32(DC_HPD3_INT_CONTROL, tmp);
  2324. }
  2325. if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
  2326. tmp = RREG32(DC_HPD4_INT_CONTROL);
  2327. tmp |= DC_HPDx_INT_ACK;
  2328. WREG32(DC_HPD4_INT_CONTROL, tmp);
  2329. }
  2330. if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
  2331. tmp = RREG32(DC_HPD5_INT_CONTROL);
  2332. tmp |= DC_HPDx_INT_ACK;
  2333. WREG32(DC_HPD5_INT_CONTROL, tmp);
  2334. }
  2335. if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
  2336. tmp = RREG32(DC_HPD5_INT_CONTROL);
  2337. tmp |= DC_HPDx_INT_ACK;
  2338. WREG32(DC_HPD6_INT_CONTROL, tmp);
  2339. }
  2340. if (rdev->irq.stat_regs.evergreen.afmt_status1 & AFMT_AZ_FORMAT_WTRIG) {
  2341. tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET);
  2342. tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
  2343. WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, tmp);
  2344. }
  2345. if (rdev->irq.stat_regs.evergreen.afmt_status2 & AFMT_AZ_FORMAT_WTRIG) {
  2346. tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
  2347. tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
  2348. WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, tmp);
  2349. }
  2350. if (rdev->irq.stat_regs.evergreen.afmt_status3 & AFMT_AZ_FORMAT_WTRIG) {
  2351. tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET);
  2352. tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
  2353. WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, tmp);
  2354. }
  2355. if (rdev->irq.stat_regs.evergreen.afmt_status4 & AFMT_AZ_FORMAT_WTRIG) {
  2356. tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
  2357. tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
  2358. WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, tmp);
  2359. }
  2360. if (rdev->irq.stat_regs.evergreen.afmt_status5 & AFMT_AZ_FORMAT_WTRIG) {
  2361. tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET);
  2362. tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
  2363. WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, tmp);
  2364. }
  2365. if (rdev->irq.stat_regs.evergreen.afmt_status6 & AFMT_AZ_FORMAT_WTRIG) {
  2366. tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
  2367. tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
  2368. WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, tmp);
  2369. }
  2370. }
  2371. void evergreen_irq_disable(struct radeon_device *rdev)
  2372. {
  2373. r600_disable_interrupts(rdev);
  2374. /* Wait and acknowledge irq */
  2375. mdelay(1);
  2376. evergreen_irq_ack(rdev);
  2377. evergreen_disable_interrupt_state(rdev);
  2378. }
  2379. void evergreen_irq_suspend(struct radeon_device *rdev)
  2380. {
  2381. evergreen_irq_disable(rdev);
  2382. r600_rlc_stop(rdev);
  2383. }
  2384. static u32 evergreen_get_ih_wptr(struct radeon_device *rdev)
  2385. {
  2386. u32 wptr, tmp;
  2387. if (rdev->wb.enabled)
  2388. wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
  2389. else
  2390. wptr = RREG32(IH_RB_WPTR);
  2391. if (wptr & RB_OVERFLOW) {
  2392. /* When a ring buffer overflow happen start parsing interrupt
  2393. * from the last not overwritten vector (wptr + 16). Hopefully
  2394. * this should allow us to catchup.
  2395. */
  2396. dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
  2397. wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
  2398. rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
  2399. tmp = RREG32(IH_RB_CNTL);
  2400. tmp |= IH_WPTR_OVERFLOW_CLEAR;
  2401. WREG32(IH_RB_CNTL, tmp);
  2402. }
  2403. return (wptr & rdev->ih.ptr_mask);
  2404. }
  2405. int evergreen_irq_process(struct radeon_device *rdev)
  2406. {
  2407. u32 wptr;
  2408. u32 rptr;
  2409. u32 src_id, src_data;
  2410. u32 ring_index;
  2411. unsigned long flags;
  2412. bool queue_hotplug = false;
  2413. bool queue_hdmi = false;
  2414. if (!rdev->ih.enabled || rdev->shutdown)
  2415. return IRQ_NONE;
  2416. wptr = evergreen_get_ih_wptr(rdev);
  2417. rptr = rdev->ih.rptr;
  2418. DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
  2419. spin_lock_irqsave(&rdev->ih.lock, flags);
  2420. if (rptr == wptr) {
  2421. spin_unlock_irqrestore(&rdev->ih.lock, flags);
  2422. return IRQ_NONE;
  2423. }
  2424. restart_ih:
  2425. /* Order reading of wptr vs. reading of IH ring data */
  2426. rmb();
  2427. /* display interrupts */
  2428. evergreen_irq_ack(rdev);
  2429. rdev->ih.wptr = wptr;
  2430. while (rptr != wptr) {
  2431. /* wptr/rptr are in bytes! */
  2432. ring_index = rptr / 4;
  2433. src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
  2434. src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
  2435. switch (src_id) {
  2436. case 1: /* D1 vblank/vline */
  2437. switch (src_data) {
  2438. case 0: /* D1 vblank */
  2439. if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT) {
  2440. if (rdev->irq.crtc_vblank_int[0]) {
  2441. drm_handle_vblank(rdev->ddev, 0);
  2442. rdev->pm.vblank_sync = true;
  2443. wake_up(&rdev->irq.vblank_queue);
  2444. }
  2445. if (rdev->irq.pflip[0])
  2446. radeon_crtc_handle_flip(rdev, 0);
  2447. rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
  2448. DRM_DEBUG("IH: D1 vblank\n");
  2449. }
  2450. break;
  2451. case 1: /* D1 vline */
  2452. if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT) {
  2453. rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VLINE_INTERRUPT;
  2454. DRM_DEBUG("IH: D1 vline\n");
  2455. }
  2456. break;
  2457. default:
  2458. DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
  2459. break;
  2460. }
  2461. break;
  2462. case 2: /* D2 vblank/vline */
  2463. switch (src_data) {
  2464. case 0: /* D2 vblank */
  2465. if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT) {
  2466. if (rdev->irq.crtc_vblank_int[1]) {
  2467. drm_handle_vblank(rdev->ddev, 1);
  2468. rdev->pm.vblank_sync = true;
  2469. wake_up(&rdev->irq.vblank_queue);
  2470. }
  2471. if (rdev->irq.pflip[1])
  2472. radeon_crtc_handle_flip(rdev, 1);
  2473. rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT;
  2474. DRM_DEBUG("IH: D2 vblank\n");
  2475. }
  2476. break;
  2477. case 1: /* D2 vline */
  2478. if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT) {
  2479. rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT;
  2480. DRM_DEBUG("IH: D2 vline\n");
  2481. }
  2482. break;
  2483. default:
  2484. DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
  2485. break;
  2486. }
  2487. break;
  2488. case 3: /* D3 vblank/vline */
  2489. switch (src_data) {
  2490. case 0: /* D3 vblank */
  2491. if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) {
  2492. if (rdev->irq.crtc_vblank_int[2]) {
  2493. drm_handle_vblank(rdev->ddev, 2);
  2494. rdev->pm.vblank_sync = true;
  2495. wake_up(&rdev->irq.vblank_queue);
  2496. }
  2497. if (rdev->irq.pflip[2])
  2498. radeon_crtc_handle_flip(rdev, 2);
  2499. rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT;
  2500. DRM_DEBUG("IH: D3 vblank\n");
  2501. }
  2502. break;
  2503. case 1: /* D3 vline */
  2504. if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) {
  2505. rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT;
  2506. DRM_DEBUG("IH: D3 vline\n");
  2507. }
  2508. break;
  2509. default:
  2510. DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
  2511. break;
  2512. }
  2513. break;
  2514. case 4: /* D4 vblank/vline */
  2515. switch (src_data) {
  2516. case 0: /* D4 vblank */
  2517. if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) {
  2518. if (rdev->irq.crtc_vblank_int[3]) {
  2519. drm_handle_vblank(rdev->ddev, 3);
  2520. rdev->pm.vblank_sync = true;
  2521. wake_up(&rdev->irq.vblank_queue);
  2522. }
  2523. if (rdev->irq.pflip[3])
  2524. radeon_crtc_handle_flip(rdev, 3);
  2525. rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT;
  2526. DRM_DEBUG("IH: D4 vblank\n");
  2527. }
  2528. break;
  2529. case 1: /* D4 vline */
  2530. if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) {
  2531. rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT;
  2532. DRM_DEBUG("IH: D4 vline\n");
  2533. }
  2534. break;
  2535. default:
  2536. DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
  2537. break;
  2538. }
  2539. break;
  2540. case 5: /* D5 vblank/vline */
  2541. switch (src_data) {
  2542. case 0: /* D5 vblank */
  2543. if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) {
  2544. if (rdev->irq.crtc_vblank_int[4]) {
  2545. drm_handle_vblank(rdev->ddev, 4);
  2546. rdev->pm.vblank_sync = true;
  2547. wake_up(&rdev->irq.vblank_queue);
  2548. }
  2549. if (rdev->irq.pflip[4])
  2550. radeon_crtc_handle_flip(rdev, 4);
  2551. rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT;
  2552. DRM_DEBUG("IH: D5 vblank\n");
  2553. }
  2554. break;
  2555. case 1: /* D5 vline */
  2556. if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) {
  2557. rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT;
  2558. DRM_DEBUG("IH: D5 vline\n");
  2559. }
  2560. break;
  2561. default:
  2562. DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
  2563. break;
  2564. }
  2565. break;
  2566. case 6: /* D6 vblank/vline */
  2567. switch (src_data) {
  2568. case 0: /* D6 vblank */
  2569. if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) {
  2570. if (rdev->irq.crtc_vblank_int[5]) {
  2571. drm_handle_vblank(rdev->ddev, 5);
  2572. rdev->pm.vblank_sync = true;
  2573. wake_up(&rdev->irq.vblank_queue);
  2574. }
  2575. if (rdev->irq.pflip[5])
  2576. radeon_crtc_handle_flip(rdev, 5);
  2577. rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT;
  2578. DRM_DEBUG("IH: D6 vblank\n");
  2579. }
  2580. break;
  2581. case 1: /* D6 vline */
  2582. if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) {
  2583. rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT;
  2584. DRM_DEBUG("IH: D6 vline\n");
  2585. }
  2586. break;
  2587. default:
  2588. DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
  2589. break;
  2590. }
  2591. break;
  2592. case 42: /* HPD hotplug */
  2593. switch (src_data) {
  2594. case 0:
  2595. if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
  2596. rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_INTERRUPT;
  2597. queue_hotplug = true;
  2598. DRM_DEBUG("IH: HPD1\n");
  2599. }
  2600. break;
  2601. case 1:
  2602. if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
  2603. rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_INTERRUPT;
  2604. queue_hotplug = true;
  2605. DRM_DEBUG("IH: HPD2\n");
  2606. }
  2607. break;
  2608. case 2:
  2609. if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
  2610. rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_INTERRUPT;
  2611. queue_hotplug = true;
  2612. DRM_DEBUG("IH: HPD3\n");
  2613. }
  2614. break;
  2615. case 3:
  2616. if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
  2617. rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_INTERRUPT;
  2618. queue_hotplug = true;
  2619. DRM_DEBUG("IH: HPD4\n");
  2620. }
  2621. break;
  2622. case 4:
  2623. if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
  2624. rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_INTERRUPT;
  2625. queue_hotplug = true;
  2626. DRM_DEBUG("IH: HPD5\n");
  2627. }
  2628. break;
  2629. case 5:
  2630. if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
  2631. rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_INTERRUPT;
  2632. queue_hotplug = true;
  2633. DRM_DEBUG("IH: HPD6\n");
  2634. }
  2635. break;
  2636. default:
  2637. DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
  2638. break;
  2639. }
  2640. break;
  2641. case 44: /* hdmi */
  2642. switch (src_data) {
  2643. case 0:
  2644. if (rdev->irq.stat_regs.evergreen.afmt_status1 & AFMT_AZ_FORMAT_WTRIG) {
  2645. rdev->irq.stat_regs.evergreen.afmt_status1 &= ~AFMT_AZ_FORMAT_WTRIG;
  2646. queue_hdmi = true;
  2647. DRM_DEBUG("IH: HDMI0\n");
  2648. }
  2649. break;
  2650. case 1:
  2651. if (rdev->irq.stat_regs.evergreen.afmt_status2 & AFMT_AZ_FORMAT_WTRIG) {
  2652. rdev->irq.stat_regs.evergreen.afmt_status2 &= ~AFMT_AZ_FORMAT_WTRIG;
  2653. queue_hdmi = true;
  2654. DRM_DEBUG("IH: HDMI1\n");
  2655. }
  2656. break;
  2657. case 2:
  2658. if (rdev->irq.stat_regs.evergreen.afmt_status3 & AFMT_AZ_FORMAT_WTRIG) {
  2659. rdev->irq.stat_regs.evergreen.afmt_status3 &= ~AFMT_AZ_FORMAT_WTRIG;
  2660. queue_hdmi = true;
  2661. DRM_DEBUG("IH: HDMI2\n");
  2662. }
  2663. break;
  2664. case 3:
  2665. if (rdev->irq.stat_regs.evergreen.afmt_status4 & AFMT_AZ_FORMAT_WTRIG) {
  2666. rdev->irq.stat_regs.evergreen.afmt_status4 &= ~AFMT_AZ_FORMAT_WTRIG;
  2667. queue_hdmi = true;
  2668. DRM_DEBUG("IH: HDMI3\n");
  2669. }
  2670. break;
  2671. case 4:
  2672. if (rdev->irq.stat_regs.evergreen.afmt_status5 & AFMT_AZ_FORMAT_WTRIG) {
  2673. rdev->irq.stat_regs.evergreen.afmt_status5 &= ~AFMT_AZ_FORMAT_WTRIG;
  2674. queue_hdmi = true;
  2675. DRM_DEBUG("IH: HDMI4\n");
  2676. }
  2677. break;
  2678. case 5:
  2679. if (rdev->irq.stat_regs.evergreen.afmt_status6 & AFMT_AZ_FORMAT_WTRIG) {
  2680. rdev->irq.stat_regs.evergreen.afmt_status6 &= ~AFMT_AZ_FORMAT_WTRIG;
  2681. queue_hdmi = true;
  2682. DRM_DEBUG("IH: HDMI5\n");
  2683. }
  2684. break;
  2685. default:
  2686. DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data);
  2687. break;
  2688. }
  2689. break;
  2690. case 176: /* CP_INT in ring buffer */
  2691. case 177: /* CP_INT in IB1 */
  2692. case 178: /* CP_INT in IB2 */
  2693. DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
  2694. radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
  2695. break;
  2696. case 181: /* CP EOP event */
  2697. DRM_DEBUG("IH: CP EOP\n");
  2698. if (rdev->family >= CHIP_CAYMAN) {
  2699. switch (src_data) {
  2700. case 0:
  2701. radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
  2702. break;
  2703. case 1:
  2704. radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
  2705. break;
  2706. case 2:
  2707. radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
  2708. break;
  2709. }
  2710. } else
  2711. radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
  2712. break;
  2713. case 233: /* GUI IDLE */
  2714. DRM_DEBUG("IH: GUI idle\n");
  2715. rdev->pm.gui_idle = true;
  2716. wake_up(&rdev->irq.idle_queue);
  2717. break;
  2718. default:
  2719. DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
  2720. break;
  2721. }
  2722. /* wptr/rptr are in bytes! */
  2723. rptr += 16;
  2724. rptr &= rdev->ih.ptr_mask;
  2725. }
  2726. /* make sure wptr hasn't changed while processing */
  2727. wptr = evergreen_get_ih_wptr(rdev);
  2728. if (wptr != rdev->ih.wptr)
  2729. goto restart_ih;
  2730. if (queue_hotplug)
  2731. schedule_work(&rdev->hotplug_work);
  2732. if (queue_hdmi)
  2733. schedule_work(&rdev->audio_work);
  2734. rdev->ih.rptr = rptr;
  2735. WREG32(IH_RB_RPTR, rdev->ih.rptr);
  2736. spin_unlock_irqrestore(&rdev->ih.lock, flags);
  2737. return IRQ_HANDLED;
  2738. }
  2739. static int evergreen_startup(struct radeon_device *rdev)
  2740. {
  2741. struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
  2742. int r;
  2743. /* enable pcie gen2 link */
  2744. evergreen_pcie_gen2_enable(rdev);
  2745. if (ASIC_IS_DCE5(rdev)) {
  2746. if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) {
  2747. r = ni_init_microcode(rdev);
  2748. if (r) {
  2749. DRM_ERROR("Failed to load firmware!\n");
  2750. return r;
  2751. }
  2752. }
  2753. r = ni_mc_load_microcode(rdev);
  2754. if (r) {
  2755. DRM_ERROR("Failed to load MC firmware!\n");
  2756. return r;
  2757. }
  2758. } else {
  2759. if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
  2760. r = r600_init_microcode(rdev);
  2761. if (r) {
  2762. DRM_ERROR("Failed to load firmware!\n");
  2763. return r;
  2764. }
  2765. }
  2766. }
  2767. r = r600_vram_scratch_init(rdev);
  2768. if (r)
  2769. return r;
  2770. evergreen_mc_program(rdev);
  2771. if (rdev->flags & RADEON_IS_AGP) {
  2772. evergreen_agp_enable(rdev);
  2773. } else {
  2774. r = evergreen_pcie_gart_enable(rdev);
  2775. if (r)
  2776. return r;
  2777. }
  2778. evergreen_gpu_init(rdev);
  2779. r = evergreen_blit_init(rdev);
  2780. if (r) {
  2781. r600_blit_fini(rdev);
  2782. rdev->asic->copy.copy = NULL;
  2783. dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
  2784. }
  2785. /* allocate wb buffer */
  2786. r = radeon_wb_init(rdev);
  2787. if (r)
  2788. return r;
  2789. r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
  2790. if (r) {
  2791. dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
  2792. return r;
  2793. }
  2794. /* Enable IRQ */
  2795. r = r600_irq_init(rdev);
  2796. if (r) {
  2797. DRM_ERROR("radeon: IH init failed (%d).\n", r);
  2798. radeon_irq_kms_fini(rdev);
  2799. return r;
  2800. }
  2801. evergreen_irq_set(rdev);
  2802. r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
  2803. R600_CP_RB_RPTR, R600_CP_RB_WPTR,
  2804. 0, 0xfffff, RADEON_CP_PACKET2);
  2805. if (r)
  2806. return r;
  2807. r = evergreen_cp_load_microcode(rdev);
  2808. if (r)
  2809. return r;
  2810. r = evergreen_cp_resume(rdev);
  2811. if (r)
  2812. return r;
  2813. r = radeon_ib_pool_start(rdev);
  2814. if (r)
  2815. return r;
  2816. r = radeon_ib_ring_tests(rdev);
  2817. if (r)
  2818. return r;
  2819. r = r600_audio_init(rdev);
  2820. if (r) {
  2821. DRM_ERROR("radeon: audio init failed\n");
  2822. return r;
  2823. }
  2824. return 0;
  2825. }
  2826. int evergreen_resume(struct radeon_device *rdev)
  2827. {
  2828. int r;
  2829. /* reset the asic, the gfx blocks are often in a bad state
  2830. * after the driver is unloaded or after a resume
  2831. */
  2832. if (radeon_asic_reset(rdev))
  2833. dev_warn(rdev->dev, "GPU reset failed !\n");
  2834. /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
  2835. * posting will perform necessary task to bring back GPU into good
  2836. * shape.
  2837. */
  2838. /* post card */
  2839. atom_asic_init(rdev->mode_info.atom_context);
  2840. rdev->accel_working = true;
  2841. r = evergreen_startup(rdev);
  2842. if (r) {
  2843. DRM_ERROR("evergreen startup failed on resume\n");
  2844. rdev->accel_working = false;
  2845. return r;
  2846. }
  2847. return r;
  2848. }
  2849. int evergreen_suspend(struct radeon_device *rdev)
  2850. {
  2851. struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
  2852. r600_audio_fini(rdev);
  2853. /* FIXME: we should wait for ring to be empty */
  2854. radeon_ib_pool_suspend(rdev);
  2855. r600_blit_suspend(rdev);
  2856. r700_cp_stop(rdev);
  2857. ring->ready = false;
  2858. evergreen_irq_suspend(rdev);
  2859. radeon_wb_disable(rdev);
  2860. evergreen_pcie_gart_disable(rdev);
  2861. return 0;
  2862. }
  2863. /* Plan is to move initialization in that function and use
  2864. * helper function so that radeon_device_init pretty much
  2865. * do nothing more than calling asic specific function. This
  2866. * should also allow to remove a bunch of callback function
  2867. * like vram_info.
  2868. */
  2869. int evergreen_init(struct radeon_device *rdev)
  2870. {
  2871. int r;
  2872. /* Read BIOS */
  2873. if (!radeon_get_bios(rdev)) {
  2874. if (ASIC_IS_AVIVO(rdev))
  2875. return -EINVAL;
  2876. }
  2877. /* Must be an ATOMBIOS */
  2878. if (!rdev->is_atom_bios) {
  2879. dev_err(rdev->dev, "Expecting atombios for evergreen GPU\n");
  2880. return -EINVAL;
  2881. }
  2882. r = radeon_atombios_init(rdev);
  2883. if (r)
  2884. return r;
  2885. /* reset the asic, the gfx blocks are often in a bad state
  2886. * after the driver is unloaded or after a resume
  2887. */
  2888. if (radeon_asic_reset(rdev))
  2889. dev_warn(rdev->dev, "GPU reset failed !\n");
  2890. /* Post card if necessary */
  2891. if (!radeon_card_posted(rdev)) {
  2892. if (!rdev->bios) {
  2893. dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
  2894. return -EINVAL;
  2895. }
  2896. DRM_INFO("GPU not posted. posting now...\n");
  2897. atom_asic_init(rdev->mode_info.atom_context);
  2898. }
  2899. /* Initialize scratch registers */
  2900. r600_scratch_init(rdev);
  2901. /* Initialize surface registers */
  2902. radeon_surface_init(rdev);
  2903. /* Initialize clocks */
  2904. radeon_get_clock_info(rdev->ddev);
  2905. /* Fence driver */
  2906. r = radeon_fence_driver_init(rdev);
  2907. if (r)
  2908. return r;
  2909. /* initialize AGP */
  2910. if (rdev->flags & RADEON_IS_AGP) {
  2911. r = radeon_agp_init(rdev);
  2912. if (r)
  2913. radeon_agp_disable(rdev);
  2914. }
  2915. /* initialize memory controller */
  2916. r = evergreen_mc_init(rdev);
  2917. if (r)
  2918. return r;
  2919. /* Memory manager */
  2920. r = radeon_bo_init(rdev);
  2921. if (r)
  2922. return r;
  2923. r = radeon_irq_kms_init(rdev);
  2924. if (r)
  2925. return r;
  2926. rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
  2927. r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
  2928. rdev->ih.ring_obj = NULL;
  2929. r600_ih_ring_init(rdev, 64 * 1024);
  2930. r = r600_pcie_gart_init(rdev);
  2931. if (r)
  2932. return r;
  2933. r = radeon_ib_pool_init(rdev);
  2934. rdev->accel_working = true;
  2935. if (r) {
  2936. dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
  2937. rdev->accel_working = false;
  2938. }
  2939. r = evergreen_startup(rdev);
  2940. if (r) {
  2941. dev_err(rdev->dev, "disabling GPU acceleration\n");
  2942. r700_cp_fini(rdev);
  2943. r600_irq_fini(rdev);
  2944. radeon_wb_fini(rdev);
  2945. r100_ib_fini(rdev);
  2946. radeon_irq_kms_fini(rdev);
  2947. evergreen_pcie_gart_fini(rdev);
  2948. rdev->accel_working = false;
  2949. }
  2950. /* Don't start up if the MC ucode is missing on BTC parts.
  2951. * The default clocks and voltages before the MC ucode
  2952. * is loaded are not suffient for advanced operations.
  2953. */
  2954. if (ASIC_IS_DCE5(rdev)) {
  2955. if (!rdev->mc_fw && !(rdev->flags & RADEON_IS_IGP)) {
  2956. DRM_ERROR("radeon: MC ucode required for NI+.\n");
  2957. return -EINVAL;
  2958. }
  2959. }
  2960. return 0;
  2961. }
  2962. void evergreen_fini(struct radeon_device *rdev)
  2963. {
  2964. r600_audio_fini(rdev);
  2965. r600_blit_fini(rdev);
  2966. r700_cp_fini(rdev);
  2967. r600_irq_fini(rdev);
  2968. radeon_wb_fini(rdev);
  2969. r100_ib_fini(rdev);
  2970. radeon_irq_kms_fini(rdev);
  2971. evergreen_pcie_gart_fini(rdev);
  2972. r600_vram_scratch_fini(rdev);
  2973. radeon_gem_fini(rdev);
  2974. radeon_fence_driver_fini(rdev);
  2975. radeon_agp_fini(rdev);
  2976. radeon_bo_fini(rdev);
  2977. radeon_atombios_fini(rdev);
  2978. kfree(rdev->bios);
  2979. rdev->bios = NULL;
  2980. }
  2981. void evergreen_pcie_gen2_enable(struct radeon_device *rdev)
  2982. {
  2983. u32 link_width_cntl, speed_cntl;
  2984. if (radeon_pcie_gen2 == 0)
  2985. return;
  2986. if (rdev->flags & RADEON_IS_IGP)
  2987. return;
  2988. if (!(rdev->flags & RADEON_IS_PCIE))
  2989. return;
  2990. /* x2 cards have a special sequence */
  2991. if (ASIC_IS_X2(rdev))
  2992. return;
  2993. speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
  2994. if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) ||
  2995. (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
  2996. link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
  2997. link_width_cntl &= ~LC_UPCONFIGURE_DIS;
  2998. WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
  2999. speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
  3000. speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
  3001. WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
  3002. speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
  3003. speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT;
  3004. WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
  3005. speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
  3006. speed_cntl &= ~LC_CLR_FAILED_SPD_CHANGE_CNT;
  3007. WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
  3008. speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
  3009. speed_cntl |= LC_GEN2_EN_STRAP;
  3010. WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
  3011. } else {
  3012. link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
  3013. /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
  3014. if (1)
  3015. link_width_cntl |= LC_UPCONFIGURE_DIS;
  3016. else
  3017. link_width_cntl &= ~LC_UPCONFIGURE_DIS;
  3018. WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
  3019. }
  3020. }